2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
9 * Authors: Matthew Garrett
14 #include <linux/delay.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_plane_helper.h>
20 #include "mgag200_drv.h"
22 #define MGAG200_LUT_SIZE 256
25 * This file contains setup code for the CRTC.
28 static void mga_crtc_load_lut(struct drm_crtc
*crtc
)
30 struct mga_crtc
*mga_crtc
= to_mga_crtc(crtc
);
31 struct drm_device
*dev
= crtc
->dev
;
32 struct mga_device
*mdev
= dev
->dev_private
;
33 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
39 WREG8(DAC_INDEX
+ MGA1064_INDEX
, 0);
41 if (fb
&& fb
->bits_per_pixel
== 16) {
42 int inc
= (fb
->depth
== 15) ? 8 : 4;
44 for (i
= 0; i
< MGAG200_LUT_SIZE
; i
+= inc
) {
45 if (fb
->depth
== 16) {
46 if (i
> (MGAG200_LUT_SIZE
>> 1)) {
49 r
= mga_crtc
->lut_r
[i
<< 1];
50 b
= mga_crtc
->lut_b
[i
<< 1];
53 r
= mga_crtc
->lut_r
[i
];
54 b
= mga_crtc
->lut_b
[i
];
57 WREG8(DAC_INDEX
+ MGA1064_COL_PAL
, r
);
58 WREG8(DAC_INDEX
+ MGA1064_COL_PAL
, mga_crtc
->lut_g
[i
]);
59 WREG8(DAC_INDEX
+ MGA1064_COL_PAL
, b
);
63 for (i
= 0; i
< MGAG200_LUT_SIZE
; i
++) {
65 WREG8(DAC_INDEX
+ MGA1064_COL_PAL
, mga_crtc
->lut_r
[i
]);
66 WREG8(DAC_INDEX
+ MGA1064_COL_PAL
, mga_crtc
->lut_g
[i
]);
67 WREG8(DAC_INDEX
+ MGA1064_COL_PAL
, mga_crtc
->lut_b
[i
]);
71 static inline void mga_wait_vsync(struct mga_device
*mdev
)
73 unsigned long timeout
= jiffies
+ HZ
/10;
74 unsigned int status
= 0;
77 status
= RREG32(MGAREG_Status
);
78 } while ((status
& 0x08) && time_before(jiffies
, timeout
));
79 timeout
= jiffies
+ HZ
/10;
82 status
= RREG32(MGAREG_Status
);
83 } while (!(status
& 0x08) && time_before(jiffies
, timeout
));
86 static inline void mga_wait_busy(struct mga_device
*mdev
)
88 unsigned long timeout
= jiffies
+ HZ
;
89 unsigned int status
= 0;
91 status
= RREG8(MGAREG_Status
+ 2);
92 } while ((status
& 0x01) && time_before(jiffies
, timeout
));
95 #define P_ARRAY_SIZE 9
97 static int mga_g200se_set_plls(struct mga_device
*mdev
, long clock
)
99 unsigned int vcomax
, vcomin
, pllreffreq
;
100 unsigned int delta
, tmpdelta
, permitteddelta
;
101 unsigned int testp
, testm
, testn
;
102 unsigned int p
, m
, n
;
103 unsigned int computed
;
104 unsigned int pvalues_e4
[P_ARRAY_SIZE
] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
108 if (mdev
->unique_rev_id
<= 0x03) {
116 permitteddelta
= clock
* 5 / 1000;
118 for (testp
= 8; testp
> 0; testp
/= 2) {
119 if (clock
* testp
> vcomax
)
121 if (clock
* testp
< vcomin
)
124 for (testn
= 17; testn
< 256; testn
++) {
125 for (testm
= 1; testm
< 32; testm
++) {
126 computed
= (pllreffreq
* testn
) /
128 if (computed
> clock
)
129 tmpdelta
= computed
- clock
;
131 tmpdelta
= clock
- computed
;
132 if (tmpdelta
< delta
) {
155 /* Permited delta is 0.5% as VESA Specification */
156 permitteddelta
= clock
* 5 / 1000;
158 for (i
= 0 ; i
< P_ARRAY_SIZE
; i
++) {
159 testp
= pvalues_e4
[i
];
161 if ((clock
* testp
) > vcomax
)
163 if ((clock
* testp
) < vcomin
)
166 for (testn
= 50; testn
<= 256; testn
++) {
167 for (testm
= 1; testm
<= 32; testm
++) {
168 computed
= (pllreffreq
* testn
) /
170 if (computed
> clock
)
171 tmpdelta
= computed
- clock
;
173 tmpdelta
= clock
- computed
;
175 if (tmpdelta
< delta
) {
185 fvv
= pllreffreq
* (n
+ 1) / (m
+ 1);
186 fvv
= (fvv
- 800000) / 50000;
197 if (delta
> permitteddelta
) {
198 printk(KERN_WARNING
"PLL delta too large\n");
202 WREG_DAC(MGA1064_PIX_PLLC_M
, m
);
203 WREG_DAC(MGA1064_PIX_PLLC_N
, n
);
204 WREG_DAC(MGA1064_PIX_PLLC_P
, p
);
206 if (mdev
->unique_rev_id
>= 0x04) {
207 WREG_DAC(0x1a, 0x09);
209 WREG_DAC(0x1a, 0x01);
216 static int mga_g200wb_set_plls(struct mga_device
*mdev
, long clock
)
218 unsigned int vcomax
, vcomin
, pllreffreq
;
219 unsigned int delta
, tmpdelta
;
220 unsigned int testp
, testm
, testn
, testp2
;
221 unsigned int p
, m
, n
;
222 unsigned int computed
;
223 int i
, j
, tmpcount
, vcount
;
224 bool pll_locked
= false;
231 if (mdev
->type
== G200_EW3
) {
237 for (testp
= 1; testp
< 8; testp
++) {
238 for (testp2
= 1; testp2
< 8; testp2
++) {
241 if ((clock
* testp
* testp2
) > vcomax
)
243 if ((clock
* testp
* testp2
) < vcomin
)
245 for (testm
= 1; testm
< 26; testm
++) {
246 for (testn
= 32; testn
< 2048 ; testn
++) {
247 computed
= (pllreffreq
* testn
) /
248 (testm
* testp
* testp2
);
249 if (computed
> clock
)
250 tmpdelta
= computed
- clock
;
252 tmpdelta
= clock
- computed
;
253 if (tmpdelta
< delta
) {
255 m
= ((testn
& 0x100) >> 1) |
258 p
= ((testn
& 0x600) >> 3) |
272 for (testp
= 1; testp
< 9; testp
++) {
273 if (clock
* testp
> vcomax
)
275 if (clock
* testp
< vcomin
)
278 for (testm
= 1; testm
< 17; testm
++) {
279 for (testn
= 1; testn
< 151; testn
++) {
280 computed
= (pllreffreq
* testn
) /
282 if (computed
> clock
)
283 tmpdelta
= computed
- clock
;
285 tmpdelta
= clock
- computed
;
286 if (tmpdelta
< delta
) {
298 for (i
= 0; i
<= 32 && pll_locked
== false; i
++) {
300 WREG8(MGAREG_CRTC_INDEX
, 0x1e);
301 tmp
= RREG8(MGAREG_CRTC_DATA
);
303 WREG8(MGAREG_CRTC_DATA
, tmp
+1);
306 /* set pixclkdis to 1 */
307 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
308 tmp
= RREG8(DAC_DATA
);
309 tmp
|= MGA1064_PIX_CLK_CTL_CLK_DIS
;
310 WREG8(DAC_DATA
, tmp
);
312 WREG8(DAC_INDEX
, MGA1064_REMHEADCTL
);
313 tmp
= RREG8(DAC_DATA
);
314 tmp
|= MGA1064_REMHEADCTL_CLKDIS
;
315 WREG8(DAC_DATA
, tmp
);
317 /* select PLL Set C */
318 tmp
= RREG8(MGAREG_MEM_MISC_READ
);
320 WREG8(MGAREG_MEM_MISC_WRITE
, tmp
);
322 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
323 tmp
= RREG8(DAC_DATA
);
324 tmp
|= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN
| 0x80;
325 WREG8(DAC_DATA
, tmp
);
330 WREG8(DAC_INDEX
, MGA1064_VREF_CTL
);
331 tmp
= RREG8(DAC_DATA
);
333 WREG8(DAC_DATA
, tmp
);
337 /* program pixel pll register */
338 WREG_DAC(MGA1064_WB_PIX_PLLC_N
, n
);
339 WREG_DAC(MGA1064_WB_PIX_PLLC_M
, m
);
340 WREG_DAC(MGA1064_WB_PIX_PLLC_P
, p
);
345 WREG8(DAC_INDEX
, MGA1064_VREF_CTL
);
346 tmp
= RREG8(DAC_DATA
);
348 WREG_DAC(MGA1064_VREF_CTL
, tmp
);
352 /* select the pixel pll */
353 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
354 tmp
= RREG8(DAC_DATA
);
355 tmp
&= ~MGA1064_PIX_CLK_CTL_SEL_MSK
;
356 tmp
|= MGA1064_PIX_CLK_CTL_SEL_PLL
;
357 WREG8(DAC_DATA
, tmp
);
359 WREG8(DAC_INDEX
, MGA1064_REMHEADCTL
);
360 tmp
= RREG8(DAC_DATA
);
361 tmp
&= ~MGA1064_REMHEADCTL_CLKSL_MSK
;
362 tmp
|= MGA1064_REMHEADCTL_CLKSL_PLL
;
363 WREG8(DAC_DATA
, tmp
);
365 /* reset dotclock rate bit */
366 WREG8(MGAREG_SEQ_INDEX
, 1);
367 tmp
= RREG8(MGAREG_SEQ_DATA
);
369 WREG8(MGAREG_SEQ_DATA
, tmp
);
371 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
372 tmp
= RREG8(DAC_DATA
);
373 tmp
&= ~MGA1064_PIX_CLK_CTL_CLK_DIS
;
374 WREG8(DAC_DATA
, tmp
);
376 vcount
= RREG8(MGAREG_VCOUNT
);
378 for (j
= 0; j
< 30 && pll_locked
== false; j
++) {
379 tmpcount
= RREG8(MGAREG_VCOUNT
);
380 if (tmpcount
< vcount
)
382 if ((tmpcount
- vcount
) > 2)
388 WREG8(DAC_INDEX
, MGA1064_REMHEADCTL
);
389 tmp
= RREG8(DAC_DATA
);
390 tmp
&= ~MGA1064_REMHEADCTL_CLKDIS
;
391 WREG_DAC(MGA1064_REMHEADCTL
, tmp
);
395 static int mga_g200ev_set_plls(struct mga_device
*mdev
, long clock
)
397 unsigned int vcomax
, vcomin
, pllreffreq
;
398 unsigned int delta
, tmpdelta
;
399 unsigned int testp
, testm
, testn
;
400 unsigned int p
, m
, n
;
401 unsigned int computed
;
411 for (testp
= 16; testp
> 0; testp
--) {
412 if (clock
* testp
> vcomax
)
414 if (clock
* testp
< vcomin
)
417 for (testn
= 1; testn
< 257; testn
++) {
418 for (testm
= 1; testm
< 17; testm
++) {
419 computed
= (pllreffreq
* testn
) /
421 if (computed
> clock
)
422 tmpdelta
= computed
- clock
;
424 tmpdelta
= clock
- computed
;
425 if (tmpdelta
< delta
) {
435 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
436 tmp
= RREG8(DAC_DATA
);
437 tmp
|= MGA1064_PIX_CLK_CTL_CLK_DIS
;
438 WREG8(DAC_DATA
, tmp
);
440 tmp
= RREG8(MGAREG_MEM_MISC_READ
);
442 WREG8(MGAREG_MEM_MISC_WRITE
, tmp
);
444 WREG8(DAC_INDEX
, MGA1064_PIX_PLL_STAT
);
445 tmp
= RREG8(DAC_DATA
);
446 WREG8(DAC_DATA
, tmp
& ~0x40);
448 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
449 tmp
= RREG8(DAC_DATA
);
450 tmp
|= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN
;
451 WREG8(DAC_DATA
, tmp
);
453 WREG_DAC(MGA1064_EV_PIX_PLLC_M
, m
);
454 WREG_DAC(MGA1064_EV_PIX_PLLC_N
, n
);
455 WREG_DAC(MGA1064_EV_PIX_PLLC_P
, p
);
459 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
460 tmp
= RREG8(DAC_DATA
);
461 tmp
&= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN
;
462 WREG8(DAC_DATA
, tmp
);
466 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
467 tmp
= RREG8(DAC_DATA
);
468 tmp
&= ~MGA1064_PIX_CLK_CTL_SEL_MSK
;
469 tmp
|= MGA1064_PIX_CLK_CTL_SEL_PLL
;
470 WREG8(DAC_DATA
, tmp
);
472 WREG8(DAC_INDEX
, MGA1064_PIX_PLL_STAT
);
473 tmp
= RREG8(DAC_DATA
);
474 WREG8(DAC_DATA
, tmp
| 0x40);
476 tmp
= RREG8(MGAREG_MEM_MISC_READ
);
478 WREG8(MGAREG_MEM_MISC_WRITE
, tmp
);
480 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
481 tmp
= RREG8(DAC_DATA
);
482 tmp
&= ~MGA1064_PIX_CLK_CTL_CLK_DIS
;
483 WREG8(DAC_DATA
, tmp
);
488 static int mga_g200eh_set_plls(struct mga_device
*mdev
, long clock
)
490 unsigned int vcomax
, vcomin
, pllreffreq
;
491 unsigned int delta
, tmpdelta
;
492 unsigned int testp
, testm
, testn
;
493 unsigned int p
, m
, n
;
494 unsigned int computed
;
495 int i
, j
, tmpcount
, vcount
;
497 bool pll_locked
= false;
501 if (mdev
->type
== G200_EH3
) {
510 for (testm
= 150; testm
>= 6; testm
--) {
511 if (clock
* testm
> vcomax
)
513 if (clock
* testm
< vcomin
)
515 for (testn
= 120; testn
>= 60; testn
--) {
516 computed
= (pllreffreq
* testn
) / testm
;
517 if (computed
> clock
)
518 tmpdelta
= computed
- clock
;
520 tmpdelta
= clock
- computed
;
521 if (tmpdelta
< delta
) {
541 for (testp
= 16; testp
> 0; testp
>>= 1) {
542 if (clock
* testp
> vcomax
)
544 if (clock
* testp
< vcomin
)
547 for (testm
= 1; testm
< 33; testm
++) {
548 for (testn
= 17; testn
< 257; testn
++) {
549 computed
= (pllreffreq
* testn
) /
551 if (computed
> clock
)
552 tmpdelta
= computed
- clock
;
554 tmpdelta
= clock
- computed
;
555 if (tmpdelta
< delta
) {
561 if ((clock
* testp
) >= 600000)
567 for (i
= 0; i
<= 32 && pll_locked
== false; i
++) {
568 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
569 tmp
= RREG8(DAC_DATA
);
570 tmp
|= MGA1064_PIX_CLK_CTL_CLK_DIS
;
571 WREG8(DAC_DATA
, tmp
);
573 tmp
= RREG8(MGAREG_MEM_MISC_READ
);
575 WREG8(MGAREG_MEM_MISC_WRITE
, tmp
);
577 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
578 tmp
= RREG8(DAC_DATA
);
579 tmp
|= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN
;
580 WREG8(DAC_DATA
, tmp
);
584 WREG_DAC(MGA1064_EH_PIX_PLLC_M
, m
);
585 WREG_DAC(MGA1064_EH_PIX_PLLC_N
, n
);
586 WREG_DAC(MGA1064_EH_PIX_PLLC_P
, p
);
590 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
591 tmp
= RREG8(DAC_DATA
);
592 tmp
&= ~MGA1064_PIX_CLK_CTL_SEL_MSK
;
593 tmp
|= MGA1064_PIX_CLK_CTL_SEL_PLL
;
594 WREG8(DAC_DATA
, tmp
);
596 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
597 tmp
= RREG8(DAC_DATA
);
598 tmp
&= ~MGA1064_PIX_CLK_CTL_CLK_DIS
;
599 tmp
&= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN
;
600 WREG8(DAC_DATA
, tmp
);
602 vcount
= RREG8(MGAREG_VCOUNT
);
604 for (j
= 0; j
< 30 && pll_locked
== false; j
++) {
605 tmpcount
= RREG8(MGAREG_VCOUNT
);
606 if (tmpcount
< vcount
)
608 if ((tmpcount
- vcount
) > 2)
618 static int mga_g200er_set_plls(struct mga_device
*mdev
, long clock
)
620 unsigned int vcomax
, vcomin
, pllreffreq
;
621 unsigned int delta
, tmpdelta
;
622 int testr
, testn
, testm
, testo
;
623 unsigned int p
, m
, n
;
624 unsigned int computed
, vco
;
626 const unsigned int m_div_val
[] = { 1, 2, 4, 8 };
635 for (testr
= 0; testr
< 4; testr
++) {
638 for (testn
= 5; testn
< 129; testn
++) {
641 for (testm
= 3; testm
>= 0; testm
--) {
644 for (testo
= 5; testo
< 33; testo
++) {
645 vco
= pllreffreq
* (testn
+ 1) /
651 computed
= vco
/ (m_div_val
[testm
] * (testo
+ 1));
652 if (computed
> clock
)
653 tmpdelta
= computed
- clock
;
655 tmpdelta
= clock
- computed
;
656 if (tmpdelta
< delta
) {
658 m
= testm
| (testo
<< 3);
660 p
= testr
| (testr
<< 3);
667 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
668 tmp
= RREG8(DAC_DATA
);
669 tmp
|= MGA1064_PIX_CLK_CTL_CLK_DIS
;
670 WREG8(DAC_DATA
, tmp
);
672 WREG8(DAC_INDEX
, MGA1064_REMHEADCTL
);
673 tmp
= RREG8(DAC_DATA
);
674 tmp
|= MGA1064_REMHEADCTL_CLKDIS
;
675 WREG8(DAC_DATA
, tmp
);
677 tmp
= RREG8(MGAREG_MEM_MISC_READ
);
678 tmp
|= (0x3<<2) | 0xc0;
679 WREG8(MGAREG_MEM_MISC_WRITE
, tmp
);
681 WREG8(DAC_INDEX
, MGA1064_PIX_CLK_CTL
);
682 tmp
= RREG8(DAC_DATA
);
683 tmp
&= ~MGA1064_PIX_CLK_CTL_CLK_DIS
;
684 tmp
|= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN
;
685 WREG8(DAC_DATA
, tmp
);
689 WREG_DAC(MGA1064_ER_PIX_PLLC_N
, n
);
690 WREG_DAC(MGA1064_ER_PIX_PLLC_M
, m
);
691 WREG_DAC(MGA1064_ER_PIX_PLLC_P
, p
);
698 static int mga_crtc_set_plls(struct mga_device
*mdev
, long clock
)
703 return mga_g200se_set_plls(mdev
, clock
);
707 return mga_g200wb_set_plls(mdev
, clock
);
710 return mga_g200ev_set_plls(mdev
, clock
);
714 return mga_g200eh_set_plls(mdev
, clock
);
717 return mga_g200er_set_plls(mdev
, clock
);
723 static void mga_g200wb_prepare(struct drm_crtc
*crtc
)
725 struct mga_device
*mdev
= crtc
->dev
->dev_private
;
729 /* 1- The first step is to warn the BMC of an upcoming mode change.
730 * We are putting the misc<0> to output.*/
732 WREG8(DAC_INDEX
, MGA1064_GEN_IO_CTL
);
733 tmp
= RREG8(DAC_DATA
);
735 WREG_DAC(MGA1064_GEN_IO_CTL
, tmp
);
737 /* we are putting a 1 on the misc<0> line */
738 WREG8(DAC_INDEX
, MGA1064_GEN_IO_DATA
);
739 tmp
= RREG8(DAC_DATA
);
741 WREG_DAC(MGA1064_GEN_IO_DATA
, tmp
);
743 /* 2- Second step to mask and further scan request
744 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
746 WREG8(DAC_INDEX
, MGA1064_SPAREREG
);
747 tmp
= RREG8(DAC_DATA
);
749 WREG_DAC(MGA1064_SPAREREG
, tmp
);
751 /* 3a- the third step is to verifu if there is an active scan
752 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
755 while (!(tmp
& 0x1) && iter_max
) {
756 WREG8(DAC_INDEX
, MGA1064_SPAREREG
);
757 tmp
= RREG8(DAC_DATA
);
762 /* 3b- this step occurs only if the remove is actually scanning
763 * we are waiting for the end of the frame which is a 1 on
764 * remvsyncsts (XSPAREREG<1>)
768 while ((tmp
& 0x2) && iter_max
) {
769 WREG8(DAC_INDEX
, MGA1064_SPAREREG
);
770 tmp
= RREG8(DAC_DATA
);
777 static void mga_g200wb_commit(struct drm_crtc
*crtc
)
780 struct mga_device
*mdev
= crtc
->dev
->dev_private
;
782 /* 1- The first step is to ensure that the vrsten and hrsten are set */
783 WREG8(MGAREG_CRTCEXT_INDEX
, 1);
784 tmp
= RREG8(MGAREG_CRTCEXT_DATA
);
785 WREG8(MGAREG_CRTCEXT_DATA
, tmp
| 0x88);
787 /* 2- second step is to assert the rstlvl2 */
788 WREG8(DAC_INDEX
, MGA1064_REMHEADCTL2
);
789 tmp
= RREG8(DAC_DATA
);
791 WREG8(DAC_DATA
, tmp
);
796 /* 3- deassert rstlvl2 */
798 WREG8(DAC_INDEX
, MGA1064_REMHEADCTL2
);
799 WREG8(DAC_DATA
, tmp
);
801 /* 4- remove mask of scan request */
802 WREG8(DAC_INDEX
, MGA1064_SPAREREG
);
803 tmp
= RREG8(DAC_DATA
);
805 WREG8(DAC_DATA
, tmp
);
807 /* 5- put back a 0 on the misc<0> line */
808 WREG8(DAC_INDEX
, MGA1064_GEN_IO_DATA
);
809 tmp
= RREG8(DAC_DATA
);
811 WREG_DAC(MGA1064_GEN_IO_DATA
, tmp
);
815 This is how the framebuffer base address is stored in g200 cards:
816 * Assume @offset is the gpu_addr variable of the framebuffer object
817 * Then addr is the number of _pixels_ (not bytes) from the start of
818 VRAM to the first pixel we want to display. (divided by 2 for 32bit
820 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
821 addr<20> -> CRTCEXT0<6>
822 addr<19-16> -> CRTCEXT0<3-0>
823 addr<15-8> -> CRTCC<7-0>
824 addr<7-0> -> CRTCD<7-0>
825 CRTCEXT0 has to be programmed last to trigger an update and make the
826 new addr variable take effect.
828 static void mga_set_start_address(struct drm_crtc
*crtc
, unsigned offset
)
830 struct mga_device
*mdev
= crtc
->dev
->dev_private
;
835 while (RREG8(0x1fda) & 0x08);
836 while (!(RREG8(0x1fda) & 0x08));
838 count
= RREG8(MGAREG_VCOUNT
) + 2;
839 while (RREG8(MGAREG_VCOUNT
) < count
);
841 WREG8(MGAREG_CRTCEXT_INDEX
, 0);
842 crtcext0
= RREG8(MGAREG_CRTCEXT_DATA
);
845 /* Can't store addresses any higher than that...
846 but we also don't have more than 16MB of memory, so it should be fine. */
847 WARN_ON(addr
> 0x1fffff);
848 crtcext0
|= (!!(addr
& (1<<20)))<<6;
849 WREG_CRT(0x0d, (u8
)(addr
& 0xff));
850 WREG_CRT(0x0c, (u8
)(addr
>> 8) & 0xff);
851 WREG_ECRT(0x0, ((u8
)(addr
>> 16) & 0xf) | crtcext0
);
855 /* ast is different - we will force move buffers out of VRAM */
856 static int mga_crtc_do_set_base(struct drm_crtc
*crtc
,
857 struct drm_framebuffer
*fb
,
858 int x
, int y
, int atomic
)
860 struct mga_device
*mdev
= crtc
->dev
->dev_private
;
861 struct drm_gem_object
*obj
;
862 struct mga_framebuffer
*mga_fb
;
863 struct mgag200_bo
*bo
;
867 /* push the previous fb to system ram */
869 mga_fb
= to_mga_framebuffer(fb
);
871 bo
= gem_to_mga_bo(obj
);
872 ret
= mgag200_bo_reserve(bo
, false);
875 mgag200_bo_push_sysram(bo
);
876 mgag200_bo_unreserve(bo
);
879 mga_fb
= to_mga_framebuffer(crtc
->primary
->fb
);
881 bo
= gem_to_mga_bo(obj
);
883 ret
= mgag200_bo_reserve(bo
, false);
887 ret
= mgag200_bo_pin(bo
, TTM_PL_FLAG_VRAM
, &gpu_addr
);
889 mgag200_bo_unreserve(bo
);
893 if (&mdev
->mfbdev
->mfb
== mga_fb
) {
894 /* if pushing console in kmap it */
895 ret
= ttm_bo_kmap(&bo
->bo
, 0, bo
->bo
.num_pages
, &bo
->kmap
);
897 DRM_ERROR("failed to kmap fbcon\n");
900 mgag200_bo_unreserve(bo
);
902 mga_set_start_address(crtc
, (u32
)gpu_addr
);
907 static int mga_crtc_mode_set_base(struct drm_crtc
*crtc
, int x
, int y
,
908 struct drm_framebuffer
*old_fb
)
910 return mga_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
913 static int mga_crtc_mode_set(struct drm_crtc
*crtc
,
914 struct drm_display_mode
*mode
,
915 struct drm_display_mode
*adjusted_mode
,
916 int x
, int y
, struct drm_framebuffer
*old_fb
)
918 struct drm_device
*dev
= crtc
->dev
;
919 struct mga_device
*mdev
= dev
->dev_private
;
920 int hdisplay
, hsyncstart
, hsyncend
, htotal
;
921 int vdisplay
, vsyncstart
, vsyncend
, vtotal
;
923 int option
= 0, option2
= 0;
925 unsigned char misc
= 0;
926 unsigned char ext_vga
[6];
929 static unsigned char dacvalue
[] = {
930 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
931 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
932 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
933 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
934 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
935 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
936 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
937 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
938 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
939 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
942 bppshift
= mdev
->bpp_shifts
[(crtc
->primary
->fb
->bits_per_pixel
>> 3) - 1];
944 switch (mdev
->type
) {
947 dacvalue
[MGA1064_VREF_CTL
] = 0x03;
948 dacvalue
[MGA1064_PIX_CLK_CTL
] = MGA1064_PIX_CLK_CTL_SEL_PLL
;
949 dacvalue
[MGA1064_MISC_CTL
] = MGA1064_MISC_CTL_DAC_EN
|
950 MGA1064_MISC_CTL_VGA8
|
951 MGA1064_MISC_CTL_DAC_RAM_CS
;
956 option2
= 0x00008000;
960 dacvalue
[MGA1064_VREF_CTL
] = 0x07;
962 option2
= 0x0000b000;
965 dacvalue
[MGA1064_PIX_CLK_CTL
] = MGA1064_PIX_CLK_CTL_SEL_PLL
;
966 dacvalue
[MGA1064_MISC_CTL
] = MGA1064_MISC_CTL_VGA8
|
967 MGA1064_MISC_CTL_DAC_RAM_CS
;
969 option2
= 0x0000b000;
973 dacvalue
[MGA1064_MISC_CTL
] = MGA1064_MISC_CTL_VGA8
|
974 MGA1064_MISC_CTL_DAC_RAM_CS
;
976 option2
= 0x0000b000;
982 switch (crtc
->primary
->fb
->bits_per_pixel
) {
984 dacvalue
[MGA1064_MUL_CTL
] = MGA1064_MUL_CTL_8bits
;
987 if (crtc
->primary
->fb
->depth
== 15)
988 dacvalue
[MGA1064_MUL_CTL
] = MGA1064_MUL_CTL_15bits
;
990 dacvalue
[MGA1064_MUL_CTL
] = MGA1064_MUL_CTL_16bits
;
993 dacvalue
[MGA1064_MUL_CTL
] = MGA1064_MUL_CTL_24bits
;
996 dacvalue
[MGA1064_MUL_CTL
] = MGA1064_MUL_CTL_32_24bits
;
1000 if (mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
1002 if (mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
1006 for (i
= 0; i
< sizeof(dacvalue
); i
++) {
1010 ((i
>= 0x1f) && (i
<= 0x29)) ||
1011 ((i
>= 0x30) && (i
<= 0x37)))
1013 if (IS_G200_SE(mdev
) &&
1014 ((i
== 0x2c) || (i
== 0x2d) || (i
== 0x2e)))
1016 if ((mdev
->type
== G200_EV
||
1017 mdev
->type
== G200_WB
||
1018 mdev
->type
== G200_EH
||
1019 mdev
->type
== G200_EW3
||
1020 mdev
->type
== G200_EH3
) &&
1021 (i
>= 0x44) && (i
<= 0x4e))
1024 WREG_DAC(i
, dacvalue
[i
]);
1027 if (mdev
->type
== G200_ER
)
1031 pci_write_config_dword(dev
->pdev
, PCI_MGA_OPTION
, option
);
1033 pci_write_config_dword(dev
->pdev
, PCI_MGA_OPTION2
, option2
);
1039 pitch
= crtc
->primary
->fb
->pitches
[0] / (crtc
->primary
->fb
->bits_per_pixel
/ 8);
1040 if (crtc
->primary
->fb
->bits_per_pixel
== 24)
1041 pitch
= (pitch
* 3) >> (4 - bppshift
);
1043 pitch
= pitch
>> (4 - bppshift
);
1045 hdisplay
= mode
->hdisplay
/ 8 - 1;
1046 hsyncstart
= mode
->hsync_start
/ 8 - 1;
1047 hsyncend
= mode
->hsync_end
/ 8 - 1;
1048 htotal
= mode
->htotal
/ 8 - 1;
1050 /* Work around hardware quirk */
1051 if ((htotal
& 0x07) == 0x06 || (htotal
& 0x07) == 0x04)
1054 vdisplay
= mode
->vdisplay
- 1;
1055 vsyncstart
= mode
->vsync_start
- 1;
1056 vsyncend
= mode
->vsync_end
- 1;
1057 vtotal
= mode
->vtotal
- 2;
1069 WREG_CRT(0, htotal
- 4);
1070 WREG_CRT(1, hdisplay
);
1071 WREG_CRT(2, hdisplay
);
1072 WREG_CRT(3, (htotal
& 0x1F) | 0x80);
1073 WREG_CRT(4, hsyncstart
);
1074 WREG_CRT(5, ((htotal
& 0x20) << 2) | (hsyncend
& 0x1F));
1075 WREG_CRT(6, vtotal
& 0xFF);
1076 WREG_CRT(7, ((vtotal
& 0x100) >> 8) |
1077 ((vdisplay
& 0x100) >> 7) |
1078 ((vsyncstart
& 0x100) >> 6) |
1079 ((vdisplay
& 0x100) >> 5) |
1080 ((vdisplay
& 0x100) >> 4) | /* linecomp */
1081 ((vtotal
& 0x200) >> 4)|
1082 ((vdisplay
& 0x200) >> 3) |
1083 ((vsyncstart
& 0x200) >> 2));
1084 WREG_CRT(9, ((vdisplay
& 0x200) >> 4) |
1085 ((vdisplay
& 0x200) >> 3));
1092 WREG_CRT(16, vsyncstart
& 0xFF);
1093 WREG_CRT(17, (vsyncend
& 0x0F) | 0x20);
1094 WREG_CRT(18, vdisplay
& 0xFF);
1095 WREG_CRT(19, pitch
& 0xFF);
1097 WREG_CRT(21, vdisplay
& 0xFF);
1098 WREG_CRT(22, (vtotal
+ 1) & 0xFF);
1100 WREG_CRT(24, vdisplay
& 0xFF);
1105 /* TODO interlace */
1107 ext_vga
[0] |= (pitch
& 0x300) >> 4;
1108 ext_vga
[1] = (((htotal
- 4) & 0x100) >> 8) |
1109 ((hdisplay
& 0x100) >> 7) |
1110 ((hsyncstart
& 0x100) >> 6) |
1112 ext_vga
[2] = ((vtotal
& 0xc00) >> 10) |
1113 ((vdisplay
& 0x400) >> 8) |
1114 ((vdisplay
& 0xc00) >> 7) |
1115 ((vsyncstart
& 0xc00) >> 5) |
1116 ((vdisplay
& 0x400) >> 3);
1117 if (crtc
->primary
->fb
->bits_per_pixel
== 24)
1118 ext_vga
[3] = (((1 << bppshift
) * 3) - 1) | 0x80;
1120 ext_vga
[3] = ((1 << bppshift
) - 1) | 0x80;
1122 if (mdev
->type
== G200_WB
|| mdev
->type
== G200_EW3
)
1125 /* Set pixel clocks */
1127 WREG8(MGA_MISC_OUT
, misc
);
1129 mga_crtc_set_plls(mdev
, mode
->clock
);
1131 for (i
= 0; i
< 6; i
++) {
1132 WREG_ECRT(i
, ext_vga
[i
]);
1135 if (mdev
->type
== G200_ER
)
1136 WREG_ECRT(0x24, 0x5);
1138 if (mdev
->type
== G200_EW3
)
1139 WREG_ECRT(0x34, 0x5);
1141 if (mdev
->type
== G200_EV
) {
1145 WREG_ECRT(0, ext_vga
[0]);
1146 /* Enable mga pixel clock */
1149 WREG8(MGA_MISC_OUT
, misc
);
1152 memcpy(&mdev
->mode
, mode
, sizeof(struct drm_display_mode
));
1154 mga_crtc_do_set_base(crtc
, old_fb
, x
, y
, 0);
1157 if (mdev
->type
== G200_ER
) {
1158 u32 mem_ctl
= RREG32(MGAREG_MEMCTL
);
1162 WREG8(MGAREG_SEQ_INDEX
, 0x01);
1163 seq1
= RREG8(MGAREG_SEQ_DATA
) | 0x20;
1164 WREG8(MGAREG_SEQ_DATA
, seq1
);
1166 WREG32(MGAREG_MEMCTL
, mem_ctl
| 0x00200000);
1168 WREG32(MGAREG_MEMCTL
, mem_ctl
& ~0x00200000);
1170 WREG8(MGAREG_SEQ_DATA
, seq1
& ~0x20);
1174 if (IS_G200_SE(mdev
)) {
1175 if (mdev
->unique_rev_id
>= 0x02) {
1180 if (crtc
->primary
->fb
->bits_per_pixel
> 16)
1182 else if (crtc
->primary
->fb
->bits_per_pixel
> 8)
1187 mb
= (mode
->clock
* bpp
) / 1000;
1201 WREG8(MGAREG_CRTCEXT_INDEX
, 0x06);
1202 WREG8(MGAREG_CRTCEXT_DATA
, hi_pri_lvl
);
1204 WREG8(MGAREG_CRTCEXT_INDEX
, 0x06);
1205 if (mdev
->unique_rev_id
>= 0x01)
1206 WREG8(MGAREG_CRTCEXT_DATA
, 0x03);
1208 WREG8(MGAREG_CRTCEXT_DATA
, 0x04);
1214 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1215 static int mga_suspend(struct drm_crtc
*crtc
)
1217 struct mga_crtc
*mga_crtc
= to_mga_crtc(crtc
);
1218 struct drm_device
*dev
= crtc
->dev
;
1219 struct mga_device
*mdev
= dev
->dev_private
;
1220 struct pci_dev
*pdev
= dev
->pdev
;
1223 if (mdev
->suspended
)
1228 /* Disable the pixel clock */
1229 WREG_DAC(0x1a, 0x05);
1230 /* Power down the DAC */
1231 WREG_DAC(0x1e, 0x18);
1232 /* Power down the pixel PLL */
1233 WREG_DAC(0x1a, 0x0d);
1235 /* Disable PLLs and clocks */
1236 pci_read_config_dword(pdev
, PCI_MGA_OPTION
, &option
);
1237 option
&= ~(0x1F8024);
1238 pci_write_config_dword(pdev
, PCI_MGA_OPTION
, option
);
1239 pci_set_power_state(pdev
, PCI_D3hot
);
1240 pci_disable_device(pdev
);
1242 mdev
->suspended
= true;
1247 static int mga_resume(struct drm_crtc
*crtc
)
1249 struct mga_crtc
*mga_crtc
= to_mga_crtc(crtc
);
1250 struct drm_device
*dev
= crtc
->dev
;
1251 struct mga_device
*mdev
= dev
->dev_private
;
1252 struct pci_dev
*pdev
= dev
->pdev
;
1255 if (!mdev
->suspended
)
1258 pci_set_power_state(pdev
, PCI_D0
);
1259 pci_enable_device(pdev
);
1261 /* Disable sysclk */
1262 pci_read_config_dword(pdev
, PCI_MGA_OPTION
, &option
);
1264 pci_write_config_dword(pdev
, PCI_MGA_OPTION
, option
);
1266 mdev
->suspended
= false;
1273 static void mga_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1275 struct drm_device
*dev
= crtc
->dev
;
1276 struct mga_device
*mdev
= dev
->dev_private
;
1277 u8 seq1
= 0, crtcext1
= 0;
1280 case DRM_MODE_DPMS_ON
:
1283 mga_crtc_load_lut(crtc
);
1285 case DRM_MODE_DPMS_STANDBY
:
1289 case DRM_MODE_DPMS_SUSPEND
:
1293 case DRM_MODE_DPMS_OFF
:
1300 if (mode
== DRM_MODE_DPMS_OFF
) {
1304 WREG8(MGAREG_SEQ_INDEX
, 0x01);
1305 seq1
|= RREG8(MGAREG_SEQ_DATA
) & ~0x20;
1306 mga_wait_vsync(mdev
);
1307 mga_wait_busy(mdev
);
1308 WREG8(MGAREG_SEQ_DATA
, seq1
);
1310 WREG8(MGAREG_CRTCEXT_INDEX
, 0x01);
1311 crtcext1
|= RREG8(MGAREG_CRTCEXT_DATA
) & ~0x30;
1312 WREG8(MGAREG_CRTCEXT_DATA
, crtcext1
);
1315 if (mode
== DRM_MODE_DPMS_ON
&& mdev
->suspended
== true) {
1317 drm_helper_resume_force_mode(dev
);
1323 * This is called before a mode is programmed. A typical use might be to
1324 * enable DPMS during the programming to avoid seeing intermediate stages,
1325 * but that's not relevant to us
1327 static void mga_crtc_prepare(struct drm_crtc
*crtc
)
1329 struct drm_device
*dev
= crtc
->dev
;
1330 struct mga_device
*mdev
= dev
->dev_private
;
1333 /* mga_resume(crtc);*/
1335 WREG8(MGAREG_CRTC_INDEX
, 0x11);
1336 tmp
= RREG8(MGAREG_CRTC_DATA
);
1337 WREG_CRT(0x11, tmp
| 0x80);
1339 if (mdev
->type
== G200_SE_A
|| mdev
->type
== G200_SE_B
) {
1345 WREG8(MGAREG_SEQ_INDEX
, 0x1);
1346 tmp
= RREG8(MGAREG_SEQ_DATA
);
1348 /* start sync reset */
1350 WREG_SEQ(1, tmp
| 0x20);
1353 if (mdev
->type
== G200_WB
|| mdev
->type
== G200_EW3
)
1354 mga_g200wb_prepare(crtc
);
1360 * This is called after a mode is programmed. It should reverse anything done
1361 * by the prepare function
1363 static void mga_crtc_commit(struct drm_crtc
*crtc
)
1365 struct drm_device
*dev
= crtc
->dev
;
1366 struct mga_device
*mdev
= dev
->dev_private
;
1367 const struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1370 if (mdev
->type
== G200_WB
|| mdev
->type
== G200_EW3
)
1371 mga_g200wb_commit(crtc
);
1373 if (mdev
->type
== G200_SE_A
|| mdev
->type
== G200_SE_B
) {
1379 WREG8(MGAREG_SEQ_INDEX
, 0x1);
1380 tmp
= RREG8(MGAREG_SEQ_DATA
);
1386 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1390 * The core can pass us a set of gamma values to program. We actually only
1391 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1392 * but it's a requirement that we provide the function
1394 static int mga_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
1395 u16
*blue
, uint32_t size
)
1397 struct mga_crtc
*mga_crtc
= to_mga_crtc(crtc
);
1400 for (i
= 0; i
< size
; i
++) {
1401 mga_crtc
->lut_r
[i
] = red
[i
] >> 8;
1402 mga_crtc
->lut_g
[i
] = green
[i
] >> 8;
1403 mga_crtc
->lut_b
[i
] = blue
[i
] >> 8;
1405 mga_crtc_load_lut(crtc
);
1410 /* Simple cleanup function */
1411 static void mga_crtc_destroy(struct drm_crtc
*crtc
)
1413 struct mga_crtc
*mga_crtc
= to_mga_crtc(crtc
);
1415 drm_crtc_cleanup(crtc
);
1419 static void mga_crtc_disable(struct drm_crtc
*crtc
)
1422 DRM_DEBUG_KMS("\n");
1423 mga_crtc_dpms(crtc
, DRM_MODE_DPMS_OFF
);
1424 if (crtc
->primary
->fb
) {
1425 struct mga_framebuffer
*mga_fb
= to_mga_framebuffer(crtc
->primary
->fb
);
1426 struct drm_gem_object
*obj
= mga_fb
->obj
;
1427 struct mgag200_bo
*bo
= gem_to_mga_bo(obj
);
1428 ret
= mgag200_bo_reserve(bo
, false);
1431 mgag200_bo_push_sysram(bo
);
1432 mgag200_bo_unreserve(bo
);
1434 crtc
->primary
->fb
= NULL
;
1437 /* These provide the minimum set of functions required to handle a CRTC */
1438 static const struct drm_crtc_funcs mga_crtc_funcs
= {
1439 .cursor_set
= mga_crtc_cursor_set
,
1440 .cursor_move
= mga_crtc_cursor_move
,
1441 .gamma_set
= mga_crtc_gamma_set
,
1442 .set_config
= drm_crtc_helper_set_config
,
1443 .destroy
= mga_crtc_destroy
,
1446 static const struct drm_crtc_helper_funcs mga_helper_funcs
= {
1447 .disable
= mga_crtc_disable
,
1448 .dpms
= mga_crtc_dpms
,
1449 .mode_set
= mga_crtc_mode_set
,
1450 .mode_set_base
= mga_crtc_mode_set_base
,
1451 .prepare
= mga_crtc_prepare
,
1452 .commit
= mga_crtc_commit
,
1453 .load_lut
= mga_crtc_load_lut
,
1457 static void mga_crtc_init(struct mga_device
*mdev
)
1459 struct mga_crtc
*mga_crtc
;
1462 mga_crtc
= kzalloc(sizeof(struct mga_crtc
) +
1463 (MGAG200FB_CONN_LIMIT
* sizeof(struct drm_connector
*)),
1466 if (mga_crtc
== NULL
)
1469 drm_crtc_init(mdev
->dev
, &mga_crtc
->base
, &mga_crtc_funcs
);
1471 drm_mode_crtc_set_gamma_size(&mga_crtc
->base
, MGAG200_LUT_SIZE
);
1472 mdev
->mode_info
.crtc
= mga_crtc
;
1474 for (i
= 0; i
< MGAG200_LUT_SIZE
; i
++) {
1475 mga_crtc
->lut_r
[i
] = i
;
1476 mga_crtc
->lut_g
[i
] = i
;
1477 mga_crtc
->lut_b
[i
] = i
;
1480 drm_crtc_helper_add(&mga_crtc
->base
, &mga_helper_funcs
);
1483 /** Sets the color ramps on behalf of fbcon */
1484 void mga_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
1485 u16 blue
, int regno
)
1487 struct mga_crtc
*mga_crtc
= to_mga_crtc(crtc
);
1489 mga_crtc
->lut_r
[regno
] = red
>> 8;
1490 mga_crtc
->lut_g
[regno
] = green
>> 8;
1491 mga_crtc
->lut_b
[regno
] = blue
>> 8;
1494 /** Gets the color ramps on behalf of fbcon */
1495 void mga_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
1496 u16
*blue
, int regno
)
1498 struct mga_crtc
*mga_crtc
= to_mga_crtc(crtc
);
1500 *red
= (u16
)mga_crtc
->lut_r
[regno
] << 8;
1501 *green
= (u16
)mga_crtc
->lut_g
[regno
] << 8;
1502 *blue
= (u16
)mga_crtc
->lut_b
[regno
] << 8;
1506 * The encoder comes after the CRTC in the output pipeline, but before
1507 * the connector. It's responsible for ensuring that the digital
1508 * stream is appropriately converted into the output format. Setup is
1509 * very simple in this case - all we have to do is inform qemu of the
1510 * colour depth in order to ensure that it displays appropriately
1514 * These functions are analagous to those in the CRTC code, but are intended
1515 * to handle any encoder-specific limitations
1517 static void mga_encoder_mode_set(struct drm_encoder
*encoder
,
1518 struct drm_display_mode
*mode
,
1519 struct drm_display_mode
*adjusted_mode
)
1524 static void mga_encoder_dpms(struct drm_encoder
*encoder
, int state
)
1529 static void mga_encoder_prepare(struct drm_encoder
*encoder
)
1533 static void mga_encoder_commit(struct drm_encoder
*encoder
)
1537 static void mga_encoder_destroy(struct drm_encoder
*encoder
)
1539 struct mga_encoder
*mga_encoder
= to_mga_encoder(encoder
);
1540 drm_encoder_cleanup(encoder
);
1544 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs
= {
1545 .dpms
= mga_encoder_dpms
,
1546 .mode_set
= mga_encoder_mode_set
,
1547 .prepare
= mga_encoder_prepare
,
1548 .commit
= mga_encoder_commit
,
1551 static const struct drm_encoder_funcs mga_encoder_encoder_funcs
= {
1552 .destroy
= mga_encoder_destroy
,
1555 static struct drm_encoder
*mga_encoder_init(struct drm_device
*dev
)
1557 struct drm_encoder
*encoder
;
1558 struct mga_encoder
*mga_encoder
;
1560 mga_encoder
= kzalloc(sizeof(struct mga_encoder
), GFP_KERNEL
);
1564 encoder
= &mga_encoder
->base
;
1565 encoder
->possible_crtcs
= 0x1;
1567 drm_encoder_init(dev
, encoder
, &mga_encoder_encoder_funcs
,
1568 DRM_MODE_ENCODER_DAC
, NULL
);
1569 drm_encoder_helper_add(encoder
, &mga_encoder_helper_funcs
);
1575 static int mga_vga_get_modes(struct drm_connector
*connector
)
1577 struct mga_connector
*mga_connector
= to_mga_connector(connector
);
1581 edid
= drm_get_edid(connector
, &mga_connector
->i2c
->adapter
);
1583 drm_mode_connector_update_edid_property(connector
, edid
);
1584 ret
= drm_add_edid_modes(connector
, edid
);
1590 static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode
*mode
,
1593 uint32_t total_area
, divisor
;
1594 uint64_t active_area
, pixels_per_second
, bandwidth
;
1595 uint64_t bytes_per_pixel
= (bits_per_pixel
+ 7) / 8;
1599 if (!mode
->htotal
|| !mode
->vtotal
|| !mode
->clock
)
1602 active_area
= mode
->hdisplay
* mode
->vdisplay
;
1603 total_area
= mode
->htotal
* mode
->vtotal
;
1605 pixels_per_second
= active_area
* mode
->clock
* 1000;
1606 do_div(pixels_per_second
, total_area
);
1608 bandwidth
= pixels_per_second
* bytes_per_pixel
* 100;
1609 do_div(bandwidth
, divisor
);
1611 return (uint32_t)(bandwidth
);
1614 #define MODE_BANDWIDTH MODE_BAD
1616 static int mga_vga_mode_valid(struct drm_connector
*connector
,
1617 struct drm_display_mode
*mode
)
1619 struct drm_device
*dev
= connector
->dev
;
1620 struct mga_device
*mdev
= (struct mga_device
*)dev
->dev_private
;
1623 if (IS_G200_SE(mdev
)) {
1624 if (mdev
->unique_rev_id
== 0x01) {
1625 if (mode
->hdisplay
> 1600)
1626 return MODE_VIRTUAL_X
;
1627 if (mode
->vdisplay
> 1200)
1628 return MODE_VIRTUAL_Y
;
1629 if (mga_vga_calculate_mode_bandwidth(mode
, bpp
)
1631 return MODE_BANDWIDTH
;
1632 } else if (mdev
->unique_rev_id
== 0x02) {
1633 if (mode
->hdisplay
> 1920)
1634 return MODE_VIRTUAL_X
;
1635 if (mode
->vdisplay
> 1200)
1636 return MODE_VIRTUAL_Y
;
1637 if (mga_vga_calculate_mode_bandwidth(mode
, bpp
)
1639 return MODE_BANDWIDTH
;
1641 } else if (mdev
->type
== G200_WB
) {
1642 if (mode
->hdisplay
> 1280)
1643 return MODE_VIRTUAL_X
;
1644 if (mode
->vdisplay
> 1024)
1645 return MODE_VIRTUAL_Y
;
1646 if (mga_vga_calculate_mode_bandwidth(mode
,
1647 bpp
> (31877 * 1024)))
1648 return MODE_BANDWIDTH
;
1649 } else if (mdev
->type
== G200_EV
&&
1650 (mga_vga_calculate_mode_bandwidth(mode
, bpp
)
1651 > (32700 * 1024))) {
1652 return MODE_BANDWIDTH
;
1653 } else if (mdev
->type
== G200_EH
&&
1654 (mga_vga_calculate_mode_bandwidth(mode
, bpp
)
1655 > (37500 * 1024))) {
1656 return MODE_BANDWIDTH
;
1657 } else if (mdev
->type
== G200_ER
&&
1658 (mga_vga_calculate_mode_bandwidth(mode
,
1659 bpp
) > (55000 * 1024))) {
1660 return MODE_BANDWIDTH
;
1663 if ((mode
->hdisplay
% 8) != 0 || (mode
->hsync_start
% 8) != 0 ||
1664 (mode
->hsync_end
% 8) != 0 || (mode
->htotal
% 8) != 0) {
1665 return MODE_H_ILLEGAL
;
1668 if (mode
->crtc_hdisplay
> 2048 || mode
->crtc_hsync_start
> 4096 ||
1669 mode
->crtc_hsync_end
> 4096 || mode
->crtc_htotal
> 4096 ||
1670 mode
->crtc_vdisplay
> 2048 || mode
->crtc_vsync_start
> 4096 ||
1671 mode
->crtc_vsync_end
> 4096 || mode
->crtc_vtotal
> 4096) {
1675 /* Validate the mode input by the user */
1676 if (connector
->cmdline_mode
.specified
) {
1677 if (connector
->cmdline_mode
.bpp_specified
)
1678 bpp
= connector
->cmdline_mode
.bpp
;
1681 if ((mode
->hdisplay
* mode
->vdisplay
* (bpp
/8)) > mdev
->mc
.vram_size
) {
1682 if (connector
->cmdline_mode
.specified
)
1683 connector
->cmdline_mode
.specified
= false;
1690 static struct drm_encoder
*mga_connector_best_encoder(struct drm_connector
1693 int enc_id
= connector
->encoder_ids
[0];
1694 /* pick the encoder ids */
1696 return drm_encoder_find(connector
->dev
, enc_id
);
1700 static void mga_connector_destroy(struct drm_connector
*connector
)
1702 struct mga_connector
*mga_connector
= to_mga_connector(connector
);
1703 mgag200_i2c_destroy(mga_connector
->i2c
);
1704 drm_connector_cleanup(connector
);
1708 static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs
= {
1709 .get_modes
= mga_vga_get_modes
,
1710 .mode_valid
= mga_vga_mode_valid
,
1711 .best_encoder
= mga_connector_best_encoder
,
1714 static const struct drm_connector_funcs mga_vga_connector_funcs
= {
1715 .dpms
= drm_helper_connector_dpms
,
1716 .fill_modes
= drm_helper_probe_single_connector_modes
,
1717 .destroy
= mga_connector_destroy
,
1720 static struct drm_connector
*mga_vga_init(struct drm_device
*dev
)
1722 struct drm_connector
*connector
;
1723 struct mga_connector
*mga_connector
;
1725 mga_connector
= kzalloc(sizeof(struct mga_connector
), GFP_KERNEL
);
1729 connector
= &mga_connector
->base
;
1731 drm_connector_init(dev
, connector
,
1732 &mga_vga_connector_funcs
, DRM_MODE_CONNECTOR_VGA
);
1734 drm_connector_helper_add(connector
, &mga_vga_connector_helper_funcs
);
1736 drm_connector_register(connector
);
1738 mga_connector
->i2c
= mgag200_i2c_create(dev
);
1739 if (!mga_connector
->i2c
)
1740 DRM_ERROR("failed to add ddc bus\n");
1746 int mgag200_modeset_init(struct mga_device
*mdev
)
1748 struct drm_encoder
*encoder
;
1749 struct drm_connector
*connector
;
1752 mdev
->mode_info
.mode_config_initialized
= true;
1754 mdev
->dev
->mode_config
.max_width
= MGAG200_MAX_FB_WIDTH
;
1755 mdev
->dev
->mode_config
.max_height
= MGAG200_MAX_FB_HEIGHT
;
1757 mdev
->dev
->mode_config
.fb_base
= mdev
->mc
.vram_base
;
1759 mga_crtc_init(mdev
);
1761 encoder
= mga_encoder_init(mdev
->dev
);
1763 DRM_ERROR("mga_encoder_init failed\n");
1767 connector
= mga_vga_init(mdev
->dev
);
1769 DRM_ERROR("mga_vga_init failed\n");
1773 drm_mode_connector_attach_encoder(connector
, encoder
);
1775 ret
= mgag200_fbdev_init(mdev
);
1777 DRM_ERROR("mga_fbdev_init failed\n");
1784 void mgag200_modeset_fini(struct mga_device
*mdev
)