2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drv.h"
27 #include <nouveau_bios.h>
28 #include "nouveau_hw.h"
29 #include "nouveau_pm.h"
30 #include "nouveau_hwsq.h"
31 #include "nv50_display.h"
47 static u32
read_clk(struct drm_device
*, enum clk_src
);
50 read_div(struct drm_device
*dev
)
52 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
54 switch (dev_priv
->chipset
) {
55 case 0x50: /* it exists, but only has bit 31, not the dividers.. */
60 return nv_rd32(dev
, 0x004700);
64 return nv_rd32(dev
, 0x004800);
71 read_pll_src(struct drm_device
*dev
, u32 base
)
73 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
74 u32 coef
, ref
= read_clk(dev
, clk_src_crystal
);
75 u32 rsel
= nv_rd32(dev
, 0x00e18c);
78 switch (dev_priv
->chipset
) {
83 case 0x4028: id
= !!(rsel
& 0x00000004); break;
84 case 0x4008: id
= !!(rsel
& 0x00000008); break;
85 case 0x4030: id
= 0; break;
87 NV_ERROR(dev
, "ref: bad pll 0x%06x\n", base
);
91 coef
= nv_rd32(dev
, 0x00e81c + (id
* 0x0c));
92 ref
*= (coef
& 0x01000000) ? 2 : 4;
93 P
= (coef
& 0x00070000) >> 16;
94 N
= ((coef
& 0x0000ff00) >> 8) + 1;
95 M
= ((coef
& 0x000000ff) >> 0) + 1;
100 coef
= nv_rd32(dev
, 0x00e81c);
101 P
= (coef
& 0x00070000) >> 16;
102 N
= (coef
& 0x0000ff00) >> 8;
103 M
= (coef
& 0x000000ff) >> 0;
108 rsel
= nv_rd32(dev
, 0x00c050);
110 case 0x4020: rsel
= (rsel
& 0x00000003) >> 0; break;
111 case 0x4008: rsel
= (rsel
& 0x0000000c) >> 2; break;
112 case 0x4028: rsel
= (rsel
& 0x00001800) >> 11; break;
113 case 0x4030: rsel
= 3; break;
115 NV_ERROR(dev
, "ref: bad pll 0x%06x\n", base
);
120 case 0: id
= 1; break;
121 case 1: return read_clk(dev
, clk_src_crystal
);
122 case 2: return read_clk(dev
, clk_src_href
);
123 case 3: id
= 0; break;
126 coef
= nv_rd32(dev
, 0x00e81c + (id
* 0x28));
127 P
= (nv_rd32(dev
, 0x00e824 + (id
* 0x28)) >> 16) & 7;
128 P
+= (coef
& 0x00070000) >> 16;
129 N
= (coef
& 0x0000ff00) >> 8;
130 M
= (coef
& 0x000000ff) >> 0;
137 return (ref
* N
/ M
) >> P
;
142 read_pll_ref(struct drm_device
*dev
, u32 base
)
144 u32 src
, mast
= nv_rd32(dev
, 0x00c040);
148 src
= !!(mast
& 0x00200000);
151 src
= !!(mast
& 0x00400000);
154 src
= !!(mast
& 0x00010000);
157 src
= !!(mast
& 0x02000000);
160 return read_clk(dev
, clk_src_crystal
);
162 NV_ERROR(dev
, "bad pll 0x%06x\n", base
);
167 return read_clk(dev
, clk_src_href
);
168 return read_pll_src(dev
, base
);
172 read_pll(struct drm_device
*dev
, u32 base
)
174 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
175 u32 mast
= nv_rd32(dev
, 0x00c040);
176 u32 ctrl
= nv_rd32(dev
, base
+ 0);
177 u32 coef
= nv_rd32(dev
, base
+ 4);
178 u32 ref
= read_pll_ref(dev
, base
);
182 if (base
== 0x004028 && (mast
& 0x00100000)) {
183 /* wtf, appears to only disable post-divider on nva0 */
184 if (dev_priv
->chipset
!= 0xa0)
185 return read_clk(dev
, clk_src_dom6
);
188 N2
= (coef
& 0xff000000) >> 24;
189 M2
= (coef
& 0x00ff0000) >> 16;
190 N1
= (coef
& 0x0000ff00) >> 8;
191 M1
= (coef
& 0x000000ff);
192 if ((ctrl
& 0x80000000) && M1
) {
194 if ((ctrl
& 0x40000100) == 0x40000000) {
206 read_clk(struct drm_device
*dev
, enum clk_src src
)
208 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
209 u32 mast
= nv_rd32(dev
, 0x00c040);
213 case clk_src_crystal
:
214 return dev_priv
->crystal
;
216 return 100000; /* PCIE reference clock */
218 return read_clk(dev
, clk_src_href
) * 27778 / 10000;
220 return read_clk(dev
, clk_src_hclk
) * 3;
221 case clk_src_hclkm3d2
:
222 return read_clk(dev
, clk_src_hclk
) * 3 / 2;
224 switch (mast
& 0x30000000) {
225 case 0x00000000: return read_clk(dev
, clk_src_href
);
226 case 0x10000000: break;
227 case 0x20000000: /* !0x50 */
228 case 0x30000000: return read_clk(dev
, clk_src_hclk
);
232 if (!(mast
& 0x00100000))
233 P
= (nv_rd32(dev
, 0x004028) & 0x00070000) >> 16;
234 switch (mast
& 0x00000003) {
235 case 0x00000000: return read_clk(dev
, clk_src_crystal
) >> P
;
236 case 0x00000001: return read_clk(dev
, clk_src_dom6
);
237 case 0x00000002: return read_pll(dev
, 0x004020) >> P
;
238 case 0x00000003: return read_pll(dev
, 0x004028) >> P
;
242 P
= (nv_rd32(dev
, 0x004020) & 0x00070000) >> 16;
243 switch (mast
& 0x00000030) {
245 if (mast
& 0x00000080)
246 return read_clk(dev
, clk_src_host
) >> P
;
247 return read_clk(dev
, clk_src_crystal
) >> P
;
248 case 0x00000010: break;
249 case 0x00000020: return read_pll(dev
, 0x004028) >> P
;
250 case 0x00000030: return read_pll(dev
, 0x004020) >> P
;
254 P
= (nv_rd32(dev
, 0x004008) & 0x00070000) >> 16;
255 if (nv_rd32(dev
, 0x004008) & 0x00000200) {
256 switch (mast
& 0x0000c000) {
258 return read_clk(dev
, clk_src_crystal
) >> P
;
261 return read_clk(dev
, clk_src_href
) >> P
;
264 return read_pll(dev
, 0x004008) >> P
;
268 P
= (read_div(dev
) & 0x00000700) >> 8;
269 switch (dev_priv
->chipset
) {
276 switch (mast
& 0x00000c00) {
278 if (dev_priv
->chipset
== 0xa0) /* wtf?? */
279 return read_clk(dev
, clk_src_nvclk
) >> P
;
280 return read_clk(dev
, clk_src_crystal
) >> P
;
284 if (mast
& 0x01000000)
285 return read_pll(dev
, 0x004028) >> P
;
286 return read_pll(dev
, 0x004030) >> P
;
288 return read_clk(dev
, clk_src_nvclk
) >> P
;
292 switch (mast
& 0x00000c00) {
294 return read_clk(dev
, clk_src_nvclk
) >> P
;
298 return read_clk(dev
, clk_src_hclkm3d2
) >> P
;
300 return read_clk(dev
, clk_src_mclk
) >> P
;
306 switch (dev_priv
->chipset
) {
309 return read_pll(dev
, 0x00e810) >> 2;
316 P
= (read_div(dev
) & 0x00000007) >> 0;
317 switch (mast
& 0x0c000000) {
318 case 0x00000000: return read_clk(dev
, clk_src_href
);
319 case 0x04000000: break;
320 case 0x08000000: return read_clk(dev
, clk_src_hclk
);
322 return read_clk(dev
, clk_src_hclkm3
) >> P
;
332 NV_DEBUG(dev
, "unknown clock source %d 0x%08x\n", src
, mast
);
337 nv50_pm_clocks_get(struct drm_device
*dev
, struct nouveau_pm_level
*perflvl
)
339 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
340 if (dev_priv
->chipset
== 0xaa ||
341 dev_priv
->chipset
== 0xac)
344 perflvl
->core
= read_clk(dev
, clk_src_nvclk
);
345 perflvl
->shader
= read_clk(dev
, clk_src_sclk
);
346 perflvl
->memory
= read_clk(dev
, clk_src_mclk
);
347 if (dev_priv
->chipset
!= 0x50) {
348 perflvl
->vdec
= read_clk(dev
, clk_src_vdec
);
349 perflvl
->dom6
= read_clk(dev
, clk_src_dom6
);
355 struct nv50_pm_state
{
356 struct nouveau_pm_level
*perflvl
;
357 struct hwsq_ucode eclk_hwsq
;
358 struct hwsq_ucode mclk_hwsq
;
366 calc_pll(struct drm_device
*dev
, u32 reg
, struct nvbios_pll
*pll
,
367 u32 clk
, int *N1
, int *M1
, int *log2P
)
369 struct nouveau_pll_vals coef
;
372 ret
= get_pll_limits(dev
, reg
, pll
);
376 pll
->vco2
.max_freq
= 0;
377 pll
->refclk
= read_pll_ref(dev
, reg
);
381 ret
= nouveau_calc_pll_mnp(dev
, pll
, clk
, &coef
);
392 calc_div(u32 src
, u32 target
, int *div
)
394 u32 clk0
= src
, clk1
= src
;
395 for (*div
= 0; *div
<= 7; (*div
)++) {
396 if (clk0
<= target
) {
397 clk1
= clk0
<< (*div
? 1 : 0);
403 if (target
- clk0
<= clk1
- target
)
410 clk_same(u32 a
, u32 b
)
412 return ((a
/ 1000) == (b
/ 1000));
416 mclk_precharge(struct nouveau_mem_exec_func
*exec
)
418 struct nv50_pm_state
*info
= exec
->priv
;
419 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
421 hwsq_wr32(hwsq
, 0x1002d4, 0x00000001);
425 mclk_refresh(struct nouveau_mem_exec_func
*exec
)
427 struct nv50_pm_state
*info
= exec
->priv
;
428 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
430 hwsq_wr32(hwsq
, 0x1002d0, 0x00000001);
434 mclk_refresh_auto(struct nouveau_mem_exec_func
*exec
, bool enable
)
436 struct nv50_pm_state
*info
= exec
->priv
;
437 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
439 hwsq_wr32(hwsq
, 0x100210, enable
? 0x80000000 : 0x00000000);
443 mclk_refresh_self(struct nouveau_mem_exec_func
*exec
, bool enable
)
445 struct nv50_pm_state
*info
= exec
->priv
;
446 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
448 hwsq_wr32(hwsq
, 0x1002dc, enable
? 0x00000001 : 0x00000000);
452 mclk_wait(struct nouveau_mem_exec_func
*exec
, u32 nsec
)
454 struct nv50_pm_state
*info
= exec
->priv
;
455 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
458 hwsq_usec(hwsq
, (nsec
+ 500) / 1000);
462 mclk_mrg(struct nouveau_mem_exec_func
*exec
, int mr
)
465 return nv_rd32(exec
->dev
, 0x1002c0 + ((mr
- 0) * 4));
467 return nv_rd32(exec
->dev
, 0x1002e0 + ((mr
- 2) * 4));
472 mclk_mrs(struct nouveau_mem_exec_func
*exec
, int mr
, u32 data
)
474 struct nv50_pm_state
*info
= exec
->priv
;
475 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
478 if (nvfb_vram_rank_B(exec
->dev
))
479 hwsq_wr32(hwsq
, 0x1002c8 + ((mr
- 0) * 4), data
);
480 hwsq_wr32(hwsq
, 0x1002c0 + ((mr
- 0) * 4), data
);
483 if (nvfb_vram_rank_B(exec
->dev
))
484 hwsq_wr32(hwsq
, 0x1002e8 + ((mr
- 2) * 4), data
);
485 hwsq_wr32(hwsq
, 0x1002e0 + ((mr
- 2) * 4), data
);
490 mclk_clock_set(struct nouveau_mem_exec_func
*exec
)
492 struct nv50_pm_state
*info
= exec
->priv
;
493 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
494 u32 ctrl
= nv_rd32(exec
->dev
, 0x004008);
496 info
->mmast
= nv_rd32(exec
->dev
, 0x00c040);
497 info
->mmast
&= ~0xc0000000; /* get MCLK_2 from HREF */
498 info
->mmast
|= 0x0000c000; /* use MCLK_2 as MPLL_BYPASS clock */
500 hwsq_wr32(hwsq
, 0xc040, info
->mmast
);
501 hwsq_wr32(hwsq
, 0x4008, ctrl
| 0x00000200); /* bypass MPLL */
502 if (info
->mctrl
& 0x80000000)
503 hwsq_wr32(hwsq
, 0x400c, info
->mcoef
);
504 hwsq_wr32(hwsq
, 0x4008, info
->mctrl
);
508 mclk_timing_set(struct nouveau_mem_exec_func
*exec
)
510 struct drm_device
*dev
= exec
->dev
;
511 struct nv50_pm_state
*info
= exec
->priv
;
512 struct nouveau_pm_level
*perflvl
= info
->perflvl
;
513 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
516 for (i
= 0; i
< 9; i
++) {
517 u32 reg
= 0x100220 + (i
* 4);
518 u32 val
= nv_rd32(dev
, reg
);
519 if (val
!= perflvl
->timing
.reg
[i
])
520 hwsq_wr32(hwsq
, reg
, perflvl
->timing
.reg
[i
]);
525 calc_mclk(struct drm_device
*dev
, struct nouveau_pm_level
*perflvl
,
526 struct nv50_pm_state
*info
)
528 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
529 u32 crtc_mask
= nv50_display_active_crtcs(dev
);
530 struct nouveau_mem_exec_func exec
= {
532 .precharge
= mclk_precharge
,
533 .refresh
= mclk_refresh
,
534 .refresh_auto
= mclk_refresh_auto
,
535 .refresh_self
= mclk_refresh_self
,
539 .clock_set
= mclk_clock_set
,
540 .timing_set
= mclk_timing_set
,
543 struct hwsq_ucode
*hwsq
= &info
->mclk_hwsq
;
544 struct nvbios_pll pll
;
548 /* use pcie refclock if possible, otherwise use mpll */
549 info
->mctrl
= nv_rd32(dev
, 0x004008);
550 info
->mctrl
&= ~0x81ff0200;
551 if (clk_same(perflvl
->memory
, read_clk(dev
, clk_src_href
))) {
552 info
->mctrl
|= 0x00000200 | (pll
.bias_p
<< 19);
554 ret
= calc_pll(dev
, 0x4008, &pll
, perflvl
->memory
, &N
, &M
, &P
);
558 info
->mctrl
|= 0x80000000 | (P
<< 22) | (P
<< 16);
559 info
->mctrl
|= pll
.bias_p
<< 19;
560 info
->mcoef
= (N
<< 8) | M
;
563 /* build the ucode which will reclock the memory for us */
566 hwsq_op5f(hwsq
, crtc_mask
, 0x00); /* wait for scanout */
567 hwsq_op5f(hwsq
, crtc_mask
, 0x01); /* wait for vblank */
569 if (dev_priv
->chipset
>= 0x92)
570 hwsq_wr32(hwsq
, 0x611200, 0x00003300); /* disable scanout */
571 hwsq_setf(hwsq
, 0x10, 0); /* disable bus access */
572 hwsq_op5f(hwsq
, 0x00, 0x01); /* no idea :s */
574 ret
= nouveau_mem_exec(&exec
, perflvl
);
578 hwsq_setf(hwsq
, 0x10, 1); /* enable bus access */
579 hwsq_op5f(hwsq
, 0x00, 0x00); /* no idea, reverse of 0x00, 0x01? */
580 if (dev_priv
->chipset
>= 0x92)
581 hwsq_wr32(hwsq
, 0x611200, 0x00003330); /* enable scanout */
587 nv50_pm_clocks_pre(struct drm_device
*dev
, struct nouveau_pm_level
*perflvl
)
589 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
590 struct nv50_pm_state
*info
;
591 struct hwsq_ucode
*hwsq
;
592 struct nvbios_pll pll
;
593 u32 out
, mast
, divs
, ctrl
;
594 int clk
, ret
= -EINVAL
;
597 if (dev_priv
->chipset
== 0xaa ||
598 dev_priv
->chipset
== 0xac)
599 return ERR_PTR(-ENODEV
);
601 info
= kmalloc(sizeof(*info
), GFP_KERNEL
);
603 return ERR_PTR(-ENOMEM
);
604 info
->perflvl
= perflvl
;
606 /* memory: build hwsq ucode which we'll use to reclock memory.
607 * use pcie refclock if possible, otherwise use mpll */
608 info
->mclk_hwsq
.len
= 0;
609 if (perflvl
->memory
) {
610 ret
= calc_mclk(dev
, perflvl
, info
);
613 info
->mscript
= perflvl
->memscript
;
616 divs
= read_div(dev
);
619 /* start building HWSQ script for engine reclocking */
620 hwsq
= &info
->eclk_hwsq
;
622 hwsq_setf(hwsq
, 0x10, 0); /* disable bus access */
623 hwsq_op5f(hwsq
, 0x00, 0x01); /* wait for access disabled? */
625 /* vdec/dom6: switch to "safe" clocks temporarily */
636 hwsq_wr32(hwsq
, 0x00c040, mast
);
638 /* vdec: avoid modifying xpll until we know exactly how the other
639 * clock domains work, i suspect at least some of them can also be
643 /* see how close we can get using nvclk as a source */
644 clk
= calc_div(perflvl
->core
, perflvl
->vdec
, &P1
);
646 /* see how close we can get using xpll/hclk as a source */
647 if (dev_priv
->chipset
!= 0x98)
648 out
= read_pll(dev
, 0x004030);
650 out
= read_clk(dev
, clk_src_hclkm3d2
);
651 out
= calc_div(out
, perflvl
->vdec
, &P2
);
653 /* select whichever gets us closest */
654 if (abs((int)perflvl
->vdec
- clk
) <=
655 abs((int)perflvl
->vdec
- out
)) {
656 if (dev_priv
->chipset
!= 0x98)
665 /* dom6: nfi what this is, but we're limited to various combinations
666 * of the host clock frequency
669 if (clk_same(perflvl
->dom6
, read_clk(dev
, clk_src_href
))) {
672 if (clk_same(perflvl
->dom6
, read_clk(dev
, clk_src_hclk
))) {
675 clk
= read_clk(dev
, clk_src_hclk
) * 3;
676 clk
= calc_div(clk
, perflvl
->dom6
, &P1
);
683 /* vdec/dom6: complete switch to new clocks */
684 switch (dev_priv
->chipset
) {
688 hwsq_wr32(hwsq
, 0x004800, divs
);
691 hwsq_wr32(hwsq
, 0x004700, divs
);
695 hwsq_wr32(hwsq
, 0x00c040, mast
);
697 /* core/shader: make sure sclk/nvclk are disconnected from their
698 * PLLs (nvclk to dom6, sclk to hclk)
700 if (dev_priv
->chipset
< 0x92)
701 mast
= (mast
& ~0x001000b0) | 0x00100080;
703 mast
= (mast
& ~0x000000b3) | 0x00000081;
705 hwsq_wr32(hwsq
, 0x00c040, mast
);
707 /* core: for the moment at least, always use nvpll */
708 clk
= calc_pll(dev
, 0x4028, &pll
, perflvl
->core
, &N
, &M
, &P1
);
712 ctrl
= nv_rd32(dev
, 0x004028) & ~0xc03f0100;
716 hwsq_wr32(hwsq
, 0x004028, 0x80000000 | (P1
<< 19) | (P1
<< 16) | ctrl
);
717 hwsq_wr32(hwsq
, 0x00402c, (N
<< 8) | M
);
719 /* shader: tie to nvclk if possible, otherwise use spll. have to be
720 * very careful that the shader clock is at least twice the core, or
721 * some chipsets will be very unhappy. i expect most or all of these
722 * cases will be handled by tying to nvclk, but it's possible there's
725 ctrl
= nv_rd32(dev
, 0x004020) & ~0xc03f0100;
727 if (P1
-- && perflvl
->shader
== (perflvl
->core
<< 1)) {
728 hwsq_wr32(hwsq
, 0x004020, (P1
<< 19) | (P1
<< 16) | ctrl
);
729 hwsq_wr32(hwsq
, 0x00c040, 0x00000020 | mast
);
731 clk
= calc_pll(dev
, 0x4020, &pll
, perflvl
->shader
, &N
, &M
, &P1
);
736 hwsq_wr32(hwsq
, 0x004020, (P1
<< 19) | (P1
<< 16) | ctrl
);
737 hwsq_wr32(hwsq
, 0x004024, (N
<< 8) | M
);
738 hwsq_wr32(hwsq
, 0x00c040, 0x00000030 | mast
);
741 hwsq_setf(hwsq
, 0x10, 1); /* enable bus access */
742 hwsq_op5f(hwsq
, 0x00, 0x00); /* wait for access enabled? */
752 prog_hwsq(struct drm_device
*dev
, struct hwsq_ucode
*hwsq
)
754 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
755 u32 hwsq_data
, hwsq_kick
;
758 if (dev_priv
->chipset
< 0x94) {
759 hwsq_data
= 0x001400;
760 hwsq_kick
= 0x00000003;
762 hwsq_data
= 0x080000;
763 hwsq_kick
= 0x00000001;
765 /* upload hwsq ucode */
766 nv_mask(dev
, 0x001098, 0x00000008, 0x00000000);
767 nv_wr32(dev
, 0x001304, 0x00000000);
768 if (dev_priv
->chipset
>= 0x92)
769 nv_wr32(dev
, 0x001318, 0x00000000);
770 for (i
= 0; i
< hwsq
->len
/ 4; i
++)
771 nv_wr32(dev
, hwsq_data
+ (i
* 4), hwsq
->ptr
.u32
[i
]);
772 nv_mask(dev
, 0x001098, 0x00000018, 0x00000018);
774 /* launch, and wait for completion */
775 nv_wr32(dev
, 0x00130c, hwsq_kick
);
776 if (!nv_wait(dev
, 0x001308, 0x00000100, 0x00000000)) {
777 NV_ERROR(dev
, "hwsq ucode exec timed out\n");
778 NV_ERROR(dev
, "0x001308: 0x%08x\n", nv_rd32(dev
, 0x001308));
779 for (i
= 0; i
< hwsq
->len
/ 4; i
++) {
780 NV_ERROR(dev
, "0x%06x: 0x%08x\n", 0x1400 + (i
* 4),
781 nv_rd32(dev
, 0x001400 + (i
* 4)));
791 nv50_pm_clocks_set(struct drm_device
*dev
, void *data
)
793 struct nv50_pm_state
*info
= data
;
797 /* halt and idle execution engines */
798 nv_mask(dev
, 0x002504, 0x00000001, 0x00000001);
799 if (!nv_wait(dev
, 0x002504, 0x00000010, 0x00000010))
801 if (!nv_wait(dev
, 0x00251c, 0x0000003f, 0x0000003f))
804 /* program memory clock, if necessary - must come before engine clock
805 * reprogramming due to how we construct the hwsq scripts in pre()
807 if (info
->mclk_hwsq
.len
) {
808 /* execute some scripts that do ??? from the vbios.. */
809 if (!bit_table(dev
, 'M', &M
) && M
.version
== 1) {
811 nouveau_bios_init_exec(dev
, ROM16(M
.data
[5]));
813 nouveau_bios_init_exec(dev
, ROM16(M
.data
[7]));
815 nouveau_bios_init_exec(dev
, ROM16(M
.data
[9]));
816 nouveau_bios_init_exec(dev
, info
->mscript
);
819 ret
= prog_hwsq(dev
, &info
->mclk_hwsq
);
824 /* program engine clocks */
825 ret
= prog_hwsq(dev
, &info
->eclk_hwsq
);
828 nv_mask(dev
, 0x002504, 0x00000001, 0x00000000);
834 pwm_info(struct drm_device
*dev
, int *line
, int *ctrl
, int *indx
)
851 NV_ERROR(dev
, "unknown pwm ctrl for gpio %d\n", *line
);
859 nv50_pm_pwm_get(struct drm_device
*dev
, int line
, u32
*divs
, u32
*duty
)
861 int ctrl
, id
, ret
= pwm_info(dev
, &line
, &ctrl
, &id
);
865 if (nv_rd32(dev
, ctrl
) & (1 << line
)) {
866 *divs
= nv_rd32(dev
, 0x00e114 + (id
* 8));
867 *duty
= nv_rd32(dev
, 0x00e118 + (id
* 8));
875 nv50_pm_pwm_set(struct drm_device
*dev
, int line
, u32 divs
, u32 duty
)
877 int ctrl
, id
, ret
= pwm_info(dev
, &line
, &ctrl
, &id
);
881 nv_mask(dev
, ctrl
, 0x00010001 << line
, 0x00000001 << line
);
882 nv_wr32(dev
, 0x00e114 + (id
* 8), divs
);
883 nv_wr32(dev
, 0x00e118 + (id
* 8), duty
| 0x80000000);