]>
git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 nv20_identify(struct nvkm_device
*device
)
29 switch (device
->chipset
) {
31 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
32 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
33 device
->oclass
[NVDEV_SUBDEV_MC
] = nv04_mc_oclass
;
34 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
35 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv04_instmem_oclass
;
36 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv04_mmu_oclass
;
37 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
38 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv17_fifo_oclass
;
39 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
40 device
->oclass
[NVDEV_ENGINE_GR
] = &nv20_gr_oclass
;
41 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
44 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
45 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
46 device
->oclass
[NVDEV_SUBDEV_MC
] = nv04_mc_oclass
;
47 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
48 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv04_instmem_oclass
;
49 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv04_mmu_oclass
;
50 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
51 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv17_fifo_oclass
;
52 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
53 device
->oclass
[NVDEV_ENGINE_GR
] = &nv25_gr_oclass
;
54 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
57 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
58 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
59 device
->oclass
[NVDEV_SUBDEV_MC
] = nv04_mc_oclass
;
60 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
61 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv04_instmem_oclass
;
62 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv04_mmu_oclass
;
63 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
64 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv17_fifo_oclass
;
65 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
66 device
->oclass
[NVDEV_ENGINE_GR
] = &nv25_gr_oclass
;
67 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;
70 device
->oclass
[NVDEV_SUBDEV_GPIO
] = nv10_gpio_oclass
;
71 device
->oclass
[NVDEV_SUBDEV_I2C
] = nv04_i2c_oclass
;
72 device
->oclass
[NVDEV_SUBDEV_MC
] = nv04_mc_oclass
;
73 device
->oclass
[NVDEV_SUBDEV_TIMER
] = &nv04_timer_oclass
;
74 device
->oclass
[NVDEV_SUBDEV_INSTMEM
] = nv04_instmem_oclass
;
75 device
->oclass
[NVDEV_SUBDEV_MMU
] = &nv04_mmu_oclass
;
76 device
->oclass
[NVDEV_ENGINE_DMAOBJ
] = nv04_dmaeng_oclass
;
77 device
->oclass
[NVDEV_ENGINE_FIFO
] = nv17_fifo_oclass
;
78 device
->oclass
[NVDEV_ENGINE_SW
] = nv10_sw_oclass
;
79 device
->oclass
[NVDEV_ENGINE_GR
] = &nv2a_gr_oclass
;
80 device
->oclass
[NVDEV_ENGINE_DISP
] = nv04_disp_oclass
;