drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25 #include "ram.h"
  26
  27 #include <core/client.h>
  28 #include <core/enum.h>
  29 #include <engine/fifo.h>
  30
  31 int
  32 nv50_fb_memtype[0x80] = {
  33         1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  34         1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
  35         1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
  36         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  37         1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
  38         0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  39         1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
  40         1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
  41 };
  42
  43 static int
  44 nv50_fb_ram_new(struct nvkm_fb *base, struct nvkm_ram **pram)
  45 {
  46         struct nv50_fb *fb = nv50_fb(base);
  47         return fb->func->ram_new(&fb->base, pram);
  48 }
  49
  50 static bool
  51 nv50_fb_memtype_valid(struct nvkm_fb *fb, u32 memtype)
  52 {
  53         return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
  54 }
  55
  56 static const struct nvkm_enum vm_dispatch_subclients[] = {
  57         { 0x00000000, "GRCTX" },
  58         { 0x00000001, "NOTIFY" },
  59         { 0x00000002, "QUERY" },
  60         { 0x00000003, "COND" },
  61         { 0x00000004, "M2M_IN" },
  62         { 0x00000005, "M2M_OUT" },
  63         { 0x00000006, "M2M_NOTIFY" },
  64         {}
  65 };
  66
  67 static const struct nvkm_enum vm_ccache_subclients[] = {
  68         { 0x00000000, "CB" },
  69         { 0x00000001, "TIC" },
  70         { 0x00000002, "TSC" },
  71         {}
  72 };
  73
  74 static const struct nvkm_enum vm_prop_subclients[] = {
  75         { 0x00000000, "RT0" },
  76         { 0x00000001, "RT1" },
  77         { 0x00000002, "RT2" },
  78         { 0x00000003, "RT3" },
  79         { 0x00000004, "RT4" },
  80         { 0x00000005, "RT5" },
  81         { 0x00000006, "RT6" },
  82         { 0x00000007, "RT7" },
  83         { 0x00000008, "ZETA" },
  84         { 0x00000009, "LOCAL" },
  85         { 0x0000000a, "GLOBAL" },
  86         { 0x0000000b, "STACK" },
  87         { 0x0000000c, "DST2D" },
  88         {}
  89 };
  90
  91 static const struct nvkm_enum vm_pfifo_subclients[] = {
  92         { 0x00000000, "PUSHBUF" },
  93         { 0x00000001, "SEMAPHORE" },
  94         {}
  95 };
  96
  97 static const struct nvkm_enum vm_bar_subclients[] = {
  98         { 0x00000000, "FB" },
  99         { 0x00000001, "IN" },
 100         {}
 101 };
 102
 103 static const struct nvkm_enum vm_client[] = {
 104         { 0x00000000, "STRMOUT" },
 105         { 0x00000003, "DISPATCH", vm_dispatch_subclients },
 106         { 0x00000004, "PFIFO_WRITE" },
 107         { 0x00000005, "CCACHE", vm_ccache_subclients },
 108         { 0x00000006, "PMSPPP" },
 109         { 0x00000007, "CLIPID" },
 110         { 0x00000008, "PFIFO_READ" },
 111         { 0x00000009, "VFETCH" },
 112         { 0x0000000a, "TEXTURE" },
 113         { 0x0000000b, "PROP", vm_prop_subclients },
 114         { 0x0000000c, "PVP" },
 115         { 0x0000000d, "PBSP" },
 116         { 0x0000000e, "PCRYPT" },
 117         { 0x0000000f, "PCOUNTER" },
 118         { 0x00000011, "PDAEMON" },
 119         {}
 120 };
 121
 122 static const struct nvkm_enum vm_engine[] = {
 123         { 0x00000000, "PGRAPH" },
 124         { 0x00000001, "PVP" },
 125         { 0x00000004, "PEEPHOLE" },
 126         { 0x00000005, "PFIFO", vm_pfifo_subclients },
 127         { 0x00000006, "BAR", vm_bar_subclients },
 128         { 0x00000008, "PMSPPP" },
 129         { 0x00000008, "PMPEG" },
 130         { 0x00000009, "PBSP" },
 131         { 0x0000000a, "PCRYPT" },
 132         { 0x0000000b, "PCOUNTER" },
 133         { 0x0000000c, "SEMAPHORE_BG" },
 134         { 0x0000000d, "PCE0" },
 135         { 0x0000000e, "PMU" },
 136         {}
 137 };
 138
 139 static const struct nvkm_enum vm_fault[] = {
 140         { 0x00000000, "PT_NOT_PRESENT" },
 141         { 0x00000001, "PT_TOO_SHORT" },
 142         { 0x00000002, "PAGE_NOT_PRESENT" },
 143         { 0x00000003, "PAGE_SYSTEM_ONLY" },
 144         { 0x00000004, "PAGE_READ_ONLY" },
 145         { 0x00000006, "NULL_DMAOBJ" },
 146         { 0x00000007, "WRONG_MEMTYPE" },
 147         { 0x0000000b, "VRAM_LIMIT" },
 148         { 0x0000000f, "DMAOBJ_LIMIT" },
 149         {}
 150 };
 151
 152 static void
 153 nv50_fb_intr(struct nvkm_fb *base)
 154 {
 155         struct nv50_fb *fb = nv50_fb(base);
 156         struct nvkm_subdev *subdev = &fb->base.subdev;
 157         struct nvkm_device *device = subdev->device;
 158         struct nvkm_fifo *fifo = device->fifo;
 159         struct nvkm_fifo_chan *chan;
 160         const struct nvkm_enum *en, *re, *cl, *sc;
 161         u32 trap[6], idx, inst;
 162         u8 st0, st1, st2, st3;
 163         unsigned long flags;
 164         int i;
 165
 166         idx = nvkm_rd32(device, 0x100c90);
 167         if (!(idx & 0x80000000))
 168                 return;
 169         idx &= 0x00ffffff;
 170
 171         for (i = 0; i < 6; i++) {
 172                 nvkm_wr32(device, 0x100c90, idx | i << 24);
 173                 trap[i] = nvkm_rd32(device, 0x100c94);
 174         }
 175         nvkm_wr32(device, 0x100c90, idx | 0x80000000);
 176
 177         /* decode status bits into something more useful */
 178         if (device->chipset  < 0xa3 ||
 179             device->chipset == 0xaa || device->chipset == 0xac) {
 180                 st0 = (trap[0] & 0x0000000f) >> 0;
 181                 st1 = (trap[0] & 0x000000f0) >> 4;
 182                 st2 = (trap[0] & 0x00000f00) >> 8;
 183                 st3 = (trap[0] & 0x0000f000) >> 12;
 184         } else {
 185                 st0 = (trap[0] & 0x000000ff) >> 0;
 186                 st1 = (trap[0] & 0x0000ff00) >> 8;
 187                 st2 = (trap[0] & 0x00ff0000) >> 16;
 188                 st3 = (trap[0] & 0xff000000) >> 24;
 189         }
 190         inst = ((trap[2] << 16) | trap[1]) << 12;
 191
 192         en = nvkm_enum_find(vm_engine, st0);
 193         re = nvkm_enum_find(vm_fault , st1);
 194         cl = nvkm_enum_find(vm_client, st2);
 195         if      (cl && cl->data) sc = nvkm_enum_find(cl->data, st3);
 196         else if (en && en->data) sc = nvkm_enum_find(en->data, st3);
 197         else                     sc = NULL;
 198
 199         chan = nvkm_fifo_chan_inst(fifo, inst, &flags);
 200         nvkm_error(subdev, "trapped %s at %02x%04x%04x on channel %d [%08x %s] "
 201                            "engine %02x [%s] client %02x [%s] "
 202                            "subclient %02x [%s] reason %08x [%s]\n",
 203                    (trap[5] & 0x00000100) ? "read" : "write",
 204                    trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff,
 205                    chan ? chan->chid : -1, inst,
 206                    chan ? chan->object.client->name : "unknown",
 207                    st0, en ? en->name : "",
 208                    st2, cl ? cl->name : "", st3, sc ? sc->name : "",
 209                    st1, re ? re->name : "");
 210         nvkm_fifo_chan_put(fifo, flags, &chan);
 211 }
 212
 213 static int
 214 nv50_fb_oneinit(struct nvkm_fb *base)
 215 {
 216         struct nv50_fb *fb = nv50_fb(base);
 217         struct nvkm_device *device = fb->base.subdev.device;
 218
 219         fb->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
 220         if (fb->r100c08_page) {
 221                 fb->r100c08 = dma_map_page(device->dev, fb->r100c08_page, 0,
 222                                            PAGE_SIZE, DMA_BIDIRECTIONAL);
 223                 if (dma_mapping_error(device->dev, fb->r100c08))
 224                         return -EFAULT;
 225         }
 226
 227         return 0;
 228 }
 229
 230 static void
 231 nv50_fb_init(struct nvkm_fb *base)
 232 {
 233         struct nv50_fb *fb = nv50_fb(base);
 234         struct nvkm_device *device = fb->base.subdev.device;
 235
 236         /* Not a clue what this is exactly.  Without pointing it at a
 237          * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
 238          * cause IOMMU "read from address 0" errors (rh#561267)
 239          */
 240         nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8);
 241
 242         /* This is needed to get meaningful information from 100c90
 243          * on traps. No idea what these values mean exactly. */
 244         nvkm_wr32(device, 0x100c90, fb->func->trap);
 245 }
 246
 247 static u32
 248 nv50_fb_tags(struct nvkm_fb *base)
 249 {
 250         struct nv50_fb *fb = nv50_fb(base);
 251         if (fb->func->tags)
 252                 return fb->func->tags(&fb->base);
 253         return 0;
 254 }
 255
 256 static void *
 257 nv50_fb_dtor(struct nvkm_fb *base)
 258 {
 259         struct nv50_fb *fb = nv50_fb(base);
 260         struct nvkm_device *device = fb->base.subdev.device;
 261
 262         if (fb->r100c08_page) {
 263                 dma_unmap_page(device->dev, fb->r100c08, PAGE_SIZE,
 264                                DMA_BIDIRECTIONAL);
 265                 __free_page(fb->r100c08_page);
 266         }
 267
 268         return fb;
 269 }
 270
 271 static const struct nvkm_fb_func
 272 nv50_fb_ = {
 273         .dtor = nv50_fb_dtor,
 274         .tags = nv50_fb_tags,
 275         .oneinit = nv50_fb_oneinit,
 276         .init = nv50_fb_init,
 277         .intr = nv50_fb_intr,
 278         .ram_new = nv50_fb_ram_new,
 279         .memtype_valid = nv50_fb_memtype_valid,
 280 };
 281
 282 int
 283 nv50_fb_new_(const struct nv50_fb_func *func, struct nvkm_device *device,
 284              int index, struct nvkm_fb **pfb)
 285 {
 286         struct nv50_fb *fb;
 287
 288         if (!(fb = kzalloc(sizeof(*fb), GFP_KERNEL)))
 289                 return -ENOMEM;
 290         nvkm_fb_ctor(&nv50_fb_, device, index, &fb->base);
 291         fb->func = func;
 292         *pfb = &fb->base;
 293
 294         return 0;
 295 }
 296
 297 static const struct nv50_fb_func
 298 nv50_fb = {
 299         .ram_new = nv50_ram_new,
 300         .tags = nv20_fb_tags,
 301         .trap = 0x000707ff,
 302 };
 303
 304 int
 305 nv50_fb_new(struct nvkm_device *device, int index, struct nvkm_fb **pfb)
 306 {
 307         return nv50_fb_new_(&nv50_fb, device, index, pfb);
 308 }