2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
28 #include <linux/power_supply.h>
29 #include <linux/hwmon.h>
30 #include <linux/hwmon-sysfs.h>
32 #define RADEON_IDLE_LOOP_MS 100
33 #define RADEON_RECLOCK_DELAY_MS 200
34 #define RADEON_WAIT_VBLANK_TIMEOUT 200
36 static const char *radeon_pm_state_type_name
[5] = {
44 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
);
45 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
);
46 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
);
47 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
);
48 static void radeon_pm_update_profile(struct radeon_device
*rdev
);
49 static void radeon_pm_set_clocks(struct radeon_device
*rdev
);
51 int radeon_pm_get_type_index(struct radeon_device
*rdev
,
52 enum radeon_pm_state_type ps_type
,
56 int found_instance
= -1;
58 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
59 if (rdev
->pm
.power_state
[i
].type
== ps_type
) {
61 if (found_instance
== instance
)
65 /* return default if no match */
66 return rdev
->pm
.default_power_state_index
;
69 void radeon_pm_acpi_event_handler(struct radeon_device
*rdev
)
71 if ((rdev
->pm
.pm_method
== PM_METHOD_DPM
) && rdev
->pm
.dpm_enabled
) {
72 mutex_lock(&rdev
->pm
.mutex
);
73 if (power_supply_is_system_supplied() > 0)
74 rdev
->pm
.dpm
.ac_power
= true;
76 rdev
->pm
.dpm
.ac_power
= false;
77 if (rdev
->family
== CHIP_ARUBA
) {
78 if (rdev
->asic
->dpm
.enable_bapm
)
79 radeon_dpm_enable_bapm(rdev
, rdev
->pm
.dpm
.ac_power
);
81 mutex_unlock(&rdev
->pm
.mutex
);
82 } else if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
83 if (rdev
->pm
.profile
== PM_PROFILE_AUTO
) {
84 mutex_lock(&rdev
->pm
.mutex
);
85 radeon_pm_update_profile(rdev
);
86 radeon_pm_set_clocks(rdev
);
87 mutex_unlock(&rdev
->pm
.mutex
);
92 static void radeon_pm_update_profile(struct radeon_device
*rdev
)
94 switch (rdev
->pm
.profile
) {
95 case PM_PROFILE_DEFAULT
:
96 rdev
->pm
.profile_index
= PM_PROFILE_DEFAULT_IDX
;
99 if (power_supply_is_system_supplied() > 0) {
100 if (rdev
->pm
.active_crtc_count
> 1)
101 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
103 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
105 if (rdev
->pm
.active_crtc_count
> 1)
106 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
108 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
112 if (rdev
->pm
.active_crtc_count
> 1)
113 rdev
->pm
.profile_index
= PM_PROFILE_LOW_MH_IDX
;
115 rdev
->pm
.profile_index
= PM_PROFILE_LOW_SH_IDX
;
118 if (rdev
->pm
.active_crtc_count
> 1)
119 rdev
->pm
.profile_index
= PM_PROFILE_MID_MH_IDX
;
121 rdev
->pm
.profile_index
= PM_PROFILE_MID_SH_IDX
;
123 case PM_PROFILE_HIGH
:
124 if (rdev
->pm
.active_crtc_count
> 1)
125 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_MH_IDX
;
127 rdev
->pm
.profile_index
= PM_PROFILE_HIGH_SH_IDX
;
131 if (rdev
->pm
.active_crtc_count
== 0) {
132 rdev
->pm
.requested_power_state_index
=
133 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_ps_idx
;
134 rdev
->pm
.requested_clock_mode_index
=
135 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_off_cm_idx
;
137 rdev
->pm
.requested_power_state_index
=
138 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_ps_idx
;
139 rdev
->pm
.requested_clock_mode_index
=
140 rdev
->pm
.profiles
[rdev
->pm
.profile_index
].dpms_on_cm_idx
;
144 static void radeon_unmap_vram_bos(struct radeon_device
*rdev
)
146 struct radeon_bo
*bo
, *n
;
148 if (list_empty(&rdev
->gem
.objects
))
151 list_for_each_entry_safe(bo
, n
, &rdev
->gem
.objects
, list
) {
152 if (bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
)
153 ttm_bo_unmap_virtual(&bo
->tbo
);
157 static void radeon_sync_with_vblank(struct radeon_device
*rdev
)
159 if (rdev
->pm
.active_crtcs
) {
160 rdev
->pm
.vblank_sync
= false;
162 rdev
->irq
.vblank_queue
, rdev
->pm
.vblank_sync
,
163 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT
));
167 static void radeon_set_power_state(struct radeon_device
*rdev
)
170 bool misc_after
= false;
172 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
173 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
176 if (radeon_gui_idle(rdev
)) {
177 sclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
178 clock_info
[rdev
->pm
.requested_clock_mode_index
].sclk
;
179 if (sclk
> rdev
->pm
.default_sclk
)
180 sclk
= rdev
->pm
.default_sclk
;
182 /* starting with BTC, there is one state that is used for both
183 * MH and SH. Difference is that we always use the high clock index for
186 if ((rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) &&
187 (rdev
->family
>= CHIP_BARTS
) &&
188 rdev
->pm
.active_crtc_count
&&
189 ((rdev
->pm
.profile_index
== PM_PROFILE_MID_MH_IDX
) ||
190 (rdev
->pm
.profile_index
== PM_PROFILE_LOW_MH_IDX
)))
191 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
192 clock_info
[rdev
->pm
.profiles
[PM_PROFILE_HIGH_MH_IDX
].dpms_on_cm_idx
].mclk
;
194 mclk
= rdev
->pm
.power_state
[rdev
->pm
.requested_power_state_index
].
195 clock_info
[rdev
->pm
.requested_clock_mode_index
].mclk
;
197 if (mclk
> rdev
->pm
.default_mclk
)
198 mclk
= rdev
->pm
.default_mclk
;
200 /* upvolt before raising clocks, downvolt after lowering clocks */
201 if (sclk
< rdev
->pm
.current_sclk
)
204 radeon_sync_with_vblank(rdev
);
206 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
207 if (!radeon_pm_in_vbl(rdev
))
211 radeon_pm_prepare(rdev
);
214 /* voltage, pcie lanes, etc.*/
215 radeon_pm_misc(rdev
);
217 /* set engine clock */
218 if (sclk
!= rdev
->pm
.current_sclk
) {
219 radeon_pm_debug_check_in_vbl(rdev
, false);
220 radeon_set_engine_clock(rdev
, sclk
);
221 radeon_pm_debug_check_in_vbl(rdev
, true);
222 rdev
->pm
.current_sclk
= sclk
;
223 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk
);
226 /* set memory clock */
227 if (rdev
->asic
->pm
.set_memory_clock
&& (mclk
!= rdev
->pm
.current_mclk
)) {
228 radeon_pm_debug_check_in_vbl(rdev
, false);
229 radeon_set_memory_clock(rdev
, mclk
);
230 radeon_pm_debug_check_in_vbl(rdev
, true);
231 rdev
->pm
.current_mclk
= mclk
;
232 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk
);
236 /* voltage, pcie lanes, etc.*/
237 radeon_pm_misc(rdev
);
239 radeon_pm_finish(rdev
);
241 rdev
->pm
.current_power_state_index
= rdev
->pm
.requested_power_state_index
;
242 rdev
->pm
.current_clock_mode_index
= rdev
->pm
.requested_clock_mode_index
;
244 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
247 static void radeon_pm_set_clocks(struct radeon_device
*rdev
)
251 /* no need to take locks, etc. if nothing's going to change */
252 if ((rdev
->pm
.requested_clock_mode_index
== rdev
->pm
.current_clock_mode_index
) &&
253 (rdev
->pm
.requested_power_state_index
== rdev
->pm
.current_power_state_index
))
256 down_write(&rdev
->pm
.mclk_lock
);
257 mutex_lock(&rdev
->ring_lock
);
259 /* wait for the rings to drain */
260 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
261 struct radeon_ring
*ring
= &rdev
->ring
[i
];
265 r
= radeon_fence_wait_empty(rdev
, i
);
267 /* needs a GPU reset dont reset here */
268 mutex_unlock(&rdev
->ring_lock
);
269 up_write(&rdev
->pm
.mclk_lock
);
274 radeon_unmap_vram_bos(rdev
);
276 if (rdev
->irq
.installed
) {
277 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
278 if (rdev
->pm
.active_crtcs
& (1 << i
)) {
279 /* This can fail if a modeset is in progress */
280 if (drm_vblank_get(rdev
->ddev
, i
) == 0)
281 rdev
->pm
.req_vblank
|= (1 << i
);
283 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n",
289 radeon_set_power_state(rdev
);
291 if (rdev
->irq
.installed
) {
292 for (i
= 0; i
< rdev
->num_crtc
; i
++) {
293 if (rdev
->pm
.req_vblank
& (1 << i
)) {
294 rdev
->pm
.req_vblank
&= ~(1 << i
);
295 drm_vblank_put(rdev
->ddev
, i
);
300 /* update display watermarks based on new power state */
301 radeon_update_bandwidth_info(rdev
);
302 if (rdev
->pm
.active_crtc_count
)
303 radeon_bandwidth_update(rdev
);
305 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
307 mutex_unlock(&rdev
->ring_lock
);
308 up_write(&rdev
->pm
.mclk_lock
);
311 static void radeon_pm_print_states(struct radeon_device
*rdev
)
314 struct radeon_power_state
*power_state
;
315 struct radeon_pm_clock_info
*clock_info
;
317 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev
->pm
.num_power_states
);
318 for (i
= 0; i
< rdev
->pm
.num_power_states
; i
++) {
319 power_state
= &rdev
->pm
.power_state
[i
];
320 DRM_DEBUG_DRIVER("State %d: %s\n", i
,
321 radeon_pm_state_type_name
[power_state
->type
]);
322 if (i
== rdev
->pm
.default_power_state_index
)
323 DRM_DEBUG_DRIVER("\tDefault");
324 if ((rdev
->flags
& RADEON_IS_PCIE
) && !(rdev
->flags
& RADEON_IS_IGP
))
325 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state
->pcie_lanes
);
326 if (power_state
->flags
& RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
)
327 DRM_DEBUG_DRIVER("\tSingle display only\n");
328 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state
->num_clock_modes
);
329 for (j
= 0; j
< power_state
->num_clock_modes
; j
++) {
330 clock_info
= &(power_state
->clock_info
[j
]);
331 if (rdev
->flags
& RADEON_IS_IGP
)
332 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
334 clock_info
->sclk
* 10);
336 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
338 clock_info
->sclk
* 10,
339 clock_info
->mclk
* 10,
340 clock_info
->voltage
.voltage
);
345 static ssize_t
radeon_get_pm_profile(struct device
*dev
,
346 struct device_attribute
*attr
,
349 struct drm_device
*ddev
= dev_get_drvdata(dev
);
350 struct radeon_device
*rdev
= ddev
->dev_private
;
351 int cp
= rdev
->pm
.profile
;
353 return snprintf(buf
, PAGE_SIZE
, "%s\n",
354 (cp
== PM_PROFILE_AUTO
) ? "auto" :
355 (cp
== PM_PROFILE_LOW
) ? "low" :
356 (cp
== PM_PROFILE_MID
) ? "mid" :
357 (cp
== PM_PROFILE_HIGH
) ? "high" : "default");
360 static ssize_t
radeon_set_pm_profile(struct device
*dev
,
361 struct device_attribute
*attr
,
365 struct drm_device
*ddev
= dev_get_drvdata(dev
);
366 struct radeon_device
*rdev
= ddev
->dev_private
;
368 /* Can't set profile when the card is off */
369 if ((rdev
->flags
& RADEON_IS_PX
) &&
370 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
373 mutex_lock(&rdev
->pm
.mutex
);
374 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
375 if (strncmp("default", buf
, strlen("default")) == 0)
376 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
377 else if (strncmp("auto", buf
, strlen("auto")) == 0)
378 rdev
->pm
.profile
= PM_PROFILE_AUTO
;
379 else if (strncmp("low", buf
, strlen("low")) == 0)
380 rdev
->pm
.profile
= PM_PROFILE_LOW
;
381 else if (strncmp("mid", buf
, strlen("mid")) == 0)
382 rdev
->pm
.profile
= PM_PROFILE_MID
;
383 else if (strncmp("high", buf
, strlen("high")) == 0)
384 rdev
->pm
.profile
= PM_PROFILE_HIGH
;
389 radeon_pm_update_profile(rdev
);
390 radeon_pm_set_clocks(rdev
);
395 mutex_unlock(&rdev
->pm
.mutex
);
400 static ssize_t
radeon_get_pm_method(struct device
*dev
,
401 struct device_attribute
*attr
,
404 struct drm_device
*ddev
= dev_get_drvdata(dev
);
405 struct radeon_device
*rdev
= ddev
->dev_private
;
406 int pm
= rdev
->pm
.pm_method
;
408 return snprintf(buf
, PAGE_SIZE
, "%s\n",
409 (pm
== PM_METHOD_DYNPM
) ? "dynpm" :
410 (pm
== PM_METHOD_PROFILE
) ? "profile" : "dpm");
413 static ssize_t
radeon_set_pm_method(struct device
*dev
,
414 struct device_attribute
*attr
,
418 struct drm_device
*ddev
= dev_get_drvdata(dev
);
419 struct radeon_device
*rdev
= ddev
->dev_private
;
421 /* Can't set method when the card is off */
422 if ((rdev
->flags
& RADEON_IS_PX
) &&
423 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
428 /* we don't support the legacy modes with dpm */
429 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
) {
434 if (strncmp("dynpm", buf
, strlen("dynpm")) == 0) {
435 mutex_lock(&rdev
->pm
.mutex
);
436 rdev
->pm
.pm_method
= PM_METHOD_DYNPM
;
437 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
438 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
439 mutex_unlock(&rdev
->pm
.mutex
);
440 } else if (strncmp("profile", buf
, strlen("profile")) == 0) {
441 mutex_lock(&rdev
->pm
.mutex
);
443 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
444 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
445 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
446 mutex_unlock(&rdev
->pm
.mutex
);
447 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
452 radeon_pm_compute_clocks(rdev
);
457 static ssize_t
radeon_get_dpm_state(struct device
*dev
,
458 struct device_attribute
*attr
,
461 struct drm_device
*ddev
= dev_get_drvdata(dev
);
462 struct radeon_device
*rdev
= ddev
->dev_private
;
463 enum radeon_pm_state_type pm
= rdev
->pm
.dpm
.user_state
;
465 return snprintf(buf
, PAGE_SIZE
, "%s\n",
466 (pm
== POWER_STATE_TYPE_BATTERY
) ? "battery" :
467 (pm
== POWER_STATE_TYPE_BALANCED
) ? "balanced" : "performance");
470 static ssize_t
radeon_set_dpm_state(struct device
*dev
,
471 struct device_attribute
*attr
,
475 struct drm_device
*ddev
= dev_get_drvdata(dev
);
476 struct radeon_device
*rdev
= ddev
->dev_private
;
478 mutex_lock(&rdev
->pm
.mutex
);
479 if (strncmp("battery", buf
, strlen("battery")) == 0)
480 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BATTERY
;
481 else if (strncmp("balanced", buf
, strlen("balanced")) == 0)
482 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
483 else if (strncmp("performance", buf
, strlen("performance")) == 0)
484 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_PERFORMANCE
;
486 mutex_unlock(&rdev
->pm
.mutex
);
490 mutex_unlock(&rdev
->pm
.mutex
);
492 /* Can't set dpm state when the card is off */
493 if (!(rdev
->flags
& RADEON_IS_PX
) ||
494 (ddev
->switch_power_state
== DRM_SWITCH_POWER_ON
))
495 radeon_pm_compute_clocks(rdev
);
501 static ssize_t
radeon_get_dpm_forced_performance_level(struct device
*dev
,
502 struct device_attribute
*attr
,
505 struct drm_device
*ddev
= dev_get_drvdata(dev
);
506 struct radeon_device
*rdev
= ddev
->dev_private
;
507 enum radeon_dpm_forced_level level
= rdev
->pm
.dpm
.forced_level
;
509 if ((rdev
->flags
& RADEON_IS_PX
) &&
510 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
511 return snprintf(buf
, PAGE_SIZE
, "off\n");
513 return snprintf(buf
, PAGE_SIZE
, "%s\n",
514 (level
== RADEON_DPM_FORCED_LEVEL_AUTO
) ? "auto" :
515 (level
== RADEON_DPM_FORCED_LEVEL_LOW
) ? "low" : "high");
518 static ssize_t
radeon_set_dpm_forced_performance_level(struct device
*dev
,
519 struct device_attribute
*attr
,
523 struct drm_device
*ddev
= dev_get_drvdata(dev
);
524 struct radeon_device
*rdev
= ddev
->dev_private
;
525 enum radeon_dpm_forced_level level
;
528 /* Can't force performance level when the card is off */
529 if ((rdev
->flags
& RADEON_IS_PX
) &&
530 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
533 mutex_lock(&rdev
->pm
.mutex
);
534 if (strncmp("low", buf
, strlen("low")) == 0) {
535 level
= RADEON_DPM_FORCED_LEVEL_LOW
;
536 } else if (strncmp("high", buf
, strlen("high")) == 0) {
537 level
= RADEON_DPM_FORCED_LEVEL_HIGH
;
538 } else if (strncmp("auto", buf
, strlen("auto")) == 0) {
539 level
= RADEON_DPM_FORCED_LEVEL_AUTO
;
544 if (rdev
->asic
->dpm
.force_performance_level
) {
545 if (rdev
->pm
.dpm
.thermal_active
) {
549 ret
= radeon_dpm_force_performance_level(rdev
, level
);
554 mutex_unlock(&rdev
->pm
.mutex
);
559 static ssize_t
radeon_hwmon_get_pwm1_enable(struct device
*dev
,
560 struct device_attribute
*attr
,
563 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
566 if (rdev
->asic
->dpm
.fan_ctrl_get_mode
)
567 pwm_mode
= rdev
->asic
->dpm
.fan_ctrl_get_mode(rdev
);
569 /* never 0 (full-speed), fuse or smc-controlled always */
570 return sprintf(buf
, "%i\n", pwm_mode
== FDO_PWM_MODE_STATIC
? 1 : 2);
573 static ssize_t
radeon_hwmon_set_pwm1_enable(struct device
*dev
,
574 struct device_attribute
*attr
,
578 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
582 if(!rdev
->asic
->dpm
.fan_ctrl_set_mode
)
585 err
= kstrtoint(buf
, 10, &value
);
590 case 1: /* manual, percent-based */
591 rdev
->asic
->dpm
.fan_ctrl_set_mode(rdev
, FDO_PWM_MODE_STATIC
);
593 default: /* disable */
594 rdev
->asic
->dpm
.fan_ctrl_set_mode(rdev
, 0);
601 static ssize_t
radeon_hwmon_get_pwm1_min(struct device
*dev
,
602 struct device_attribute
*attr
,
605 return sprintf(buf
, "%i\n", 0);
608 static ssize_t
radeon_hwmon_get_pwm1_max(struct device
*dev
,
609 struct device_attribute
*attr
,
612 return sprintf(buf
, "%i\n", 255);
615 static ssize_t
radeon_hwmon_set_pwm1(struct device
*dev
,
616 struct device_attribute
*attr
,
617 const char *buf
, size_t count
)
619 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
623 err
= kstrtou32(buf
, 10, &value
);
627 value
= (value
* 100) / 255;
629 err
= rdev
->asic
->dpm
.set_fan_speed_percent(rdev
, value
);
636 static ssize_t
radeon_hwmon_get_pwm1(struct device
*dev
,
637 struct device_attribute
*attr
,
640 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
644 err
= rdev
->asic
->dpm
.get_fan_speed_percent(rdev
, &speed
);
648 speed
= (speed
* 255) / 100;
650 return sprintf(buf
, "%i\n", speed
);
653 static DEVICE_ATTR(power_profile
, S_IRUGO
| S_IWUSR
, radeon_get_pm_profile
, radeon_set_pm_profile
);
654 static DEVICE_ATTR(power_method
, S_IRUGO
| S_IWUSR
, radeon_get_pm_method
, radeon_set_pm_method
);
655 static DEVICE_ATTR(power_dpm_state
, S_IRUGO
| S_IWUSR
, radeon_get_dpm_state
, radeon_set_dpm_state
);
656 static DEVICE_ATTR(power_dpm_force_performance_level
, S_IRUGO
| S_IWUSR
,
657 radeon_get_dpm_forced_performance_level
,
658 radeon_set_dpm_forced_performance_level
);
660 static ssize_t
radeon_hwmon_show_temp(struct device
*dev
,
661 struct device_attribute
*attr
,
664 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
665 struct drm_device
*ddev
= rdev
->ddev
;
668 /* Can't get temperature when the card is off */
669 if ((rdev
->flags
& RADEON_IS_PX
) &&
670 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
))
673 if (rdev
->asic
->pm
.get_temperature
)
674 temp
= radeon_get_temperature(rdev
);
678 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
681 static ssize_t
radeon_hwmon_show_temp_thresh(struct device
*dev
,
682 struct device_attribute
*attr
,
685 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
686 int hyst
= to_sensor_dev_attr(attr
)->index
;
690 temp
= rdev
->pm
.dpm
.thermal
.min_temp
;
692 temp
= rdev
->pm
.dpm
.thermal
.max_temp
;
694 return snprintf(buf
, PAGE_SIZE
, "%d\n", temp
);
697 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, radeon_hwmon_show_temp
, NULL
, 0);
698 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, radeon_hwmon_show_temp_thresh
, NULL
, 0);
699 static SENSOR_DEVICE_ATTR(temp1_crit_hyst
, S_IRUGO
, radeon_hwmon_show_temp_thresh
, NULL
, 1);
700 static SENSOR_DEVICE_ATTR(pwm1
, S_IRUGO
| S_IWUSR
, radeon_hwmon_get_pwm1
, radeon_hwmon_set_pwm1
, 0);
701 static SENSOR_DEVICE_ATTR(pwm1_enable
, S_IRUGO
| S_IWUSR
, radeon_hwmon_get_pwm1_enable
, radeon_hwmon_set_pwm1_enable
, 0);
702 static SENSOR_DEVICE_ATTR(pwm1_min
, S_IRUGO
, radeon_hwmon_get_pwm1_min
, NULL
, 0);
703 static SENSOR_DEVICE_ATTR(pwm1_max
, S_IRUGO
, radeon_hwmon_get_pwm1_max
, NULL
, 0);
706 static struct attribute
*hwmon_attributes
[] = {
707 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
708 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
709 &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
,
710 &sensor_dev_attr_pwm1
.dev_attr
.attr
,
711 &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
,
712 &sensor_dev_attr_pwm1_min
.dev_attr
.attr
,
713 &sensor_dev_attr_pwm1_max
.dev_attr
.attr
,
717 static umode_t
hwmon_attributes_visible(struct kobject
*kobj
,
718 struct attribute
*attr
, int index
)
720 struct device
*dev
= kobj_to_dev(kobj
);
721 struct radeon_device
*rdev
= dev_get_drvdata(dev
);
722 umode_t effective_mode
= attr
->mode
;
724 /* Skip attributes if DPM is not enabled */
725 if (rdev
->pm
.pm_method
!= PM_METHOD_DPM
&&
726 (attr
== &sensor_dev_attr_temp1_crit
.dev_attr
.attr
||
727 attr
== &sensor_dev_attr_temp1_crit_hyst
.dev_attr
.attr
||
728 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
729 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
730 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
731 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
734 /* Skip fan attributes if fan is not present */
735 if (rdev
->pm
.no_fan
&&
736 (attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
||
737 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
||
738 attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
739 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
742 /* mask fan attributes if we have no bindings for this asic to expose */
743 if ((!rdev
->asic
->dpm
.get_fan_speed_percent
&&
744 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't query fan */
745 (!rdev
->asic
->dpm
.fan_ctrl_get_mode
&&
746 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't query state */
747 effective_mode
&= ~S_IRUGO
;
749 if ((!rdev
->asic
->dpm
.set_fan_speed_percent
&&
750 attr
== &sensor_dev_attr_pwm1
.dev_attr
.attr
) || /* can't manage fan */
751 (!rdev
->asic
->dpm
.fan_ctrl_set_mode
&&
752 attr
== &sensor_dev_attr_pwm1_enable
.dev_attr
.attr
)) /* can't manage state */
753 effective_mode
&= ~S_IWUSR
;
755 /* hide max/min values if we can't both query and manage the fan */
756 if ((!rdev
->asic
->dpm
.set_fan_speed_percent
&&
757 !rdev
->asic
->dpm
.get_fan_speed_percent
) &&
758 (attr
== &sensor_dev_attr_pwm1_max
.dev_attr
.attr
||
759 attr
== &sensor_dev_attr_pwm1_min
.dev_attr
.attr
))
762 return effective_mode
;
765 static const struct attribute_group hwmon_attrgroup
= {
766 .attrs
= hwmon_attributes
,
767 .is_visible
= hwmon_attributes_visible
,
770 static const struct attribute_group
*hwmon_groups
[] = {
775 static int radeon_hwmon_init(struct radeon_device
*rdev
)
779 switch (rdev
->pm
.int_thermal_type
) {
780 case THERMAL_TYPE_RV6XX
:
781 case THERMAL_TYPE_RV770
:
782 case THERMAL_TYPE_EVERGREEN
:
783 case THERMAL_TYPE_NI
:
784 case THERMAL_TYPE_SUMO
:
785 case THERMAL_TYPE_SI
:
786 case THERMAL_TYPE_CI
:
787 case THERMAL_TYPE_KV
:
788 if (rdev
->asic
->pm
.get_temperature
== NULL
)
790 rdev
->pm
.int_hwmon_dev
= hwmon_device_register_with_groups(rdev
->dev
,
793 if (IS_ERR(rdev
->pm
.int_hwmon_dev
)) {
794 err
= PTR_ERR(rdev
->pm
.int_hwmon_dev
);
796 "Unable to register hwmon device: %d\n", err
);
806 static void radeon_hwmon_fini(struct radeon_device
*rdev
)
808 if (rdev
->pm
.int_hwmon_dev
)
809 hwmon_device_unregister(rdev
->pm
.int_hwmon_dev
);
812 static void radeon_dpm_thermal_work_handler(struct work_struct
*work
)
814 struct radeon_device
*rdev
=
815 container_of(work
, struct radeon_device
,
816 pm
.dpm
.thermal
.work
);
817 /* switch to the thermal state */
818 enum radeon_pm_state_type dpm_state
= POWER_STATE_TYPE_INTERNAL_THERMAL
;
820 if (!rdev
->pm
.dpm_enabled
)
823 if (rdev
->asic
->pm
.get_temperature
) {
824 int temp
= radeon_get_temperature(rdev
);
826 if (temp
< rdev
->pm
.dpm
.thermal
.min_temp
)
827 /* switch back the user state */
828 dpm_state
= rdev
->pm
.dpm
.user_state
;
830 if (rdev
->pm
.dpm
.thermal
.high_to_low
)
831 /* switch back the user state */
832 dpm_state
= rdev
->pm
.dpm
.user_state
;
834 mutex_lock(&rdev
->pm
.mutex
);
835 if (dpm_state
== POWER_STATE_TYPE_INTERNAL_THERMAL
)
836 rdev
->pm
.dpm
.thermal_active
= true;
838 rdev
->pm
.dpm
.thermal_active
= false;
839 rdev
->pm
.dpm
.state
= dpm_state
;
840 mutex_unlock(&rdev
->pm
.mutex
);
842 radeon_pm_compute_clocks(rdev
);
845 static bool radeon_dpm_single_display(struct radeon_device
*rdev
)
847 bool single_display
= (rdev
->pm
.dpm
.new_active_crtc_count
< 2) ?
850 /* check if the vblank period is too short to adjust the mclk */
851 if (single_display
&& rdev
->asic
->dpm
.vblank_too_short
) {
852 if (radeon_dpm_vblank_too_short(rdev
))
853 single_display
= false;
856 /* 120hz tends to be problematic even if they are under the
859 if (single_display
&& (r600_dpm_get_vrefresh(rdev
) >= 120))
860 single_display
= false;
862 return single_display
;
865 static struct radeon_ps
*radeon_dpm_pick_power_state(struct radeon_device
*rdev
,
866 enum radeon_pm_state_type dpm_state
)
869 struct radeon_ps
*ps
;
871 bool single_display
= radeon_dpm_single_display(rdev
);
873 /* certain older asics have a separare 3D performance state,
874 * so try that first if the user selected performance
876 if (dpm_state
== POWER_STATE_TYPE_PERFORMANCE
)
877 dpm_state
= POWER_STATE_TYPE_INTERNAL_3DPERF
;
878 /* balanced states don't exist at the moment */
879 if (dpm_state
== POWER_STATE_TYPE_BALANCED
)
880 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
883 /* Pick the best power state based on current conditions */
884 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
885 ps
= &rdev
->pm
.dpm
.ps
[i
];
886 ui_class
= ps
->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK
;
889 case POWER_STATE_TYPE_BATTERY
:
890 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
) {
891 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
898 case POWER_STATE_TYPE_BALANCED
:
899 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
) {
900 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
907 case POWER_STATE_TYPE_PERFORMANCE
:
908 if (ui_class
== ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
) {
909 if (ps
->caps
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
) {
916 /* internal states */
917 case POWER_STATE_TYPE_INTERNAL_UVD
:
918 if (rdev
->pm
.dpm
.uvd_ps
)
919 return rdev
->pm
.dpm
.uvd_ps
;
922 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
923 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE
)
926 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
927 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE
)
930 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
931 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE
)
934 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
935 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_MVC
)
938 case POWER_STATE_TYPE_INTERNAL_BOOT
:
939 return rdev
->pm
.dpm
.boot_ps
;
940 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
941 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_THERMAL
)
944 case POWER_STATE_TYPE_INTERNAL_ACPI
:
945 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_ACPI
)
948 case POWER_STATE_TYPE_INTERNAL_ULV
:
949 if (ps
->class2
& ATOM_PPLIB_CLASSIFICATION2_ULV
)
952 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
953 if (ps
->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
960 /* use a fallback state if we didn't match */
962 case POWER_STATE_TYPE_INTERNAL_UVD_SD
:
963 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
965 case POWER_STATE_TYPE_INTERNAL_UVD_HD
:
966 case POWER_STATE_TYPE_INTERNAL_UVD_HD2
:
967 case POWER_STATE_TYPE_INTERNAL_UVD_MVC
:
968 if (rdev
->pm
.dpm
.uvd_ps
) {
969 return rdev
->pm
.dpm
.uvd_ps
;
971 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
974 case POWER_STATE_TYPE_INTERNAL_THERMAL
:
975 dpm_state
= POWER_STATE_TYPE_INTERNAL_ACPI
;
977 case POWER_STATE_TYPE_INTERNAL_ACPI
:
978 dpm_state
= POWER_STATE_TYPE_BATTERY
;
980 case POWER_STATE_TYPE_BATTERY
:
981 case POWER_STATE_TYPE_BALANCED
:
982 case POWER_STATE_TYPE_INTERNAL_3DPERF
:
983 dpm_state
= POWER_STATE_TYPE_PERFORMANCE
;
992 static void radeon_dpm_change_power_state_locked(struct radeon_device
*rdev
)
995 struct radeon_ps
*ps
;
996 enum radeon_pm_state_type dpm_state
;
998 bool single_display
= radeon_dpm_single_display(rdev
);
1000 /* if dpm init failed */
1001 if (!rdev
->pm
.dpm_enabled
)
1004 if (rdev
->pm
.dpm
.user_state
!= rdev
->pm
.dpm
.state
) {
1005 /* add other state override checks here */
1006 if ((!rdev
->pm
.dpm
.thermal_active
) &&
1007 (!rdev
->pm
.dpm
.uvd_active
))
1008 rdev
->pm
.dpm
.state
= rdev
->pm
.dpm
.user_state
;
1010 dpm_state
= rdev
->pm
.dpm
.state
;
1012 ps
= radeon_dpm_pick_power_state(rdev
, dpm_state
);
1014 rdev
->pm
.dpm
.requested_ps
= ps
;
1018 /* no need to reprogram if nothing changed unless we are on BTC+ */
1019 if (rdev
->pm
.dpm
.current_ps
== rdev
->pm
.dpm
.requested_ps
) {
1020 /* vce just modifies an existing state so force a change */
1021 if (ps
->vce_active
!= rdev
->pm
.dpm
.vce_active
)
1023 /* user has made a display change (such as timing) */
1024 if (rdev
->pm
.dpm
.single_display
!= single_display
)
1026 if ((rdev
->family
< CHIP_BARTS
) || (rdev
->flags
& RADEON_IS_IGP
)) {
1027 /* for pre-BTC and APUs if the num crtcs changed but state is the same,
1028 * all we need to do is update the display configuration.
1030 if (rdev
->pm
.dpm
.new_active_crtcs
!= rdev
->pm
.dpm
.current_active_crtcs
) {
1031 /* update display watermarks based on new power state */
1032 radeon_bandwidth_update(rdev
);
1033 /* update displays */
1034 radeon_dpm_display_configuration_changed(rdev
);
1035 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
1036 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
1040 /* for BTC+ if the num crtcs hasn't changed and state is the same,
1041 * nothing to do, if the num crtcs is > 1 and state is the same,
1042 * update display configuration.
1044 if (rdev
->pm
.dpm
.new_active_crtcs
==
1045 rdev
->pm
.dpm
.current_active_crtcs
) {
1048 if ((rdev
->pm
.dpm
.current_active_crtc_count
> 1) &&
1049 (rdev
->pm
.dpm
.new_active_crtc_count
> 1)) {
1050 /* update display watermarks based on new power state */
1051 radeon_bandwidth_update(rdev
);
1052 /* update displays */
1053 radeon_dpm_display_configuration_changed(rdev
);
1054 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
1055 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
1063 if (radeon_dpm
== 1) {
1064 printk("switching from power state:\n");
1065 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.current_ps
);
1066 printk("switching to power state:\n");
1067 radeon_dpm_print_power_state(rdev
, rdev
->pm
.dpm
.requested_ps
);
1070 down_write(&rdev
->pm
.mclk_lock
);
1071 mutex_lock(&rdev
->ring_lock
);
1073 /* update whether vce is active */
1074 ps
->vce_active
= rdev
->pm
.dpm
.vce_active
;
1076 ret
= radeon_dpm_pre_set_power_state(rdev
);
1080 /* update display watermarks based on new power state */
1081 radeon_bandwidth_update(rdev
);
1083 /* wait for the rings to drain */
1084 for (i
= 0; i
< RADEON_NUM_RINGS
; i
++) {
1085 struct radeon_ring
*ring
= &rdev
->ring
[i
];
1087 radeon_fence_wait_empty(rdev
, i
);
1090 /* program the new power state */
1091 radeon_dpm_set_power_state(rdev
);
1093 /* update current power state */
1094 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
;
1096 radeon_dpm_post_set_power_state(rdev
);
1098 /* update displays */
1099 radeon_dpm_display_configuration_changed(rdev
);
1101 rdev
->pm
.dpm
.current_active_crtcs
= rdev
->pm
.dpm
.new_active_crtcs
;
1102 rdev
->pm
.dpm
.current_active_crtc_count
= rdev
->pm
.dpm
.new_active_crtc_count
;
1103 rdev
->pm
.dpm
.single_display
= single_display
;
1105 if (rdev
->asic
->dpm
.force_performance_level
) {
1106 if (rdev
->pm
.dpm
.thermal_active
) {
1107 enum radeon_dpm_forced_level level
= rdev
->pm
.dpm
.forced_level
;
1108 /* force low perf level for thermal */
1109 radeon_dpm_force_performance_level(rdev
, RADEON_DPM_FORCED_LEVEL_LOW
);
1110 /* save the user's level */
1111 rdev
->pm
.dpm
.forced_level
= level
;
1113 /* otherwise, user selected level */
1114 radeon_dpm_force_performance_level(rdev
, rdev
->pm
.dpm
.forced_level
);
1119 mutex_unlock(&rdev
->ring_lock
);
1120 up_write(&rdev
->pm
.mclk_lock
);
1123 void radeon_dpm_enable_uvd(struct radeon_device
*rdev
, bool enable
)
1125 enum radeon_pm_state_type dpm_state
;
1127 if (rdev
->asic
->dpm
.powergate_uvd
) {
1128 mutex_lock(&rdev
->pm
.mutex
);
1129 /* don't powergate anything if we
1130 have active but pause streams */
1131 enable
|= rdev
->pm
.dpm
.sd
> 0;
1132 enable
|= rdev
->pm
.dpm
.hd
> 0;
1133 /* enable/disable UVD */
1134 radeon_dpm_powergate_uvd(rdev
, !enable
);
1135 mutex_unlock(&rdev
->pm
.mutex
);
1138 mutex_lock(&rdev
->pm
.mutex
);
1139 rdev
->pm
.dpm
.uvd_active
= true;
1140 /* disable this for now */
1142 if ((rdev
->pm
.dpm
.sd
== 1) && (rdev
->pm
.dpm
.hd
== 0))
1143 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_SD
;
1144 else if ((rdev
->pm
.dpm
.sd
== 2) && (rdev
->pm
.dpm
.hd
== 0))
1145 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
1146 else if ((rdev
->pm
.dpm
.sd
== 0) && (rdev
->pm
.dpm
.hd
== 1))
1147 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD
;
1148 else if ((rdev
->pm
.dpm
.sd
== 0) && (rdev
->pm
.dpm
.hd
== 2))
1149 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD_HD2
;
1152 dpm_state
= POWER_STATE_TYPE_INTERNAL_UVD
;
1153 rdev
->pm
.dpm
.state
= dpm_state
;
1154 mutex_unlock(&rdev
->pm
.mutex
);
1156 mutex_lock(&rdev
->pm
.mutex
);
1157 rdev
->pm
.dpm
.uvd_active
= false;
1158 mutex_unlock(&rdev
->pm
.mutex
);
1161 radeon_pm_compute_clocks(rdev
);
1165 void radeon_dpm_enable_vce(struct radeon_device
*rdev
, bool enable
)
1168 mutex_lock(&rdev
->pm
.mutex
);
1169 rdev
->pm
.dpm
.vce_active
= true;
1170 /* XXX select vce level based on ring/task */
1171 rdev
->pm
.dpm
.vce_level
= RADEON_VCE_LEVEL_AC_ALL
;
1172 mutex_unlock(&rdev
->pm
.mutex
);
1174 mutex_lock(&rdev
->pm
.mutex
);
1175 rdev
->pm
.dpm
.vce_active
= false;
1176 mutex_unlock(&rdev
->pm
.mutex
);
1179 radeon_pm_compute_clocks(rdev
);
1182 static void radeon_pm_suspend_old(struct radeon_device
*rdev
)
1184 mutex_lock(&rdev
->pm
.mutex
);
1185 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1186 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
)
1187 rdev
->pm
.dynpm_state
= DYNPM_STATE_SUSPENDED
;
1189 mutex_unlock(&rdev
->pm
.mutex
);
1191 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
1194 static void radeon_pm_suspend_dpm(struct radeon_device
*rdev
)
1196 mutex_lock(&rdev
->pm
.mutex
);
1198 radeon_dpm_disable(rdev
);
1199 /* reset the power state */
1200 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
1201 rdev
->pm
.dpm_enabled
= false;
1202 mutex_unlock(&rdev
->pm
.mutex
);
1205 void radeon_pm_suspend(struct radeon_device
*rdev
)
1207 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1208 radeon_pm_suspend_dpm(rdev
);
1210 radeon_pm_suspend_old(rdev
);
1213 static void radeon_pm_resume_old(struct radeon_device
*rdev
)
1215 /* set up the default clocks if the MC ucode is loaded */
1216 if ((rdev
->family
>= CHIP_BARTS
) &&
1217 (rdev
->family
<= CHIP_CAYMAN
) &&
1219 if (rdev
->pm
.default_vddc
)
1220 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1221 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1222 if (rdev
->pm
.default_vddci
)
1223 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1224 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1225 if (rdev
->pm
.default_sclk
)
1226 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1227 if (rdev
->pm
.default_mclk
)
1228 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1230 /* asic init will reset the default power state */
1231 mutex_lock(&rdev
->pm
.mutex
);
1232 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
1233 rdev
->pm
.current_clock_mode_index
= 0;
1234 rdev
->pm
.current_sclk
= rdev
->pm
.default_sclk
;
1235 rdev
->pm
.current_mclk
= rdev
->pm
.default_mclk
;
1236 if (rdev
->pm
.power_state
) {
1237 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
1238 rdev
->pm
.current_vddci
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.vddci
;
1240 if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
1241 && rdev
->pm
.dynpm_state
== DYNPM_STATE_SUSPENDED
) {
1242 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1243 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1244 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1246 mutex_unlock(&rdev
->pm
.mutex
);
1247 radeon_pm_compute_clocks(rdev
);
1250 static void radeon_pm_resume_dpm(struct radeon_device
*rdev
)
1254 /* asic init will reset to the boot state */
1255 mutex_lock(&rdev
->pm
.mutex
);
1256 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
1257 radeon_dpm_setup_asic(rdev
);
1258 ret
= radeon_dpm_enable(rdev
);
1259 mutex_unlock(&rdev
->pm
.mutex
);
1261 goto dpm_resume_fail
;
1262 rdev
->pm
.dpm_enabled
= true;
1266 DRM_ERROR("radeon: dpm resume failed\n");
1267 if ((rdev
->family
>= CHIP_BARTS
) &&
1268 (rdev
->family
<= CHIP_CAYMAN
) &&
1270 if (rdev
->pm
.default_vddc
)
1271 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1272 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1273 if (rdev
->pm
.default_vddci
)
1274 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1275 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1276 if (rdev
->pm
.default_sclk
)
1277 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1278 if (rdev
->pm
.default_mclk
)
1279 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1283 void radeon_pm_resume(struct radeon_device
*rdev
)
1285 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1286 radeon_pm_resume_dpm(rdev
);
1288 radeon_pm_resume_old(rdev
);
1291 static int radeon_pm_init_old(struct radeon_device
*rdev
)
1295 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
1296 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
1297 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1298 rdev
->pm
.dynpm_can_upclock
= true;
1299 rdev
->pm
.dynpm_can_downclock
= true;
1300 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
1301 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
1302 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
1303 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
1304 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
1307 if (rdev
->is_atom_bios
)
1308 radeon_atombios_get_power_modes(rdev
);
1310 radeon_combios_get_power_modes(rdev
);
1311 radeon_pm_print_states(rdev
);
1312 radeon_pm_init_profile(rdev
);
1313 /* set up the default clocks if the MC ucode is loaded */
1314 if ((rdev
->family
>= CHIP_BARTS
) &&
1315 (rdev
->family
<= CHIP_CAYMAN
) &&
1317 if (rdev
->pm
.default_vddc
)
1318 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1319 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1320 if (rdev
->pm
.default_vddci
)
1321 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1322 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1323 if (rdev
->pm
.default_sclk
)
1324 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1325 if (rdev
->pm
.default_mclk
)
1326 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1330 /* set up the internal thermal sensor if applicable */
1331 ret
= radeon_hwmon_init(rdev
);
1335 INIT_DELAYED_WORK(&rdev
->pm
.dynpm_idle_work
, radeon_dynpm_idle_work_handler
);
1337 if (rdev
->pm
.num_power_states
> 1) {
1338 if (radeon_debugfs_pm_init(rdev
)) {
1339 DRM_ERROR("Failed to register debugfs file for PM!\n");
1342 DRM_INFO("radeon: power management initialized\n");
1348 static void radeon_dpm_print_power_states(struct radeon_device
*rdev
)
1352 for (i
= 0; i
< rdev
->pm
.dpm
.num_ps
; i
++) {
1353 printk("== power state %d ==\n", i
);
1354 radeon_dpm_print_power_state(rdev
, &rdev
->pm
.dpm
.ps
[i
]);
1358 static int radeon_pm_init_dpm(struct radeon_device
*rdev
)
1362 /* default to balanced state */
1363 rdev
->pm
.dpm
.state
= POWER_STATE_TYPE_BALANCED
;
1364 rdev
->pm
.dpm
.user_state
= POWER_STATE_TYPE_BALANCED
;
1365 rdev
->pm
.dpm
.forced_level
= RADEON_DPM_FORCED_LEVEL_AUTO
;
1366 rdev
->pm
.default_sclk
= rdev
->clock
.default_sclk
;
1367 rdev
->pm
.default_mclk
= rdev
->clock
.default_mclk
;
1368 rdev
->pm
.current_sclk
= rdev
->clock
.default_sclk
;
1369 rdev
->pm
.current_mclk
= rdev
->clock
.default_mclk
;
1370 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_NONE
;
1372 if (rdev
->bios
&& rdev
->is_atom_bios
)
1373 radeon_atombios_get_power_modes(rdev
);
1377 /* set up the internal thermal sensor if applicable */
1378 ret
= radeon_hwmon_init(rdev
);
1382 INIT_WORK(&rdev
->pm
.dpm
.thermal
.work
, radeon_dpm_thermal_work_handler
);
1383 mutex_lock(&rdev
->pm
.mutex
);
1384 radeon_dpm_init(rdev
);
1385 rdev
->pm
.dpm
.current_ps
= rdev
->pm
.dpm
.requested_ps
= rdev
->pm
.dpm
.boot_ps
;
1386 if (radeon_dpm
== 1)
1387 radeon_dpm_print_power_states(rdev
);
1388 radeon_dpm_setup_asic(rdev
);
1389 ret
= radeon_dpm_enable(rdev
);
1390 mutex_unlock(&rdev
->pm
.mutex
);
1393 rdev
->pm
.dpm_enabled
= true;
1395 if (radeon_debugfs_pm_init(rdev
)) {
1396 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1399 DRM_INFO("radeon: dpm initialized\n");
1404 rdev
->pm
.dpm_enabled
= false;
1405 if ((rdev
->family
>= CHIP_BARTS
) &&
1406 (rdev
->family
<= CHIP_CAYMAN
) &&
1408 if (rdev
->pm
.default_vddc
)
1409 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddc
,
1410 SET_VOLTAGE_TYPE_ASIC_VDDC
);
1411 if (rdev
->pm
.default_vddci
)
1412 radeon_atom_set_voltage(rdev
, rdev
->pm
.default_vddci
,
1413 SET_VOLTAGE_TYPE_ASIC_VDDCI
);
1414 if (rdev
->pm
.default_sclk
)
1415 radeon_set_engine_clock(rdev
, rdev
->pm
.default_sclk
);
1416 if (rdev
->pm
.default_mclk
)
1417 radeon_set_memory_clock(rdev
, rdev
->pm
.default_mclk
);
1419 DRM_ERROR("radeon: dpm initialization failed\n");
1423 struct radeon_dpm_quirk
{
1430 /* cards with dpm stability problems */
1431 static struct radeon_dpm_quirk radeon_dpm_quirk_list
[] = {
1432 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */
1433 { PCI_VENDOR_ID_ATI
, 0x6759, 0x1682, 0x3195 },
1434 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */
1435 { PCI_VENDOR_ID_ATI
, 0x6840, 0x1179, 0xfb81 },
1439 int radeon_pm_init(struct radeon_device
*rdev
)
1441 struct radeon_dpm_quirk
*p
= radeon_dpm_quirk_list
;
1442 bool disable_dpm
= false;
1444 /* Apply dpm quirks */
1445 while (p
&& p
->chip_device
!= 0) {
1446 if (rdev
->pdev
->vendor
== p
->chip_vendor
&&
1447 rdev
->pdev
->device
== p
->chip_device
&&
1448 rdev
->pdev
->subsystem_vendor
== p
->subsys_vendor
&&
1449 rdev
->pdev
->subsystem_device
== p
->subsys_device
) {
1456 /* enable dpm on rv6xx+ */
1457 switch (rdev
->family
) {
1466 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1468 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1469 else if ((rdev
->family
>= CHIP_RV770
) &&
1470 (!(rdev
->flags
& RADEON_IS_IGP
)) &&
1472 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1473 else if (radeon_dpm
== 1)
1474 rdev
->pm
.pm_method
= PM_METHOD_DPM
;
1476 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1504 /* DPM requires the RLC, RV770+ dGPU requires SMC */
1506 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1507 else if ((rdev
->family
>= CHIP_RV770
) &&
1508 (!(rdev
->flags
& RADEON_IS_IGP
)) &&
1510 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1511 else if (disable_dpm
&& (radeon_dpm
== -1))
1512 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1513 else if (radeon_dpm
== 0)
1514 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1516 rdev
->pm
.pm_method
= PM_METHOD_DPM
;
1519 /* default to profile method */
1520 rdev
->pm
.pm_method
= PM_METHOD_PROFILE
;
1524 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1525 return radeon_pm_init_dpm(rdev
);
1527 return radeon_pm_init_old(rdev
);
1530 int radeon_pm_late_init(struct radeon_device
*rdev
)
1534 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
) {
1535 if (rdev
->pm
.dpm_enabled
) {
1536 if (!rdev
->pm
.sysfs_initialized
) {
1537 ret
= device_create_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1539 DRM_ERROR("failed to create device file for dpm state\n");
1540 ret
= device_create_file(rdev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1542 DRM_ERROR("failed to create device file for dpm state\n");
1543 /* XXX: these are noops for dpm but are here for backwards compat */
1544 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
1546 DRM_ERROR("failed to create device file for power profile\n");
1547 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
1549 DRM_ERROR("failed to create device file for power method\n");
1550 rdev
->pm
.sysfs_initialized
= true;
1553 mutex_lock(&rdev
->pm
.mutex
);
1554 ret
= radeon_dpm_late_enable(rdev
);
1555 mutex_unlock(&rdev
->pm
.mutex
);
1557 rdev
->pm
.dpm_enabled
= false;
1558 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1560 /* set the dpm state for PX since there won't be
1561 * a modeset to call this.
1563 radeon_pm_compute_clocks(rdev
);
1567 if ((rdev
->pm
.num_power_states
> 1) &&
1568 (!rdev
->pm
.sysfs_initialized
)) {
1569 /* where's the best place to put these? */
1570 ret
= device_create_file(rdev
->dev
, &dev_attr_power_profile
);
1572 DRM_ERROR("failed to create device file for power profile\n");
1573 ret
= device_create_file(rdev
->dev
, &dev_attr_power_method
);
1575 DRM_ERROR("failed to create device file for power method\n");
1577 rdev
->pm
.sysfs_initialized
= true;
1583 static void radeon_pm_fini_old(struct radeon_device
*rdev
)
1585 if (rdev
->pm
.num_power_states
> 1) {
1586 mutex_lock(&rdev
->pm
.mutex
);
1587 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1588 rdev
->pm
.profile
= PM_PROFILE_DEFAULT
;
1589 radeon_pm_update_profile(rdev
);
1590 radeon_pm_set_clocks(rdev
);
1591 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1592 /* reset default clocks */
1593 rdev
->pm
.dynpm_state
= DYNPM_STATE_DISABLED
;
1594 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1595 radeon_pm_set_clocks(rdev
);
1597 mutex_unlock(&rdev
->pm
.mutex
);
1599 cancel_delayed_work_sync(&rdev
->pm
.dynpm_idle_work
);
1601 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1602 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1605 radeon_hwmon_fini(rdev
);
1606 kfree(rdev
->pm
.power_state
);
1609 static void radeon_pm_fini_dpm(struct radeon_device
*rdev
)
1611 if (rdev
->pm
.num_power_states
> 1) {
1612 mutex_lock(&rdev
->pm
.mutex
);
1613 radeon_dpm_disable(rdev
);
1614 mutex_unlock(&rdev
->pm
.mutex
);
1616 device_remove_file(rdev
->dev
, &dev_attr_power_dpm_state
);
1617 device_remove_file(rdev
->dev
, &dev_attr_power_dpm_force_performance_level
);
1618 /* XXX backwards compat */
1619 device_remove_file(rdev
->dev
, &dev_attr_power_profile
);
1620 device_remove_file(rdev
->dev
, &dev_attr_power_method
);
1622 radeon_dpm_fini(rdev
);
1624 radeon_hwmon_fini(rdev
);
1625 kfree(rdev
->pm
.power_state
);
1628 void radeon_pm_fini(struct radeon_device
*rdev
)
1630 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1631 radeon_pm_fini_dpm(rdev
);
1633 radeon_pm_fini_old(rdev
);
1636 static void radeon_pm_compute_clocks_old(struct radeon_device
*rdev
)
1638 struct drm_device
*ddev
= rdev
->ddev
;
1639 struct drm_crtc
*crtc
;
1640 struct radeon_crtc
*radeon_crtc
;
1642 if (rdev
->pm
.num_power_states
< 2)
1645 mutex_lock(&rdev
->pm
.mutex
);
1647 rdev
->pm
.active_crtcs
= 0;
1648 rdev
->pm
.active_crtc_count
= 0;
1649 if (rdev
->num_crtc
&& rdev
->mode_info
.mode_config_initialized
) {
1650 list_for_each_entry(crtc
,
1651 &ddev
->mode_config
.crtc_list
, head
) {
1652 radeon_crtc
= to_radeon_crtc(crtc
);
1653 if (radeon_crtc
->enabled
) {
1654 rdev
->pm
.active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1655 rdev
->pm
.active_crtc_count
++;
1660 if (rdev
->pm
.pm_method
== PM_METHOD_PROFILE
) {
1661 radeon_pm_update_profile(rdev
);
1662 radeon_pm_set_clocks(rdev
);
1663 } else if (rdev
->pm
.pm_method
== PM_METHOD_DYNPM
) {
1664 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_DISABLED
) {
1665 if (rdev
->pm
.active_crtc_count
> 1) {
1666 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1667 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1669 rdev
->pm
.dynpm_state
= DYNPM_STATE_PAUSED
;
1670 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_DEFAULT
;
1671 radeon_pm_get_dynpm_state(rdev
);
1672 radeon_pm_set_clocks(rdev
);
1674 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1676 } else if (rdev
->pm
.active_crtc_count
== 1) {
1677 /* TODO: Increase clocks if needed for current mode */
1679 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_MINIMUM
) {
1680 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1681 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_UPCLOCK
;
1682 radeon_pm_get_dynpm_state(rdev
);
1683 radeon_pm_set_clocks(rdev
);
1685 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1686 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1687 } else if (rdev
->pm
.dynpm_state
== DYNPM_STATE_PAUSED
) {
1688 rdev
->pm
.dynpm_state
= DYNPM_STATE_ACTIVE
;
1689 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1690 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1691 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1693 } else { /* count == 0 */
1694 if (rdev
->pm
.dynpm_state
!= DYNPM_STATE_MINIMUM
) {
1695 cancel_delayed_work(&rdev
->pm
.dynpm_idle_work
);
1697 rdev
->pm
.dynpm_state
= DYNPM_STATE_MINIMUM
;
1698 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_MINIMUM
;
1699 radeon_pm_get_dynpm_state(rdev
);
1700 radeon_pm_set_clocks(rdev
);
1706 mutex_unlock(&rdev
->pm
.mutex
);
1709 static void radeon_pm_compute_clocks_dpm(struct radeon_device
*rdev
)
1711 struct drm_device
*ddev
= rdev
->ddev
;
1712 struct drm_crtc
*crtc
;
1713 struct radeon_crtc
*radeon_crtc
;
1715 if (!rdev
->pm
.dpm_enabled
)
1718 mutex_lock(&rdev
->pm
.mutex
);
1720 /* update active crtc counts */
1721 rdev
->pm
.dpm
.new_active_crtcs
= 0;
1722 rdev
->pm
.dpm
.new_active_crtc_count
= 0;
1723 if (rdev
->num_crtc
&& rdev
->mode_info
.mode_config_initialized
) {
1724 list_for_each_entry(crtc
,
1725 &ddev
->mode_config
.crtc_list
, head
) {
1726 radeon_crtc
= to_radeon_crtc(crtc
);
1727 if (crtc
->enabled
) {
1728 rdev
->pm
.dpm
.new_active_crtcs
|= (1 << radeon_crtc
->crtc_id
);
1729 rdev
->pm
.dpm
.new_active_crtc_count
++;
1734 /* update battery/ac status */
1735 if (power_supply_is_system_supplied() > 0)
1736 rdev
->pm
.dpm
.ac_power
= true;
1738 rdev
->pm
.dpm
.ac_power
= false;
1740 radeon_dpm_change_power_state_locked(rdev
);
1742 mutex_unlock(&rdev
->pm
.mutex
);
1746 void radeon_pm_compute_clocks(struct radeon_device
*rdev
)
1748 if (rdev
->pm
.pm_method
== PM_METHOD_DPM
)
1749 radeon_pm_compute_clocks_dpm(rdev
);
1751 radeon_pm_compute_clocks_old(rdev
);
1754 static bool radeon_pm_in_vbl(struct radeon_device
*rdev
)
1756 int crtc
, vpos
, hpos
, vbl_status
;
1759 /* Iterate over all active crtc's. All crtc's must be in vblank,
1760 * otherwise return in_vbl == false.
1762 for (crtc
= 0; (crtc
< rdev
->num_crtc
) && in_vbl
; crtc
++) {
1763 if (rdev
->pm
.active_crtcs
& (1 << crtc
)) {
1764 vbl_status
= radeon_get_crtc_scanoutpos(rdev
->ddev
,
1766 USE_REAL_VBLANKSTART
,
1767 &vpos
, &hpos
, NULL
, NULL
,
1768 &rdev
->mode_info
.crtcs
[crtc
]->base
.hwmode
);
1769 if ((vbl_status
& DRM_SCANOUTPOS_VALID
) &&
1770 !(vbl_status
& DRM_SCANOUTPOS_IN_VBLANK
))
1778 static bool radeon_pm_debug_check_in_vbl(struct radeon_device
*rdev
, bool finish
)
1781 bool in_vbl
= radeon_pm_in_vbl(rdev
);
1783 if (in_vbl
== false)
1784 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc
,
1785 finish
? "exit" : "entry");
1789 static void radeon_dynpm_idle_work_handler(struct work_struct
*work
)
1791 struct radeon_device
*rdev
;
1793 rdev
= container_of(work
, struct radeon_device
,
1794 pm
.dynpm_idle_work
.work
);
1796 resched
= ttm_bo_lock_delayed_workqueue(&rdev
->mman
.bdev
);
1797 mutex_lock(&rdev
->pm
.mutex
);
1798 if (rdev
->pm
.dynpm_state
== DYNPM_STATE_ACTIVE
) {
1799 int not_processed
= 0;
1802 for (i
= 0; i
< RADEON_NUM_RINGS
; ++i
) {
1803 struct radeon_ring
*ring
= &rdev
->ring
[i
];
1806 not_processed
+= radeon_fence_count_emitted(rdev
, i
);
1807 if (not_processed
>= 3)
1812 if (not_processed
>= 3) { /* should upclock */
1813 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_DOWNCLOCK
) {
1814 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1815 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1816 rdev
->pm
.dynpm_can_upclock
) {
1817 rdev
->pm
.dynpm_planned_action
=
1818 DYNPM_ACTION_UPCLOCK
;
1819 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1820 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1822 } else if (not_processed
== 0) { /* should downclock */
1823 if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_UPCLOCK
) {
1824 rdev
->pm
.dynpm_planned_action
= DYNPM_ACTION_NONE
;
1825 } else if (rdev
->pm
.dynpm_planned_action
== DYNPM_ACTION_NONE
&&
1826 rdev
->pm
.dynpm_can_downclock
) {
1827 rdev
->pm
.dynpm_planned_action
=
1828 DYNPM_ACTION_DOWNCLOCK
;
1829 rdev
->pm
.dynpm_action_timeout
= jiffies
+
1830 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS
);
1834 /* Note, radeon_pm_set_clocks is called with static_switch set
1835 * to false since we want to wait for vbl to avoid flicker.
1837 if (rdev
->pm
.dynpm_planned_action
!= DYNPM_ACTION_NONE
&&
1838 jiffies
> rdev
->pm
.dynpm_action_timeout
) {
1839 radeon_pm_get_dynpm_state(rdev
);
1840 radeon_pm_set_clocks(rdev
);
1843 schedule_delayed_work(&rdev
->pm
.dynpm_idle_work
,
1844 msecs_to_jiffies(RADEON_IDLE_LOOP_MS
));
1846 mutex_unlock(&rdev
->pm
.mutex
);
1847 ttm_bo_unlock_delayed_workqueue(&rdev
->mman
.bdev
, resched
);
1853 #if defined(CONFIG_DEBUG_FS)
1855 static int radeon_debugfs_pm_info(struct seq_file
*m
, void *data
)
1857 struct drm_info_node
*node
= (struct drm_info_node
*) m
->private;
1858 struct drm_device
*dev
= node
->minor
->dev
;
1859 struct radeon_device
*rdev
= dev
->dev_private
;
1860 struct drm_device
*ddev
= rdev
->ddev
;
1862 if ((rdev
->flags
& RADEON_IS_PX
) &&
1863 (ddev
->switch_power_state
!= DRM_SWITCH_POWER_ON
)) {
1864 seq_printf(m
, "PX asic powered off\n");
1865 } else if (rdev
->pm
.dpm_enabled
) {
1866 mutex_lock(&rdev
->pm
.mutex
);
1867 if (rdev
->asic
->dpm
.debugfs_print_current_performance_level
)
1868 radeon_dpm_debugfs_print_current_performance_level(rdev
, m
);
1870 seq_printf(m
, "Debugfs support not implemented for this asic\n");
1871 mutex_unlock(&rdev
->pm
.mutex
);
1873 seq_printf(m
, "default engine clock: %u0 kHz\n", rdev
->pm
.default_sclk
);
1874 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1875 if ((rdev
->family
>= CHIP_PALM
) && (rdev
->flags
& RADEON_IS_IGP
))
1876 seq_printf(m
, "current engine clock: %u0 kHz\n", rdev
->pm
.current_sclk
);
1878 seq_printf(m
, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev
));
1879 seq_printf(m
, "default memory clock: %u0 kHz\n", rdev
->pm
.default_mclk
);
1880 if (rdev
->asic
->pm
.get_memory_clock
)
1881 seq_printf(m
, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev
));
1882 if (rdev
->pm
.current_vddc
)
1883 seq_printf(m
, "voltage: %u mV\n", rdev
->pm
.current_vddc
);
1884 if (rdev
->asic
->pm
.get_pcie_lanes
)
1885 seq_printf(m
, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev
));
1891 static struct drm_info_list radeon_pm_info_list
[] = {
1892 {"radeon_pm_info", radeon_debugfs_pm_info
, 0, NULL
},
1896 static int radeon_debugfs_pm_init(struct radeon_device
*rdev
)
1898 #if defined(CONFIG_DEBUG_FS)
1899 return radeon_debugfs_add_files(rdev
, radeon_pm_info_list
, ARRAY_SIZE(radeon_pm_info_list
));