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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / tegra / hdmi.c
1 /*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/clk/tegra.h>
12 #include <linux/debugfs.h>
13 #include <linux/hdmi.h>
14 #include <linux/regulator/consumer.h>
15
16 #include "hdmi.h"
17 #include "drm.h"
18 #include "dc.h"
19
20 struct tmds_config {
21 unsigned int pclk;
22 u32 pll0;
23 u32 pll1;
24 u32 pe_current;
25 u32 drive_current;
26 u32 peak_current;
27 };
28
29 struct tegra_hdmi_config {
30 const struct tmds_config *tmds;
31 unsigned int num_tmds;
32
33 unsigned long fuse_override_offset;
34 unsigned long fuse_override_value;
35
36 bool has_sor_io_peak_current;
37 };
38
39 struct tegra_hdmi {
40 struct host1x_client client;
41 struct tegra_output output;
42 struct device *dev;
43
44 struct regulator *vdd;
45 struct regulator *pll;
46
47 void __iomem *regs;
48 unsigned int irq;
49
50 struct clk *clk_parent;
51 struct clk *clk;
52
53 const struct tegra_hdmi_config *config;
54
55 unsigned int audio_source;
56 unsigned int audio_freq;
57 bool stereo;
58 bool dvi;
59
60 struct drm_info_list *debugfs_files;
61 struct drm_minor *minor;
62 struct dentry *debugfs;
63 };
64
65 static inline struct tegra_hdmi *
66 host1x_client_to_hdmi(struct host1x_client *client)
67 {
68 return container_of(client, struct tegra_hdmi, client);
69 }
70
71 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
72 {
73 return container_of(output, struct tegra_hdmi, output);
74 }
75
76 #define HDMI_AUDIOCLK_FREQ 216000000
77 #define HDMI_REKEY_DEFAULT 56
78
79 enum {
80 AUTO = 0,
81 SPDIF,
82 HDA,
83 };
84
85 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
86 unsigned long reg)
87 {
88 return readl(hdmi->regs + (reg << 2));
89 }
90
91 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
92 unsigned long reg)
93 {
94 writel(val, hdmi->regs + (reg << 2));
95 }
96
97 struct tegra_hdmi_audio_config {
98 unsigned int pclk;
99 unsigned int n;
100 unsigned int cts;
101 unsigned int aval;
102 };
103
104 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
105 { 25200000, 4096, 25200, 24000 },
106 { 27000000, 4096, 27000, 24000 },
107 { 74250000, 4096, 74250, 24000 },
108 { 148500000, 4096, 148500, 24000 },
109 { 0, 0, 0, 0 },
110 };
111
112 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
113 { 25200000, 5880, 26250, 25000 },
114 { 27000000, 5880, 28125, 25000 },
115 { 74250000, 4704, 61875, 20000 },
116 { 148500000, 4704, 123750, 20000 },
117 { 0, 0, 0, 0 },
118 };
119
120 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
121 { 25200000, 6144, 25200, 24000 },
122 { 27000000, 6144, 27000, 24000 },
123 { 74250000, 6144, 74250, 24000 },
124 { 148500000, 6144, 148500, 24000 },
125 { 0, 0, 0, 0 },
126 };
127
128 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
129 { 25200000, 11760, 26250, 25000 },
130 { 27000000, 11760, 28125, 25000 },
131 { 74250000, 9408, 61875, 20000 },
132 { 148500000, 9408, 123750, 20000 },
133 { 0, 0, 0, 0 },
134 };
135
136 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
137 { 25200000, 12288, 25200, 24000 },
138 { 27000000, 12288, 27000, 24000 },
139 { 74250000, 12288, 74250, 24000 },
140 { 148500000, 12288, 148500, 24000 },
141 { 0, 0, 0, 0 },
142 };
143
144 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
145 { 25200000, 23520, 26250, 25000 },
146 { 27000000, 23520, 28125, 25000 },
147 { 74250000, 18816, 61875, 20000 },
148 { 148500000, 18816, 123750, 20000 },
149 { 0, 0, 0, 0 },
150 };
151
152 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
153 { 25200000, 24576, 25200, 24000 },
154 { 27000000, 24576, 27000, 24000 },
155 { 74250000, 24576, 74250, 24000 },
156 { 148500000, 24576, 148500, 24000 },
157 { 0, 0, 0, 0 },
158 };
159
160 static const struct tmds_config tegra20_tmds_config[] = {
161 { /* slow pixel clock modes */
162 .pclk = 27000000,
163 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
164 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
165 SOR_PLL_TX_REG_LOAD(3),
166 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
167 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
168 PE_CURRENT1(PE_CURRENT_0_0_mA) |
169 PE_CURRENT2(PE_CURRENT_0_0_mA) |
170 PE_CURRENT3(PE_CURRENT_0_0_mA),
171 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
172 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
173 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
174 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
175 },
176 { /* high pixel clock modes */
177 .pclk = UINT_MAX,
178 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
179 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
180 SOR_PLL_TX_REG_LOAD(3),
181 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
182 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
183 PE_CURRENT1(PE_CURRENT_6_0_mA) |
184 PE_CURRENT2(PE_CURRENT_6_0_mA) |
185 PE_CURRENT3(PE_CURRENT_6_0_mA),
186 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
187 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
188 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
189 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
190 },
191 };
192
193 static const struct tmds_config tegra30_tmds_config[] = {
194 { /* 480p modes */
195 .pclk = 27000000,
196 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
197 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
198 SOR_PLL_TX_REG_LOAD(0),
199 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
200 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
201 PE_CURRENT1(PE_CURRENT_0_0_mA) |
202 PE_CURRENT2(PE_CURRENT_0_0_mA) |
203 PE_CURRENT3(PE_CURRENT_0_0_mA),
204 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
205 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
206 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
207 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
208 }, { /* 720p modes */
209 .pclk = 74250000,
210 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
211 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
212 SOR_PLL_TX_REG_LOAD(0),
213 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
214 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
215 PE_CURRENT1(PE_CURRENT_5_0_mA) |
216 PE_CURRENT2(PE_CURRENT_5_0_mA) |
217 PE_CURRENT3(PE_CURRENT_5_0_mA),
218 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
219 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
220 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
221 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
222 }, { /* 1080p modes */
223 .pclk = UINT_MAX,
224 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
225 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
226 SOR_PLL_TX_REG_LOAD(0),
227 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
228 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
229 PE_CURRENT1(PE_CURRENT_5_0_mA) |
230 PE_CURRENT2(PE_CURRENT_5_0_mA) |
231 PE_CURRENT3(PE_CURRENT_5_0_mA),
232 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
233 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
234 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
235 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
236 },
237 };
238
239 static const struct tmds_config tegra114_tmds_config[] = {
240 { /* 480p/576p / 25.2MHz/27MHz modes */
241 .pclk = 27000000,
242 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
243 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
244 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
245 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
246 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
247 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
248 PE_CURRENT3(PE_CURRENT_0_mA_T114),
249 .drive_current =
250 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
251 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
252 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
253 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
254 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
255 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
256 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
257 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
258 }, { /* 720p / 74.25MHz modes */
259 .pclk = 74250000,
260 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
261 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
262 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
263 SOR_PLL_TMDS_TERMADJ(0),
264 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
265 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
266 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
267 PE_CURRENT3(PE_CURRENT_15_mA_T114),
268 .drive_current =
269 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
270 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
271 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
272 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
273 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
274 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
275 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
276 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
277 }, { /* 1080p / 148.5MHz modes */
278 .pclk = 148500000,
279 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
280 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
281 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
282 SOR_PLL_TMDS_TERMADJ(0),
283 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
284 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
285 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
286 PE_CURRENT3(PE_CURRENT_10_mA_T114),
287 .drive_current =
288 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
289 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
290 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
291 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
292 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
293 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
294 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
295 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
296 }, { /* 225/297MHz modes */
297 .pclk = UINT_MAX,
298 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
299 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
300 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
301 | SOR_PLL_TMDS_TERM_ENABLE,
302 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
303 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
304 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
305 PE_CURRENT3(PE_CURRENT_0_mA_T114),
306 .drive_current =
307 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
308 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
309 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
310 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
311 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
312 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
313 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
314 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
315 },
316 };
317
318 static const struct tegra_hdmi_audio_config *
319 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
320 {
321 const struct tegra_hdmi_audio_config *table;
322
323 switch (audio_freq) {
324 case 32000:
325 table = tegra_hdmi_audio_32k;
326 break;
327
328 case 44100:
329 table = tegra_hdmi_audio_44_1k;
330 break;
331
332 case 48000:
333 table = tegra_hdmi_audio_48k;
334 break;
335
336 case 88200:
337 table = tegra_hdmi_audio_88_2k;
338 break;
339
340 case 96000:
341 table = tegra_hdmi_audio_96k;
342 break;
343
344 case 176400:
345 table = tegra_hdmi_audio_176_4k;
346 break;
347
348 case 192000:
349 table = tegra_hdmi_audio_192k;
350 break;
351
352 default:
353 return NULL;
354 }
355
356 while (table->pclk) {
357 if (table->pclk == pclk)
358 return table;
359
360 table++;
361 }
362
363 return NULL;
364 }
365
366 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
367 {
368 const unsigned int freqs[] = {
369 32000, 44100, 48000, 88200, 96000, 176400, 192000
370 };
371 unsigned int i;
372
373 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
374 unsigned int f = freqs[i];
375 unsigned int eight_half;
376 unsigned long value;
377 unsigned int delta;
378
379 if (f > 96000)
380 delta = 2;
381 else if (f > 480000)
382 delta = 6;
383 else
384 delta = 9;
385
386 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
387 value = AUDIO_FS_LOW(eight_half - delta) |
388 AUDIO_FS_HIGH(eight_half + delta);
389 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
390 }
391 }
392
393 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
394 {
395 struct device_node *node = hdmi->dev->of_node;
396 const struct tegra_hdmi_audio_config *config;
397 unsigned int offset = 0;
398 unsigned long value;
399
400 switch (hdmi->audio_source) {
401 case HDA:
402 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
403 break;
404
405 case SPDIF:
406 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
407 break;
408
409 default:
410 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
411 break;
412 }
413
414 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
415 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
416 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
417 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
418 } else {
419 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
420 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
421
422 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
423 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
424 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
425 }
426
427 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
428 if (!config) {
429 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
430 hdmi->audio_freq, pclk);
431 return -EINVAL;
432 }
433
434 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
435
436 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
437 AUDIO_N_VALUE(config->n - 1);
438 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
439
440 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
441 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
442
443 value = ACR_SUBPACK_CTS(config->cts);
444 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
445
446 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
447 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
448
449 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
450 value &= ~AUDIO_N_RESETF;
451 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
452
453 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
454 switch (hdmi->audio_freq) {
455 case 32000:
456 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
457 break;
458
459 case 44100:
460 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
461 break;
462
463 case 48000:
464 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
465 break;
466
467 case 88200:
468 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
469 break;
470
471 case 96000:
472 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
473 break;
474
475 case 176400:
476 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
477 break;
478
479 case 192000:
480 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
481 break;
482 }
483
484 tegra_hdmi_writel(hdmi, config->aval, offset);
485 }
486
487 tegra_hdmi_setup_audio_fs_tables(hdmi);
488
489 return 0;
490 }
491
492 static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size)
493 {
494 unsigned long value = 0;
495 size_t i;
496
497 for (i = size; i > 0; i--)
498 value = (value << 8) | ptr[i - 1];
499
500 return value;
501 }
502
503 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
504 size_t size)
505 {
506 const u8 *ptr = data;
507 unsigned long offset;
508 unsigned long value;
509 size_t i, j;
510
511 switch (ptr[0]) {
512 case HDMI_INFOFRAME_TYPE_AVI:
513 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
514 break;
515
516 case HDMI_INFOFRAME_TYPE_AUDIO:
517 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
518 break;
519
520 case HDMI_INFOFRAME_TYPE_VENDOR:
521 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
522 break;
523
524 default:
525 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
526 ptr[0]);
527 return;
528 }
529
530 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
531 INFOFRAME_HEADER_VERSION(ptr[1]) |
532 INFOFRAME_HEADER_LEN(ptr[2]);
533 tegra_hdmi_writel(hdmi, value, offset);
534 offset++;
535
536 /*
537 * Each subpack contains 7 bytes, divided into:
538 * - subpack_low: bytes 0 - 3
539 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
540 */
541 for (i = 3, j = 0; i < size; i += 7, j += 8) {
542 size_t rem = size - i, num = min_t(size_t, rem, 4);
543
544 value = tegra_hdmi_subpack(&ptr[i], num);
545 tegra_hdmi_writel(hdmi, value, offset++);
546
547 num = min_t(size_t, rem - num, 3);
548
549 value = tegra_hdmi_subpack(&ptr[i + 4], num);
550 tegra_hdmi_writel(hdmi, value, offset++);
551 }
552 }
553
554 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
555 struct drm_display_mode *mode)
556 {
557 struct hdmi_avi_infoframe frame;
558 u8 buffer[17];
559 ssize_t err;
560
561 if (hdmi->dvi) {
562 tegra_hdmi_writel(hdmi, 0,
563 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
564 return;
565 }
566
567 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
568 if (err < 0) {
569 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
570 return;
571 }
572
573 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
574 if (err < 0) {
575 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
576 return;
577 }
578
579 tegra_hdmi_write_infopack(hdmi, buffer, err);
580
581 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
582 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
583 }
584
585 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
586 {
587 struct hdmi_audio_infoframe frame;
588 u8 buffer[14];
589 ssize_t err;
590
591 if (hdmi->dvi) {
592 tegra_hdmi_writel(hdmi, 0,
593 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
594 return;
595 }
596
597 err = hdmi_audio_infoframe_init(&frame);
598 if (err < 0) {
599 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
600 err);
601 return;
602 }
603
604 frame.channels = 2;
605
606 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
607 if (err < 0) {
608 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
609 err);
610 return;
611 }
612
613 /*
614 * The audio infoframe has only one set of subpack registers, so the
615 * infoframe needs to be truncated. One set of subpack registers can
616 * contain 7 bytes. Including the 3 byte header only the first 10
617 * bytes can be programmed.
618 */
619 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
620
621 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
622 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
623 }
624
625 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
626 {
627 struct hdmi_vendor_infoframe frame;
628 unsigned long value;
629 u8 buffer[10];
630 ssize_t err;
631
632 if (!hdmi->stereo) {
633 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
634 value &= ~GENERIC_CTRL_ENABLE;
635 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
636 return;
637 }
638
639 hdmi_vendor_infoframe_init(&frame);
640 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
641
642 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
643 if (err < 0) {
644 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
645 err);
646 return;
647 }
648
649 tegra_hdmi_write_infopack(hdmi, buffer, err);
650
651 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
652 value |= GENERIC_CTRL_ENABLE;
653 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
654 }
655
656 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
657 const struct tmds_config *tmds)
658 {
659 unsigned long value;
660
661 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
662 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
663 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
664
665 tegra_hdmi_writel(hdmi, tmds->drive_current,
666 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
667
668 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
669 value |= hdmi->config->fuse_override_value;
670 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
671
672 if (hdmi->config->has_sor_io_peak_current)
673 tegra_hdmi_writel(hdmi, tmds->peak_current,
674 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
675 }
676
677 static bool tegra_output_is_hdmi(struct tegra_output *output)
678 {
679 struct edid *edid;
680
681 if (!output->connector.edid_blob_ptr)
682 return false;
683
684 edid = (struct edid *)output->connector.edid_blob_ptr->data;
685
686 return drm_detect_hdmi_monitor(edid);
687 }
688
689 static int tegra_output_hdmi_enable(struct tegra_output *output)
690 {
691 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
692 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
693 struct drm_display_mode *mode = &dc->base.mode;
694 struct tegra_hdmi *hdmi = to_hdmi(output);
695 struct device_node *node = hdmi->dev->of_node;
696 unsigned int pulse_start, div82, pclk;
697 unsigned long value;
698 int retries = 1000;
699 int err;
700
701 hdmi->dvi = !tegra_output_is_hdmi(output);
702
703 pclk = mode->clock * 1000;
704 h_sync_width = mode->hsync_end - mode->hsync_start;
705 h_back_porch = mode->htotal - mode->hsync_end;
706 h_front_porch = mode->hsync_start - mode->hdisplay;
707
708 err = regulator_enable(hdmi->pll);
709 if (err < 0) {
710 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
711 return err;
712 }
713
714 /*
715 * This assumes that the display controller will divide its parent
716 * clock by 2 to generate the pixel clock.
717 */
718 err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
719 if (err < 0) {
720 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
721 return err;
722 }
723
724 err = clk_set_rate(hdmi->clk, pclk);
725 if (err < 0)
726 return err;
727
728 err = clk_enable(hdmi->clk);
729 if (err < 0) {
730 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
731 return err;
732 }
733
734 tegra_periph_reset_assert(hdmi->clk);
735 usleep_range(1000, 2000);
736 tegra_periph_reset_deassert(hdmi->clk);
737
738 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
739 DC_DISP_DISP_TIMING_OPTIONS);
740 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
741 DC_DISP_DISP_COLOR_CONTROL);
742
743 /* video_preamble uses h_pulse2 */
744 pulse_start = 1 + h_sync_width + h_back_porch - 10;
745
746 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
747
748 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
749 PULSE_LAST_END_A;
750 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
751
752 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
753 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
754
755 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
756 VSYNC_WINDOW_ENABLE;
757 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
758
759 if (dc->pipe)
760 value = HDMI_SRC_DISPLAYB;
761 else
762 value = HDMI_SRC_DISPLAYA;
763
764 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
765 (mode->vdisplay == 576)))
766 tegra_hdmi_writel(hdmi,
767 value | ARM_VIDEO_RANGE_FULL,
768 HDMI_NV_PDISP_INPUT_CONTROL);
769 else
770 tegra_hdmi_writel(hdmi,
771 value | ARM_VIDEO_RANGE_LIMITED,
772 HDMI_NV_PDISP_INPUT_CONTROL);
773
774 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
775 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
776 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
777
778 if (!hdmi->dvi) {
779 err = tegra_hdmi_setup_audio(hdmi, pclk);
780 if (err < 0)
781 hdmi->dvi = true;
782 }
783
784 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
785 /*
786 * TODO: add ELD support
787 */
788 }
789
790 rekey = HDMI_REKEY_DEFAULT;
791 value = HDMI_CTRL_REKEY(rekey);
792 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
793 h_front_porch - rekey - 18) / 32);
794
795 if (!hdmi->dvi)
796 value |= HDMI_CTRL_ENABLE;
797
798 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
799
800 if (hdmi->dvi)
801 tegra_hdmi_writel(hdmi, 0x0,
802 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
803 else
804 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
805 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
806
807 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
808 tegra_hdmi_setup_audio_infoframe(hdmi);
809 tegra_hdmi_setup_stereo_infoframe(hdmi);
810
811 /* TMDS CONFIG */
812 for (i = 0; i < hdmi->config->num_tmds; i++) {
813 if (pclk <= hdmi->config->tmds[i].pclk) {
814 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
815 break;
816 }
817 }
818
819 tegra_hdmi_writel(hdmi,
820 SOR_SEQ_CTL_PU_PC(0) |
821 SOR_SEQ_PU_PC_ALT(0) |
822 SOR_SEQ_PD_PC(8) |
823 SOR_SEQ_PD_PC_ALT(8),
824 HDMI_NV_PDISP_SOR_SEQ_CTL);
825
826 value = SOR_SEQ_INST_WAIT_TIME(1) |
827 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
828 SOR_SEQ_INST_HALT |
829 SOR_SEQ_INST_PIN_A_LOW |
830 SOR_SEQ_INST_PIN_B_LOW |
831 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
832
833 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
834 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
835
836 value = 0x1c800;
837 value &= ~SOR_CSTM_ROTCLK(~0);
838 value |= SOR_CSTM_ROTCLK(2);
839 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
840
841 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
842 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
843 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
844
845 /* start SOR */
846 tegra_hdmi_writel(hdmi,
847 SOR_PWR_NORMAL_STATE_PU |
848 SOR_PWR_NORMAL_START_NORMAL |
849 SOR_PWR_SAFE_STATE_PD |
850 SOR_PWR_SETTING_NEW_TRIGGER,
851 HDMI_NV_PDISP_SOR_PWR);
852 tegra_hdmi_writel(hdmi,
853 SOR_PWR_NORMAL_STATE_PU |
854 SOR_PWR_NORMAL_START_NORMAL |
855 SOR_PWR_SAFE_STATE_PD |
856 SOR_PWR_SETTING_NEW_DONE,
857 HDMI_NV_PDISP_SOR_PWR);
858
859 do {
860 BUG_ON(--retries < 0);
861 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
862 } while (value & SOR_PWR_SETTING_NEW_PENDING);
863
864 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
865 SOR_STATE_ASY_OWNER_HEAD0 |
866 SOR_STATE_ASY_SUBOWNER_BOTH |
867 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
868 SOR_STATE_ASY_DEPOL_POS;
869
870 /* setup sync polarities */
871 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
872 value |= SOR_STATE_ASY_HSYNCPOL_POS;
873
874 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
875 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
876
877 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
878 value |= SOR_STATE_ASY_VSYNCPOL_POS;
879
880 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
881 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
882
883 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
884
885 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
886 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
887
888 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
889 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
890 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
891 HDMI_NV_PDISP_SOR_STATE1);
892 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
893
894 tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
895
896 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
897 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
898 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
899
900 value = DISP_CTRL_MODE_C_DISPLAY;
901 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
902
903 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
904 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
905
906 /* TODO: add HDCP support */
907
908 return 0;
909 }
910
911 static int tegra_output_hdmi_disable(struct tegra_output *output)
912 {
913 struct tegra_hdmi *hdmi = to_hdmi(output);
914
915 tegra_periph_reset_assert(hdmi->clk);
916 clk_disable(hdmi->clk);
917 regulator_disable(hdmi->pll);
918
919 return 0;
920 }
921
922 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
923 struct clk *clk, unsigned long pclk)
924 {
925 struct tegra_hdmi *hdmi = to_hdmi(output);
926 struct clk *base;
927 int err;
928
929 err = clk_set_parent(clk, hdmi->clk_parent);
930 if (err < 0) {
931 dev_err(output->dev, "failed to set parent: %d\n", err);
932 return err;
933 }
934
935 base = clk_get_parent(hdmi->clk_parent);
936
937 /*
938 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
939 * respectively, each of which divides the base pll_d by 2.
940 */
941 err = clk_set_rate(base, pclk * 2);
942 if (err < 0)
943 dev_err(output->dev,
944 "failed to set base clock rate to %lu Hz\n",
945 pclk * 2);
946
947 return 0;
948 }
949
950 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
951 struct drm_display_mode *mode,
952 enum drm_mode_status *status)
953 {
954 struct tegra_hdmi *hdmi = to_hdmi(output);
955 unsigned long pclk = mode->clock * 1000;
956 struct clk *parent;
957 long err;
958
959 parent = clk_get_parent(hdmi->clk_parent);
960
961 err = clk_round_rate(parent, pclk * 4);
962 if (err < 0)
963 *status = MODE_NOCLOCK;
964 else
965 *status = MODE_OK;
966
967 return 0;
968 }
969
970 static const struct tegra_output_ops hdmi_ops = {
971 .enable = tegra_output_hdmi_enable,
972 .disable = tegra_output_hdmi_disable,
973 .setup_clock = tegra_output_hdmi_setup_clock,
974 .check_mode = tegra_output_hdmi_check_mode,
975 };
976
977 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
978 {
979 struct drm_info_node *node = s->private;
980 struct tegra_hdmi *hdmi = node->info_ent->data;
981 int err;
982
983 err = clk_enable(hdmi->clk);
984 if (err)
985 return err;
986
987 #define DUMP_REG(name) \
988 seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \
989 tegra_hdmi_readl(hdmi, name))
990
991 DUMP_REG(HDMI_CTXSW);
992 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
993 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
994 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
995 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
996 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
997 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
998 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
999 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1000 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1001 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1002 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1003 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1004 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1005 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1006 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1007 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1008 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1009 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1010 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1011 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1012 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1013 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1014 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1015 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1016 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1017 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1018 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1019 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1020 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1021 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1022 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1023 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1024 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1025 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1026 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1027 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1028 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1029 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1030 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1031 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1032 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1033 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1034 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1035 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1036 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1037 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1038 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1039 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1040 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1041 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1042 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1043 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1044 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1045 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1046 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1047 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1048 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1049 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1050 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1051 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1052 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1053 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1054 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1055 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1056 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1057 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1058 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1059 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1060 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1061 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1062 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1063 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1064 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1065 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1066 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1067 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1068 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1069 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1070 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1071 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1072 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1073 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1074 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1075 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1076 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1077 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1078 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1079 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1080 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1081 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1082 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1083 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1084 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1085 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1086 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1087 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1088 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1089 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1090 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1091 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1092 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1093 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1094 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1095 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1096 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1097 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1098 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1099 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1100 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1101 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1102 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1103 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1104 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1105 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1106 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1107 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1108 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1109 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1110 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1111 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1112 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1113 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1114 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1115 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1116 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1117 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1118 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1119 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1120 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1121 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1122 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1123 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1124 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1125 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1126 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1127 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1128 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1129 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1130 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1131 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1132 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1133 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1134 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1135 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1136 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1137 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1138 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1139 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1140 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1141 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1142 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1143 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1144 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1145 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1146 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1147 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1148 DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1149
1150 #undef DUMP_REG
1151
1152 clk_disable(hdmi->clk);
1153
1154 return 0;
1155 }
1156
1157 static struct drm_info_list debugfs_files[] = {
1158 { "regs", tegra_hdmi_show_regs, 0, NULL },
1159 };
1160
1161 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1162 struct drm_minor *minor)
1163 {
1164 unsigned int i;
1165 int err;
1166
1167 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1168 if (!hdmi->debugfs)
1169 return -ENOMEM;
1170
1171 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1172 GFP_KERNEL);
1173 if (!hdmi->debugfs_files) {
1174 err = -ENOMEM;
1175 goto remove;
1176 }
1177
1178 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1179 hdmi->debugfs_files[i].data = hdmi;
1180
1181 err = drm_debugfs_create_files(hdmi->debugfs_files,
1182 ARRAY_SIZE(debugfs_files),
1183 hdmi->debugfs, minor);
1184 if (err < 0)
1185 goto free;
1186
1187 hdmi->minor = minor;
1188
1189 return 0;
1190
1191 free:
1192 kfree(hdmi->debugfs_files);
1193 hdmi->debugfs_files = NULL;
1194 remove:
1195 debugfs_remove(hdmi->debugfs);
1196 hdmi->debugfs = NULL;
1197
1198 return err;
1199 }
1200
1201 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1202 {
1203 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1204 hdmi->minor);
1205 hdmi->minor = NULL;
1206
1207 kfree(hdmi->debugfs_files);
1208 hdmi->debugfs_files = NULL;
1209
1210 debugfs_remove(hdmi->debugfs);
1211 hdmi->debugfs = NULL;
1212
1213 return 0;
1214 }
1215
1216 static int tegra_hdmi_init(struct host1x_client *client)
1217 {
1218 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
1219 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1220 int err;
1221
1222 err = regulator_enable(hdmi->vdd);
1223 if (err < 0) {
1224 dev_err(client->dev, "failed to enable VDD regulator: %d\n",
1225 err);
1226 return err;
1227 }
1228
1229 hdmi->output.type = TEGRA_OUTPUT_HDMI;
1230 hdmi->output.dev = client->dev;
1231 hdmi->output.ops = &hdmi_ops;
1232
1233 err = tegra_output_init(tegra->drm, &hdmi->output);
1234 if (err < 0) {
1235 dev_err(client->dev, "output setup failed: %d\n", err);
1236 return err;
1237 }
1238
1239 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1240 err = tegra_hdmi_debugfs_init(hdmi, tegra->drm->primary);
1241 if (err < 0)
1242 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1243 }
1244
1245 return 0;
1246 }
1247
1248 static int tegra_hdmi_exit(struct host1x_client *client)
1249 {
1250 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1251 int err;
1252
1253 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1254 err = tegra_hdmi_debugfs_exit(hdmi);
1255 if (err < 0)
1256 dev_err(client->dev, "debugfs cleanup failed: %d\n",
1257 err);
1258 }
1259
1260 err = tegra_output_disable(&hdmi->output);
1261 if (err < 0) {
1262 dev_err(client->dev, "output failed to disable: %d\n", err);
1263 return err;
1264 }
1265
1266 err = tegra_output_exit(&hdmi->output);
1267 if (err < 0) {
1268 dev_err(client->dev, "output cleanup failed: %d\n", err);
1269 return err;
1270 }
1271
1272 regulator_disable(hdmi->vdd);
1273
1274 return 0;
1275 }
1276
1277 static const struct host1x_client_ops hdmi_client_ops = {
1278 .init = tegra_hdmi_init,
1279 .exit = tegra_hdmi_exit,
1280 };
1281
1282 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1283 .tmds = tegra20_tmds_config,
1284 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1285 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1286 .fuse_override_value = 1 << 31,
1287 .has_sor_io_peak_current = false,
1288 };
1289
1290 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1291 .tmds = tegra30_tmds_config,
1292 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1293 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1294 .fuse_override_value = 1 << 31,
1295 .has_sor_io_peak_current = false,
1296 };
1297
1298 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1299 .tmds = tegra114_tmds_config,
1300 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1301 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1302 .fuse_override_value = 1 << 31,
1303 .has_sor_io_peak_current = true,
1304 };
1305
1306 static const struct of_device_id tegra_hdmi_of_match[] = {
1307 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1308 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1309 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1310 { },
1311 };
1312
1313 static int tegra_hdmi_probe(struct platform_device *pdev)
1314 {
1315 const struct of_device_id *match;
1316 struct tegra_hdmi *hdmi;
1317 struct resource *regs;
1318 int err;
1319
1320 match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node);
1321 if (!match)
1322 return -ENODEV;
1323
1324 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1325 if (!hdmi)
1326 return -ENOMEM;
1327
1328 hdmi->config = match->data;
1329 hdmi->dev = &pdev->dev;
1330 hdmi->audio_source = AUTO;
1331 hdmi->audio_freq = 44100;
1332 hdmi->stereo = false;
1333 hdmi->dvi = false;
1334
1335 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1336 if (IS_ERR(hdmi->clk)) {
1337 dev_err(&pdev->dev, "failed to get clock\n");
1338 return PTR_ERR(hdmi->clk);
1339 }
1340
1341 err = clk_prepare(hdmi->clk);
1342 if (err < 0)
1343 return err;
1344
1345 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1346 if (IS_ERR(hdmi->clk_parent))
1347 return PTR_ERR(hdmi->clk_parent);
1348
1349 err = clk_prepare(hdmi->clk_parent);
1350 if (err < 0)
1351 return err;
1352
1353 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1354 if (err < 0) {
1355 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1356 return err;
1357 }
1358
1359 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1360 if (IS_ERR(hdmi->vdd)) {
1361 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1362 return PTR_ERR(hdmi->vdd);
1363 }
1364
1365 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1366 if (IS_ERR(hdmi->pll)) {
1367 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1368 return PTR_ERR(hdmi->pll);
1369 }
1370
1371 hdmi->output.dev = &pdev->dev;
1372
1373 err = tegra_output_probe(&hdmi->output);
1374 if (err < 0)
1375 return err;
1376
1377 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1378 if (!regs)
1379 return -ENXIO;
1380
1381 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1382 if (IS_ERR(hdmi->regs))
1383 return PTR_ERR(hdmi->regs);
1384
1385 err = platform_get_irq(pdev, 0);
1386 if (err < 0)
1387 return err;
1388
1389 hdmi->irq = err;
1390
1391 INIT_LIST_HEAD(&hdmi->client.list);
1392 hdmi->client.ops = &hdmi_client_ops;
1393 hdmi->client.dev = &pdev->dev;
1394
1395 err = host1x_client_register(&hdmi->client);
1396 if (err < 0) {
1397 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1398 err);
1399 return err;
1400 }
1401
1402 platform_set_drvdata(pdev, hdmi);
1403
1404 return 0;
1405 }
1406
1407 static int tegra_hdmi_remove(struct platform_device *pdev)
1408 {
1409 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1410 int err;
1411
1412 err = host1x_client_unregister(&hdmi->client);
1413 if (err < 0) {
1414 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1415 err);
1416 return err;
1417 }
1418
1419 err = tegra_output_remove(&hdmi->output);
1420 if (err < 0) {
1421 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
1422 return err;
1423 }
1424
1425 clk_unprepare(hdmi->clk_parent);
1426 clk_unprepare(hdmi->clk);
1427
1428 return 0;
1429 }
1430
1431 struct platform_driver tegra_hdmi_driver = {
1432 .driver = {
1433 .name = "tegra-hdmi",
1434 .owner = THIS_MODULE,
1435 .of_match_table = tegra_hdmi_of_match,
1436 },
1437 .probe = tegra_hdmi_probe,
1438 .remove = tegra_hdmi_remove,
1439 };
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