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Merge tag 'arc-4.13-rc7-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupt...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / host1x / cdma.h
1 /*
2 * Tegra host1x Command DMA
3 *
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #ifndef __HOST1X_CDMA_H
20 #define __HOST1X_CDMA_H
21
22 #include <linux/sched.h>
23 #include <linux/semaphore.h>
24 #include <linux/list.h>
25
26 struct host1x_syncpt;
27 struct host1x_userctx_timeout;
28 struct host1x_job;
29
30 /*
31 * cdma
32 *
33 * This is in charge of a host command DMA channel.
34 * Sends ops to a push buffer, and takes responsibility for unpinning
35 * (& possibly freeing) of memory after those ops have completed.
36 * Producer:
37 * begin
38 * push - send ops to the push buffer
39 * end - start command DMA and enqueue handles to be unpinned
40 * Consumer:
41 * update - call to update sync queue and push buffer, unpin memory
42 */
43
44 struct push_buffer {
45 void *mapped; /* mapped pushbuffer memory */
46 dma_addr_t dma; /* device address of pushbuffer */
47 phys_addr_t phys; /* physical address of pushbuffer */
48 u32 fence; /* index we've written */
49 u32 pos; /* index to write to */
50 u32 size;
51 u32 alloc_size;
52 };
53
54 struct buffer_timeout {
55 struct delayed_work wq; /* work queue */
56 bool initialized; /* timer one-time setup flag */
57 struct host1x_syncpt *syncpt; /* buffer completion syncpt */
58 u32 syncpt_val; /* syncpt value when completed */
59 ktime_t start_ktime; /* starting time */
60 /* context timeout information */
61 int client;
62 };
63
64 enum cdma_event {
65 CDMA_EVENT_NONE, /* not waiting for any event */
66 CDMA_EVENT_SYNC_QUEUE_EMPTY, /* wait for empty sync queue */
67 CDMA_EVENT_PUSH_BUFFER_SPACE /* wait for space in push buffer */
68 };
69
70 struct host1x_cdma {
71 struct mutex lock; /* controls access to shared state */
72 struct semaphore sem; /* signalled when event occurs */
73 enum cdma_event event; /* event that sem is waiting for */
74 unsigned int slots_used; /* pb slots used in current submit */
75 unsigned int slots_free; /* pb slots free in current submit */
76 unsigned int first_get; /* DMAGET value, where submit begins */
77 unsigned int last_pos; /* last value written to DMAPUT */
78 struct push_buffer push_buffer; /* channel's push buffer */
79 struct list_head sync_queue; /* job queue */
80 struct buffer_timeout timeout; /* channel's timeout state/wq */
81 bool running;
82 bool torndown;
83 };
84
85 #define cdma_to_channel(cdma) container_of(cdma, struct host1x_channel, cdma)
86 #define cdma_to_host1x(cdma) dev_get_drvdata(cdma_to_channel(cdma)->dev->parent)
87 #define pb_to_cdma(pb) container_of(pb, struct host1x_cdma, push_buffer)
88
89 int host1x_cdma_init(struct host1x_cdma *cdma);
90 int host1x_cdma_deinit(struct host1x_cdma *cdma);
91 int host1x_cdma_begin(struct host1x_cdma *cdma, struct host1x_job *job);
92 void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2);
93 void host1x_cdma_end(struct host1x_cdma *cdma, struct host1x_job *job);
94 void host1x_cdma_update(struct host1x_cdma *cdma);
95 void host1x_cdma_peek(struct host1x_cdma *cdma, u32 dmaget, int slot,
96 u32 *out);
97 unsigned int host1x_cdma_wait_locked(struct host1x_cdma *cdma,
98 enum cdma_event event);
99 void host1x_cdma_update_sync_queue(struct host1x_cdma *cdma,
100 struct device *dev);
101 #endif