2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Xudong Chen <xudong.chen@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/i2c.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
26 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/platform_device.h>
32 #include <linux/scatterlist.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
36 #define I2C_RS_TRANSFER (1 << 4)
37 #define I2C_HS_NACKERR (1 << 2)
38 #define I2C_ACKERR (1 << 1)
39 #define I2C_TRANSAC_COMP (1 << 0)
40 #define I2C_TRANSAC_START (1 << 0)
41 #define I2C_RS_MUL_CNFG (1 << 15)
42 #define I2C_RS_MUL_TRIG (1 << 14)
43 #define I2C_DCM_DISABLE 0x0000
44 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
45 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
46 #define I2C_SOFT_RST 0x0001
47 #define I2C_FIFO_ADDR_CLR 0x0001
48 #define I2C_DELAY_LEN 0x0002
49 #define I2C_ST_START_CON 0x8001
50 #define I2C_FS_START_CON 0x1800
51 #define I2C_TIME_CLR_VALUE 0x0000
52 #define I2C_TIME_DEFAULT_VALUE 0x0003
53 #define I2C_WRRD_TRANAC_VALUE 0x0002
54 #define I2C_RD_TRANAC_VALUE 0x0001
56 #define I2C_DMA_CON_TX 0x0000
57 #define I2C_DMA_CON_RX 0x0001
58 #define I2C_DMA_START_EN 0x0001
59 #define I2C_DMA_INT_FLAG_NONE 0x0000
60 #define I2C_DMA_CLR_FLAG 0x0000
61 #define I2C_DMA_HARD_RST 0x0002
62 #define I2C_DMA_4G_MODE 0x0001
64 #define I2C_DEFAULT_SPEED 100000 /* hz */
65 #define MAX_FS_MODE_SPEED 400000
66 #define MAX_HS_MODE_SPEED 3400000
67 #define MAX_SAMPLE_CNT_DIV 8
68 #define MAX_STEP_CNT_DIV 64
69 #define MAX_HS_STEP_CNT_DIV 8
71 #define I2C_CONTROL_RS (0x1 << 1)
72 #define I2C_CONTROL_DMA_EN (0x1 << 2)
73 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
74 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
75 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
76 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
77 #define I2C_CONTROL_WRAPPER (0x1 << 0)
79 #define I2C_DRV_NAME "i2c-mt65xx"
81 enum DMA_REGS_OFFSET
{
82 OFFSET_INT_FLAG
= 0x0,
87 OFFSET_TX_MEM_ADDR
= 0x1c,
88 OFFSET_RX_MEM_ADDR
= 0x20,
91 OFFSET_TX_4G_MODE
= 0x54,
92 OFFSET_RX_4G_MODE
= 0x58,
95 enum i2c_trans_st_rs
{
97 I2C_TRANS_REPEATED_START
,
106 enum I2C_REGS_OFFSET
{
107 OFFSET_DATA_PORT
= 0x0,
108 OFFSET_SLAVE_ADDR
= 0x04,
109 OFFSET_INTR_MASK
= 0x08,
110 OFFSET_INTR_STAT
= 0x0c,
111 OFFSET_CONTROL
= 0x10,
112 OFFSET_TRANSFER_LEN
= 0x14,
113 OFFSET_TRANSAC_LEN
= 0x18,
114 OFFSET_DELAY_LEN
= 0x1c,
115 OFFSET_TIMING
= 0x20,
117 OFFSET_EXT_CONF
= 0x28,
118 OFFSET_FIFO_STAT
= 0x30,
119 OFFSET_FIFO_THRESH
= 0x34,
120 OFFSET_FIFO_ADDR_CLR
= 0x38,
121 OFFSET_IO_CONFIG
= 0x40,
122 OFFSET_RSV_DEBUG
= 0x44,
124 OFFSET_SOFTRESET
= 0x50,
125 OFFSET_DCM_EN
= 0x54,
126 OFFSET_PATH_DIR
= 0x60,
127 OFFSET_DEBUGSTAT
= 0x64,
128 OFFSET_DEBUGCTRL
= 0x68,
129 OFFSET_TRANSFER_LEN_AUX
= 0x6c,
132 struct mtk_i2c_compatible
{
133 const struct i2c_adapter_quirks
*quirks
;
134 unsigned char pmic_i2c
: 1;
135 unsigned char dcm
: 1;
136 unsigned char auto_restart
: 1;
137 unsigned char aux_len_reg
: 1;
138 unsigned char support_33bits
: 1;
142 struct i2c_adapter adap
; /* i2c host adapter */
144 struct completion msg_complete
;
146 /* set in i2c probe */
147 void __iomem
*base
; /* i2c base addr */
148 void __iomem
*pdmabase
; /* dma base address*/
149 struct clk
*clk_main
; /* main clock for i2c bus */
150 struct clk
*clk_dma
; /* DMA clock for i2c via DMA */
151 struct clk
*clk_pmic
; /* PMIC clock for i2c from PMIC */
152 bool have_pmic
; /* can use i2c pins from PMIC */
153 bool use_push_pull
; /* IO config push-pull mode */
155 u16 irq_stat
; /* interrupt status */
156 unsigned int clk_src_div
;
157 unsigned int speed_hz
; /* The speed in transfer */
158 enum mtk_trans_op op
;
161 unsigned char auto_restart
;
162 bool ignore_restart_irq
;
163 const struct mtk_i2c_compatible
*dev_comp
;
166 static const struct i2c_adapter_quirks mt6577_i2c_quirks
= {
167 .flags
= I2C_AQ_COMB_WRITE_THEN_READ
,
169 .max_write_len
= 255,
171 .max_comb_1st_msg_len
= 255,
172 .max_comb_2nd_msg_len
= 31,
175 static const struct i2c_adapter_quirks mt7622_i2c_quirks
= {
179 static const struct mtk_i2c_compatible mt6577_compat
= {
180 .quirks
= &mt6577_i2c_quirks
,
188 static const struct mtk_i2c_compatible mt6589_compat
= {
189 .quirks
= &mt6577_i2c_quirks
,
197 static const struct mtk_i2c_compatible mt7622_compat
= {
198 .quirks
= &mt7622_i2c_quirks
,
206 static const struct mtk_i2c_compatible mt8173_compat
= {
214 static const struct of_device_id mtk_i2c_of_match
[] = {
215 { .compatible
= "mediatek,mt6577-i2c", .data
= &mt6577_compat
},
216 { .compatible
= "mediatek,mt6589-i2c", .data
= &mt6589_compat
},
217 { .compatible
= "mediatek,mt7622-i2c", .data
= &mt7622_compat
},
218 { .compatible
= "mediatek,mt8173-i2c", .data
= &mt8173_compat
},
221 MODULE_DEVICE_TABLE(of
, mtk_i2c_of_match
);
223 static int mtk_i2c_clock_enable(struct mtk_i2c
*i2c
)
227 ret
= clk_prepare_enable(i2c
->clk_dma
);
231 ret
= clk_prepare_enable(i2c
->clk_main
);
235 if (i2c
->have_pmic
) {
236 ret
= clk_prepare_enable(i2c
->clk_pmic
);
243 clk_disable_unprepare(i2c
->clk_main
);
245 clk_disable_unprepare(i2c
->clk_dma
);
250 static void mtk_i2c_clock_disable(struct mtk_i2c
*i2c
)
253 clk_disable_unprepare(i2c
->clk_pmic
);
255 clk_disable_unprepare(i2c
->clk_main
);
256 clk_disable_unprepare(i2c
->clk_dma
);
259 static void mtk_i2c_init_hw(struct mtk_i2c
*i2c
)
263 writew(I2C_SOFT_RST
, i2c
->base
+ OFFSET_SOFTRESET
);
266 if (i2c
->use_push_pull
)
267 writew(I2C_IO_CONFIG_PUSH_PULL
, i2c
->base
+ OFFSET_IO_CONFIG
);
269 writew(I2C_IO_CONFIG_OPEN_DRAIN
, i2c
->base
+ OFFSET_IO_CONFIG
);
271 if (i2c
->dev_comp
->dcm
)
272 writew(I2C_DCM_DISABLE
, i2c
->base
+ OFFSET_DCM_EN
);
274 writew(i2c
->timing_reg
, i2c
->base
+ OFFSET_TIMING
);
275 writew(i2c
->high_speed_reg
, i2c
->base
+ OFFSET_HS
);
277 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
279 writew(I2C_CONTROL_WRAPPER
, i2c
->base
+ OFFSET_PATH_DIR
);
281 control_reg
= I2C_CONTROL_ACKERR_DET_EN
|
282 I2C_CONTROL_CLK_EXT_EN
| I2C_CONTROL_DMA_EN
;
283 writew(control_reg
, i2c
->base
+ OFFSET_CONTROL
);
284 writew(I2C_DELAY_LEN
, i2c
->base
+ OFFSET_DELAY_LEN
);
286 writel(I2C_DMA_HARD_RST
, i2c
->pdmabase
+ OFFSET_RST
);
288 writel(I2C_DMA_CLR_FLAG
, i2c
->pdmabase
+ OFFSET_RST
);
292 * Calculate i2c port speed
295 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
296 * clock_div: fixed in hardware, but may be various in different SoCs
298 * The calculation want to pick the highest bus frequency that is still
299 * less than or equal to i2c->speed_hz. The calculation try to get
300 * sample_cnt and step_cn
302 static int mtk_i2c_calculate_speed(struct mtk_i2c
*i2c
, unsigned int clk_src
,
303 unsigned int target_speed
,
304 unsigned int *timing_step_cnt
,
305 unsigned int *timing_sample_cnt
)
307 unsigned int step_cnt
;
308 unsigned int sample_cnt
;
309 unsigned int max_step_cnt
;
310 unsigned int base_sample_cnt
= MAX_SAMPLE_CNT_DIV
;
311 unsigned int base_step_cnt
;
312 unsigned int opt_div
;
313 unsigned int best_mul
;
314 unsigned int cnt_mul
;
316 if (target_speed
> MAX_HS_MODE_SPEED
)
317 target_speed
= MAX_HS_MODE_SPEED
;
319 if (target_speed
> MAX_FS_MODE_SPEED
)
320 max_step_cnt
= MAX_HS_STEP_CNT_DIV
;
322 max_step_cnt
= MAX_STEP_CNT_DIV
;
324 base_step_cnt
= max_step_cnt
;
325 /* Find the best combination */
326 opt_div
= DIV_ROUND_UP(clk_src
>> 1, target_speed
);
327 best_mul
= MAX_SAMPLE_CNT_DIV
* max_step_cnt
;
329 /* Search for the best pair (sample_cnt, step_cnt) with
330 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
331 * 0 < step_cnt < max_step_cnt
332 * sample_cnt * step_cnt >= opt_div
333 * optimizing for sample_cnt * step_cnt being minimal
335 for (sample_cnt
= 1; sample_cnt
<= MAX_SAMPLE_CNT_DIV
; sample_cnt
++) {
336 step_cnt
= DIV_ROUND_UP(opt_div
, sample_cnt
);
337 cnt_mul
= step_cnt
* sample_cnt
;
338 if (step_cnt
> max_step_cnt
)
341 if (cnt_mul
< best_mul
) {
343 base_sample_cnt
= sample_cnt
;
344 base_step_cnt
= step_cnt
;
345 if (best_mul
== opt_div
)
350 sample_cnt
= base_sample_cnt
;
351 step_cnt
= base_step_cnt
;
353 if ((clk_src
/ (2 * sample_cnt
* step_cnt
)) > target_speed
) {
354 /* In this case, hardware can't support such
357 dev_dbg(i2c
->dev
, "Unsupported speed (%uhz)\n", target_speed
);
361 *timing_step_cnt
= step_cnt
- 1;
362 *timing_sample_cnt
= sample_cnt
- 1;
367 static int mtk_i2c_set_speed(struct mtk_i2c
*i2c
, unsigned int parent_clk
)
369 unsigned int clk_src
;
370 unsigned int step_cnt
;
371 unsigned int sample_cnt
;
372 unsigned int target_speed
;
375 clk_src
= parent_clk
/ i2c
->clk_src_div
;
376 target_speed
= i2c
->speed_hz
;
378 if (target_speed
> MAX_FS_MODE_SPEED
) {
379 /* Set master code speed register */
380 ret
= mtk_i2c_calculate_speed(i2c
, clk_src
, MAX_FS_MODE_SPEED
,
381 &step_cnt
, &sample_cnt
);
385 i2c
->timing_reg
= (sample_cnt
<< 8) | step_cnt
;
387 /* Set the high speed mode register */
388 ret
= mtk_i2c_calculate_speed(i2c
, clk_src
, target_speed
,
389 &step_cnt
, &sample_cnt
);
393 i2c
->high_speed_reg
= I2C_TIME_DEFAULT_VALUE
|
394 (sample_cnt
<< 12) | (step_cnt
<< 8);
396 ret
= mtk_i2c_calculate_speed(i2c
, clk_src
, target_speed
,
397 &step_cnt
, &sample_cnt
);
401 i2c
->timing_reg
= (sample_cnt
<< 8) | step_cnt
;
403 /* Disable the high speed transaction */
404 i2c
->high_speed_reg
= I2C_TIME_CLR_VALUE
;
410 static inline u32
mtk_i2c_set_4g_mode(dma_addr_t addr
)
412 return (addr
& BIT_ULL(32)) ? I2C_DMA_4G_MODE
: I2C_DMA_CLR_FLAG
;
415 static int mtk_i2c_do_transfer(struct mtk_i2c
*i2c
, struct i2c_msg
*msgs
,
416 int num
, int left_num
)
421 u16 restart_flag
= 0;
423 dma_addr_t rpaddr
= 0;
424 dma_addr_t wpaddr
= 0;
429 if (i2c
->auto_restart
)
430 restart_flag
= I2C_RS_TRANSFER
;
432 reinit_completion(&i2c
->msg_complete
);
434 control_reg
= readw(i2c
->base
+ OFFSET_CONTROL
) &
435 ~(I2C_CONTROL_DIR_CHANGE
| I2C_CONTROL_RS
);
436 if ((i2c
->speed_hz
> 400000) || (left_num
>= 1))
437 control_reg
|= I2C_CONTROL_RS
;
439 if (i2c
->op
== I2C_MASTER_WRRD
)
440 control_reg
|= I2C_CONTROL_DIR_CHANGE
| I2C_CONTROL_RS
;
442 writew(control_reg
, i2c
->base
+ OFFSET_CONTROL
);
444 /* set start condition */
445 if (i2c
->speed_hz
<= 100000)
446 writew(I2C_ST_START_CON
, i2c
->base
+ OFFSET_EXT_CONF
);
448 writew(I2C_FS_START_CON
, i2c
->base
+ OFFSET_EXT_CONF
);
450 addr_reg
= i2c_8bit_addr_from_msg(msgs
);
451 writew(addr_reg
, i2c
->base
+ OFFSET_SLAVE_ADDR
);
453 /* Clear interrupt status */
454 writew(restart_flag
| I2C_HS_NACKERR
| I2C_ACKERR
|
455 I2C_TRANSAC_COMP
, i2c
->base
+ OFFSET_INTR_STAT
);
456 writew(I2C_FIFO_ADDR_CLR
, i2c
->base
+ OFFSET_FIFO_ADDR_CLR
);
458 /* Enable interrupt */
459 writew(restart_flag
| I2C_HS_NACKERR
| I2C_ACKERR
|
460 I2C_TRANSAC_COMP
, i2c
->base
+ OFFSET_INTR_MASK
);
462 /* Set transfer and transaction len */
463 if (i2c
->op
== I2C_MASTER_WRRD
) {
464 if (i2c
->dev_comp
->aux_len_reg
) {
465 writew(msgs
->len
, i2c
->base
+ OFFSET_TRANSFER_LEN
);
466 writew((msgs
+ 1)->len
, i2c
->base
+
467 OFFSET_TRANSFER_LEN_AUX
);
469 writew(msgs
->len
| ((msgs
+ 1)->len
) << 8,
470 i2c
->base
+ OFFSET_TRANSFER_LEN
);
472 writew(I2C_WRRD_TRANAC_VALUE
, i2c
->base
+ OFFSET_TRANSAC_LEN
);
474 writew(msgs
->len
, i2c
->base
+ OFFSET_TRANSFER_LEN
);
475 writew(num
, i2c
->base
+ OFFSET_TRANSAC_LEN
);
478 /* Prepare buffer data to start transfer */
479 if (i2c
->op
== I2C_MASTER_RD
) {
480 writel(I2C_DMA_INT_FLAG_NONE
, i2c
->pdmabase
+ OFFSET_INT_FLAG
);
481 writel(I2C_DMA_CON_RX
, i2c
->pdmabase
+ OFFSET_CON
);
482 rpaddr
= dma_map_single(i2c
->dev
, msgs
->buf
,
483 msgs
->len
, DMA_FROM_DEVICE
);
484 if (dma_mapping_error(i2c
->dev
, rpaddr
))
487 if (i2c
->dev_comp
->support_33bits
) {
488 reg_4g_mode
= mtk_i2c_set_4g_mode(rpaddr
);
489 writel(reg_4g_mode
, i2c
->pdmabase
+ OFFSET_RX_4G_MODE
);
492 writel((u32
)rpaddr
, i2c
->pdmabase
+ OFFSET_RX_MEM_ADDR
);
493 writel(msgs
->len
, i2c
->pdmabase
+ OFFSET_RX_LEN
);
494 } else if (i2c
->op
== I2C_MASTER_WR
) {
495 writel(I2C_DMA_INT_FLAG_NONE
, i2c
->pdmabase
+ OFFSET_INT_FLAG
);
496 writel(I2C_DMA_CON_TX
, i2c
->pdmabase
+ OFFSET_CON
);
497 wpaddr
= dma_map_single(i2c
->dev
, msgs
->buf
,
498 msgs
->len
, DMA_TO_DEVICE
);
499 if (dma_mapping_error(i2c
->dev
, wpaddr
))
502 if (i2c
->dev_comp
->support_33bits
) {
503 reg_4g_mode
= mtk_i2c_set_4g_mode(wpaddr
);
504 writel(reg_4g_mode
, i2c
->pdmabase
+ OFFSET_TX_4G_MODE
);
507 writel((u32
)wpaddr
, i2c
->pdmabase
+ OFFSET_TX_MEM_ADDR
);
508 writel(msgs
->len
, i2c
->pdmabase
+ OFFSET_TX_LEN
);
510 writel(I2C_DMA_CLR_FLAG
, i2c
->pdmabase
+ OFFSET_INT_FLAG
);
511 writel(I2C_DMA_CLR_FLAG
, i2c
->pdmabase
+ OFFSET_CON
);
512 wpaddr
= dma_map_single(i2c
->dev
, msgs
->buf
,
513 msgs
->len
, DMA_TO_DEVICE
);
514 if (dma_mapping_error(i2c
->dev
, wpaddr
))
516 rpaddr
= dma_map_single(i2c
->dev
, (msgs
+ 1)->buf
,
519 if (dma_mapping_error(i2c
->dev
, rpaddr
)) {
520 dma_unmap_single(i2c
->dev
, wpaddr
,
521 msgs
->len
, DMA_TO_DEVICE
);
525 if (i2c
->dev_comp
->support_33bits
) {
526 reg_4g_mode
= mtk_i2c_set_4g_mode(wpaddr
);
527 writel(reg_4g_mode
, i2c
->pdmabase
+ OFFSET_TX_4G_MODE
);
529 reg_4g_mode
= mtk_i2c_set_4g_mode(rpaddr
);
530 writel(reg_4g_mode
, i2c
->pdmabase
+ OFFSET_RX_4G_MODE
);
533 writel((u32
)wpaddr
, i2c
->pdmabase
+ OFFSET_TX_MEM_ADDR
);
534 writel((u32
)rpaddr
, i2c
->pdmabase
+ OFFSET_RX_MEM_ADDR
);
535 writel(msgs
->len
, i2c
->pdmabase
+ OFFSET_TX_LEN
);
536 writel((msgs
+ 1)->len
, i2c
->pdmabase
+ OFFSET_RX_LEN
);
539 writel(I2C_DMA_START_EN
, i2c
->pdmabase
+ OFFSET_EN
);
541 if (!i2c
->auto_restart
) {
542 start_reg
= I2C_TRANSAC_START
;
544 start_reg
= I2C_TRANSAC_START
| I2C_RS_MUL_TRIG
;
546 start_reg
|= I2C_RS_MUL_CNFG
;
548 writew(start_reg
, i2c
->base
+ OFFSET_START
);
550 ret
= wait_for_completion_timeout(&i2c
->msg_complete
,
553 /* Clear interrupt mask */
554 writew(~(restart_flag
| I2C_HS_NACKERR
| I2C_ACKERR
|
555 I2C_TRANSAC_COMP
), i2c
->base
+ OFFSET_INTR_MASK
);
557 if (i2c
->op
== I2C_MASTER_WR
) {
558 dma_unmap_single(i2c
->dev
, wpaddr
,
559 msgs
->len
, DMA_TO_DEVICE
);
560 } else if (i2c
->op
== I2C_MASTER_RD
) {
561 dma_unmap_single(i2c
->dev
, rpaddr
,
562 msgs
->len
, DMA_FROM_DEVICE
);
564 dma_unmap_single(i2c
->dev
, wpaddr
, msgs
->len
,
566 dma_unmap_single(i2c
->dev
, rpaddr
, (msgs
+ 1)->len
,
571 dev_dbg(i2c
->dev
, "addr: %x, transfer timeout\n", msgs
->addr
);
572 mtk_i2c_init_hw(i2c
);
576 completion_done(&i2c
->msg_complete
);
578 if (i2c
->irq_stat
& (I2C_HS_NACKERR
| I2C_ACKERR
)) {
579 dev_dbg(i2c
->dev
, "addr: %x, transfer ACK error\n", msgs
->addr
);
580 mtk_i2c_init_hw(i2c
);
587 static int mtk_i2c_transfer(struct i2c_adapter
*adap
,
588 struct i2c_msg msgs
[], int num
)
592 struct mtk_i2c
*i2c
= i2c_get_adapdata(adap
);
594 ret
= mtk_i2c_clock_enable(i2c
);
598 i2c
->auto_restart
= i2c
->dev_comp
->auto_restart
;
600 /* checking if we can skip restart and optimize using WRRD mode */
601 if (i2c
->auto_restart
&& num
== 2) {
602 if (!(msgs
[0].flags
& I2C_M_RD
) && (msgs
[1].flags
& I2C_M_RD
) &&
603 msgs
[0].addr
== msgs
[1].addr
) {
604 i2c
->auto_restart
= 0;
608 if (i2c
->auto_restart
&& num
>= 2 && i2c
->speed_hz
> MAX_FS_MODE_SPEED
)
609 /* ignore the first restart irq after the master code,
610 * otherwise the first transfer will be discarded.
612 i2c
->ignore_restart_irq
= true;
614 i2c
->ignore_restart_irq
= false;
618 dev_dbg(i2c
->dev
, "data buffer is NULL.\n");
623 if (msgs
->flags
& I2C_M_RD
)
624 i2c
->op
= I2C_MASTER_RD
;
626 i2c
->op
= I2C_MASTER_WR
;
628 if (!i2c
->auto_restart
) {
630 /* combined two messages into one transaction */
631 i2c
->op
= I2C_MASTER_WRRD
;
636 /* always use DMA mode. */
637 ret
= mtk_i2c_do_transfer(i2c
, msgs
, num
, left_num
);
643 /* the return value is number of executed messages */
647 mtk_i2c_clock_disable(i2c
);
651 static irqreturn_t
mtk_i2c_irq(int irqno
, void *dev_id
)
653 struct mtk_i2c
*i2c
= dev_id
;
654 u16 restart_flag
= 0;
657 if (i2c
->auto_restart
)
658 restart_flag
= I2C_RS_TRANSFER
;
660 intr_stat
= readw(i2c
->base
+ OFFSET_INTR_STAT
);
661 writew(intr_stat
, i2c
->base
+ OFFSET_INTR_STAT
);
664 * when occurs ack error, i2c controller generate two interrupts
665 * first is the ack error interrupt, then the complete interrupt
666 * i2c->irq_stat need keep the two interrupt value.
668 i2c
->irq_stat
|= intr_stat
;
670 if (i2c
->ignore_restart_irq
&& (i2c
->irq_stat
& restart_flag
)) {
671 i2c
->ignore_restart_irq
= false;
673 writew(I2C_RS_MUL_CNFG
| I2C_RS_MUL_TRIG
| I2C_TRANSAC_START
,
674 i2c
->base
+ OFFSET_START
);
676 if (i2c
->irq_stat
& (I2C_TRANSAC_COMP
| restart_flag
))
677 complete(&i2c
->msg_complete
);
683 static u32
mtk_i2c_functionality(struct i2c_adapter
*adap
)
685 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
688 static const struct i2c_algorithm mtk_i2c_algorithm
= {
689 .master_xfer
= mtk_i2c_transfer
,
690 .functionality
= mtk_i2c_functionality
,
693 static int mtk_i2c_parse_dt(struct device_node
*np
, struct mtk_i2c
*i2c
)
697 ret
= of_property_read_u32(np
, "clock-frequency", &i2c
->speed_hz
);
699 i2c
->speed_hz
= I2C_DEFAULT_SPEED
;
701 ret
= of_property_read_u32(np
, "clock-div", &i2c
->clk_src_div
);
705 if (i2c
->clk_src_div
== 0)
708 i2c
->have_pmic
= of_property_read_bool(np
, "mediatek,have-pmic");
710 of_property_read_bool(np
, "mediatek,use-push-pull");
715 static int mtk_i2c_probe(struct platform_device
*pdev
)
717 const struct of_device_id
*of_id
;
721 struct resource
*res
;
724 i2c
= devm_kzalloc(&pdev
->dev
, sizeof(*i2c
), GFP_KERNEL
);
728 ret
= mtk_i2c_parse_dt(pdev
->dev
.of_node
, i2c
);
732 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
733 i2c
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
734 if (IS_ERR(i2c
->base
))
735 return PTR_ERR(i2c
->base
);
737 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
738 i2c
->pdmabase
= devm_ioremap_resource(&pdev
->dev
, res
);
739 if (IS_ERR(i2c
->pdmabase
))
740 return PTR_ERR(i2c
->pdmabase
);
742 irq
= platform_get_irq(pdev
, 0);
746 init_completion(&i2c
->msg_complete
);
748 of_id
= of_match_node(mtk_i2c_of_match
, pdev
->dev
.of_node
);
752 i2c
->dev_comp
= of_id
->data
;
753 i2c
->adap
.dev
.of_node
= pdev
->dev
.of_node
;
754 i2c
->dev
= &pdev
->dev
;
755 i2c
->adap
.dev
.parent
= &pdev
->dev
;
756 i2c
->adap
.owner
= THIS_MODULE
;
757 i2c
->adap
.algo
= &mtk_i2c_algorithm
;
758 i2c
->adap
.quirks
= i2c
->dev_comp
->quirks
;
759 i2c
->adap
.timeout
= 2 * HZ
;
760 i2c
->adap
.retries
= 1;
762 if (i2c
->have_pmic
&& !i2c
->dev_comp
->pmic_i2c
)
765 i2c
->clk_main
= devm_clk_get(&pdev
->dev
, "main");
766 if (IS_ERR(i2c
->clk_main
)) {
767 dev_err(&pdev
->dev
, "cannot get main clock\n");
768 return PTR_ERR(i2c
->clk_main
);
771 i2c
->clk_dma
= devm_clk_get(&pdev
->dev
, "dma");
772 if (IS_ERR(i2c
->clk_dma
)) {
773 dev_err(&pdev
->dev
, "cannot get dma clock\n");
774 return PTR_ERR(i2c
->clk_dma
);
778 if (i2c
->have_pmic
) {
779 i2c
->clk_pmic
= devm_clk_get(&pdev
->dev
, "pmic");
780 if (IS_ERR(i2c
->clk_pmic
)) {
781 dev_err(&pdev
->dev
, "cannot get pmic clock\n");
782 return PTR_ERR(i2c
->clk_pmic
);
787 strlcpy(i2c
->adap
.name
, I2C_DRV_NAME
, sizeof(i2c
->adap
.name
));
789 ret
= mtk_i2c_set_speed(i2c
, clk_get_rate(clk
));
791 dev_err(&pdev
->dev
, "Failed to set the speed.\n");
795 if (i2c
->dev_comp
->support_33bits
) {
796 ret
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(33));
798 dev_err(&pdev
->dev
, "dma_set_mask return error.\n");
803 ret
= mtk_i2c_clock_enable(i2c
);
805 dev_err(&pdev
->dev
, "clock enable failed!\n");
808 mtk_i2c_init_hw(i2c
);
809 mtk_i2c_clock_disable(i2c
);
811 ret
= devm_request_irq(&pdev
->dev
, irq
, mtk_i2c_irq
,
812 IRQF_TRIGGER_NONE
, I2C_DRV_NAME
, i2c
);
815 "Request I2C IRQ %d fail\n", irq
);
819 i2c_set_adapdata(&i2c
->adap
, i2c
);
820 ret
= i2c_add_adapter(&i2c
->adap
);
824 platform_set_drvdata(pdev
, i2c
);
829 static int mtk_i2c_remove(struct platform_device
*pdev
)
831 struct mtk_i2c
*i2c
= platform_get_drvdata(pdev
);
833 i2c_del_adapter(&i2c
->adap
);
838 #ifdef CONFIG_PM_SLEEP
839 static int mtk_i2c_resume(struct device
*dev
)
841 struct mtk_i2c
*i2c
= dev_get_drvdata(dev
);
843 mtk_i2c_init_hw(i2c
);
849 static const struct dev_pm_ops mtk_i2c_pm
= {
850 SET_SYSTEM_SLEEP_PM_OPS(NULL
, mtk_i2c_resume
)
853 static struct platform_driver mtk_i2c_driver
= {
854 .probe
= mtk_i2c_probe
,
855 .remove
= mtk_i2c_remove
,
857 .name
= I2C_DRV_NAME
,
859 .of_match_table
= of_match_ptr(mtk_i2c_of_match
),
863 module_platform_driver(mtk_i2c_driver
);
865 MODULE_LICENSE("GPL v2");
866 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
867 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");