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UBUNTU: SAUCE: i2c:amd move out pointer in union i2c_event_base
[mirror_ubuntu-bionic-kernel.git] / drivers / i2c / busses / i2c-sh_mobile.c
1 /*
2 * SuperH Mobile I2C Controller
3 *
4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
5 *
6 * Copyright (C) 2008 Magnus Damm
7 *
8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/dmaengine.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/err.h>
26 #include <linux/i2c.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/of_device.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/slab.h>
36
37 /* Transmit operation: */
38 /* */
39 /* 0 byte transmit */
40 /* BUS: S A8 ACK P(*) */
41 /* IRQ: DTE WAIT */
42 /* ICIC: */
43 /* ICCR: 0x94 0x90 */
44 /* ICDR: A8 */
45 /* */
46 /* 1 byte transmit */
47 /* BUS: S A8 ACK D8(1) ACK P(*) */
48 /* IRQ: DTE WAIT WAIT */
49 /* ICIC: -DTE */
50 /* ICCR: 0x94 0x90 */
51 /* ICDR: A8 D8(1) */
52 /* */
53 /* 2 byte transmit */
54 /* BUS: S A8 ACK D8(1) ACK D8(2) ACK P(*) */
55 /* IRQ: DTE WAIT WAIT WAIT */
56 /* ICIC: -DTE */
57 /* ICCR: 0x94 0x90 */
58 /* ICDR: A8 D8(1) D8(2) */
59 /* */
60 /* 3 bytes or more, +---------+ gets repeated */
61 /* */
62 /* */
63 /* Receive operation: */
64 /* */
65 /* 0 byte receive - not supported since slave may hold SDA low */
66 /* */
67 /* 1 byte receive [TX] | [RX] */
68 /* BUS: S A8 ACK | D8(1) ACK P(*) */
69 /* IRQ: DTE WAIT | WAIT DTE */
70 /* ICIC: -DTE | +DTE */
71 /* ICCR: 0x94 0x81 | 0xc0 */
72 /* ICDR: A8 | D8(1) */
73 /* */
74 /* 2 byte receive [TX]| [RX] */
75 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK P(*) */
76 /* IRQ: DTE WAIT | WAIT WAIT DTE */
77 /* ICIC: -DTE | +DTE */
78 /* ICCR: 0x94 0x81 | 0xc0 */
79 /* ICDR: A8 | D8(1) D8(2) */
80 /* */
81 /* 3 byte receive [TX] | [RX] (*) */
82 /* BUS: S A8 ACK | D8(1) ACK D8(2) ACK D8(3) ACK P */
83 /* IRQ: DTE WAIT | WAIT WAIT WAIT DTE */
84 /* ICIC: -DTE | +DTE */
85 /* ICCR: 0x94 0x81 | 0xc0 */
86 /* ICDR: A8 | D8(1) D8(2) D8(3) */
87 /* */
88 /* 4 bytes or more, this part is repeated +---------+ */
89 /* */
90 /* */
91 /* Interrupt order and BUSY flag */
92 /* ___ _ */
93 /* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/ */
94 /* SCL \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/ */
95 /* */
96 /* S D7 D6 D5 D4 D3 D2 D1 D0 P(*) */
97 /* ___ */
98 /* WAIT IRQ ________________________________/ \___________ */
99 /* TACK IRQ ____________________________________/ \_______ */
100 /* DTE IRQ __________________________________________/ \_ */
101 /* AL IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX */
102 /* _______________________________________________ */
103 /* BUSY __/ \_ */
104 /* */
105 /* (*) The STOP condition is only sent by the master at the end of the last */
106 /* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
107 /* only cleared after the STOP condition, so, between messages we have to */
108 /* poll for the DTE bit. */
109 /* */
110
111 enum sh_mobile_i2c_op {
112 OP_START = 0,
113 OP_TX_FIRST,
114 OP_TX,
115 OP_TX_STOP,
116 OP_TX_STOP_DATA,
117 OP_TX_TO_RX,
118 OP_RX,
119 OP_RX_STOP,
120 OP_RX_STOP_DATA,
121 };
122
123 struct sh_mobile_i2c_data {
124 struct device *dev;
125 void __iomem *reg;
126 struct i2c_adapter adap;
127 unsigned long bus_speed;
128 unsigned int clks_per_count;
129 struct clk *clk;
130 u_int8_t icic;
131 u_int8_t flags;
132 u_int16_t iccl;
133 u_int16_t icch;
134
135 spinlock_t lock;
136 wait_queue_head_t wait;
137 struct i2c_msg *msg;
138 int pos;
139 int sr;
140 bool send_stop;
141 bool stop_after_dma;
142
143 struct resource *res;
144 struct dma_chan *dma_tx;
145 struct dma_chan *dma_rx;
146 struct scatterlist sg;
147 enum dma_data_direction dma_direction;
148 };
149
150 struct sh_mobile_dt_config {
151 int clks_per_count;
152 void (*setup)(struct sh_mobile_i2c_data *pd);
153 };
154
155 #define IIC_FLAG_HAS_ICIC67 (1 << 0)
156
157 #define STANDARD_MODE 100000
158 #define FAST_MODE 400000
159
160 /* Register offsets */
161 #define ICDR 0x00
162 #define ICCR 0x04
163 #define ICSR 0x08
164 #define ICIC 0x0c
165 #define ICCL 0x10
166 #define ICCH 0x14
167 #define ICSTART 0x70
168
169 /* Register bits */
170 #define ICCR_ICE 0x80
171 #define ICCR_RACK 0x40
172 #define ICCR_TRS 0x10
173 #define ICCR_BBSY 0x04
174 #define ICCR_SCP 0x01
175
176 #define ICSR_SCLM 0x80
177 #define ICSR_SDAM 0x40
178 #define SW_DONE 0x20
179 #define ICSR_BUSY 0x10
180 #define ICSR_AL 0x08
181 #define ICSR_TACK 0x04
182 #define ICSR_WAIT 0x02
183 #define ICSR_DTE 0x01
184
185 #define ICIC_ICCLB8 0x80
186 #define ICIC_ICCHB8 0x40
187 #define ICIC_TDMAE 0x20
188 #define ICIC_RDMAE 0x10
189 #define ICIC_ALE 0x08
190 #define ICIC_TACKE 0x04
191 #define ICIC_WAITE 0x02
192 #define ICIC_DTEE 0x01
193
194 #define ICSTART_ICSTART 0x10
195
196 static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
197 {
198 if (offs == ICIC)
199 data |= pd->icic;
200
201 iowrite8(data, pd->reg + offs);
202 }
203
204 static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
205 {
206 return ioread8(pd->reg + offs);
207 }
208
209 static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
210 unsigned char set, unsigned char clr)
211 {
212 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
213 }
214
215 static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
216 {
217 /*
218 * Conditional expression:
219 * ICCL >= COUNT_CLK * (tLOW + tf)
220 *
221 * SH-Mobile IIC hardware starts counting the LOW period of
222 * the SCL signal (tLOW) as soon as it pulls the SCL line.
223 * In order to meet the tLOW timing spec, we need to take into
224 * account the fall time of SCL signal (tf). Default tf value
225 * should be 0.3 us, for safety.
226 */
227 return (((count_khz * (tLOW + tf)) + 5000) / 10000);
228 }
229
230 static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
231 {
232 /*
233 * Conditional expression:
234 * ICCH >= COUNT_CLK * (tHIGH + tf)
235 *
236 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
237 * and can ignore it. SH-Mobile IIC controller starts counting
238 * the HIGH period of the SCL signal (tHIGH) after the SCL input
239 * voltage increases at VIH.
240 *
241 * Afterward it turned out calculating ICCH using only tHIGH spec
242 * will result in violation of the tHD;STA timing spec. We need
243 * to take into account the fall time of SDA signal (tf) at START
244 * condition, in order to meet both tHIGH and tHD;STA specs.
245 */
246 return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
247 }
248
249 static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
250 {
251 unsigned long i2c_clk_khz;
252 u32 tHIGH, tLOW, tf;
253 uint16_t max_val;
254
255 /* Get clock rate after clock is enabled */
256 clk_prepare_enable(pd->clk);
257 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
258 clk_disable_unprepare(pd->clk);
259 i2c_clk_khz /= pd->clks_per_count;
260
261 if (pd->bus_speed == STANDARD_MODE) {
262 tLOW = 47; /* tLOW = 4.7 us */
263 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
264 tf = 3; /* tf = 0.3 us */
265 } else if (pd->bus_speed == FAST_MODE) {
266 tLOW = 13; /* tLOW = 1.3 us */
267 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
268 tf = 3; /* tf = 0.3 us */
269 } else {
270 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
271 pd->bus_speed);
272 return -EINVAL;
273 }
274
275 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
276 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
277
278 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
279 if (pd->iccl > max_val || pd->icch > max_val) {
280 dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
281 pd->iccl, pd->icch);
282 return -EINVAL;
283 }
284
285 /* one more bit of ICCL in ICIC */
286 if (pd->iccl & 0x100)
287 pd->icic |= ICIC_ICCLB8;
288 else
289 pd->icic &= ~ICIC_ICCLB8;
290
291 /* one more bit of ICCH in ICIC */
292 if (pd->icch & 0x100)
293 pd->icic |= ICIC_ICCHB8;
294 else
295 pd->icic &= ~ICIC_ICCHB8;
296
297 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
298 return 0;
299 }
300
301 static void activate_ch(struct sh_mobile_i2c_data *pd)
302 {
303 /* Wake up device and enable clock */
304 pm_runtime_get_sync(pd->dev);
305 clk_prepare_enable(pd->clk);
306
307 /* Enable channel and configure rx ack */
308 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
309
310 /* Mask all interrupts */
311 iic_wr(pd, ICIC, 0);
312
313 /* Set the clock */
314 iic_wr(pd, ICCL, pd->iccl & 0xff);
315 iic_wr(pd, ICCH, pd->icch & 0xff);
316 }
317
318 static void deactivate_ch(struct sh_mobile_i2c_data *pd)
319 {
320 /* Clear/disable interrupts */
321 iic_wr(pd, ICSR, 0);
322 iic_wr(pd, ICIC, 0);
323
324 /* Disable channel */
325 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
326
327 /* Disable clock and mark device as idle */
328 clk_disable_unprepare(pd->clk);
329 pm_runtime_put_sync(pd->dev);
330 }
331
332 static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
333 enum sh_mobile_i2c_op op, unsigned char data)
334 {
335 unsigned char ret = 0;
336 unsigned long flags;
337
338 dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
339
340 spin_lock_irqsave(&pd->lock, flags);
341
342 switch (op) {
343 case OP_START: /* issue start and trigger DTE interrupt */
344 iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
345 break;
346 case OP_TX_FIRST: /* disable DTE interrupt and write data */
347 iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
348 iic_wr(pd, ICDR, data);
349 break;
350 case OP_TX: /* write data */
351 iic_wr(pd, ICDR, data);
352 break;
353 case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
354 iic_wr(pd, ICDR, data);
355 /* fallthrough */
356 case OP_TX_STOP: /* issue a stop */
357 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
358 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
359 break;
360 case OP_TX_TO_RX: /* select read mode */
361 iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
362 break;
363 case OP_RX: /* just read data */
364 ret = iic_rd(pd, ICDR);
365 break;
366 case OP_RX_STOP: /* enable DTE interrupt, issue stop */
367 iic_wr(pd, ICIC,
368 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
369 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
370 break;
371 case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
372 iic_wr(pd, ICIC,
373 ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
374 ret = iic_rd(pd, ICDR);
375 iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
376 break;
377 }
378
379 spin_unlock_irqrestore(&pd->lock, flags);
380
381 dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
382 return ret;
383 }
384
385 static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
386 {
387 return pd->pos == -1;
388 }
389
390 static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
391 {
392 return pd->pos == pd->msg->len - 1;
393 }
394
395 static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
396 unsigned char *buf)
397 {
398 switch (pd->pos) {
399 case -1:
400 *buf = i2c_8bit_addr_from_msg(pd->msg);
401 break;
402 default:
403 *buf = pd->msg->buf[pd->pos];
404 }
405 }
406
407 static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
408 {
409 unsigned char data;
410
411 if (pd->pos == pd->msg->len) {
412 /* Send stop if we haven't yet (DMA case) */
413 if (pd->send_stop && pd->stop_after_dma)
414 i2c_op(pd, OP_TX_STOP, 0);
415 return 1;
416 }
417
418 sh_mobile_i2c_get_data(pd, &data);
419
420 if (sh_mobile_i2c_is_last_byte(pd))
421 i2c_op(pd, OP_TX_STOP_DATA, data);
422 else if (sh_mobile_i2c_is_first_byte(pd))
423 i2c_op(pd, OP_TX_FIRST, data);
424 else
425 i2c_op(pd, OP_TX, data);
426
427 pd->pos++;
428 return 0;
429 }
430
431 static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
432 {
433 unsigned char data;
434 int real_pos;
435
436 do {
437 if (pd->pos <= -1) {
438 sh_mobile_i2c_get_data(pd, &data);
439
440 if (sh_mobile_i2c_is_first_byte(pd))
441 i2c_op(pd, OP_TX_FIRST, data);
442 else
443 i2c_op(pd, OP_TX, data);
444 break;
445 }
446
447 if (pd->pos == 0) {
448 i2c_op(pd, OP_TX_TO_RX, 0);
449 break;
450 }
451
452 real_pos = pd->pos - 2;
453
454 if (pd->pos == pd->msg->len) {
455 if (pd->stop_after_dma) {
456 /* Simulate PIO end condition after DMA transfer */
457 i2c_op(pd, OP_RX_STOP, 0);
458 pd->pos++;
459 break;
460 }
461
462 if (real_pos < 0) {
463 i2c_op(pd, OP_RX_STOP, 0);
464 break;
465 }
466 data = i2c_op(pd, OP_RX_STOP_DATA, 0);
467 } else
468 data = i2c_op(pd, OP_RX, 0);
469
470 if (real_pos >= 0)
471 pd->msg->buf[real_pos] = data;
472 } while (0);
473
474 pd->pos++;
475 return pd->pos == (pd->msg->len + 2);
476 }
477
478 static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
479 {
480 struct sh_mobile_i2c_data *pd = dev_id;
481 unsigned char sr;
482 int wakeup = 0;
483
484 sr = iic_rd(pd, ICSR);
485 pd->sr |= sr; /* remember state */
486
487 dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
488 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
489 pd->pos, pd->msg->len);
490
491 /* Kick off TxDMA after preface was done */
492 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
493 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
494 else if (sr & (ICSR_AL | ICSR_TACK))
495 /* don't interrupt transaction - continue to issue stop */
496 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
497 else if (pd->msg->flags & I2C_M_RD)
498 wakeup = sh_mobile_i2c_isr_rx(pd);
499 else
500 wakeup = sh_mobile_i2c_isr_tx(pd);
501
502 /* Kick off RxDMA after preface was done */
503 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
504 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
505
506 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
507 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
508
509 if (wakeup) {
510 pd->sr |= SW_DONE;
511 wake_up(&pd->wait);
512 }
513
514 /* defeat write posting to avoid spurious WAIT interrupts */
515 iic_rd(pd, ICSR);
516
517 return IRQ_HANDLED;
518 }
519
520 static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
521 {
522 struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
523 ? pd->dma_rx : pd->dma_tx;
524
525 dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
526 pd->msg->len, pd->dma_direction);
527
528 pd->dma_direction = DMA_NONE;
529 }
530
531 static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
532 {
533 if (pd->dma_direction == DMA_NONE)
534 return;
535 else if (pd->dma_direction == DMA_FROM_DEVICE)
536 dmaengine_terminate_all(pd->dma_rx);
537 else if (pd->dma_direction == DMA_TO_DEVICE)
538 dmaengine_terminate_all(pd->dma_tx);
539
540 sh_mobile_i2c_dma_unmap(pd);
541 }
542
543 static void sh_mobile_i2c_dma_callback(void *data)
544 {
545 struct sh_mobile_i2c_data *pd = data;
546
547 sh_mobile_i2c_dma_unmap(pd);
548 pd->pos = pd->msg->len;
549 pd->stop_after_dma = true;
550
551 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
552 }
553
554 static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
555 enum dma_transfer_direction dir, dma_addr_t port_addr)
556 {
557 struct dma_chan *chan;
558 struct dma_slave_config cfg;
559 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
560 int ret;
561
562 chan = dma_request_slave_channel_reason(dev, chan_name);
563 if (IS_ERR(chan)) {
564 dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name,
565 PTR_ERR(chan));
566 return chan;
567 }
568
569 memset(&cfg, 0, sizeof(cfg));
570 cfg.direction = dir;
571 if (dir == DMA_MEM_TO_DEV) {
572 cfg.dst_addr = port_addr;
573 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
574 } else {
575 cfg.src_addr = port_addr;
576 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
577 }
578
579 ret = dmaengine_slave_config(chan, &cfg);
580 if (ret) {
581 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
582 dma_release_channel(chan);
583 return ERR_PTR(ret);
584 }
585
586 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
587 return chan;
588 }
589
590 static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
591 {
592 bool read = pd->msg->flags & I2C_M_RD;
593 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
594 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
595 struct dma_async_tx_descriptor *txdesc;
596 dma_addr_t dma_addr;
597 dma_cookie_t cookie;
598
599 if (PTR_ERR(chan) == -EPROBE_DEFER) {
600 if (read)
601 chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
602 pd->res->start + ICDR);
603 else
604 chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
605 pd->res->start + ICDR);
606 }
607
608 if (IS_ERR(chan))
609 return;
610
611 dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
612 if (dma_mapping_error(chan->device->dev, dma_addr)) {
613 dev_dbg(pd->dev, "dma map failed, using PIO\n");
614 return;
615 }
616
617 sg_dma_len(&pd->sg) = pd->msg->len;
618 sg_dma_address(&pd->sg) = dma_addr;
619
620 pd->dma_direction = dir;
621
622 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
623 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
624 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
625 if (!txdesc) {
626 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
627 sh_mobile_i2c_cleanup_dma(pd);
628 return;
629 }
630
631 txdesc->callback = sh_mobile_i2c_dma_callback;
632 txdesc->callback_param = pd;
633
634 cookie = dmaengine_submit(txdesc);
635 if (dma_submit_error(cookie)) {
636 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
637 sh_mobile_i2c_cleanup_dma(pd);
638 return;
639 }
640
641 dma_async_issue_pending(chan);
642 }
643
644 static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
645 bool do_init)
646 {
647 if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
648 dev_err(pd->dev, "Unsupported zero length i2c read\n");
649 return -EOPNOTSUPP;
650 }
651
652 if (do_init) {
653 /* Initialize channel registers */
654 iic_set_clr(pd, ICCR, 0, ICCR_ICE);
655
656 /* Enable channel and configure rx ack */
657 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
658
659 /* Set the clock */
660 iic_wr(pd, ICCL, pd->iccl & 0xff);
661 iic_wr(pd, ICCH, pd->icch & 0xff);
662 }
663
664 pd->msg = usr_msg;
665 pd->pos = -1;
666 pd->sr = 0;
667
668 if (pd->msg->len > 8)
669 sh_mobile_i2c_xfer_dma(pd);
670
671 /* Enable all interrupts to begin with */
672 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
673 return 0;
674 }
675
676 static int poll_dte(struct sh_mobile_i2c_data *pd)
677 {
678 int i;
679
680 for (i = 1000; i; i--) {
681 u_int8_t val = iic_rd(pd, ICSR);
682
683 if (val & ICSR_DTE)
684 break;
685
686 if (val & ICSR_TACK)
687 return -ENXIO;
688
689 udelay(10);
690 }
691
692 return i ? 0 : -ETIMEDOUT;
693 }
694
695 static int poll_busy(struct sh_mobile_i2c_data *pd)
696 {
697 int i;
698
699 for (i = 1000; i; i--) {
700 u_int8_t val = iic_rd(pd, ICSR);
701
702 dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
703
704 /* the interrupt handler may wake us up before the
705 * transfer is finished, so poll the hardware
706 * until we're done.
707 */
708 if (!(val & ICSR_BUSY)) {
709 /* handle missing acknowledge and arbitration lost */
710 val |= pd->sr;
711 if (val & ICSR_TACK)
712 return -ENXIO;
713 if (val & ICSR_AL)
714 return -EAGAIN;
715 break;
716 }
717
718 udelay(10);
719 }
720
721 return i ? 0 : -ETIMEDOUT;
722 }
723
724 static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
725 struct i2c_msg *msgs,
726 int num)
727 {
728 struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
729 struct i2c_msg *msg;
730 int err = 0;
731 int i;
732 long timeout;
733
734 activate_ch(pd);
735
736 /* Process all messages */
737 for (i = 0; i < num; i++) {
738 bool do_start = pd->send_stop || !i;
739 msg = &msgs[i];
740 pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
741 pd->stop_after_dma = false;
742
743 err = start_ch(pd, msg, do_start);
744 if (err)
745 break;
746
747 if (do_start)
748 i2c_op(pd, OP_START, 0);
749
750 /* The interrupt handler takes care of the rest... */
751 timeout = wait_event_timeout(pd->wait,
752 pd->sr & (ICSR_TACK | SW_DONE),
753 adapter->timeout);
754 if (!timeout) {
755 dev_err(pd->dev, "Transfer request timed out\n");
756 if (pd->dma_direction != DMA_NONE)
757 sh_mobile_i2c_cleanup_dma(pd);
758
759 err = -ETIMEDOUT;
760 break;
761 }
762
763 if (pd->send_stop)
764 err = poll_busy(pd);
765 else
766 err = poll_dte(pd);
767 if (err < 0)
768 break;
769 }
770
771 deactivate_ch(pd);
772
773 if (!err)
774 err = num;
775 return err;
776 }
777
778 static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
779 {
780 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
781 }
782
783 static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
784 .functionality = sh_mobile_i2c_func,
785 .master_xfer = sh_mobile_i2c_xfer,
786 };
787
788 /*
789 * r8a7740 chip has lasting errata on I2C I/O pad reset.
790 * this is work-around for it.
791 */
792 static void sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
793 {
794 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
795 iic_rd(pd, ICCR); /* dummy read */
796
797 iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
798 iic_rd(pd, ICSTART); /* dummy read */
799
800 udelay(10);
801
802 iic_wr(pd, ICCR, ICCR_SCP);
803 iic_wr(pd, ICSTART, 0);
804
805 udelay(10);
806
807 iic_wr(pd, ICCR, ICCR_TRS);
808 udelay(10);
809 iic_wr(pd, ICCR, 0);
810 udelay(10);
811 iic_wr(pd, ICCR, ICCR_TRS);
812 udelay(10);
813 }
814
815 static const struct sh_mobile_dt_config default_dt_config = {
816 .clks_per_count = 1,
817 };
818
819 static const struct sh_mobile_dt_config fast_clock_dt_config = {
820 .clks_per_count = 2,
821 };
822
823 static const struct sh_mobile_dt_config r8a7740_dt_config = {
824 .clks_per_count = 1,
825 .setup = sh_mobile_i2c_r8a7740_workaround,
826 };
827
828 static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
829 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
830 { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
831 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
832 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
833 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
834 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
835 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
836 { .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config },
837 { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
838 { .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config },
839 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
840 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
841 {},
842 };
843 MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
844
845 static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
846 {
847 if (!IS_ERR(pd->dma_tx)) {
848 dma_release_channel(pd->dma_tx);
849 pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
850 }
851
852 if (!IS_ERR(pd->dma_rx)) {
853 dma_release_channel(pd->dma_rx);
854 pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
855 }
856 }
857
858 static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
859 {
860 struct resource *res;
861 resource_size_t n;
862 int k = 0, ret;
863
864 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
865 for (n = res->start; n <= res->end; n++) {
866 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
867 0, dev_name(&dev->dev), pd);
868 if (ret) {
869 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
870 return ret;
871 }
872 }
873 k++;
874 }
875
876 return k > 0 ? 0 : -ENOENT;
877 }
878
879 static int sh_mobile_i2c_probe(struct platform_device *dev)
880 {
881 struct sh_mobile_i2c_data *pd;
882 struct i2c_adapter *adap;
883 struct resource *res;
884 const struct sh_mobile_dt_config *config;
885 int ret;
886 u32 bus_speed;
887
888 pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
889 if (!pd)
890 return -ENOMEM;
891
892 pd->clk = devm_clk_get(&dev->dev, NULL);
893 if (IS_ERR(pd->clk)) {
894 dev_err(&dev->dev, "cannot get clock\n");
895 return PTR_ERR(pd->clk);
896 }
897
898 ret = sh_mobile_i2c_hook_irqs(dev, pd);
899 if (ret)
900 return ret;
901
902 pd->dev = &dev->dev;
903 platform_set_drvdata(dev, pd);
904
905 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
906
907 pd->res = res;
908 pd->reg = devm_ioremap_resource(&dev->dev, res);
909 if (IS_ERR(pd->reg))
910 return PTR_ERR(pd->reg);
911
912 ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
913 pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
914 pd->clks_per_count = 1;
915
916 config = of_device_get_match_data(&dev->dev);
917 if (config) {
918 pd->clks_per_count = config->clks_per_count;
919
920 if (config->setup)
921 config->setup(pd);
922 }
923
924 /* The IIC blocks on SH-Mobile ARM processors
925 * come with two new bits in ICIC.
926 */
927 if (resource_size(res) > 0x17)
928 pd->flags |= IIC_FLAG_HAS_ICIC67;
929
930 ret = sh_mobile_i2c_init(pd);
931 if (ret)
932 return ret;
933
934 /* Init DMA */
935 sg_init_table(&pd->sg, 1);
936 pd->dma_direction = DMA_NONE;
937 pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
938
939 /* Enable Runtime PM for this device.
940 *
941 * Also tell the Runtime PM core to ignore children
942 * for this device since it is valid for us to suspend
943 * this I2C master driver even though the slave devices
944 * on the I2C bus may not be suspended.
945 *
946 * The state of the I2C hardware bus is unaffected by
947 * the Runtime PM state.
948 */
949 pm_suspend_ignore_children(&dev->dev, true);
950 pm_runtime_enable(&dev->dev);
951
952 /* setup the private data */
953 adap = &pd->adap;
954 i2c_set_adapdata(adap, pd);
955
956 adap->owner = THIS_MODULE;
957 adap->algo = &sh_mobile_i2c_algorithm;
958 adap->dev.parent = &dev->dev;
959 adap->retries = 5;
960 adap->nr = dev->id;
961 adap->dev.of_node = dev->dev.of_node;
962
963 strlcpy(adap->name, dev->name, sizeof(adap->name));
964
965 spin_lock_init(&pd->lock);
966 init_waitqueue_head(&pd->wait);
967
968 ret = i2c_add_numbered_adapter(adap);
969 if (ret < 0) {
970 sh_mobile_i2c_release_dma(pd);
971 return ret;
972 }
973
974 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
975
976 return 0;
977 }
978
979 static int sh_mobile_i2c_remove(struct platform_device *dev)
980 {
981 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
982
983 i2c_del_adapter(&pd->adap);
984 sh_mobile_i2c_release_dma(pd);
985 pm_runtime_disable(&dev->dev);
986 return 0;
987 }
988
989 static int sh_mobile_i2c_runtime_nop(struct device *dev)
990 {
991 /* Runtime PM callback shared between ->runtime_suspend()
992 * and ->runtime_resume(). Simply returns success.
993 *
994 * This driver re-initializes all registers after
995 * pm_runtime_get_sync() anyway so there is no need
996 * to save and restore registers here.
997 */
998 return 0;
999 }
1000
1001 static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
1002 .runtime_suspend = sh_mobile_i2c_runtime_nop,
1003 .runtime_resume = sh_mobile_i2c_runtime_nop,
1004 };
1005
1006 static struct platform_driver sh_mobile_i2c_driver = {
1007 .driver = {
1008 .name = "i2c-sh_mobile",
1009 .pm = &sh_mobile_i2c_dev_pm_ops,
1010 .of_match_table = sh_mobile_i2c_dt_ids,
1011 },
1012 .probe = sh_mobile_i2c_probe,
1013 .remove = sh_mobile_i2c_remove,
1014 };
1015
1016 static int __init sh_mobile_i2c_adap_init(void)
1017 {
1018 return platform_driver_register(&sh_mobile_i2c_driver);
1019 }
1020 subsys_initcall(sh_mobile_i2c_adap_init);
1021
1022 static void __exit sh_mobile_i2c_adap_exit(void)
1023 {
1024 platform_driver_unregister(&sh_mobile_i2c_driver);
1025 }
1026 module_exit(sh_mobile_i2c_adap_exit);
1027
1028 MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
1029 MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
1030 MODULE_LICENSE("GPL v2");
1031 MODULE_ALIAS("platform:i2c-sh_mobile");
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