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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / bnxt_re / ib_verbs.c
1 /*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: IB Verbs interpreter
37 */
38
39 #include <linux/interrupt.h>
40 #include <linux/types.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/if_ether.h>
44
45 #include <rdma/ib_verbs.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/ib_umem.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_mad.h>
50 #include <rdma/ib_cache.h>
51
52 #include "bnxt_ulp.h"
53
54 #include "roce_hsi.h"
55 #include "qplib_res.h"
56 #include "qplib_sp.h"
57 #include "qplib_fp.h"
58 #include "qplib_rcfw.h"
59
60 #include "bnxt_re.h"
61 #include "ib_verbs.h"
62 #include <rdma/bnxt_re-abi.h>
63
64 static int __from_ib_access_flags(int iflags)
65 {
66 int qflags = 0;
67
68 if (iflags & IB_ACCESS_LOCAL_WRITE)
69 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
70 if (iflags & IB_ACCESS_REMOTE_READ)
71 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ;
72 if (iflags & IB_ACCESS_REMOTE_WRITE)
73 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE;
74 if (iflags & IB_ACCESS_REMOTE_ATOMIC)
75 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC;
76 if (iflags & IB_ACCESS_MW_BIND)
77 qflags |= BNXT_QPLIB_ACCESS_MW_BIND;
78 if (iflags & IB_ZERO_BASED)
79 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED;
80 if (iflags & IB_ACCESS_ON_DEMAND)
81 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND;
82 return qflags;
83 };
84
85 static enum ib_access_flags __to_ib_access_flags(int qflags)
86 {
87 enum ib_access_flags iflags = 0;
88
89 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE)
90 iflags |= IB_ACCESS_LOCAL_WRITE;
91 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE)
92 iflags |= IB_ACCESS_REMOTE_WRITE;
93 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ)
94 iflags |= IB_ACCESS_REMOTE_READ;
95 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC)
96 iflags |= IB_ACCESS_REMOTE_ATOMIC;
97 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND)
98 iflags |= IB_ACCESS_MW_BIND;
99 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED)
100 iflags |= IB_ZERO_BASED;
101 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND)
102 iflags |= IB_ACCESS_ON_DEMAND;
103 return iflags;
104 };
105
106 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list,
107 struct bnxt_qplib_sge *sg_list, int num)
108 {
109 int i, total = 0;
110
111 for (i = 0; i < num; i++) {
112 sg_list[i].addr = ib_sg_list[i].addr;
113 sg_list[i].lkey = ib_sg_list[i].lkey;
114 sg_list[i].size = ib_sg_list[i].length;
115 total += sg_list[i].size;
116 }
117 return total;
118 }
119
120 /* Device */
121 struct net_device *bnxt_re_get_netdev(struct ib_device *ibdev, u8 port_num)
122 {
123 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
124 struct net_device *netdev = NULL;
125
126 rcu_read_lock();
127 if (rdev)
128 netdev = rdev->netdev;
129 if (netdev)
130 dev_hold(netdev);
131
132 rcu_read_unlock();
133 return netdev;
134 }
135
136 int bnxt_re_query_device(struct ib_device *ibdev,
137 struct ib_device_attr *ib_attr,
138 struct ib_udata *udata)
139 {
140 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
141 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
142
143 memset(ib_attr, 0, sizeof(*ib_attr));
144
145 ib_attr->fw_ver = (u64)(unsigned long)(dev_attr->fw_ver);
146 bnxt_qplib_get_guid(rdev->netdev->dev_addr,
147 (u8 *)&ib_attr->sys_image_guid);
148 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE;
149 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K;
150
151 ib_attr->vendor_id = rdev->en_dev->pdev->vendor;
152 ib_attr->vendor_part_id = rdev->en_dev->pdev->device;
153 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device;
154 ib_attr->max_qp = dev_attr->max_qp;
155 ib_attr->max_qp_wr = dev_attr->max_qp_wqes;
156 ib_attr->device_cap_flags =
157 IB_DEVICE_CURR_QP_STATE_MOD
158 | IB_DEVICE_RC_RNR_NAK_GEN
159 | IB_DEVICE_SHUTDOWN_PORT
160 | IB_DEVICE_SYS_IMAGE_GUID
161 | IB_DEVICE_LOCAL_DMA_LKEY
162 | IB_DEVICE_RESIZE_MAX_WR
163 | IB_DEVICE_PORT_ACTIVE_EVENT
164 | IB_DEVICE_N_NOTIFY_CQ
165 | IB_DEVICE_MEM_WINDOW
166 | IB_DEVICE_MEM_WINDOW_TYPE_2B
167 | IB_DEVICE_MEM_MGT_EXTENSIONS;
168 ib_attr->max_sge = dev_attr->max_qp_sges;
169 ib_attr->max_sge_rd = dev_attr->max_qp_sges;
170 ib_attr->max_cq = dev_attr->max_cq;
171 ib_attr->max_cqe = dev_attr->max_cq_wqes;
172 ib_attr->max_mr = dev_attr->max_mr;
173 ib_attr->max_pd = dev_attr->max_pd;
174 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom;
175 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom;
176 if (dev_attr->is_atomic) {
177 ib_attr->atomic_cap = IB_ATOMIC_HCA;
178 ib_attr->masked_atomic_cap = IB_ATOMIC_HCA;
179 }
180
181 ib_attr->max_ee_rd_atom = 0;
182 ib_attr->max_res_rd_atom = 0;
183 ib_attr->max_ee_init_rd_atom = 0;
184 ib_attr->max_ee = 0;
185 ib_attr->max_rdd = 0;
186 ib_attr->max_mw = dev_attr->max_mw;
187 ib_attr->max_raw_ipv6_qp = 0;
188 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp;
189 ib_attr->max_mcast_grp = 0;
190 ib_attr->max_mcast_qp_attach = 0;
191 ib_attr->max_total_mcast_qp_attach = 0;
192 ib_attr->max_ah = dev_attr->max_ah;
193
194 ib_attr->max_fmr = 0;
195 ib_attr->max_map_per_fmr = 0;
196
197 ib_attr->max_srq = dev_attr->max_srq;
198 ib_attr->max_srq_wr = dev_attr->max_srq_wqes;
199 ib_attr->max_srq_sge = dev_attr->max_srq_sges;
200
201 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS;
202
203 ib_attr->max_pkeys = 1;
204 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY;
205 return 0;
206 }
207
208 int bnxt_re_modify_device(struct ib_device *ibdev,
209 int device_modify_mask,
210 struct ib_device_modify *device_modify)
211 {
212 switch (device_modify_mask) {
213 case IB_DEVICE_MODIFY_SYS_IMAGE_GUID:
214 /* Modify the GUID requires the modification of the GID table */
215 /* GUID should be made as READ-ONLY */
216 break;
217 case IB_DEVICE_MODIFY_NODE_DESC:
218 /* Node Desc should be made as READ-ONLY */
219 break;
220 default:
221 break;
222 }
223 return 0;
224 }
225
226 /* Port */
227 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num,
228 struct ib_port_attr *port_attr)
229 {
230 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
231 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
232
233 memset(port_attr, 0, sizeof(*port_attr));
234
235 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) {
236 port_attr->state = IB_PORT_ACTIVE;
237 port_attr->phys_state = 5;
238 } else {
239 port_attr->state = IB_PORT_DOWN;
240 port_attr->phys_state = 3;
241 }
242 port_attr->max_mtu = IB_MTU_4096;
243 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu);
244 port_attr->gid_tbl_len = dev_attr->max_sgid;
245 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
246 IB_PORT_DEVICE_MGMT_SUP |
247 IB_PORT_VENDOR_CLASS_SUP |
248 IB_PORT_IP_BASED_GIDS;
249
250 /* Max MSG size set to 2G for now */
251 port_attr->max_msg_sz = 0x80000000;
252 port_attr->bad_pkey_cntr = 0;
253 port_attr->qkey_viol_cntr = 0;
254 port_attr->pkey_tbl_len = dev_attr->max_pkey;
255 port_attr->lid = 0;
256 port_attr->sm_lid = 0;
257 port_attr->lmc = 0;
258 port_attr->max_vl_num = 4;
259 port_attr->sm_sl = 0;
260 port_attr->subnet_timeout = 0;
261 port_attr->init_type_reply = 0;
262 port_attr->active_speed = rdev->active_speed;
263 port_attr->active_width = rdev->active_width;
264
265 return 0;
266 }
267
268 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num,
269 struct ib_port_immutable *immutable)
270 {
271 struct ib_port_attr port_attr;
272
273 if (bnxt_re_query_port(ibdev, port_num, &port_attr))
274 return -EINVAL;
275
276 immutable->pkey_tbl_len = port_attr.pkey_tbl_len;
277 immutable->gid_tbl_len = port_attr.gid_tbl_len;
278 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
279 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP;
280 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
281 return 0;
282 }
283
284 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num,
285 u16 index, u16 *pkey)
286 {
287 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
288
289 /* Ignore port_num */
290
291 memset(pkey, 0, sizeof(*pkey));
292 return bnxt_qplib_get_pkey(&rdev->qplib_res,
293 &rdev->qplib_res.pkey_tbl, index, pkey);
294 }
295
296 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num,
297 int index, union ib_gid *gid)
298 {
299 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
300 int rc = 0;
301
302 /* Ignore port_num */
303 memset(gid, 0, sizeof(*gid));
304 rc = bnxt_qplib_get_sgid(&rdev->qplib_res,
305 &rdev->qplib_res.sgid_tbl, index,
306 (struct bnxt_qplib_gid *)gid);
307 return rc;
308 }
309
310 int bnxt_re_del_gid(struct ib_device *ibdev, u8 port_num,
311 unsigned int index, void **context)
312 {
313 int rc = 0;
314 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
315 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
316 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
317 struct bnxt_qplib_gid *gid_to_del;
318
319 /* Delete the entry from the hardware */
320 ctx = *context;
321 if (!ctx)
322 return -EINVAL;
323
324 if (sgid_tbl && sgid_tbl->active) {
325 if (ctx->idx >= sgid_tbl->max)
326 return -EINVAL;
327 gid_to_del = &sgid_tbl->tbl[ctx->idx];
328 /* DEL_GID is called in WQ context(netdevice_event_work_handler)
329 * or via the ib_unregister_device path. In the former case QP1
330 * may not be destroyed yet, in which case just return as FW
331 * needs that entry to be present and will fail it's deletion.
332 * We could get invoked again after QP1 is destroyed OR get an
333 * ADD_GID call with a different GID value for the same index
334 * where we issue MODIFY_GID cmd to update the GID entry -- TBD
335 */
336 if (ctx->idx == 0 &&
337 rdma_link_local_addr((struct in6_addr *)gid_to_del) &&
338 ctx->refcnt == 1 && rdev->qp1_sqp) {
339 dev_dbg(rdev_to_dev(rdev),
340 "Trying to delete GID0 while QP1 is alive\n");
341 return -EFAULT;
342 }
343 ctx->refcnt--;
344 if (!ctx->refcnt) {
345 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, true);
346 if (rc) {
347 dev_err(rdev_to_dev(rdev),
348 "Failed to remove GID: %#x", rc);
349 } else {
350 ctx_tbl = sgid_tbl->ctx;
351 ctx_tbl[ctx->idx] = NULL;
352 kfree(ctx);
353 }
354 }
355 } else {
356 return -EINVAL;
357 }
358 return rc;
359 }
360
361 int bnxt_re_add_gid(struct ib_device *ibdev, u8 port_num,
362 unsigned int index, const union ib_gid *gid,
363 const struct ib_gid_attr *attr, void **context)
364 {
365 int rc;
366 u32 tbl_idx = 0;
367 u16 vlan_id = 0xFFFF;
368 struct bnxt_re_gid_ctx *ctx, **ctx_tbl;
369 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
370 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl;
371
372 if ((attr->ndev) && is_vlan_dev(attr->ndev))
373 vlan_id = vlan_dev_vlan_id(attr->ndev);
374
375 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)gid,
376 rdev->qplib_res.netdev->dev_addr,
377 vlan_id, true, &tbl_idx);
378 if (rc == -EALREADY) {
379 ctx_tbl = sgid_tbl->ctx;
380 ctx_tbl[tbl_idx]->refcnt++;
381 *context = ctx_tbl[tbl_idx];
382 return 0;
383 }
384
385 if (rc < 0) {
386 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc);
387 return rc;
388 }
389
390 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL);
391 if (!ctx)
392 return -ENOMEM;
393 ctx_tbl = sgid_tbl->ctx;
394 ctx->idx = tbl_idx;
395 ctx->refcnt = 1;
396 ctx_tbl[tbl_idx] = ctx;
397 *context = ctx;
398
399 return rc;
400 }
401
402 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev,
403 u8 port_num)
404 {
405 return IB_LINK_LAYER_ETHERNET;
406 }
407
408 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE)
409
410 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd)
411 {
412 struct bnxt_re_fence_data *fence = &pd->fence;
413 struct ib_mr *ib_mr = &fence->mr->ib_mr;
414 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe;
415
416 memset(wqe, 0, sizeof(*wqe));
417 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW;
418 wqe->wr_id = BNXT_QPLIB_FENCE_WRID;
419 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
420 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
421 wqe->bind.zero_based = false;
422 wqe->bind.parent_l_key = ib_mr->lkey;
423 wqe->bind.va = (u64)(unsigned long)fence->va;
424 wqe->bind.length = fence->size;
425 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ);
426 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1;
427
428 /* Save the initial rkey in fence structure for now;
429 * wqe->bind.r_key will be set at (re)bind time.
430 */
431 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey);
432 }
433
434 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp)
435 {
436 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp,
437 qplib_qp);
438 struct ib_pd *ib_pd = qp->ib_qp.pd;
439 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
440 struct bnxt_re_fence_data *fence = &pd->fence;
441 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe;
442 struct bnxt_qplib_swqe wqe;
443 int rc;
444
445 memcpy(&wqe, fence_wqe, sizeof(wqe));
446 wqe.bind.r_key = fence->bind_rkey;
447 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey);
448
449 dev_dbg(rdev_to_dev(qp->rdev),
450 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n",
451 wqe.bind.r_key, qp->qplib_qp.id, pd);
452 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
453 if (rc) {
454 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n");
455 return rc;
456 }
457 bnxt_qplib_post_send_db(&qp->qplib_qp);
458
459 return rc;
460 }
461
462 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd)
463 {
464 struct bnxt_re_fence_data *fence = &pd->fence;
465 struct bnxt_re_dev *rdev = pd->rdev;
466 struct device *dev = &rdev->en_dev->pdev->dev;
467 struct bnxt_re_mr *mr = fence->mr;
468
469 if (fence->mw) {
470 bnxt_re_dealloc_mw(fence->mw);
471 fence->mw = NULL;
472 }
473 if (mr) {
474 if (mr->ib_mr.rkey)
475 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr,
476 true);
477 if (mr->ib_mr.lkey)
478 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
479 kfree(mr);
480 fence->mr = NULL;
481 }
482 if (fence->dma_addr) {
483 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES,
484 DMA_BIDIRECTIONAL);
485 fence->dma_addr = 0;
486 }
487 }
488
489 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd)
490 {
491 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND;
492 struct bnxt_re_fence_data *fence = &pd->fence;
493 struct bnxt_re_dev *rdev = pd->rdev;
494 struct device *dev = &rdev->en_dev->pdev->dev;
495 struct bnxt_re_mr *mr = NULL;
496 dma_addr_t dma_addr = 0;
497 struct ib_mw *mw;
498 u64 pbl_tbl;
499 int rc;
500
501 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES,
502 DMA_BIDIRECTIONAL);
503 rc = dma_mapping_error(dev, dma_addr);
504 if (rc) {
505 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n");
506 rc = -EIO;
507 fence->dma_addr = 0;
508 goto fail;
509 }
510 fence->dma_addr = dma_addr;
511
512 /* Allocate a MR */
513 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
514 if (!mr) {
515 rc = -ENOMEM;
516 goto fail;
517 }
518 fence->mr = mr;
519 mr->rdev = rdev;
520 mr->qplib_mr.pd = &pd->qplib_pd;
521 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
522 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
523 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
524 if (rc) {
525 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n");
526 goto fail;
527 }
528
529 /* Register MR */
530 mr->ib_mr.lkey = mr->qplib_mr.lkey;
531 mr->qplib_mr.va = (u64)(unsigned long)fence->va;
532 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES;
533 pbl_tbl = dma_addr;
534 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl,
535 BNXT_RE_FENCE_PBL_SIZE, false);
536 if (rc) {
537 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n");
538 goto fail;
539 }
540 mr->ib_mr.rkey = mr->qplib_mr.rkey;
541
542 /* Create a fence MW only for kernel consumers */
543 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL);
544 if (IS_ERR(mw)) {
545 dev_err(rdev_to_dev(rdev),
546 "Failed to create fence-MW for PD: %p\n", pd);
547 rc = PTR_ERR(mw);
548 goto fail;
549 }
550 fence->mw = mw;
551
552 bnxt_re_create_fence_wqe(pd);
553 return 0;
554
555 fail:
556 bnxt_re_destroy_fence_mr(pd);
557 return rc;
558 }
559
560 /* Protection Domains */
561 int bnxt_re_dealloc_pd(struct ib_pd *ib_pd)
562 {
563 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
564 struct bnxt_re_dev *rdev = pd->rdev;
565 int rc;
566
567 bnxt_re_destroy_fence_mr(pd);
568
569 if (pd->qplib_pd.id) {
570 rc = bnxt_qplib_dealloc_pd(&rdev->qplib_res,
571 &rdev->qplib_res.pd_tbl,
572 &pd->qplib_pd);
573 if (rc)
574 dev_err(rdev_to_dev(rdev), "Failed to deallocate HW PD");
575 }
576
577 kfree(pd);
578 return 0;
579 }
580
581 struct ib_pd *bnxt_re_alloc_pd(struct ib_device *ibdev,
582 struct ib_ucontext *ucontext,
583 struct ib_udata *udata)
584 {
585 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
586 struct bnxt_re_ucontext *ucntx = container_of(ucontext,
587 struct bnxt_re_ucontext,
588 ib_uctx);
589 struct bnxt_re_pd *pd;
590 int rc;
591
592 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
593 if (!pd)
594 return ERR_PTR(-ENOMEM);
595
596 pd->rdev = rdev;
597 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) {
598 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD");
599 rc = -ENOMEM;
600 goto fail;
601 }
602
603 if (udata) {
604 struct bnxt_re_pd_resp resp;
605
606 if (!ucntx->dpi.dbr) {
607 /* Allocate DPI in alloc_pd to avoid failing of
608 * ibv_devinfo and family of application when DPIs
609 * are depleted.
610 */
611 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl,
612 &ucntx->dpi, ucntx)) {
613 rc = -ENOMEM;
614 goto dbfail;
615 }
616 }
617
618 resp.pdid = pd->qplib_pd.id;
619 /* Still allow mapping this DBR to the new user PD. */
620 resp.dpi = ucntx->dpi.dpi;
621 resp.dbr = (u64)ucntx->dpi.umdbr;
622
623 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
624 if (rc) {
625 dev_err(rdev_to_dev(rdev),
626 "Failed to copy user response\n");
627 goto dbfail;
628 }
629 }
630
631 if (!udata)
632 if (bnxt_re_create_fence_mr(pd))
633 dev_warn(rdev_to_dev(rdev),
634 "Failed to create Fence-MR\n");
635 return &pd->ib_pd;
636 dbfail:
637 (void)bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl,
638 &pd->qplib_pd);
639 fail:
640 kfree(pd);
641 return ERR_PTR(rc);
642 }
643
644 /* Address Handles */
645 int bnxt_re_destroy_ah(struct ib_ah *ib_ah)
646 {
647 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
648 struct bnxt_re_dev *rdev = ah->rdev;
649 int rc;
650
651 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah);
652 if (rc) {
653 dev_err(rdev_to_dev(rdev), "Failed to destroy HW AH");
654 return rc;
655 }
656 kfree(ah);
657 return 0;
658 }
659
660 struct ib_ah *bnxt_re_create_ah(struct ib_pd *ib_pd,
661 struct rdma_ah_attr *ah_attr,
662 struct ib_udata *udata)
663 {
664 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
665 struct bnxt_re_dev *rdev = pd->rdev;
666 struct bnxt_re_ah *ah;
667 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
668 int rc;
669 u8 nw_type;
670
671 struct ib_gid_attr sgid_attr;
672
673 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) {
674 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set");
675 return ERR_PTR(-EINVAL);
676 }
677 ah = kzalloc(sizeof(*ah), GFP_ATOMIC);
678 if (!ah)
679 return ERR_PTR(-ENOMEM);
680
681 ah->rdev = rdev;
682 ah->qplib_ah.pd = &pd->qplib_pd;
683
684 /* Supply the configuration for the HW */
685 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw,
686 sizeof(union ib_gid));
687 /*
688 * If RoCE V2 is enabled, stack will have two entries for
689 * each GID entry. Avoiding this duplicte entry in HW. Dividing
690 * the GID index by 2 for RoCE V2
691 */
692 ah->qplib_ah.sgid_index = grh->sgid_index / 2;
693 ah->qplib_ah.host_sgid_index = grh->sgid_index;
694 ah->qplib_ah.traffic_class = grh->traffic_class;
695 ah->qplib_ah.flow_label = grh->flow_label;
696 ah->qplib_ah.hop_limit = grh->hop_limit;
697 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr);
698 if (ib_pd->uobject &&
699 !rdma_is_multicast_addr((struct in6_addr *)
700 grh->dgid.raw) &&
701 !rdma_link_local_addr((struct in6_addr *)
702 grh->dgid.raw)) {
703 union ib_gid sgid;
704
705 rc = ib_get_cached_gid(&rdev->ibdev, 1,
706 grh->sgid_index, &sgid,
707 &sgid_attr);
708 if (rc) {
709 dev_err(rdev_to_dev(rdev),
710 "Failed to query gid at index %d",
711 grh->sgid_index);
712 goto fail;
713 }
714 if (sgid_attr.ndev)
715 dev_put(sgid_attr.ndev);
716 /* Get network header type for this GID */
717 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
718 switch (nw_type) {
719 case RDMA_NETWORK_IPV4:
720 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4;
721 break;
722 case RDMA_NETWORK_IPV6:
723 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6;
724 break;
725 default:
726 ah->qplib_ah.nw_type = CMDQ_CREATE_AH_TYPE_V1;
727 break;
728 }
729 }
730
731 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN);
732 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
733 if (rc) {
734 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH");
735 goto fail;
736 }
737
738 /* Write AVID to shared page. */
739 if (ib_pd->uobject) {
740 struct ib_ucontext *ib_uctx = ib_pd->uobject->context;
741 struct bnxt_re_ucontext *uctx;
742 unsigned long flag;
743 u32 *wrptr;
744
745 uctx = container_of(ib_uctx, struct bnxt_re_ucontext, ib_uctx);
746 spin_lock_irqsave(&uctx->sh_lock, flag);
747 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT);
748 *wrptr = ah->qplib_ah.id;
749 wmb(); /* make sure cache is updated. */
750 spin_unlock_irqrestore(&uctx->sh_lock, flag);
751 }
752
753 return &ah->ib_ah;
754
755 fail:
756 kfree(ah);
757 return ERR_PTR(rc);
758 }
759
760 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
761 {
762 return 0;
763 }
764
765 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr)
766 {
767 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah);
768
769 ah_attr->type = ib_ah->type;
770 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl);
771 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN);
772 rdma_ah_set_grh(ah_attr, NULL, 0,
773 ah->qplib_ah.host_sgid_index,
774 0, ah->qplib_ah.traffic_class);
775 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data);
776 rdma_ah_set_port_num(ah_attr, 1);
777 rdma_ah_set_static_rate(ah_attr, 0);
778 return 0;
779 }
780
781 /* Queue Pairs */
782 int bnxt_re_destroy_qp(struct ib_qp *ib_qp)
783 {
784 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
785 struct bnxt_re_dev *rdev = qp->rdev;
786 int rc;
787
788 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp);
789 bnxt_qplib_del_flush_qp(&qp->qplib_qp);
790 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
791 if (rc) {
792 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP");
793 return rc;
794 }
795 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) {
796 rc = bnxt_qplib_destroy_ah(&rdev->qplib_res,
797 &rdev->sqp_ah->qplib_ah);
798 if (rc) {
799 dev_err(rdev_to_dev(rdev),
800 "Failed to destroy HW AH for shadow QP");
801 return rc;
802 }
803
804 bnxt_qplib_del_flush_qp(&qp->qplib_qp);
805 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res,
806 &rdev->qp1_sqp->qplib_qp);
807 if (rc) {
808 dev_err(rdev_to_dev(rdev),
809 "Failed to destroy Shadow QP");
810 return rc;
811 }
812 mutex_lock(&rdev->qp_lock);
813 list_del(&rdev->qp1_sqp->list);
814 atomic_dec(&rdev->qp_count);
815 mutex_unlock(&rdev->qp_lock);
816
817 kfree(rdev->sqp_ah);
818 kfree(rdev->qp1_sqp);
819 rdev->qp1_sqp = NULL;
820 rdev->sqp_ah = NULL;
821 }
822
823 if (!IS_ERR_OR_NULL(qp->rumem))
824 ib_umem_release(qp->rumem);
825 if (!IS_ERR_OR_NULL(qp->sumem))
826 ib_umem_release(qp->sumem);
827
828 mutex_lock(&rdev->qp_lock);
829 list_del(&qp->list);
830 atomic_dec(&rdev->qp_count);
831 mutex_unlock(&rdev->qp_lock);
832 kfree(qp);
833 return 0;
834 }
835
836 static u8 __from_ib_qp_type(enum ib_qp_type type)
837 {
838 switch (type) {
839 case IB_QPT_GSI:
840 return CMDQ_CREATE_QP1_TYPE_GSI;
841 case IB_QPT_RC:
842 return CMDQ_CREATE_QP_TYPE_RC;
843 case IB_QPT_UD:
844 return CMDQ_CREATE_QP_TYPE_UD;
845 default:
846 return IB_QPT_MAX;
847 }
848 }
849
850 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd,
851 struct bnxt_re_qp *qp, struct ib_udata *udata)
852 {
853 struct bnxt_re_qp_req ureq;
854 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp;
855 struct ib_umem *umem;
856 int bytes = 0;
857 struct ib_ucontext *context = pd->ib_pd.uobject->context;
858 struct bnxt_re_ucontext *cntx = container_of(context,
859 struct bnxt_re_ucontext,
860 ib_uctx);
861 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq)))
862 return -EFAULT;
863
864 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE);
865 /* Consider mapping PSN search memory only for RC QPs. */
866 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC)
867 bytes += (qplib_qp->sq.max_wqe * sizeof(struct sq_psn_search));
868 bytes = PAGE_ALIGN(bytes);
869 umem = ib_umem_get(context, ureq.qpsva, bytes,
870 IB_ACCESS_LOCAL_WRITE, 1);
871 if (IS_ERR(umem))
872 return PTR_ERR(umem);
873
874 qp->sumem = umem;
875 qplib_qp->sq.sglist = umem->sg_head.sgl;
876 qplib_qp->sq.nmap = umem->nmap;
877 qplib_qp->qp_handle = ureq.qp_handle;
878
879 if (!qp->qplib_qp.srq) {
880 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE);
881 bytes = PAGE_ALIGN(bytes);
882 umem = ib_umem_get(context, ureq.qprva, bytes,
883 IB_ACCESS_LOCAL_WRITE, 1);
884 if (IS_ERR(umem))
885 goto rqfail;
886 qp->rumem = umem;
887 qplib_qp->rq.sglist = umem->sg_head.sgl;
888 qplib_qp->rq.nmap = umem->nmap;
889 }
890
891 qplib_qp->dpi = &cntx->dpi;
892 return 0;
893 rqfail:
894 ib_umem_release(qp->sumem);
895 qp->sumem = NULL;
896 qplib_qp->sq.sglist = NULL;
897 qplib_qp->sq.nmap = 0;
898
899 return PTR_ERR(umem);
900 }
901
902 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah
903 (struct bnxt_re_pd *pd,
904 struct bnxt_qplib_res *qp1_res,
905 struct bnxt_qplib_qp *qp1_qp)
906 {
907 struct bnxt_re_dev *rdev = pd->rdev;
908 struct bnxt_re_ah *ah;
909 union ib_gid sgid;
910 int rc;
911
912 ah = kzalloc(sizeof(*ah), GFP_KERNEL);
913 if (!ah)
914 return NULL;
915
916 ah->rdev = rdev;
917 ah->qplib_ah.pd = &pd->qplib_pd;
918
919 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid);
920 if (rc)
921 goto fail;
922
923 /* supply the dgid data same as sgid */
924 memcpy(ah->qplib_ah.dgid.data, &sgid.raw,
925 sizeof(union ib_gid));
926 ah->qplib_ah.sgid_index = 0;
927
928 ah->qplib_ah.traffic_class = 0;
929 ah->qplib_ah.flow_label = 0;
930 ah->qplib_ah.hop_limit = 1;
931 ah->qplib_ah.sl = 0;
932 /* Have DMAC same as SMAC */
933 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr);
934
935 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah);
936 if (rc) {
937 dev_err(rdev_to_dev(rdev),
938 "Failed to allocate HW AH for Shadow QP");
939 goto fail;
940 }
941
942 return ah;
943
944 fail:
945 kfree(ah);
946 return NULL;
947 }
948
949 static struct bnxt_re_qp *bnxt_re_create_shadow_qp
950 (struct bnxt_re_pd *pd,
951 struct bnxt_qplib_res *qp1_res,
952 struct bnxt_qplib_qp *qp1_qp)
953 {
954 struct bnxt_re_dev *rdev = pd->rdev;
955 struct bnxt_re_qp *qp;
956 int rc;
957
958 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
959 if (!qp)
960 return NULL;
961
962 qp->rdev = rdev;
963
964 /* Initialize the shadow QP structure from the QP1 values */
965 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
966
967 qp->qplib_qp.pd = &pd->qplib_pd;
968 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
969 qp->qplib_qp.type = IB_QPT_UD;
970
971 qp->qplib_qp.max_inline_data = 0;
972 qp->qplib_qp.sig_type = true;
973
974 /* Shadow QP SQ depth should be same as QP1 RQ depth */
975 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe;
976 qp->qplib_qp.sq.max_sge = 2;
977 /* Q full delta can be 1 since it is internal QP */
978 qp->qplib_qp.sq.q_full_delta = 1;
979
980 qp->qplib_qp.scq = qp1_qp->scq;
981 qp->qplib_qp.rcq = qp1_qp->rcq;
982
983 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe;
984 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge;
985 /* Q full delta can be 1 since it is internal QP */
986 qp->qplib_qp.rq.q_full_delta = 1;
987
988 qp->qplib_qp.mtu = qp1_qp->mtu;
989
990 qp->qplib_qp.sq_hdr_buf_size = 0;
991 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
992 qp->qplib_qp.dpi = &rdev->dpi_privileged;
993
994 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp);
995 if (rc)
996 goto fail;
997
998 rdev->sqp_id = qp->qplib_qp.id;
999
1000 spin_lock_init(&qp->sq_lock);
1001 INIT_LIST_HEAD(&qp->list);
1002 mutex_lock(&rdev->qp_lock);
1003 list_add_tail(&qp->list, &rdev->qp_list);
1004 atomic_inc(&rdev->qp_count);
1005 mutex_unlock(&rdev->qp_lock);
1006 return qp;
1007 fail:
1008 kfree(qp);
1009 return NULL;
1010 }
1011
1012 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd,
1013 struct ib_qp_init_attr *qp_init_attr,
1014 struct ib_udata *udata)
1015 {
1016 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
1017 struct bnxt_re_dev *rdev = pd->rdev;
1018 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1019 struct bnxt_re_qp *qp;
1020 struct bnxt_re_cq *cq;
1021 int rc, entries;
1022
1023 if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) ||
1024 (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) ||
1025 (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) ||
1026 (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) ||
1027 (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data))
1028 return ERR_PTR(-EINVAL);
1029
1030 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1031 if (!qp)
1032 return ERR_PTR(-ENOMEM);
1033
1034 qp->rdev = rdev;
1035 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr);
1036 qp->qplib_qp.pd = &pd->qplib_pd;
1037 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp);
1038 qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type);
1039 if (qp->qplib_qp.type == IB_QPT_MAX) {
1040 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported",
1041 qp->qplib_qp.type);
1042 rc = -EINVAL;
1043 goto fail;
1044 }
1045 qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data;
1046 qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type ==
1047 IB_SIGNAL_ALL_WR) ? true : false);
1048
1049 qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge;
1050 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1051 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1052
1053 if (qp_init_attr->send_cq) {
1054 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq,
1055 ib_cq);
1056 if (!cq) {
1057 dev_err(rdev_to_dev(rdev), "Send CQ not found");
1058 rc = -EINVAL;
1059 goto fail;
1060 }
1061 qp->qplib_qp.scq = &cq->qplib_cq;
1062 }
1063
1064 if (qp_init_attr->recv_cq) {
1065 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq,
1066 ib_cq);
1067 if (!cq) {
1068 dev_err(rdev_to_dev(rdev), "Receive CQ not found");
1069 rc = -EINVAL;
1070 goto fail;
1071 }
1072 qp->qplib_qp.rcq = &cq->qplib_cq;
1073 }
1074
1075 if (qp_init_attr->srq) {
1076 dev_err(rdev_to_dev(rdev), "SRQ not supported");
1077 rc = -ENOTSUPP;
1078 goto fail;
1079 } else {
1080 /* Allocate 1 more than what's provided so posting max doesn't
1081 * mean empty
1082 */
1083 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1);
1084 qp->qplib_qp.rq.max_wqe = min_t(u32, entries,
1085 dev_attr->max_qp_wqes + 1);
1086
1087 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1088 qp_init_attr->cap.max_recv_wr;
1089
1090 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge;
1091 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1092 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1093 }
1094
1095 qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1096
1097 if (qp_init_attr->qp_type == IB_QPT_GSI) {
1098 /* Allocate 1 more than what's provided */
1099 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1);
1100 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1101 dev_attr->max_qp_wqes + 1);
1102 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1103 qp_init_attr->cap.max_send_wr;
1104 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1105 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges)
1106 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges;
1107 qp->qplib_qp.sq.max_sge++;
1108 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges)
1109 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges;
1110
1111 qp->qplib_qp.rq_hdr_buf_size =
1112 BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1113
1114 qp->qplib_qp.sq_hdr_buf_size =
1115 BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2;
1116 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1117 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp);
1118 if (rc) {
1119 dev_err(rdev_to_dev(rdev), "Failed to create HW QP1");
1120 goto fail;
1121 }
1122 /* Create a shadow QP to handle the QP1 traffic */
1123 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res,
1124 &qp->qplib_qp);
1125 if (!rdev->qp1_sqp) {
1126 rc = -EINVAL;
1127 dev_err(rdev_to_dev(rdev),
1128 "Failed to create Shadow QP for QP1");
1129 goto qp_destroy;
1130 }
1131 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res,
1132 &qp->qplib_qp);
1133 if (!rdev->sqp_ah) {
1134 bnxt_qplib_destroy_qp(&rdev->qplib_res,
1135 &rdev->qp1_sqp->qplib_qp);
1136 rc = -EINVAL;
1137 dev_err(rdev_to_dev(rdev),
1138 "Failed to create AH entry for ShadowQP");
1139 goto qp_destroy;
1140 }
1141
1142 } else {
1143 /* Allocate 128 + 1 more than what's provided */
1144 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr +
1145 BNXT_QPLIB_RESERVED_QP_WRS + 1);
1146 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1147 dev_attr->max_qp_wqes +
1148 BNXT_QPLIB_RESERVED_QP_WRS + 1);
1149 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1;
1150
1151 /*
1152 * Reserving one slot for Phantom WQE. Application can
1153 * post one extra entry in this case. But allowing this to avoid
1154 * unexpected Queue full condition
1155 */
1156
1157 qp->qplib_qp.sq.q_full_delta -= 1;
1158
1159 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom;
1160 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom;
1161 if (udata) {
1162 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata);
1163 if (rc)
1164 goto fail;
1165 } else {
1166 qp->qplib_qp.dpi = &rdev->dpi_privileged;
1167 }
1168
1169 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp);
1170 if (rc) {
1171 dev_err(rdev_to_dev(rdev), "Failed to create HW QP");
1172 goto free_umem;
1173 }
1174 }
1175
1176 qp->ib_qp.qp_num = qp->qplib_qp.id;
1177 spin_lock_init(&qp->sq_lock);
1178 spin_lock_init(&qp->rq_lock);
1179
1180 if (udata) {
1181 struct bnxt_re_qp_resp resp;
1182
1183 resp.qpid = qp->ib_qp.qp_num;
1184 resp.rsvd = 0;
1185 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
1186 if (rc) {
1187 dev_err(rdev_to_dev(rdev), "Failed to copy QP udata");
1188 goto qp_destroy;
1189 }
1190 }
1191 INIT_LIST_HEAD(&qp->list);
1192 mutex_lock(&rdev->qp_lock);
1193 list_add_tail(&qp->list, &rdev->qp_list);
1194 atomic_inc(&rdev->qp_count);
1195 mutex_unlock(&rdev->qp_lock);
1196
1197 return &qp->ib_qp;
1198 qp_destroy:
1199 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp);
1200 free_umem:
1201 if (udata) {
1202 if (qp->rumem)
1203 ib_umem_release(qp->rumem);
1204 if (qp->sumem)
1205 ib_umem_release(qp->sumem);
1206 }
1207 fail:
1208 kfree(qp);
1209 return ERR_PTR(rc);
1210 }
1211
1212 static u8 __from_ib_qp_state(enum ib_qp_state state)
1213 {
1214 switch (state) {
1215 case IB_QPS_RESET:
1216 return CMDQ_MODIFY_QP_NEW_STATE_RESET;
1217 case IB_QPS_INIT:
1218 return CMDQ_MODIFY_QP_NEW_STATE_INIT;
1219 case IB_QPS_RTR:
1220 return CMDQ_MODIFY_QP_NEW_STATE_RTR;
1221 case IB_QPS_RTS:
1222 return CMDQ_MODIFY_QP_NEW_STATE_RTS;
1223 case IB_QPS_SQD:
1224 return CMDQ_MODIFY_QP_NEW_STATE_SQD;
1225 case IB_QPS_SQE:
1226 return CMDQ_MODIFY_QP_NEW_STATE_SQE;
1227 case IB_QPS_ERR:
1228 default:
1229 return CMDQ_MODIFY_QP_NEW_STATE_ERR;
1230 }
1231 }
1232
1233 static enum ib_qp_state __to_ib_qp_state(u8 state)
1234 {
1235 switch (state) {
1236 case CMDQ_MODIFY_QP_NEW_STATE_RESET:
1237 return IB_QPS_RESET;
1238 case CMDQ_MODIFY_QP_NEW_STATE_INIT:
1239 return IB_QPS_INIT;
1240 case CMDQ_MODIFY_QP_NEW_STATE_RTR:
1241 return IB_QPS_RTR;
1242 case CMDQ_MODIFY_QP_NEW_STATE_RTS:
1243 return IB_QPS_RTS;
1244 case CMDQ_MODIFY_QP_NEW_STATE_SQD:
1245 return IB_QPS_SQD;
1246 case CMDQ_MODIFY_QP_NEW_STATE_SQE:
1247 return IB_QPS_SQE;
1248 case CMDQ_MODIFY_QP_NEW_STATE_ERR:
1249 default:
1250 return IB_QPS_ERR;
1251 }
1252 }
1253
1254 static u32 __from_ib_mtu(enum ib_mtu mtu)
1255 {
1256 switch (mtu) {
1257 case IB_MTU_256:
1258 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256;
1259 case IB_MTU_512:
1260 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512;
1261 case IB_MTU_1024:
1262 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024;
1263 case IB_MTU_2048:
1264 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1265 case IB_MTU_4096:
1266 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096;
1267 default:
1268 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048;
1269 }
1270 }
1271
1272 static enum ib_mtu __to_ib_mtu(u32 mtu)
1273 {
1274 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) {
1275 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256:
1276 return IB_MTU_256;
1277 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512:
1278 return IB_MTU_512;
1279 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024:
1280 return IB_MTU_1024;
1281 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048:
1282 return IB_MTU_2048;
1283 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096:
1284 return IB_MTU_4096;
1285 default:
1286 return IB_MTU_2048;
1287 }
1288 }
1289
1290 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev,
1291 struct bnxt_re_qp *qp1_qp,
1292 int qp_attr_mask)
1293 {
1294 struct bnxt_re_qp *qp = rdev->qp1_sqp;
1295 int rc = 0;
1296
1297 if (qp_attr_mask & IB_QP_STATE) {
1298 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1299 qp->qplib_qp.state = qp1_qp->qplib_qp.state;
1300 }
1301 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1302 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1303 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index;
1304 }
1305
1306 if (qp_attr_mask & IB_QP_QKEY) {
1307 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1308 /* Using a Random QKEY */
1309 qp->qplib_qp.qkey = 0x81818181;
1310 }
1311 if (qp_attr_mask & IB_QP_SQ_PSN) {
1312 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1313 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn;
1314 }
1315
1316 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1317 if (rc)
1318 dev_err(rdev_to_dev(rdev),
1319 "Failed to modify Shadow QP for QP1");
1320 return rc;
1321 }
1322
1323 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1324 int qp_attr_mask, struct ib_udata *udata)
1325 {
1326 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1327 struct bnxt_re_dev *rdev = qp->rdev;
1328 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
1329 enum ib_qp_state curr_qp_state, new_qp_state;
1330 int rc, entries;
1331 int status;
1332 union ib_gid sgid;
1333 struct ib_gid_attr sgid_attr;
1334 u8 nw_type;
1335
1336 qp->qplib_qp.modify_flags = 0;
1337 if (qp_attr_mask & IB_QP_STATE) {
1338 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state);
1339 new_qp_state = qp_attr->qp_state;
1340 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state,
1341 ib_qp->qp_type, qp_attr_mask,
1342 IB_LINK_LAYER_ETHERNET)) {
1343 dev_err(rdev_to_dev(rdev),
1344 "Invalid attribute mask: %#x specified ",
1345 qp_attr_mask);
1346 dev_err(rdev_to_dev(rdev),
1347 "for qpn: %#x type: %#x",
1348 ib_qp->qp_num, ib_qp->qp_type);
1349 dev_err(rdev_to_dev(rdev),
1350 "curr_qp_state=0x%x, new_qp_state=0x%x\n",
1351 curr_qp_state, new_qp_state);
1352 return -EINVAL;
1353 }
1354 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE;
1355 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state);
1356
1357 if (!qp->sumem &&
1358 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) {
1359 dev_dbg(rdev_to_dev(rdev),
1360 "Move QP = %p to flush list\n",
1361 qp);
1362 bnxt_qplib_add_flush_qp(&qp->qplib_qp);
1363 }
1364 if (!qp->sumem &&
1365 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) {
1366 dev_dbg(rdev_to_dev(rdev),
1367 "Move QP = %p out of flush list\n",
1368 qp);
1369 bnxt_qplib_del_flush_qp(&qp->qplib_qp);
1370 }
1371 }
1372 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) {
1373 qp->qplib_qp.modify_flags |=
1374 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY;
1375 qp->qplib_qp.en_sqd_async_notify = true;
1376 }
1377 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) {
1378 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS;
1379 qp->qplib_qp.access =
1380 __from_ib_access_flags(qp_attr->qp_access_flags);
1381 /* LOCAL_WRITE access must be set to allow RC receive */
1382 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE;
1383 }
1384 if (qp_attr_mask & IB_QP_PKEY_INDEX) {
1385 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY;
1386 qp->qplib_qp.pkey_index = qp_attr->pkey_index;
1387 }
1388 if (qp_attr_mask & IB_QP_QKEY) {
1389 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY;
1390 qp->qplib_qp.qkey = qp_attr->qkey;
1391 }
1392 if (qp_attr_mask & IB_QP_AV) {
1393 const struct ib_global_route *grh =
1394 rdma_ah_read_grh(&qp_attr->ah_attr);
1395
1396 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID |
1397 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL |
1398 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX |
1399 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT |
1400 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS |
1401 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC |
1402 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID;
1403 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw,
1404 sizeof(qp->qplib_qp.ah.dgid.data));
1405 qp->qplib_qp.ah.flow_label = grh->flow_label;
1406 /* If RoCE V2 is enabled, stack will have two entries for
1407 * each GID entry. Avoiding this duplicte entry in HW. Dividing
1408 * the GID index by 2 for RoCE V2
1409 */
1410 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2;
1411 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index;
1412 qp->qplib_qp.ah.hop_limit = grh->hop_limit;
1413 qp->qplib_qp.ah.traffic_class = grh->traffic_class;
1414 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr);
1415 ether_addr_copy(qp->qplib_qp.ah.dmac,
1416 qp_attr->ah_attr.roce.dmac);
1417
1418 status = ib_get_cached_gid(&rdev->ibdev, 1,
1419 grh->sgid_index,
1420 &sgid, &sgid_attr);
1421 if (!status && sgid_attr.ndev) {
1422 memcpy(qp->qplib_qp.smac, sgid_attr.ndev->dev_addr,
1423 ETH_ALEN);
1424 dev_put(sgid_attr.ndev);
1425 nw_type = ib_gid_to_network_type(sgid_attr.gid_type,
1426 &sgid);
1427 switch (nw_type) {
1428 case RDMA_NETWORK_IPV4:
1429 qp->qplib_qp.nw_type =
1430 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4;
1431 break;
1432 case RDMA_NETWORK_IPV6:
1433 qp->qplib_qp.nw_type =
1434 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6;
1435 break;
1436 default:
1437 qp->qplib_qp.nw_type =
1438 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1;
1439 break;
1440 }
1441 }
1442 }
1443
1444 if (qp_attr_mask & IB_QP_PATH_MTU) {
1445 qp->qplib_qp.modify_flags |=
1446 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1447 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu);
1448 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu);
1449 } else if (qp_attr->qp_state == IB_QPS_RTR) {
1450 qp->qplib_qp.modify_flags |=
1451 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU;
1452 qp->qplib_qp.path_mtu =
1453 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu));
1454 qp->qplib_qp.mtu =
1455 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu));
1456 }
1457
1458 if (qp_attr_mask & IB_QP_TIMEOUT) {
1459 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT;
1460 qp->qplib_qp.timeout = qp_attr->timeout;
1461 }
1462 if (qp_attr_mask & IB_QP_RETRY_CNT) {
1463 qp->qplib_qp.modify_flags |=
1464 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT;
1465 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt;
1466 }
1467 if (qp_attr_mask & IB_QP_RNR_RETRY) {
1468 qp->qplib_qp.modify_flags |=
1469 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY;
1470 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry;
1471 }
1472 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) {
1473 qp->qplib_qp.modify_flags |=
1474 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER;
1475 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer;
1476 }
1477 if (qp_attr_mask & IB_QP_RQ_PSN) {
1478 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN;
1479 qp->qplib_qp.rq.psn = qp_attr->rq_psn;
1480 }
1481 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1482 qp->qplib_qp.modify_flags |=
1483 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC;
1484 /* Cap the max_rd_atomic to device max */
1485 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic,
1486 dev_attr->max_qp_rd_atom);
1487 }
1488 if (qp_attr_mask & IB_QP_SQ_PSN) {
1489 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN;
1490 qp->qplib_qp.sq.psn = qp_attr->sq_psn;
1491 }
1492 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1493 if (qp_attr->max_dest_rd_atomic >
1494 dev_attr->max_qp_init_rd_atom) {
1495 dev_err(rdev_to_dev(rdev),
1496 "max_dest_rd_atomic requested%d is > dev_max%d",
1497 qp_attr->max_dest_rd_atomic,
1498 dev_attr->max_qp_init_rd_atom);
1499 return -EINVAL;
1500 }
1501
1502 qp->qplib_qp.modify_flags |=
1503 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC;
1504 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic;
1505 }
1506 if (qp_attr_mask & IB_QP_CAP) {
1507 qp->qplib_qp.modify_flags |=
1508 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE |
1509 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE |
1510 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE |
1511 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE |
1512 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA;
1513 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) ||
1514 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) ||
1515 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) ||
1516 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) ||
1517 (qp_attr->cap.max_inline_data >=
1518 dev_attr->max_inline_data)) {
1519 dev_err(rdev_to_dev(rdev),
1520 "Create QP failed - max exceeded");
1521 return -EINVAL;
1522 }
1523 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr);
1524 qp->qplib_qp.sq.max_wqe = min_t(u32, entries,
1525 dev_attr->max_qp_wqes + 1);
1526 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe -
1527 qp_attr->cap.max_send_wr;
1528 /*
1529 * Reserving one slot for Phantom WQE. Some application can
1530 * post one extra entry in this case. Allowing this to avoid
1531 * unexpected Queue full condition
1532 */
1533 qp->qplib_qp.sq.q_full_delta -= 1;
1534 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge;
1535 if (qp->qplib_qp.rq.max_wqe) {
1536 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr);
1537 qp->qplib_qp.rq.max_wqe =
1538 min_t(u32, entries, dev_attr->max_qp_wqes + 1);
1539 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe -
1540 qp_attr->cap.max_recv_wr;
1541 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge;
1542 } else {
1543 /* SRQ was used prior, just ignore the RQ caps */
1544 }
1545 }
1546 if (qp_attr_mask & IB_QP_DEST_QPN) {
1547 qp->qplib_qp.modify_flags |=
1548 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID;
1549 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num;
1550 }
1551 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp);
1552 if (rc) {
1553 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP");
1554 return rc;
1555 }
1556 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp)
1557 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask);
1558 return rc;
1559 }
1560
1561 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr,
1562 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1563 {
1564 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
1565 struct bnxt_re_dev *rdev = qp->rdev;
1566 struct bnxt_qplib_qp *qplib_qp;
1567 int rc;
1568
1569 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL);
1570 if (!qplib_qp)
1571 return -ENOMEM;
1572
1573 qplib_qp->id = qp->qplib_qp.id;
1574 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index;
1575
1576 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp);
1577 if (rc) {
1578 dev_err(rdev_to_dev(rdev), "Failed to query HW QP");
1579 goto out;
1580 }
1581 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state);
1582 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0;
1583 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access);
1584 qp_attr->pkey_index = qplib_qp->pkey_index;
1585 qp_attr->qkey = qplib_qp->qkey;
1586 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE;
1587 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label,
1588 qplib_qp->ah.host_sgid_index,
1589 qplib_qp->ah.hop_limit,
1590 qplib_qp->ah.traffic_class);
1591 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data);
1592 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl);
1593 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac);
1594 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu);
1595 qp_attr->timeout = qplib_qp->timeout;
1596 qp_attr->retry_cnt = qplib_qp->retry_cnt;
1597 qp_attr->rnr_retry = qplib_qp->rnr_retry;
1598 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer;
1599 qp_attr->rq_psn = qplib_qp->rq.psn;
1600 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic;
1601 qp_attr->sq_psn = qplib_qp->sq.psn;
1602 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic;
1603 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR :
1604 IB_SIGNAL_REQ_WR;
1605 qp_attr->dest_qp_num = qplib_qp->dest_qpn;
1606
1607 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe;
1608 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge;
1609 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe;
1610 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge;
1611 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data;
1612 qp_init_attr->cap = qp_attr->cap;
1613
1614 out:
1615 kfree(qplib_qp);
1616 return rc;
1617 }
1618
1619 /* Routine for sending QP1 packets for RoCE V1 an V2
1620 */
1621 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp,
1622 struct ib_send_wr *wr,
1623 struct bnxt_qplib_swqe *wqe,
1624 int payload_size)
1625 {
1626 struct ib_device *ibdev = &qp->rdev->ibdev;
1627 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah,
1628 ib_ah);
1629 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah;
1630 struct bnxt_qplib_sge sge;
1631 union ib_gid sgid;
1632 u8 nw_type;
1633 u16 ether_type;
1634 struct ib_gid_attr sgid_attr;
1635 union ib_gid dgid;
1636 bool is_eth = false;
1637 bool is_vlan = false;
1638 bool is_grh = false;
1639 bool is_udp = false;
1640 u8 ip_version = 0;
1641 u16 vlan_id = 0xFFFF;
1642 void *buf;
1643 int i, rc = 0;
1644
1645 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr));
1646
1647 rc = ib_get_cached_gid(ibdev, 1,
1648 qplib_ah->host_sgid_index, &sgid,
1649 &sgid_attr);
1650 if (rc) {
1651 dev_err(rdev_to_dev(qp->rdev),
1652 "Failed to query gid at index %d",
1653 qplib_ah->host_sgid_index);
1654 return rc;
1655 }
1656 if (sgid_attr.ndev) {
1657 if (is_vlan_dev(sgid_attr.ndev))
1658 vlan_id = vlan_dev_vlan_id(sgid_attr.ndev);
1659 dev_put(sgid_attr.ndev);
1660 }
1661 /* Get network header type for this GID */
1662 nw_type = ib_gid_to_network_type(sgid_attr.gid_type, &sgid);
1663 switch (nw_type) {
1664 case RDMA_NETWORK_IPV4:
1665 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET;
1666 break;
1667 case RDMA_NETWORK_IPV6:
1668 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET;
1669 break;
1670 default:
1671 nw_type = BNXT_RE_ROCE_V1_PACKET;
1672 break;
1673 }
1674 memcpy(&dgid.raw, &qplib_ah->dgid, 16);
1675 is_udp = sgid_attr.gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
1676 if (is_udp) {
1677 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid)) {
1678 ip_version = 4;
1679 ether_type = ETH_P_IP;
1680 } else {
1681 ip_version = 6;
1682 ether_type = ETH_P_IPV6;
1683 }
1684 is_grh = false;
1685 } else {
1686 ether_type = ETH_P_IBOE;
1687 is_grh = true;
1688 }
1689
1690 is_eth = true;
1691 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false;
1692
1693 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh,
1694 ip_version, is_udp, 0, &qp->qp1_hdr);
1695
1696 /* ETH */
1697 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac);
1698 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac);
1699
1700 /* For vlan, check the sgid for vlan existence */
1701
1702 if (!is_vlan) {
1703 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type);
1704 } else {
1705 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type);
1706 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id);
1707 }
1708
1709 if (is_grh || (ip_version == 6)) {
1710 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid.raw, sizeof(sgid));
1711 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data,
1712 sizeof(sgid));
1713 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit;
1714 }
1715
1716 if (ip_version == 4) {
1717 qp->qp1_hdr.ip4.tos = 0;
1718 qp->qp1_hdr.ip4.id = 0;
1719 qp->qp1_hdr.ip4.frag_off = htons(IP_DF);
1720 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit;
1721
1722 memcpy(&qp->qp1_hdr.ip4.saddr, sgid.raw + 12, 4);
1723 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4);
1724 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr);
1725 }
1726
1727 if (is_udp) {
1728 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT);
1729 qp->qp1_hdr.udp.sport = htons(0x8CD1);
1730 qp->qp1_hdr.udp.csum = 0;
1731 }
1732
1733 /* BTH */
1734 if (wr->opcode == IB_WR_SEND_WITH_IMM) {
1735 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1736 qp->qp1_hdr.immediate_present = 1;
1737 } else {
1738 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1739 }
1740 if (wr->send_flags & IB_SEND_SOLICITED)
1741 qp->qp1_hdr.bth.solicited_event = 1;
1742 /* pad_count */
1743 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3;
1744
1745 /* P_key for QP1 is for all members */
1746 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF);
1747 qp->qp1_hdr.bth.destination_qpn = IB_QP1;
1748 qp->qp1_hdr.bth.ack_req = 0;
1749 qp->send_psn++;
1750 qp->send_psn &= BTH_PSN_MASK;
1751 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn);
1752 /* DETH */
1753 /* Use the priviledged Q_Key for QP1 */
1754 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY);
1755 qp->qp1_hdr.deth.source_qpn = IB_QP1;
1756
1757 /* Pack the QP1 to the transmit buffer */
1758 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge);
1759 if (buf) {
1760 ib_ud_header_pack(&qp->qp1_hdr, buf);
1761 for (i = wqe->num_sge; i; i--) {
1762 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr;
1763 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey;
1764 wqe->sg_list[i].size = wqe->sg_list[i - 1].size;
1765 }
1766
1767 /*
1768 * Max Header buf size for IPV6 RoCE V2 is 86,
1769 * which is same as the QP1 SQ header buffer.
1770 * Header buf size for IPV4 RoCE V2 can be 66.
1771 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20).
1772 * Subtract 20 bytes from QP1 SQ header buf size
1773 */
1774 if (is_udp && ip_version == 4)
1775 sge.size -= 20;
1776 /*
1777 * Max Header buf size for RoCE V1 is 78.
1778 * ETH(14) + VLAN(4) + GRH(40) + BTH(20).
1779 * Subtract 8 bytes from QP1 SQ header buf size
1780 */
1781 if (!is_udp)
1782 sge.size -= 8;
1783
1784 /* Subtract 4 bytes for non vlan packets */
1785 if (!is_vlan)
1786 sge.size -= 4;
1787
1788 wqe->sg_list[0].addr = sge.addr;
1789 wqe->sg_list[0].lkey = sge.lkey;
1790 wqe->sg_list[0].size = sge.size;
1791 wqe->num_sge++;
1792
1793 } else {
1794 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!");
1795 rc = -ENOMEM;
1796 }
1797 return rc;
1798 }
1799
1800 /* For the MAD layer, it only provides the recv SGE the size of
1801 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH,
1802 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire
1803 * receive packet (334 bytes) with no VLAN and then copy the GRH
1804 * and the MAD datagram out to the provided SGE.
1805 */
1806 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp,
1807 struct ib_recv_wr *wr,
1808 struct bnxt_qplib_swqe *wqe,
1809 int payload_size)
1810 {
1811 struct bnxt_qplib_sge ref, sge;
1812 u32 rq_prod_index;
1813 struct bnxt_re_sqp_entries *sqp_entry;
1814
1815 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp);
1816
1817 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge))
1818 return -ENOMEM;
1819
1820 /* Create 1 SGE to receive the entire
1821 * ethernet packet
1822 */
1823 /* Save the reference from ULP */
1824 ref.addr = wqe->sg_list[0].addr;
1825 ref.lkey = wqe->sg_list[0].lkey;
1826 ref.size = wqe->sg_list[0].size;
1827
1828 sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index];
1829
1830 /* SGE 1 */
1831 wqe->sg_list[0].addr = sge.addr;
1832 wqe->sg_list[0].lkey = sge.lkey;
1833 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2;
1834 sge.size -= wqe->sg_list[0].size;
1835
1836 sqp_entry->sge.addr = ref.addr;
1837 sqp_entry->sge.lkey = ref.lkey;
1838 sqp_entry->sge.size = ref.size;
1839 /* Store the wrid for reporting completion */
1840 sqp_entry->wrid = wqe->wr_id;
1841 /* change the wqe->wrid to table index */
1842 wqe->wr_id = rq_prod_index;
1843 return 0;
1844 }
1845
1846 static int is_ud_qp(struct bnxt_re_qp *qp)
1847 {
1848 return qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD;
1849 }
1850
1851 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp,
1852 struct ib_send_wr *wr,
1853 struct bnxt_qplib_swqe *wqe)
1854 {
1855 struct bnxt_re_ah *ah = NULL;
1856
1857 if (is_ud_qp(qp)) {
1858 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah);
1859 wqe->send.q_key = ud_wr(wr)->remote_qkey;
1860 wqe->send.dst_qp = ud_wr(wr)->remote_qpn;
1861 wqe->send.avid = ah->qplib_ah.id;
1862 }
1863 switch (wr->opcode) {
1864 case IB_WR_SEND:
1865 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND;
1866 break;
1867 case IB_WR_SEND_WITH_IMM:
1868 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM;
1869 wqe->send.imm_data = wr->ex.imm_data;
1870 break;
1871 case IB_WR_SEND_WITH_INV:
1872 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV;
1873 wqe->send.inv_key = wr->ex.invalidate_rkey;
1874 break;
1875 default:
1876 return -EINVAL;
1877 }
1878 if (wr->send_flags & IB_SEND_SIGNALED)
1879 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1880 if (wr->send_flags & IB_SEND_FENCE)
1881 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1882 if (wr->send_flags & IB_SEND_SOLICITED)
1883 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1884 if (wr->send_flags & IB_SEND_INLINE)
1885 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
1886
1887 return 0;
1888 }
1889
1890 static int bnxt_re_build_rdma_wqe(struct ib_send_wr *wr,
1891 struct bnxt_qplib_swqe *wqe)
1892 {
1893 switch (wr->opcode) {
1894 case IB_WR_RDMA_WRITE:
1895 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE;
1896 break;
1897 case IB_WR_RDMA_WRITE_WITH_IMM:
1898 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM;
1899 wqe->rdma.imm_data = wr->ex.imm_data;
1900 break;
1901 case IB_WR_RDMA_READ:
1902 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ;
1903 wqe->rdma.inv_key = wr->ex.invalidate_rkey;
1904 break;
1905 default:
1906 return -EINVAL;
1907 }
1908 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr;
1909 wqe->rdma.r_key = rdma_wr(wr)->rkey;
1910 if (wr->send_flags & IB_SEND_SIGNALED)
1911 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1912 if (wr->send_flags & IB_SEND_FENCE)
1913 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1914 if (wr->send_flags & IB_SEND_SOLICITED)
1915 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1916 if (wr->send_flags & IB_SEND_INLINE)
1917 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE;
1918
1919 return 0;
1920 }
1921
1922 static int bnxt_re_build_atomic_wqe(struct ib_send_wr *wr,
1923 struct bnxt_qplib_swqe *wqe)
1924 {
1925 switch (wr->opcode) {
1926 case IB_WR_ATOMIC_CMP_AND_SWP:
1927 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP;
1928 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
1929 wqe->atomic.swap_data = atomic_wr(wr)->swap;
1930 break;
1931 case IB_WR_ATOMIC_FETCH_AND_ADD:
1932 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD;
1933 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add;
1934 break;
1935 default:
1936 return -EINVAL;
1937 }
1938 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr;
1939 wqe->atomic.r_key = atomic_wr(wr)->rkey;
1940 if (wr->send_flags & IB_SEND_SIGNALED)
1941 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1942 if (wr->send_flags & IB_SEND_FENCE)
1943 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1944 if (wr->send_flags & IB_SEND_SOLICITED)
1945 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1946 return 0;
1947 }
1948
1949 static int bnxt_re_build_inv_wqe(struct ib_send_wr *wr,
1950 struct bnxt_qplib_swqe *wqe)
1951 {
1952 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV;
1953 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey;
1954
1955 /* Need unconditional fence for local invalidate
1956 * opcode to work as expected.
1957 */
1958 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1959
1960 if (wr->send_flags & IB_SEND_SIGNALED)
1961 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1962 if (wr->send_flags & IB_SEND_SOLICITED)
1963 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT;
1964
1965 return 0;
1966 }
1967
1968 static int bnxt_re_build_reg_wqe(struct ib_reg_wr *wr,
1969 struct bnxt_qplib_swqe *wqe)
1970 {
1971 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr);
1972 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl;
1973 int access = wr->access;
1974
1975 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0];
1976 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0];
1977 wqe->frmr.page_list = mr->pages;
1978 wqe->frmr.page_list_len = mr->npages;
1979 wqe->frmr.levels = qplib_frpl->hwq.level + 1;
1980 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR;
1981
1982 /* Need unconditional fence for reg_mr
1983 * opcode to function as expected.
1984 */
1985
1986 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE;
1987
1988 if (wr->wr.send_flags & IB_SEND_SIGNALED)
1989 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP;
1990
1991 if (access & IB_ACCESS_LOCAL_WRITE)
1992 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE;
1993 if (access & IB_ACCESS_REMOTE_READ)
1994 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ;
1995 if (access & IB_ACCESS_REMOTE_WRITE)
1996 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE;
1997 if (access & IB_ACCESS_REMOTE_ATOMIC)
1998 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC;
1999 if (access & IB_ACCESS_MW_BIND)
2000 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND;
2001
2002 wqe->frmr.l_key = wr->key;
2003 wqe->frmr.length = wr->mr->length;
2004 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1;
2005 wqe->frmr.va = wr->mr->iova;
2006 return 0;
2007 }
2008
2009 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev,
2010 struct ib_send_wr *wr,
2011 struct bnxt_qplib_swqe *wqe)
2012 {
2013 /* Copy the inline data to the data field */
2014 u8 *in_data;
2015 u32 i, sge_len;
2016 void *sge_addr;
2017
2018 in_data = wqe->inline_data;
2019 for (i = 0; i < wr->num_sge; i++) {
2020 sge_addr = (void *)(unsigned long)
2021 wr->sg_list[i].addr;
2022 sge_len = wr->sg_list[i].length;
2023
2024 if ((sge_len + wqe->inline_len) >
2025 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) {
2026 dev_err(rdev_to_dev(rdev),
2027 "Inline data size requested > supported value");
2028 return -EINVAL;
2029 }
2030 sge_len = wr->sg_list[i].length;
2031
2032 memcpy(in_data, sge_addr, sge_len);
2033 in_data += wr->sg_list[i].length;
2034 wqe->inline_len += wr->sg_list[i].length;
2035 }
2036 return wqe->inline_len;
2037 }
2038
2039 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev,
2040 struct ib_send_wr *wr,
2041 struct bnxt_qplib_swqe *wqe)
2042 {
2043 int payload_sz = 0;
2044
2045 if (wr->send_flags & IB_SEND_INLINE)
2046 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe);
2047 else
2048 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list,
2049 wqe->num_sge);
2050
2051 return payload_sz;
2052 }
2053
2054 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp)
2055 {
2056 if ((qp->ib_qp.qp_type == IB_QPT_UD ||
2057 qp->ib_qp.qp_type == IB_QPT_GSI ||
2058 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) &&
2059 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) {
2060 int qp_attr_mask;
2061 struct ib_qp_attr qp_attr;
2062
2063 qp_attr_mask = IB_QP_STATE;
2064 qp_attr.qp_state = IB_QPS_RTS;
2065 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL);
2066 qp->qplib_qp.wqe_cnt = 0;
2067 }
2068 }
2069
2070 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev,
2071 struct bnxt_re_qp *qp,
2072 struct ib_send_wr *wr)
2073 {
2074 struct bnxt_qplib_swqe wqe;
2075 int rc = 0, payload_sz = 0;
2076 unsigned long flags;
2077
2078 spin_lock_irqsave(&qp->sq_lock, flags);
2079 memset(&wqe, 0, sizeof(wqe));
2080 while (wr) {
2081 /* House keeping */
2082 memset(&wqe, 0, sizeof(wqe));
2083
2084 /* Common */
2085 wqe.num_sge = wr->num_sge;
2086 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2087 dev_err(rdev_to_dev(rdev),
2088 "Limit exceeded for Send SGEs");
2089 rc = -EINVAL;
2090 goto bad;
2091 }
2092
2093 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2094 if (payload_sz < 0) {
2095 rc = -EINVAL;
2096 goto bad;
2097 }
2098 wqe.wr_id = wr->wr_id;
2099
2100 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND;
2101
2102 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2103 if (!rc)
2104 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2105 bad:
2106 if (rc) {
2107 dev_err(rdev_to_dev(rdev),
2108 "Post send failed opcode = %#x rc = %d",
2109 wr->opcode, rc);
2110 break;
2111 }
2112 wr = wr->next;
2113 }
2114 bnxt_qplib_post_send_db(&qp->qplib_qp);
2115 bnxt_ud_qp_hw_stall_workaround(qp);
2116 spin_unlock_irqrestore(&qp->sq_lock, flags);
2117 return rc;
2118 }
2119
2120 int bnxt_re_post_send(struct ib_qp *ib_qp, struct ib_send_wr *wr,
2121 struct ib_send_wr **bad_wr)
2122 {
2123 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2124 struct bnxt_qplib_swqe wqe;
2125 int rc = 0, payload_sz = 0;
2126 unsigned long flags;
2127
2128 spin_lock_irqsave(&qp->sq_lock, flags);
2129 while (wr) {
2130 /* House keeping */
2131 memset(&wqe, 0, sizeof(wqe));
2132
2133 /* Common */
2134 wqe.num_sge = wr->num_sge;
2135 if (wr->num_sge > qp->qplib_qp.sq.max_sge) {
2136 dev_err(rdev_to_dev(qp->rdev),
2137 "Limit exceeded for Send SGEs");
2138 rc = -EINVAL;
2139 goto bad;
2140 }
2141
2142 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe);
2143 if (payload_sz < 0) {
2144 rc = -EINVAL;
2145 goto bad;
2146 }
2147 wqe.wr_id = wr->wr_id;
2148
2149 switch (wr->opcode) {
2150 case IB_WR_SEND:
2151 case IB_WR_SEND_WITH_IMM:
2152 if (ib_qp->qp_type == IB_QPT_GSI) {
2153 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe,
2154 payload_sz);
2155 if (rc)
2156 goto bad;
2157 wqe.rawqp1.lflags |=
2158 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC;
2159 }
2160 switch (wr->send_flags) {
2161 case IB_SEND_IP_CSUM:
2162 wqe.rawqp1.lflags |=
2163 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM;
2164 break;
2165 default:
2166 break;
2167 }
2168 /* Fall thru to build the wqe */
2169 case IB_WR_SEND_WITH_INV:
2170 rc = bnxt_re_build_send_wqe(qp, wr, &wqe);
2171 break;
2172 case IB_WR_RDMA_WRITE:
2173 case IB_WR_RDMA_WRITE_WITH_IMM:
2174 case IB_WR_RDMA_READ:
2175 rc = bnxt_re_build_rdma_wqe(wr, &wqe);
2176 break;
2177 case IB_WR_ATOMIC_CMP_AND_SWP:
2178 case IB_WR_ATOMIC_FETCH_AND_ADD:
2179 rc = bnxt_re_build_atomic_wqe(wr, &wqe);
2180 break;
2181 case IB_WR_RDMA_READ_WITH_INV:
2182 dev_err(rdev_to_dev(qp->rdev),
2183 "RDMA Read with Invalidate is not supported");
2184 rc = -EINVAL;
2185 goto bad;
2186 case IB_WR_LOCAL_INV:
2187 rc = bnxt_re_build_inv_wqe(wr, &wqe);
2188 break;
2189 case IB_WR_REG_MR:
2190 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe);
2191 break;
2192 default:
2193 /* Unsupported WRs */
2194 dev_err(rdev_to_dev(qp->rdev),
2195 "WR (%#x) is not supported", wr->opcode);
2196 rc = -EINVAL;
2197 goto bad;
2198 }
2199 if (!rc)
2200 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe);
2201 bad:
2202 if (rc) {
2203 dev_err(rdev_to_dev(qp->rdev),
2204 "post_send failed op:%#x qps = %#x rc = %d\n",
2205 wr->opcode, qp->qplib_qp.state, rc);
2206 *bad_wr = wr;
2207 break;
2208 }
2209 wr = wr->next;
2210 }
2211 bnxt_qplib_post_send_db(&qp->qplib_qp);
2212 bnxt_ud_qp_hw_stall_workaround(qp);
2213 spin_unlock_irqrestore(&qp->sq_lock, flags);
2214
2215 return rc;
2216 }
2217
2218 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev,
2219 struct bnxt_re_qp *qp,
2220 struct ib_recv_wr *wr)
2221 {
2222 struct bnxt_qplib_swqe wqe;
2223 int rc = 0;
2224
2225 memset(&wqe, 0, sizeof(wqe));
2226 while (wr) {
2227 /* House keeping */
2228 memset(&wqe, 0, sizeof(wqe));
2229
2230 /* Common */
2231 wqe.num_sge = wr->num_sge;
2232 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2233 dev_err(rdev_to_dev(rdev),
2234 "Limit exceeded for Receive SGEs");
2235 rc = -EINVAL;
2236 break;
2237 }
2238 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge);
2239 wqe.wr_id = wr->wr_id;
2240 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2241
2242 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2243 if (rc)
2244 break;
2245
2246 wr = wr->next;
2247 }
2248 if (!rc)
2249 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2250 return rc;
2251 }
2252
2253 int bnxt_re_post_recv(struct ib_qp *ib_qp, struct ib_recv_wr *wr,
2254 struct ib_recv_wr **bad_wr)
2255 {
2256 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp);
2257 struct bnxt_qplib_swqe wqe;
2258 int rc = 0, payload_sz = 0;
2259 unsigned long flags;
2260 u32 count = 0;
2261
2262 spin_lock_irqsave(&qp->rq_lock, flags);
2263 while (wr) {
2264 /* House keeping */
2265 memset(&wqe, 0, sizeof(wqe));
2266
2267 /* Common */
2268 wqe.num_sge = wr->num_sge;
2269 if (wr->num_sge > qp->qplib_qp.rq.max_sge) {
2270 dev_err(rdev_to_dev(qp->rdev),
2271 "Limit exceeded for Receive SGEs");
2272 rc = -EINVAL;
2273 *bad_wr = wr;
2274 break;
2275 }
2276
2277 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list,
2278 wr->num_sge);
2279 wqe.wr_id = wr->wr_id;
2280 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV;
2281
2282 if (ib_qp->qp_type == IB_QPT_GSI)
2283 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe,
2284 payload_sz);
2285 if (!rc)
2286 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe);
2287 if (rc) {
2288 *bad_wr = wr;
2289 break;
2290 }
2291
2292 /* Ring DB if the RQEs posted reaches a threshold value */
2293 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) {
2294 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2295 count = 0;
2296 }
2297
2298 wr = wr->next;
2299 }
2300
2301 if (count)
2302 bnxt_qplib_post_recv_db(&qp->qplib_qp);
2303
2304 spin_unlock_irqrestore(&qp->rq_lock, flags);
2305
2306 return rc;
2307 }
2308
2309 /* Completion Queues */
2310 int bnxt_re_destroy_cq(struct ib_cq *ib_cq)
2311 {
2312 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2313 struct bnxt_re_dev *rdev = cq->rdev;
2314 int rc;
2315 struct bnxt_qplib_nq *nq = cq->qplib_cq.nq;
2316
2317 rc = bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2318 if (rc) {
2319 dev_err(rdev_to_dev(rdev), "Failed to destroy HW CQ");
2320 return rc;
2321 }
2322 if (!IS_ERR_OR_NULL(cq->umem))
2323 ib_umem_release(cq->umem);
2324
2325 if (cq) {
2326 kfree(cq->cql);
2327 kfree(cq);
2328 }
2329 atomic_dec(&rdev->cq_count);
2330 nq->budget--;
2331 return 0;
2332 }
2333
2334 struct ib_cq *bnxt_re_create_cq(struct ib_device *ibdev,
2335 const struct ib_cq_init_attr *attr,
2336 struct ib_ucontext *context,
2337 struct ib_udata *udata)
2338 {
2339 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
2340 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
2341 struct bnxt_re_cq *cq = NULL;
2342 int rc, entries;
2343 int cqe = attr->cqe;
2344 struct bnxt_qplib_nq *nq = NULL;
2345 unsigned int nq_alloc_cnt;
2346
2347 /* Validate CQ fields */
2348 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) {
2349 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded");
2350 return ERR_PTR(-EINVAL);
2351 }
2352 cq = kzalloc(sizeof(*cq), GFP_KERNEL);
2353 if (!cq)
2354 return ERR_PTR(-ENOMEM);
2355
2356 cq->rdev = rdev;
2357 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq);
2358
2359 entries = roundup_pow_of_two(cqe + 1);
2360 if (entries > dev_attr->max_cq_wqes + 1)
2361 entries = dev_attr->max_cq_wqes + 1;
2362
2363 if (context) {
2364 struct bnxt_re_cq_req req;
2365 struct bnxt_re_ucontext *uctx = container_of
2366 (context,
2367 struct bnxt_re_ucontext,
2368 ib_uctx);
2369 if (ib_copy_from_udata(&req, udata, sizeof(req))) {
2370 rc = -EFAULT;
2371 goto fail;
2372 }
2373
2374 cq->umem = ib_umem_get(context, req.cq_va,
2375 entries * sizeof(struct cq_base),
2376 IB_ACCESS_LOCAL_WRITE, 1);
2377 if (IS_ERR(cq->umem)) {
2378 rc = PTR_ERR(cq->umem);
2379 goto fail;
2380 }
2381 cq->qplib_cq.sghead = cq->umem->sg_head.sgl;
2382 cq->qplib_cq.nmap = cq->umem->nmap;
2383 cq->qplib_cq.dpi = &uctx->dpi;
2384 } else {
2385 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL);
2386 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe),
2387 GFP_KERNEL);
2388 if (!cq->cql) {
2389 rc = -ENOMEM;
2390 goto fail;
2391 }
2392
2393 cq->qplib_cq.dpi = &rdev->dpi_privileged;
2394 cq->qplib_cq.sghead = NULL;
2395 cq->qplib_cq.nmap = 0;
2396 }
2397 /*
2398 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a
2399 * used for getting the NQ index.
2400 */
2401 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt);
2402 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)];
2403 cq->qplib_cq.max_wqe = entries;
2404 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id;
2405 cq->qplib_cq.nq = nq;
2406
2407 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq);
2408 if (rc) {
2409 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ");
2410 goto fail;
2411 }
2412
2413 cq->ib_cq.cqe = entries;
2414 cq->cq_period = cq->qplib_cq.period;
2415 nq->budget++;
2416
2417 atomic_inc(&rdev->cq_count);
2418
2419 if (context) {
2420 struct bnxt_re_cq_resp resp;
2421
2422 resp.cqid = cq->qplib_cq.id;
2423 resp.tail = cq->qplib_cq.hwq.cons;
2424 resp.phase = cq->qplib_cq.period;
2425 resp.rsvd = 0;
2426 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
2427 if (rc) {
2428 dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata");
2429 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq);
2430 goto c2fail;
2431 }
2432 }
2433
2434 return &cq->ib_cq;
2435
2436 c2fail:
2437 if (context)
2438 ib_umem_release(cq->umem);
2439 fail:
2440 kfree(cq->cql);
2441 kfree(cq);
2442 return ERR_PTR(rc);
2443 }
2444
2445 static u8 __req_to_ib_wc_status(u8 qstatus)
2446 {
2447 switch (qstatus) {
2448 case CQ_REQ_STATUS_OK:
2449 return IB_WC_SUCCESS;
2450 case CQ_REQ_STATUS_BAD_RESPONSE_ERR:
2451 return IB_WC_BAD_RESP_ERR;
2452 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR:
2453 return IB_WC_LOC_LEN_ERR;
2454 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR:
2455 return IB_WC_LOC_QP_OP_ERR;
2456 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR:
2457 return IB_WC_LOC_PROT_ERR;
2458 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR:
2459 return IB_WC_GENERAL_ERR;
2460 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR:
2461 return IB_WC_REM_INV_REQ_ERR;
2462 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR:
2463 return IB_WC_REM_ACCESS_ERR;
2464 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR:
2465 return IB_WC_REM_OP_ERR;
2466 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR:
2467 return IB_WC_RNR_RETRY_EXC_ERR;
2468 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR:
2469 return IB_WC_RETRY_EXC_ERR;
2470 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR:
2471 return IB_WC_WR_FLUSH_ERR;
2472 default:
2473 return IB_WC_GENERAL_ERR;
2474 }
2475 return 0;
2476 }
2477
2478 static u8 __rawqp1_to_ib_wc_status(u8 qstatus)
2479 {
2480 switch (qstatus) {
2481 case CQ_RES_RAWETH_QP1_STATUS_OK:
2482 return IB_WC_SUCCESS;
2483 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR:
2484 return IB_WC_LOC_ACCESS_ERR;
2485 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR:
2486 return IB_WC_LOC_LEN_ERR;
2487 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR:
2488 return IB_WC_LOC_PROT_ERR;
2489 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR:
2490 return IB_WC_LOC_QP_OP_ERR;
2491 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR:
2492 return IB_WC_GENERAL_ERR;
2493 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR:
2494 return IB_WC_WR_FLUSH_ERR;
2495 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR:
2496 return IB_WC_WR_FLUSH_ERR;
2497 default:
2498 return IB_WC_GENERAL_ERR;
2499 }
2500 }
2501
2502 static u8 __rc_to_ib_wc_status(u8 qstatus)
2503 {
2504 switch (qstatus) {
2505 case CQ_RES_RC_STATUS_OK:
2506 return IB_WC_SUCCESS;
2507 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR:
2508 return IB_WC_LOC_ACCESS_ERR;
2509 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR:
2510 return IB_WC_LOC_LEN_ERR;
2511 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR:
2512 return IB_WC_LOC_PROT_ERR;
2513 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR:
2514 return IB_WC_LOC_QP_OP_ERR;
2515 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR:
2516 return IB_WC_GENERAL_ERR;
2517 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR:
2518 return IB_WC_REM_INV_REQ_ERR;
2519 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR:
2520 return IB_WC_WR_FLUSH_ERR;
2521 case CQ_RES_RC_STATUS_HW_FLUSH_ERR:
2522 return IB_WC_WR_FLUSH_ERR;
2523 default:
2524 return IB_WC_GENERAL_ERR;
2525 }
2526 }
2527
2528 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe)
2529 {
2530 switch (cqe->type) {
2531 case BNXT_QPLIB_SWQE_TYPE_SEND:
2532 wc->opcode = IB_WC_SEND;
2533 break;
2534 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM:
2535 wc->opcode = IB_WC_SEND;
2536 wc->wc_flags |= IB_WC_WITH_IMM;
2537 break;
2538 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV:
2539 wc->opcode = IB_WC_SEND;
2540 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2541 break;
2542 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE:
2543 wc->opcode = IB_WC_RDMA_WRITE;
2544 break;
2545 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM:
2546 wc->opcode = IB_WC_RDMA_WRITE;
2547 wc->wc_flags |= IB_WC_WITH_IMM;
2548 break;
2549 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ:
2550 wc->opcode = IB_WC_RDMA_READ;
2551 break;
2552 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP:
2553 wc->opcode = IB_WC_COMP_SWAP;
2554 break;
2555 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD:
2556 wc->opcode = IB_WC_FETCH_ADD;
2557 break;
2558 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV:
2559 wc->opcode = IB_WC_LOCAL_INV;
2560 break;
2561 case BNXT_QPLIB_SWQE_TYPE_REG_MR:
2562 wc->opcode = IB_WC_REG_MR;
2563 break;
2564 default:
2565 wc->opcode = IB_WC_SEND;
2566 break;
2567 }
2568
2569 wc->status = __req_to_ib_wc_status(cqe->status);
2570 }
2571
2572 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags,
2573 u16 raweth_qp1_flags2)
2574 {
2575 bool is_ipv6 = false, is_ipv4 = false;
2576
2577 /* raweth_qp1_flags Bit 9-6 indicates itype */
2578 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2579 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE)
2580 return -1;
2581
2582 if (raweth_qp1_flags2 &
2583 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC &&
2584 raweth_qp1_flags2 &
2585 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) {
2586 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */
2587 (raweth_qp1_flags2 &
2588 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ?
2589 (is_ipv6 = true) : (is_ipv4 = true);
2590 return ((is_ipv6) ?
2591 BNXT_RE_ROCEV2_IPV6_PACKET :
2592 BNXT_RE_ROCEV2_IPV4_PACKET);
2593 } else {
2594 return BNXT_RE_ROCE_V1_PACKET;
2595 }
2596 }
2597
2598 static int bnxt_re_to_ib_nw_type(int nw_type)
2599 {
2600 u8 nw_hdr_type = 0xFF;
2601
2602 switch (nw_type) {
2603 case BNXT_RE_ROCE_V1_PACKET:
2604 nw_hdr_type = RDMA_NETWORK_ROCE_V1;
2605 break;
2606 case BNXT_RE_ROCEV2_IPV4_PACKET:
2607 nw_hdr_type = RDMA_NETWORK_IPV4;
2608 break;
2609 case BNXT_RE_ROCEV2_IPV6_PACKET:
2610 nw_hdr_type = RDMA_NETWORK_IPV6;
2611 break;
2612 }
2613 return nw_hdr_type;
2614 }
2615
2616 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev,
2617 void *rq_hdr_buf)
2618 {
2619 u8 *tmp_buf = NULL;
2620 struct ethhdr *eth_hdr;
2621 u16 eth_type;
2622 bool rc = false;
2623
2624 tmp_buf = (u8 *)rq_hdr_buf;
2625 /*
2626 * If dest mac is not same as I/F mac, this could be a
2627 * loopback address or multicast address, check whether
2628 * it is a loopback packet
2629 */
2630 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) {
2631 tmp_buf += 4;
2632 /* Check the ether type */
2633 eth_hdr = (struct ethhdr *)tmp_buf;
2634 eth_type = ntohs(eth_hdr->h_proto);
2635 switch (eth_type) {
2636 case ETH_P_IBOE:
2637 rc = true;
2638 break;
2639 case ETH_P_IP:
2640 case ETH_P_IPV6: {
2641 u32 len;
2642 struct udphdr *udp_hdr;
2643
2644 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) :
2645 sizeof(struct ipv6hdr));
2646 tmp_buf += sizeof(struct ethhdr) + len;
2647 udp_hdr = (struct udphdr *)tmp_buf;
2648 if (ntohs(udp_hdr->dest) ==
2649 ROCE_V2_UDP_DPORT)
2650 rc = true;
2651 break;
2652 }
2653 default:
2654 break;
2655 }
2656 }
2657
2658 return rc;
2659 }
2660
2661 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp,
2662 struct bnxt_qplib_cqe *cqe)
2663 {
2664 struct bnxt_re_dev *rdev = qp1_qp->rdev;
2665 struct bnxt_re_sqp_entries *sqp_entry = NULL;
2666 struct bnxt_re_qp *qp = rdev->qp1_sqp;
2667 struct ib_send_wr *swr;
2668 struct ib_ud_wr udwr;
2669 struct ib_recv_wr rwr;
2670 int pkt_type = 0;
2671 u32 tbl_idx;
2672 void *rq_hdr_buf;
2673 dma_addr_t rq_hdr_buf_map;
2674 dma_addr_t shrq_hdr_buf_map;
2675 u32 offset = 0;
2676 u32 skip_bytes = 0;
2677 struct ib_sge s_sge[2];
2678 struct ib_sge r_sge[2];
2679 int rc;
2680
2681 memset(&udwr, 0, sizeof(udwr));
2682 memset(&rwr, 0, sizeof(rwr));
2683 memset(&s_sge, 0, sizeof(s_sge));
2684 memset(&r_sge, 0, sizeof(r_sge));
2685
2686 swr = &udwr.wr;
2687 tbl_idx = cqe->wr_id;
2688
2689 rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf +
2690 (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size);
2691 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp,
2692 tbl_idx);
2693
2694 /* Shadow QP header buffer */
2695 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp,
2696 tbl_idx);
2697 sqp_entry = &rdev->sqp_tbl[tbl_idx];
2698
2699 /* Store this cqe */
2700 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe));
2701 sqp_entry->qp1_qp = qp1_qp;
2702
2703 /* Find packet type from the cqe */
2704
2705 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags,
2706 cqe->raweth_qp1_flags2);
2707 if (pkt_type < 0) {
2708 dev_err(rdev_to_dev(rdev), "Invalid packet\n");
2709 return -EINVAL;
2710 }
2711
2712 /* Adjust the offset for the user buffer and post in the rq */
2713
2714 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET)
2715 offset = 20;
2716
2717 /*
2718 * QP1 loopback packet has 4 bytes of internal header before
2719 * ether header. Skip these four bytes.
2720 */
2721 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf))
2722 skip_bytes = 4;
2723
2724 /* First send SGE . Skip the ether header*/
2725 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE
2726 + skip_bytes;
2727 s_sge[0].lkey = 0xFFFFFFFF;
2728 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 :
2729 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6;
2730
2731 /* Second Send SGE */
2732 s_sge[1].addr = s_sge[0].addr + s_sge[0].length +
2733 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE;
2734 if (pkt_type != BNXT_RE_ROCE_V1_PACKET)
2735 s_sge[1].addr += 8;
2736 s_sge[1].lkey = 0xFFFFFFFF;
2737 s_sge[1].length = 256;
2738
2739 /* First recv SGE */
2740
2741 r_sge[0].addr = shrq_hdr_buf_map;
2742 r_sge[0].lkey = 0xFFFFFFFF;
2743 r_sge[0].length = 40;
2744
2745 r_sge[1].addr = sqp_entry->sge.addr + offset;
2746 r_sge[1].lkey = sqp_entry->sge.lkey;
2747 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset;
2748
2749 /* Create receive work request */
2750 rwr.num_sge = 2;
2751 rwr.sg_list = r_sge;
2752 rwr.wr_id = tbl_idx;
2753 rwr.next = NULL;
2754
2755 rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr);
2756 if (rc) {
2757 dev_err(rdev_to_dev(rdev),
2758 "Failed to post Rx buffers to shadow QP");
2759 return -ENOMEM;
2760 }
2761
2762 swr->num_sge = 2;
2763 swr->sg_list = s_sge;
2764 swr->wr_id = tbl_idx;
2765 swr->opcode = IB_WR_SEND;
2766 swr->next = NULL;
2767
2768 udwr.ah = &rdev->sqp_ah->ib_ah;
2769 udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id;
2770 udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey;
2771
2772 /* post data received in the send queue */
2773 rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr);
2774
2775 return 0;
2776 }
2777
2778 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc,
2779 struct bnxt_qplib_cqe *cqe)
2780 {
2781 wc->opcode = IB_WC_RECV;
2782 wc->status = __rawqp1_to_ib_wc_status(cqe->status);
2783 wc->wc_flags |= IB_WC_GRH;
2784 }
2785
2786 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe,
2787 u16 *vid, u8 *sl)
2788 {
2789 bool ret = false;
2790 u32 metadata;
2791 u16 tpid;
2792
2793 metadata = orig_cqe->raweth_qp1_metadata;
2794 if (orig_cqe->raweth_qp1_flags2 &
2795 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) {
2796 tpid = ((metadata &
2797 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >>
2798 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT);
2799 if (tpid == ETH_P_8021Q) {
2800 *vid = metadata &
2801 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK;
2802 *sl = (metadata &
2803 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >>
2804 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT;
2805 ret = true;
2806 }
2807 }
2808
2809 return ret;
2810 }
2811
2812 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc,
2813 struct bnxt_qplib_cqe *cqe)
2814 {
2815 wc->opcode = IB_WC_RECV;
2816 wc->status = __rc_to_ib_wc_status(cqe->status);
2817
2818 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
2819 wc->wc_flags |= IB_WC_WITH_IMM;
2820 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
2821 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2822 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
2823 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
2824 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2825 }
2826
2827 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp,
2828 struct ib_wc *wc,
2829 struct bnxt_qplib_cqe *cqe)
2830 {
2831 struct bnxt_re_dev *rdev = qp->rdev;
2832 struct bnxt_re_qp *qp1_qp = NULL;
2833 struct bnxt_qplib_cqe *orig_cqe = NULL;
2834 struct bnxt_re_sqp_entries *sqp_entry = NULL;
2835 int nw_type;
2836 u32 tbl_idx;
2837 u16 vlan_id;
2838 u8 sl;
2839
2840 tbl_idx = cqe->wr_id;
2841
2842 sqp_entry = &rdev->sqp_tbl[tbl_idx];
2843 qp1_qp = sqp_entry->qp1_qp;
2844 orig_cqe = &sqp_entry->cqe;
2845
2846 wc->wr_id = sqp_entry->wrid;
2847 wc->byte_len = orig_cqe->length;
2848 wc->qp = &qp1_qp->ib_qp;
2849
2850 wc->ex.imm_data = orig_cqe->immdata;
2851 wc->src_qp = orig_cqe->src_qp;
2852 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN);
2853 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) {
2854 wc->vlan_id = vlan_id;
2855 wc->sl = sl;
2856 wc->wc_flags |= IB_WC_WITH_VLAN;
2857 }
2858 wc->port_num = 1;
2859 wc->vendor_err = orig_cqe->status;
2860
2861 wc->opcode = IB_WC_RECV;
2862 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status);
2863 wc->wc_flags |= IB_WC_GRH;
2864
2865 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags,
2866 orig_cqe->raweth_qp1_flags2);
2867 if (nw_type >= 0) {
2868 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type);
2869 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
2870 }
2871 }
2872
2873 static void bnxt_re_process_res_ud_wc(struct ib_wc *wc,
2874 struct bnxt_qplib_cqe *cqe)
2875 {
2876 wc->opcode = IB_WC_RECV;
2877 wc->status = __rc_to_ib_wc_status(cqe->status);
2878
2879 if (cqe->flags & CQ_RES_RC_FLAGS_IMM)
2880 wc->wc_flags |= IB_WC_WITH_IMM;
2881 if (cqe->flags & CQ_RES_RC_FLAGS_INV)
2882 wc->wc_flags |= IB_WC_WITH_INVALIDATE;
2883 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) ==
2884 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM))
2885 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
2886 }
2887
2888 static int send_phantom_wqe(struct bnxt_re_qp *qp)
2889 {
2890 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp;
2891 unsigned long flags;
2892 int rc = 0;
2893
2894 spin_lock_irqsave(&qp->sq_lock, flags);
2895
2896 rc = bnxt_re_bind_fence_mw(lib_qp);
2897 if (!rc) {
2898 lib_qp->sq.phantom_wqe_cnt++;
2899 dev_dbg(&lib_qp->sq.hwq.pdev->dev,
2900 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n",
2901 lib_qp->id, lib_qp->sq.hwq.prod,
2902 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq),
2903 lib_qp->sq.phantom_wqe_cnt);
2904 }
2905
2906 spin_unlock_irqrestore(&qp->sq_lock, flags);
2907 return rc;
2908 }
2909
2910 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc)
2911 {
2912 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
2913 struct bnxt_re_qp *qp;
2914 struct bnxt_qplib_cqe *cqe;
2915 int i, ncqe, budget;
2916 struct bnxt_qplib_q *sq;
2917 struct bnxt_qplib_qp *lib_qp;
2918 u32 tbl_idx;
2919 struct bnxt_re_sqp_entries *sqp_entry = NULL;
2920 unsigned long flags;
2921
2922 spin_lock_irqsave(&cq->cq_lock, flags);
2923 budget = min_t(u32, num_entries, cq->max_cql);
2924 num_entries = budget;
2925 if (!cq->cql) {
2926 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use");
2927 goto exit;
2928 }
2929 cqe = &cq->cql[0];
2930 while (budget) {
2931 lib_qp = NULL;
2932 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp);
2933 if (lib_qp) {
2934 sq = &lib_qp->sq;
2935 if (sq->send_phantom) {
2936 qp = container_of(lib_qp,
2937 struct bnxt_re_qp, qplib_qp);
2938 if (send_phantom_wqe(qp) == -ENOMEM)
2939 dev_err(rdev_to_dev(cq->rdev),
2940 "Phantom failed! Scheduled to send again\n");
2941 else
2942 sq->send_phantom = false;
2943 }
2944 }
2945 if (ncqe < budget)
2946 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq,
2947 cqe + ncqe,
2948 budget - ncqe);
2949
2950 if (!ncqe)
2951 break;
2952
2953 for (i = 0; i < ncqe; i++, cqe++) {
2954 /* Transcribe each qplib_wqe back to ib_wc */
2955 memset(wc, 0, sizeof(*wc));
2956
2957 wc->wr_id = cqe->wr_id;
2958 wc->byte_len = cqe->length;
2959 qp = container_of
2960 ((struct bnxt_qplib_qp *)
2961 (unsigned long)(cqe->qp_handle),
2962 struct bnxt_re_qp, qplib_qp);
2963 if (!qp) {
2964 dev_err(rdev_to_dev(cq->rdev),
2965 "POLL CQ : bad QP handle");
2966 continue;
2967 }
2968 wc->qp = &qp->ib_qp;
2969 wc->ex.imm_data = cqe->immdata;
2970 wc->src_qp = cqe->src_qp;
2971 memcpy(wc->smac, cqe->smac, ETH_ALEN);
2972 wc->port_num = 1;
2973 wc->vendor_err = cqe->status;
2974
2975 switch (cqe->opcode) {
2976 case CQ_BASE_CQE_TYPE_REQ:
2977 if (qp->qplib_qp.id ==
2978 qp->rdev->qp1_sqp->qplib_qp.id) {
2979 /* Handle this completion with
2980 * the stored completion
2981 */
2982 memset(wc, 0, sizeof(*wc));
2983 continue;
2984 }
2985 bnxt_re_process_req_wc(wc, cqe);
2986 break;
2987 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1:
2988 if (!cqe->status) {
2989 int rc = 0;
2990
2991 rc = bnxt_re_process_raw_qp_pkt_rx
2992 (qp, cqe);
2993 if (!rc) {
2994 memset(wc, 0, sizeof(*wc));
2995 continue;
2996 }
2997 cqe->status = -1;
2998 }
2999 /* Errors need not be looped back.
3000 * But change the wr_id to the one
3001 * stored in the table
3002 */
3003 tbl_idx = cqe->wr_id;
3004 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx];
3005 wc->wr_id = sqp_entry->wrid;
3006 bnxt_re_process_res_rawqp1_wc(wc, cqe);
3007 break;
3008 case CQ_BASE_CQE_TYPE_RES_RC:
3009 bnxt_re_process_res_rc_wc(wc, cqe);
3010 break;
3011 case CQ_BASE_CQE_TYPE_RES_UD:
3012 if (qp->qplib_qp.id ==
3013 qp->rdev->qp1_sqp->qplib_qp.id) {
3014 /* Handle this completion with
3015 * the stored completion
3016 */
3017 if (cqe->status) {
3018 continue;
3019 } else {
3020 bnxt_re_process_res_shadow_qp_wc
3021 (qp, wc, cqe);
3022 break;
3023 }
3024 }
3025 bnxt_re_process_res_ud_wc(wc, cqe);
3026 break;
3027 default:
3028 dev_err(rdev_to_dev(cq->rdev),
3029 "POLL CQ : type 0x%x not handled",
3030 cqe->opcode);
3031 continue;
3032 }
3033 wc++;
3034 budget--;
3035 }
3036 }
3037 exit:
3038 spin_unlock_irqrestore(&cq->cq_lock, flags);
3039 return num_entries - budget;
3040 }
3041
3042 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq,
3043 enum ib_cq_notify_flags ib_cqn_flags)
3044 {
3045 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq);
3046 int type = 0, rc = 0;
3047 unsigned long flags;
3048
3049 spin_lock_irqsave(&cq->cq_lock, flags);
3050 /* Trigger on the very next completion */
3051 if (ib_cqn_flags & IB_CQ_NEXT_COMP)
3052 type = DBR_DBR_TYPE_CQ_ARMALL;
3053 /* Trigger on the next solicited completion */
3054 else if (ib_cqn_flags & IB_CQ_SOLICITED)
3055 type = DBR_DBR_TYPE_CQ_ARMSE;
3056
3057 /* Poll to see if there are missed events */
3058 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) &&
3059 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) {
3060 rc = 1;
3061 goto exit;
3062 }
3063 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type);
3064
3065 exit:
3066 spin_unlock_irqrestore(&cq->cq_lock, flags);
3067 return rc;
3068 }
3069
3070 /* Memory Regions */
3071 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags)
3072 {
3073 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3074 struct bnxt_re_dev *rdev = pd->rdev;
3075 struct bnxt_re_mr *mr;
3076 u64 pbl = 0;
3077 int rc;
3078
3079 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3080 if (!mr)
3081 return ERR_PTR(-ENOMEM);
3082
3083 mr->rdev = rdev;
3084 mr->qplib_mr.pd = &pd->qplib_pd;
3085 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3086 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3087
3088 /* Allocate and register 0 as the address */
3089 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3090 if (rc)
3091 goto fail;
3092
3093 mr->qplib_mr.hwq.level = PBL_LVL_MAX;
3094 mr->qplib_mr.total_size = -1; /* Infinte length */
3095 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false);
3096 if (rc)
3097 goto fail_mr;
3098
3099 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3100 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ |
3101 IB_ACCESS_REMOTE_ATOMIC))
3102 mr->ib_mr.rkey = mr->ib_mr.lkey;
3103 atomic_inc(&rdev->mr_count);
3104
3105 return &mr->ib_mr;
3106
3107 fail_mr:
3108 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3109 fail:
3110 kfree(mr);
3111 return ERR_PTR(rc);
3112 }
3113
3114 int bnxt_re_dereg_mr(struct ib_mr *ib_mr)
3115 {
3116 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3117 struct bnxt_re_dev *rdev = mr->rdev;
3118 int rc;
3119
3120 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3121 if (rc) {
3122 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc);
3123 return rc;
3124 }
3125
3126 if (mr->pages) {
3127 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res,
3128 &mr->qplib_frpl);
3129 kfree(mr->pages);
3130 mr->npages = 0;
3131 mr->pages = NULL;
3132 }
3133 if (!IS_ERR_OR_NULL(mr->ib_umem))
3134 ib_umem_release(mr->ib_umem);
3135
3136 kfree(mr);
3137 atomic_dec(&rdev->mr_count);
3138 return rc;
3139 }
3140
3141 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr)
3142 {
3143 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3144
3145 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs))
3146 return -ENOMEM;
3147
3148 mr->pages[mr->npages++] = addr;
3149 return 0;
3150 }
3151
3152 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents,
3153 unsigned int *sg_offset)
3154 {
3155 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr);
3156
3157 mr->npages = 0;
3158 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page);
3159 }
3160
3161 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type,
3162 u32 max_num_sg)
3163 {
3164 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3165 struct bnxt_re_dev *rdev = pd->rdev;
3166 struct bnxt_re_mr *mr = NULL;
3167 int rc;
3168
3169 if (type != IB_MR_TYPE_MEM_REG) {
3170 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type);
3171 return ERR_PTR(-EINVAL);
3172 }
3173 if (max_num_sg > MAX_PBL_LVL_1_PGS)
3174 return ERR_PTR(-EINVAL);
3175
3176 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3177 if (!mr)
3178 return ERR_PTR(-ENOMEM);
3179
3180 mr->rdev = rdev;
3181 mr->qplib_mr.pd = &pd->qplib_pd;
3182 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR;
3183 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR;
3184
3185 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3186 if (rc)
3187 goto fail;
3188
3189 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3190 mr->ib_mr.rkey = mr->ib_mr.lkey;
3191
3192 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL);
3193 if (!mr->pages) {
3194 rc = -ENOMEM;
3195 goto fail;
3196 }
3197 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res,
3198 &mr->qplib_frpl, max_num_sg);
3199 if (rc) {
3200 dev_err(rdev_to_dev(rdev),
3201 "Failed to allocate HW FR page list");
3202 goto fail_mr;
3203 }
3204
3205 atomic_inc(&rdev->mr_count);
3206 return &mr->ib_mr;
3207
3208 fail_mr:
3209 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3210 fail:
3211 kfree(mr->pages);
3212 kfree(mr);
3213 return ERR_PTR(rc);
3214 }
3215
3216 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type,
3217 struct ib_udata *udata)
3218 {
3219 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3220 struct bnxt_re_dev *rdev = pd->rdev;
3221 struct bnxt_re_mw *mw;
3222 int rc;
3223
3224 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
3225 if (!mw)
3226 return ERR_PTR(-ENOMEM);
3227 mw->rdev = rdev;
3228 mw->qplib_mw.pd = &pd->qplib_pd;
3229
3230 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ?
3231 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 :
3232 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B);
3233 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw);
3234 if (rc) {
3235 dev_err(rdev_to_dev(rdev), "Allocate MW failed!");
3236 goto fail;
3237 }
3238 mw->ib_mw.rkey = mw->qplib_mw.rkey;
3239
3240 atomic_inc(&rdev->mw_count);
3241 return &mw->ib_mw;
3242
3243 fail:
3244 kfree(mw);
3245 return ERR_PTR(rc);
3246 }
3247
3248 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw)
3249 {
3250 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw);
3251 struct bnxt_re_dev *rdev = mw->rdev;
3252 int rc;
3253
3254 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw);
3255 if (rc) {
3256 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc);
3257 return rc;
3258 }
3259
3260 kfree(mw);
3261 atomic_dec(&rdev->mw_count);
3262 return rc;
3263 }
3264
3265 /* uverbs */
3266 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length,
3267 u64 virt_addr, int mr_access_flags,
3268 struct ib_udata *udata)
3269 {
3270 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd);
3271 struct bnxt_re_dev *rdev = pd->rdev;
3272 struct bnxt_re_mr *mr;
3273 struct ib_umem *umem;
3274 u64 *pbl_tbl, *pbl_tbl_orig;
3275 int i, umem_pgs, pages, rc;
3276 struct scatterlist *sg;
3277 int entry;
3278
3279 if (length > BNXT_RE_MAX_MR_SIZE) {
3280 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%ld\n",
3281 length, BNXT_RE_MAX_MR_SIZE);
3282 return ERR_PTR(-ENOMEM);
3283 }
3284
3285 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
3286 if (!mr)
3287 return ERR_PTR(-ENOMEM);
3288
3289 mr->rdev = rdev;
3290 mr->qplib_mr.pd = &pd->qplib_pd;
3291 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags);
3292 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR;
3293
3294 umem = ib_umem_get(ib_pd->uobject->context, start, length,
3295 mr_access_flags, 0);
3296 if (IS_ERR(umem)) {
3297 dev_err(rdev_to_dev(rdev), "Failed to get umem");
3298 rc = -EFAULT;
3299 goto free_mr;
3300 }
3301 mr->ib_umem = umem;
3302
3303 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr);
3304 if (rc) {
3305 dev_err(rdev_to_dev(rdev), "Failed to allocate MR");
3306 goto release_umem;
3307 }
3308 /* The fixed portion of the rkey is the same as the lkey */
3309 mr->ib_mr.rkey = mr->qplib_mr.rkey;
3310
3311 mr->qplib_mr.va = virt_addr;
3312 umem_pgs = ib_umem_page_count(umem);
3313 if (!umem_pgs) {
3314 dev_err(rdev_to_dev(rdev), "umem is invalid!");
3315 rc = -EINVAL;
3316 goto free_mrw;
3317 }
3318 mr->qplib_mr.total_size = length;
3319
3320 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL);
3321 if (!pbl_tbl) {
3322 rc = -EINVAL;
3323 goto free_mrw;
3324 }
3325 pbl_tbl_orig = pbl_tbl;
3326
3327 if (umem->hugetlb) {
3328 dev_err(rdev_to_dev(rdev), "umem hugetlb not supported!");
3329 rc = -EFAULT;
3330 goto fail;
3331 }
3332
3333 if (umem->page_shift != PAGE_SHIFT) {
3334 dev_err(rdev_to_dev(rdev), "umem page shift unsupported!");
3335 rc = -EFAULT;
3336 goto fail;
3337 }
3338 /* Map umem buf ptrs to the PBL */
3339 for_each_sg(umem->sg_head.sgl, sg, umem->nmap, entry) {
3340 pages = sg_dma_len(sg) >> umem->page_shift;
3341 for (i = 0; i < pages; i++, pbl_tbl++)
3342 *pbl_tbl = sg_dma_address(sg) + (i << umem->page_shift);
3343 }
3344 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl_orig,
3345 umem_pgs, false);
3346 if (rc) {
3347 dev_err(rdev_to_dev(rdev), "Failed to register user MR");
3348 goto fail;
3349 }
3350
3351 kfree(pbl_tbl_orig);
3352
3353 mr->ib_mr.lkey = mr->qplib_mr.lkey;
3354 mr->ib_mr.rkey = mr->qplib_mr.lkey;
3355 atomic_inc(&rdev->mr_count);
3356
3357 return &mr->ib_mr;
3358 fail:
3359 kfree(pbl_tbl_orig);
3360 free_mrw:
3361 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr);
3362 release_umem:
3363 ib_umem_release(umem);
3364 free_mr:
3365 kfree(mr);
3366 return ERR_PTR(rc);
3367 }
3368
3369 struct ib_ucontext *bnxt_re_alloc_ucontext(struct ib_device *ibdev,
3370 struct ib_udata *udata)
3371 {
3372 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev);
3373 struct bnxt_re_uctx_resp resp;
3374 struct bnxt_re_ucontext *uctx;
3375 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr;
3376 int rc;
3377
3378 dev_dbg(rdev_to_dev(rdev), "ABI version requested %d",
3379 ibdev->uverbs_abi_ver);
3380
3381 if (ibdev->uverbs_abi_ver != BNXT_RE_ABI_VERSION) {
3382 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ",
3383 BNXT_RE_ABI_VERSION);
3384 return ERR_PTR(-EPERM);
3385 }
3386
3387 uctx = kzalloc(sizeof(*uctx), GFP_KERNEL);
3388 if (!uctx)
3389 return ERR_PTR(-ENOMEM);
3390
3391 uctx->rdev = rdev;
3392
3393 uctx->shpg = (void *)__get_free_page(GFP_KERNEL);
3394 if (!uctx->shpg) {
3395 rc = -ENOMEM;
3396 goto fail;
3397 }
3398 spin_lock_init(&uctx->sh_lock);
3399
3400 resp.dev_id = rdev->en_dev->pdev->devfn; /*Temp, Use idr_alloc instead*/
3401 resp.max_qp = rdev->qplib_ctx.qpc_count;
3402 resp.pg_size = PAGE_SIZE;
3403 resp.cqe_sz = sizeof(struct cq_base);
3404 resp.max_cqd = dev_attr->max_cq_wqes;
3405 resp.rsvd = 0;
3406
3407 rc = ib_copy_to_udata(udata, &resp, sizeof(resp));
3408 if (rc) {
3409 dev_err(rdev_to_dev(rdev), "Failed to copy user context");
3410 rc = -EFAULT;
3411 goto cfail;
3412 }
3413
3414 return &uctx->ib_uctx;
3415 cfail:
3416 free_page((unsigned long)uctx->shpg);
3417 uctx->shpg = NULL;
3418 fail:
3419 kfree(uctx);
3420 return ERR_PTR(rc);
3421 }
3422
3423 int bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx)
3424 {
3425 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3426 struct bnxt_re_ucontext,
3427 ib_uctx);
3428
3429 struct bnxt_re_dev *rdev = uctx->rdev;
3430 int rc = 0;
3431
3432 if (uctx->shpg)
3433 free_page((unsigned long)uctx->shpg);
3434
3435 if (uctx->dpi.dbr) {
3436 /* Free DPI only if this is the first PD allocated by the
3437 * application and mark the context dpi as NULL
3438 */
3439 rc = bnxt_qplib_dealloc_dpi(&rdev->qplib_res,
3440 &rdev->qplib_res.dpi_tbl,
3441 &uctx->dpi);
3442 if (rc)
3443 dev_err(rdev_to_dev(rdev), "Deallocate HW DPI failed!");
3444 /* Don't fail, continue*/
3445 uctx->dpi.dbr = NULL;
3446 }
3447
3448 kfree(uctx);
3449 return 0;
3450 }
3451
3452 /* Helper function to mmap the virtual memory from user app */
3453 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma)
3454 {
3455 struct bnxt_re_ucontext *uctx = container_of(ib_uctx,
3456 struct bnxt_re_ucontext,
3457 ib_uctx);
3458 struct bnxt_re_dev *rdev = uctx->rdev;
3459 u64 pfn;
3460
3461 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3462 return -EINVAL;
3463
3464 if (vma->vm_pgoff) {
3465 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3466 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
3467 PAGE_SIZE, vma->vm_page_prot)) {
3468 dev_err(rdev_to_dev(rdev), "Failed to map DPI");
3469 return -EAGAIN;
3470 }
3471 } else {
3472 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT;
3473 if (remap_pfn_range(vma, vma->vm_start,
3474 pfn, PAGE_SIZE, vma->vm_page_prot)) {
3475 dev_err(rdev_to_dev(rdev),
3476 "Failed to map shared page");
3477 return -EAGAIN;
3478 }
3479 }
3480
3481 return 0;
3482 }
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