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Merge branch 'for-4.15-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / cxgb4 / t4.h
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31 #ifndef __T4_H__
32 #define __T4_H__
33
34 #include "t4_hw.h"
35 #include "t4_regs.h"
36 #include "t4_values.h"
37 #include "t4_msg.h"
38 #include "t4fw_ri_api.h"
39
40 #define T4_MAX_NUM_PD 65536
41 #define T4_MAX_MR_SIZE (~0ULL)
42 #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */
43 #define T4_STAG_UNSET 0xffffffff
44 #define T4_FW_MAJ 0
45 #define PCIE_MA_SYNC_A 0x30b4
46
47 struct t4_status_page {
48 __be32 rsvd1; /* flit 0 - hw owns */
49 __be16 rsvd2;
50 __be16 qid;
51 __be16 cidx;
52 __be16 pidx;
53 u8 qp_err; /* flit 1 - sw owns */
54 u8 db_off;
55 u8 pad;
56 u16 host_wq_pidx;
57 u16 host_cidx;
58 u16 host_pidx;
59 };
60
61 #define T4_EQ_ENTRY_SIZE 64
62
63 #define T4_SQ_NUM_SLOTS 5
64 #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
65 #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
66 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
67 #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \
68 sizeof(struct fw_ri_immd)))
69 #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \
70 sizeof(struct fw_ri_rdma_write_wr) - \
71 sizeof(struct fw_ri_immd)))
72 #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \
73 sizeof(struct fw_ri_rdma_write_wr) - \
74 sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge))
75 #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \
76 sizeof(struct fw_ri_immd)) & ~31UL)
77 #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
78 #define T4_MAX_FR_DSGL 1024
79 #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
80
81 static inline int t4_max_fr_depth(int use_dsgl)
82 {
83 return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
84 }
85
86 #define T4_RQ_NUM_SLOTS 2
87 #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
88 #define T4_MAX_RECV_SGE 4
89
90 union t4_wr {
91 struct fw_ri_res_wr res;
92 struct fw_ri_wr ri;
93 struct fw_ri_rdma_write_wr write;
94 struct fw_ri_send_wr send;
95 struct fw_ri_rdma_read_wr read;
96 struct fw_ri_bind_mw_wr bind;
97 struct fw_ri_fr_nsmr_wr fr;
98 struct fw_ri_fr_nsmr_tpte_wr fr_tpte;
99 struct fw_ri_inv_lstag_wr inv;
100 struct t4_status_page status;
101 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
102 };
103
104 union t4_recv_wr {
105 struct fw_ri_recv_wr recv;
106 struct t4_status_page status;
107 __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
108 };
109
110 static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
111 enum fw_wr_opcodes opcode, u8 flags, u8 len16)
112 {
113 wqe->send.opcode = (u8)opcode;
114 wqe->send.flags = flags;
115 wqe->send.wrid = wrid;
116 wqe->send.r1[0] = 0;
117 wqe->send.r1[1] = 0;
118 wqe->send.r1[2] = 0;
119 wqe->send.len16 = len16;
120 }
121
122 /* CQE/AE status codes */
123 #define T4_ERR_SUCCESS 0x0
124 #define T4_ERR_STAG 0x1 /* STAG invalid: either the */
125 /* STAG is offlimt, being 0, */
126 /* or STAG_key mismatch */
127 #define T4_ERR_PDID 0x2 /* PDID mismatch */
128 #define T4_ERR_QPID 0x3 /* QPID mismatch */
129 #define T4_ERR_ACCESS 0x4 /* Invalid access right */
130 #define T4_ERR_WRAP 0x5 /* Wrap error */
131 #define T4_ERR_BOUND 0x6 /* base and bounds voilation */
132 #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */
133 /* shared memory region */
134 #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */
135 /* shared memory region */
136 #define T4_ERR_ECC 0x9 /* ECC error detected */
137 #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */
138 /* reading PSTAG for a MW */
139 /* Invalidate */
140 #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */
141 /* software error */
142 #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */
143 #define T4_ERR_CRC 0x10 /* CRC error */
144 #define T4_ERR_MARKER 0x11 /* Marker error */
145 #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */
146 #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */
147 #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */
148 #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */
149 #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */
150 #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */
151 #define T4_ERR_MSN 0x18 /* MSN error */
152 #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */
153 #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */
154 /* or READ_REQ */
155 #define T4_ERR_MSN_GAP 0x1B
156 #define T4_ERR_MSN_RANGE 0x1C
157 #define T4_ERR_IRD_OVERFLOW 0x1D
158 #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */
159 /* software error */
160 #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */
161 /* mismatch) */
162 /*
163 * CQE defs
164 */
165 struct t4_cqe {
166 __be32 header;
167 __be32 len;
168 union {
169 struct {
170 __be32 stag;
171 __be32 msn;
172 } rcqe;
173 struct {
174 __be32 stag;
175 u16 nada2;
176 u16 cidx;
177 } scqe;
178 struct {
179 __be32 wrid_hi;
180 __be32 wrid_low;
181 } gen;
182 u64 drain_cookie;
183 } u;
184 __be64 reserved;
185 __be64 bits_type_ts;
186 };
187
188 /* macros for flit 0 of the cqe */
189
190 #define CQE_QPID_S 12
191 #define CQE_QPID_M 0xFFFFF
192 #define CQE_QPID_G(x) ((((x) >> CQE_QPID_S)) & CQE_QPID_M)
193 #define CQE_QPID_V(x) ((x)<<CQE_QPID_S)
194
195 #define CQE_SWCQE_S 11
196 #define CQE_SWCQE_M 0x1
197 #define CQE_SWCQE_G(x) ((((x) >> CQE_SWCQE_S)) & CQE_SWCQE_M)
198 #define CQE_SWCQE_V(x) ((x)<<CQE_SWCQE_S)
199
200 #define CQE_DRAIN_S 10
201 #define CQE_DRAIN_M 0x1
202 #define CQE_DRAIN_G(x) ((((x) >> CQE_DRAIN_S)) & CQE_DRAIN_M)
203 #define CQE_DRAIN_V(x) ((x)<<CQE_DRAIN_S)
204
205 #define CQE_STATUS_S 5
206 #define CQE_STATUS_M 0x1F
207 #define CQE_STATUS_G(x) ((((x) >> CQE_STATUS_S)) & CQE_STATUS_M)
208 #define CQE_STATUS_V(x) ((x)<<CQE_STATUS_S)
209
210 #define CQE_TYPE_S 4
211 #define CQE_TYPE_M 0x1
212 #define CQE_TYPE_G(x) ((((x) >> CQE_TYPE_S)) & CQE_TYPE_M)
213 #define CQE_TYPE_V(x) ((x)<<CQE_TYPE_S)
214
215 #define CQE_OPCODE_S 0
216 #define CQE_OPCODE_M 0xF
217 #define CQE_OPCODE_G(x) ((((x) >> CQE_OPCODE_S)) & CQE_OPCODE_M)
218 #define CQE_OPCODE_V(x) ((x)<<CQE_OPCODE_S)
219
220 #define SW_CQE(x) (CQE_SWCQE_G(be32_to_cpu((x)->header)))
221 #define DRAIN_CQE(x) (CQE_DRAIN_G(be32_to_cpu((x)->header)))
222 #define CQE_QPID(x) (CQE_QPID_G(be32_to_cpu((x)->header)))
223 #define CQE_TYPE(x) (CQE_TYPE_G(be32_to_cpu((x)->header)))
224 #define SQ_TYPE(x) (CQE_TYPE((x)))
225 #define RQ_TYPE(x) (!CQE_TYPE((x)))
226 #define CQE_STATUS(x) (CQE_STATUS_G(be32_to_cpu((x)->header)))
227 #define CQE_OPCODE(x) (CQE_OPCODE_G(be32_to_cpu((x)->header)))
228
229 #define CQE_SEND_OPCODE(x)( \
230 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
231 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
232 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
233 (CQE_OPCODE_G(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
234
235 #define CQE_LEN(x) (be32_to_cpu((x)->len))
236
237 /* used for RQ completion processing */
238 #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag))
239 #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn))
240
241 /* used for SQ completion processing */
242 #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx)
243 #define CQE_WRID_FR_STAG(x) (be32_to_cpu((x)->u.scqe.stag))
244
245 /* generic accessor macros */
246 #define CQE_WRID_HI(x) (be32_to_cpu((x)->u.gen.wrid_hi))
247 #define CQE_WRID_LOW(x) (be32_to_cpu((x)->u.gen.wrid_low))
248 #define CQE_DRAIN_COOKIE(x) ((x)->u.drain_cookie)
249
250 /* macros for flit 3 of the cqe */
251 #define CQE_GENBIT_S 63
252 #define CQE_GENBIT_M 0x1
253 #define CQE_GENBIT_G(x) (((x) >> CQE_GENBIT_S) & CQE_GENBIT_M)
254 #define CQE_GENBIT_V(x) ((x)<<CQE_GENBIT_S)
255
256 #define CQE_OVFBIT_S 62
257 #define CQE_OVFBIT_M 0x1
258 #define CQE_OVFBIT_G(x) ((((x) >> CQE_OVFBIT_S)) & CQE_OVFBIT_M)
259
260 #define CQE_IQTYPE_S 60
261 #define CQE_IQTYPE_M 0x3
262 #define CQE_IQTYPE_G(x) ((((x) >> CQE_IQTYPE_S)) & CQE_IQTYPE_M)
263
264 #define CQE_TS_M 0x0fffffffffffffffULL
265 #define CQE_TS_G(x) ((x) & CQE_TS_M)
266
267 #define CQE_OVFBIT(x) ((unsigned)CQE_OVFBIT_G(be64_to_cpu((x)->bits_type_ts)))
268 #define CQE_GENBIT(x) ((unsigned)CQE_GENBIT_G(be64_to_cpu((x)->bits_type_ts)))
269 #define CQE_TS(x) (CQE_TS_G(be64_to_cpu((x)->bits_type_ts)))
270
271 struct t4_swsqe {
272 u64 wr_id;
273 struct t4_cqe cqe;
274 int read_len;
275 int opcode;
276 int complete;
277 int signaled;
278 u16 idx;
279 int flushed;
280 struct timespec host_ts;
281 u64 sge_ts;
282 };
283
284 static inline pgprot_t t4_pgprot_wc(pgprot_t prot)
285 {
286 #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64)
287 return pgprot_writecombine(prot);
288 #else
289 return pgprot_noncached(prot);
290 #endif
291 }
292
293 enum {
294 T4_SQ_ONCHIP = (1<<0),
295 };
296
297 struct t4_sq {
298 union t4_wr *queue;
299 dma_addr_t dma_addr;
300 DEFINE_DMA_UNMAP_ADDR(mapping);
301 unsigned long phys_addr;
302 struct t4_swsqe *sw_sq;
303 struct t4_swsqe *oldest_read;
304 void __iomem *bar2_va;
305 u64 bar2_pa;
306 size_t memsize;
307 u32 bar2_qid;
308 u32 qid;
309 u16 in_use;
310 u16 size;
311 u16 cidx;
312 u16 pidx;
313 u16 wq_pidx;
314 u16 wq_pidx_inc;
315 u16 flags;
316 short flush_cidx;
317 };
318
319 struct t4_swrqe {
320 u64 wr_id;
321 struct timespec host_ts;
322 u64 sge_ts;
323 };
324
325 struct t4_rq {
326 union t4_recv_wr *queue;
327 dma_addr_t dma_addr;
328 DEFINE_DMA_UNMAP_ADDR(mapping);
329 struct t4_swrqe *sw_rq;
330 void __iomem *bar2_va;
331 u64 bar2_pa;
332 size_t memsize;
333 u32 bar2_qid;
334 u32 qid;
335 u32 msn;
336 u32 rqt_hwaddr;
337 u16 rqt_size;
338 u16 in_use;
339 u16 size;
340 u16 cidx;
341 u16 pidx;
342 u16 wq_pidx;
343 u16 wq_pidx_inc;
344 };
345
346 struct t4_wq {
347 struct t4_sq sq;
348 struct t4_rq rq;
349 void __iomem *db;
350 struct c4iw_rdev *rdev;
351 int flushed;
352 };
353
354 static inline int t4_rqes_posted(struct t4_wq *wq)
355 {
356 return wq->rq.in_use;
357 }
358
359 static inline int t4_rq_empty(struct t4_wq *wq)
360 {
361 return wq->rq.in_use == 0;
362 }
363
364 static inline int t4_rq_full(struct t4_wq *wq)
365 {
366 return wq->rq.in_use == (wq->rq.size - 1);
367 }
368
369 static inline u32 t4_rq_avail(struct t4_wq *wq)
370 {
371 return wq->rq.size - 1 - wq->rq.in_use;
372 }
373
374 static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
375 {
376 wq->rq.in_use++;
377 if (++wq->rq.pidx == wq->rq.size)
378 wq->rq.pidx = 0;
379 wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
380 if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
381 wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
382 }
383
384 static inline void t4_rq_consume(struct t4_wq *wq)
385 {
386 wq->rq.in_use--;
387 wq->rq.msn++;
388 if (++wq->rq.cidx == wq->rq.size)
389 wq->rq.cidx = 0;
390 }
391
392 static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq)
393 {
394 return wq->rq.queue[wq->rq.size].status.host_wq_pidx;
395 }
396
397 static inline u16 t4_rq_wq_size(struct t4_wq *wq)
398 {
399 return wq->rq.size * T4_RQ_NUM_SLOTS;
400 }
401
402 static inline int t4_sq_onchip(struct t4_sq *sq)
403 {
404 return sq->flags & T4_SQ_ONCHIP;
405 }
406
407 static inline int t4_sq_empty(struct t4_wq *wq)
408 {
409 return wq->sq.in_use == 0;
410 }
411
412 static inline int t4_sq_full(struct t4_wq *wq)
413 {
414 return wq->sq.in_use == (wq->sq.size - 1);
415 }
416
417 static inline u32 t4_sq_avail(struct t4_wq *wq)
418 {
419 return wq->sq.size - 1 - wq->sq.in_use;
420 }
421
422 static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
423 {
424 wq->sq.in_use++;
425 if (++wq->sq.pidx == wq->sq.size)
426 wq->sq.pidx = 0;
427 wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
428 if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
429 wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
430 }
431
432 static inline void t4_sq_consume(struct t4_wq *wq)
433 {
434 if (wq->sq.cidx == wq->sq.flush_cidx)
435 wq->sq.flush_cidx = -1;
436 wq->sq.in_use--;
437 if (++wq->sq.cidx == wq->sq.size)
438 wq->sq.cidx = 0;
439 }
440
441 static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq)
442 {
443 return wq->sq.queue[wq->sq.size].status.host_wq_pidx;
444 }
445
446 static inline u16 t4_sq_wq_size(struct t4_wq *wq)
447 {
448 return wq->sq.size * T4_SQ_NUM_SLOTS;
449 }
450
451 /* This function copies 64 byte coalesced work request to memory
452 * mapped BAR2 space. For coalesced WRs, the SGE fetches data
453 * from the FIFO instead of from Host.
454 */
455 static inline void pio_copy(u64 __iomem *dst, u64 *src)
456 {
457 int count = 8;
458
459 while (count) {
460 writeq(*src, dst);
461 src++;
462 dst++;
463 count--;
464 }
465 }
466
467 static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, union t4_wr *wqe)
468 {
469
470 /* Flush host queue memory writes. */
471 wmb();
472 if (wq->sq.bar2_va) {
473 if (inc == 1 && wq->sq.bar2_qid == 0 && wqe) {
474 pr_debug("WC wq->sq.pidx = %d\n", wq->sq.pidx);
475 pio_copy((u64 __iomem *)
476 (wq->sq.bar2_va + SGE_UDB_WCDOORBELL),
477 (u64 *)wqe);
478 } else {
479 pr_debug("DB wq->sq.pidx = %d\n", wq->sq.pidx);
480 writel(PIDX_T5_V(inc) | QID_V(wq->sq.bar2_qid),
481 wq->sq.bar2_va + SGE_UDB_KDOORBELL);
482 }
483
484 /* Flush user doorbell area writes. */
485 wmb();
486 return;
487 }
488 writel(QID_V(wq->sq.qid) | PIDX_V(inc), wq->db);
489 }
490
491 static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc,
492 union t4_recv_wr *wqe)
493 {
494
495 /* Flush host queue memory writes. */
496 wmb();
497 if (wq->rq.bar2_va) {
498 if (inc == 1 && wq->rq.bar2_qid == 0 && wqe) {
499 pr_debug("WC wq->rq.pidx = %d\n", wq->rq.pidx);
500 pio_copy((u64 __iomem *)
501 (wq->rq.bar2_va + SGE_UDB_WCDOORBELL),
502 (void *)wqe);
503 } else {
504 pr_debug("DB wq->rq.pidx = %d\n", wq->rq.pidx);
505 writel(PIDX_T5_V(inc) | QID_V(wq->rq.bar2_qid),
506 wq->rq.bar2_va + SGE_UDB_KDOORBELL);
507 }
508
509 /* Flush user doorbell area writes. */
510 wmb();
511 return;
512 }
513 writel(QID_V(wq->rq.qid) | PIDX_V(inc), wq->db);
514 }
515
516 static inline int t4_wq_in_error(struct t4_wq *wq)
517 {
518 return wq->rq.queue[wq->rq.size].status.qp_err;
519 }
520
521 static inline void t4_set_wq_in_error(struct t4_wq *wq)
522 {
523 wq->rq.queue[wq->rq.size].status.qp_err = 1;
524 }
525
526 static inline void t4_disable_wq_db(struct t4_wq *wq)
527 {
528 wq->rq.queue[wq->rq.size].status.db_off = 1;
529 }
530
531 static inline void t4_enable_wq_db(struct t4_wq *wq)
532 {
533 wq->rq.queue[wq->rq.size].status.db_off = 0;
534 }
535
536 static inline int t4_wq_db_enabled(struct t4_wq *wq)
537 {
538 return !wq->rq.queue[wq->rq.size].status.db_off;
539 }
540
541 enum t4_cq_flags {
542 CQ_ARMED = 1,
543 };
544
545 struct t4_cq {
546 struct t4_cqe *queue;
547 dma_addr_t dma_addr;
548 DEFINE_DMA_UNMAP_ADDR(mapping);
549 struct t4_cqe *sw_queue;
550 void __iomem *gts;
551 void __iomem *bar2_va;
552 u64 bar2_pa;
553 u32 bar2_qid;
554 struct c4iw_rdev *rdev;
555 size_t memsize;
556 __be64 bits_type_ts;
557 u32 cqid;
558 u32 qid_mask;
559 int vector;
560 u16 size; /* including status page */
561 u16 cidx;
562 u16 sw_pidx;
563 u16 sw_cidx;
564 u16 sw_in_use;
565 u16 cidx_inc;
566 u8 gen;
567 u8 error;
568 unsigned long flags;
569 };
570
571 static inline void write_gts(struct t4_cq *cq, u32 val)
572 {
573 if (cq->bar2_va)
574 writel(val | INGRESSQID_V(cq->bar2_qid),
575 cq->bar2_va + SGE_UDB_GTS);
576 else
577 writel(val | INGRESSQID_V(cq->cqid), cq->gts);
578 }
579
580 static inline int t4_clear_cq_armed(struct t4_cq *cq)
581 {
582 return test_and_clear_bit(CQ_ARMED, &cq->flags);
583 }
584
585 static inline int t4_arm_cq(struct t4_cq *cq, int se)
586 {
587 u32 val;
588
589 set_bit(CQ_ARMED, &cq->flags);
590 while (cq->cidx_inc > CIDXINC_M) {
591 val = SEINTARM_V(0) | CIDXINC_V(CIDXINC_M) | TIMERREG_V(7);
592 write_gts(cq, val);
593 cq->cidx_inc -= CIDXINC_M;
594 }
595 val = SEINTARM_V(se) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(6);
596 write_gts(cq, val);
597 cq->cidx_inc = 0;
598 return 0;
599 }
600
601 static inline void t4_swcq_produce(struct t4_cq *cq)
602 {
603 cq->sw_in_use++;
604 if (cq->sw_in_use == cq->size) {
605 pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
606 __func__, cq->cqid);
607 cq->error = 1;
608 cq->sw_in_use--;
609 return;
610 }
611 if (++cq->sw_pidx == cq->size)
612 cq->sw_pidx = 0;
613 }
614
615 static inline void t4_swcq_consume(struct t4_cq *cq)
616 {
617 cq->sw_in_use--;
618 if (++cq->sw_cidx == cq->size)
619 cq->sw_cidx = 0;
620 }
621
622 static inline void t4_hwcq_consume(struct t4_cq *cq)
623 {
624 cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
625 if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_M) {
626 u32 val;
627
628 val = SEINTARM_V(0) | CIDXINC_V(cq->cidx_inc) | TIMERREG_V(7);
629 write_gts(cq, val);
630 cq->cidx_inc = 0;
631 }
632 if (++cq->cidx == cq->size) {
633 cq->cidx = 0;
634 cq->gen ^= 1;
635 }
636 }
637
638 static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
639 {
640 return (CQE_GENBIT(cqe) == cq->gen);
641 }
642
643 static inline int t4_cq_notempty(struct t4_cq *cq)
644 {
645 return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]);
646 }
647
648 static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
649 {
650 int ret;
651 u16 prev_cidx;
652
653 if (cq->cidx == 0)
654 prev_cidx = cq->size - 1;
655 else
656 prev_cidx = cq->cidx - 1;
657
658 if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
659 ret = -EOVERFLOW;
660 cq->error = 1;
661 pr_err("cq overflow cqid %u\n", cq->cqid);
662 } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
663
664 /* Ensure CQE is flushed to memory */
665 rmb();
666 *cqe = &cq->queue[cq->cidx];
667 ret = 0;
668 } else
669 ret = -ENODATA;
670 return ret;
671 }
672
673 static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
674 {
675 if (cq->sw_in_use == cq->size) {
676 pr_warn("%s cxgb4 sw cq overflow cqid %u\n",
677 __func__, cq->cqid);
678 cq->error = 1;
679 return NULL;
680 }
681 if (cq->sw_in_use)
682 return &cq->sw_queue[cq->sw_cidx];
683 return NULL;
684 }
685
686 static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
687 {
688 int ret = 0;
689
690 if (cq->error)
691 ret = -ENODATA;
692 else if (cq->sw_in_use)
693 *cqe = &cq->sw_queue[cq->sw_cidx];
694 else
695 ret = t4_next_hw_cqe(cq, cqe);
696 return ret;
697 }
698
699 static inline int t4_cq_in_error(struct t4_cq *cq)
700 {
701 return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
702 }
703
704 static inline void t4_set_cq_in_error(struct t4_cq *cq)
705 {
706 ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
707 }
708 #endif
709
710 struct t4_dev_status_page {
711 u8 db_off;
712 u8 pad1;
713 u16 pad2;
714 u32 pad3;
715 u64 qp_start;
716 u64 qp_size;
717 u64 cq_start;
718 u64 cq_size;
719 };
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