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[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / mlx4 / main.c
1 /*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38 #include <linux/netdevice.h>
39 #include <linux/inetdevice.h>
40 #include <linux/rtnetlink.h>
41 #include <linux/if_vlan.h>
42 #include <linux/sched/mm.h>
43
44 #include <net/ipv6.h>
45 #include <net/addrconf.h>
46 #include <net/devlink.h>
47
48 #include <rdma/ib_smi.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <rdma/ib_addr.h>
51 #include <rdma/ib_cache.h>
52
53 #include <net/bonding.h>
54
55 #include <linux/mlx4/driver.h>
56 #include <linux/mlx4/cmd.h>
57 #include <linux/mlx4/qp.h>
58
59 #include "mlx4_ib.h"
60 #include <rdma/mlx4-abi.h>
61
62 #define DRV_NAME MLX4_IB_DRV_NAME
63 #define DRV_VERSION "2.2-1"
64 #define DRV_RELDATE "Feb 2014"
65
66 #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
67 #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
68 #define MLX4_IB_CARD_REV_A0 0xA0
69
70 MODULE_AUTHOR("Roland Dreier");
71 MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
72 MODULE_LICENSE("Dual BSD/GPL");
73 MODULE_VERSION(DRV_VERSION);
74
75 int mlx4_ib_sm_guid_assign = 0;
76 module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
77 MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
78
79 static const char mlx4_ib_version[] =
80 DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
81 DRV_VERSION " (" DRV_RELDATE ")\n";
82
83 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
84
85 static struct workqueue_struct *wq;
86
87 static void init_query_mad(struct ib_smp *mad)
88 {
89 mad->base_version = 1;
90 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
91 mad->class_version = 1;
92 mad->method = IB_MGMT_METHOD_GET;
93 }
94
95 static int check_flow_steering_support(struct mlx4_dev *dev)
96 {
97 int eth_num_ports = 0;
98 int ib_num_ports = 0;
99
100 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
101
102 if (dmfs) {
103 int i;
104 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
105 eth_num_ports++;
106 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
107 ib_num_ports++;
108 dmfs &= (!ib_num_ports ||
109 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
110 (!eth_num_ports ||
111 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
112 if (ib_num_ports && mlx4_is_mfunc(dev)) {
113 pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
114 dmfs = 0;
115 }
116 }
117 return dmfs;
118 }
119
120 static int num_ib_ports(struct mlx4_dev *dev)
121 {
122 int ib_ports = 0;
123 int i;
124
125 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
126 ib_ports++;
127
128 return ib_ports;
129 }
130
131 static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
132 {
133 struct mlx4_ib_dev *ibdev = to_mdev(device);
134 struct net_device *dev;
135
136 rcu_read_lock();
137 dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
138
139 if (dev) {
140 if (mlx4_is_bonded(ibdev->dev)) {
141 struct net_device *upper = NULL;
142
143 upper = netdev_master_upper_dev_get_rcu(dev);
144 if (upper) {
145 struct net_device *active;
146
147 active = bond_option_active_slave_get_rcu(netdev_priv(upper));
148 if (active)
149 dev = active;
150 }
151 }
152 }
153 if (dev)
154 dev_hold(dev);
155
156 rcu_read_unlock();
157 return dev;
158 }
159
160 static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
161 struct mlx4_ib_dev *ibdev,
162 u8 port_num)
163 {
164 struct mlx4_cmd_mailbox *mailbox;
165 int err;
166 struct mlx4_dev *dev = ibdev->dev;
167 int i;
168 union ib_gid *gid_tbl;
169
170 mailbox = mlx4_alloc_cmd_mailbox(dev);
171 if (IS_ERR(mailbox))
172 return -ENOMEM;
173
174 gid_tbl = mailbox->buf;
175
176 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
177 memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
178
179 err = mlx4_cmd(dev, mailbox->dma,
180 MLX4_SET_PORT_GID_TABLE << 8 | port_num,
181 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
182 MLX4_CMD_WRAPPED);
183 if (mlx4_is_bonded(dev))
184 err += mlx4_cmd(dev, mailbox->dma,
185 MLX4_SET_PORT_GID_TABLE << 8 | 2,
186 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
187 MLX4_CMD_WRAPPED);
188
189 mlx4_free_cmd_mailbox(dev, mailbox);
190 return err;
191 }
192
193 static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
194 struct mlx4_ib_dev *ibdev,
195 u8 port_num)
196 {
197 struct mlx4_cmd_mailbox *mailbox;
198 int err;
199 struct mlx4_dev *dev = ibdev->dev;
200 int i;
201 struct {
202 union ib_gid gid;
203 __be32 rsrvd1[2];
204 __be16 rsrvd2;
205 u8 type;
206 u8 version;
207 __be32 rsrvd3;
208 } *gid_tbl;
209
210 mailbox = mlx4_alloc_cmd_mailbox(dev);
211 if (IS_ERR(mailbox))
212 return -ENOMEM;
213
214 gid_tbl = mailbox->buf;
215 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
216 memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
217 if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
218 gid_tbl[i].version = 2;
219 if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
220 gid_tbl[i].type = 1;
221 else
222 memset(&gid_tbl[i].gid, 0, 12);
223 }
224 }
225
226 err = mlx4_cmd(dev, mailbox->dma,
227 MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
228 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
229 MLX4_CMD_WRAPPED);
230 if (mlx4_is_bonded(dev))
231 err += mlx4_cmd(dev, mailbox->dma,
232 MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
233 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
234 MLX4_CMD_WRAPPED);
235
236 mlx4_free_cmd_mailbox(dev, mailbox);
237 return err;
238 }
239
240 static int mlx4_ib_update_gids(struct gid_entry *gids,
241 struct mlx4_ib_dev *ibdev,
242 u8 port_num)
243 {
244 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
245 return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
246
247 return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
248 }
249
250 static int mlx4_ib_add_gid(struct ib_device *device,
251 u8 port_num,
252 unsigned int index,
253 const union ib_gid *gid,
254 const struct ib_gid_attr *attr,
255 void **context)
256 {
257 struct mlx4_ib_dev *ibdev = to_mdev(device);
258 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
259 struct mlx4_port_gid_table *port_gid_table;
260 int free = -1, found = -1;
261 int ret = 0;
262 int hw_update = 0;
263 int i;
264 struct gid_entry *gids = NULL;
265
266 if (!rdma_cap_roce_gid_table(device, port_num))
267 return -EINVAL;
268
269 if (port_num > MLX4_MAX_PORTS)
270 return -EINVAL;
271
272 if (!context)
273 return -EINVAL;
274
275 port_gid_table = &iboe->gids[port_num - 1];
276 spin_lock_bh(&iboe->lock);
277 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
278 if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid)) &&
279 (port_gid_table->gids[i].gid_type == attr->gid_type)) {
280 found = i;
281 break;
282 }
283 if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
284 free = i; /* HW has space */
285 }
286
287 if (found < 0) {
288 if (free < 0) {
289 ret = -ENOSPC;
290 } else {
291 port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
292 if (!port_gid_table->gids[free].ctx) {
293 ret = -ENOMEM;
294 } else {
295 *context = port_gid_table->gids[free].ctx;
296 memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
297 port_gid_table->gids[free].gid_type = attr->gid_type;
298 port_gid_table->gids[free].ctx->real_index = free;
299 port_gid_table->gids[free].ctx->refcount = 1;
300 hw_update = 1;
301 }
302 }
303 } else {
304 struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
305 *context = ctx;
306 ctx->refcount++;
307 }
308 if (!ret && hw_update) {
309 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
310 if (!gids) {
311 ret = -ENOMEM;
312 } else {
313 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
314 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
315 gids[i].gid_type = port_gid_table->gids[i].gid_type;
316 }
317 }
318 }
319 spin_unlock_bh(&iboe->lock);
320
321 if (!ret && hw_update) {
322 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
323 kfree(gids);
324 }
325
326 return ret;
327 }
328
329 static int mlx4_ib_del_gid(struct ib_device *device,
330 u8 port_num,
331 unsigned int index,
332 void **context)
333 {
334 struct gid_cache_context *ctx = *context;
335 struct mlx4_ib_dev *ibdev = to_mdev(device);
336 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
337 struct mlx4_port_gid_table *port_gid_table;
338 int ret = 0;
339 int hw_update = 0;
340 struct gid_entry *gids = NULL;
341
342 if (!rdma_cap_roce_gid_table(device, port_num))
343 return -EINVAL;
344
345 if (port_num > MLX4_MAX_PORTS)
346 return -EINVAL;
347
348 port_gid_table = &iboe->gids[port_num - 1];
349 spin_lock_bh(&iboe->lock);
350 if (ctx) {
351 ctx->refcount--;
352 if (!ctx->refcount) {
353 unsigned int real_index = ctx->real_index;
354
355 memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
356 kfree(port_gid_table->gids[real_index].ctx);
357 port_gid_table->gids[real_index].ctx = NULL;
358 hw_update = 1;
359 }
360 }
361 if (!ret && hw_update) {
362 int i;
363
364 gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
365 if (!gids) {
366 ret = -ENOMEM;
367 } else {
368 for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
369 memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
370 }
371 }
372 spin_unlock_bh(&iboe->lock);
373
374 if (!ret && hw_update) {
375 ret = mlx4_ib_update_gids(gids, ibdev, port_num);
376 kfree(gids);
377 }
378 return ret;
379 }
380
381 int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
382 u8 port_num, int index)
383 {
384 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
385 struct gid_cache_context *ctx = NULL;
386 union ib_gid gid;
387 struct mlx4_port_gid_table *port_gid_table;
388 int real_index = -EINVAL;
389 int i;
390 int ret;
391 unsigned long flags;
392 struct ib_gid_attr attr;
393
394 if (port_num > MLX4_MAX_PORTS)
395 return -EINVAL;
396
397 if (mlx4_is_bonded(ibdev->dev))
398 port_num = 1;
399
400 if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
401 return index;
402
403 ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, &attr);
404 if (ret)
405 return ret;
406
407 if (attr.ndev)
408 dev_put(attr.ndev);
409
410 if (!memcmp(&gid, &zgid, sizeof(gid)))
411 return -EINVAL;
412
413 spin_lock_irqsave(&iboe->lock, flags);
414 port_gid_table = &iboe->gids[port_num - 1];
415
416 for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
417 if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid)) &&
418 attr.gid_type == port_gid_table->gids[i].gid_type) {
419 ctx = port_gid_table->gids[i].ctx;
420 break;
421 }
422 if (ctx)
423 real_index = ctx->real_index;
424 spin_unlock_irqrestore(&iboe->lock, flags);
425 return real_index;
426 }
427
428 static int mlx4_ib_query_device(struct ib_device *ibdev,
429 struct ib_device_attr *props,
430 struct ib_udata *uhw)
431 {
432 struct mlx4_ib_dev *dev = to_mdev(ibdev);
433 struct ib_smp *in_mad = NULL;
434 struct ib_smp *out_mad = NULL;
435 int err;
436 int have_ib_ports;
437 struct mlx4_uverbs_ex_query_device cmd;
438 struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
439 struct mlx4_clock_params clock_params;
440
441 if (uhw->inlen) {
442 if (uhw->inlen < sizeof(cmd))
443 return -EINVAL;
444
445 err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
446 if (err)
447 return err;
448
449 if (cmd.comp_mask)
450 return -EINVAL;
451
452 if (cmd.reserved)
453 return -EINVAL;
454 }
455
456 resp.response_length = offsetof(typeof(resp), response_length) +
457 sizeof(resp.response_length);
458 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
459 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
460 err = -ENOMEM;
461 if (!in_mad || !out_mad)
462 goto out;
463
464 init_query_mad(in_mad);
465 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
466
467 err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
468 1, NULL, NULL, in_mad, out_mad);
469 if (err)
470 goto out;
471
472 memset(props, 0, sizeof *props);
473
474 have_ib_ports = num_ib_ports(dev->dev);
475
476 props->fw_ver = dev->dev->caps.fw_ver;
477 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
478 IB_DEVICE_PORT_ACTIVE_EVENT |
479 IB_DEVICE_SYS_IMAGE_GUID |
480 IB_DEVICE_RC_RNR_NAK_GEN |
481 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
482 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
483 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
484 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
485 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
486 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
487 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
488 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
489 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
490 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
491 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
492 if (dev->dev->caps.max_gso_sz &&
493 (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
494 (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
495 props->device_cap_flags |= IB_DEVICE_UD_TSO;
496 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
497 props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
498 if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
499 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
500 (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
501 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
502 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
503 props->device_cap_flags |= IB_DEVICE_XRC;
504 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
505 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
506 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
507 if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
508 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
509 else
510 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
511 }
512 if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
513 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
514
515 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
516
517 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
518 0xffffff;
519 props->vendor_part_id = dev->dev->persist->pdev->device;
520 props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
521 memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
522
523 props->max_mr_size = ~0ull;
524 props->page_size_cap = dev->dev->caps.page_size_cap;
525 props->max_qp = dev->dev->quotas.qp;
526 props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
527 props->max_sge = min(dev->dev->caps.max_sq_sg,
528 dev->dev->caps.max_rq_sg);
529 props->max_sge_rd = MLX4_MAX_SGE_RD;
530 props->max_cq = dev->dev->quotas.cq;
531 props->max_cqe = dev->dev->caps.max_cqes;
532 props->max_mr = dev->dev->quotas.mpt;
533 props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
534 props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
535 props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
536 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
537 props->max_srq = dev->dev->quotas.srq;
538 props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
539 props->max_srq_sge = dev->dev->caps.max_srq_sge;
540 props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
541 props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
542 props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
543 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
544 props->masked_atomic_cap = props->atomic_cap;
545 props->max_pkeys = dev->dev->caps.pkey_table_len[1];
546 props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
547 props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
548 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
549 props->max_mcast_grp;
550 props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
551 props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
552 props->timestamp_mask = 0xFFFFFFFFFFFFULL;
553 props->max_ah = INT_MAX;
554
555 if (!mlx4_is_slave(dev->dev))
556 err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
557
558 if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
559 resp.response_length += sizeof(resp.hca_core_clock_offset);
560 if (!err && !mlx4_is_slave(dev->dev)) {
561 resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
562 resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
563 }
564 }
565
566 if (uhw->outlen) {
567 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
568 if (err)
569 goto out;
570 }
571 out:
572 kfree(in_mad);
573 kfree(out_mad);
574
575 return err;
576 }
577
578 static enum rdma_link_layer
579 mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
580 {
581 struct mlx4_dev *dev = to_mdev(device)->dev;
582
583 return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
584 IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
585 }
586
587 static int ib_link_query_port(struct ib_device *ibdev, u8 port,
588 struct ib_port_attr *props, int netw_view)
589 {
590 struct ib_smp *in_mad = NULL;
591 struct ib_smp *out_mad = NULL;
592 int ext_active_speed;
593 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
594 int err = -ENOMEM;
595
596 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
597 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
598 if (!in_mad || !out_mad)
599 goto out;
600
601 init_query_mad(in_mad);
602 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
603 in_mad->attr_mod = cpu_to_be32(port);
604
605 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
606 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
607
608 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
609 in_mad, out_mad);
610 if (err)
611 goto out;
612
613
614 props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
615 props->lmc = out_mad->data[34] & 0x7;
616 props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
617 props->sm_sl = out_mad->data[36] & 0xf;
618 props->state = out_mad->data[32] & 0xf;
619 props->phys_state = out_mad->data[33] >> 4;
620 props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
621 if (netw_view)
622 props->gid_tbl_len = out_mad->data[50];
623 else
624 props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
625 props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
626 props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
627 props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
628 props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
629 props->active_width = out_mad->data[31] & 0xf;
630 props->active_speed = out_mad->data[35] >> 4;
631 props->max_mtu = out_mad->data[41] & 0xf;
632 props->active_mtu = out_mad->data[36] >> 4;
633 props->subnet_timeout = out_mad->data[51] & 0x1f;
634 props->max_vl_num = out_mad->data[37] >> 4;
635 props->init_type_reply = out_mad->data[41] >> 4;
636
637 /* Check if extended speeds (EDR/FDR/...) are supported */
638 if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
639 ext_active_speed = out_mad->data[62] >> 4;
640
641 switch (ext_active_speed) {
642 case 1:
643 props->active_speed = IB_SPEED_FDR;
644 break;
645 case 2:
646 props->active_speed = IB_SPEED_EDR;
647 break;
648 }
649 }
650
651 /* If reported active speed is QDR, check if is FDR-10 */
652 if (props->active_speed == IB_SPEED_QDR) {
653 init_query_mad(in_mad);
654 in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
655 in_mad->attr_mod = cpu_to_be32(port);
656
657 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
658 NULL, NULL, in_mad, out_mad);
659 if (err)
660 goto out;
661
662 /* Checking LinkSpeedActive for FDR-10 */
663 if (out_mad->data[15] & 0x1)
664 props->active_speed = IB_SPEED_FDR10;
665 }
666
667 /* Avoid wrong speed value returned by FW if the IB link is down. */
668 if (props->state == IB_PORT_DOWN)
669 props->active_speed = IB_SPEED_SDR;
670
671 out:
672 kfree(in_mad);
673 kfree(out_mad);
674 return err;
675 }
676
677 static u8 state_to_phys_state(enum ib_port_state state)
678 {
679 return state == IB_PORT_ACTIVE ? 5 : 3;
680 }
681
682 static int eth_link_query_port(struct ib_device *ibdev, u8 port,
683 struct ib_port_attr *props)
684 {
685
686 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
687 struct mlx4_ib_iboe *iboe = &mdev->iboe;
688 struct net_device *ndev;
689 enum ib_mtu tmp;
690 struct mlx4_cmd_mailbox *mailbox;
691 int err = 0;
692 int is_bonded = mlx4_is_bonded(mdev->dev);
693
694 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
695 if (IS_ERR(mailbox))
696 return PTR_ERR(mailbox);
697
698 err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
699 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
700 MLX4_CMD_WRAPPED);
701 if (err)
702 goto out;
703
704 props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
705 (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
706 IB_WIDTH_4X : IB_WIDTH_1X;
707 props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
708 IB_SPEED_FDR : IB_SPEED_QDR;
709 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
710 props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
711 props->max_msg_sz = mdev->dev->caps.max_msg_sz;
712 props->pkey_tbl_len = 1;
713 props->max_mtu = IB_MTU_4096;
714 props->max_vl_num = 2;
715 props->state = IB_PORT_DOWN;
716 props->phys_state = state_to_phys_state(props->state);
717 props->active_mtu = IB_MTU_256;
718 spin_lock_bh(&iboe->lock);
719 ndev = iboe->netdevs[port - 1];
720 if (ndev && is_bonded) {
721 rcu_read_lock(); /* required to get upper dev */
722 ndev = netdev_master_upper_dev_get_rcu(ndev);
723 rcu_read_unlock();
724 }
725 if (!ndev)
726 goto out_unlock;
727
728 tmp = iboe_get_mtu(ndev->mtu);
729 props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
730
731 props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
732 IB_PORT_ACTIVE : IB_PORT_DOWN;
733 props->phys_state = state_to_phys_state(props->state);
734 out_unlock:
735 spin_unlock_bh(&iboe->lock);
736 out:
737 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
738 return err;
739 }
740
741 int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
742 struct ib_port_attr *props, int netw_view)
743 {
744 int err;
745
746 /* props being zeroed by the caller, avoid zeroing it here */
747
748 err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
749 ib_link_query_port(ibdev, port, props, netw_view) :
750 eth_link_query_port(ibdev, port, props);
751
752 return err;
753 }
754
755 static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
756 struct ib_port_attr *props)
757 {
758 /* returns host view */
759 return __mlx4_ib_query_port(ibdev, port, props, 0);
760 }
761
762 int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
763 union ib_gid *gid, int netw_view)
764 {
765 struct ib_smp *in_mad = NULL;
766 struct ib_smp *out_mad = NULL;
767 int err = -ENOMEM;
768 struct mlx4_ib_dev *dev = to_mdev(ibdev);
769 int clear = 0;
770 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
771
772 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
773 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
774 if (!in_mad || !out_mad)
775 goto out;
776
777 init_query_mad(in_mad);
778 in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
779 in_mad->attr_mod = cpu_to_be32(port);
780
781 if (mlx4_is_mfunc(dev->dev) && netw_view)
782 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
783
784 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
785 if (err)
786 goto out;
787
788 memcpy(gid->raw, out_mad->data + 8, 8);
789
790 if (mlx4_is_mfunc(dev->dev) && !netw_view) {
791 if (index) {
792 /* For any index > 0, return the null guid */
793 err = 0;
794 clear = 1;
795 goto out;
796 }
797 }
798
799 init_query_mad(in_mad);
800 in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
801 in_mad->attr_mod = cpu_to_be32(index / 8);
802
803 err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
804 NULL, NULL, in_mad, out_mad);
805 if (err)
806 goto out;
807
808 memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
809
810 out:
811 if (clear)
812 memset(gid->raw + 8, 0, 8);
813 kfree(in_mad);
814 kfree(out_mad);
815 return err;
816 }
817
818 static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
819 union ib_gid *gid)
820 {
821 int ret;
822
823 if (rdma_protocol_ib(ibdev, port))
824 return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
825
826 if (!rdma_protocol_roce(ibdev, port))
827 return -ENODEV;
828
829 if (!rdma_cap_roce_gid_table(ibdev, port))
830 return -ENODEV;
831
832 ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
833 if (ret == -EAGAIN) {
834 memcpy(gid, &zgid, sizeof(*gid));
835 return 0;
836 }
837
838 return ret;
839 }
840
841 static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
842 {
843 union sl2vl_tbl_to_u64 sl2vl64;
844 struct ib_smp *in_mad = NULL;
845 struct ib_smp *out_mad = NULL;
846 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
847 int err = -ENOMEM;
848 int jj;
849
850 if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
851 *sl2vl_tbl = 0;
852 return 0;
853 }
854
855 in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
856 out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
857 if (!in_mad || !out_mad)
858 goto out;
859
860 init_query_mad(in_mad);
861 in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
862 in_mad->attr_mod = 0;
863
864 if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
865 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
866
867 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
868 in_mad, out_mad);
869 if (err)
870 goto out;
871
872 for (jj = 0; jj < 8; jj++)
873 sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
874 *sl2vl_tbl = sl2vl64.sl64;
875
876 out:
877 kfree(in_mad);
878 kfree(out_mad);
879 return err;
880 }
881
882 static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
883 {
884 u64 sl2vl;
885 int i;
886 int err;
887
888 for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
889 if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
890 continue;
891 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
892 if (err) {
893 pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
894 i, err);
895 sl2vl = 0;
896 }
897 atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
898 }
899 }
900
901 int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
902 u16 *pkey, int netw_view)
903 {
904 struct ib_smp *in_mad = NULL;
905 struct ib_smp *out_mad = NULL;
906 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
907 int err = -ENOMEM;
908
909 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
910 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
911 if (!in_mad || !out_mad)
912 goto out;
913
914 init_query_mad(in_mad);
915 in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
916 in_mad->attr_mod = cpu_to_be32(index / 32);
917
918 if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
919 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
920
921 err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
922 in_mad, out_mad);
923 if (err)
924 goto out;
925
926 *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
927
928 out:
929 kfree(in_mad);
930 kfree(out_mad);
931 return err;
932 }
933
934 static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
935 {
936 return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
937 }
938
939 static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
940 struct ib_device_modify *props)
941 {
942 struct mlx4_cmd_mailbox *mailbox;
943 unsigned long flags;
944
945 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
946 return -EOPNOTSUPP;
947
948 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
949 return 0;
950
951 if (mlx4_is_slave(to_mdev(ibdev)->dev))
952 return -EOPNOTSUPP;
953
954 spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
955 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
956 spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
957
958 /*
959 * If possible, pass node desc to FW, so it can generate
960 * a 144 trap. If cmd fails, just ignore.
961 */
962 mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
963 if (IS_ERR(mailbox))
964 return 0;
965
966 memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
967 mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
968 MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
969
970 mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
971
972 return 0;
973 }
974
975 static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
976 u32 cap_mask)
977 {
978 struct mlx4_cmd_mailbox *mailbox;
979 int err;
980
981 mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
982 if (IS_ERR(mailbox))
983 return PTR_ERR(mailbox);
984
985 if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
986 *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
987 ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
988 } else {
989 ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
990 ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
991 }
992
993 err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
994 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
995 MLX4_CMD_WRAPPED);
996
997 mlx4_free_cmd_mailbox(dev->dev, mailbox);
998 return err;
999 }
1000
1001 static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1002 struct ib_port_modify *props)
1003 {
1004 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1005 u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
1006 struct ib_port_attr attr;
1007 u32 cap_mask;
1008 int err;
1009
1010 /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1011 * of whether port link layer is ETH or IB. For ETH ports, qkey
1012 * violations and port capabilities are not meaningful.
1013 */
1014 if (is_eth)
1015 return 0;
1016
1017 mutex_lock(&mdev->cap_mask_mutex);
1018
1019 err = ib_query_port(ibdev, port, &attr);
1020 if (err)
1021 goto out;
1022
1023 cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1024 ~props->clr_port_cap_mask;
1025
1026 err = mlx4_ib_SET_PORT(mdev, port,
1027 !!(mask & IB_PORT_RESET_QKEY_CNTR),
1028 cap_mask);
1029
1030 out:
1031 mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1032 return err;
1033 }
1034
1035 static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
1036 struct ib_udata *udata)
1037 {
1038 struct mlx4_ib_dev *dev = to_mdev(ibdev);
1039 struct mlx4_ib_ucontext *context;
1040 struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
1041 struct mlx4_ib_alloc_ucontext_resp resp;
1042 int err;
1043
1044 if (!dev->ib_active)
1045 return ERR_PTR(-EAGAIN);
1046
1047 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1048 resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1049 resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1050 resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1051 } else {
1052 resp.dev_caps = dev->dev->caps.userspace_caps;
1053 resp.qp_tab_size = dev->dev->caps.num_qps;
1054 resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1055 resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1056 resp.cqe_size = dev->dev->caps.cqe_size;
1057 }
1058
1059 context = kzalloc(sizeof(*context), GFP_KERNEL);
1060 if (!context)
1061 return ERR_PTR(-ENOMEM);
1062
1063 err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1064 if (err) {
1065 kfree(context);
1066 return ERR_PTR(err);
1067 }
1068
1069 INIT_LIST_HEAD(&context->db_page_list);
1070 mutex_init(&context->db_page_mutex);
1071
1072 if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1073 err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1074 else
1075 err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1076
1077 if (err) {
1078 mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1079 kfree(context);
1080 return ERR_PTR(-EFAULT);
1081 }
1082
1083 return &context->ibucontext;
1084 }
1085
1086 static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1087 {
1088 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1089
1090 mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1091 kfree(context);
1092
1093 return 0;
1094 }
1095
1096 static void mlx4_ib_vma_open(struct vm_area_struct *area)
1097 {
1098 /* vma_open is called when a new VMA is created on top of our VMA.
1099 * This is done through either mremap flow or split_vma (usually due
1100 * to mlock, madvise, munmap, etc.). We do not support a clone of the
1101 * vma, as this VMA is strongly hardware related. Therefore we set the
1102 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1103 * calling us again and trying to do incorrect actions. We assume that
1104 * the original vma size is exactly a single page that there will be no
1105 * "splitting" operations on.
1106 */
1107 area->vm_ops = NULL;
1108 }
1109
1110 static void mlx4_ib_vma_close(struct vm_area_struct *area)
1111 {
1112 struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
1113
1114 /* It's guaranteed that all VMAs opened on a FD are closed before the
1115 * file itself is closed, therefore no sync is needed with the regular
1116 * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
1117 * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
1118 * The close operation is usually called under mm->mmap_sem except when
1119 * process is exiting. The exiting case is handled explicitly as part
1120 * of mlx4_ib_disassociate_ucontext.
1121 */
1122 mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
1123 area->vm_private_data;
1124
1125 /* set the vma context pointer to null in the mlx4_ib driver's private
1126 * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
1127 */
1128 mlx4_ib_vma_priv_data->vma = NULL;
1129 }
1130
1131 static const struct vm_operations_struct mlx4_ib_vm_ops = {
1132 .open = mlx4_ib_vma_open,
1133 .close = mlx4_ib_vma_close
1134 };
1135
1136 static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1137 {
1138 int i;
1139 int ret = 0;
1140 struct vm_area_struct *vma;
1141 struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1142 struct task_struct *owning_process = NULL;
1143 struct mm_struct *owning_mm = NULL;
1144
1145 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1146 if (!owning_process)
1147 return;
1148
1149 owning_mm = get_task_mm(owning_process);
1150 if (!owning_mm) {
1151 pr_info("no mm, disassociate ucontext is pending task termination\n");
1152 while (1) {
1153 /* make sure that task is dead before returning, it may
1154 * prevent a rare case of module down in parallel to a
1155 * call to mlx4_ib_vma_close.
1156 */
1157 put_task_struct(owning_process);
1158 msleep(1);
1159 owning_process = get_pid_task(ibcontext->tgid,
1160 PIDTYPE_PID);
1161 if (!owning_process ||
1162 owning_process->state == TASK_DEAD) {
1163 pr_info("disassociate ucontext done, task was terminated\n");
1164 /* in case task was dead need to release the task struct */
1165 if (owning_process)
1166 put_task_struct(owning_process);
1167 return;
1168 }
1169 }
1170 }
1171
1172 /* need to protect from a race on closing the vma as part of
1173 * mlx4_ib_vma_close().
1174 */
1175 down_read(&owning_mm->mmap_sem);
1176 for (i = 0; i < HW_BAR_COUNT; i++) {
1177 vma = context->hw_bar_info[i].vma;
1178 if (!vma)
1179 continue;
1180
1181 ret = zap_vma_ptes(context->hw_bar_info[i].vma,
1182 context->hw_bar_info[i].vma->vm_start,
1183 PAGE_SIZE);
1184 if (ret) {
1185 pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
1186 BUG_ON(1);
1187 }
1188
1189 /* context going to be destroyed, should not access ops any more */
1190 context->hw_bar_info[i].vma->vm_ops = NULL;
1191 }
1192
1193 up_read(&owning_mm->mmap_sem);
1194 mmput(owning_mm);
1195 put_task_struct(owning_process);
1196 }
1197
1198 static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
1199 struct mlx4_ib_vma_private_data *vma_private_data)
1200 {
1201 vma_private_data->vma = vma;
1202 vma->vm_private_data = vma_private_data;
1203 vma->vm_ops = &mlx4_ib_vm_ops;
1204 }
1205
1206 static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1207 {
1208 struct mlx4_ib_dev *dev = to_mdev(context->device);
1209 struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
1210
1211 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1212 return -EINVAL;
1213
1214 if (vma->vm_pgoff == 0) {
1215 /* We prevent double mmaping on same context */
1216 if (mucontext->hw_bar_info[HW_BAR_DB].vma)
1217 return -EINVAL;
1218
1219 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1220
1221 if (io_remap_pfn_range(vma, vma->vm_start,
1222 to_mucontext(context)->uar.pfn,
1223 PAGE_SIZE, vma->vm_page_prot))
1224 return -EAGAIN;
1225
1226 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
1227
1228 } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
1229 /* We prevent double mmaping on same context */
1230 if (mucontext->hw_bar_info[HW_BAR_BF].vma)
1231 return -EINVAL;
1232
1233 vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
1234
1235 if (io_remap_pfn_range(vma, vma->vm_start,
1236 to_mucontext(context)->uar.pfn +
1237 dev->dev->caps.num_uars,
1238 PAGE_SIZE, vma->vm_page_prot))
1239 return -EAGAIN;
1240
1241 mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
1242
1243 } else if (vma->vm_pgoff == 3) {
1244 struct mlx4_clock_params params;
1245 int ret;
1246
1247 /* We prevent double mmaping on same context */
1248 if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
1249 return -EINVAL;
1250
1251 ret = mlx4_get_internal_clock_params(dev->dev, &params);
1252
1253 if (ret)
1254 return ret;
1255
1256 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1257 if (io_remap_pfn_range(vma, vma->vm_start,
1258 (pci_resource_start(dev->dev->persist->pdev,
1259 params.bar) +
1260 params.offset)
1261 >> PAGE_SHIFT,
1262 PAGE_SIZE, vma->vm_page_prot))
1263 return -EAGAIN;
1264
1265 mlx4_ib_set_vma_data(vma,
1266 &mucontext->hw_bar_info[HW_BAR_CLOCK]);
1267 } else {
1268 return -EINVAL;
1269 }
1270
1271 return 0;
1272 }
1273
1274 static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
1275 struct ib_ucontext *context,
1276 struct ib_udata *udata)
1277 {
1278 struct mlx4_ib_pd *pd;
1279 int err;
1280
1281 pd = kmalloc(sizeof *pd, GFP_KERNEL);
1282 if (!pd)
1283 return ERR_PTR(-ENOMEM);
1284
1285 err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1286 if (err) {
1287 kfree(pd);
1288 return ERR_PTR(err);
1289 }
1290
1291 if (context)
1292 if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
1293 mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1294 kfree(pd);
1295 return ERR_PTR(-EFAULT);
1296 }
1297
1298 return &pd->ibpd;
1299 }
1300
1301 static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
1302 {
1303 mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1304 kfree(pd);
1305
1306 return 0;
1307 }
1308
1309 static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
1310 struct ib_ucontext *context,
1311 struct ib_udata *udata)
1312 {
1313 struct mlx4_ib_xrcd *xrcd;
1314 struct ib_cq_init_attr cq_attr = {};
1315 int err;
1316
1317 if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1318 return ERR_PTR(-ENOSYS);
1319
1320 xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
1321 if (!xrcd)
1322 return ERR_PTR(-ENOMEM);
1323
1324 err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
1325 if (err)
1326 goto err1;
1327
1328 xrcd->pd = ib_alloc_pd(ibdev, 0);
1329 if (IS_ERR(xrcd->pd)) {
1330 err = PTR_ERR(xrcd->pd);
1331 goto err2;
1332 }
1333
1334 cq_attr.cqe = 1;
1335 xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
1336 if (IS_ERR(xrcd->cq)) {
1337 err = PTR_ERR(xrcd->cq);
1338 goto err3;
1339 }
1340
1341 return &xrcd->ibxrcd;
1342
1343 err3:
1344 ib_dealloc_pd(xrcd->pd);
1345 err2:
1346 mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
1347 err1:
1348 kfree(xrcd);
1349 return ERR_PTR(err);
1350 }
1351
1352 static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
1353 {
1354 ib_destroy_cq(to_mxrcd(xrcd)->cq);
1355 ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1356 mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1357 kfree(xrcd);
1358
1359 return 0;
1360 }
1361
1362 static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1363 {
1364 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1365 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1366 struct mlx4_ib_gid_entry *ge;
1367
1368 ge = kzalloc(sizeof *ge, GFP_KERNEL);
1369 if (!ge)
1370 return -ENOMEM;
1371
1372 ge->gid = *gid;
1373 if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1374 ge->port = mqp->port;
1375 ge->added = 1;
1376 }
1377
1378 mutex_lock(&mqp->mutex);
1379 list_add_tail(&ge->list, &mqp->gid_list);
1380 mutex_unlock(&mqp->mutex);
1381
1382 return 0;
1383 }
1384
1385 static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1386 struct mlx4_ib_counters *ctr_table)
1387 {
1388 struct counter_index *counter, *tmp_count;
1389
1390 mutex_lock(&ctr_table->mutex);
1391 list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1392 list) {
1393 if (counter->allocated)
1394 mlx4_counter_free(ibdev->dev, counter->index);
1395 list_del(&counter->list);
1396 kfree(counter);
1397 }
1398 mutex_unlock(&ctr_table->mutex);
1399 }
1400
1401 int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1402 union ib_gid *gid)
1403 {
1404 struct net_device *ndev;
1405 int ret = 0;
1406
1407 if (!mqp->port)
1408 return 0;
1409
1410 spin_lock_bh(&mdev->iboe.lock);
1411 ndev = mdev->iboe.netdevs[mqp->port - 1];
1412 if (ndev)
1413 dev_hold(ndev);
1414 spin_unlock_bh(&mdev->iboe.lock);
1415
1416 if (ndev) {
1417 ret = 1;
1418 dev_put(ndev);
1419 }
1420
1421 return ret;
1422 }
1423
1424 struct mlx4_ib_steering {
1425 struct list_head list;
1426 struct mlx4_flow_reg_id reg_id;
1427 union ib_gid gid;
1428 };
1429
1430 #define LAST_ETH_FIELD vlan_tag
1431 #define LAST_IB_FIELD sl
1432 #define LAST_IPV4_FIELD dst_ip
1433 #define LAST_TCP_UDP_FIELD src_port
1434
1435 /* Field is the last supported field */
1436 #define FIELDS_NOT_SUPPORTED(filter, field)\
1437 memchr_inv((void *)&filter.field +\
1438 sizeof(filter.field), 0,\
1439 sizeof(filter) -\
1440 offsetof(typeof(filter), field) -\
1441 sizeof(filter.field))
1442
1443 static int parse_flow_attr(struct mlx4_dev *dev,
1444 u32 qp_num,
1445 union ib_flow_spec *ib_spec,
1446 struct _rule_hw *mlx4_spec)
1447 {
1448 enum mlx4_net_trans_rule_id type;
1449
1450 switch (ib_spec->type) {
1451 case IB_FLOW_SPEC_ETH:
1452 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1453 return -ENOTSUPP;
1454
1455 type = MLX4_NET_TRANS_RULE_ID_ETH;
1456 memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1457 ETH_ALEN);
1458 memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1459 ETH_ALEN);
1460 mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1461 mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1462 break;
1463 case IB_FLOW_SPEC_IB:
1464 if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1465 return -ENOTSUPP;
1466
1467 type = MLX4_NET_TRANS_RULE_ID_IB;
1468 mlx4_spec->ib.l3_qpn =
1469 cpu_to_be32(qp_num);
1470 mlx4_spec->ib.qpn_mask =
1471 cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1472 break;
1473
1474
1475 case IB_FLOW_SPEC_IPV4:
1476 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1477 return -ENOTSUPP;
1478
1479 type = MLX4_NET_TRANS_RULE_ID_IPV4;
1480 mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1481 mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1482 mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1483 mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1484 break;
1485
1486 case IB_FLOW_SPEC_TCP:
1487 case IB_FLOW_SPEC_UDP:
1488 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1489 return -ENOTSUPP;
1490
1491 type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1492 MLX4_NET_TRANS_RULE_ID_TCP :
1493 MLX4_NET_TRANS_RULE_ID_UDP;
1494 mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1495 mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1496 mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1497 mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1498 break;
1499
1500 default:
1501 return -EINVAL;
1502 }
1503 if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1504 mlx4_hw_rule_sz(dev, type) < 0)
1505 return -EINVAL;
1506 mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1507 mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1508 return mlx4_hw_rule_sz(dev, type);
1509 }
1510
1511 struct default_rules {
1512 __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1513 __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1514 __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1515 __u8 link_layer;
1516 };
1517 static const struct default_rules default_table[] = {
1518 {
1519 .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1520 .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1521 .rules_create_list = {IB_FLOW_SPEC_IB},
1522 .link_layer = IB_LINK_LAYER_INFINIBAND
1523 }
1524 };
1525
1526 static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1527 struct ib_flow_attr *flow_attr)
1528 {
1529 int i, j, k;
1530 void *ib_flow;
1531 const struct default_rules *pdefault_rules = default_table;
1532 u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1533
1534 for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
1535 __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1536 memset(&field_types, 0, sizeof(field_types));
1537
1538 if (link_layer != pdefault_rules->link_layer)
1539 continue;
1540
1541 ib_flow = flow_attr + 1;
1542 /* we assume the specs are sorted */
1543 for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1544 j < flow_attr->num_of_specs; k++) {
1545 union ib_flow_spec *current_flow =
1546 (union ib_flow_spec *)ib_flow;
1547
1548 /* same layer but different type */
1549 if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1550 (pdefault_rules->mandatory_fields[k] &
1551 IB_FLOW_SPEC_LAYER_MASK)) &&
1552 (current_flow->type !=
1553 pdefault_rules->mandatory_fields[k]))
1554 goto out;
1555
1556 /* same layer, try match next one */
1557 if (current_flow->type ==
1558 pdefault_rules->mandatory_fields[k]) {
1559 j++;
1560 ib_flow +=
1561 ((union ib_flow_spec *)ib_flow)->size;
1562 }
1563 }
1564
1565 ib_flow = flow_attr + 1;
1566 for (j = 0; j < flow_attr->num_of_specs;
1567 j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1568 for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1569 /* same layer and same type */
1570 if (((union ib_flow_spec *)ib_flow)->type ==
1571 pdefault_rules->mandatory_not_fields[k])
1572 goto out;
1573
1574 return i;
1575 }
1576 out:
1577 return -1;
1578 }
1579
1580 static int __mlx4_ib_create_default_rules(
1581 struct mlx4_ib_dev *mdev,
1582 struct ib_qp *qp,
1583 const struct default_rules *pdefault_rules,
1584 struct _rule_hw *mlx4_spec) {
1585 int size = 0;
1586 int i;
1587
1588 for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
1589 int ret;
1590 union ib_flow_spec ib_spec;
1591 switch (pdefault_rules->rules_create_list[i]) {
1592 case 0:
1593 /* no rule */
1594 continue;
1595 case IB_FLOW_SPEC_IB:
1596 ib_spec.type = IB_FLOW_SPEC_IB;
1597 ib_spec.size = sizeof(struct ib_flow_spec_ib);
1598
1599 break;
1600 default:
1601 /* invalid rule */
1602 return -EINVAL;
1603 }
1604 /* We must put empty rule, qpn is being ignored */
1605 ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1606 mlx4_spec);
1607 if (ret < 0) {
1608 pr_info("invalid parsing\n");
1609 return -EINVAL;
1610 }
1611
1612 mlx4_spec = (void *)mlx4_spec + ret;
1613 size += ret;
1614 }
1615 return size;
1616 }
1617
1618 static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1619 int domain,
1620 enum mlx4_net_trans_promisc_mode flow_type,
1621 u64 *reg_id)
1622 {
1623 int ret, i;
1624 int size = 0;
1625 void *ib_flow;
1626 struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1627 struct mlx4_cmd_mailbox *mailbox;
1628 struct mlx4_net_trans_rule_hw_ctrl *ctrl;
1629 int default_flow;
1630
1631 static const u16 __mlx4_domain[] = {
1632 [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
1633 [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
1634 [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
1635 [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
1636 };
1637
1638 if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1639 pr_err("Invalid priority value %d\n", flow_attr->priority);
1640 return -EINVAL;
1641 }
1642
1643 if (domain >= IB_FLOW_DOMAIN_NUM) {
1644 pr_err("Invalid domain value %d\n", domain);
1645 return -EINVAL;
1646 }
1647
1648 if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1649 return -EINVAL;
1650
1651 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1652 if (IS_ERR(mailbox))
1653 return PTR_ERR(mailbox);
1654 ctrl = mailbox->buf;
1655
1656 ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
1657 flow_attr->priority);
1658 ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1659 ctrl->port = flow_attr->port;
1660 ctrl->qpn = cpu_to_be32(qp->qp_num);
1661
1662 ib_flow = flow_attr + 1;
1663 size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
1664 /* Add default flows */
1665 default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1666 if (default_flow >= 0) {
1667 ret = __mlx4_ib_create_default_rules(
1668 mdev, qp, default_table + default_flow,
1669 mailbox->buf + size);
1670 if (ret < 0) {
1671 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1672 return -EINVAL;
1673 }
1674 size += ret;
1675 }
1676 for (i = 0; i < flow_attr->num_of_specs; i++) {
1677 ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1678 mailbox->buf + size);
1679 if (ret < 0) {
1680 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1681 return -EINVAL;
1682 }
1683 ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1684 size += ret;
1685 }
1686
1687 if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
1688 flow_attr->num_of_specs == 1) {
1689 struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
1690 enum ib_flow_spec_type header_spec =
1691 ((union ib_flow_spec *)(flow_attr + 1))->type;
1692
1693 if (header_spec == IB_FLOW_SPEC_ETH)
1694 mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
1695 }
1696
1697 ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1698 MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1699 MLX4_CMD_NATIVE);
1700 if (ret == -ENOMEM)
1701 pr_err("mcg table is full. Fail to register network rule.\n");
1702 else if (ret == -ENXIO)
1703 pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1704 else if (ret)
1705 pr_err("Invalid argument. Fail to register network rule.\n");
1706
1707 mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1708 return ret;
1709 }
1710
1711 static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1712 {
1713 int err;
1714 err = mlx4_cmd(dev, reg_id, 0, 0,
1715 MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1716 MLX4_CMD_NATIVE);
1717 if (err)
1718 pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1719 reg_id);
1720 return err;
1721 }
1722
1723 static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1724 u64 *reg_id)
1725 {
1726 void *ib_flow;
1727 union ib_flow_spec *ib_spec;
1728 struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1729 int err = 0;
1730
1731 if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1732 dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
1733 return 0; /* do nothing */
1734
1735 ib_flow = flow_attr + 1;
1736 ib_spec = (union ib_flow_spec *)ib_flow;
1737
1738 if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1739 return 0; /* do nothing */
1740
1741 err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1742 flow_attr->port, qp->qp_num,
1743 MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1744 reg_id);
1745 return err;
1746 }
1747
1748 static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1749 struct ib_flow_attr *flow_attr,
1750 enum mlx4_net_trans_promisc_mode *type)
1751 {
1752 int err = 0;
1753
1754 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1755 (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1756 (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1757 return -EOPNOTSUPP;
1758 }
1759
1760 if (flow_attr->num_of_specs == 0) {
1761 type[0] = MLX4_FS_MC_SNIFFER;
1762 type[1] = MLX4_FS_UC_SNIFFER;
1763 } else {
1764 union ib_flow_spec *ib_spec;
1765
1766 ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1767 if (ib_spec->type != IB_FLOW_SPEC_ETH)
1768 return -EINVAL;
1769
1770 /* if all is zero than MC and UC */
1771 if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1772 type[0] = MLX4_FS_MC_SNIFFER;
1773 type[1] = MLX4_FS_UC_SNIFFER;
1774 } else {
1775 u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1776 ib_spec->eth.mask.dst_mac[1],
1777 ib_spec->eth.mask.dst_mac[2],
1778 ib_spec->eth.mask.dst_mac[3],
1779 ib_spec->eth.mask.dst_mac[4],
1780 ib_spec->eth.mask.dst_mac[5]};
1781
1782 /* Above xor was only on MC bit, non empty mask is valid
1783 * only if this bit is set and rest are zero.
1784 */
1785 if (!is_zero_ether_addr(&mac[0]))
1786 return -EINVAL;
1787
1788 if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1789 type[0] = MLX4_FS_MC_SNIFFER;
1790 else
1791 type[0] = MLX4_FS_UC_SNIFFER;
1792 }
1793 }
1794
1795 return err;
1796 }
1797
1798 static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1799 struct ib_flow_attr *flow_attr,
1800 int domain)
1801 {
1802 int err = 0, i = 0, j = 0;
1803 struct mlx4_ib_flow *mflow;
1804 enum mlx4_net_trans_promisc_mode type[2];
1805 struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1806 int is_bonded = mlx4_is_bonded(dev);
1807
1808 if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1809 return ERR_PTR(-EINVAL);
1810
1811 if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1812 (flow_attr->type != IB_FLOW_ATTR_NORMAL))
1813 return ERR_PTR(-EOPNOTSUPP);
1814
1815 memset(type, 0, sizeof(type));
1816
1817 mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1818 if (!mflow) {
1819 err = -ENOMEM;
1820 goto err_free;
1821 }
1822
1823 switch (flow_attr->type) {
1824 case IB_FLOW_ATTR_NORMAL:
1825 /* If dont trap flag (continue match) is set, under specific
1826 * condition traffic be replicated to given qp,
1827 * without stealing it
1828 */
1829 if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1830 err = mlx4_ib_add_dont_trap_rule(dev,
1831 flow_attr,
1832 type);
1833 if (err)
1834 goto err_free;
1835 } else {
1836 type[0] = MLX4_FS_REGULAR;
1837 }
1838 break;
1839
1840 case IB_FLOW_ATTR_ALL_DEFAULT:
1841 type[0] = MLX4_FS_ALL_DEFAULT;
1842 break;
1843
1844 case IB_FLOW_ATTR_MC_DEFAULT:
1845 type[0] = MLX4_FS_MC_DEFAULT;
1846 break;
1847
1848 case IB_FLOW_ATTR_SNIFFER:
1849 type[0] = MLX4_FS_MIRROR_RX_PORT;
1850 type[1] = MLX4_FS_MIRROR_SX_PORT;
1851 break;
1852
1853 default:
1854 err = -EINVAL;
1855 goto err_free;
1856 }
1857
1858 while (i < ARRAY_SIZE(type) && type[i]) {
1859 err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
1860 &mflow->reg_id[i].id);
1861 if (err)
1862 goto err_create_flow;
1863 if (is_bonded) {
1864 /* Application always sees one port so the mirror rule
1865 * must be on port #2
1866 */
1867 flow_attr->port = 2;
1868 err = __mlx4_ib_create_flow(qp, flow_attr,
1869 domain, type[j],
1870 &mflow->reg_id[j].mirror);
1871 flow_attr->port = 1;
1872 if (err)
1873 goto err_create_flow;
1874 j++;
1875 }
1876
1877 i++;
1878 }
1879
1880 if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1881 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1882 &mflow->reg_id[i].id);
1883 if (err)
1884 goto err_create_flow;
1885
1886 if (is_bonded) {
1887 flow_attr->port = 2;
1888 err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1889 &mflow->reg_id[j].mirror);
1890 flow_attr->port = 1;
1891 if (err)
1892 goto err_create_flow;
1893 j++;
1894 }
1895 /* function to create mirror rule */
1896 i++;
1897 }
1898
1899 return &mflow->ibflow;
1900
1901 err_create_flow:
1902 while (i) {
1903 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1904 mflow->reg_id[i].id);
1905 i--;
1906 }
1907
1908 while (j) {
1909 (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1910 mflow->reg_id[j].mirror);
1911 j--;
1912 }
1913 err_free:
1914 kfree(mflow);
1915 return ERR_PTR(err);
1916 }
1917
1918 static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1919 {
1920 int err, ret = 0;
1921 int i = 0;
1922 struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1923 struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1924
1925 while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1926 err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
1927 if (err)
1928 ret = err;
1929 if (mflow->reg_id[i].mirror) {
1930 err = __mlx4_ib_destroy_flow(mdev->dev,
1931 mflow->reg_id[i].mirror);
1932 if (err)
1933 ret = err;
1934 }
1935 i++;
1936 }
1937
1938 kfree(mflow);
1939 return ret;
1940 }
1941
1942 static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1943 {
1944 int err;
1945 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1946 struct mlx4_dev *dev = mdev->dev;
1947 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1948 struct mlx4_ib_steering *ib_steering = NULL;
1949 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1950 struct mlx4_flow_reg_id reg_id;
1951
1952 if (mdev->dev->caps.steering_mode ==
1953 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1954 ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1955 if (!ib_steering)
1956 return -ENOMEM;
1957 }
1958
1959 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1960 !!(mqp->flags &
1961 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1962 prot, &reg_id.id);
1963 if (err) {
1964 pr_err("multicast attach op failed, err %d\n", err);
1965 goto err_malloc;
1966 }
1967
1968 reg_id.mirror = 0;
1969 if (mlx4_is_bonded(dev)) {
1970 err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1971 (mqp->port == 1) ? 2 : 1,
1972 !!(mqp->flags &
1973 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1974 prot, &reg_id.mirror);
1975 if (err)
1976 goto err_add;
1977 }
1978
1979 err = add_gid_entry(ibqp, gid);
1980 if (err)
1981 goto err_add;
1982
1983 if (ib_steering) {
1984 memcpy(ib_steering->gid.raw, gid->raw, 16);
1985 ib_steering->reg_id = reg_id;
1986 mutex_lock(&mqp->mutex);
1987 list_add(&ib_steering->list, &mqp->steering_rules);
1988 mutex_unlock(&mqp->mutex);
1989 }
1990 return 0;
1991
1992 err_add:
1993 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1994 prot, reg_id.id);
1995 if (reg_id.mirror)
1996 mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1997 prot, reg_id.mirror);
1998 err_malloc:
1999 kfree(ib_steering);
2000
2001 return err;
2002 }
2003
2004 static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
2005 {
2006 struct mlx4_ib_gid_entry *ge;
2007 struct mlx4_ib_gid_entry *tmp;
2008 struct mlx4_ib_gid_entry *ret = NULL;
2009
2010 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
2011 if (!memcmp(raw, ge->gid.raw, 16)) {
2012 ret = ge;
2013 break;
2014 }
2015 }
2016
2017 return ret;
2018 }
2019
2020 static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2021 {
2022 int err;
2023 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
2024 struct mlx4_dev *dev = mdev->dev;
2025 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2026 struct net_device *ndev;
2027 struct mlx4_ib_gid_entry *ge;
2028 struct mlx4_flow_reg_id reg_id = {0, 0};
2029 enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
2030
2031 if (mdev->dev->caps.steering_mode ==
2032 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2033 struct mlx4_ib_steering *ib_steering;
2034
2035 mutex_lock(&mqp->mutex);
2036 list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
2037 if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
2038 list_del(&ib_steering->list);
2039 break;
2040 }
2041 }
2042 mutex_unlock(&mqp->mutex);
2043 if (&ib_steering->list == &mqp->steering_rules) {
2044 pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
2045 return -EINVAL;
2046 }
2047 reg_id = ib_steering->reg_id;
2048 kfree(ib_steering);
2049 }
2050
2051 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2052 prot, reg_id.id);
2053 if (err)
2054 return err;
2055
2056 if (mlx4_is_bonded(dev)) {
2057 err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
2058 prot, reg_id.mirror);
2059 if (err)
2060 return err;
2061 }
2062
2063 mutex_lock(&mqp->mutex);
2064 ge = find_gid_entry(mqp, gid->raw);
2065 if (ge) {
2066 spin_lock_bh(&mdev->iboe.lock);
2067 ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
2068 if (ndev)
2069 dev_hold(ndev);
2070 spin_unlock_bh(&mdev->iboe.lock);
2071 if (ndev)
2072 dev_put(ndev);
2073 list_del(&ge->list);
2074 kfree(ge);
2075 } else
2076 pr_warn("could not find mgid entry\n");
2077
2078 mutex_unlock(&mqp->mutex);
2079
2080 return 0;
2081 }
2082
2083 static int init_node_data(struct mlx4_ib_dev *dev)
2084 {
2085 struct ib_smp *in_mad = NULL;
2086 struct ib_smp *out_mad = NULL;
2087 int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
2088 int err = -ENOMEM;
2089
2090 in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
2091 out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
2092 if (!in_mad || !out_mad)
2093 goto out;
2094
2095 init_query_mad(in_mad);
2096 in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
2097 if (mlx4_is_master(dev->dev))
2098 mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
2099
2100 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2101 if (err)
2102 goto out;
2103
2104 memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
2105
2106 in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2107
2108 err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2109 if (err)
2110 goto out;
2111
2112 dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
2113 memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2114
2115 out:
2116 kfree(in_mad);
2117 kfree(out_mad);
2118 return err;
2119 }
2120
2121 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2122 char *buf)
2123 {
2124 struct mlx4_ib_dev *dev =
2125 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2126 return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
2127 }
2128
2129 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2130 char *buf)
2131 {
2132 struct mlx4_ib_dev *dev =
2133 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2134 return sprintf(buf, "%x\n", dev->dev->rev_id);
2135 }
2136
2137 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2138 char *buf)
2139 {
2140 struct mlx4_ib_dev *dev =
2141 container_of(device, struct mlx4_ib_dev, ib_dev.dev);
2142 return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2143 dev->dev->board_id);
2144 }
2145
2146 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2147 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2148 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2149
2150 static struct device_attribute *mlx4_class_attributes[] = {
2151 &dev_attr_hw_rev,
2152 &dev_attr_hca_type,
2153 &dev_attr_board_id
2154 };
2155
2156 struct diag_counter {
2157 const char *name;
2158 u32 offset;
2159 };
2160
2161 #define DIAG_COUNTER(_name, _offset) \
2162 { .name = #_name, .offset = _offset }
2163
2164 static const struct diag_counter diag_basic[] = {
2165 DIAG_COUNTER(rq_num_lle, 0x00),
2166 DIAG_COUNTER(sq_num_lle, 0x04),
2167 DIAG_COUNTER(rq_num_lqpoe, 0x08),
2168 DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2169 DIAG_COUNTER(rq_num_lpe, 0x18),
2170 DIAG_COUNTER(sq_num_lpe, 0x1C),
2171 DIAG_COUNTER(rq_num_wrfe, 0x20),
2172 DIAG_COUNTER(sq_num_wrfe, 0x24),
2173 DIAG_COUNTER(sq_num_mwbe, 0x2C),
2174 DIAG_COUNTER(sq_num_bre, 0x34),
2175 DIAG_COUNTER(sq_num_rire, 0x44),
2176 DIAG_COUNTER(rq_num_rire, 0x48),
2177 DIAG_COUNTER(sq_num_rae, 0x4C),
2178 DIAG_COUNTER(rq_num_rae, 0x50),
2179 DIAG_COUNTER(sq_num_roe, 0x54),
2180 DIAG_COUNTER(sq_num_tree, 0x5C),
2181 DIAG_COUNTER(sq_num_rree, 0x64),
2182 DIAG_COUNTER(rq_num_rnr, 0x68),
2183 DIAG_COUNTER(sq_num_rnr, 0x6C),
2184 DIAG_COUNTER(rq_num_oos, 0x100),
2185 DIAG_COUNTER(sq_num_oos, 0x104),
2186 };
2187
2188 static const struct diag_counter diag_ext[] = {
2189 DIAG_COUNTER(rq_num_dup, 0x130),
2190 DIAG_COUNTER(sq_num_to, 0x134),
2191 };
2192
2193 static const struct diag_counter diag_device_only[] = {
2194 DIAG_COUNTER(num_cqovf, 0x1A0),
2195 DIAG_COUNTER(rq_num_udsdprd, 0x118),
2196 };
2197
2198 static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2199 u8 port_num)
2200 {
2201 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2202 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2203
2204 if (!diag[!!port_num].name)
2205 return NULL;
2206
2207 return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2208 diag[!!port_num].num_counters,
2209 RDMA_HW_STATS_DEFAULT_LIFESPAN);
2210 }
2211
2212 static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2213 struct rdma_hw_stats *stats,
2214 u8 port, int index)
2215 {
2216 struct mlx4_ib_dev *dev = to_mdev(ibdev);
2217 struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2218 u32 hw_value[ARRAY_SIZE(diag_device_only) +
2219 ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2220 int ret;
2221 int i;
2222
2223 ret = mlx4_query_diag_counters(dev->dev,
2224 MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2225 diag[!!port].offset, hw_value,
2226 diag[!!port].num_counters, port);
2227
2228 if (ret)
2229 return ret;
2230
2231 for (i = 0; i < diag[!!port].num_counters; i++)
2232 stats->value[i] = hw_value[i];
2233
2234 return diag[!!port].num_counters;
2235 }
2236
2237 static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2238 const char ***name,
2239 u32 **offset,
2240 u32 *num,
2241 bool port)
2242 {
2243 u32 num_counters;
2244
2245 num_counters = ARRAY_SIZE(diag_basic);
2246
2247 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2248 num_counters += ARRAY_SIZE(diag_ext);
2249
2250 if (!port)
2251 num_counters += ARRAY_SIZE(diag_device_only);
2252
2253 *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2254 if (!*name)
2255 return -ENOMEM;
2256
2257 *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2258 if (!*offset)
2259 goto err_name;
2260
2261 *num = num_counters;
2262
2263 return 0;
2264
2265 err_name:
2266 kfree(*name);
2267 return -ENOMEM;
2268 }
2269
2270 static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2271 const char **name,
2272 u32 *offset,
2273 bool port)
2274 {
2275 int i;
2276 int j;
2277
2278 for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2279 name[i] = diag_basic[i].name;
2280 offset[i] = diag_basic[i].offset;
2281 }
2282
2283 if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2284 for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2285 name[j] = diag_ext[i].name;
2286 offset[j] = diag_ext[i].offset;
2287 }
2288 }
2289
2290 if (!port) {
2291 for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2292 name[j] = diag_device_only[i].name;
2293 offset[j] = diag_device_only[i].offset;
2294 }
2295 }
2296 }
2297
2298 static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2299 {
2300 struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2301 int i;
2302 int ret;
2303 bool per_port = !!(ibdev->dev->caps.flags2 &
2304 MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2305
2306 if (mlx4_is_slave(ibdev->dev))
2307 return 0;
2308
2309 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2310 /* i == 1 means we are building port counters */
2311 if (i && !per_port)
2312 continue;
2313
2314 ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2315 &diag[i].offset,
2316 &diag[i].num_counters, i);
2317 if (ret)
2318 goto err_alloc;
2319
2320 mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2321 diag[i].offset, i);
2322 }
2323
2324 ibdev->ib_dev.get_hw_stats = mlx4_ib_get_hw_stats;
2325 ibdev->ib_dev.alloc_hw_stats = mlx4_ib_alloc_hw_stats;
2326
2327 return 0;
2328
2329 err_alloc:
2330 if (i) {
2331 kfree(diag[i - 1].name);
2332 kfree(diag[i - 1].offset);
2333 }
2334
2335 return ret;
2336 }
2337
2338 static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2339 {
2340 int i;
2341
2342 for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2343 kfree(ibdev->diag_counters[i].offset);
2344 kfree(ibdev->diag_counters[i].name);
2345 }
2346 }
2347
2348 #define MLX4_IB_INVALID_MAC ((u64)-1)
2349 static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2350 struct net_device *dev,
2351 int port)
2352 {
2353 u64 new_smac = 0;
2354 u64 release_mac = MLX4_IB_INVALID_MAC;
2355 struct mlx4_ib_qp *qp;
2356
2357 read_lock(&dev_base_lock);
2358 new_smac = mlx4_mac_to_u64(dev->dev_addr);
2359 read_unlock(&dev_base_lock);
2360
2361 atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2362
2363 /* no need for update QP1 and mac registration in non-SRIOV */
2364 if (!mlx4_is_mfunc(ibdev->dev))
2365 return;
2366
2367 mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2368 qp = ibdev->qp1_proxy[port - 1];
2369 if (qp) {
2370 int new_smac_index;
2371 u64 old_smac;
2372 struct mlx4_update_qp_params update_params;
2373
2374 mutex_lock(&qp->mutex);
2375 old_smac = qp->pri.smac;
2376 if (new_smac == old_smac)
2377 goto unlock;
2378
2379 new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2380
2381 if (new_smac_index < 0)
2382 goto unlock;
2383
2384 update_params.smac_index = new_smac_index;
2385 if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
2386 &update_params)) {
2387 release_mac = new_smac;
2388 goto unlock;
2389 }
2390 /* if old port was zero, no mac was yet registered for this QP */
2391 if (qp->pri.smac_port)
2392 release_mac = old_smac;
2393 qp->pri.smac = new_smac;
2394 qp->pri.smac_port = port;
2395 qp->pri.smac_index = new_smac_index;
2396 }
2397
2398 unlock:
2399 if (release_mac != MLX4_IB_INVALID_MAC)
2400 mlx4_unregister_mac(ibdev->dev, port, release_mac);
2401 if (qp)
2402 mutex_unlock(&qp->mutex);
2403 mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
2404 }
2405
2406 static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2407 struct net_device *dev,
2408 unsigned long event)
2409
2410 {
2411 struct mlx4_ib_iboe *iboe;
2412 int update_qps_port = -1;
2413 int port;
2414
2415 ASSERT_RTNL();
2416
2417 iboe = &ibdev->iboe;
2418
2419 spin_lock_bh(&iboe->lock);
2420 mlx4_foreach_ib_transport_port(port, ibdev->dev) {
2421
2422 iboe->netdevs[port - 1] =
2423 mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
2424
2425 if (dev == iboe->netdevs[port - 1] &&
2426 (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2427 event == NETDEV_UP || event == NETDEV_CHANGE))
2428 update_qps_port = port;
2429
2430 }
2431 spin_unlock_bh(&iboe->lock);
2432
2433 if (update_qps_port > 0)
2434 mlx4_ib_update_qps(ibdev, dev, update_qps_port);
2435 }
2436
2437 static int mlx4_ib_netdev_event(struct notifier_block *this,
2438 unsigned long event, void *ptr)
2439 {
2440 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2441 struct mlx4_ib_dev *ibdev;
2442
2443 if (!net_eq(dev_net(dev), &init_net))
2444 return NOTIFY_DONE;
2445
2446 ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
2447 mlx4_ib_scan_netdevs(ibdev, dev, event);
2448
2449 return NOTIFY_DONE;
2450 }
2451
2452 static void init_pkeys(struct mlx4_ib_dev *ibdev)
2453 {
2454 int port;
2455 int slave;
2456 int i;
2457
2458 if (mlx4_is_master(ibdev->dev)) {
2459 for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2460 ++slave) {
2461 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2462 for (i = 0;
2463 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2464 ++i) {
2465 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2466 /* master has the identity virt2phys pkey mapping */
2467 (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2468 ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2469 mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2470 ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2471 }
2472 }
2473 }
2474 /* initialize pkey cache */
2475 for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2476 for (i = 0;
2477 i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2478 ++i)
2479 ibdev->pkeys.phys_pkey_cache[port-1][i] =
2480 (i) ? 0 : 0xFFFF;
2481 }
2482 }
2483 }
2484
2485 static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2486 {
2487 int i, j, eq = 0, total_eqs = 0;
2488
2489 ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2490 sizeof(ibdev->eq_table[0]), GFP_KERNEL);
2491 if (!ibdev->eq_table)
2492 return;
2493
2494 for (i = 1; i <= dev->caps.num_ports; i++) {
2495 for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2496 j++, total_eqs++) {
2497 if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2498 continue;
2499 ibdev->eq_table[eq] = total_eqs;
2500 if (!mlx4_assign_eq(dev, i,
2501 &ibdev->eq_table[eq]))
2502 eq++;
2503 else
2504 ibdev->eq_table[eq] = -1;
2505 }
2506 }
2507
2508 for (i = eq; i < dev->caps.num_comp_vectors;
2509 ibdev->eq_table[i++] = -1)
2510 ;
2511
2512 /* Advertise the new number of EQs to clients */
2513 ibdev->ib_dev.num_comp_vectors = eq;
2514 }
2515
2516 static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2517 {
2518 int i;
2519 int total_eqs = ibdev->ib_dev.num_comp_vectors;
2520
2521 /* no eqs were allocated */
2522 if (!ibdev->eq_table)
2523 return;
2524
2525 /* Reset the advertised EQ number */
2526 ibdev->ib_dev.num_comp_vectors = 0;
2527
2528 for (i = 0; i < total_eqs; i++)
2529 mlx4_release_eq(dev, ibdev->eq_table[i]);
2530
2531 kfree(ibdev->eq_table);
2532 ibdev->eq_table = NULL;
2533 }
2534
2535 static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2536 struct ib_port_immutable *immutable)
2537 {
2538 struct ib_port_attr attr;
2539 struct mlx4_ib_dev *mdev = to_mdev(ibdev);
2540 int err;
2541
2542 if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
2543 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2544 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2545 } else {
2546 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2547 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2548 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2549 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2550 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2551 immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
2552 if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
2553 RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
2554 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2555 }
2556
2557 err = ib_query_port(ibdev, port_num, &attr);
2558 if (err)
2559 return err;
2560
2561 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2562 immutable->gid_tbl_len = attr.gid_tbl_len;
2563
2564 return 0;
2565 }
2566
2567 static void get_fw_ver_str(struct ib_device *device, char *str,
2568 size_t str_len)
2569 {
2570 struct mlx4_ib_dev *dev =
2571 container_of(device, struct mlx4_ib_dev, ib_dev);
2572 snprintf(str, str_len, "%d.%d.%d",
2573 (int) (dev->dev->caps.fw_ver >> 32),
2574 (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2575 (int) dev->dev->caps.fw_ver & 0xffff);
2576 }
2577
2578 static void *mlx4_ib_add(struct mlx4_dev *dev)
2579 {
2580 struct mlx4_ib_dev *ibdev;
2581 int num_ports = 0;
2582 int i, j;
2583 int err;
2584 struct mlx4_ib_iboe *iboe;
2585 int ib_num_ports = 0;
2586 int num_req_counters;
2587 int allocated;
2588 u32 counter_index;
2589 struct counter_index *new_counter_index = NULL;
2590
2591 pr_info_once("%s", mlx4_ib_version);
2592
2593 num_ports = 0;
2594 mlx4_foreach_ib_transport_port(i, dev)
2595 num_ports++;
2596
2597 /* No point in registering a device with no ports... */
2598 if (num_ports == 0)
2599 return NULL;
2600
2601 ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
2602 if (!ibdev) {
2603 dev_err(&dev->persist->pdev->dev,
2604 "Device struct alloc failed\n");
2605 return NULL;
2606 }
2607
2608 iboe = &ibdev->iboe;
2609
2610 if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2611 goto err_dealloc;
2612
2613 if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2614 goto err_pd;
2615
2616 ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2617 PAGE_SIZE);
2618 if (!ibdev->uar_map)
2619 goto err_uar;
2620 MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
2621
2622 ibdev->dev = dev;
2623 ibdev->bond_next_port = 0;
2624
2625 strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
2626 ibdev->ib_dev.owner = THIS_MODULE;
2627 ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
2628 ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
2629 ibdev->num_ports = num_ports;
2630 ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2631 1 : ibdev->num_ports;
2632 ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
2633 ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
2634 ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
2635 ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
2636 ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
2637
2638 if (dev->caps.userspace_caps)
2639 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
2640 else
2641 ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2642
2643 ibdev->ib_dev.uverbs_cmd_mask =
2644 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2645 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2646 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2647 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2648 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2649 (1ull << IB_USER_VERBS_CMD_REG_MR) |
2650 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2651 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2652 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2653 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2654 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2655 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2656 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2657 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2658 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2659 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2660 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2661 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2662 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2663 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2664 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2665 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2666 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2667 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2668
2669 ibdev->ib_dev.query_device = mlx4_ib_query_device;
2670 ibdev->ib_dev.query_port = mlx4_ib_query_port;
2671 ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
2672 ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
2673 ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
2674 ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
2675 ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
2676 ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
2677 ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
2678 ibdev->ib_dev.mmap = mlx4_ib_mmap;
2679 ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
2680 ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
2681 ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
2682 ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
2683 ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
2684 ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
2685 ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
2686 ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
2687 ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
2688 ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
2689 ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
2690 ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
2691 ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
2692 ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
2693 ibdev->ib_dev.post_send = mlx4_ib_post_send;
2694 ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
2695 ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
2696 ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
2697 ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
2698 ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
2699 ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
2700 ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
2701 ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
2702 ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
2703 ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
2704 ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
2705 ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
2706 ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
2707 ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
2708 ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
2709 ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
2710 ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
2711 ibdev->ib_dev.get_dev_fw_str = get_fw_ver_str;
2712 ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
2713
2714 if (!mlx4_is_slave(ibdev->dev)) {
2715 ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
2716 ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
2717 ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
2718 ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
2719 }
2720
2721 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2722 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2723 ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
2724 ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
2725
2726 ibdev->ib_dev.uverbs_cmd_mask |=
2727 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2728 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2729 }
2730
2731 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2732 ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
2733 ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
2734 ibdev->ib_dev.uverbs_cmd_mask |=
2735 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2736 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2737 }
2738
2739 if (check_flow_steering_support(dev)) {
2740 ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
2741 ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
2742 ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
2743
2744 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2745 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2746 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2747 }
2748
2749 ibdev->ib_dev.uverbs_ex_cmd_mask |=
2750 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2751 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2752 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2753
2754 mlx4_ib_alloc_eqs(dev, ibdev);
2755
2756 spin_lock_init(&iboe->lock);
2757
2758 if (init_node_data(ibdev))
2759 goto err_map;
2760 mlx4_init_sl2vl_tbl(ibdev);
2761
2762 for (i = 0; i < ibdev->num_ports; ++i) {
2763 mutex_init(&ibdev->counters_table[i].mutex);
2764 INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2765 }
2766
2767 num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2768 for (i = 0; i < num_req_counters; ++i) {
2769 mutex_init(&ibdev->qp1_proxy_lock[i]);
2770 allocated = 0;
2771 if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2772 IB_LINK_LAYER_ETHERNET) {
2773 err = mlx4_counter_alloc(ibdev->dev, &counter_index);
2774 /* if failed to allocate a new counter, use default */
2775 if (err)
2776 counter_index =
2777 mlx4_get_default_counter_index(dev,
2778 i + 1);
2779 else
2780 allocated = 1;
2781 } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2782 counter_index = mlx4_get_default_counter_index(dev,
2783 i + 1);
2784 }
2785 new_counter_index = kmalloc(sizeof(*new_counter_index),
2786 GFP_KERNEL);
2787 if (!new_counter_index) {
2788 if (allocated)
2789 mlx4_counter_free(ibdev->dev, counter_index);
2790 goto err_counter;
2791 }
2792 new_counter_index->index = counter_index;
2793 new_counter_index->allocated = allocated;
2794 list_add_tail(&new_counter_index->list,
2795 &ibdev->counters_table[i].counters_list);
2796 ibdev->counters_table[i].default_counter = counter_index;
2797 pr_info("counter index %d for port %d allocated %d\n",
2798 counter_index, i + 1, allocated);
2799 }
2800 if (mlx4_is_bonded(dev))
2801 for (i = 1; i < ibdev->num_ports ; ++i) {
2802 new_counter_index =
2803 kmalloc(sizeof(struct counter_index),
2804 GFP_KERNEL);
2805 if (!new_counter_index)
2806 goto err_counter;
2807 new_counter_index->index = counter_index;
2808 new_counter_index->allocated = 0;
2809 list_add_tail(&new_counter_index->list,
2810 &ibdev->counters_table[i].counters_list);
2811 ibdev->counters_table[i].default_counter =
2812 counter_index;
2813 }
2814
2815 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2816 ib_num_ports++;
2817
2818 spin_lock_init(&ibdev->sm_lock);
2819 mutex_init(&ibdev->cap_mask_mutex);
2820 INIT_LIST_HEAD(&ibdev->qp_list);
2821 spin_lock_init(&ibdev->reset_flow_resource_lock);
2822
2823 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2824 ib_num_ports) {
2825 ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2826 err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2827 MLX4_IB_UC_STEER_QPN_ALIGN,
2828 &ibdev->steer_qpn_base, 0);
2829 if (err)
2830 goto err_counter;
2831
2832 ibdev->ib_uc_qpns_bitmap =
2833 kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
2834 sizeof(long),
2835 GFP_KERNEL);
2836 if (!ibdev->ib_uc_qpns_bitmap)
2837 goto err_steer_qp_release;
2838
2839 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2840 bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2841 ibdev->steer_qpn_count);
2842 err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2843 dev, ibdev->steer_qpn_base,
2844 ibdev->steer_qpn_base +
2845 ibdev->steer_qpn_count - 1);
2846 if (err)
2847 goto err_steer_free_bitmap;
2848 } else {
2849 bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2850 ibdev->steer_qpn_count);
2851 }
2852 }
2853
2854 for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2855 atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2856
2857 if (mlx4_ib_alloc_diag_counters(ibdev))
2858 goto err_steer_free_bitmap;
2859
2860 if (ib_register_device(&ibdev->ib_dev, NULL))
2861 goto err_diag_counters;
2862
2863 if (mlx4_ib_mad_init(ibdev))
2864 goto err_reg;
2865
2866 if (mlx4_ib_init_sriov(ibdev))
2867 goto err_mad;
2868
2869 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE ||
2870 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2871 if (!iboe->nb.notifier_call) {
2872 iboe->nb.notifier_call = mlx4_ib_netdev_event;
2873 err = register_netdevice_notifier(&iboe->nb);
2874 if (err) {
2875 iboe->nb.notifier_call = NULL;
2876 goto err_notif;
2877 }
2878 }
2879 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2880 err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2881 if (err) {
2882 goto err_notif;
2883 }
2884 }
2885 }
2886
2887 for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
2888 if (device_create_file(&ibdev->ib_dev.dev,
2889 mlx4_class_attributes[j]))
2890 goto err_notif;
2891 }
2892
2893 ibdev->ib_active = true;
2894 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2895 devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2896 &ibdev->ib_dev);
2897
2898 if (mlx4_is_mfunc(ibdev->dev))
2899 init_pkeys(ibdev);
2900
2901 /* create paravirt contexts for any VFs which are active */
2902 if (mlx4_is_master(ibdev->dev)) {
2903 for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2904 if (j == mlx4_master_func_num(ibdev->dev))
2905 continue;
2906 if (mlx4_is_slave_active(ibdev->dev, j))
2907 do_slave_init(ibdev, j, 1);
2908 }
2909 }
2910 return ibdev;
2911
2912 err_notif:
2913 if (ibdev->iboe.nb.notifier_call) {
2914 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2915 pr_warn("failure unregistering notifier\n");
2916 ibdev->iboe.nb.notifier_call = NULL;
2917 }
2918 flush_workqueue(wq);
2919
2920 mlx4_ib_close_sriov(ibdev);
2921
2922 err_mad:
2923 mlx4_ib_mad_cleanup(ibdev);
2924
2925 err_reg:
2926 ib_unregister_device(&ibdev->ib_dev);
2927
2928 err_diag_counters:
2929 mlx4_ib_diag_cleanup(ibdev);
2930
2931 err_steer_free_bitmap:
2932 kfree(ibdev->ib_uc_qpns_bitmap);
2933
2934 err_steer_qp_release:
2935 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
2936 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2937 ibdev->steer_qpn_count);
2938 err_counter:
2939 for (i = 0; i < ibdev->num_ports; ++i)
2940 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2941
2942 err_map:
2943 iounmap(ibdev->uar_map);
2944
2945 err_uar:
2946 mlx4_uar_free(dev, &ibdev->priv_uar);
2947
2948 err_pd:
2949 mlx4_pd_free(dev, ibdev->priv_pdn);
2950
2951 err_dealloc:
2952 ib_dealloc_device(&ibdev->ib_dev);
2953
2954 return NULL;
2955 }
2956
2957 int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2958 {
2959 int offset;
2960
2961 WARN_ON(!dev->ib_uc_qpns_bitmap);
2962
2963 offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2964 dev->steer_qpn_count,
2965 get_count_order(count));
2966 if (offset < 0)
2967 return offset;
2968
2969 *qpn = dev->steer_qpn_base + offset;
2970 return 0;
2971 }
2972
2973 void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2974 {
2975 if (!qpn ||
2976 dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2977 return;
2978
2979 BUG_ON(qpn < dev->steer_qpn_base);
2980
2981 bitmap_release_region(dev->ib_uc_qpns_bitmap,
2982 qpn - dev->steer_qpn_base,
2983 get_count_order(count));
2984 }
2985
2986 int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2987 int is_attach)
2988 {
2989 int err;
2990 size_t flow_size;
2991 struct ib_flow_attr *flow = NULL;
2992 struct ib_flow_spec_ib *ib_spec;
2993
2994 if (is_attach) {
2995 flow_size = sizeof(struct ib_flow_attr) +
2996 sizeof(struct ib_flow_spec_ib);
2997 flow = kzalloc(flow_size, GFP_KERNEL);
2998 if (!flow)
2999 return -ENOMEM;
3000 flow->port = mqp->port;
3001 flow->num_of_specs = 1;
3002 flow->size = flow_size;
3003 ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
3004 ib_spec->type = IB_FLOW_SPEC_IB;
3005 ib_spec->size = sizeof(struct ib_flow_spec_ib);
3006 /* Add an empty rule for IB L2 */
3007 memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
3008
3009 err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
3010 IB_FLOW_DOMAIN_NIC,
3011 MLX4_FS_REGULAR,
3012 &mqp->reg_id);
3013 } else {
3014 err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
3015 }
3016 kfree(flow);
3017 return err;
3018 }
3019
3020 static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
3021 {
3022 struct mlx4_ib_dev *ibdev = ibdev_ptr;
3023 int p;
3024 int i;
3025
3026 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3027 devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
3028 ibdev->ib_active = false;
3029 flush_workqueue(wq);
3030
3031 mlx4_ib_close_sriov(ibdev);
3032 mlx4_ib_mad_cleanup(ibdev);
3033 ib_unregister_device(&ibdev->ib_dev);
3034 mlx4_ib_diag_cleanup(ibdev);
3035 if (ibdev->iboe.nb.notifier_call) {
3036 if (unregister_netdevice_notifier(&ibdev->iboe.nb))
3037 pr_warn("failure unregistering notifier\n");
3038 ibdev->iboe.nb.notifier_call = NULL;
3039 }
3040
3041 if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED) {
3042 mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3043 ibdev->steer_qpn_count);
3044 kfree(ibdev->ib_uc_qpns_bitmap);
3045 }
3046
3047 iounmap(ibdev->uar_map);
3048 for (p = 0; p < ibdev->num_ports; ++p)
3049 mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3050
3051 mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
3052 mlx4_CLOSE_PORT(dev, p);
3053
3054 mlx4_ib_free_eqs(dev, ibdev);
3055
3056 mlx4_uar_free(dev, &ibdev->priv_uar);
3057 mlx4_pd_free(dev, ibdev->priv_pdn);
3058 ib_dealloc_device(&ibdev->ib_dev);
3059 }
3060
3061 static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3062 {
3063 struct mlx4_ib_demux_work **dm = NULL;
3064 struct mlx4_dev *dev = ibdev->dev;
3065 int i;
3066 unsigned long flags;
3067 struct mlx4_active_ports actv_ports;
3068 unsigned int ports;
3069 unsigned int first_port;
3070
3071 if (!mlx4_is_master(dev))
3072 return;
3073
3074 actv_ports = mlx4_get_active_ports(dev, slave);
3075 ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3076 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3077
3078 dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3079 if (!dm)
3080 return;
3081
3082 for (i = 0; i < ports; i++) {
3083 dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3084 if (!dm[i]) {
3085 while (--i >= 0)
3086 kfree(dm[i]);
3087 goto out;
3088 }
3089 INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
3090 dm[i]->port = first_port + i + 1;
3091 dm[i]->slave = slave;
3092 dm[i]->do_init = do_init;
3093 dm[i]->dev = ibdev;
3094 }
3095 /* initialize or tear down tunnel QPs for the slave */
3096 spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3097 if (!ibdev->sriov.is_going_down) {
3098 for (i = 0; i < ports; i++)
3099 queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3100 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3101 } else {
3102 spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3103 for (i = 0; i < ports; i++)
3104 kfree(dm[i]);
3105 }
3106 out:
3107 kfree(dm);
3108 return;
3109 }
3110
3111 static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3112 {
3113 struct mlx4_ib_qp *mqp;
3114 unsigned long flags_qp;
3115 unsigned long flags_cq;
3116 struct mlx4_ib_cq *send_mcq, *recv_mcq;
3117 struct list_head cq_notify_list;
3118 struct mlx4_cq *mcq;
3119 unsigned long flags;
3120
3121 pr_warn("mlx4_ib_handle_catas_error was started\n");
3122 INIT_LIST_HEAD(&cq_notify_list);
3123
3124 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3125 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3126
3127 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3128 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3129 if (mqp->sq.tail != mqp->sq.head) {
3130 send_mcq = to_mcq(mqp->ibqp.send_cq);
3131 spin_lock_irqsave(&send_mcq->lock, flags_cq);
3132 if (send_mcq->mcq.comp &&
3133 mqp->ibqp.send_cq->comp_handler) {
3134 if (!send_mcq->mcq.reset_notify_added) {
3135 send_mcq->mcq.reset_notify_added = 1;
3136 list_add_tail(&send_mcq->mcq.reset_notify,
3137 &cq_notify_list);
3138 }
3139 }
3140 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3141 }
3142 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3143 /* Now, handle the QP's receive queue */
3144 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3145 /* no handling is needed for SRQ */
3146 if (!mqp->ibqp.srq) {
3147 if (mqp->rq.tail != mqp->rq.head) {
3148 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3149 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3150 if (recv_mcq->mcq.comp &&
3151 mqp->ibqp.recv_cq->comp_handler) {
3152 if (!recv_mcq->mcq.reset_notify_added) {
3153 recv_mcq->mcq.reset_notify_added = 1;
3154 list_add_tail(&recv_mcq->mcq.reset_notify,
3155 &cq_notify_list);
3156 }
3157 }
3158 spin_unlock_irqrestore(&recv_mcq->lock,
3159 flags_cq);
3160 }
3161 }
3162 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3163 }
3164
3165 list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3166 mcq->comp(mcq);
3167 }
3168 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3169 pr_warn("mlx4_ib_handle_catas_error ended\n");
3170 }
3171
3172 static void handle_bonded_port_state_event(struct work_struct *work)
3173 {
3174 struct ib_event_work *ew =
3175 container_of(work, struct ib_event_work, work);
3176 struct mlx4_ib_dev *ibdev = ew->ib_dev;
3177 enum ib_port_state bonded_port_state = IB_PORT_NOP;
3178 int i;
3179 struct ib_event ibev;
3180
3181 kfree(ew);
3182 spin_lock_bh(&ibdev->iboe.lock);
3183 for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3184 struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
3185 enum ib_port_state curr_port_state;
3186
3187 if (!curr_netdev)
3188 continue;
3189
3190 curr_port_state =
3191 (netif_running(curr_netdev) &&
3192 netif_carrier_ok(curr_netdev)) ?
3193 IB_PORT_ACTIVE : IB_PORT_DOWN;
3194
3195 bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3196 curr_port_state : IB_PORT_ACTIVE;
3197 }
3198 spin_unlock_bh(&ibdev->iboe.lock);
3199
3200 ibev.device = &ibdev->ib_dev;
3201 ibev.element.port_num = 1;
3202 ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3203 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3204
3205 ib_dispatch_event(&ibev);
3206 }
3207
3208 void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3209 {
3210 u64 sl2vl;
3211 int err;
3212
3213 err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3214 if (err) {
3215 pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3216 port, err);
3217 sl2vl = 0;
3218 }
3219 atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3220 }
3221
3222 static void ib_sl2vl_update_work(struct work_struct *work)
3223 {
3224 struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3225 struct mlx4_ib_dev *mdev = ew->ib_dev;
3226 int port = ew->port;
3227
3228 mlx4_ib_sl2vl_update(mdev, port);
3229
3230 kfree(ew);
3231 }
3232
3233 void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3234 int port)
3235 {
3236 struct ib_event_work *ew;
3237
3238 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3239 if (ew) {
3240 INIT_WORK(&ew->work, ib_sl2vl_update_work);
3241 ew->port = port;
3242 ew->ib_dev = ibdev;
3243 queue_work(wq, &ew->work);
3244 }
3245 }
3246
3247 static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3248 enum mlx4_dev_event event, unsigned long param)
3249 {
3250 struct ib_event ibev;
3251 struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
3252 struct mlx4_eqe *eqe = NULL;
3253 struct ib_event_work *ew;
3254 int p = 0;
3255
3256 if (mlx4_is_bonded(dev) &&
3257 ((event == MLX4_DEV_EVENT_PORT_UP) ||
3258 (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3259 ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3260 if (!ew)
3261 return;
3262 INIT_WORK(&ew->work, handle_bonded_port_state_event);
3263 ew->ib_dev = ibdev;
3264 queue_work(wq, &ew->work);
3265 return;
3266 }
3267
3268 if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3269 eqe = (struct mlx4_eqe *)param;
3270 else
3271 p = (int) param;
3272
3273 switch (event) {
3274 case MLX4_DEV_EVENT_PORT_UP:
3275 if (p > ibdev->num_ports)
3276 return;
3277 if (!mlx4_is_slave(dev) &&
3278 rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3279 IB_LINK_LAYER_INFINIBAND) {
3280 if (mlx4_is_master(dev))
3281 mlx4_ib_invalidate_all_guid_record(ibdev, p);
3282 if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3283 !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3284 mlx4_sched_ib_sl2vl_update_work(ibdev, p);
3285 }
3286 ibev.event = IB_EVENT_PORT_ACTIVE;
3287 break;
3288
3289 case MLX4_DEV_EVENT_PORT_DOWN:
3290 if (p > ibdev->num_ports)
3291 return;
3292 ibev.event = IB_EVENT_PORT_ERR;
3293 break;
3294
3295 case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3296 ibdev->ib_active = false;
3297 ibev.event = IB_EVENT_DEVICE_FATAL;
3298 mlx4_ib_handle_catas_error(ibdev);
3299 break;
3300
3301 case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3302 ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3303 if (!ew)
3304 break;
3305
3306 INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3307 memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3308 ew->ib_dev = ibdev;
3309 /* need to queue only for port owner, which uses GEN_EQE */
3310 if (mlx4_is_master(dev))
3311 queue_work(wq, &ew->work);
3312 else
3313 handle_port_mgmt_change_event(&ew->work);
3314 return;
3315
3316 case MLX4_DEV_EVENT_SLAVE_INIT:
3317 /* here, p is the slave id */
3318 do_slave_init(ibdev, p, 1);
3319 if (mlx4_is_master(dev)) {
3320 int i;
3321
3322 for (i = 1; i <= ibdev->num_ports; i++) {
3323 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3324 == IB_LINK_LAYER_INFINIBAND)
3325 mlx4_ib_slave_alias_guid_event(ibdev,
3326 p, i,
3327 1);
3328 }
3329 }
3330 return;
3331
3332 case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
3333 if (mlx4_is_master(dev)) {
3334 int i;
3335
3336 for (i = 1; i <= ibdev->num_ports; i++) {
3337 if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3338 == IB_LINK_LAYER_INFINIBAND)
3339 mlx4_ib_slave_alias_guid_event(ibdev,
3340 p, i,
3341 0);
3342 }
3343 }
3344 /* here, p is the slave id */
3345 do_slave_init(ibdev, p, 0);
3346 return;
3347
3348 default:
3349 return;
3350 }
3351
3352 ibev.device = ibdev_ptr;
3353 ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
3354
3355 ib_dispatch_event(&ibev);
3356 }
3357
3358 static struct mlx4_interface mlx4_ib_interface = {
3359 .add = mlx4_ib_add,
3360 .remove = mlx4_ib_remove,
3361 .event = mlx4_ib_event,
3362 .protocol = MLX4_PROT_IB_IPV6,
3363 .flags = MLX4_INTFF_BONDING
3364 };
3365
3366 static int __init mlx4_ib_init(void)
3367 {
3368 int err;
3369
3370 wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
3371 if (!wq)
3372 return -ENOMEM;
3373
3374 err = mlx4_ib_mcg_init();
3375 if (err)
3376 goto clean_wq;
3377
3378 err = mlx4_register_interface(&mlx4_ib_interface);
3379 if (err)
3380 goto clean_mcg;
3381
3382 return 0;
3383
3384 clean_mcg:
3385 mlx4_ib_mcg_destroy();
3386
3387 clean_wq:
3388 destroy_workqueue(wq);
3389 return err;
3390 }
3391
3392 static void __exit mlx4_ib_cleanup(void)
3393 {
3394 mlx4_unregister_interface(&mlx4_ib_interface);
3395 mlx4_ib_mcg_destroy();
3396 destroy_workqueue(wq);
3397 }
3398
3399 module_init(mlx4_ib_init);
3400 module_exit(mlx4_ib_cleanup);
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