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IB/mlx5: Remove deprecated module parameter
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
41 #include <asm/pat.h>
42 #endif
43 #include <linux/sched.h>
44 #include <linux/delay.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <linux/list.h>
51 #include <rdma/ib_smi.h>
52 #include <rdma/ib_umem.h>
53 #include <linux/in.h>
54 #include <linux/etherdevice.h>
55 #include <linux/mlx5/fs.h>
56 #include "mlx5_ib.h"
57
58 #define DRIVER_NAME "mlx5_ib"
59 #define DRIVER_VERSION "2.2-1"
60 #define DRIVER_RELDATE "Feb 2014"
61
62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_VERSION(DRIVER_VERSION);
66
67 static char mlx5_version[] =
68 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
69 DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
70
71 enum {
72 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
73 };
74
75 static enum rdma_link_layer
76 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
77 {
78 switch (port_type_cap) {
79 case MLX5_CAP_PORT_TYPE_IB:
80 return IB_LINK_LAYER_INFINIBAND;
81 case MLX5_CAP_PORT_TYPE_ETH:
82 return IB_LINK_LAYER_ETHERNET;
83 default:
84 return IB_LINK_LAYER_UNSPECIFIED;
85 }
86 }
87
88 static enum rdma_link_layer
89 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
90 {
91 struct mlx5_ib_dev *dev = to_mdev(device);
92 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
93
94 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
95 }
96
97 static int mlx5_netdev_event(struct notifier_block *this,
98 unsigned long event, void *ptr)
99 {
100 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
101 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
102 roce.nb);
103
104 switch (event) {
105 case NETDEV_REGISTER:
106 case NETDEV_UNREGISTER:
107 write_lock(&ibdev->roce.netdev_lock);
108 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
109 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
110 NULL : ndev;
111 write_unlock(&ibdev->roce.netdev_lock);
112 break;
113
114 case NETDEV_UP:
115 case NETDEV_DOWN: {
116 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
117 struct net_device *upper = NULL;
118
119 if (lag_ndev) {
120 upper = netdev_master_upper_dev_get(lag_ndev);
121 dev_put(lag_ndev);
122 }
123
124 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
125 && ibdev->ib_active) {
126 struct ib_event ibev = { };
127
128 ibev.device = &ibdev->ib_dev;
129 ibev.event = (event == NETDEV_UP) ?
130 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
131 ibev.element.port_num = 1;
132 ib_dispatch_event(&ibev);
133 }
134 break;
135 }
136
137 default:
138 break;
139 }
140
141 return NOTIFY_DONE;
142 }
143
144 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
145 u8 port_num)
146 {
147 struct mlx5_ib_dev *ibdev = to_mdev(device);
148 struct net_device *ndev;
149
150 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
151 if (ndev)
152 return ndev;
153
154 /* Ensure ndev does not disappear before we invoke dev_hold()
155 */
156 read_lock(&ibdev->roce.netdev_lock);
157 ndev = ibdev->roce.netdev;
158 if (ndev)
159 dev_hold(ndev);
160 read_unlock(&ibdev->roce.netdev_lock);
161
162 return ndev;
163 }
164
165 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
166 struct ib_port_attr *props)
167 {
168 struct mlx5_ib_dev *dev = to_mdev(device);
169 struct net_device *ndev, *upper;
170 enum ib_mtu ndev_ib_mtu;
171 u16 qkey_viol_cntr;
172
173 memset(props, 0, sizeof(*props));
174
175 props->port_cap_flags |= IB_PORT_CM_SUP;
176 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
177
178 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
179 roce_address_table_size);
180 props->max_mtu = IB_MTU_4096;
181 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
182 props->pkey_tbl_len = 1;
183 props->state = IB_PORT_DOWN;
184 props->phys_state = 3;
185
186 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
187 props->qkey_viol_cntr = qkey_viol_cntr;
188
189 ndev = mlx5_ib_get_netdev(device, port_num);
190 if (!ndev)
191 return 0;
192
193 if (mlx5_lag_is_active(dev->mdev)) {
194 rcu_read_lock();
195 upper = netdev_master_upper_dev_get_rcu(ndev);
196 if (upper) {
197 dev_put(ndev);
198 ndev = upper;
199 dev_hold(ndev);
200 }
201 rcu_read_unlock();
202 }
203
204 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
205 props->state = IB_PORT_ACTIVE;
206 props->phys_state = 5;
207 }
208
209 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
210
211 dev_put(ndev);
212
213 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
214
215 props->active_width = IB_WIDTH_4X; /* TODO */
216 props->active_speed = IB_SPEED_QDR; /* TODO */
217
218 return 0;
219 }
220
221 static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid,
222 const struct ib_gid_attr *attr,
223 void *mlx5_addr)
224 {
225 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
226 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
227 source_l3_address);
228 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr,
229 source_mac_47_32);
230
231 if (!gid)
232 return;
233
234 ether_addr_copy(mlx5_addr_mac, attr->ndev->dev_addr);
235
236 if (is_vlan_dev(attr->ndev)) {
237 MLX5_SET_RA(mlx5_addr, vlan_valid, 1);
238 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_dev_vlan_id(attr->ndev));
239 }
240
241 switch (attr->gid_type) {
242 case IB_GID_TYPE_IB:
243 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1);
244 break;
245 case IB_GID_TYPE_ROCE_UDP_ENCAP:
246 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2);
247 break;
248
249 default:
250 WARN_ON(true);
251 }
252
253 if (attr->gid_type != IB_GID_TYPE_IB) {
254 if (ipv6_addr_v4mapped((void *)gid))
255 MLX5_SET_RA(mlx5_addr, roce_l3_type,
256 MLX5_ROCE_L3_TYPE_IPV4);
257 else
258 MLX5_SET_RA(mlx5_addr, roce_l3_type,
259 MLX5_ROCE_L3_TYPE_IPV6);
260 }
261
262 if ((attr->gid_type == IB_GID_TYPE_IB) ||
263 !ipv6_addr_v4mapped((void *)gid))
264 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid));
265 else
266 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4);
267 }
268
269 static int set_roce_addr(struct ib_device *device, u8 port_num,
270 unsigned int index,
271 const union ib_gid *gid,
272 const struct ib_gid_attr *attr)
273 {
274 struct mlx5_ib_dev *dev = to_mdev(device);
275 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0};
276 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0};
277 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address);
278 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num);
279
280 if (ll != IB_LINK_LAYER_ETHERNET)
281 return -EINVAL;
282
283 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr);
284
285 MLX5_SET(set_roce_address_in, in, roce_address_index, index);
286 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS);
287 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out));
288 }
289
290 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
291 unsigned int index, const union ib_gid *gid,
292 const struct ib_gid_attr *attr,
293 __always_unused void **context)
294 {
295 return set_roce_addr(device, port_num, index, gid, attr);
296 }
297
298 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
299 unsigned int index, __always_unused void **context)
300 {
301 return set_roce_addr(device, port_num, index, NULL, NULL);
302 }
303
304 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
305 int index)
306 {
307 struct ib_gid_attr attr;
308 union ib_gid gid;
309
310 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
311 return 0;
312
313 if (!attr.ndev)
314 return 0;
315
316 dev_put(attr.ndev);
317
318 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
319 return 0;
320
321 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
322 }
323
324 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
325 int index, enum ib_gid_type *gid_type)
326 {
327 struct ib_gid_attr attr;
328 union ib_gid gid;
329 int ret;
330
331 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
332 if (ret)
333 return ret;
334
335 if (!attr.ndev)
336 return -ENODEV;
337
338 dev_put(attr.ndev);
339
340 *gid_type = attr.gid_type;
341
342 return 0;
343 }
344
345 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
346 {
347 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
348 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
349 return 0;
350 }
351
352 enum {
353 MLX5_VPORT_ACCESS_METHOD_MAD,
354 MLX5_VPORT_ACCESS_METHOD_HCA,
355 MLX5_VPORT_ACCESS_METHOD_NIC,
356 };
357
358 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
359 {
360 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
361 return MLX5_VPORT_ACCESS_METHOD_MAD;
362
363 if (mlx5_ib_port_link_layer(ibdev, 1) ==
364 IB_LINK_LAYER_ETHERNET)
365 return MLX5_VPORT_ACCESS_METHOD_NIC;
366
367 return MLX5_VPORT_ACCESS_METHOD_HCA;
368 }
369
370 static void get_atomic_caps(struct mlx5_ib_dev *dev,
371 struct ib_device_attr *props)
372 {
373 u8 tmp;
374 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
375 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
376 u8 atomic_req_8B_endianness_mode =
377 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode);
378
379 /* Check if HW supports 8 bytes standard atomic operations and capable
380 * of host endianness respond
381 */
382 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
383 if (((atomic_operations & tmp) == tmp) &&
384 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
385 (atomic_req_8B_endianness_mode)) {
386 props->atomic_cap = IB_ATOMIC_HCA;
387 } else {
388 props->atomic_cap = IB_ATOMIC_NONE;
389 }
390 }
391
392 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
393 __be64 *sys_image_guid)
394 {
395 struct mlx5_ib_dev *dev = to_mdev(ibdev);
396 struct mlx5_core_dev *mdev = dev->mdev;
397 u64 tmp;
398 int err;
399
400 switch (mlx5_get_vport_access_method(ibdev)) {
401 case MLX5_VPORT_ACCESS_METHOD_MAD:
402 return mlx5_query_mad_ifc_system_image_guid(ibdev,
403 sys_image_guid);
404
405 case MLX5_VPORT_ACCESS_METHOD_HCA:
406 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
407 break;
408
409 case MLX5_VPORT_ACCESS_METHOD_NIC:
410 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
411 break;
412
413 default:
414 return -EINVAL;
415 }
416
417 if (!err)
418 *sys_image_guid = cpu_to_be64(tmp);
419
420 return err;
421
422 }
423
424 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
425 u16 *max_pkeys)
426 {
427 struct mlx5_ib_dev *dev = to_mdev(ibdev);
428 struct mlx5_core_dev *mdev = dev->mdev;
429
430 switch (mlx5_get_vport_access_method(ibdev)) {
431 case MLX5_VPORT_ACCESS_METHOD_MAD:
432 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
433
434 case MLX5_VPORT_ACCESS_METHOD_HCA:
435 case MLX5_VPORT_ACCESS_METHOD_NIC:
436 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
437 pkey_table_size));
438 return 0;
439
440 default:
441 return -EINVAL;
442 }
443 }
444
445 static int mlx5_query_vendor_id(struct ib_device *ibdev,
446 u32 *vendor_id)
447 {
448 struct mlx5_ib_dev *dev = to_mdev(ibdev);
449
450 switch (mlx5_get_vport_access_method(ibdev)) {
451 case MLX5_VPORT_ACCESS_METHOD_MAD:
452 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
453
454 case MLX5_VPORT_ACCESS_METHOD_HCA:
455 case MLX5_VPORT_ACCESS_METHOD_NIC:
456 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
457
458 default:
459 return -EINVAL;
460 }
461 }
462
463 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
464 __be64 *node_guid)
465 {
466 u64 tmp;
467 int err;
468
469 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
470 case MLX5_VPORT_ACCESS_METHOD_MAD:
471 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
472
473 case MLX5_VPORT_ACCESS_METHOD_HCA:
474 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
475 break;
476
477 case MLX5_VPORT_ACCESS_METHOD_NIC:
478 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
479 break;
480
481 default:
482 return -EINVAL;
483 }
484
485 if (!err)
486 *node_guid = cpu_to_be64(tmp);
487
488 return err;
489 }
490
491 struct mlx5_reg_node_desc {
492 u8 desc[IB_DEVICE_NODE_DESC_MAX];
493 };
494
495 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
496 {
497 struct mlx5_reg_node_desc in;
498
499 if (mlx5_use_mad_ifc(dev))
500 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
501
502 memset(&in, 0, sizeof(in));
503
504 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
505 sizeof(struct mlx5_reg_node_desc),
506 MLX5_REG_NODE_DESC, 0, 0);
507 }
508
509 static int mlx5_ib_query_device(struct ib_device *ibdev,
510 struct ib_device_attr *props,
511 struct ib_udata *uhw)
512 {
513 struct mlx5_ib_dev *dev = to_mdev(ibdev);
514 struct mlx5_core_dev *mdev = dev->mdev;
515 int err = -ENOMEM;
516 int max_sq_desc;
517 int max_rq_sg;
518 int max_sq_sg;
519 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
520 struct mlx5_ib_query_device_resp resp = {};
521 size_t resp_len;
522 u64 max_tso;
523
524 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
525 if (uhw->outlen && uhw->outlen < resp_len)
526 return -EINVAL;
527 else
528 resp.response_length = resp_len;
529
530 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
531 return -EINVAL;
532
533 memset(props, 0, sizeof(*props));
534 err = mlx5_query_system_image_guid(ibdev,
535 &props->sys_image_guid);
536 if (err)
537 return err;
538
539 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
540 if (err)
541 return err;
542
543 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
544 if (err)
545 return err;
546
547 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
548 (fw_rev_min(dev->mdev) << 16) |
549 fw_rev_sub(dev->mdev);
550 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
551 IB_DEVICE_PORT_ACTIVE_EVENT |
552 IB_DEVICE_SYS_IMAGE_GUID |
553 IB_DEVICE_RC_RNR_NAK_GEN;
554
555 if (MLX5_CAP_GEN(mdev, pkv))
556 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
557 if (MLX5_CAP_GEN(mdev, qkv))
558 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
559 if (MLX5_CAP_GEN(mdev, apm))
560 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
561 if (MLX5_CAP_GEN(mdev, xrc))
562 props->device_cap_flags |= IB_DEVICE_XRC;
563 if (MLX5_CAP_GEN(mdev, imaicl)) {
564 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
565 IB_DEVICE_MEM_WINDOW_TYPE_2B;
566 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
567 /* We support 'Gappy' memory registration too */
568 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
569 }
570 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
571 if (MLX5_CAP_GEN(mdev, sho)) {
572 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
573 /* At this stage no support for signature handover */
574 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
575 IB_PROT_T10DIF_TYPE_2 |
576 IB_PROT_T10DIF_TYPE_3;
577 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
578 IB_GUARD_T10DIF_CSUM;
579 }
580 if (MLX5_CAP_GEN(mdev, block_lb_mc))
581 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
582
583 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
584 if (MLX5_CAP_ETH(mdev, csum_cap))
585 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
586
587 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
588 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
589 if (max_tso) {
590 resp.tso_caps.max_tso = 1 << max_tso;
591 resp.tso_caps.supported_qpts |=
592 1 << IB_QPT_RAW_PACKET;
593 resp.response_length += sizeof(resp.tso_caps);
594 }
595 }
596
597 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
598 resp.rss_caps.rx_hash_function =
599 MLX5_RX_HASH_FUNC_TOEPLITZ;
600 resp.rss_caps.rx_hash_fields_mask =
601 MLX5_RX_HASH_SRC_IPV4 |
602 MLX5_RX_HASH_DST_IPV4 |
603 MLX5_RX_HASH_SRC_IPV6 |
604 MLX5_RX_HASH_DST_IPV6 |
605 MLX5_RX_HASH_SRC_PORT_TCP |
606 MLX5_RX_HASH_DST_PORT_TCP |
607 MLX5_RX_HASH_SRC_PORT_UDP |
608 MLX5_RX_HASH_DST_PORT_UDP;
609 resp.response_length += sizeof(resp.rss_caps);
610 }
611 } else {
612 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
613 resp.response_length += sizeof(resp.tso_caps);
614 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
615 resp.response_length += sizeof(resp.rss_caps);
616 }
617
618 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
619 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
620 props->device_cap_flags |= IB_DEVICE_UD_TSO;
621 }
622
623 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
624 MLX5_CAP_ETH(dev->mdev, scatter_fcs))
625 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
626
627 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
628 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
629
630 props->vendor_part_id = mdev->pdev->device;
631 props->hw_ver = mdev->pdev->revision;
632
633 props->max_mr_size = ~0ull;
634 props->page_size_cap = ~(min_page_size - 1);
635 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
636 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
637 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
638 sizeof(struct mlx5_wqe_data_seg);
639 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
640 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
641 sizeof(struct mlx5_wqe_raddr_seg)) /
642 sizeof(struct mlx5_wqe_data_seg);
643 props->max_sge = min(max_rq_sg, max_sq_sg);
644 props->max_sge_rd = MLX5_MAX_SGE_RD;
645 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
646 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
647 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
648 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
649 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
650 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
651 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
652 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
653 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
654 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
655 props->max_srq_sge = max_rq_sg - 1;
656 props->max_fast_reg_page_list_len =
657 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
658 get_atomic_caps(dev, props);
659 props->masked_atomic_cap = IB_ATOMIC_NONE;
660 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
661 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
662 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
663 props->max_mcast_grp;
664 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
665 props->max_ah = INT_MAX;
666 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
667 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
668
669 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
670 if (MLX5_CAP_GEN(mdev, pg))
671 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
672 props->odp_caps = dev->odp_caps;
673 #endif
674
675 if (MLX5_CAP_GEN(mdev, cd))
676 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
677
678 if (!mlx5_core_is_pf(mdev))
679 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
680
681 if (mlx5_ib_port_link_layer(ibdev, 1) ==
682 IB_LINK_LAYER_ETHERNET) {
683 props->rss_caps.max_rwq_indirection_tables =
684 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
685 props->rss_caps.max_rwq_indirection_table_size =
686 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
687 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
688 props->max_wq_type_rq =
689 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
690 }
691
692 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
693 resp.cqe_comp_caps.max_num =
694 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
695 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
696 resp.cqe_comp_caps.supported_format =
697 MLX5_IB_CQE_RES_FORMAT_HASH |
698 MLX5_IB_CQE_RES_FORMAT_CSUM;
699 resp.response_length += sizeof(resp.cqe_comp_caps);
700 }
701
702 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
703 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
704 MLX5_CAP_GEN(mdev, qos)) {
705 resp.packet_pacing_caps.qp_rate_limit_max =
706 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
707 resp.packet_pacing_caps.qp_rate_limit_min =
708 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
709 resp.packet_pacing_caps.supported_qpts |=
710 1 << IB_QPT_RAW_PACKET;
711 }
712 resp.response_length += sizeof(resp.packet_pacing_caps);
713 }
714
715 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
716 uhw->outlen)) {
717 resp.mlx5_ib_support_multi_pkt_send_wqes =
718 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
719 resp.response_length +=
720 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
721 }
722
723 if (field_avail(typeof(resp), reserved, uhw->outlen))
724 resp.response_length += sizeof(resp.reserved);
725
726 if (uhw->outlen) {
727 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
728
729 if (err)
730 return err;
731 }
732
733 return 0;
734 }
735
736 enum mlx5_ib_width {
737 MLX5_IB_WIDTH_1X = 1 << 0,
738 MLX5_IB_WIDTH_2X = 1 << 1,
739 MLX5_IB_WIDTH_4X = 1 << 2,
740 MLX5_IB_WIDTH_8X = 1 << 3,
741 MLX5_IB_WIDTH_12X = 1 << 4
742 };
743
744 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
745 u8 *ib_width)
746 {
747 struct mlx5_ib_dev *dev = to_mdev(ibdev);
748 int err = 0;
749
750 if (active_width & MLX5_IB_WIDTH_1X) {
751 *ib_width = IB_WIDTH_1X;
752 } else if (active_width & MLX5_IB_WIDTH_2X) {
753 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
754 (int)active_width);
755 err = -EINVAL;
756 } else if (active_width & MLX5_IB_WIDTH_4X) {
757 *ib_width = IB_WIDTH_4X;
758 } else if (active_width & MLX5_IB_WIDTH_8X) {
759 *ib_width = IB_WIDTH_8X;
760 } else if (active_width & MLX5_IB_WIDTH_12X) {
761 *ib_width = IB_WIDTH_12X;
762 } else {
763 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
764 (int)active_width);
765 err = -EINVAL;
766 }
767
768 return err;
769 }
770
771 static int mlx5_mtu_to_ib_mtu(int mtu)
772 {
773 switch (mtu) {
774 case 256: return 1;
775 case 512: return 2;
776 case 1024: return 3;
777 case 2048: return 4;
778 case 4096: return 5;
779 default:
780 pr_warn("invalid mtu\n");
781 return -1;
782 }
783 }
784
785 enum ib_max_vl_num {
786 __IB_MAX_VL_0 = 1,
787 __IB_MAX_VL_0_1 = 2,
788 __IB_MAX_VL_0_3 = 3,
789 __IB_MAX_VL_0_7 = 4,
790 __IB_MAX_VL_0_14 = 5,
791 };
792
793 enum mlx5_vl_hw_cap {
794 MLX5_VL_HW_0 = 1,
795 MLX5_VL_HW_0_1 = 2,
796 MLX5_VL_HW_0_2 = 3,
797 MLX5_VL_HW_0_3 = 4,
798 MLX5_VL_HW_0_4 = 5,
799 MLX5_VL_HW_0_5 = 6,
800 MLX5_VL_HW_0_6 = 7,
801 MLX5_VL_HW_0_7 = 8,
802 MLX5_VL_HW_0_14 = 15
803 };
804
805 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
806 u8 *max_vl_num)
807 {
808 switch (vl_hw_cap) {
809 case MLX5_VL_HW_0:
810 *max_vl_num = __IB_MAX_VL_0;
811 break;
812 case MLX5_VL_HW_0_1:
813 *max_vl_num = __IB_MAX_VL_0_1;
814 break;
815 case MLX5_VL_HW_0_3:
816 *max_vl_num = __IB_MAX_VL_0_3;
817 break;
818 case MLX5_VL_HW_0_7:
819 *max_vl_num = __IB_MAX_VL_0_7;
820 break;
821 case MLX5_VL_HW_0_14:
822 *max_vl_num = __IB_MAX_VL_0_14;
823 break;
824
825 default:
826 return -EINVAL;
827 }
828
829 return 0;
830 }
831
832 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
833 struct ib_port_attr *props)
834 {
835 struct mlx5_ib_dev *dev = to_mdev(ibdev);
836 struct mlx5_core_dev *mdev = dev->mdev;
837 struct mlx5_hca_vport_context *rep;
838 u16 max_mtu;
839 u16 oper_mtu;
840 int err;
841 u8 ib_link_width_oper;
842 u8 vl_hw_cap;
843
844 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
845 if (!rep) {
846 err = -ENOMEM;
847 goto out;
848 }
849
850 memset(props, 0, sizeof(*props));
851
852 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
853 if (err)
854 goto out;
855
856 props->lid = rep->lid;
857 props->lmc = rep->lmc;
858 props->sm_lid = rep->sm_lid;
859 props->sm_sl = rep->sm_sl;
860 props->state = rep->vport_state;
861 props->phys_state = rep->port_physical_state;
862 props->port_cap_flags = rep->cap_mask1;
863 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
864 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
865 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
866 props->bad_pkey_cntr = rep->pkey_violation_counter;
867 props->qkey_viol_cntr = rep->qkey_violation_counter;
868 props->subnet_timeout = rep->subnet_timeout;
869 props->init_type_reply = rep->init_type_reply;
870 props->grh_required = rep->grh_required;
871
872 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
873 if (err)
874 goto out;
875
876 err = translate_active_width(ibdev, ib_link_width_oper,
877 &props->active_width);
878 if (err)
879 goto out;
880 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
881 if (err)
882 goto out;
883
884 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
885
886 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
887
888 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
889
890 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
891
892 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
893 if (err)
894 goto out;
895
896 err = translate_max_vl_num(ibdev, vl_hw_cap,
897 &props->max_vl_num);
898 out:
899 kfree(rep);
900 return err;
901 }
902
903 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
904 struct ib_port_attr *props)
905 {
906 switch (mlx5_get_vport_access_method(ibdev)) {
907 case MLX5_VPORT_ACCESS_METHOD_MAD:
908 return mlx5_query_mad_ifc_port(ibdev, port, props);
909
910 case MLX5_VPORT_ACCESS_METHOD_HCA:
911 return mlx5_query_hca_port(ibdev, port, props);
912
913 case MLX5_VPORT_ACCESS_METHOD_NIC:
914 return mlx5_query_port_roce(ibdev, port, props);
915
916 default:
917 return -EINVAL;
918 }
919 }
920
921 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
922 union ib_gid *gid)
923 {
924 struct mlx5_ib_dev *dev = to_mdev(ibdev);
925 struct mlx5_core_dev *mdev = dev->mdev;
926
927 switch (mlx5_get_vport_access_method(ibdev)) {
928 case MLX5_VPORT_ACCESS_METHOD_MAD:
929 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
930
931 case MLX5_VPORT_ACCESS_METHOD_HCA:
932 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
933
934 default:
935 return -EINVAL;
936 }
937
938 }
939
940 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
941 u16 *pkey)
942 {
943 struct mlx5_ib_dev *dev = to_mdev(ibdev);
944 struct mlx5_core_dev *mdev = dev->mdev;
945
946 switch (mlx5_get_vport_access_method(ibdev)) {
947 case MLX5_VPORT_ACCESS_METHOD_MAD:
948 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
949
950 case MLX5_VPORT_ACCESS_METHOD_HCA:
951 case MLX5_VPORT_ACCESS_METHOD_NIC:
952 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
953 pkey);
954 default:
955 return -EINVAL;
956 }
957 }
958
959 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
960 struct ib_device_modify *props)
961 {
962 struct mlx5_ib_dev *dev = to_mdev(ibdev);
963 struct mlx5_reg_node_desc in;
964 struct mlx5_reg_node_desc out;
965 int err;
966
967 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
968 return -EOPNOTSUPP;
969
970 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
971 return 0;
972
973 /*
974 * If possible, pass node desc to FW, so it can generate
975 * a 144 trap. If cmd fails, just ignore.
976 */
977 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
978 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
979 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
980 if (err)
981 return err;
982
983 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
984
985 return err;
986 }
987
988 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
989 struct ib_port_modify *props)
990 {
991 struct mlx5_ib_dev *dev = to_mdev(ibdev);
992 struct ib_port_attr attr;
993 u32 tmp;
994 int err;
995
996 mutex_lock(&dev->cap_mask_mutex);
997
998 err = mlx5_ib_query_port(ibdev, port, &attr);
999 if (err)
1000 goto out;
1001
1002 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1003 ~props->clr_port_cap_mask;
1004
1005 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1006
1007 out:
1008 mutex_unlock(&dev->cap_mask_mutex);
1009 return err;
1010 }
1011
1012 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1013 {
1014 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1015 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1016 }
1017
1018 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1019 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1020 u32 *num_sys_pages)
1021 {
1022 int uars_per_sys_page;
1023 int bfregs_per_sys_page;
1024 int ref_bfregs = req->total_num_bfregs;
1025
1026 if (req->total_num_bfregs == 0)
1027 return -EINVAL;
1028
1029 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1030 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1031
1032 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1033 return -ENOMEM;
1034
1035 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1036 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1037 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1038 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1039
1040 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1041 return -EINVAL;
1042
1043 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1044 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1045 lib_uar_4k ? "yes" : "no", ref_bfregs,
1046 req->total_num_bfregs, *num_sys_pages);
1047
1048 return 0;
1049 }
1050
1051 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1052 {
1053 struct mlx5_bfreg_info *bfregi;
1054 int err;
1055 int i;
1056
1057 bfregi = &context->bfregi;
1058 for (i = 0; i < bfregi->num_sys_pages; i++) {
1059 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1060 if (err)
1061 goto error;
1062
1063 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1064 }
1065 return 0;
1066
1067 error:
1068 for (--i; i >= 0; i--)
1069 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1070 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1071
1072 return err;
1073 }
1074
1075 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1076 {
1077 struct mlx5_bfreg_info *bfregi;
1078 int err;
1079 int i;
1080
1081 bfregi = &context->bfregi;
1082 for (i = 0; i < bfregi->num_sys_pages; i++) {
1083 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1084 if (err) {
1085 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1086 return err;
1087 }
1088 }
1089 return 0;
1090 }
1091
1092 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1093 struct ib_udata *udata)
1094 {
1095 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1096 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1097 struct mlx5_ib_alloc_ucontext_resp resp = {};
1098 struct mlx5_ib_ucontext *context;
1099 struct mlx5_bfreg_info *bfregi;
1100 int ver;
1101 int err;
1102 size_t reqlen;
1103 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1104 max_cqe_version);
1105 bool lib_uar_4k;
1106
1107 if (!dev->ib_active)
1108 return ERR_PTR(-EAGAIN);
1109
1110 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1111 return ERR_PTR(-EINVAL);
1112
1113 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1114 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1115 ver = 0;
1116 else if (reqlen >= min_req_v2)
1117 ver = 2;
1118 else
1119 return ERR_PTR(-EINVAL);
1120
1121 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1122 if (err)
1123 return ERR_PTR(err);
1124
1125 if (req.flags)
1126 return ERR_PTR(-EINVAL);
1127
1128 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1129 return ERR_PTR(-EOPNOTSUPP);
1130
1131 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1132 MLX5_NON_FP_BFREGS_PER_UAR);
1133 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1134 return ERR_PTR(-EINVAL);
1135
1136 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1137 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1138 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1139 resp.cache_line_size = cache_line_size();
1140 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1141 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1142 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1143 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1144 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1145 resp.cqe_version = min_t(__u8,
1146 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1147 req.max_cqe_version);
1148 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1149 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1150 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1151 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1152 resp.response_length = min(offsetof(typeof(resp), response_length) +
1153 sizeof(resp.response_length), udata->outlen);
1154
1155 context = kzalloc(sizeof(*context), GFP_KERNEL);
1156 if (!context)
1157 return ERR_PTR(-ENOMEM);
1158
1159 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1160 bfregi = &context->bfregi;
1161
1162 /* updates req->total_num_bfregs */
1163 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1164 if (err)
1165 goto out_ctx;
1166
1167 mutex_init(&bfregi->lock);
1168 bfregi->lib_uar_4k = lib_uar_4k;
1169 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1170 GFP_KERNEL);
1171 if (!bfregi->count) {
1172 err = -ENOMEM;
1173 goto out_ctx;
1174 }
1175
1176 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1177 sizeof(*bfregi->sys_pages),
1178 GFP_KERNEL);
1179 if (!bfregi->sys_pages) {
1180 err = -ENOMEM;
1181 goto out_count;
1182 }
1183
1184 err = allocate_uars(dev, context);
1185 if (err)
1186 goto out_sys_pages;
1187
1188 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1189 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1190 #endif
1191
1192 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1193 if (!context->upd_xlt_page) {
1194 err = -ENOMEM;
1195 goto out_uars;
1196 }
1197 mutex_init(&context->upd_xlt_page_mutex);
1198
1199 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1200 err = mlx5_core_alloc_transport_domain(dev->mdev,
1201 &context->tdn);
1202 if (err)
1203 goto out_page;
1204 }
1205
1206 INIT_LIST_HEAD(&context->vma_private_list);
1207 INIT_LIST_HEAD(&context->db_page_list);
1208 mutex_init(&context->db_page_mutex);
1209
1210 resp.tot_bfregs = req.total_num_bfregs;
1211 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1212
1213 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1214 resp.response_length += sizeof(resp.cqe_version);
1215
1216 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1217 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1218 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1219 resp.response_length += sizeof(resp.cmds_supp_uhw);
1220 }
1221
1222 /*
1223 * We don't want to expose information from the PCI bar that is located
1224 * after 4096 bytes, so if the arch only supports larger pages, let's
1225 * pretend we don't support reading the HCA's core clock. This is also
1226 * forced by mmap function.
1227 */
1228 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1229 if (PAGE_SIZE <= 4096) {
1230 resp.comp_mask |=
1231 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1232 resp.hca_core_clock_offset =
1233 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1234 }
1235 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1236 sizeof(resp.reserved2);
1237 }
1238
1239 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1240 resp.response_length += sizeof(resp.log_uar_size);
1241
1242 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1243 resp.response_length += sizeof(resp.num_uars_per_page);
1244
1245 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1246 if (err)
1247 goto out_td;
1248
1249 bfregi->ver = ver;
1250 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1251 context->cqe_version = resp.cqe_version;
1252 context->lib_caps = req.lib_caps;
1253 print_lib_caps(dev, context->lib_caps);
1254
1255 return &context->ibucontext;
1256
1257 out_td:
1258 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1259 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1260
1261 out_page:
1262 free_page(context->upd_xlt_page);
1263
1264 out_uars:
1265 deallocate_uars(dev, context);
1266
1267 out_sys_pages:
1268 kfree(bfregi->sys_pages);
1269
1270 out_count:
1271 kfree(bfregi->count);
1272
1273 out_ctx:
1274 kfree(context);
1275
1276 return ERR_PTR(err);
1277 }
1278
1279 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1280 {
1281 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1282 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1283 struct mlx5_bfreg_info *bfregi;
1284
1285 bfregi = &context->bfregi;
1286 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1287 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1288
1289 free_page(context->upd_xlt_page);
1290 deallocate_uars(dev, context);
1291 kfree(bfregi->sys_pages);
1292 kfree(bfregi->count);
1293 kfree(context);
1294
1295 return 0;
1296 }
1297
1298 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1299 struct mlx5_bfreg_info *bfregi,
1300 int idx)
1301 {
1302 int fw_uars_per_page;
1303
1304 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1305
1306 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1307 bfregi->sys_pages[idx] / fw_uars_per_page;
1308 }
1309
1310 static int get_command(unsigned long offset)
1311 {
1312 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1313 }
1314
1315 static int get_arg(unsigned long offset)
1316 {
1317 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1318 }
1319
1320 static int get_index(unsigned long offset)
1321 {
1322 return get_arg(offset);
1323 }
1324
1325 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1326 {
1327 /* vma_open is called when a new VMA is created on top of our VMA. This
1328 * is done through either mremap flow or split_vma (usually due to
1329 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1330 * as this VMA is strongly hardware related. Therefore we set the
1331 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1332 * calling us again and trying to do incorrect actions. We assume that
1333 * the original VMA size is exactly a single page, and therefore all
1334 * "splitting" operation will not happen to it.
1335 */
1336 area->vm_ops = NULL;
1337 }
1338
1339 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1340 {
1341 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1342
1343 /* It's guaranteed that all VMAs opened on a FD are closed before the
1344 * file itself is closed, therefore no sync is needed with the regular
1345 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1346 * However need a sync with accessing the vma as part of
1347 * mlx5_ib_disassociate_ucontext.
1348 * The close operation is usually called under mm->mmap_sem except when
1349 * process is exiting.
1350 * The exiting case is handled explicitly as part of
1351 * mlx5_ib_disassociate_ucontext.
1352 */
1353 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1354
1355 /* setting the vma context pointer to null in the mlx5_ib driver's
1356 * private data, to protect a race condition in
1357 * mlx5_ib_disassociate_ucontext().
1358 */
1359 mlx5_ib_vma_priv_data->vma = NULL;
1360 list_del(&mlx5_ib_vma_priv_data->list);
1361 kfree(mlx5_ib_vma_priv_data);
1362 }
1363
1364 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1365 .open = mlx5_ib_vma_open,
1366 .close = mlx5_ib_vma_close
1367 };
1368
1369 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1370 struct mlx5_ib_ucontext *ctx)
1371 {
1372 struct mlx5_ib_vma_private_data *vma_prv;
1373 struct list_head *vma_head = &ctx->vma_private_list;
1374
1375 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1376 if (!vma_prv)
1377 return -ENOMEM;
1378
1379 vma_prv->vma = vma;
1380 vma->vm_private_data = vma_prv;
1381 vma->vm_ops = &mlx5_ib_vm_ops;
1382
1383 list_add(&vma_prv->list, vma_head);
1384
1385 return 0;
1386 }
1387
1388 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1389 {
1390 int ret;
1391 struct vm_area_struct *vma;
1392 struct mlx5_ib_vma_private_data *vma_private, *n;
1393 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1394 struct task_struct *owning_process = NULL;
1395 struct mm_struct *owning_mm = NULL;
1396
1397 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1398 if (!owning_process)
1399 return;
1400
1401 owning_mm = get_task_mm(owning_process);
1402 if (!owning_mm) {
1403 pr_info("no mm, disassociate ucontext is pending task termination\n");
1404 while (1) {
1405 put_task_struct(owning_process);
1406 usleep_range(1000, 2000);
1407 owning_process = get_pid_task(ibcontext->tgid,
1408 PIDTYPE_PID);
1409 if (!owning_process ||
1410 owning_process->state == TASK_DEAD) {
1411 pr_info("disassociate ucontext done, task was terminated\n");
1412 /* in case task was dead need to release the
1413 * task struct.
1414 */
1415 if (owning_process)
1416 put_task_struct(owning_process);
1417 return;
1418 }
1419 }
1420 }
1421
1422 /* need to protect from a race on closing the vma as part of
1423 * mlx5_ib_vma_close.
1424 */
1425 down_read(&owning_mm->mmap_sem);
1426 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1427 list) {
1428 vma = vma_private->vma;
1429 ret = zap_vma_ptes(vma, vma->vm_start,
1430 PAGE_SIZE);
1431 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1432 /* context going to be destroyed, should
1433 * not access ops any more.
1434 */
1435 vma->vm_ops = NULL;
1436 list_del(&vma_private->list);
1437 kfree(vma_private);
1438 }
1439 up_read(&owning_mm->mmap_sem);
1440 mmput(owning_mm);
1441 put_task_struct(owning_process);
1442 }
1443
1444 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1445 {
1446 switch (cmd) {
1447 case MLX5_IB_MMAP_WC_PAGE:
1448 return "WC";
1449 case MLX5_IB_MMAP_REGULAR_PAGE:
1450 return "best effort WC";
1451 case MLX5_IB_MMAP_NC_PAGE:
1452 return "NC";
1453 default:
1454 return NULL;
1455 }
1456 }
1457
1458 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1459 struct vm_area_struct *vma,
1460 struct mlx5_ib_ucontext *context)
1461 {
1462 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1463 int err;
1464 unsigned long idx;
1465 phys_addr_t pfn, pa;
1466 pgprot_t prot;
1467 int uars_per_page;
1468
1469 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1470 return -EINVAL;
1471
1472 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1473 idx = get_index(vma->vm_pgoff);
1474 if (idx % uars_per_page ||
1475 idx * uars_per_page >= bfregi->num_sys_pages) {
1476 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1477 return -EINVAL;
1478 }
1479
1480 switch (cmd) {
1481 case MLX5_IB_MMAP_WC_PAGE:
1482 /* Some architectures don't support WC memory */
1483 #if defined(CONFIG_X86)
1484 if (!pat_enabled())
1485 return -EPERM;
1486 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1487 return -EPERM;
1488 #endif
1489 /* fall through */
1490 case MLX5_IB_MMAP_REGULAR_PAGE:
1491 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1492 prot = pgprot_writecombine(vma->vm_page_prot);
1493 break;
1494 case MLX5_IB_MMAP_NC_PAGE:
1495 prot = pgprot_noncached(vma->vm_page_prot);
1496 break;
1497 default:
1498 return -EINVAL;
1499 }
1500
1501 pfn = uar_index2pfn(dev, bfregi, idx);
1502 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1503
1504 vma->vm_page_prot = prot;
1505 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1506 PAGE_SIZE, vma->vm_page_prot);
1507 if (err) {
1508 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1509 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1510 return -EAGAIN;
1511 }
1512
1513 pa = pfn << PAGE_SHIFT;
1514 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1515 vma->vm_start, &pa);
1516
1517 return mlx5_ib_set_vma_data(vma, context);
1518 }
1519
1520 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1521 {
1522 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1523 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1524 unsigned long command;
1525 phys_addr_t pfn;
1526
1527 command = get_command(vma->vm_pgoff);
1528 switch (command) {
1529 case MLX5_IB_MMAP_WC_PAGE:
1530 case MLX5_IB_MMAP_NC_PAGE:
1531 case MLX5_IB_MMAP_REGULAR_PAGE:
1532 return uar_mmap(dev, command, vma, context);
1533
1534 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1535 return -ENOSYS;
1536
1537 case MLX5_IB_MMAP_CORE_CLOCK:
1538 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1539 return -EINVAL;
1540
1541 if (vma->vm_flags & VM_WRITE)
1542 return -EPERM;
1543
1544 /* Don't expose to user-space information it shouldn't have */
1545 if (PAGE_SIZE > 4096)
1546 return -EOPNOTSUPP;
1547
1548 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1549 pfn = (dev->mdev->iseg_base +
1550 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1551 PAGE_SHIFT;
1552 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1553 PAGE_SIZE, vma->vm_page_prot))
1554 return -EAGAIN;
1555
1556 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1557 vma->vm_start,
1558 (unsigned long long)pfn << PAGE_SHIFT);
1559 break;
1560
1561 default:
1562 return -EINVAL;
1563 }
1564
1565 return 0;
1566 }
1567
1568 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1569 struct ib_ucontext *context,
1570 struct ib_udata *udata)
1571 {
1572 struct mlx5_ib_alloc_pd_resp resp;
1573 struct mlx5_ib_pd *pd;
1574 int err;
1575
1576 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1577 if (!pd)
1578 return ERR_PTR(-ENOMEM);
1579
1580 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1581 if (err) {
1582 kfree(pd);
1583 return ERR_PTR(err);
1584 }
1585
1586 if (context) {
1587 resp.pdn = pd->pdn;
1588 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1589 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1590 kfree(pd);
1591 return ERR_PTR(-EFAULT);
1592 }
1593 }
1594
1595 return &pd->ibpd;
1596 }
1597
1598 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1599 {
1600 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1601 struct mlx5_ib_pd *mpd = to_mpd(pd);
1602
1603 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1604 kfree(mpd);
1605
1606 return 0;
1607 }
1608
1609 enum {
1610 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1611 MATCH_CRITERIA_ENABLE_MISC_BIT,
1612 MATCH_CRITERIA_ENABLE_INNER_BIT
1613 };
1614
1615 #define HEADER_IS_ZERO(match_criteria, headers) \
1616 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1617 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1618
1619 static u8 get_match_criteria_enable(u32 *match_criteria)
1620 {
1621 u8 match_criteria_enable;
1622
1623 match_criteria_enable =
1624 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1625 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1626 match_criteria_enable |=
1627 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1628 MATCH_CRITERIA_ENABLE_MISC_BIT;
1629 match_criteria_enable |=
1630 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1631 MATCH_CRITERIA_ENABLE_INNER_BIT;
1632
1633 return match_criteria_enable;
1634 }
1635
1636 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1637 {
1638 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1639 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1640 }
1641
1642 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1643 bool inner)
1644 {
1645 if (inner) {
1646 MLX5_SET(fte_match_set_misc,
1647 misc_c, inner_ipv6_flow_label, mask);
1648 MLX5_SET(fte_match_set_misc,
1649 misc_v, inner_ipv6_flow_label, val);
1650 } else {
1651 MLX5_SET(fte_match_set_misc,
1652 misc_c, outer_ipv6_flow_label, mask);
1653 MLX5_SET(fte_match_set_misc,
1654 misc_v, outer_ipv6_flow_label, val);
1655 }
1656 }
1657
1658 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1659 {
1660 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1661 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1662 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1663 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1664 }
1665
1666 #define LAST_ETH_FIELD vlan_tag
1667 #define LAST_IB_FIELD sl
1668 #define LAST_IPV4_FIELD tos
1669 #define LAST_IPV6_FIELD traffic_class
1670 #define LAST_TCP_UDP_FIELD src_port
1671 #define LAST_TUNNEL_FIELD tunnel_id
1672
1673 /* Field is the last supported field */
1674 #define FIELDS_NOT_SUPPORTED(filter, field)\
1675 memchr_inv((void *)&filter.field +\
1676 sizeof(filter.field), 0,\
1677 sizeof(filter) -\
1678 offsetof(typeof(filter), field) -\
1679 sizeof(filter.field))
1680
1681 static int parse_flow_attr(u32 *match_c, u32 *match_v,
1682 const union ib_flow_spec *ib_spec)
1683 {
1684 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1685 misc_parameters);
1686 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1687 misc_parameters);
1688 void *headers_c;
1689 void *headers_v;
1690
1691 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1692 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1693 inner_headers);
1694 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1695 inner_headers);
1696 } else {
1697 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1698 outer_headers);
1699 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1700 outer_headers);
1701 }
1702
1703 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1704 case IB_FLOW_SPEC_ETH:
1705 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1706 return -ENOTSUPP;
1707
1708 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1709 dmac_47_16),
1710 ib_spec->eth.mask.dst_mac);
1711 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1712 dmac_47_16),
1713 ib_spec->eth.val.dst_mac);
1714
1715 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1716 smac_47_16),
1717 ib_spec->eth.mask.src_mac);
1718 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1719 smac_47_16),
1720 ib_spec->eth.val.src_mac);
1721
1722 if (ib_spec->eth.mask.vlan_tag) {
1723 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1724 vlan_tag, 1);
1725 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1726 vlan_tag, 1);
1727
1728 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1729 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1730 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1731 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1732
1733 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1734 first_cfi,
1735 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1736 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1737 first_cfi,
1738 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1739
1740 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1741 first_prio,
1742 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1743 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1744 first_prio,
1745 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1746 }
1747 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1748 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1749 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1750 ethertype, ntohs(ib_spec->eth.val.ether_type));
1751 break;
1752 case IB_FLOW_SPEC_IPV4:
1753 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1754 return -ENOTSUPP;
1755
1756 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1757 ethertype, 0xffff);
1758 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1759 ethertype, ETH_P_IP);
1760
1761 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1762 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1763 &ib_spec->ipv4.mask.src_ip,
1764 sizeof(ib_spec->ipv4.mask.src_ip));
1765 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1766 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1767 &ib_spec->ipv4.val.src_ip,
1768 sizeof(ib_spec->ipv4.val.src_ip));
1769 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1770 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1771 &ib_spec->ipv4.mask.dst_ip,
1772 sizeof(ib_spec->ipv4.mask.dst_ip));
1773 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1774 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1775 &ib_spec->ipv4.val.dst_ip,
1776 sizeof(ib_spec->ipv4.val.dst_ip));
1777
1778 set_tos(headers_c, headers_v,
1779 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1780
1781 set_proto(headers_c, headers_v,
1782 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1783 break;
1784 case IB_FLOW_SPEC_IPV6:
1785 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1786 return -ENOTSUPP;
1787
1788 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1789 ethertype, 0xffff);
1790 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1791 ethertype, ETH_P_IPV6);
1792
1793 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1794 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1795 &ib_spec->ipv6.mask.src_ip,
1796 sizeof(ib_spec->ipv6.mask.src_ip));
1797 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1798 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1799 &ib_spec->ipv6.val.src_ip,
1800 sizeof(ib_spec->ipv6.val.src_ip));
1801 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1802 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1803 &ib_spec->ipv6.mask.dst_ip,
1804 sizeof(ib_spec->ipv6.mask.dst_ip));
1805 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1806 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1807 &ib_spec->ipv6.val.dst_ip,
1808 sizeof(ib_spec->ipv6.val.dst_ip));
1809
1810 set_tos(headers_c, headers_v,
1811 ib_spec->ipv6.mask.traffic_class,
1812 ib_spec->ipv6.val.traffic_class);
1813
1814 set_proto(headers_c, headers_v,
1815 ib_spec->ipv6.mask.next_hdr,
1816 ib_spec->ipv6.val.next_hdr);
1817
1818 set_flow_label(misc_params_c, misc_params_v,
1819 ntohl(ib_spec->ipv6.mask.flow_label),
1820 ntohl(ib_spec->ipv6.val.flow_label),
1821 ib_spec->type & IB_FLOW_SPEC_INNER);
1822
1823 break;
1824 case IB_FLOW_SPEC_TCP:
1825 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1826 LAST_TCP_UDP_FIELD))
1827 return -ENOTSUPP;
1828
1829 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1830 0xff);
1831 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1832 IPPROTO_TCP);
1833
1834 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
1835 ntohs(ib_spec->tcp_udp.mask.src_port));
1836 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1837 ntohs(ib_spec->tcp_udp.val.src_port));
1838
1839 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
1840 ntohs(ib_spec->tcp_udp.mask.dst_port));
1841 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1842 ntohs(ib_spec->tcp_udp.val.dst_port));
1843 break;
1844 case IB_FLOW_SPEC_UDP:
1845 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1846 LAST_TCP_UDP_FIELD))
1847 return -ENOTSUPP;
1848
1849 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1850 0xff);
1851 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1852 IPPROTO_UDP);
1853
1854 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
1855 ntohs(ib_spec->tcp_udp.mask.src_port));
1856 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1857 ntohs(ib_spec->tcp_udp.val.src_port));
1858
1859 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
1860 ntohs(ib_spec->tcp_udp.mask.dst_port));
1861 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1862 ntohs(ib_spec->tcp_udp.val.dst_port));
1863 break;
1864 case IB_FLOW_SPEC_VXLAN_TUNNEL:
1865 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1866 LAST_TUNNEL_FIELD))
1867 return -ENOTSUPP;
1868
1869 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
1870 ntohl(ib_spec->tunnel.mask.tunnel_id));
1871 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
1872 ntohl(ib_spec->tunnel.val.tunnel_id));
1873 break;
1874 default:
1875 return -EINVAL;
1876 }
1877
1878 return 0;
1879 }
1880
1881 /* If a flow could catch both multicast and unicast packets,
1882 * it won't fall into the multicast flow steering table and this rule
1883 * could steal other multicast packets.
1884 */
1885 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
1886 {
1887 struct ib_flow_spec_eth *eth_spec;
1888
1889 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
1890 ib_attr->size < sizeof(struct ib_flow_attr) +
1891 sizeof(struct ib_flow_spec_eth) ||
1892 ib_attr->num_of_specs < 1)
1893 return false;
1894
1895 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
1896 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
1897 eth_spec->size != sizeof(*eth_spec))
1898 return false;
1899
1900 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
1901 is_multicast_ether_addr(eth_spec->val.dst_mac);
1902 }
1903
1904 static bool is_valid_attr(const struct ib_flow_attr *flow_attr)
1905 {
1906 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1907 bool has_ipv4_spec = false;
1908 bool eth_type_ipv4 = true;
1909 unsigned int spec_index;
1910
1911 /* Validate that ethertype is correct */
1912 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
1913 if (ib_spec->type == IB_FLOW_SPEC_ETH &&
1914 ib_spec->eth.mask.ether_type) {
1915 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) &&
1916 ib_spec->eth.val.ether_type == htons(ETH_P_IP)))
1917 eth_type_ipv4 = false;
1918 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) {
1919 has_ipv4_spec = true;
1920 }
1921 ib_spec = (void *)ib_spec + ib_spec->size;
1922 }
1923 return !has_ipv4_spec || eth_type_ipv4;
1924 }
1925
1926 static void put_flow_table(struct mlx5_ib_dev *dev,
1927 struct mlx5_ib_flow_prio *prio, bool ft_added)
1928 {
1929 prio->refcount -= !!ft_added;
1930 if (!prio->refcount) {
1931 mlx5_destroy_flow_table(prio->flow_table);
1932 prio->flow_table = NULL;
1933 }
1934 }
1935
1936 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
1937 {
1938 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
1939 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
1940 struct mlx5_ib_flow_handler,
1941 ibflow);
1942 struct mlx5_ib_flow_handler *iter, *tmp;
1943
1944 mutex_lock(&dev->flow_db.lock);
1945
1946 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
1947 mlx5_del_flow_rules(iter->rule);
1948 put_flow_table(dev, iter->prio, true);
1949 list_del(&iter->list);
1950 kfree(iter);
1951 }
1952
1953 mlx5_del_flow_rules(handler->rule);
1954 put_flow_table(dev, handler->prio, true);
1955 mutex_unlock(&dev->flow_db.lock);
1956
1957 kfree(handler);
1958
1959 return 0;
1960 }
1961
1962 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
1963 {
1964 priority *= 2;
1965 if (!dont_trap)
1966 priority++;
1967 return priority;
1968 }
1969
1970 enum flow_table_type {
1971 MLX5_IB_FT_RX,
1972 MLX5_IB_FT_TX
1973 };
1974
1975 #define MLX5_FS_MAX_TYPES 10
1976 #define MLX5_FS_MAX_ENTRIES 32000UL
1977 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
1978 struct ib_flow_attr *flow_attr,
1979 enum flow_table_type ft_type)
1980 {
1981 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
1982 struct mlx5_flow_namespace *ns = NULL;
1983 struct mlx5_ib_flow_prio *prio;
1984 struct mlx5_flow_table *ft;
1985 int num_entries;
1986 int num_groups;
1987 int priority;
1988 int err = 0;
1989
1990 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1991 if (flow_is_multicast_only(flow_attr) &&
1992 !dont_trap)
1993 priority = MLX5_IB_FLOW_MCAST_PRIO;
1994 else
1995 priority = ib_prio_to_core_prio(flow_attr->priority,
1996 dont_trap);
1997 ns = mlx5_get_flow_namespace(dev->mdev,
1998 MLX5_FLOW_NAMESPACE_BYPASS);
1999 num_entries = MLX5_FS_MAX_ENTRIES;
2000 num_groups = MLX5_FS_MAX_TYPES;
2001 prio = &dev->flow_db.prios[priority];
2002 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2003 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2004 ns = mlx5_get_flow_namespace(dev->mdev,
2005 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2006 build_leftovers_ft_param(&priority,
2007 &num_entries,
2008 &num_groups);
2009 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2010 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2011 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2012 allow_sniffer_and_nic_rx_shared_tir))
2013 return ERR_PTR(-ENOTSUPP);
2014
2015 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2016 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2017 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2018
2019 prio = &dev->flow_db.sniffer[ft_type];
2020 priority = 0;
2021 num_entries = 1;
2022 num_groups = 1;
2023 }
2024
2025 if (!ns)
2026 return ERR_PTR(-ENOTSUPP);
2027
2028 ft = prio->flow_table;
2029 if (!ft) {
2030 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2031 num_entries,
2032 num_groups,
2033 0, 0);
2034
2035 if (!IS_ERR(ft)) {
2036 prio->refcount = 0;
2037 prio->flow_table = ft;
2038 } else {
2039 err = PTR_ERR(ft);
2040 }
2041 }
2042
2043 return err ? ERR_PTR(err) : prio;
2044 }
2045
2046 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2047 struct mlx5_ib_flow_prio *ft_prio,
2048 const struct ib_flow_attr *flow_attr,
2049 struct mlx5_flow_destination *dst)
2050 {
2051 struct mlx5_flow_table *ft = ft_prio->flow_table;
2052 struct mlx5_ib_flow_handler *handler;
2053 struct mlx5_flow_act flow_act = {0};
2054 struct mlx5_flow_spec *spec;
2055 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2056 unsigned int spec_index;
2057 int err = 0;
2058
2059 if (!is_valid_attr(flow_attr))
2060 return ERR_PTR(-EINVAL);
2061
2062 spec = mlx5_vzalloc(sizeof(*spec));
2063 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2064 if (!handler || !spec) {
2065 err = -ENOMEM;
2066 goto free;
2067 }
2068
2069 INIT_LIST_HEAD(&handler->list);
2070
2071 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2072 err = parse_flow_attr(spec->match_criteria,
2073 spec->match_value, ib_flow);
2074 if (err < 0)
2075 goto free;
2076
2077 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2078 }
2079
2080 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2081 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2082 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2083 flow_act.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2084 handler->rule = mlx5_add_flow_rules(ft, spec,
2085 &flow_act,
2086 dst, 1);
2087
2088 if (IS_ERR(handler->rule)) {
2089 err = PTR_ERR(handler->rule);
2090 goto free;
2091 }
2092
2093 ft_prio->refcount++;
2094 handler->prio = ft_prio;
2095
2096 ft_prio->flow_table = ft;
2097 free:
2098 if (err)
2099 kfree(handler);
2100 kvfree(spec);
2101 return err ? ERR_PTR(err) : handler;
2102 }
2103
2104 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2105 struct mlx5_ib_flow_prio *ft_prio,
2106 struct ib_flow_attr *flow_attr,
2107 struct mlx5_flow_destination *dst)
2108 {
2109 struct mlx5_ib_flow_handler *handler_dst = NULL;
2110 struct mlx5_ib_flow_handler *handler = NULL;
2111
2112 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2113 if (!IS_ERR(handler)) {
2114 handler_dst = create_flow_rule(dev, ft_prio,
2115 flow_attr, dst);
2116 if (IS_ERR(handler_dst)) {
2117 mlx5_del_flow_rules(handler->rule);
2118 ft_prio->refcount--;
2119 kfree(handler);
2120 handler = handler_dst;
2121 } else {
2122 list_add(&handler_dst->list, &handler->list);
2123 }
2124 }
2125
2126 return handler;
2127 }
2128 enum {
2129 LEFTOVERS_MC,
2130 LEFTOVERS_UC,
2131 };
2132
2133 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2134 struct mlx5_ib_flow_prio *ft_prio,
2135 struct ib_flow_attr *flow_attr,
2136 struct mlx5_flow_destination *dst)
2137 {
2138 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2139 struct mlx5_ib_flow_handler *handler = NULL;
2140
2141 static struct {
2142 struct ib_flow_attr flow_attr;
2143 struct ib_flow_spec_eth eth_flow;
2144 } leftovers_specs[] = {
2145 [LEFTOVERS_MC] = {
2146 .flow_attr = {
2147 .num_of_specs = 1,
2148 .size = sizeof(leftovers_specs[0])
2149 },
2150 .eth_flow = {
2151 .type = IB_FLOW_SPEC_ETH,
2152 .size = sizeof(struct ib_flow_spec_eth),
2153 .mask = {.dst_mac = {0x1} },
2154 .val = {.dst_mac = {0x1} }
2155 }
2156 },
2157 [LEFTOVERS_UC] = {
2158 .flow_attr = {
2159 .num_of_specs = 1,
2160 .size = sizeof(leftovers_specs[0])
2161 },
2162 .eth_flow = {
2163 .type = IB_FLOW_SPEC_ETH,
2164 .size = sizeof(struct ib_flow_spec_eth),
2165 .mask = {.dst_mac = {0x1} },
2166 .val = {.dst_mac = {} }
2167 }
2168 }
2169 };
2170
2171 handler = create_flow_rule(dev, ft_prio,
2172 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2173 dst);
2174 if (!IS_ERR(handler) &&
2175 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2176 handler_ucast = create_flow_rule(dev, ft_prio,
2177 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2178 dst);
2179 if (IS_ERR(handler_ucast)) {
2180 mlx5_del_flow_rules(handler->rule);
2181 ft_prio->refcount--;
2182 kfree(handler);
2183 handler = handler_ucast;
2184 } else {
2185 list_add(&handler_ucast->list, &handler->list);
2186 }
2187 }
2188
2189 return handler;
2190 }
2191
2192 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2193 struct mlx5_ib_flow_prio *ft_rx,
2194 struct mlx5_ib_flow_prio *ft_tx,
2195 struct mlx5_flow_destination *dst)
2196 {
2197 struct mlx5_ib_flow_handler *handler_rx;
2198 struct mlx5_ib_flow_handler *handler_tx;
2199 int err;
2200 static const struct ib_flow_attr flow_attr = {
2201 .num_of_specs = 0,
2202 .size = sizeof(flow_attr)
2203 };
2204
2205 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2206 if (IS_ERR(handler_rx)) {
2207 err = PTR_ERR(handler_rx);
2208 goto err;
2209 }
2210
2211 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2212 if (IS_ERR(handler_tx)) {
2213 err = PTR_ERR(handler_tx);
2214 goto err_tx;
2215 }
2216
2217 list_add(&handler_tx->list, &handler_rx->list);
2218
2219 return handler_rx;
2220
2221 err_tx:
2222 mlx5_del_flow_rules(handler_rx->rule);
2223 ft_rx->refcount--;
2224 kfree(handler_rx);
2225 err:
2226 return ERR_PTR(err);
2227 }
2228
2229 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2230 struct ib_flow_attr *flow_attr,
2231 int domain)
2232 {
2233 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2234 struct mlx5_ib_qp *mqp = to_mqp(qp);
2235 struct mlx5_ib_flow_handler *handler = NULL;
2236 struct mlx5_flow_destination *dst = NULL;
2237 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2238 struct mlx5_ib_flow_prio *ft_prio;
2239 int err;
2240
2241 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2242 return ERR_PTR(-ENOSPC);
2243
2244 if (domain != IB_FLOW_DOMAIN_USER ||
2245 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2246 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2247 return ERR_PTR(-EINVAL);
2248
2249 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2250 if (!dst)
2251 return ERR_PTR(-ENOMEM);
2252
2253 mutex_lock(&dev->flow_db.lock);
2254
2255 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2256 if (IS_ERR(ft_prio)) {
2257 err = PTR_ERR(ft_prio);
2258 goto unlock;
2259 }
2260 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2261 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2262 if (IS_ERR(ft_prio_tx)) {
2263 err = PTR_ERR(ft_prio_tx);
2264 ft_prio_tx = NULL;
2265 goto destroy_ft;
2266 }
2267 }
2268
2269 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2270 if (mqp->flags & MLX5_IB_QP_RSS)
2271 dst->tir_num = mqp->rss_qp.tirn;
2272 else
2273 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2274
2275 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2276 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2277 handler = create_dont_trap_rule(dev, ft_prio,
2278 flow_attr, dst);
2279 } else {
2280 handler = create_flow_rule(dev, ft_prio, flow_attr,
2281 dst);
2282 }
2283 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2284 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2285 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2286 dst);
2287 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2288 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2289 } else {
2290 err = -EINVAL;
2291 goto destroy_ft;
2292 }
2293
2294 if (IS_ERR(handler)) {
2295 err = PTR_ERR(handler);
2296 handler = NULL;
2297 goto destroy_ft;
2298 }
2299
2300 mutex_unlock(&dev->flow_db.lock);
2301 kfree(dst);
2302
2303 return &handler->ibflow;
2304
2305 destroy_ft:
2306 put_flow_table(dev, ft_prio, false);
2307 if (ft_prio_tx)
2308 put_flow_table(dev, ft_prio_tx, false);
2309 unlock:
2310 mutex_unlock(&dev->flow_db.lock);
2311 kfree(dst);
2312 kfree(handler);
2313 return ERR_PTR(err);
2314 }
2315
2316 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2317 {
2318 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2319 int err;
2320
2321 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2322 if (err)
2323 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2324 ibqp->qp_num, gid->raw);
2325
2326 return err;
2327 }
2328
2329 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2330 {
2331 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2332 int err;
2333
2334 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2335 if (err)
2336 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2337 ibqp->qp_num, gid->raw);
2338
2339 return err;
2340 }
2341
2342 static int init_node_data(struct mlx5_ib_dev *dev)
2343 {
2344 int err;
2345
2346 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2347 if (err)
2348 return err;
2349
2350 dev->mdev->rev_id = dev->mdev->pdev->revision;
2351
2352 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2353 }
2354
2355 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2356 char *buf)
2357 {
2358 struct mlx5_ib_dev *dev =
2359 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2360
2361 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2362 }
2363
2364 static ssize_t show_reg_pages(struct device *device,
2365 struct device_attribute *attr, char *buf)
2366 {
2367 struct mlx5_ib_dev *dev =
2368 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2369
2370 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2371 }
2372
2373 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2374 char *buf)
2375 {
2376 struct mlx5_ib_dev *dev =
2377 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2378 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2379 }
2380
2381 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2382 char *buf)
2383 {
2384 struct mlx5_ib_dev *dev =
2385 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2386 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2387 }
2388
2389 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2390 char *buf)
2391 {
2392 struct mlx5_ib_dev *dev =
2393 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2394 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2395 dev->mdev->board_id);
2396 }
2397
2398 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2399 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2400 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2401 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2402 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2403
2404 static struct device_attribute *mlx5_class_attributes[] = {
2405 &dev_attr_hw_rev,
2406 &dev_attr_hca_type,
2407 &dev_attr_board_id,
2408 &dev_attr_fw_pages,
2409 &dev_attr_reg_pages,
2410 };
2411
2412 static void pkey_change_handler(struct work_struct *work)
2413 {
2414 struct mlx5_ib_port_resources *ports =
2415 container_of(work, struct mlx5_ib_port_resources,
2416 pkey_change_work);
2417
2418 mutex_lock(&ports->devr->mutex);
2419 mlx5_ib_gsi_pkey_change(ports->gsi);
2420 mutex_unlock(&ports->devr->mutex);
2421 }
2422
2423 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2424 {
2425 struct mlx5_ib_qp *mqp;
2426 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2427 struct mlx5_core_cq *mcq;
2428 struct list_head cq_armed_list;
2429 unsigned long flags_qp;
2430 unsigned long flags_cq;
2431 unsigned long flags;
2432
2433 INIT_LIST_HEAD(&cq_armed_list);
2434
2435 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2436 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2437 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2438 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2439 if (mqp->sq.tail != mqp->sq.head) {
2440 send_mcq = to_mcq(mqp->ibqp.send_cq);
2441 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2442 if (send_mcq->mcq.comp &&
2443 mqp->ibqp.send_cq->comp_handler) {
2444 if (!send_mcq->mcq.reset_notify_added) {
2445 send_mcq->mcq.reset_notify_added = 1;
2446 list_add_tail(&send_mcq->mcq.reset_notify,
2447 &cq_armed_list);
2448 }
2449 }
2450 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2451 }
2452 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2453 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2454 /* no handling is needed for SRQ */
2455 if (!mqp->ibqp.srq) {
2456 if (mqp->rq.tail != mqp->rq.head) {
2457 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2458 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2459 if (recv_mcq->mcq.comp &&
2460 mqp->ibqp.recv_cq->comp_handler) {
2461 if (!recv_mcq->mcq.reset_notify_added) {
2462 recv_mcq->mcq.reset_notify_added = 1;
2463 list_add_tail(&recv_mcq->mcq.reset_notify,
2464 &cq_armed_list);
2465 }
2466 }
2467 spin_unlock_irqrestore(&recv_mcq->lock,
2468 flags_cq);
2469 }
2470 }
2471 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2472 }
2473 /*At that point all inflight post send were put to be executed as of we
2474 * lock/unlock above locks Now need to arm all involved CQs.
2475 */
2476 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2477 mcq->comp(mcq);
2478 }
2479 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2480 }
2481
2482 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2483 enum mlx5_dev_event event, unsigned long param)
2484 {
2485 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2486 struct ib_event ibev;
2487 bool fatal = false;
2488 u8 port = 0;
2489
2490 switch (event) {
2491 case MLX5_DEV_EVENT_SYS_ERROR:
2492 ibev.event = IB_EVENT_DEVICE_FATAL;
2493 mlx5_ib_handle_internal_error(ibdev);
2494 fatal = true;
2495 break;
2496
2497 case MLX5_DEV_EVENT_PORT_UP:
2498 case MLX5_DEV_EVENT_PORT_DOWN:
2499 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2500 port = (u8)param;
2501
2502 /* In RoCE, port up/down events are handled in
2503 * mlx5_netdev_event().
2504 */
2505 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2506 IB_LINK_LAYER_ETHERNET)
2507 return;
2508
2509 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2510 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2511 break;
2512
2513 case MLX5_DEV_EVENT_LID_CHANGE:
2514 ibev.event = IB_EVENT_LID_CHANGE;
2515 port = (u8)param;
2516 break;
2517
2518 case MLX5_DEV_EVENT_PKEY_CHANGE:
2519 ibev.event = IB_EVENT_PKEY_CHANGE;
2520 port = (u8)param;
2521
2522 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2523 break;
2524
2525 case MLX5_DEV_EVENT_GUID_CHANGE:
2526 ibev.event = IB_EVENT_GID_CHANGE;
2527 port = (u8)param;
2528 break;
2529
2530 case MLX5_DEV_EVENT_CLIENT_REREG:
2531 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2532 port = (u8)param;
2533 break;
2534 default:
2535 return;
2536 }
2537
2538 ibev.device = &ibdev->ib_dev;
2539 ibev.element.port_num = port;
2540
2541 if (port < 1 || port > ibdev->num_ports) {
2542 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2543 return;
2544 }
2545
2546 if (ibdev->ib_active)
2547 ib_dispatch_event(&ibev);
2548
2549 if (fatal)
2550 ibdev->ib_active = false;
2551 }
2552
2553 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2554 {
2555 struct mlx5_hca_vport_context vport_ctx;
2556 int err;
2557 int port;
2558
2559 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2560 dev->mdev->port_caps[port - 1].has_smi = false;
2561 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2562 MLX5_CAP_PORT_TYPE_IB) {
2563 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2564 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2565 port, 0,
2566 &vport_ctx);
2567 if (err) {
2568 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2569 port, err);
2570 return err;
2571 }
2572 dev->mdev->port_caps[port - 1].has_smi =
2573 vport_ctx.has_smi;
2574 } else {
2575 dev->mdev->port_caps[port - 1].has_smi = true;
2576 }
2577 }
2578 }
2579 return 0;
2580 }
2581
2582 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2583 {
2584 int port;
2585
2586 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2587 mlx5_query_ext_port_caps(dev, port);
2588 }
2589
2590 static int get_port_caps(struct mlx5_ib_dev *dev)
2591 {
2592 struct ib_device_attr *dprops = NULL;
2593 struct ib_port_attr *pprops = NULL;
2594 int err = -ENOMEM;
2595 int port;
2596 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2597
2598 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2599 if (!pprops)
2600 goto out;
2601
2602 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2603 if (!dprops)
2604 goto out;
2605
2606 err = set_has_smi_cap(dev);
2607 if (err)
2608 goto out;
2609
2610 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2611 if (err) {
2612 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2613 goto out;
2614 }
2615
2616 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2617 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2618 if (err) {
2619 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2620 port, err);
2621 break;
2622 }
2623 dev->mdev->port_caps[port - 1].pkey_table_len =
2624 dprops->max_pkeys;
2625 dev->mdev->port_caps[port - 1].gid_table_len =
2626 pprops->gid_tbl_len;
2627 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2628 dprops->max_pkeys, pprops->gid_tbl_len);
2629 }
2630
2631 out:
2632 kfree(pprops);
2633 kfree(dprops);
2634
2635 return err;
2636 }
2637
2638 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2639 {
2640 int err;
2641
2642 err = mlx5_mr_cache_cleanup(dev);
2643 if (err)
2644 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2645
2646 mlx5_ib_destroy_qp(dev->umrc.qp);
2647 ib_free_cq(dev->umrc.cq);
2648 ib_dealloc_pd(dev->umrc.pd);
2649 }
2650
2651 enum {
2652 MAX_UMR_WR = 128,
2653 };
2654
2655 static int create_umr_res(struct mlx5_ib_dev *dev)
2656 {
2657 struct ib_qp_init_attr *init_attr = NULL;
2658 struct ib_qp_attr *attr = NULL;
2659 struct ib_pd *pd;
2660 struct ib_cq *cq;
2661 struct ib_qp *qp;
2662 int ret;
2663
2664 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2665 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2666 if (!attr || !init_attr) {
2667 ret = -ENOMEM;
2668 goto error_0;
2669 }
2670
2671 pd = ib_alloc_pd(&dev->ib_dev, 0);
2672 if (IS_ERR(pd)) {
2673 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2674 ret = PTR_ERR(pd);
2675 goto error_0;
2676 }
2677
2678 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2679 if (IS_ERR(cq)) {
2680 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2681 ret = PTR_ERR(cq);
2682 goto error_2;
2683 }
2684
2685 init_attr->send_cq = cq;
2686 init_attr->recv_cq = cq;
2687 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2688 init_attr->cap.max_send_wr = MAX_UMR_WR;
2689 init_attr->cap.max_send_sge = 1;
2690 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2691 init_attr->port_num = 1;
2692 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2693 if (IS_ERR(qp)) {
2694 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2695 ret = PTR_ERR(qp);
2696 goto error_3;
2697 }
2698 qp->device = &dev->ib_dev;
2699 qp->real_qp = qp;
2700 qp->uobject = NULL;
2701 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2702
2703 attr->qp_state = IB_QPS_INIT;
2704 attr->port_num = 1;
2705 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2706 IB_QP_PORT, NULL);
2707 if (ret) {
2708 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2709 goto error_4;
2710 }
2711
2712 memset(attr, 0, sizeof(*attr));
2713 attr->qp_state = IB_QPS_RTR;
2714 attr->path_mtu = IB_MTU_256;
2715
2716 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2717 if (ret) {
2718 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2719 goto error_4;
2720 }
2721
2722 memset(attr, 0, sizeof(*attr));
2723 attr->qp_state = IB_QPS_RTS;
2724 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2725 if (ret) {
2726 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2727 goto error_4;
2728 }
2729
2730 dev->umrc.qp = qp;
2731 dev->umrc.cq = cq;
2732 dev->umrc.pd = pd;
2733
2734 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2735 ret = mlx5_mr_cache_init(dev);
2736 if (ret) {
2737 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2738 goto error_4;
2739 }
2740
2741 kfree(attr);
2742 kfree(init_attr);
2743
2744 return 0;
2745
2746 error_4:
2747 mlx5_ib_destroy_qp(qp);
2748
2749 error_3:
2750 ib_free_cq(cq);
2751
2752 error_2:
2753 ib_dealloc_pd(pd);
2754
2755 error_0:
2756 kfree(attr);
2757 kfree(init_attr);
2758 return ret;
2759 }
2760
2761 static int create_dev_resources(struct mlx5_ib_resources *devr)
2762 {
2763 struct ib_srq_init_attr attr;
2764 struct mlx5_ib_dev *dev;
2765 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2766 int port;
2767 int ret = 0;
2768
2769 dev = container_of(devr, struct mlx5_ib_dev, devr);
2770
2771 mutex_init(&devr->mutex);
2772
2773 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2774 if (IS_ERR(devr->p0)) {
2775 ret = PTR_ERR(devr->p0);
2776 goto error0;
2777 }
2778 devr->p0->device = &dev->ib_dev;
2779 devr->p0->uobject = NULL;
2780 atomic_set(&devr->p0->usecnt, 0);
2781
2782 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
2783 if (IS_ERR(devr->c0)) {
2784 ret = PTR_ERR(devr->c0);
2785 goto error1;
2786 }
2787 devr->c0->device = &dev->ib_dev;
2788 devr->c0->uobject = NULL;
2789 devr->c0->comp_handler = NULL;
2790 devr->c0->event_handler = NULL;
2791 devr->c0->cq_context = NULL;
2792 atomic_set(&devr->c0->usecnt, 0);
2793
2794 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2795 if (IS_ERR(devr->x0)) {
2796 ret = PTR_ERR(devr->x0);
2797 goto error2;
2798 }
2799 devr->x0->device = &dev->ib_dev;
2800 devr->x0->inode = NULL;
2801 atomic_set(&devr->x0->usecnt, 0);
2802 mutex_init(&devr->x0->tgt_qp_mutex);
2803 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
2804
2805 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
2806 if (IS_ERR(devr->x1)) {
2807 ret = PTR_ERR(devr->x1);
2808 goto error3;
2809 }
2810 devr->x1->device = &dev->ib_dev;
2811 devr->x1->inode = NULL;
2812 atomic_set(&devr->x1->usecnt, 0);
2813 mutex_init(&devr->x1->tgt_qp_mutex);
2814 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
2815
2816 memset(&attr, 0, sizeof(attr));
2817 attr.attr.max_sge = 1;
2818 attr.attr.max_wr = 1;
2819 attr.srq_type = IB_SRQT_XRC;
2820 attr.ext.xrc.cq = devr->c0;
2821 attr.ext.xrc.xrcd = devr->x0;
2822
2823 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2824 if (IS_ERR(devr->s0)) {
2825 ret = PTR_ERR(devr->s0);
2826 goto error4;
2827 }
2828 devr->s0->device = &dev->ib_dev;
2829 devr->s0->pd = devr->p0;
2830 devr->s0->uobject = NULL;
2831 devr->s0->event_handler = NULL;
2832 devr->s0->srq_context = NULL;
2833 devr->s0->srq_type = IB_SRQT_XRC;
2834 devr->s0->ext.xrc.xrcd = devr->x0;
2835 devr->s0->ext.xrc.cq = devr->c0;
2836 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
2837 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
2838 atomic_inc(&devr->p0->usecnt);
2839 atomic_set(&devr->s0->usecnt, 0);
2840
2841 memset(&attr, 0, sizeof(attr));
2842 attr.attr.max_sge = 1;
2843 attr.attr.max_wr = 1;
2844 attr.srq_type = IB_SRQT_BASIC;
2845 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
2846 if (IS_ERR(devr->s1)) {
2847 ret = PTR_ERR(devr->s1);
2848 goto error5;
2849 }
2850 devr->s1->device = &dev->ib_dev;
2851 devr->s1->pd = devr->p0;
2852 devr->s1->uobject = NULL;
2853 devr->s1->event_handler = NULL;
2854 devr->s1->srq_context = NULL;
2855 devr->s1->srq_type = IB_SRQT_BASIC;
2856 devr->s1->ext.xrc.cq = devr->c0;
2857 atomic_inc(&devr->p0->usecnt);
2858 atomic_set(&devr->s0->usecnt, 0);
2859
2860 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
2861 INIT_WORK(&devr->ports[port].pkey_change_work,
2862 pkey_change_handler);
2863 devr->ports[port].devr = devr;
2864 }
2865
2866 return 0;
2867
2868 error5:
2869 mlx5_ib_destroy_srq(devr->s0);
2870 error4:
2871 mlx5_ib_dealloc_xrcd(devr->x1);
2872 error3:
2873 mlx5_ib_dealloc_xrcd(devr->x0);
2874 error2:
2875 mlx5_ib_destroy_cq(devr->c0);
2876 error1:
2877 mlx5_ib_dealloc_pd(devr->p0);
2878 error0:
2879 return ret;
2880 }
2881
2882 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
2883 {
2884 struct mlx5_ib_dev *dev =
2885 container_of(devr, struct mlx5_ib_dev, devr);
2886 int port;
2887
2888 mlx5_ib_destroy_srq(devr->s1);
2889 mlx5_ib_destroy_srq(devr->s0);
2890 mlx5_ib_dealloc_xrcd(devr->x0);
2891 mlx5_ib_dealloc_xrcd(devr->x1);
2892 mlx5_ib_destroy_cq(devr->c0);
2893 mlx5_ib_dealloc_pd(devr->p0);
2894
2895 /* Make sure no change P_Key work items are still executing */
2896 for (port = 0; port < dev->num_ports; ++port)
2897 cancel_work_sync(&devr->ports[port].pkey_change_work);
2898 }
2899
2900 static u32 get_core_cap_flags(struct ib_device *ibdev)
2901 {
2902 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2903 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
2904 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
2905 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
2906 u32 ret = 0;
2907
2908 if (ll == IB_LINK_LAYER_INFINIBAND)
2909 return RDMA_CORE_PORT_IBA_IB;
2910
2911 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
2912 return 0;
2913
2914 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
2915 return 0;
2916
2917 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
2918 ret |= RDMA_CORE_PORT_IBA_ROCE;
2919
2920 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
2921 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2922
2923 return ret;
2924 }
2925
2926 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
2927 struct ib_port_immutable *immutable)
2928 {
2929 struct ib_port_attr attr;
2930 struct mlx5_ib_dev *dev = to_mdev(ibdev);
2931 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
2932 int err;
2933
2934 err = mlx5_ib_query_port(ibdev, port_num, &attr);
2935 if (err)
2936 return err;
2937
2938 immutable->pkey_tbl_len = attr.pkey_tbl_len;
2939 immutable->gid_tbl_len = attr.gid_tbl_len;
2940 immutable->core_cap_flags = get_core_cap_flags(ibdev);
2941 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
2942 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2943
2944 return 0;
2945 }
2946
2947 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
2948 size_t str_len)
2949 {
2950 struct mlx5_ib_dev *dev =
2951 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
2952 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
2953 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
2954 }
2955
2956 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
2957 {
2958 struct mlx5_core_dev *mdev = dev->mdev;
2959 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
2960 MLX5_FLOW_NAMESPACE_LAG);
2961 struct mlx5_flow_table *ft;
2962 int err;
2963
2964 if (!ns || !mlx5_lag_is_active(mdev))
2965 return 0;
2966
2967 err = mlx5_cmd_create_vport_lag(mdev);
2968 if (err)
2969 return err;
2970
2971 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
2972 if (IS_ERR(ft)) {
2973 err = PTR_ERR(ft);
2974 goto err_destroy_vport_lag;
2975 }
2976
2977 dev->flow_db.lag_demux_ft = ft;
2978 return 0;
2979
2980 err_destroy_vport_lag:
2981 mlx5_cmd_destroy_vport_lag(mdev);
2982 return err;
2983 }
2984
2985 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
2986 {
2987 struct mlx5_core_dev *mdev = dev->mdev;
2988
2989 if (dev->flow_db.lag_demux_ft) {
2990 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
2991 dev->flow_db.lag_demux_ft = NULL;
2992
2993 mlx5_cmd_destroy_vport_lag(mdev);
2994 }
2995 }
2996
2997 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
2998 {
2999 int err;
3000
3001 dev->roce.nb.notifier_call = mlx5_netdev_event;
3002 err = register_netdevice_notifier(&dev->roce.nb);
3003 if (err) {
3004 dev->roce.nb.notifier_call = NULL;
3005 return err;
3006 }
3007
3008 return 0;
3009 }
3010
3011 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3012 {
3013 if (dev->roce.nb.notifier_call) {
3014 unregister_netdevice_notifier(&dev->roce.nb);
3015 dev->roce.nb.notifier_call = NULL;
3016 }
3017 }
3018
3019 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3020 {
3021 int err;
3022
3023 err = mlx5_add_netdev_notifier(dev);
3024 if (err)
3025 return err;
3026
3027 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3028 err = mlx5_nic_vport_enable_roce(dev->mdev);
3029 if (err)
3030 goto err_unregister_netdevice_notifier;
3031 }
3032
3033 err = mlx5_eth_lag_init(dev);
3034 if (err)
3035 goto err_disable_roce;
3036
3037 return 0;
3038
3039 err_disable_roce:
3040 if (MLX5_CAP_GEN(dev->mdev, roce))
3041 mlx5_nic_vport_disable_roce(dev->mdev);
3042
3043 err_unregister_netdevice_notifier:
3044 mlx5_remove_netdev_notifier(dev);
3045 return err;
3046 }
3047
3048 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3049 {
3050 mlx5_eth_lag_cleanup(dev);
3051 if (MLX5_CAP_GEN(dev->mdev, roce))
3052 mlx5_nic_vport_disable_roce(dev->mdev);
3053 }
3054
3055 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev)
3056 {
3057 unsigned int i;
3058
3059 for (i = 0; i < dev->num_ports; i++)
3060 mlx5_core_dealloc_q_counter(dev->mdev,
3061 dev->port[i].q_cnt_id);
3062 }
3063
3064 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev)
3065 {
3066 int i;
3067 int ret;
3068
3069 for (i = 0; i < dev->num_ports; i++) {
3070 ret = mlx5_core_alloc_q_counter(dev->mdev,
3071 &dev->port[i].q_cnt_id);
3072 if (ret) {
3073 mlx5_ib_warn(dev,
3074 "couldn't allocate queue counter for port %d, err %d\n",
3075 i + 1, ret);
3076 goto dealloc_counters;
3077 }
3078 }
3079
3080 return 0;
3081
3082 dealloc_counters:
3083 while (--i >= 0)
3084 mlx5_core_dealloc_q_counter(dev->mdev,
3085 dev->port[i].q_cnt_id);
3086
3087 return ret;
3088 }
3089
3090 static const char * const names[] = {
3091 "rx_write_requests",
3092 "rx_read_requests",
3093 "rx_atomic_requests",
3094 "out_of_buffer",
3095 "out_of_sequence",
3096 "duplicate_request",
3097 "rnr_nak_retry_err",
3098 "packet_seq_err",
3099 "implied_nak_seq_err",
3100 "local_ack_timeout_err",
3101 };
3102
3103 static const size_t stats_offsets[] = {
3104 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests),
3105 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests),
3106 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests),
3107 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer),
3108 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence),
3109 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request),
3110 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err),
3111 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err),
3112 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err),
3113 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err),
3114 };
3115
3116 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3117 u8 port_num)
3118 {
3119 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets));
3120
3121 /* We support only per port stats */
3122 if (port_num == 0)
3123 return NULL;
3124
3125 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names),
3126 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3127 }
3128
3129 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3130 struct rdma_hw_stats *stats,
3131 u8 port, int index)
3132 {
3133 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3134 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3135 void *out;
3136 __be32 val;
3137 int ret;
3138 int i;
3139
3140 if (!port || !stats)
3141 return -ENOSYS;
3142
3143 out = mlx5_vzalloc(outlen);
3144 if (!out)
3145 return -ENOMEM;
3146
3147 ret = mlx5_core_query_q_counter(dev->mdev,
3148 dev->port[port - 1].q_cnt_id, 0,
3149 out, outlen);
3150 if (ret)
3151 goto free;
3152
3153 for (i = 0; i < ARRAY_SIZE(names); i++) {
3154 val = *(__be32 *)(out + stats_offsets[i]);
3155 stats->value[i] = (u64)be32_to_cpu(val);
3156 }
3157 free:
3158 kvfree(out);
3159 return ARRAY_SIZE(names);
3160 }
3161
3162 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3163 {
3164 struct mlx5_ib_dev *dev;
3165 enum rdma_link_layer ll;
3166 int port_type_cap;
3167 const char *name;
3168 int err;
3169 int i;
3170
3171 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3172 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3173
3174 printk_once(KERN_INFO "%s", mlx5_version);
3175
3176 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3177 if (!dev)
3178 return NULL;
3179
3180 dev->mdev = mdev;
3181
3182 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3183 GFP_KERNEL);
3184 if (!dev->port)
3185 goto err_dealloc;
3186
3187 rwlock_init(&dev->roce.netdev_lock);
3188 err = get_port_caps(dev);
3189 if (err)
3190 goto err_free_port;
3191
3192 if (mlx5_use_mad_ifc(dev))
3193 get_ext_port_caps(dev);
3194
3195 if (!mlx5_lag_is_active(mdev))
3196 name = "mlx5_%d";
3197 else
3198 name = "mlx5_bond_%d";
3199
3200 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3201 dev->ib_dev.owner = THIS_MODULE;
3202 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3203 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3204 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
3205 dev->ib_dev.phys_port_cnt = dev->num_ports;
3206 dev->ib_dev.num_comp_vectors =
3207 dev->mdev->priv.eq_table.num_comp_vectors;
3208 dev->ib_dev.dma_device = &mdev->pdev->dev;
3209
3210 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3211 dev->ib_dev.uverbs_cmd_mask =
3212 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3213 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3214 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3215 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3216 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3217 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3218 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
3219 (1ull << IB_USER_VERBS_CMD_REG_MR) |
3220 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3221 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3222 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3223 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3224 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3225 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3226 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3227 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3228 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3229 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3230 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3231 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3232 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3233 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3234 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3235 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3236 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3237 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3238 dev->ib_dev.uverbs_ex_cmd_mask =
3239 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3240 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3241 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3242 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3243
3244 dev->ib_dev.query_device = mlx5_ib_query_device;
3245 dev->ib_dev.query_port = mlx5_ib_query_port;
3246 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3247 if (ll == IB_LINK_LAYER_ETHERNET)
3248 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3249 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3250 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3251 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3252 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3253 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3254 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3255 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3256 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3257 dev->ib_dev.mmap = mlx5_ib_mmap;
3258 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3259 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3260 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3261 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3262 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3263 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3264 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3265 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3266 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3267 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3268 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3269 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3270 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3271 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3272 dev->ib_dev.post_send = mlx5_ib_post_send;
3273 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3274 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3275 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3276 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3277 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3278 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3279 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3280 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3281 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3282 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3283 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3284 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3285 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3286 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3287 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3288 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3289 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3290 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3291 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3292 if (mlx5_core_is_pf(mdev)) {
3293 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3294 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3295 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3296 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3297 }
3298
3299 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3300
3301 mlx5_ib_internal_fill_odp_caps(dev);
3302
3303 if (MLX5_CAP_GEN(mdev, imaicl)) {
3304 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3305 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3306 dev->ib_dev.uverbs_cmd_mask |=
3307 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3308 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3309 }
3310
3311 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) &&
3312 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3313 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3314 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3315 }
3316
3317 if (MLX5_CAP_GEN(mdev, xrc)) {
3318 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3319 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3320 dev->ib_dev.uverbs_cmd_mask |=
3321 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3322 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3323 }
3324
3325 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3326 IB_LINK_LAYER_ETHERNET) {
3327 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3328 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3329 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3330 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3331 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3332 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3333 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3334 dev->ib_dev.uverbs_ex_cmd_mask |=
3335 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3336 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3337 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3338 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3339 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3340 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3341 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3342 }
3343 err = init_node_data(dev);
3344 if (err)
3345 goto err_free_port;
3346
3347 mutex_init(&dev->flow_db.lock);
3348 mutex_init(&dev->cap_mask_mutex);
3349 INIT_LIST_HEAD(&dev->qp_list);
3350 spin_lock_init(&dev->reset_flow_resource_lock);
3351
3352 if (ll == IB_LINK_LAYER_ETHERNET) {
3353 err = mlx5_enable_eth(dev);
3354 if (err)
3355 goto err_free_port;
3356 }
3357
3358 err = create_dev_resources(&dev->devr);
3359 if (err)
3360 goto err_disable_eth;
3361
3362 err = mlx5_ib_odp_init_one(dev);
3363 if (err)
3364 goto err_rsrc;
3365
3366 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3367 err = mlx5_ib_alloc_q_counters(dev);
3368 if (err)
3369 goto err_odp;
3370 }
3371
3372 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3373 if (!dev->mdev->priv.uar)
3374 goto err_q_cnt;
3375
3376 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3377 if (err)
3378 goto err_uar_page;
3379
3380 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3381 if (err)
3382 goto err_bfreg;
3383
3384 err = ib_register_device(&dev->ib_dev, NULL);
3385 if (err)
3386 goto err_fp_bfreg;
3387
3388 err = create_umr_res(dev);
3389 if (err)
3390 goto err_dev;
3391
3392 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3393 err = device_create_file(&dev->ib_dev.dev,
3394 mlx5_class_attributes[i]);
3395 if (err)
3396 goto err_umrc;
3397 }
3398
3399 dev->ib_active = true;
3400
3401 return dev;
3402
3403 err_umrc:
3404 destroy_umrc_res(dev);
3405
3406 err_dev:
3407 ib_unregister_device(&dev->ib_dev);
3408
3409 err_fp_bfreg:
3410 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3411
3412 err_bfreg:
3413 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3414
3415 err_uar_page:
3416 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3417
3418 err_q_cnt:
3419 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3420 mlx5_ib_dealloc_q_counters(dev);
3421
3422 err_odp:
3423 mlx5_ib_odp_remove_one(dev);
3424
3425 err_rsrc:
3426 destroy_dev_resources(&dev->devr);
3427
3428 err_disable_eth:
3429 if (ll == IB_LINK_LAYER_ETHERNET) {
3430 mlx5_disable_eth(dev);
3431 mlx5_remove_netdev_notifier(dev);
3432 }
3433
3434 err_free_port:
3435 kfree(dev->port);
3436
3437 err_dealloc:
3438 ib_dealloc_device((struct ib_device *)dev);
3439
3440 return NULL;
3441 }
3442
3443 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3444 {
3445 struct mlx5_ib_dev *dev = context;
3446 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3447
3448 mlx5_remove_netdev_notifier(dev);
3449 ib_unregister_device(&dev->ib_dev);
3450 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3451 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3452 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
3453 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3454 mlx5_ib_dealloc_q_counters(dev);
3455 destroy_umrc_res(dev);
3456 mlx5_ib_odp_remove_one(dev);
3457 destroy_dev_resources(&dev->devr);
3458 if (ll == IB_LINK_LAYER_ETHERNET)
3459 mlx5_disable_eth(dev);
3460 kfree(dev->port);
3461 ib_dealloc_device(&dev->ib_dev);
3462 }
3463
3464 static struct mlx5_interface mlx5_ib_interface = {
3465 .add = mlx5_ib_add,
3466 .remove = mlx5_ib_remove,
3467 .event = mlx5_ib_event,
3468 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3469 .pfault = mlx5_ib_pfault,
3470 #endif
3471 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3472 };
3473
3474 static int __init mlx5_ib_init(void)
3475 {
3476 int err;
3477
3478 err = mlx5_register_interface(&mlx5_ib_interface);
3479
3480 return err;
3481 }
3482
3483 static void __exit mlx5_ib_cleanup(void)
3484 {
3485 mlx5_unregister_interface(&mlx5_ib_interface);
3486 }
3487
3488 module_init(mlx5_ib_init);
3489 module_exit(mlx5_ib_cleanup);
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