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[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include "mlx5_ib.h"
36 #include "user.h"
37
38 /* not supported currently */
39 static int wq_signature;
40
41 enum {
42 MLX5_IB_ACK_REQ_FREQ = 8,
43 };
44
45 enum {
46 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
47 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
48 MLX5_IB_LINK_TYPE_IB = 0,
49 MLX5_IB_LINK_TYPE_ETH = 1
50 };
51
52 enum {
53 MLX5_IB_SQ_STRIDE = 6,
54 MLX5_IB_CACHE_LINE_SIZE = 64,
55 };
56
57 static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
59 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
60 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
61 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
62 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
63 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
64 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
65 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
66 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
67 [IB_WR_FAST_REG_MR] = MLX5_OPCODE_UMR,
68 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
69 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
70 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
71 };
72
73 struct umr_wr {
74 u64 virt_addr;
75 struct ib_pd *pd;
76 unsigned int page_shift;
77 unsigned int npages;
78 u32 length;
79 int access_flags;
80 u32 mkey;
81 };
82
83 static int is_qp0(enum ib_qp_type qp_type)
84 {
85 return qp_type == IB_QPT_SMI;
86 }
87
88 static int is_qp1(enum ib_qp_type qp_type)
89 {
90 return qp_type == IB_QPT_GSI;
91 }
92
93 static int is_sqp(enum ib_qp_type qp_type)
94 {
95 return is_qp0(qp_type) || is_qp1(qp_type);
96 }
97
98 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
99 {
100 return mlx5_buf_offset(&qp->buf, offset);
101 }
102
103 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
104 {
105 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
106 }
107
108 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
109 {
110 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
111 }
112
113 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
114 {
115 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
116 struct ib_event event;
117
118 if (type == MLX5_EVENT_TYPE_PATH_MIG)
119 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
120
121 if (ibqp->event_handler) {
122 event.device = ibqp->device;
123 event.element.qp = ibqp;
124 switch (type) {
125 case MLX5_EVENT_TYPE_PATH_MIG:
126 event.event = IB_EVENT_PATH_MIG;
127 break;
128 case MLX5_EVENT_TYPE_COMM_EST:
129 event.event = IB_EVENT_COMM_EST;
130 break;
131 case MLX5_EVENT_TYPE_SQ_DRAINED:
132 event.event = IB_EVENT_SQ_DRAINED;
133 break;
134 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
135 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
136 break;
137 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
138 event.event = IB_EVENT_QP_FATAL;
139 break;
140 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
141 event.event = IB_EVENT_PATH_MIG_ERR;
142 break;
143 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
144 event.event = IB_EVENT_QP_REQ_ERR;
145 break;
146 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
147 event.event = IB_EVENT_QP_ACCESS_ERR;
148 break;
149 default:
150 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
151 return;
152 }
153
154 ibqp->event_handler(&event, ibqp->qp_context);
155 }
156 }
157
158 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
159 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
160 {
161 struct mlx5_general_caps *gen;
162 int wqe_size;
163 int wq_size;
164
165 gen = &dev->mdev->caps.gen;
166 /* Sanity check RQ size before proceeding */
167 if (cap->max_recv_wr > gen->max_wqes)
168 return -EINVAL;
169
170 if (!has_rq) {
171 qp->rq.max_gs = 0;
172 qp->rq.wqe_cnt = 0;
173 qp->rq.wqe_shift = 0;
174 } else {
175 if (ucmd) {
176 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
177 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
178 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
179 qp->rq.max_post = qp->rq.wqe_cnt;
180 } else {
181 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
182 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
183 wqe_size = roundup_pow_of_two(wqe_size);
184 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
185 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
186 qp->rq.wqe_cnt = wq_size / wqe_size;
187 if (wqe_size > gen->max_rq_desc_sz) {
188 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
189 wqe_size,
190 gen->max_rq_desc_sz);
191 return -EINVAL;
192 }
193 qp->rq.wqe_shift = ilog2(wqe_size);
194 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
195 qp->rq.max_post = qp->rq.wqe_cnt;
196 }
197 }
198
199 return 0;
200 }
201
202 static int sq_overhead(enum ib_qp_type qp_type)
203 {
204 int size = 0;
205
206 switch (qp_type) {
207 case IB_QPT_XRC_INI:
208 size += sizeof(struct mlx5_wqe_xrc_seg);
209 /* fall through */
210 case IB_QPT_RC:
211 size += sizeof(struct mlx5_wqe_ctrl_seg) +
212 sizeof(struct mlx5_wqe_atomic_seg) +
213 sizeof(struct mlx5_wqe_raddr_seg);
214 break;
215
216 case IB_QPT_XRC_TGT:
217 return 0;
218
219 case IB_QPT_UC:
220 size += sizeof(struct mlx5_wqe_ctrl_seg) +
221 sizeof(struct mlx5_wqe_raddr_seg) +
222 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
223 sizeof(struct mlx5_mkey_seg);
224 break;
225
226 case IB_QPT_UD:
227 case IB_QPT_SMI:
228 case IB_QPT_GSI:
229 size += sizeof(struct mlx5_wqe_ctrl_seg) +
230 sizeof(struct mlx5_wqe_datagram_seg);
231 break;
232
233 case MLX5_IB_QPT_REG_UMR:
234 size += sizeof(struct mlx5_wqe_ctrl_seg) +
235 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
236 sizeof(struct mlx5_mkey_seg);
237 break;
238
239 default:
240 return -EINVAL;
241 }
242
243 return size;
244 }
245
246 static int calc_send_wqe(struct ib_qp_init_attr *attr)
247 {
248 int inl_size = 0;
249 int size;
250
251 size = sq_overhead(attr->qp_type);
252 if (size < 0)
253 return size;
254
255 if (attr->cap.max_inline_data) {
256 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
257 attr->cap.max_inline_data;
258 }
259
260 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
261 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
262 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
263 return MLX5_SIG_WQE_SIZE;
264 else
265 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
266 }
267
268 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
269 struct mlx5_ib_qp *qp)
270 {
271 struct mlx5_general_caps *gen;
272 int wqe_size;
273 int wq_size;
274
275 gen = &dev->mdev->caps.gen;
276 if (!attr->cap.max_send_wr)
277 return 0;
278
279 wqe_size = calc_send_wqe(attr);
280 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
281 if (wqe_size < 0)
282 return wqe_size;
283
284 if (wqe_size > gen->max_sq_desc_sz) {
285 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
286 wqe_size, gen->max_sq_desc_sz);
287 return -EINVAL;
288 }
289
290 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
291 sizeof(struct mlx5_wqe_inline_seg);
292 attr->cap.max_inline_data = qp->max_inline_data;
293
294 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
295 qp->signature_en = true;
296
297 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
298 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
299 if (qp->sq.wqe_cnt > gen->max_wqes) {
300 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
301 qp->sq.wqe_cnt, gen->max_wqes);
302 return -ENOMEM;
303 }
304 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
305 qp->sq.max_gs = attr->cap.max_send_sge;
306 qp->sq.max_post = wq_size / wqe_size;
307 attr->cap.max_send_wr = qp->sq.max_post;
308
309 return wq_size;
310 }
311
312 static int set_user_buf_size(struct mlx5_ib_dev *dev,
313 struct mlx5_ib_qp *qp,
314 struct mlx5_ib_create_qp *ucmd)
315 {
316 struct mlx5_general_caps *gen;
317 int desc_sz = 1 << qp->sq.wqe_shift;
318
319 gen = &dev->mdev->caps.gen;
320 if (desc_sz > gen->max_sq_desc_sz) {
321 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
322 desc_sz, gen->max_sq_desc_sz);
323 return -EINVAL;
324 }
325
326 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
327 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
328 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
329 return -EINVAL;
330 }
331
332 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
333
334 if (qp->sq.wqe_cnt > gen->max_wqes) {
335 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
336 qp->sq.wqe_cnt, gen->max_wqes);
337 return -EINVAL;
338 }
339
340 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
341 (qp->sq.wqe_cnt << 6);
342
343 return 0;
344 }
345
346 static int qp_has_rq(struct ib_qp_init_attr *attr)
347 {
348 if (attr->qp_type == IB_QPT_XRC_INI ||
349 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
350 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
351 !attr->cap.max_recv_wr)
352 return 0;
353
354 return 1;
355 }
356
357 static int first_med_uuar(void)
358 {
359 return 1;
360 }
361
362 static int next_uuar(int n)
363 {
364 n++;
365
366 while (((n % 4) & 2))
367 n++;
368
369 return n;
370 }
371
372 static int num_med_uuar(struct mlx5_uuar_info *uuari)
373 {
374 int n;
375
376 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
377 uuari->num_low_latency_uuars - 1;
378
379 return n >= 0 ? n : 0;
380 }
381
382 static int max_uuari(struct mlx5_uuar_info *uuari)
383 {
384 return uuari->num_uars * 4;
385 }
386
387 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
388 {
389 int med;
390 int i;
391 int t;
392
393 med = num_med_uuar(uuari);
394 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
395 t++;
396 if (t == med)
397 return next_uuar(i);
398 }
399
400 return 0;
401 }
402
403 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
404 {
405 int i;
406
407 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
408 if (!test_bit(i, uuari->bitmap)) {
409 set_bit(i, uuari->bitmap);
410 uuari->count[i]++;
411 return i;
412 }
413 }
414
415 return -ENOMEM;
416 }
417
418 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
419 {
420 int minidx = first_med_uuar();
421 int i;
422
423 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
424 if (uuari->count[i] < uuari->count[minidx])
425 minidx = i;
426 }
427
428 uuari->count[minidx]++;
429 return minidx;
430 }
431
432 static int alloc_uuar(struct mlx5_uuar_info *uuari,
433 enum mlx5_ib_latency_class lat)
434 {
435 int uuarn = -EINVAL;
436
437 mutex_lock(&uuari->lock);
438 switch (lat) {
439 case MLX5_IB_LATENCY_CLASS_LOW:
440 uuarn = 0;
441 uuari->count[uuarn]++;
442 break;
443
444 case MLX5_IB_LATENCY_CLASS_MEDIUM:
445 if (uuari->ver < 2)
446 uuarn = -ENOMEM;
447 else
448 uuarn = alloc_med_class_uuar(uuari);
449 break;
450
451 case MLX5_IB_LATENCY_CLASS_HIGH:
452 if (uuari->ver < 2)
453 uuarn = -ENOMEM;
454 else
455 uuarn = alloc_high_class_uuar(uuari);
456 break;
457
458 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
459 uuarn = 2;
460 break;
461 }
462 mutex_unlock(&uuari->lock);
463
464 return uuarn;
465 }
466
467 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
468 {
469 clear_bit(uuarn, uuari->bitmap);
470 --uuari->count[uuarn];
471 }
472
473 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
474 {
475 clear_bit(uuarn, uuari->bitmap);
476 --uuari->count[uuarn];
477 }
478
479 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
480 {
481 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
482 int high_uuar = nuuars - uuari->num_low_latency_uuars;
483
484 mutex_lock(&uuari->lock);
485 if (uuarn == 0) {
486 --uuari->count[uuarn];
487 goto out;
488 }
489
490 if (uuarn < high_uuar) {
491 free_med_class_uuar(uuari, uuarn);
492 goto out;
493 }
494
495 free_high_class_uuar(uuari, uuarn);
496
497 out:
498 mutex_unlock(&uuari->lock);
499 }
500
501 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
502 {
503 switch (state) {
504 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
505 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
506 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
507 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
508 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
509 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
510 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
511 default: return -1;
512 }
513 }
514
515 static int to_mlx5_st(enum ib_qp_type type)
516 {
517 switch (type) {
518 case IB_QPT_RC: return MLX5_QP_ST_RC;
519 case IB_QPT_UC: return MLX5_QP_ST_UC;
520 case IB_QPT_UD: return MLX5_QP_ST_UD;
521 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
522 case IB_QPT_XRC_INI:
523 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
524 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
525 case IB_QPT_GSI: return MLX5_QP_ST_QP1;
526 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
527 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
528 case IB_QPT_RAW_PACKET:
529 case IB_QPT_MAX:
530 default: return -EINVAL;
531 }
532 }
533
534 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
535 {
536 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
537 }
538
539 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
540 struct mlx5_ib_qp *qp, struct ib_udata *udata,
541 struct mlx5_create_qp_mbox_in **in,
542 struct mlx5_ib_create_qp_resp *resp, int *inlen)
543 {
544 struct mlx5_ib_ucontext *context;
545 struct mlx5_ib_create_qp ucmd;
546 int page_shift = 0;
547 int uar_index;
548 int npages;
549 u32 offset = 0;
550 int uuarn;
551 int ncont = 0;
552 int err;
553
554 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
555 if (err) {
556 mlx5_ib_dbg(dev, "copy failed\n");
557 return err;
558 }
559
560 context = to_mucontext(pd->uobject->context);
561 /*
562 * TBD: should come from the verbs when we have the API
563 */
564 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
565 if (uuarn < 0) {
566 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
567 mlx5_ib_dbg(dev, "reverting to medium latency\n");
568 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
569 if (uuarn < 0) {
570 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
571 mlx5_ib_dbg(dev, "reverting to high latency\n");
572 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
573 if (uuarn < 0) {
574 mlx5_ib_warn(dev, "uuar allocation failed\n");
575 return uuarn;
576 }
577 }
578 }
579
580 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
581 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
582
583 qp->rq.offset = 0;
584 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
585 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
586
587 err = set_user_buf_size(dev, qp, &ucmd);
588 if (err)
589 goto err_uuar;
590
591 if (ucmd.buf_addr && qp->buf_size) {
592 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
593 qp->buf_size, 0, 0);
594 if (IS_ERR(qp->umem)) {
595 mlx5_ib_dbg(dev, "umem_get failed\n");
596 err = PTR_ERR(qp->umem);
597 goto err_uuar;
598 }
599 } else {
600 qp->umem = NULL;
601 }
602
603 if (qp->umem) {
604 mlx5_ib_cont_pages(qp->umem, ucmd.buf_addr, &npages, &page_shift,
605 &ncont, NULL);
606 err = mlx5_ib_get_buf_offset(ucmd.buf_addr, page_shift, &offset);
607 if (err) {
608 mlx5_ib_warn(dev, "bad offset\n");
609 goto err_umem;
610 }
611 mlx5_ib_dbg(dev, "addr 0x%llx, size %d, npages %d, page_shift %d, ncont %d, offset %d\n",
612 ucmd.buf_addr, qp->buf_size, npages, page_shift, ncont, offset);
613 }
614
615 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
616 *in = mlx5_vzalloc(*inlen);
617 if (!*in) {
618 err = -ENOMEM;
619 goto err_umem;
620 }
621 if (qp->umem)
622 mlx5_ib_populate_pas(dev, qp->umem, page_shift, (*in)->pas, 0);
623 (*in)->ctx.log_pg_sz_remote_qpn =
624 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
625 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
626
627 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
628 resp->uuar_index = uuarn;
629 qp->uuarn = uuarn;
630
631 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
632 if (err) {
633 mlx5_ib_dbg(dev, "map failed\n");
634 goto err_free;
635 }
636
637 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
638 if (err) {
639 mlx5_ib_dbg(dev, "copy failed\n");
640 goto err_unmap;
641 }
642 qp->create_type = MLX5_QP_USER;
643
644 return 0;
645
646 err_unmap:
647 mlx5_ib_db_unmap_user(context, &qp->db);
648
649 err_free:
650 mlx5_vfree(*in);
651
652 err_umem:
653 if (qp->umem)
654 ib_umem_release(qp->umem);
655
656 err_uuar:
657 free_uuar(&context->uuari, uuarn);
658 return err;
659 }
660
661 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp)
662 {
663 struct mlx5_ib_ucontext *context;
664
665 context = to_mucontext(pd->uobject->context);
666 mlx5_ib_db_unmap_user(context, &qp->db);
667 if (qp->umem)
668 ib_umem_release(qp->umem);
669 free_uuar(&context->uuari, qp->uuarn);
670 }
671
672 static int create_kernel_qp(struct mlx5_ib_dev *dev,
673 struct ib_qp_init_attr *init_attr,
674 struct mlx5_ib_qp *qp,
675 struct mlx5_create_qp_mbox_in **in, int *inlen)
676 {
677 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
678 struct mlx5_uuar_info *uuari;
679 int uar_index;
680 int uuarn;
681 int err;
682
683 uuari = &dev->mdev->priv.uuari;
684 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
685 return -EINVAL;
686
687 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
688 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
689
690 uuarn = alloc_uuar(uuari, lc);
691 if (uuarn < 0) {
692 mlx5_ib_dbg(dev, "\n");
693 return -ENOMEM;
694 }
695
696 qp->bf = &uuari->bfs[uuarn];
697 uar_index = qp->bf->uar->index;
698
699 err = calc_sq_size(dev, init_attr, qp);
700 if (err < 0) {
701 mlx5_ib_dbg(dev, "err %d\n", err);
702 goto err_uuar;
703 }
704
705 qp->rq.offset = 0;
706 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
707 qp->buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
708
709 err = mlx5_buf_alloc(dev->mdev, qp->buf_size, PAGE_SIZE * 2, &qp->buf);
710 if (err) {
711 mlx5_ib_dbg(dev, "err %d\n", err);
712 goto err_uuar;
713 }
714
715 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
716 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
717 *in = mlx5_vzalloc(*inlen);
718 if (!*in) {
719 err = -ENOMEM;
720 goto err_buf;
721 }
722 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
723 (*in)->ctx.log_pg_sz_remote_qpn =
724 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
725 /* Set "fast registration enabled" for all kernel QPs */
726 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
727 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
728
729 mlx5_fill_page_array(&qp->buf, (*in)->pas);
730
731 err = mlx5_db_alloc(dev->mdev, &qp->db);
732 if (err) {
733 mlx5_ib_dbg(dev, "err %d\n", err);
734 goto err_free;
735 }
736
737 qp->db.db[0] = 0;
738 qp->db.db[1] = 0;
739
740 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
741 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
742 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
743 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
744 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
745
746 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
747 !qp->sq.w_list || !qp->sq.wqe_head) {
748 err = -ENOMEM;
749 goto err_wrid;
750 }
751 qp->create_type = MLX5_QP_KERNEL;
752
753 return 0;
754
755 err_wrid:
756 mlx5_db_free(dev->mdev, &qp->db);
757 kfree(qp->sq.wqe_head);
758 kfree(qp->sq.w_list);
759 kfree(qp->sq.wrid);
760 kfree(qp->sq.wr_data);
761 kfree(qp->rq.wrid);
762
763 err_free:
764 mlx5_vfree(*in);
765
766 err_buf:
767 mlx5_buf_free(dev->mdev, &qp->buf);
768
769 err_uuar:
770 free_uuar(&dev->mdev->priv.uuari, uuarn);
771 return err;
772 }
773
774 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
775 {
776 mlx5_db_free(dev->mdev, &qp->db);
777 kfree(qp->sq.wqe_head);
778 kfree(qp->sq.w_list);
779 kfree(qp->sq.wrid);
780 kfree(qp->sq.wr_data);
781 kfree(qp->rq.wrid);
782 mlx5_buf_free(dev->mdev, &qp->buf);
783 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
784 }
785
786 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
787 {
788 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
789 (attr->qp_type == IB_QPT_XRC_INI))
790 return cpu_to_be32(MLX5_SRQ_RQ);
791 else if (!qp->has_rq)
792 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
793 else
794 return cpu_to_be32(MLX5_NON_ZERO_RQ);
795 }
796
797 static int is_connected(enum ib_qp_type qp_type)
798 {
799 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
800 return 1;
801
802 return 0;
803 }
804
805 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
806 struct ib_qp_init_attr *init_attr,
807 struct ib_udata *udata, struct mlx5_ib_qp *qp)
808 {
809 struct mlx5_ib_resources *devr = &dev->devr;
810 struct mlx5_ib_create_qp_resp resp;
811 struct mlx5_create_qp_mbox_in *in;
812 struct mlx5_general_caps *gen;
813 struct mlx5_ib_create_qp ucmd;
814 int inlen = sizeof(*in);
815 int err;
816
817 gen = &dev->mdev->caps.gen;
818 mutex_init(&qp->mutex);
819 spin_lock_init(&qp->sq.lock);
820 spin_lock_init(&qp->rq.lock);
821
822 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
823 if (!(gen->flags & MLX5_DEV_CAP_FLAG_BLOCK_MCAST)) {
824 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
825 return -EINVAL;
826 } else {
827 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
828 }
829 }
830
831 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
832 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
833
834 if (pd && pd->uobject) {
835 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
836 mlx5_ib_dbg(dev, "copy failed\n");
837 return -EFAULT;
838 }
839
840 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
841 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
842 } else {
843 qp->wq_sig = !!wq_signature;
844 }
845
846 qp->has_rq = qp_has_rq(init_attr);
847 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
848 qp, (pd && pd->uobject) ? &ucmd : NULL);
849 if (err) {
850 mlx5_ib_dbg(dev, "err %d\n", err);
851 return err;
852 }
853
854 if (pd) {
855 if (pd->uobject) {
856 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
857 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
858 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
859 mlx5_ib_dbg(dev, "invalid rq params\n");
860 return -EINVAL;
861 }
862 if (ucmd.sq_wqe_count > gen->max_wqes) {
863 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
864 ucmd.sq_wqe_count, gen->max_wqes);
865 return -EINVAL;
866 }
867 err = create_user_qp(dev, pd, qp, udata, &in, &resp, &inlen);
868 if (err)
869 mlx5_ib_dbg(dev, "err %d\n", err);
870 } else {
871 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen);
872 if (err)
873 mlx5_ib_dbg(dev, "err %d\n", err);
874 else
875 qp->pa_lkey = to_mpd(pd)->pa_lkey;
876 }
877
878 if (err)
879 return err;
880 } else {
881 in = mlx5_vzalloc(sizeof(*in));
882 if (!in)
883 return -ENOMEM;
884
885 qp->create_type = MLX5_QP_EMPTY;
886 }
887
888 if (is_sqp(init_attr->qp_type))
889 qp->port = init_attr->port_num;
890
891 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
892 MLX5_QP_PM_MIGRATED << 11);
893
894 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
895 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
896 else
897 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
898
899 if (qp->wq_sig)
900 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
901
902 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
903 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
904
905 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
906 int rcqe_sz;
907 int scqe_sz;
908
909 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
910 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
911
912 if (rcqe_sz == 128)
913 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
914 else
915 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
916
917 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
918 if (scqe_sz == 128)
919 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
920 else
921 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
922 }
923 }
924
925 if (qp->rq.wqe_cnt) {
926 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
927 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
928 }
929
930 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
931
932 if (qp->sq.wqe_cnt)
933 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
934 else
935 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
936
937 /* Set default resources */
938 switch (init_attr->qp_type) {
939 case IB_QPT_XRC_TGT:
940 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
941 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
942 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
943 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
944 break;
945 case IB_QPT_XRC_INI:
946 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
947 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
948 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
949 break;
950 default:
951 if (init_attr->srq) {
952 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
953 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
954 } else {
955 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
956 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
957 }
958 }
959
960 if (init_attr->send_cq)
961 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
962
963 if (init_attr->recv_cq)
964 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
965
966 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
967
968 err = mlx5_core_create_qp(dev->mdev, &qp->mqp, in, inlen);
969 if (err) {
970 mlx5_ib_dbg(dev, "create qp failed\n");
971 goto err_create;
972 }
973
974 mlx5_vfree(in);
975 /* Hardware wants QPN written in big-endian order (after
976 * shifting) for send doorbell. Precompute this value to save
977 * a little bit when posting sends.
978 */
979 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
980
981 qp->mqp.event = mlx5_ib_qp_event;
982
983 return 0;
984
985 err_create:
986 if (qp->create_type == MLX5_QP_USER)
987 destroy_qp_user(pd, qp);
988 else if (qp->create_type == MLX5_QP_KERNEL)
989 destroy_qp_kernel(dev, qp);
990
991 mlx5_vfree(in);
992 return err;
993 }
994
995 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
996 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
997 {
998 if (send_cq) {
999 if (recv_cq) {
1000 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1001 spin_lock_irq(&send_cq->lock);
1002 spin_lock_nested(&recv_cq->lock,
1003 SINGLE_DEPTH_NESTING);
1004 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1005 spin_lock_irq(&send_cq->lock);
1006 __acquire(&recv_cq->lock);
1007 } else {
1008 spin_lock_irq(&recv_cq->lock);
1009 spin_lock_nested(&send_cq->lock,
1010 SINGLE_DEPTH_NESTING);
1011 }
1012 } else {
1013 spin_lock_irq(&send_cq->lock);
1014 }
1015 } else if (recv_cq) {
1016 spin_lock_irq(&recv_cq->lock);
1017 }
1018 }
1019
1020 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1021 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1022 {
1023 if (send_cq) {
1024 if (recv_cq) {
1025 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1026 spin_unlock(&recv_cq->lock);
1027 spin_unlock_irq(&send_cq->lock);
1028 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1029 __release(&recv_cq->lock);
1030 spin_unlock_irq(&send_cq->lock);
1031 } else {
1032 spin_unlock(&send_cq->lock);
1033 spin_unlock_irq(&recv_cq->lock);
1034 }
1035 } else {
1036 spin_unlock_irq(&send_cq->lock);
1037 }
1038 } else if (recv_cq) {
1039 spin_unlock_irq(&recv_cq->lock);
1040 }
1041 }
1042
1043 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1044 {
1045 return to_mpd(qp->ibqp.pd);
1046 }
1047
1048 static void get_cqs(struct mlx5_ib_qp *qp,
1049 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1050 {
1051 switch (qp->ibqp.qp_type) {
1052 case IB_QPT_XRC_TGT:
1053 *send_cq = NULL;
1054 *recv_cq = NULL;
1055 break;
1056 case MLX5_IB_QPT_REG_UMR:
1057 case IB_QPT_XRC_INI:
1058 *send_cq = to_mcq(qp->ibqp.send_cq);
1059 *recv_cq = NULL;
1060 break;
1061
1062 case IB_QPT_SMI:
1063 case IB_QPT_GSI:
1064 case IB_QPT_RC:
1065 case IB_QPT_UC:
1066 case IB_QPT_UD:
1067 case IB_QPT_RAW_IPV6:
1068 case IB_QPT_RAW_ETHERTYPE:
1069 *send_cq = to_mcq(qp->ibqp.send_cq);
1070 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1071 break;
1072
1073 case IB_QPT_RAW_PACKET:
1074 case IB_QPT_MAX:
1075 default:
1076 *send_cq = NULL;
1077 *recv_cq = NULL;
1078 break;
1079 }
1080 }
1081
1082 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1083 {
1084 struct mlx5_ib_cq *send_cq, *recv_cq;
1085 struct mlx5_modify_qp_mbox_in *in;
1086 int err;
1087
1088 in = kzalloc(sizeof(*in), GFP_KERNEL);
1089 if (!in)
1090 return;
1091 if (qp->state != IB_QPS_RESET)
1092 if (mlx5_core_qp_modify(dev->mdev, to_mlx5_state(qp->state),
1093 MLX5_QP_STATE_RST, in, sizeof(*in), &qp->mqp))
1094 mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1095 qp->mqp.qpn);
1096
1097 get_cqs(qp, &send_cq, &recv_cq);
1098
1099 if (qp->create_type == MLX5_QP_KERNEL) {
1100 mlx5_ib_lock_cqs(send_cq, recv_cq);
1101 __mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1102 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1103 if (send_cq != recv_cq)
1104 __mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1105 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1106 }
1107
1108 err = mlx5_core_destroy_qp(dev->mdev, &qp->mqp);
1109 if (err)
1110 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n", qp->mqp.qpn);
1111 kfree(in);
1112
1113
1114 if (qp->create_type == MLX5_QP_KERNEL)
1115 destroy_qp_kernel(dev, qp);
1116 else if (qp->create_type == MLX5_QP_USER)
1117 destroy_qp_user(&get_pd(qp)->ibpd, qp);
1118 }
1119
1120 static const char *ib_qp_type_str(enum ib_qp_type type)
1121 {
1122 switch (type) {
1123 case IB_QPT_SMI:
1124 return "IB_QPT_SMI";
1125 case IB_QPT_GSI:
1126 return "IB_QPT_GSI";
1127 case IB_QPT_RC:
1128 return "IB_QPT_RC";
1129 case IB_QPT_UC:
1130 return "IB_QPT_UC";
1131 case IB_QPT_UD:
1132 return "IB_QPT_UD";
1133 case IB_QPT_RAW_IPV6:
1134 return "IB_QPT_RAW_IPV6";
1135 case IB_QPT_RAW_ETHERTYPE:
1136 return "IB_QPT_RAW_ETHERTYPE";
1137 case IB_QPT_XRC_INI:
1138 return "IB_QPT_XRC_INI";
1139 case IB_QPT_XRC_TGT:
1140 return "IB_QPT_XRC_TGT";
1141 case IB_QPT_RAW_PACKET:
1142 return "IB_QPT_RAW_PACKET";
1143 case MLX5_IB_QPT_REG_UMR:
1144 return "MLX5_IB_QPT_REG_UMR";
1145 case IB_QPT_MAX:
1146 default:
1147 return "Invalid QP type";
1148 }
1149 }
1150
1151 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1152 struct ib_qp_init_attr *init_attr,
1153 struct ib_udata *udata)
1154 {
1155 struct mlx5_general_caps *gen;
1156 struct mlx5_ib_dev *dev;
1157 struct mlx5_ib_qp *qp;
1158 u16 xrcdn = 0;
1159 int err;
1160
1161 if (pd) {
1162 dev = to_mdev(pd->device);
1163 } else {
1164 /* being cautious here */
1165 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1166 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1167 pr_warn("%s: no PD for transport %s\n", __func__,
1168 ib_qp_type_str(init_attr->qp_type));
1169 return ERR_PTR(-EINVAL);
1170 }
1171 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1172 }
1173 gen = &dev->mdev->caps.gen;
1174
1175 switch (init_attr->qp_type) {
1176 case IB_QPT_XRC_TGT:
1177 case IB_QPT_XRC_INI:
1178 if (!(gen->flags & MLX5_DEV_CAP_FLAG_XRC)) {
1179 mlx5_ib_dbg(dev, "XRC not supported\n");
1180 return ERR_PTR(-ENOSYS);
1181 }
1182 init_attr->recv_cq = NULL;
1183 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1184 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1185 init_attr->send_cq = NULL;
1186 }
1187
1188 /* fall through */
1189 case IB_QPT_RC:
1190 case IB_QPT_UC:
1191 case IB_QPT_UD:
1192 case IB_QPT_SMI:
1193 case IB_QPT_GSI:
1194 case MLX5_IB_QPT_REG_UMR:
1195 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1196 if (!qp)
1197 return ERR_PTR(-ENOMEM);
1198
1199 err = create_qp_common(dev, pd, init_attr, udata, qp);
1200 if (err) {
1201 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1202 kfree(qp);
1203 return ERR_PTR(err);
1204 }
1205
1206 if (is_qp0(init_attr->qp_type))
1207 qp->ibqp.qp_num = 0;
1208 else if (is_qp1(init_attr->qp_type))
1209 qp->ibqp.qp_num = 1;
1210 else
1211 qp->ibqp.qp_num = qp->mqp.qpn;
1212
1213 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1214 qp->ibqp.qp_num, qp->mqp.qpn, to_mcq(init_attr->recv_cq)->mcq.cqn,
1215 to_mcq(init_attr->send_cq)->mcq.cqn);
1216
1217 qp->xrcdn = xrcdn;
1218
1219 break;
1220
1221 case IB_QPT_RAW_IPV6:
1222 case IB_QPT_RAW_ETHERTYPE:
1223 case IB_QPT_RAW_PACKET:
1224 case IB_QPT_MAX:
1225 default:
1226 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1227 init_attr->qp_type);
1228 /* Don't support raw QPs */
1229 return ERR_PTR(-EINVAL);
1230 }
1231
1232 return &qp->ibqp;
1233 }
1234
1235 int mlx5_ib_destroy_qp(struct ib_qp *qp)
1236 {
1237 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1238 struct mlx5_ib_qp *mqp = to_mqp(qp);
1239
1240 destroy_qp_common(dev, mqp);
1241
1242 kfree(mqp);
1243
1244 return 0;
1245 }
1246
1247 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1248 int attr_mask)
1249 {
1250 u32 hw_access_flags = 0;
1251 u8 dest_rd_atomic;
1252 u32 access_flags;
1253
1254 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1255 dest_rd_atomic = attr->max_dest_rd_atomic;
1256 else
1257 dest_rd_atomic = qp->resp_depth;
1258
1259 if (attr_mask & IB_QP_ACCESS_FLAGS)
1260 access_flags = attr->qp_access_flags;
1261 else
1262 access_flags = qp->atomic_rd_en;
1263
1264 if (!dest_rd_atomic)
1265 access_flags &= IB_ACCESS_REMOTE_WRITE;
1266
1267 if (access_flags & IB_ACCESS_REMOTE_READ)
1268 hw_access_flags |= MLX5_QP_BIT_RRE;
1269 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1270 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1271 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1272 hw_access_flags |= MLX5_QP_BIT_RWE;
1273
1274 return cpu_to_be32(hw_access_flags);
1275 }
1276
1277 enum {
1278 MLX5_PATH_FLAG_FL = 1 << 0,
1279 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1280 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1281 };
1282
1283 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1284 {
1285 struct mlx5_general_caps *gen;
1286
1287 gen = &dev->mdev->caps.gen;
1288 if (rate == IB_RATE_PORT_CURRENT) {
1289 return 0;
1290 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1291 return -EINVAL;
1292 } else {
1293 while (rate != IB_RATE_2_5_GBPS &&
1294 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1295 gen->stat_rate_support))
1296 --rate;
1297 }
1298
1299 return rate + MLX5_STAT_RATE_OFFSET;
1300 }
1301
1302 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1303 struct mlx5_qp_path *path, u8 port, int attr_mask,
1304 u32 path_flags, const struct ib_qp_attr *attr)
1305 {
1306 struct mlx5_general_caps *gen;
1307 int err;
1308
1309 gen = &dev->mdev->caps.gen;
1310 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1311 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 : 0;
1312
1313 if (attr_mask & IB_QP_PKEY_INDEX)
1314 path->pkey_index = attr->pkey_index;
1315
1316 path->grh_mlid = ah->src_path_bits & 0x7f;
1317 path->rlid = cpu_to_be16(ah->dlid);
1318
1319 if (ah->ah_flags & IB_AH_GRH) {
1320 path->grh_mlid |= 1 << 7;
1321 path->mgid_index = ah->grh.sgid_index;
1322 path->hop_limit = ah->grh.hop_limit;
1323 path->tclass_flowlabel =
1324 cpu_to_be32((ah->grh.traffic_class << 20) |
1325 (ah->grh.flow_label));
1326 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1327 }
1328
1329 err = ib_rate_to_mlx5(dev, ah->static_rate);
1330 if (err < 0)
1331 return err;
1332 path->static_rate = err;
1333 path->port = port;
1334
1335 if (ah->ah_flags & IB_AH_GRH) {
1336 if (ah->grh.sgid_index >= gen->port[port - 1].gid_table_len) {
1337 pr_err(KERN_ERR "sgid_index (%u) too large. max is %d\n",
1338 ah->grh.sgid_index, gen->port[port - 1].gid_table_len);
1339 return -EINVAL;
1340 }
1341
1342 path->grh_mlid |= 1 << 7;
1343 path->mgid_index = ah->grh.sgid_index;
1344 path->hop_limit = ah->grh.hop_limit;
1345 path->tclass_flowlabel =
1346 cpu_to_be32((ah->grh.traffic_class << 20) |
1347 (ah->grh.flow_label));
1348 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1349 }
1350
1351 if (attr_mask & IB_QP_TIMEOUT)
1352 path->ackto_lt = attr->timeout << 3;
1353
1354 path->sl = ah->sl & 0xf;
1355
1356 return 0;
1357 }
1358
1359 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1360 [MLX5_QP_STATE_INIT] = {
1361 [MLX5_QP_STATE_INIT] = {
1362 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1363 MLX5_QP_OPTPAR_RAE |
1364 MLX5_QP_OPTPAR_RWE |
1365 MLX5_QP_OPTPAR_PKEY_INDEX |
1366 MLX5_QP_OPTPAR_PRI_PORT,
1367 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1368 MLX5_QP_OPTPAR_PKEY_INDEX |
1369 MLX5_QP_OPTPAR_PRI_PORT,
1370 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1371 MLX5_QP_OPTPAR_Q_KEY |
1372 MLX5_QP_OPTPAR_PRI_PORT,
1373 },
1374 [MLX5_QP_STATE_RTR] = {
1375 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1376 MLX5_QP_OPTPAR_RRE |
1377 MLX5_QP_OPTPAR_RAE |
1378 MLX5_QP_OPTPAR_RWE |
1379 MLX5_QP_OPTPAR_PKEY_INDEX,
1380 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1381 MLX5_QP_OPTPAR_RWE |
1382 MLX5_QP_OPTPAR_PKEY_INDEX,
1383 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1384 MLX5_QP_OPTPAR_Q_KEY,
1385 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
1386 MLX5_QP_OPTPAR_Q_KEY,
1387 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1388 MLX5_QP_OPTPAR_RRE |
1389 MLX5_QP_OPTPAR_RAE |
1390 MLX5_QP_OPTPAR_RWE |
1391 MLX5_QP_OPTPAR_PKEY_INDEX,
1392 },
1393 },
1394 [MLX5_QP_STATE_RTR] = {
1395 [MLX5_QP_STATE_RTS] = {
1396 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1397 MLX5_QP_OPTPAR_RRE |
1398 MLX5_QP_OPTPAR_RAE |
1399 MLX5_QP_OPTPAR_RWE |
1400 MLX5_QP_OPTPAR_PM_STATE |
1401 MLX5_QP_OPTPAR_RNR_TIMEOUT,
1402 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1403 MLX5_QP_OPTPAR_RWE |
1404 MLX5_QP_OPTPAR_PM_STATE,
1405 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1406 },
1407 },
1408 [MLX5_QP_STATE_RTS] = {
1409 [MLX5_QP_STATE_RTS] = {
1410 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1411 MLX5_QP_OPTPAR_RAE |
1412 MLX5_QP_OPTPAR_RWE |
1413 MLX5_QP_OPTPAR_RNR_TIMEOUT |
1414 MLX5_QP_OPTPAR_PM_STATE |
1415 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1416 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1417 MLX5_QP_OPTPAR_PM_STATE |
1418 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1419 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
1420 MLX5_QP_OPTPAR_SRQN |
1421 MLX5_QP_OPTPAR_CQN_RCV,
1422 },
1423 },
1424 [MLX5_QP_STATE_SQER] = {
1425 [MLX5_QP_STATE_RTS] = {
1426 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1427 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
1428 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
1429 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
1430 MLX5_QP_OPTPAR_RWE |
1431 MLX5_QP_OPTPAR_RAE |
1432 MLX5_QP_OPTPAR_RRE,
1433 },
1434 },
1435 };
1436
1437 static int ib_nr_to_mlx5_nr(int ib_mask)
1438 {
1439 switch (ib_mask) {
1440 case IB_QP_STATE:
1441 return 0;
1442 case IB_QP_CUR_STATE:
1443 return 0;
1444 case IB_QP_EN_SQD_ASYNC_NOTIFY:
1445 return 0;
1446 case IB_QP_ACCESS_FLAGS:
1447 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1448 MLX5_QP_OPTPAR_RAE;
1449 case IB_QP_PKEY_INDEX:
1450 return MLX5_QP_OPTPAR_PKEY_INDEX;
1451 case IB_QP_PORT:
1452 return MLX5_QP_OPTPAR_PRI_PORT;
1453 case IB_QP_QKEY:
1454 return MLX5_QP_OPTPAR_Q_KEY;
1455 case IB_QP_AV:
1456 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1457 MLX5_QP_OPTPAR_PRI_PORT;
1458 case IB_QP_PATH_MTU:
1459 return 0;
1460 case IB_QP_TIMEOUT:
1461 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1462 case IB_QP_RETRY_CNT:
1463 return MLX5_QP_OPTPAR_RETRY_COUNT;
1464 case IB_QP_RNR_RETRY:
1465 return MLX5_QP_OPTPAR_RNR_RETRY;
1466 case IB_QP_RQ_PSN:
1467 return 0;
1468 case IB_QP_MAX_QP_RD_ATOMIC:
1469 return MLX5_QP_OPTPAR_SRA_MAX;
1470 case IB_QP_ALT_PATH:
1471 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1472 case IB_QP_MIN_RNR_TIMER:
1473 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1474 case IB_QP_SQ_PSN:
1475 return 0;
1476 case IB_QP_MAX_DEST_RD_ATOMIC:
1477 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1478 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1479 case IB_QP_PATH_MIG_STATE:
1480 return MLX5_QP_OPTPAR_PM_STATE;
1481 case IB_QP_CAP:
1482 return 0;
1483 case IB_QP_DEST_QPN:
1484 return 0;
1485 }
1486 return 0;
1487 }
1488
1489 static int ib_mask_to_mlx5_opt(int ib_mask)
1490 {
1491 int result = 0;
1492 int i;
1493
1494 for (i = 0; i < 8 * sizeof(int); i++) {
1495 if ((1 << i) & ib_mask)
1496 result |= ib_nr_to_mlx5_nr(1 << i);
1497 }
1498
1499 return result;
1500 }
1501
1502 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1503 const struct ib_qp_attr *attr, int attr_mask,
1504 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1505 {
1506 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1507 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1508 struct mlx5_ib_cq *send_cq, *recv_cq;
1509 struct mlx5_qp_context *context;
1510 struct mlx5_general_caps *gen;
1511 struct mlx5_modify_qp_mbox_in *in;
1512 struct mlx5_ib_pd *pd;
1513 enum mlx5_qp_state mlx5_cur, mlx5_new;
1514 enum mlx5_qp_optpar optpar;
1515 int sqd_event;
1516 int mlx5_st;
1517 int err;
1518
1519 gen = &dev->mdev->caps.gen;
1520 in = kzalloc(sizeof(*in), GFP_KERNEL);
1521 if (!in)
1522 return -ENOMEM;
1523
1524 context = &in->ctx;
1525 err = to_mlx5_st(ibqp->qp_type);
1526 if (err < 0)
1527 goto out;
1528
1529 context->flags = cpu_to_be32(err << 16);
1530
1531 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1532 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1533 } else {
1534 switch (attr->path_mig_state) {
1535 case IB_MIG_MIGRATED:
1536 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1537 break;
1538 case IB_MIG_REARM:
1539 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1540 break;
1541 case IB_MIG_ARMED:
1542 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1543 break;
1544 }
1545 }
1546
1547 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
1548 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
1549 } else if (ibqp->qp_type == IB_QPT_UD ||
1550 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
1551 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
1552 } else if (attr_mask & IB_QP_PATH_MTU) {
1553 if (attr->path_mtu < IB_MTU_256 ||
1554 attr->path_mtu > IB_MTU_4096) {
1555 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
1556 err = -EINVAL;
1557 goto out;
1558 }
1559 context->mtu_msgmax = (attr->path_mtu << 5) | gen->log_max_msg;
1560 }
1561
1562 if (attr_mask & IB_QP_DEST_QPN)
1563 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
1564
1565 if (attr_mask & IB_QP_PKEY_INDEX)
1566 context->pri_path.pkey_index = attr->pkey_index;
1567
1568 /* todo implement counter_index functionality */
1569
1570 if (is_sqp(ibqp->qp_type))
1571 context->pri_path.port = qp->port;
1572
1573 if (attr_mask & IB_QP_PORT)
1574 context->pri_path.port = attr->port_num;
1575
1576 if (attr_mask & IB_QP_AV) {
1577 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
1578 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
1579 attr_mask, 0, attr);
1580 if (err)
1581 goto out;
1582 }
1583
1584 if (attr_mask & IB_QP_TIMEOUT)
1585 context->pri_path.ackto_lt |= attr->timeout << 3;
1586
1587 if (attr_mask & IB_QP_ALT_PATH) {
1588 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
1589 attr->alt_port_num, attr_mask, 0, attr);
1590 if (err)
1591 goto out;
1592 }
1593
1594 pd = get_pd(qp);
1595 get_cqs(qp, &send_cq, &recv_cq);
1596
1597 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
1598 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
1599 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
1600 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
1601
1602 if (attr_mask & IB_QP_RNR_RETRY)
1603 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1604
1605 if (attr_mask & IB_QP_RETRY_CNT)
1606 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1607
1608 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1609 if (attr->max_rd_atomic)
1610 context->params1 |=
1611 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1612 }
1613
1614 if (attr_mask & IB_QP_SQ_PSN)
1615 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1616
1617 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1618 if (attr->max_dest_rd_atomic)
1619 context->params2 |=
1620 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1621 }
1622
1623 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
1624 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
1625
1626 if (attr_mask & IB_QP_MIN_RNR_TIMER)
1627 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1628
1629 if (attr_mask & IB_QP_RQ_PSN)
1630 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1631
1632 if (attr_mask & IB_QP_QKEY)
1633 context->qkey = cpu_to_be32(attr->qkey);
1634
1635 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1636 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1637
1638 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1639 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1640 sqd_event = 1;
1641 else
1642 sqd_event = 0;
1643
1644 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1645 context->sq_crq_size |= cpu_to_be16(1 << 4);
1646
1647
1648 mlx5_cur = to_mlx5_state(cur_state);
1649 mlx5_new = to_mlx5_state(new_state);
1650 mlx5_st = to_mlx5_st(ibqp->qp_type);
1651 if (mlx5_st < 0)
1652 goto out;
1653
1654 optpar = ib_mask_to_mlx5_opt(attr_mask);
1655 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
1656 in->optparam = cpu_to_be32(optpar);
1657 err = mlx5_core_qp_modify(dev->mdev, to_mlx5_state(cur_state),
1658 to_mlx5_state(new_state), in, sqd_event,
1659 &qp->mqp);
1660 if (err)
1661 goto out;
1662
1663 qp->state = new_state;
1664
1665 if (attr_mask & IB_QP_ACCESS_FLAGS)
1666 qp->atomic_rd_en = attr->qp_access_flags;
1667 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1668 qp->resp_depth = attr->max_dest_rd_atomic;
1669 if (attr_mask & IB_QP_PORT)
1670 qp->port = attr->port_num;
1671 if (attr_mask & IB_QP_ALT_PATH)
1672 qp->alt_port = attr->alt_port_num;
1673
1674 /*
1675 * If we moved a kernel QP to RESET, clean up all old CQ
1676 * entries and reinitialize the QP.
1677 */
1678 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1679 mlx5_ib_cq_clean(recv_cq, qp->mqp.qpn,
1680 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
1681 if (send_cq != recv_cq)
1682 mlx5_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1683
1684 qp->rq.head = 0;
1685 qp->rq.tail = 0;
1686 qp->sq.head = 0;
1687 qp->sq.tail = 0;
1688 qp->sq.cur_post = 0;
1689 qp->sq.last_poll = 0;
1690 qp->db.db[MLX5_RCV_DBR] = 0;
1691 qp->db.db[MLX5_SND_DBR] = 0;
1692 }
1693
1694 out:
1695 kfree(in);
1696 return err;
1697 }
1698
1699 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1700 int attr_mask, struct ib_udata *udata)
1701 {
1702 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1703 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1704 enum ib_qp_state cur_state, new_state;
1705 struct mlx5_general_caps *gen;
1706 int err = -EINVAL;
1707 int port;
1708
1709 gen = &dev->mdev->caps.gen;
1710 mutex_lock(&qp->mutex);
1711
1712 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1713 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1714
1715 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
1716 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
1717 IB_LINK_LAYER_UNSPECIFIED))
1718 goto out;
1719
1720 if ((attr_mask & IB_QP_PORT) &&
1721 (attr->port_num == 0 || attr->port_num > gen->num_ports))
1722 goto out;
1723
1724 if (attr_mask & IB_QP_PKEY_INDEX) {
1725 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1726 if (attr->pkey_index >= gen->port[port - 1].pkey_table_len)
1727 goto out;
1728 }
1729
1730 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1731 attr->max_rd_atomic > (1 << gen->log_max_ra_res_qp))
1732 goto out;
1733
1734 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1735 attr->max_dest_rd_atomic > (1 << gen->log_max_ra_req_qp))
1736 goto out;
1737
1738 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1739 err = 0;
1740 goto out;
1741 }
1742
1743 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1744
1745 out:
1746 mutex_unlock(&qp->mutex);
1747 return err;
1748 }
1749
1750 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1751 {
1752 struct mlx5_ib_cq *cq;
1753 unsigned cur;
1754
1755 cur = wq->head - wq->tail;
1756 if (likely(cur + nreq < wq->max_post))
1757 return 0;
1758
1759 cq = to_mcq(ib_cq);
1760 spin_lock(&cq->lock);
1761 cur = wq->head - wq->tail;
1762 spin_unlock(&cq->lock);
1763
1764 return cur + nreq >= wq->max_post;
1765 }
1766
1767 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
1768 u64 remote_addr, u32 rkey)
1769 {
1770 rseg->raddr = cpu_to_be64(remote_addr);
1771 rseg->rkey = cpu_to_be32(rkey);
1772 rseg->reserved = 0;
1773 }
1774
1775 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
1776 struct ib_send_wr *wr)
1777 {
1778 memcpy(&dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof(struct mlx5_av));
1779 dseg->av.dqp_dct = cpu_to_be32(wr->wr.ud.remote_qpn | MLX5_EXTENDED_UD_AV);
1780 dseg->av.key.qkey.qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1781 }
1782
1783 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
1784 {
1785 dseg->byte_count = cpu_to_be32(sg->length);
1786 dseg->lkey = cpu_to_be32(sg->lkey);
1787 dseg->addr = cpu_to_be64(sg->addr);
1788 }
1789
1790 static __be16 get_klm_octo(int npages)
1791 {
1792 return cpu_to_be16(ALIGN(npages, 8) / 2);
1793 }
1794
1795 static __be64 frwr_mkey_mask(void)
1796 {
1797 u64 result;
1798
1799 result = MLX5_MKEY_MASK_LEN |
1800 MLX5_MKEY_MASK_PAGE_SIZE |
1801 MLX5_MKEY_MASK_START_ADDR |
1802 MLX5_MKEY_MASK_EN_RINVAL |
1803 MLX5_MKEY_MASK_KEY |
1804 MLX5_MKEY_MASK_LR |
1805 MLX5_MKEY_MASK_LW |
1806 MLX5_MKEY_MASK_RR |
1807 MLX5_MKEY_MASK_RW |
1808 MLX5_MKEY_MASK_A |
1809 MLX5_MKEY_MASK_SMALL_FENCE |
1810 MLX5_MKEY_MASK_FREE;
1811
1812 return cpu_to_be64(result);
1813 }
1814
1815 static __be64 sig_mkey_mask(void)
1816 {
1817 u64 result;
1818
1819 result = MLX5_MKEY_MASK_LEN |
1820 MLX5_MKEY_MASK_PAGE_SIZE |
1821 MLX5_MKEY_MASK_START_ADDR |
1822 MLX5_MKEY_MASK_EN_SIGERR |
1823 MLX5_MKEY_MASK_EN_RINVAL |
1824 MLX5_MKEY_MASK_KEY |
1825 MLX5_MKEY_MASK_LR |
1826 MLX5_MKEY_MASK_LW |
1827 MLX5_MKEY_MASK_RR |
1828 MLX5_MKEY_MASK_RW |
1829 MLX5_MKEY_MASK_SMALL_FENCE |
1830 MLX5_MKEY_MASK_FREE |
1831 MLX5_MKEY_MASK_BSF_EN;
1832
1833 return cpu_to_be64(result);
1834 }
1835
1836 static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1837 struct ib_send_wr *wr, int li)
1838 {
1839 memset(umr, 0, sizeof(*umr));
1840
1841 if (li) {
1842 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
1843 umr->flags = 1 << 7;
1844 return;
1845 }
1846
1847 umr->flags = (1 << 5); /* fail if not free */
1848 umr->klm_octowords = get_klm_octo(wr->wr.fast_reg.page_list_len);
1849 umr->mkey_mask = frwr_mkey_mask();
1850 }
1851
1852 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
1853 struct ib_send_wr *wr)
1854 {
1855 struct umr_wr *umrwr = (struct umr_wr *)&wr->wr.fast_reg;
1856 u64 mask;
1857
1858 memset(umr, 0, sizeof(*umr));
1859
1860 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
1861 umr->flags = 1 << 5; /* fail if not free */
1862 umr->klm_octowords = get_klm_octo(umrwr->npages);
1863 mask = MLX5_MKEY_MASK_LEN |
1864 MLX5_MKEY_MASK_PAGE_SIZE |
1865 MLX5_MKEY_MASK_START_ADDR |
1866 MLX5_MKEY_MASK_PD |
1867 MLX5_MKEY_MASK_LR |
1868 MLX5_MKEY_MASK_LW |
1869 MLX5_MKEY_MASK_KEY |
1870 MLX5_MKEY_MASK_RR |
1871 MLX5_MKEY_MASK_RW |
1872 MLX5_MKEY_MASK_A |
1873 MLX5_MKEY_MASK_FREE;
1874 umr->mkey_mask = cpu_to_be64(mask);
1875 } else {
1876 umr->flags = 2 << 5; /* fail if free */
1877 mask = MLX5_MKEY_MASK_FREE;
1878 umr->mkey_mask = cpu_to_be64(mask);
1879 }
1880
1881 if (!wr->num_sge)
1882 umr->flags |= (1 << 7); /* inline */
1883 }
1884
1885 static u8 get_umr_flags(int acc)
1886 {
1887 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
1888 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
1889 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
1890 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
1891 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
1892 }
1893
1894 static void set_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr,
1895 int li, int *writ)
1896 {
1897 memset(seg, 0, sizeof(*seg));
1898 if (li) {
1899 seg->status = 1 << 6;
1900 return;
1901 }
1902
1903 seg->flags = get_umr_flags(wr->wr.fast_reg.access_flags) |
1904 MLX5_ACCESS_MODE_MTT;
1905 *writ = seg->flags & (MLX5_PERM_LOCAL_WRITE | IB_ACCESS_REMOTE_WRITE);
1906 seg->qpn_mkey7_0 = cpu_to_be32((wr->wr.fast_reg.rkey & 0xff) | 0xffffff00);
1907 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
1908 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1909 seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1910 seg->xlt_oct_size = cpu_to_be32((wr->wr.fast_reg.page_list_len + 1) / 2);
1911 seg->log2_page_size = wr->wr.fast_reg.page_shift;
1912 }
1913
1914 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
1915 {
1916 memset(seg, 0, sizeof(*seg));
1917 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
1918 seg->status = 1 << 6;
1919 return;
1920 }
1921
1922 seg->flags = convert_access(wr->wr.fast_reg.access_flags);
1923 seg->flags_pd = cpu_to_be32(to_mpd((struct ib_pd *)wr->wr.fast_reg.page_list)->pdn);
1924 seg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1925 seg->len = cpu_to_be64(wr->wr.fast_reg.length);
1926 seg->log2_page_size = wr->wr.fast_reg.page_shift;
1927 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
1928 mlx5_mkey_variant(wr->wr.fast_reg.rkey));
1929 }
1930
1931 static void set_frwr_pages(struct mlx5_wqe_data_seg *dseg,
1932 struct ib_send_wr *wr,
1933 struct mlx5_core_dev *mdev,
1934 struct mlx5_ib_pd *pd,
1935 int writ)
1936 {
1937 struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1938 u64 *page_list = wr->wr.fast_reg.page_list->page_list;
1939 u64 perm = MLX5_EN_RD | (writ ? MLX5_EN_WR : 0);
1940 int i;
1941
1942 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++)
1943 mfrpl->mapped_page_list[i] = cpu_to_be64(page_list[i] | perm);
1944 dseg->addr = cpu_to_be64(mfrpl->map);
1945 dseg->byte_count = cpu_to_be32(ALIGN(sizeof(u64) * wr->wr.fast_reg.page_list_len, 64));
1946 dseg->lkey = cpu_to_be32(pd->pa_lkey);
1947 }
1948
1949 static __be32 send_ieth(struct ib_send_wr *wr)
1950 {
1951 switch (wr->opcode) {
1952 case IB_WR_SEND_WITH_IMM:
1953 case IB_WR_RDMA_WRITE_WITH_IMM:
1954 return wr->ex.imm_data;
1955
1956 case IB_WR_SEND_WITH_INV:
1957 return cpu_to_be32(wr->ex.invalidate_rkey);
1958
1959 default:
1960 return 0;
1961 }
1962 }
1963
1964 static u8 calc_sig(void *wqe, int size)
1965 {
1966 u8 *p = wqe;
1967 u8 res = 0;
1968 int i;
1969
1970 for (i = 0; i < size; i++)
1971 res ^= p[i];
1972
1973 return ~res;
1974 }
1975
1976 static u8 wq_sig(void *wqe)
1977 {
1978 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
1979 }
1980
1981 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
1982 void *wqe, int *sz)
1983 {
1984 struct mlx5_wqe_inline_seg *seg;
1985 void *qend = qp->sq.qend;
1986 void *addr;
1987 int inl = 0;
1988 int copy;
1989 int len;
1990 int i;
1991
1992 seg = wqe;
1993 wqe += sizeof(*seg);
1994 for (i = 0; i < wr->num_sge; i++) {
1995 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
1996 len = wr->sg_list[i].length;
1997 inl += len;
1998
1999 if (unlikely(inl > qp->max_inline_data))
2000 return -ENOMEM;
2001
2002 if (unlikely(wqe + len > qend)) {
2003 copy = qend - wqe;
2004 memcpy(wqe, addr, copy);
2005 addr += copy;
2006 len -= copy;
2007 wqe = mlx5_get_send_wqe(qp, 0);
2008 }
2009 memcpy(wqe, addr, len);
2010 wqe += len;
2011 }
2012
2013 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2014
2015 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2016
2017 return 0;
2018 }
2019
2020 static u16 prot_field_size(enum ib_signature_type type)
2021 {
2022 switch (type) {
2023 case IB_SIG_TYPE_T10_DIF:
2024 return MLX5_DIF_SIZE;
2025 default:
2026 return 0;
2027 }
2028 }
2029
2030 static u8 bs_selector(int block_size)
2031 {
2032 switch (block_size) {
2033 case 512: return 0x1;
2034 case 520: return 0x2;
2035 case 4096: return 0x3;
2036 case 4160: return 0x4;
2037 case 1073741824: return 0x5;
2038 default: return 0;
2039 }
2040 }
2041
2042 static int format_selector(struct ib_sig_attrs *attr,
2043 struct ib_sig_domain *domain,
2044 int *selector)
2045 {
2046
2047 #define FORMAT_DIF_NONE 0
2048 #define FORMAT_DIF_CRC_INC 8
2049 #define FORMAT_DIF_CRC_NO_INC 12
2050 #define FORMAT_DIF_CSUM_INC 13
2051 #define FORMAT_DIF_CSUM_NO_INC 14
2052
2053 switch (domain->sig.dif.type) {
2054 case IB_T10DIF_NONE:
2055 /* No DIF */
2056 *selector = FORMAT_DIF_NONE;
2057 break;
2058 case IB_T10DIF_TYPE1: /* Fall through */
2059 case IB_T10DIF_TYPE2:
2060 switch (domain->sig.dif.bg_type) {
2061 case IB_T10DIF_CRC:
2062 *selector = FORMAT_DIF_CRC_INC;
2063 break;
2064 case IB_T10DIF_CSUM:
2065 *selector = FORMAT_DIF_CSUM_INC;
2066 break;
2067 default:
2068 return 1;
2069 }
2070 break;
2071 case IB_T10DIF_TYPE3:
2072 switch (domain->sig.dif.bg_type) {
2073 case IB_T10DIF_CRC:
2074 *selector = domain->sig.dif.type3_inc_reftag ?
2075 FORMAT_DIF_CRC_INC :
2076 FORMAT_DIF_CRC_NO_INC;
2077 break;
2078 case IB_T10DIF_CSUM:
2079 *selector = domain->sig.dif.type3_inc_reftag ?
2080 FORMAT_DIF_CSUM_INC :
2081 FORMAT_DIF_CSUM_NO_INC;
2082 break;
2083 default:
2084 return 1;
2085 }
2086 break;
2087 default:
2088 return 1;
2089 }
2090
2091 return 0;
2092 }
2093
2094 static int mlx5_set_bsf(struct ib_mr *sig_mr,
2095 struct ib_sig_attrs *sig_attrs,
2096 struct mlx5_bsf *bsf, u32 data_size)
2097 {
2098 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
2099 struct mlx5_bsf_basic *basic = &bsf->basic;
2100 struct ib_sig_domain *mem = &sig_attrs->mem;
2101 struct ib_sig_domain *wire = &sig_attrs->wire;
2102 int ret, selector;
2103
2104 memset(bsf, 0, sizeof(*bsf));
2105 switch (sig_attrs->mem.sig_type) {
2106 case IB_SIG_TYPE_T10_DIF:
2107 if (sig_attrs->wire.sig_type != IB_SIG_TYPE_T10_DIF)
2108 return -EINVAL;
2109
2110 /* Input domain check byte mask */
2111 basic->check_byte_mask = sig_attrs->check_mask;
2112 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
2113 mem->sig.dif.type == wire->sig.dif.type) {
2114 /* Same block structure */
2115 basic->bsf_size_sbs = 1 << 4;
2116 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
2117 basic->wire.copy_byte_mask |= 0xc0;
2118 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
2119 basic->wire.copy_byte_mask |= 0x30;
2120 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
2121 basic->wire.copy_byte_mask |= 0x0f;
2122 } else
2123 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
2124
2125 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2126 basic->raw_data_size = cpu_to_be32(data_size);
2127
2128 ret = format_selector(sig_attrs, mem, &selector);
2129 if (ret)
2130 return -EINVAL;
2131 basic->m_bfs_psv = cpu_to_be32(selector << 24 |
2132 msig->psv_memory.psv_idx);
2133
2134 ret = format_selector(sig_attrs, wire, &selector);
2135 if (ret)
2136 return -EINVAL;
2137 basic->w_bfs_psv = cpu_to_be32(selector << 24 |
2138 msig->psv_wire.psv_idx);
2139 break;
2140
2141 default:
2142 return -EINVAL;
2143 }
2144
2145 return 0;
2146 }
2147
2148 static int set_sig_data_segment(struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
2149 void **seg, int *size)
2150 {
2151 struct ib_sig_attrs *sig_attrs = wr->wr.sig_handover.sig_attrs;
2152 struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr;
2153 struct mlx5_bsf *bsf;
2154 u32 data_len = wr->sg_list->length;
2155 u32 data_key = wr->sg_list->lkey;
2156 u64 data_va = wr->sg_list->addr;
2157 int ret;
2158 int wqe_size;
2159
2160 if (!wr->wr.sig_handover.prot ||
2161 (data_key == wr->wr.sig_handover.prot->lkey &&
2162 data_va == wr->wr.sig_handover.prot->addr &&
2163 data_len == wr->wr.sig_handover.prot->length)) {
2164 /**
2165 * Source domain doesn't contain signature information
2166 * or data and protection are interleaved in memory.
2167 * So need construct:
2168 * ------------------
2169 * | data_klm |
2170 * ------------------
2171 * | BSF |
2172 * ------------------
2173 **/
2174 struct mlx5_klm *data_klm = *seg;
2175
2176 data_klm->bcount = cpu_to_be32(data_len);
2177 data_klm->key = cpu_to_be32(data_key);
2178 data_klm->va = cpu_to_be64(data_va);
2179 wqe_size = ALIGN(sizeof(*data_klm), 64);
2180 } else {
2181 /**
2182 * Source domain contains signature information
2183 * So need construct a strided block format:
2184 * ---------------------------
2185 * | stride_block_ctrl |
2186 * ---------------------------
2187 * | data_klm |
2188 * ---------------------------
2189 * | prot_klm |
2190 * ---------------------------
2191 * | BSF |
2192 * ---------------------------
2193 **/
2194 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
2195 struct mlx5_stride_block_entry *data_sentry;
2196 struct mlx5_stride_block_entry *prot_sentry;
2197 u32 prot_key = wr->wr.sig_handover.prot->lkey;
2198 u64 prot_va = wr->wr.sig_handover.prot->addr;
2199 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
2200 int prot_size;
2201
2202 sblock_ctrl = *seg;
2203 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
2204 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
2205
2206 prot_size = prot_field_size(sig_attrs->mem.sig_type);
2207 if (!prot_size) {
2208 pr_err("Bad block size given: %u\n", block_size);
2209 return -EINVAL;
2210 }
2211 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
2212 prot_size);
2213 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
2214 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
2215 sblock_ctrl->num_entries = cpu_to_be16(2);
2216
2217 data_sentry->bcount = cpu_to_be16(block_size);
2218 data_sentry->key = cpu_to_be32(data_key);
2219 data_sentry->va = cpu_to_be64(data_va);
2220 data_sentry->stride = cpu_to_be16(block_size);
2221
2222 prot_sentry->bcount = cpu_to_be16(prot_size);
2223 prot_sentry->key = cpu_to_be32(prot_key);
2224 prot_sentry->va = cpu_to_be64(prot_va);
2225 prot_sentry->stride = cpu_to_be16(prot_size);
2226
2227 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
2228 sizeof(*prot_sentry), 64);
2229 }
2230
2231 *seg += wqe_size;
2232 *size += wqe_size / 16;
2233 if (unlikely((*seg == qp->sq.qend)))
2234 *seg = mlx5_get_send_wqe(qp, 0);
2235
2236 bsf = *seg;
2237 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
2238 if (ret)
2239 return -EINVAL;
2240
2241 *seg += sizeof(*bsf);
2242 *size += sizeof(*bsf) / 16;
2243 if (unlikely((*seg == qp->sq.qend)))
2244 *seg = mlx5_get_send_wqe(qp, 0);
2245
2246 return 0;
2247 }
2248
2249 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
2250 struct ib_send_wr *wr, u32 nelements,
2251 u32 length, u32 pdn)
2252 {
2253 struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr;
2254 u32 sig_key = sig_mr->rkey;
2255 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
2256
2257 memset(seg, 0, sizeof(*seg));
2258
2259 seg->flags = get_umr_flags(wr->wr.sig_handover.access_flags) |
2260 MLX5_ACCESS_MODE_KLM;
2261 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
2262 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
2263 MLX5_MKEY_BSF_EN | pdn);
2264 seg->len = cpu_to_be64(length);
2265 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
2266 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
2267 }
2268
2269 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2270 struct ib_send_wr *wr, u32 nelements)
2271 {
2272 memset(umr, 0, sizeof(*umr));
2273
2274 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
2275 umr->klm_octowords = get_klm_octo(nelements);
2276 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
2277 umr->mkey_mask = sig_mkey_mask();
2278 }
2279
2280
2281 static int set_sig_umr_wr(struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
2282 void **seg, int *size)
2283 {
2284 struct mlx5_ib_mr *sig_mr = to_mmr(wr->wr.sig_handover.sig_mr);
2285 u32 pdn = get_pd(qp)->pdn;
2286 u32 klm_oct_size;
2287 int region_len, ret;
2288
2289 if (unlikely(wr->num_sge != 1) ||
2290 unlikely(wr->wr.sig_handover.access_flags &
2291 IB_ACCESS_REMOTE_ATOMIC) ||
2292 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
2293 unlikely(!sig_mr->sig->sig_status_checked))
2294 return -EINVAL;
2295
2296 /* length of the protected region, data + protection */
2297 region_len = wr->sg_list->length;
2298 if (wr->wr.sig_handover.prot &&
2299 (wr->wr.sig_handover.prot->lkey != wr->sg_list->lkey ||
2300 wr->wr.sig_handover.prot->addr != wr->sg_list->addr ||
2301 wr->wr.sig_handover.prot->length != wr->sg_list->length))
2302 region_len += wr->wr.sig_handover.prot->length;
2303
2304 /**
2305 * KLM octoword size - if protection was provided
2306 * then we use strided block format (3 octowords),
2307 * else we use single KLM (1 octoword)
2308 **/
2309 klm_oct_size = wr->wr.sig_handover.prot ? 3 : 1;
2310
2311 set_sig_umr_segment(*seg, wr, klm_oct_size);
2312 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2313 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2314 if (unlikely((*seg == qp->sq.qend)))
2315 *seg = mlx5_get_send_wqe(qp, 0);
2316
2317 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
2318 *seg += sizeof(struct mlx5_mkey_seg);
2319 *size += sizeof(struct mlx5_mkey_seg) / 16;
2320 if (unlikely((*seg == qp->sq.qend)))
2321 *seg = mlx5_get_send_wqe(qp, 0);
2322
2323 ret = set_sig_data_segment(wr, qp, seg, size);
2324 if (ret)
2325 return ret;
2326
2327 sig_mr->sig->sig_status_checked = false;
2328 return 0;
2329 }
2330
2331 static int set_psv_wr(struct ib_sig_domain *domain,
2332 u32 psv_idx, void **seg, int *size)
2333 {
2334 struct mlx5_seg_set_psv *psv_seg = *seg;
2335
2336 memset(psv_seg, 0, sizeof(*psv_seg));
2337 psv_seg->psv_num = cpu_to_be32(psv_idx);
2338 switch (domain->sig_type) {
2339 case IB_SIG_TYPE_T10_DIF:
2340 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
2341 domain->sig.dif.app_tag);
2342 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
2343
2344 *seg += sizeof(*psv_seg);
2345 *size += sizeof(*psv_seg) / 16;
2346 break;
2347
2348 default:
2349 pr_err("Bad signature type given.\n");
2350 return 1;
2351 }
2352
2353 return 0;
2354 }
2355
2356 static int set_frwr_li_wr(void **seg, struct ib_send_wr *wr, int *size,
2357 struct mlx5_core_dev *mdev, struct mlx5_ib_pd *pd, struct mlx5_ib_qp *qp)
2358 {
2359 int writ = 0;
2360 int li;
2361
2362 li = wr->opcode == IB_WR_LOCAL_INV ? 1 : 0;
2363 if (unlikely(wr->send_flags & IB_SEND_INLINE))
2364 return -EINVAL;
2365
2366 set_frwr_umr_segment(*seg, wr, li);
2367 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2368 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2369 if (unlikely((*seg == qp->sq.qend)))
2370 *seg = mlx5_get_send_wqe(qp, 0);
2371 set_mkey_segment(*seg, wr, li, &writ);
2372 *seg += sizeof(struct mlx5_mkey_seg);
2373 *size += sizeof(struct mlx5_mkey_seg) / 16;
2374 if (unlikely((*seg == qp->sq.qend)))
2375 *seg = mlx5_get_send_wqe(qp, 0);
2376 if (!li) {
2377 if (unlikely(wr->wr.fast_reg.page_list_len >
2378 wr->wr.fast_reg.page_list->max_page_list_len))
2379 return -ENOMEM;
2380
2381 set_frwr_pages(*seg, wr, mdev, pd, writ);
2382 *seg += sizeof(struct mlx5_wqe_data_seg);
2383 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
2384 }
2385 return 0;
2386 }
2387
2388 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
2389 {
2390 __be32 *p = NULL;
2391 int tidx = idx;
2392 int i, j;
2393
2394 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
2395 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
2396 if ((i & 0xf) == 0) {
2397 void *buf = mlx5_get_send_wqe(qp, tidx);
2398 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
2399 p = buf;
2400 j = 0;
2401 }
2402 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
2403 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
2404 be32_to_cpu(p[j + 3]));
2405 }
2406 }
2407
2408 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
2409 unsigned bytecnt, struct mlx5_ib_qp *qp)
2410 {
2411 while (bytecnt > 0) {
2412 __iowrite64_copy(dst++, src++, 8);
2413 __iowrite64_copy(dst++, src++, 8);
2414 __iowrite64_copy(dst++, src++, 8);
2415 __iowrite64_copy(dst++, src++, 8);
2416 __iowrite64_copy(dst++, src++, 8);
2417 __iowrite64_copy(dst++, src++, 8);
2418 __iowrite64_copy(dst++, src++, 8);
2419 __iowrite64_copy(dst++, src++, 8);
2420 bytecnt -= 64;
2421 if (unlikely(src == qp->sq.qend))
2422 src = mlx5_get_send_wqe(qp, 0);
2423 }
2424 }
2425
2426 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
2427 {
2428 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
2429 wr->send_flags & IB_SEND_FENCE))
2430 return MLX5_FENCE_MODE_STRONG_ORDERING;
2431
2432 if (unlikely(fence)) {
2433 if (wr->send_flags & IB_SEND_FENCE)
2434 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
2435 else
2436 return fence;
2437
2438 } else {
2439 return 0;
2440 }
2441 }
2442
2443 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
2444 struct mlx5_wqe_ctrl_seg **ctrl,
2445 struct ib_send_wr *wr, int *idx,
2446 int *size, int nreq)
2447 {
2448 int err = 0;
2449
2450 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2451 err = -ENOMEM;
2452 return err;
2453 }
2454
2455 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2456 *seg = mlx5_get_send_wqe(qp, *idx);
2457 *ctrl = *seg;
2458 *(uint32_t *)(*seg + 8) = 0;
2459 (*ctrl)->imm = send_ieth(wr);
2460 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
2461 (wr->send_flags & IB_SEND_SIGNALED ?
2462 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2463 (wr->send_flags & IB_SEND_SOLICITED ?
2464 MLX5_WQE_CTRL_SOLICITED : 0);
2465
2466 *seg += sizeof(**ctrl);
2467 *size = sizeof(**ctrl) / 16;
2468
2469 return err;
2470 }
2471
2472 static void finish_wqe(struct mlx5_ib_qp *qp,
2473 struct mlx5_wqe_ctrl_seg *ctrl,
2474 u8 size, unsigned idx, u64 wr_id,
2475 int nreq, u8 fence, u8 next_fence,
2476 u32 mlx5_opcode)
2477 {
2478 u8 opmod = 0;
2479
2480 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
2481 mlx5_opcode | ((u32)opmod << 24));
2482 ctrl->qpn_ds = cpu_to_be32(size | (qp->mqp.qpn << 8));
2483 ctrl->fm_ce_se |= fence;
2484 qp->fm_cache = next_fence;
2485 if (unlikely(qp->wq_sig))
2486 ctrl->signature = wq_sig(ctrl);
2487
2488 qp->sq.wrid[idx] = wr_id;
2489 qp->sq.w_list[idx].opcode = mlx5_opcode;
2490 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2491 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
2492 qp->sq.w_list[idx].next = qp->sq.cur_post;
2493 }
2494
2495
2496 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
2497 struct ib_send_wr **bad_wr)
2498 {
2499 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
2500 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2501 struct mlx5_core_dev *mdev = dev->mdev;
2502 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2503 struct mlx5_ib_mr *mr;
2504 struct mlx5_wqe_data_seg *dpseg;
2505 struct mlx5_wqe_xrc_seg *xrc;
2506 struct mlx5_bf *bf = qp->bf;
2507 int uninitialized_var(size);
2508 void *qend = qp->sq.qend;
2509 unsigned long flags;
2510 unsigned idx;
2511 int err = 0;
2512 int inl = 0;
2513 int num_sge;
2514 void *seg;
2515 int nreq;
2516 int i;
2517 u8 next_fence = 0;
2518 u8 fence;
2519
2520 spin_lock_irqsave(&qp->sq.lock, flags);
2521
2522 for (nreq = 0; wr; nreq++, wr = wr->next) {
2523 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
2524 mlx5_ib_warn(dev, "\n");
2525 err = -EINVAL;
2526 *bad_wr = wr;
2527 goto out;
2528 }
2529
2530 fence = qp->fm_cache;
2531 num_sge = wr->num_sge;
2532 if (unlikely(num_sge > qp->sq.max_gs)) {
2533 mlx5_ib_warn(dev, "\n");
2534 err = -ENOMEM;
2535 *bad_wr = wr;
2536 goto out;
2537 }
2538
2539 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
2540 if (err) {
2541 mlx5_ib_warn(dev, "\n");
2542 err = -ENOMEM;
2543 *bad_wr = wr;
2544 goto out;
2545 }
2546
2547 switch (ibqp->qp_type) {
2548 case IB_QPT_XRC_INI:
2549 xrc = seg;
2550 xrc->xrc_srqn = htonl(wr->xrc_remote_srq_num);
2551 seg += sizeof(*xrc);
2552 size += sizeof(*xrc) / 16;
2553 /* fall through */
2554 case IB_QPT_RC:
2555 switch (wr->opcode) {
2556 case IB_WR_RDMA_READ:
2557 case IB_WR_RDMA_WRITE:
2558 case IB_WR_RDMA_WRITE_WITH_IMM:
2559 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2560 wr->wr.rdma.rkey);
2561 seg += sizeof(struct mlx5_wqe_raddr_seg);
2562 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2563 break;
2564
2565 case IB_WR_ATOMIC_CMP_AND_SWP:
2566 case IB_WR_ATOMIC_FETCH_AND_ADD:
2567 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
2568 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
2569 err = -ENOSYS;
2570 *bad_wr = wr;
2571 goto out;
2572
2573 case IB_WR_LOCAL_INV:
2574 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2575 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
2576 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
2577 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2578 if (err) {
2579 mlx5_ib_warn(dev, "\n");
2580 *bad_wr = wr;
2581 goto out;
2582 }
2583 num_sge = 0;
2584 break;
2585
2586 case IB_WR_FAST_REG_MR:
2587 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2588 qp->sq.wr_data[idx] = IB_WR_FAST_REG_MR;
2589 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2590 err = set_frwr_li_wr(&seg, wr, &size, mdev, to_mpd(ibqp->pd), qp);
2591 if (err) {
2592 mlx5_ib_warn(dev, "\n");
2593 *bad_wr = wr;
2594 goto out;
2595 }
2596 num_sge = 0;
2597 break;
2598
2599 case IB_WR_REG_SIG_MR:
2600 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
2601 mr = to_mmr(wr->wr.sig_handover.sig_mr);
2602
2603 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
2604 err = set_sig_umr_wr(wr, qp, &seg, &size);
2605 if (err) {
2606 mlx5_ib_warn(dev, "\n");
2607 *bad_wr = wr;
2608 goto out;
2609 }
2610
2611 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2612 nreq, get_fence(fence, wr),
2613 next_fence, MLX5_OPCODE_UMR);
2614 /*
2615 * SET_PSV WQEs are not signaled and solicited
2616 * on error
2617 */
2618 wr->send_flags &= ~IB_SEND_SIGNALED;
2619 wr->send_flags |= IB_SEND_SOLICITED;
2620 err = begin_wqe(qp, &seg, &ctrl, wr,
2621 &idx, &size, nreq);
2622 if (err) {
2623 mlx5_ib_warn(dev, "\n");
2624 err = -ENOMEM;
2625 *bad_wr = wr;
2626 goto out;
2627 }
2628
2629 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->mem,
2630 mr->sig->psv_memory.psv_idx, &seg,
2631 &size);
2632 if (err) {
2633 mlx5_ib_warn(dev, "\n");
2634 *bad_wr = wr;
2635 goto out;
2636 }
2637
2638 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2639 nreq, get_fence(fence, wr),
2640 next_fence, MLX5_OPCODE_SET_PSV);
2641 err = begin_wqe(qp, &seg, &ctrl, wr,
2642 &idx, &size, nreq);
2643 if (err) {
2644 mlx5_ib_warn(dev, "\n");
2645 err = -ENOMEM;
2646 *bad_wr = wr;
2647 goto out;
2648 }
2649
2650 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
2651 err = set_psv_wr(&wr->wr.sig_handover.sig_attrs->wire,
2652 mr->sig->psv_wire.psv_idx, &seg,
2653 &size);
2654 if (err) {
2655 mlx5_ib_warn(dev, "\n");
2656 *bad_wr = wr;
2657 goto out;
2658 }
2659
2660 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
2661 nreq, get_fence(fence, wr),
2662 next_fence, MLX5_OPCODE_SET_PSV);
2663 num_sge = 0;
2664 goto skip_psv;
2665
2666 default:
2667 break;
2668 }
2669 break;
2670
2671 case IB_QPT_UC:
2672 switch (wr->opcode) {
2673 case IB_WR_RDMA_WRITE:
2674 case IB_WR_RDMA_WRITE_WITH_IMM:
2675 set_raddr_seg(seg, wr->wr.rdma.remote_addr,
2676 wr->wr.rdma.rkey);
2677 seg += sizeof(struct mlx5_wqe_raddr_seg);
2678 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
2679 break;
2680
2681 default:
2682 break;
2683 }
2684 break;
2685
2686 case IB_QPT_UD:
2687 case IB_QPT_SMI:
2688 case IB_QPT_GSI:
2689 set_datagram_seg(seg, wr);
2690 seg += sizeof(struct mlx5_wqe_datagram_seg);
2691 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
2692 if (unlikely((seg == qend)))
2693 seg = mlx5_get_send_wqe(qp, 0);
2694 break;
2695
2696 case MLX5_IB_QPT_REG_UMR:
2697 if (wr->opcode != MLX5_IB_WR_UMR) {
2698 err = -EINVAL;
2699 mlx5_ib_warn(dev, "bad opcode\n");
2700 goto out;
2701 }
2702 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
2703 ctrl->imm = cpu_to_be32(wr->wr.fast_reg.rkey);
2704 set_reg_umr_segment(seg, wr);
2705 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2706 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2707 if (unlikely((seg == qend)))
2708 seg = mlx5_get_send_wqe(qp, 0);
2709 set_reg_mkey_segment(seg, wr);
2710 seg += sizeof(struct mlx5_mkey_seg);
2711 size += sizeof(struct mlx5_mkey_seg) / 16;
2712 if (unlikely((seg == qend)))
2713 seg = mlx5_get_send_wqe(qp, 0);
2714 break;
2715
2716 default:
2717 break;
2718 }
2719
2720 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
2721 int uninitialized_var(sz);
2722
2723 err = set_data_inl_seg(qp, wr, seg, &sz);
2724 if (unlikely(err)) {
2725 mlx5_ib_warn(dev, "\n");
2726 *bad_wr = wr;
2727 goto out;
2728 }
2729 inl = 1;
2730 size += sz;
2731 } else {
2732 dpseg = seg;
2733 for (i = 0; i < num_sge; i++) {
2734 if (unlikely(dpseg == qend)) {
2735 seg = mlx5_get_send_wqe(qp, 0);
2736 dpseg = seg;
2737 }
2738 if (likely(wr->sg_list[i].length)) {
2739 set_data_ptr_seg(dpseg, wr->sg_list + i);
2740 size += sizeof(struct mlx5_wqe_data_seg) / 16;
2741 dpseg++;
2742 }
2743 }
2744 }
2745
2746 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
2747 get_fence(fence, wr), next_fence,
2748 mlx5_ib_opcode[wr->opcode]);
2749 skip_psv:
2750 if (0)
2751 dump_wqe(qp, idx, size);
2752 }
2753
2754 out:
2755 if (likely(nreq)) {
2756 qp->sq.head += nreq;
2757
2758 /* Make sure that descriptors are written before
2759 * updating doorbell record and ringing the doorbell
2760 */
2761 wmb();
2762
2763 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
2764
2765 /* Make sure doorbell record is visible to the HCA before
2766 * we hit doorbell */
2767 wmb();
2768
2769 if (bf->need_lock)
2770 spin_lock(&bf->lock);
2771
2772 /* TBD enable WC */
2773 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
2774 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
2775 /* wc_wmb(); */
2776 } else {
2777 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
2778 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
2779 /* Make sure doorbells don't leak out of SQ spinlock
2780 * and reach the HCA out of order.
2781 */
2782 mmiowb();
2783 }
2784 bf->offset ^= bf->buf_size;
2785 if (bf->need_lock)
2786 spin_unlock(&bf->lock);
2787 }
2788
2789 spin_unlock_irqrestore(&qp->sq.lock, flags);
2790
2791 return err;
2792 }
2793
2794 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
2795 {
2796 sig->signature = calc_sig(sig, size);
2797 }
2798
2799 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2800 struct ib_recv_wr **bad_wr)
2801 {
2802 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2803 struct mlx5_wqe_data_seg *scat;
2804 struct mlx5_rwqe_sig *sig;
2805 unsigned long flags;
2806 int err = 0;
2807 int nreq;
2808 int ind;
2809 int i;
2810
2811 spin_lock_irqsave(&qp->rq.lock, flags);
2812
2813 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
2814
2815 for (nreq = 0; wr; nreq++, wr = wr->next) {
2816 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2817 err = -ENOMEM;
2818 *bad_wr = wr;
2819 goto out;
2820 }
2821
2822 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2823 err = -EINVAL;
2824 *bad_wr = wr;
2825 goto out;
2826 }
2827
2828 scat = get_recv_wqe(qp, ind);
2829 if (qp->wq_sig)
2830 scat++;
2831
2832 for (i = 0; i < wr->num_sge; i++)
2833 set_data_ptr_seg(scat + i, wr->sg_list + i);
2834
2835 if (i < qp->rq.max_gs) {
2836 scat[i].byte_count = 0;
2837 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
2838 scat[i].addr = 0;
2839 }
2840
2841 if (qp->wq_sig) {
2842 sig = (struct mlx5_rwqe_sig *)scat;
2843 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
2844 }
2845
2846 qp->rq.wrid[ind] = wr->wr_id;
2847
2848 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
2849 }
2850
2851 out:
2852 if (likely(nreq)) {
2853 qp->rq.head += nreq;
2854
2855 /* Make sure that descriptors are written before
2856 * doorbell record.
2857 */
2858 wmb();
2859
2860 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
2861 }
2862
2863 spin_unlock_irqrestore(&qp->rq.lock, flags);
2864
2865 return err;
2866 }
2867
2868 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
2869 {
2870 switch (mlx5_state) {
2871 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
2872 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
2873 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
2874 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
2875 case MLX5_QP_STATE_SQ_DRAINING:
2876 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
2877 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
2878 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
2879 default: return -1;
2880 }
2881 }
2882
2883 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
2884 {
2885 switch (mlx5_mig_state) {
2886 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
2887 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
2888 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
2889 default: return -1;
2890 }
2891 }
2892
2893 static int to_ib_qp_access_flags(int mlx5_flags)
2894 {
2895 int ib_flags = 0;
2896
2897 if (mlx5_flags & MLX5_QP_BIT_RRE)
2898 ib_flags |= IB_ACCESS_REMOTE_READ;
2899 if (mlx5_flags & MLX5_QP_BIT_RWE)
2900 ib_flags |= IB_ACCESS_REMOTE_WRITE;
2901 if (mlx5_flags & MLX5_QP_BIT_RAE)
2902 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
2903
2904 return ib_flags;
2905 }
2906
2907 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
2908 struct mlx5_qp_path *path)
2909 {
2910 struct mlx5_core_dev *dev = ibdev->mdev;
2911
2912 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
2913 ib_ah_attr->port_num = path->port;
2914
2915 if (ib_ah_attr->port_num == 0 ||
2916 ib_ah_attr->port_num > dev->caps.gen.num_ports)
2917 return;
2918
2919 ib_ah_attr->sl = path->sl & 0xf;
2920
2921 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
2922 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
2923 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
2924 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
2925 if (ib_ah_attr->ah_flags) {
2926 ib_ah_attr->grh.sgid_index = path->mgid_index;
2927 ib_ah_attr->grh.hop_limit = path->hop_limit;
2928 ib_ah_attr->grh.traffic_class =
2929 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
2930 ib_ah_attr->grh.flow_label =
2931 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
2932 memcpy(ib_ah_attr->grh.dgid.raw,
2933 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
2934 }
2935 }
2936
2937 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
2938 struct ib_qp_init_attr *qp_init_attr)
2939 {
2940 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2941 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2942 struct mlx5_query_qp_mbox_out *outb;
2943 struct mlx5_qp_context *context;
2944 int mlx5_state;
2945 int err = 0;
2946
2947 mutex_lock(&qp->mutex);
2948 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
2949 if (!outb) {
2950 err = -ENOMEM;
2951 goto out;
2952 }
2953 context = &outb->ctx;
2954 err = mlx5_core_qp_query(dev->mdev, &qp->mqp, outb, sizeof(*outb));
2955 if (err)
2956 goto out_free;
2957
2958 mlx5_state = be32_to_cpu(context->flags) >> 28;
2959
2960 qp->state = to_ib_qp_state(mlx5_state);
2961 qp_attr->qp_state = qp->state;
2962 qp_attr->path_mtu = context->mtu_msgmax >> 5;
2963 qp_attr->path_mig_state =
2964 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
2965 qp_attr->qkey = be32_to_cpu(context->qkey);
2966 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
2967 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
2968 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
2969 qp_attr->qp_access_flags =
2970 to_ib_qp_access_flags(be32_to_cpu(context->params2));
2971
2972 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
2973 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
2974 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
2975 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
2976 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
2977 }
2978
2979 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
2980 qp_attr->port_num = context->pri_path.port;
2981
2982 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
2983 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
2984
2985 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
2986
2987 qp_attr->max_dest_rd_atomic =
2988 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
2989 qp_attr->min_rnr_timer =
2990 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
2991 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
2992 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
2993 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
2994 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
2995 qp_attr->cur_qp_state = qp_attr->qp_state;
2996 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
2997 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
2998
2999 if (!ibqp->uobject) {
3000 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3001 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3002 } else {
3003 qp_attr->cap.max_send_wr = 0;
3004 qp_attr->cap.max_send_sge = 0;
3005 }
3006
3007 /* We don't support inline sends for kernel QPs (yet), and we
3008 * don't know what userspace's value should be.
3009 */
3010 qp_attr->cap.max_inline_data = 0;
3011
3012 qp_init_attr->cap = qp_attr->cap;
3013
3014 qp_init_attr->create_flags = 0;
3015 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3016 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3017
3018 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
3019 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3020
3021 out_free:
3022 kfree(outb);
3023
3024 out:
3025 mutex_unlock(&qp->mutex);
3026 return err;
3027 }
3028
3029 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
3030 struct ib_ucontext *context,
3031 struct ib_udata *udata)
3032 {
3033 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3034 struct mlx5_general_caps *gen;
3035 struct mlx5_ib_xrcd *xrcd;
3036 int err;
3037
3038 gen = &dev->mdev->caps.gen;
3039 if (!(gen->flags & MLX5_DEV_CAP_FLAG_XRC))
3040 return ERR_PTR(-ENOSYS);
3041
3042 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
3043 if (!xrcd)
3044 return ERR_PTR(-ENOMEM);
3045
3046 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
3047 if (err) {
3048 kfree(xrcd);
3049 return ERR_PTR(-ENOMEM);
3050 }
3051
3052 return &xrcd->ibxrcd;
3053 }
3054
3055 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
3056 {
3057 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
3058 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
3059 int err;
3060
3061 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
3062 if (err) {
3063 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
3064 return err;
3065 }
3066
3067 kfree(xrcd);
3068
3069 return 0;
3070 }
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