2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
40 /* not supported currently */
41 static int wq_signature
;
44 MLX5_IB_ACK_REQ_FREQ
= 8,
48 MLX5_IB_DEFAULT_SCHED_QUEUE
= 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE
= 0x3f,
50 MLX5_IB_LINK_TYPE_IB
= 0,
51 MLX5_IB_LINK_TYPE_ETH
= 1
55 MLX5_IB_SQ_STRIDE
= 6,
56 MLX5_IB_CACHE_LINE_SIZE
= 64,
59 static const u32 mlx5_ib_opcode
[] = {
60 [IB_WR_SEND
] = MLX5_OPCODE_SEND
,
61 [IB_WR_SEND_WITH_IMM
] = MLX5_OPCODE_SEND_IMM
,
62 [IB_WR_RDMA_WRITE
] = MLX5_OPCODE_RDMA_WRITE
,
63 [IB_WR_RDMA_WRITE_WITH_IMM
] = MLX5_OPCODE_RDMA_WRITE_IMM
,
64 [IB_WR_RDMA_READ
] = MLX5_OPCODE_RDMA_READ
,
65 [IB_WR_ATOMIC_CMP_AND_SWP
] = MLX5_OPCODE_ATOMIC_CS
,
66 [IB_WR_ATOMIC_FETCH_AND_ADD
] = MLX5_OPCODE_ATOMIC_FA
,
67 [IB_WR_SEND_WITH_INV
] = MLX5_OPCODE_SEND_INVAL
,
68 [IB_WR_LOCAL_INV
] = MLX5_OPCODE_UMR
,
69 [IB_WR_REG_MR
] = MLX5_OPCODE_UMR
,
70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP
] = MLX5_OPCODE_ATOMIC_MASKED_CS
,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD
] = MLX5_OPCODE_ATOMIC_MASKED_FA
,
72 [MLX5_IB_WR_UMR
] = MLX5_OPCODE_UMR
,
76 static int is_qp0(enum ib_qp_type qp_type
)
78 return qp_type
== IB_QPT_SMI
;
81 static int is_sqp(enum ib_qp_type qp_type
)
83 return is_qp0(qp_type
) || is_qp1(qp_type
);
86 static void *get_wqe(struct mlx5_ib_qp
*qp
, int offset
)
88 return mlx5_buf_offset(&qp
->buf
, offset
);
91 static void *get_recv_wqe(struct mlx5_ib_qp
*qp
, int n
)
93 return get_wqe(qp
, qp
->rq
.offset
+ (n
<< qp
->rq
.wqe_shift
));
96 void *mlx5_get_send_wqe(struct mlx5_ib_qp
*qp
, int n
)
98 return get_wqe(qp
, qp
->sq
.offset
+ (n
<< MLX5_IB_SQ_STRIDE
));
102 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
104 * @qp: QP to copy from.
105 * @send: copy from the send queue when non-zero, use the receive queue
107 * @wqe_index: index to start copying from. For send work queues, the
108 * wqe_index is in units of MLX5_SEND_WQE_BB.
109 * For receive work queue, it is the number of work queue
110 * element in the queue.
111 * @buffer: destination buffer.
112 * @length: maximum number of bytes to copy.
114 * Copies at least a single WQE, but may copy more data.
116 * Return: the number of bytes copied, or an error code.
118 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp
*qp
, int send
, int wqe_index
,
119 void *buffer
, u32 length
,
120 struct mlx5_ib_qp_base
*base
)
122 struct ib_device
*ibdev
= qp
->ibqp
.device
;
123 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
124 struct mlx5_ib_wq
*wq
= send
? &qp
->sq
: &qp
->rq
;
127 struct ib_umem
*umem
= base
->ubuffer
.umem
;
128 u32 first_copy_length
;
132 if (wq
->wqe_cnt
== 0) {
133 mlx5_ib_dbg(dev
, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
138 offset
= wq
->offset
+ ((wqe_index
% wq
->wqe_cnt
) << wq
->wqe_shift
);
139 wq_end
= wq
->offset
+ (wq
->wqe_cnt
<< wq
->wqe_shift
);
141 if (send
&& length
< sizeof(struct mlx5_wqe_ctrl_seg
))
144 if (offset
> umem
->length
||
145 (send
&& offset
+ sizeof(struct mlx5_wqe_ctrl_seg
) > umem
->length
))
148 first_copy_length
= min_t(u32
, offset
+ length
, wq_end
) - offset
;
149 ret
= ib_umem_copy_from(buffer
, umem
, offset
, first_copy_length
);
154 struct mlx5_wqe_ctrl_seg
*ctrl
= buffer
;
155 int ds
= be32_to_cpu(ctrl
->qpn_ds
) & MLX5_WQE_CTRL_DS_MASK
;
157 wqe_length
= ds
* MLX5_WQE_DS_UNITS
;
159 wqe_length
= 1 << wq
->wqe_shift
;
162 if (wqe_length
<= first_copy_length
)
163 return first_copy_length
;
165 ret
= ib_umem_copy_from(buffer
+ first_copy_length
, umem
, wq
->offset
,
166 wqe_length
- first_copy_length
);
173 static void mlx5_ib_qp_event(struct mlx5_core_qp
*qp
, int type
)
175 struct ib_qp
*ibqp
= &to_mibqp(qp
)->ibqp
;
176 struct ib_event event
;
178 if (type
== MLX5_EVENT_TYPE_PATH_MIG
) {
179 /* This event is only valid for trans_qps */
180 to_mibqp(qp
)->port
= to_mibqp(qp
)->trans_qp
.alt_port
;
183 if (ibqp
->event_handler
) {
184 event
.device
= ibqp
->device
;
185 event
.element
.qp
= ibqp
;
187 case MLX5_EVENT_TYPE_PATH_MIG
:
188 event
.event
= IB_EVENT_PATH_MIG
;
190 case MLX5_EVENT_TYPE_COMM_EST
:
191 event
.event
= IB_EVENT_COMM_EST
;
193 case MLX5_EVENT_TYPE_SQ_DRAINED
:
194 event
.event
= IB_EVENT_SQ_DRAINED
;
196 case MLX5_EVENT_TYPE_SRQ_LAST_WQE
:
197 event
.event
= IB_EVENT_QP_LAST_WQE_REACHED
;
199 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR
:
200 event
.event
= IB_EVENT_QP_FATAL
;
202 case MLX5_EVENT_TYPE_PATH_MIG_FAILED
:
203 event
.event
= IB_EVENT_PATH_MIG_ERR
;
205 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR
:
206 event
.event
= IB_EVENT_QP_REQ_ERR
;
208 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR
:
209 event
.event
= IB_EVENT_QP_ACCESS_ERR
;
212 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type
, qp
->qpn
);
216 ibqp
->event_handler(&event
, ibqp
->qp_context
);
220 static int set_rq_size(struct mlx5_ib_dev
*dev
, struct ib_qp_cap
*cap
,
221 int has_rq
, struct mlx5_ib_qp
*qp
, struct mlx5_ib_create_qp
*ucmd
)
226 /* Sanity check RQ size before proceeding */
227 if (cap
->max_recv_wr
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
)))
233 qp
->rq
.wqe_shift
= 0;
236 qp
->rq
.wqe_cnt
= ucmd
->rq_wqe_count
;
237 qp
->rq
.wqe_shift
= ucmd
->rq_wqe_shift
;
238 qp
->rq
.max_gs
= (1 << qp
->rq
.wqe_shift
) / sizeof(struct mlx5_wqe_data_seg
) - qp
->wq_sig
;
239 qp
->rq
.max_post
= qp
->rq
.wqe_cnt
;
241 wqe_size
= qp
->wq_sig
? sizeof(struct mlx5_wqe_signature_seg
) : 0;
242 wqe_size
+= cap
->max_recv_sge
* sizeof(struct mlx5_wqe_data_seg
);
243 wqe_size
= roundup_pow_of_two(wqe_size
);
244 wq_size
= roundup_pow_of_two(cap
->max_recv_wr
) * wqe_size
;
245 wq_size
= max_t(int, wq_size
, MLX5_SEND_WQE_BB
);
246 qp
->rq
.wqe_cnt
= wq_size
/ wqe_size
;
247 if (wqe_size
> MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
)) {
248 mlx5_ib_dbg(dev
, "wqe_size %d, max %d\n",
250 MLX5_CAP_GEN(dev
->mdev
,
254 qp
->rq
.wqe_shift
= ilog2(wqe_size
);
255 qp
->rq
.max_gs
= (1 << qp
->rq
.wqe_shift
) / sizeof(struct mlx5_wqe_data_seg
) - qp
->wq_sig
;
256 qp
->rq
.max_post
= qp
->rq
.wqe_cnt
;
263 static int sq_overhead(enum ib_qp_type qp_type
)
269 size
+= sizeof(struct mlx5_wqe_xrc_seg
);
272 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
273 max(sizeof(struct mlx5_wqe_atomic_seg
) +
274 sizeof(struct mlx5_wqe_raddr_seg
),
275 sizeof(struct mlx5_wqe_umr_ctrl_seg
) +
276 sizeof(struct mlx5_mkey_seg
));
283 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
284 max(sizeof(struct mlx5_wqe_raddr_seg
),
285 sizeof(struct mlx5_wqe_umr_ctrl_seg
) +
286 sizeof(struct mlx5_mkey_seg
));
292 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
293 sizeof(struct mlx5_wqe_datagram_seg
);
296 case MLX5_IB_QPT_REG_UMR
:
297 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
298 sizeof(struct mlx5_wqe_umr_ctrl_seg
) +
299 sizeof(struct mlx5_mkey_seg
);
309 static int calc_send_wqe(struct ib_qp_init_attr
*attr
)
314 size
= sq_overhead(attr
->qp_type
);
318 if (attr
->cap
.max_inline_data
) {
319 inl_size
= size
+ sizeof(struct mlx5_wqe_inline_seg
) +
320 attr
->cap
.max_inline_data
;
323 size
+= attr
->cap
.max_send_sge
* sizeof(struct mlx5_wqe_data_seg
);
324 if (attr
->create_flags
& IB_QP_CREATE_SIGNATURE_EN
&&
325 ALIGN(max_t(int, inl_size
, size
), MLX5_SEND_WQE_BB
) < MLX5_SIG_WQE_SIZE
)
326 return MLX5_SIG_WQE_SIZE
;
328 return ALIGN(max_t(int, inl_size
, size
), MLX5_SEND_WQE_BB
);
331 static int calc_sq_size(struct mlx5_ib_dev
*dev
, struct ib_qp_init_attr
*attr
,
332 struct mlx5_ib_qp
*qp
)
337 if (!attr
->cap
.max_send_wr
)
340 wqe_size
= calc_send_wqe(attr
);
341 mlx5_ib_dbg(dev
, "wqe_size %d\n", wqe_size
);
345 if (wqe_size
> MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
)) {
346 mlx5_ib_dbg(dev
, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
347 wqe_size
, MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
));
351 qp
->max_inline_data
= wqe_size
- sq_overhead(attr
->qp_type
) -
352 sizeof(struct mlx5_wqe_inline_seg
);
353 attr
->cap
.max_inline_data
= qp
->max_inline_data
;
355 if (attr
->create_flags
& IB_QP_CREATE_SIGNATURE_EN
)
356 qp
->signature_en
= true;
358 wq_size
= roundup_pow_of_two(attr
->cap
.max_send_wr
* wqe_size
);
359 qp
->sq
.wqe_cnt
= wq_size
/ MLX5_SEND_WQE_BB
;
360 if (qp
->sq
.wqe_cnt
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
))) {
361 mlx5_ib_dbg(dev
, "wqe count(%d) exceeds limits(%d)\n",
363 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
));
366 qp
->sq
.wqe_shift
= ilog2(MLX5_SEND_WQE_BB
);
367 qp
->sq
.max_gs
= attr
->cap
.max_send_sge
;
368 qp
->sq
.max_post
= wq_size
/ wqe_size
;
369 attr
->cap
.max_send_wr
= qp
->sq
.max_post
;
374 static int set_user_buf_size(struct mlx5_ib_dev
*dev
,
375 struct mlx5_ib_qp
*qp
,
376 struct mlx5_ib_create_qp
*ucmd
,
377 struct mlx5_ib_qp_base
*base
,
378 struct ib_qp_init_attr
*attr
)
380 int desc_sz
= 1 << qp
->sq
.wqe_shift
;
382 if (desc_sz
> MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
)) {
383 mlx5_ib_warn(dev
, "desc_sz %d, max_sq_desc_sz %d\n",
384 desc_sz
, MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
));
388 if (ucmd
->sq_wqe_count
&& ((1 << ilog2(ucmd
->sq_wqe_count
)) != ucmd
->sq_wqe_count
)) {
389 mlx5_ib_warn(dev
, "sq_wqe_count %d, sq_wqe_count %d\n",
390 ucmd
->sq_wqe_count
, ucmd
->sq_wqe_count
);
394 qp
->sq
.wqe_cnt
= ucmd
->sq_wqe_count
;
396 if (qp
->sq
.wqe_cnt
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
))) {
397 mlx5_ib_warn(dev
, "wqe_cnt %d, max_wqes %d\n",
399 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
));
403 if (attr
->qp_type
== IB_QPT_RAW_PACKET
) {
404 base
->ubuffer
.buf_size
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
405 qp
->raw_packet_qp
.sq
.ubuffer
.buf_size
= qp
->sq
.wqe_cnt
<< 6;
407 base
->ubuffer
.buf_size
= (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
) +
408 (qp
->sq
.wqe_cnt
<< 6);
414 static int qp_has_rq(struct ib_qp_init_attr
*attr
)
416 if (attr
->qp_type
== IB_QPT_XRC_INI
||
417 attr
->qp_type
== IB_QPT_XRC_TGT
|| attr
->srq
||
418 attr
->qp_type
== MLX5_IB_QPT_REG_UMR
||
419 !attr
->cap
.max_recv_wr
)
425 static int first_med_uuar(void)
430 static int next_uuar(int n
)
434 while (((n
% 4) & 2))
440 static int num_med_uuar(struct mlx5_uuar_info
*uuari
)
444 n
= uuari
->num_uars
* MLX5_NON_FP_BF_REGS_PER_PAGE
-
445 uuari
->num_low_latency_uuars
- 1;
447 return n
>= 0 ? n
: 0;
450 static int max_uuari(struct mlx5_uuar_info
*uuari
)
452 return uuari
->num_uars
* 4;
455 static int first_hi_uuar(struct mlx5_uuar_info
*uuari
)
461 med
= num_med_uuar(uuari
);
462 for (t
= 0, i
= first_med_uuar();; i
= next_uuar(i
)) {
471 static int alloc_high_class_uuar(struct mlx5_uuar_info
*uuari
)
475 for (i
= first_hi_uuar(uuari
); i
< max_uuari(uuari
); i
= next_uuar(i
)) {
476 if (!test_bit(i
, uuari
->bitmap
)) {
477 set_bit(i
, uuari
->bitmap
);
486 static int alloc_med_class_uuar(struct mlx5_uuar_info
*uuari
)
488 int minidx
= first_med_uuar();
491 for (i
= first_med_uuar(); i
< first_hi_uuar(uuari
); i
= next_uuar(i
)) {
492 if (uuari
->count
[i
] < uuari
->count
[minidx
])
496 uuari
->count
[minidx
]++;
500 static int alloc_uuar(struct mlx5_uuar_info
*uuari
,
501 enum mlx5_ib_latency_class lat
)
505 mutex_lock(&uuari
->lock
);
507 case MLX5_IB_LATENCY_CLASS_LOW
:
509 uuari
->count
[uuarn
]++;
512 case MLX5_IB_LATENCY_CLASS_MEDIUM
:
516 uuarn
= alloc_med_class_uuar(uuari
);
519 case MLX5_IB_LATENCY_CLASS_HIGH
:
523 uuarn
= alloc_high_class_uuar(uuari
);
526 case MLX5_IB_LATENCY_CLASS_FAST_PATH
:
530 mutex_unlock(&uuari
->lock
);
535 static void free_med_class_uuar(struct mlx5_uuar_info
*uuari
, int uuarn
)
537 clear_bit(uuarn
, uuari
->bitmap
);
538 --uuari
->count
[uuarn
];
541 static void free_high_class_uuar(struct mlx5_uuar_info
*uuari
, int uuarn
)
543 clear_bit(uuarn
, uuari
->bitmap
);
544 --uuari
->count
[uuarn
];
547 static void free_uuar(struct mlx5_uuar_info
*uuari
, int uuarn
)
549 int nuuars
= uuari
->num_uars
* MLX5_BF_REGS_PER_PAGE
;
550 int high_uuar
= nuuars
- uuari
->num_low_latency_uuars
;
552 mutex_lock(&uuari
->lock
);
554 --uuari
->count
[uuarn
];
558 if (uuarn
< high_uuar
) {
559 free_med_class_uuar(uuari
, uuarn
);
563 free_high_class_uuar(uuari
, uuarn
);
566 mutex_unlock(&uuari
->lock
);
569 static enum mlx5_qp_state
to_mlx5_state(enum ib_qp_state state
)
572 case IB_QPS_RESET
: return MLX5_QP_STATE_RST
;
573 case IB_QPS_INIT
: return MLX5_QP_STATE_INIT
;
574 case IB_QPS_RTR
: return MLX5_QP_STATE_RTR
;
575 case IB_QPS_RTS
: return MLX5_QP_STATE_RTS
;
576 case IB_QPS_SQD
: return MLX5_QP_STATE_SQD
;
577 case IB_QPS_SQE
: return MLX5_QP_STATE_SQER
;
578 case IB_QPS_ERR
: return MLX5_QP_STATE_ERR
;
583 static int to_mlx5_st(enum ib_qp_type type
)
586 case IB_QPT_RC
: return MLX5_QP_ST_RC
;
587 case IB_QPT_UC
: return MLX5_QP_ST_UC
;
588 case IB_QPT_UD
: return MLX5_QP_ST_UD
;
589 case MLX5_IB_QPT_REG_UMR
: return MLX5_QP_ST_REG_UMR
;
591 case IB_QPT_XRC_TGT
: return MLX5_QP_ST_XRC
;
592 case IB_QPT_SMI
: return MLX5_QP_ST_QP0
;
593 case IB_QPT_GSI
: return MLX5_QP_ST_QP1
;
594 case IB_QPT_RAW_IPV6
: return MLX5_QP_ST_RAW_IPV6
;
595 case IB_QPT_RAW_PACKET
:
596 case IB_QPT_RAW_ETHERTYPE
: return MLX5_QP_ST_RAW_ETHERTYPE
;
598 default: return -EINVAL
;
602 static int uuarn_to_uar_index(struct mlx5_uuar_info
*uuari
, int uuarn
)
604 return uuari
->uars
[uuarn
/ MLX5_BF_REGS_PER_PAGE
].index
;
607 static int mlx5_ib_umem_get(struct mlx5_ib_dev
*dev
,
609 unsigned long addr
, size_t size
,
610 struct ib_umem
**umem
,
611 int *npages
, int *page_shift
, int *ncont
,
616 *umem
= ib_umem_get(pd
->uobject
->context
, addr
, size
, 0, 0);
618 mlx5_ib_dbg(dev
, "umem_get failed\n");
619 return PTR_ERR(*umem
);
622 mlx5_ib_cont_pages(*umem
, addr
, npages
, page_shift
, ncont
, NULL
);
624 err
= mlx5_ib_get_buf_offset(addr
, *page_shift
, offset
);
626 mlx5_ib_warn(dev
, "bad offset\n");
630 mlx5_ib_dbg(dev
, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
631 addr
, size
, *npages
, *page_shift
, *ncont
, *offset
);
636 ib_umem_release(*umem
);
642 static int create_user_qp(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
643 struct mlx5_ib_qp
*qp
, struct ib_udata
*udata
,
644 struct ib_qp_init_attr
*attr
,
645 struct mlx5_create_qp_mbox_in
**in
,
646 struct mlx5_ib_create_qp_resp
*resp
, int *inlen
,
647 struct mlx5_ib_qp_base
*base
)
649 struct mlx5_ib_ucontext
*context
;
650 struct mlx5_ib_create_qp ucmd
;
651 struct mlx5_ib_ubuffer
*ubuffer
= &base
->ubuffer
;
660 err
= ib_copy_from_udata(&ucmd
, udata
, sizeof(ucmd
));
662 mlx5_ib_dbg(dev
, "copy failed\n");
666 context
= to_mucontext(pd
->uobject
->context
);
668 * TBD: should come from the verbs when we have the API
670 if (qp
->flags
& MLX5_IB_QP_CROSS_CHANNEL
)
671 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
672 uuarn
= MLX5_CROSS_CHANNEL_UUAR
;
674 uuarn
= alloc_uuar(&context
->uuari
, MLX5_IB_LATENCY_CLASS_HIGH
);
676 mlx5_ib_dbg(dev
, "failed to allocate low latency UUAR\n");
677 mlx5_ib_dbg(dev
, "reverting to medium latency\n");
678 uuarn
= alloc_uuar(&context
->uuari
, MLX5_IB_LATENCY_CLASS_MEDIUM
);
680 mlx5_ib_dbg(dev
, "failed to allocate medium latency UUAR\n");
681 mlx5_ib_dbg(dev
, "reverting to high latency\n");
682 uuarn
= alloc_uuar(&context
->uuari
, MLX5_IB_LATENCY_CLASS_LOW
);
684 mlx5_ib_warn(dev
, "uuar allocation failed\n");
691 uar_index
= uuarn_to_uar_index(&context
->uuari
, uuarn
);
692 mlx5_ib_dbg(dev
, "uuarn 0x%x, uar_index 0x%x\n", uuarn
, uar_index
);
695 qp
->sq
.wqe_shift
= ilog2(MLX5_SEND_WQE_BB
);
696 qp
->sq
.offset
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
698 err
= set_user_buf_size(dev
, qp
, &ucmd
, base
, attr
);
702 if (ucmd
.buf_addr
&& ubuffer
->buf_size
) {
703 ubuffer
->buf_addr
= ucmd
.buf_addr
;
704 err
= mlx5_ib_umem_get(dev
, pd
, ubuffer
->buf_addr
,
706 &ubuffer
->umem
, &npages
, &page_shift
,
711 ubuffer
->umem
= NULL
;
714 *inlen
= sizeof(**in
) + sizeof(*(*in
)->pas
) * ncont
;
715 *in
= mlx5_vzalloc(*inlen
);
721 mlx5_ib_populate_pas(dev
, ubuffer
->umem
, page_shift
,
723 (*in
)->ctx
.log_pg_sz_remote_qpn
=
724 cpu_to_be32((page_shift
- MLX5_ADAPTER_PAGE_SHIFT
) << 24);
725 (*in
)->ctx
.params2
= cpu_to_be32(offset
<< 6);
727 (*in
)->ctx
.qp_counter_set_usr_page
= cpu_to_be32(uar_index
);
728 resp
->uuar_index
= uuarn
;
731 err
= mlx5_ib_db_map_user(context
, ucmd
.db_addr
, &qp
->db
);
733 mlx5_ib_dbg(dev
, "map failed\n");
737 err
= ib_copy_to_udata(udata
, resp
, sizeof(*resp
));
739 mlx5_ib_dbg(dev
, "copy failed\n");
742 qp
->create_type
= MLX5_QP_USER
;
747 mlx5_ib_db_unmap_user(context
, &qp
->db
);
754 ib_umem_release(ubuffer
->umem
);
757 free_uuar(&context
->uuari
, uuarn
);
761 static void destroy_qp_user(struct ib_pd
*pd
, struct mlx5_ib_qp
*qp
,
762 struct mlx5_ib_qp_base
*base
)
764 struct mlx5_ib_ucontext
*context
;
766 context
= to_mucontext(pd
->uobject
->context
);
767 mlx5_ib_db_unmap_user(context
, &qp
->db
);
768 if (base
->ubuffer
.umem
)
769 ib_umem_release(base
->ubuffer
.umem
);
770 free_uuar(&context
->uuari
, qp
->uuarn
);
773 static int create_kernel_qp(struct mlx5_ib_dev
*dev
,
774 struct ib_qp_init_attr
*init_attr
,
775 struct mlx5_ib_qp
*qp
,
776 struct mlx5_create_qp_mbox_in
**in
, int *inlen
,
777 struct mlx5_ib_qp_base
*base
)
779 enum mlx5_ib_latency_class lc
= MLX5_IB_LATENCY_CLASS_LOW
;
780 struct mlx5_uuar_info
*uuari
;
785 uuari
= &dev
->mdev
->priv
.uuari
;
786 if (init_attr
->create_flags
& ~(IB_QP_CREATE_SIGNATURE_EN
| IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
))
789 if (init_attr
->qp_type
== MLX5_IB_QPT_REG_UMR
)
790 lc
= MLX5_IB_LATENCY_CLASS_FAST_PATH
;
792 uuarn
= alloc_uuar(uuari
, lc
);
794 mlx5_ib_dbg(dev
, "\n");
798 qp
->bf
= &uuari
->bfs
[uuarn
];
799 uar_index
= qp
->bf
->uar
->index
;
801 err
= calc_sq_size(dev
, init_attr
, qp
);
803 mlx5_ib_dbg(dev
, "err %d\n", err
);
808 qp
->sq
.offset
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
809 base
->ubuffer
.buf_size
= err
+ (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
);
811 err
= mlx5_buf_alloc(dev
->mdev
, base
->ubuffer
.buf_size
, &qp
->buf
);
813 mlx5_ib_dbg(dev
, "err %d\n", err
);
817 qp
->sq
.qend
= mlx5_get_send_wqe(qp
, qp
->sq
.wqe_cnt
);
818 *inlen
= sizeof(**in
) + sizeof(*(*in
)->pas
) * qp
->buf
.npages
;
819 *in
= mlx5_vzalloc(*inlen
);
824 (*in
)->ctx
.qp_counter_set_usr_page
= cpu_to_be32(uar_index
);
825 (*in
)->ctx
.log_pg_sz_remote_qpn
=
826 cpu_to_be32((qp
->buf
.page_shift
- MLX5_ADAPTER_PAGE_SHIFT
) << 24);
827 /* Set "fast registration enabled" for all kernel QPs */
828 (*in
)->ctx
.params1
|= cpu_to_be32(1 << 11);
829 (*in
)->ctx
.sq_crq_size
|= cpu_to_be16(1 << 4);
831 mlx5_fill_page_array(&qp
->buf
, (*in
)->pas
);
833 err
= mlx5_db_alloc(dev
->mdev
, &qp
->db
);
835 mlx5_ib_dbg(dev
, "err %d\n", err
);
839 qp
->sq
.wrid
= kmalloc(qp
->sq
.wqe_cnt
* sizeof(*qp
->sq
.wrid
), GFP_KERNEL
);
840 qp
->sq
.wr_data
= kmalloc(qp
->sq
.wqe_cnt
* sizeof(*qp
->sq
.wr_data
), GFP_KERNEL
);
841 qp
->rq
.wrid
= kmalloc(qp
->rq
.wqe_cnt
* sizeof(*qp
->rq
.wrid
), GFP_KERNEL
);
842 qp
->sq
.w_list
= kmalloc(qp
->sq
.wqe_cnt
* sizeof(*qp
->sq
.w_list
), GFP_KERNEL
);
843 qp
->sq
.wqe_head
= kmalloc(qp
->sq
.wqe_cnt
* sizeof(*qp
->sq
.wqe_head
), GFP_KERNEL
);
845 if (!qp
->sq
.wrid
|| !qp
->sq
.wr_data
|| !qp
->rq
.wrid
||
846 !qp
->sq
.w_list
|| !qp
->sq
.wqe_head
) {
850 qp
->create_type
= MLX5_QP_KERNEL
;
855 mlx5_db_free(dev
->mdev
, &qp
->db
);
856 kfree(qp
->sq
.wqe_head
);
857 kfree(qp
->sq
.w_list
);
859 kfree(qp
->sq
.wr_data
);
866 mlx5_buf_free(dev
->mdev
, &qp
->buf
);
869 free_uuar(&dev
->mdev
->priv
.uuari
, uuarn
);
873 static void destroy_qp_kernel(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
)
875 mlx5_db_free(dev
->mdev
, &qp
->db
);
876 kfree(qp
->sq
.wqe_head
);
877 kfree(qp
->sq
.w_list
);
879 kfree(qp
->sq
.wr_data
);
881 mlx5_buf_free(dev
->mdev
, &qp
->buf
);
882 free_uuar(&dev
->mdev
->priv
.uuari
, qp
->bf
->uuarn
);
885 static __be32
get_rx_type(struct mlx5_ib_qp
*qp
, struct ib_qp_init_attr
*attr
)
887 if (attr
->srq
|| (attr
->qp_type
== IB_QPT_XRC_TGT
) ||
888 (attr
->qp_type
== IB_QPT_XRC_INI
))
889 return cpu_to_be32(MLX5_SRQ_RQ
);
890 else if (!qp
->has_rq
)
891 return cpu_to_be32(MLX5_ZERO_LEN_RQ
);
893 return cpu_to_be32(MLX5_NON_ZERO_RQ
);
896 static int is_connected(enum ib_qp_type qp_type
)
898 if (qp_type
== IB_QPT_RC
|| qp_type
== IB_QPT_UC
)
904 static int create_raw_packet_qp_tis(struct mlx5_ib_dev
*dev
,
905 struct mlx5_ib_sq
*sq
, u32 tdn
)
907 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)];
908 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
910 memset(in
, 0, sizeof(in
));
912 MLX5_SET(tisc
, tisc
, transport_domain
, tdn
);
914 return mlx5_core_create_tis(dev
->mdev
, in
, sizeof(in
), &sq
->tisn
);
917 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev
*dev
,
918 struct mlx5_ib_sq
*sq
)
920 mlx5_core_destroy_tis(dev
->mdev
, sq
->tisn
);
923 static int create_raw_packet_qp_sq(struct mlx5_ib_dev
*dev
,
924 struct mlx5_ib_sq
*sq
, void *qpin
,
927 struct mlx5_ib_ubuffer
*ubuffer
= &sq
->ubuffer
;
931 void *qpc
= MLX5_ADDR_OF(create_qp_in
, qpin
, qpc
);
940 err
= mlx5_ib_umem_get(dev
, pd
, ubuffer
->buf_addr
, ubuffer
->buf_size
,
941 &sq
->ubuffer
.umem
, &npages
, &page_shift
,
946 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) + sizeof(u64
) * ncont
;
947 in
= mlx5_vzalloc(inlen
);
953 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
954 MLX5_SET(sqc
, sqc
, flush_in_error_en
, 1);
955 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
956 MLX5_SET(sqc
, sqc
, user_index
, MLX5_GET(qpc
, qpc
, user_index
));
957 MLX5_SET(sqc
, sqc
, cqn
, MLX5_GET(qpc
, qpc
, cqn_snd
));
958 MLX5_SET(sqc
, sqc
, tis_lst_sz
, 1);
959 MLX5_SET(sqc
, sqc
, tis_num_0
, sq
->tisn
);
961 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
962 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
963 MLX5_SET(wq
, wq
, pd
, MLX5_GET(qpc
, qpc
, pd
));
964 MLX5_SET(wq
, wq
, uar_page
, MLX5_GET(qpc
, qpc
, uar_page
));
965 MLX5_SET64(wq
, wq
, dbr_addr
, MLX5_GET64(qpc
, qpc
, dbr_addr
));
966 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
967 MLX5_SET(wq
, wq
, log_wq_sz
, MLX5_GET(qpc
, qpc
, log_sq_size
));
968 MLX5_SET(wq
, wq
, log_wq_pg_sz
, page_shift
- MLX5_ADAPTER_PAGE_SHIFT
);
969 MLX5_SET(wq
, wq
, page_offset
, offset
);
971 pas
= (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
);
972 mlx5_ib_populate_pas(dev
, sq
->ubuffer
.umem
, page_shift
, pas
, 0);
974 err
= mlx5_core_create_sq_tracked(dev
->mdev
, in
, inlen
, &sq
->base
.mqp
);
984 ib_umem_release(sq
->ubuffer
.umem
);
985 sq
->ubuffer
.umem
= NULL
;
990 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev
*dev
,
991 struct mlx5_ib_sq
*sq
)
993 mlx5_core_destroy_sq_tracked(dev
->mdev
, &sq
->base
.mqp
);
994 ib_umem_release(sq
->ubuffer
.umem
);
997 static int get_rq_pas_size(void *qpc
)
999 u32 log_page_size
= MLX5_GET(qpc
, qpc
, log_page_size
) + 12;
1000 u32 log_rq_stride
= MLX5_GET(qpc
, qpc
, log_rq_stride
);
1001 u32 log_rq_size
= MLX5_GET(qpc
, qpc
, log_rq_size
);
1002 u32 page_offset
= MLX5_GET(qpc
, qpc
, page_offset
);
1003 u32 po_quanta
= 1 << (log_page_size
- 6);
1004 u32 rq_sz
= 1 << (log_rq_size
+ 4 + log_rq_stride
);
1005 u32 page_size
= 1 << log_page_size
;
1006 u32 rq_sz_po
= rq_sz
+ (page_offset
* po_quanta
);
1007 u32 rq_num_pas
= (rq_sz_po
+ page_size
- 1) / page_size
;
1009 return rq_num_pas
* sizeof(u64
);
1012 static int create_raw_packet_qp_rq(struct mlx5_ib_dev
*dev
,
1013 struct mlx5_ib_rq
*rq
, void *qpin
)
1020 void *qpc
= MLX5_ADDR_OF(create_qp_in
, qpin
, qpc
);
1023 u32 rq_pas_size
= get_rq_pas_size(qpc
);
1025 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) + rq_pas_size
;
1026 in
= mlx5_vzalloc(inlen
);
1030 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
1031 MLX5_SET(rqc
, rqc
, vsd
, 1);
1032 MLX5_SET(rqc
, rqc
, mem_rq_type
, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
);
1033 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
1034 MLX5_SET(rqc
, rqc
, flush_in_error_en
, 1);
1035 MLX5_SET(rqc
, rqc
, user_index
, MLX5_GET(qpc
, qpc
, user_index
));
1036 MLX5_SET(rqc
, rqc
, cqn
, MLX5_GET(qpc
, qpc
, cqn_rcv
));
1038 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1039 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
1040 MLX5_SET(wq
, wq
, end_padding_mode
,
1041 MLX5_GET(qpc
, qpc
, end_padding_mode
));
1042 MLX5_SET(wq
, wq
, page_offset
, MLX5_GET(qpc
, qpc
, page_offset
));
1043 MLX5_SET(wq
, wq
, pd
, MLX5_GET(qpc
, qpc
, pd
));
1044 MLX5_SET64(wq
, wq
, dbr_addr
, MLX5_GET64(qpc
, qpc
, dbr_addr
));
1045 MLX5_SET(wq
, wq
, log_wq_stride
, MLX5_GET(qpc
, qpc
, log_rq_stride
) + 4);
1046 MLX5_SET(wq
, wq
, log_wq_pg_sz
, MLX5_GET(qpc
, qpc
, log_page_size
));
1047 MLX5_SET(wq
, wq
, log_wq_sz
, MLX5_GET(qpc
, qpc
, log_rq_size
));
1049 pas
= (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
);
1050 qp_pas
= (__be64
*)MLX5_ADDR_OF(create_qp_in
, qpin
, pas
);
1051 memcpy(pas
, qp_pas
, rq_pas_size
);
1053 err
= mlx5_core_create_rq_tracked(dev
->mdev
, in
, inlen
, &rq
->base
.mqp
);
1060 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev
*dev
,
1061 struct mlx5_ib_rq
*rq
)
1063 mlx5_core_destroy_rq_tracked(dev
->mdev
, &rq
->base
.mqp
);
1066 static int create_raw_packet_qp_tir(struct mlx5_ib_dev
*dev
,
1067 struct mlx5_ib_rq
*rq
, u32 tdn
)
1074 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
1075 in
= mlx5_vzalloc(inlen
);
1079 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
1080 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_DIRECT
);
1081 MLX5_SET(tirc
, tirc
, inline_rqn
, rq
->base
.mqp
.qpn
);
1082 MLX5_SET(tirc
, tirc
, transport_domain
, tdn
);
1084 err
= mlx5_core_create_tir(dev
->mdev
, in
, inlen
, &rq
->tirn
);
1091 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev
*dev
,
1092 struct mlx5_ib_rq
*rq
)
1094 mlx5_core_destroy_tir(dev
->mdev
, rq
->tirn
);
1097 static int create_raw_packet_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
1098 struct mlx5_create_qp_mbox_in
*in
,
1101 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
1102 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
1103 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
1104 struct ib_uobject
*uobj
= pd
->uobject
;
1105 struct ib_ucontext
*ucontext
= uobj
->context
;
1106 struct mlx5_ib_ucontext
*mucontext
= to_mucontext(ucontext
);
1108 u32 tdn
= mucontext
->tdn
;
1110 if (qp
->sq
.wqe_cnt
) {
1111 err
= create_raw_packet_qp_tis(dev
, sq
, tdn
);
1115 err
= create_raw_packet_qp_sq(dev
, sq
, in
, pd
);
1117 goto err_destroy_tis
;
1119 sq
->base
.container_mibqp
= qp
;
1122 if (qp
->rq
.wqe_cnt
) {
1123 err
= create_raw_packet_qp_rq(dev
, rq
, in
);
1125 goto err_destroy_sq
;
1127 rq
->base
.container_mibqp
= qp
;
1129 err
= create_raw_packet_qp_tir(dev
, rq
, tdn
);
1131 goto err_destroy_rq
;
1134 qp
->trans_qp
.base
.mqp
.qpn
= qp
->sq
.wqe_cnt
? sq
->base
.mqp
.qpn
:
1140 destroy_raw_packet_qp_rq(dev
, rq
);
1142 if (!qp
->sq
.wqe_cnt
)
1144 destroy_raw_packet_qp_sq(dev
, sq
);
1146 destroy_raw_packet_qp_tis(dev
, sq
);
1151 static void destroy_raw_packet_qp(struct mlx5_ib_dev
*dev
,
1152 struct mlx5_ib_qp
*qp
)
1154 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
1155 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
1156 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
1158 if (qp
->rq
.wqe_cnt
) {
1159 destroy_raw_packet_qp_tir(dev
, rq
);
1160 destroy_raw_packet_qp_rq(dev
, rq
);
1163 if (qp
->sq
.wqe_cnt
) {
1164 destroy_raw_packet_qp_sq(dev
, sq
);
1165 destroy_raw_packet_qp_tis(dev
, sq
);
1169 static void raw_packet_qp_copy_info(struct mlx5_ib_qp
*qp
,
1170 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
)
1172 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
1173 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
1177 sq
->doorbell
= &qp
->db
;
1178 rq
->doorbell
= &qp
->db
;
1181 static int create_qp_common(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
1182 struct ib_qp_init_attr
*init_attr
,
1183 struct ib_udata
*udata
, struct mlx5_ib_qp
*qp
)
1185 struct mlx5_ib_resources
*devr
= &dev
->devr
;
1186 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1187 struct mlx5_ib_qp_base
*base
;
1188 struct mlx5_ib_create_qp_resp resp
;
1189 struct mlx5_create_qp_mbox_in
*in
;
1190 struct mlx5_ib_create_qp ucmd
;
1191 int inlen
= sizeof(*in
);
1193 u32 uidx
= MLX5_IB_DEFAULT_UIDX
;
1196 base
= init_attr
->qp_type
== IB_QPT_RAW_PACKET
?
1197 &qp
->raw_packet_qp
.rq
.base
:
1200 if (init_attr
->qp_type
!= IB_QPT_RAW_PACKET
)
1201 mlx5_ib_odp_create_qp(qp
);
1203 mutex_init(&qp
->mutex
);
1204 spin_lock_init(&qp
->sq
.lock
);
1205 spin_lock_init(&qp
->rq
.lock
);
1207 if (init_attr
->create_flags
& IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
) {
1208 if (!MLX5_CAP_GEN(mdev
, block_lb_mc
)) {
1209 mlx5_ib_dbg(dev
, "block multicast loopback isn't supported\n");
1212 qp
->flags
|= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
;
1216 if (init_attr
->create_flags
&
1217 (IB_QP_CREATE_CROSS_CHANNEL
|
1218 IB_QP_CREATE_MANAGED_SEND
|
1219 IB_QP_CREATE_MANAGED_RECV
)) {
1220 if (!MLX5_CAP_GEN(mdev
, cd
)) {
1221 mlx5_ib_dbg(dev
, "cross-channel isn't supported\n");
1224 if (init_attr
->create_flags
& IB_QP_CREATE_CROSS_CHANNEL
)
1225 qp
->flags
|= MLX5_IB_QP_CROSS_CHANNEL
;
1226 if (init_attr
->create_flags
& IB_QP_CREATE_MANAGED_SEND
)
1227 qp
->flags
|= MLX5_IB_QP_MANAGED_SEND
;
1228 if (init_attr
->create_flags
& IB_QP_CREATE_MANAGED_RECV
)
1229 qp
->flags
|= MLX5_IB_QP_MANAGED_RECV
;
1231 if (init_attr
->sq_sig_type
== IB_SIGNAL_ALL_WR
)
1232 qp
->sq_signal_bits
= MLX5_WQE_CTRL_CQ_UPDATE
;
1234 if (pd
&& pd
->uobject
) {
1235 if (ib_copy_from_udata(&ucmd
, udata
, sizeof(ucmd
))) {
1236 mlx5_ib_dbg(dev
, "copy failed\n");
1240 err
= get_qp_user_index(to_mucontext(pd
->uobject
->context
),
1241 &ucmd
, udata
->inlen
, &uidx
);
1245 qp
->wq_sig
= !!(ucmd
.flags
& MLX5_QP_FLAG_SIGNATURE
);
1246 qp
->scat_cqe
= !!(ucmd
.flags
& MLX5_QP_FLAG_SCATTER_CQE
);
1248 qp
->wq_sig
= !!wq_signature
;
1251 qp
->has_rq
= qp_has_rq(init_attr
);
1252 err
= set_rq_size(dev
, &init_attr
->cap
, qp
->has_rq
,
1253 qp
, (pd
&& pd
->uobject
) ? &ucmd
: NULL
);
1255 mlx5_ib_dbg(dev
, "err %d\n", err
);
1262 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
1263 mlx5_ib_dbg(dev
, "requested sq_wqe_count (%d)\n", ucmd
.sq_wqe_count
);
1264 if (ucmd
.rq_wqe_shift
!= qp
->rq
.wqe_shift
||
1265 ucmd
.rq_wqe_count
!= qp
->rq
.wqe_cnt
) {
1266 mlx5_ib_dbg(dev
, "invalid rq params\n");
1269 if (ucmd
.sq_wqe_count
> max_wqes
) {
1270 mlx5_ib_dbg(dev
, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1271 ucmd
.sq_wqe_count
, max_wqes
);
1274 err
= create_user_qp(dev
, pd
, qp
, udata
, init_attr
, &in
,
1275 &resp
, &inlen
, base
);
1277 mlx5_ib_dbg(dev
, "err %d\n", err
);
1279 err
= create_kernel_qp(dev
, init_attr
, qp
, &in
, &inlen
,
1282 mlx5_ib_dbg(dev
, "err %d\n", err
);
1288 in
= mlx5_vzalloc(sizeof(*in
));
1292 qp
->create_type
= MLX5_QP_EMPTY
;
1295 if (is_sqp(init_attr
->qp_type
))
1296 qp
->port
= init_attr
->port_num
;
1298 in
->ctx
.flags
= cpu_to_be32(to_mlx5_st(init_attr
->qp_type
) << 16 |
1299 MLX5_QP_PM_MIGRATED
<< 11);
1301 if (init_attr
->qp_type
!= MLX5_IB_QPT_REG_UMR
)
1302 in
->ctx
.flags_pd
= cpu_to_be32(to_mpd(pd
? pd
: devr
->p0
)->pdn
);
1304 in
->ctx
.flags_pd
= cpu_to_be32(MLX5_QP_LAT_SENSITIVE
);
1307 in
->ctx
.flags_pd
|= cpu_to_be32(MLX5_QP_ENABLE_SIG
);
1309 if (qp
->flags
& MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
)
1310 in
->ctx
.flags_pd
|= cpu_to_be32(MLX5_QP_BLOCK_MCAST
);
1312 if (qp
->flags
& MLX5_IB_QP_CROSS_CHANNEL
)
1313 in
->ctx
.params2
|= cpu_to_be32(MLX5_QP_BIT_CC_MASTER
);
1314 if (qp
->flags
& MLX5_IB_QP_MANAGED_SEND
)
1315 in
->ctx
.params2
|= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND
);
1316 if (qp
->flags
& MLX5_IB_QP_MANAGED_RECV
)
1317 in
->ctx
.params2
|= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV
);
1319 if (qp
->scat_cqe
&& is_connected(init_attr
->qp_type
)) {
1323 rcqe_sz
= mlx5_ib_get_cqe_size(dev
, init_attr
->recv_cq
);
1324 scqe_sz
= mlx5_ib_get_cqe_size(dev
, init_attr
->send_cq
);
1327 in
->ctx
.cs_res
= MLX5_RES_SCAT_DATA64_CQE
;
1329 in
->ctx
.cs_res
= MLX5_RES_SCAT_DATA32_CQE
;
1331 if (init_attr
->sq_sig_type
== IB_SIGNAL_ALL_WR
) {
1333 in
->ctx
.cs_req
= MLX5_REQ_SCAT_DATA64_CQE
;
1335 in
->ctx
.cs_req
= MLX5_REQ_SCAT_DATA32_CQE
;
1339 if (qp
->rq
.wqe_cnt
) {
1340 in
->ctx
.rq_size_stride
= (qp
->rq
.wqe_shift
- 4);
1341 in
->ctx
.rq_size_stride
|= ilog2(qp
->rq
.wqe_cnt
) << 3;
1344 in
->ctx
.rq_type_srqn
= get_rx_type(qp
, init_attr
);
1347 in
->ctx
.sq_crq_size
|= cpu_to_be16(ilog2(qp
->sq
.wqe_cnt
) << 11);
1349 in
->ctx
.sq_crq_size
|= cpu_to_be16(0x8000);
1351 /* Set default resources */
1352 switch (init_attr
->qp_type
) {
1353 case IB_QPT_XRC_TGT
:
1354 in
->ctx
.cqn_recv
= cpu_to_be32(to_mcq(devr
->c0
)->mcq
.cqn
);
1355 in
->ctx
.cqn_send
= cpu_to_be32(to_mcq(devr
->c0
)->mcq
.cqn
);
1356 in
->ctx
.rq_type_srqn
|= cpu_to_be32(to_msrq(devr
->s0
)->msrq
.srqn
);
1357 in
->ctx
.xrcd
= cpu_to_be32(to_mxrcd(init_attr
->xrcd
)->xrcdn
);
1359 case IB_QPT_XRC_INI
:
1360 in
->ctx
.cqn_recv
= cpu_to_be32(to_mcq(devr
->c0
)->mcq
.cqn
);
1361 in
->ctx
.xrcd
= cpu_to_be32(to_mxrcd(devr
->x1
)->xrcdn
);
1362 in
->ctx
.rq_type_srqn
|= cpu_to_be32(to_msrq(devr
->s0
)->msrq
.srqn
);
1365 if (init_attr
->srq
) {
1366 in
->ctx
.xrcd
= cpu_to_be32(to_mxrcd(devr
->x0
)->xrcdn
);
1367 in
->ctx
.rq_type_srqn
|= cpu_to_be32(to_msrq(init_attr
->srq
)->msrq
.srqn
);
1369 in
->ctx
.xrcd
= cpu_to_be32(to_mxrcd(devr
->x1
)->xrcdn
);
1370 in
->ctx
.rq_type_srqn
|=
1371 cpu_to_be32(to_msrq(devr
->s1
)->msrq
.srqn
);
1375 if (init_attr
->send_cq
)
1376 in
->ctx
.cqn_send
= cpu_to_be32(to_mcq(init_attr
->send_cq
)->mcq
.cqn
);
1378 if (init_attr
->recv_cq
)
1379 in
->ctx
.cqn_recv
= cpu_to_be32(to_mcq(init_attr
->recv_cq
)->mcq
.cqn
);
1381 in
->ctx
.db_rec_addr
= cpu_to_be64(qp
->db
.dma
);
1383 if (MLX5_CAP_GEN(mdev
, cqe_version
) == MLX5_CQE_VERSION_V1
) {
1384 qpc
= MLX5_ADDR_OF(create_qp_in
, in
, qpc
);
1385 /* 0xffffff means we ask to work with cqe version 0 */
1386 MLX5_SET(qpc
, qpc
, user_index
, uidx
);
1389 if (init_attr
->qp_type
== IB_QPT_RAW_PACKET
) {
1390 qp
->raw_packet_qp
.sq
.ubuffer
.buf_addr
= ucmd
.sq_buf_addr
;
1391 raw_packet_qp_copy_info(qp
, &qp
->raw_packet_qp
);
1392 err
= create_raw_packet_qp(dev
, qp
, in
, pd
);
1394 err
= mlx5_core_create_qp(dev
->mdev
, &base
->mqp
, in
, inlen
);
1398 mlx5_ib_dbg(dev
, "create qp failed\n");
1404 base
->container_mibqp
= qp
;
1405 base
->mqp
.event
= mlx5_ib_qp_event
;
1410 if (qp
->create_type
== MLX5_QP_USER
)
1411 destroy_qp_user(pd
, qp
, base
);
1412 else if (qp
->create_type
== MLX5_QP_KERNEL
)
1413 destroy_qp_kernel(dev
, qp
);
1419 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq
*send_cq
, struct mlx5_ib_cq
*recv_cq
)
1420 __acquires(&send_cq
->lock
) __acquires(&recv_cq
->lock
)
1424 if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
1425 spin_lock_irq(&send_cq
->lock
);
1426 spin_lock_nested(&recv_cq
->lock
,
1427 SINGLE_DEPTH_NESTING
);
1428 } else if (send_cq
->mcq
.cqn
== recv_cq
->mcq
.cqn
) {
1429 spin_lock_irq(&send_cq
->lock
);
1430 __acquire(&recv_cq
->lock
);
1432 spin_lock_irq(&recv_cq
->lock
);
1433 spin_lock_nested(&send_cq
->lock
,
1434 SINGLE_DEPTH_NESTING
);
1437 spin_lock_irq(&send_cq
->lock
);
1438 __acquire(&recv_cq
->lock
);
1440 } else if (recv_cq
) {
1441 spin_lock_irq(&recv_cq
->lock
);
1442 __acquire(&send_cq
->lock
);
1444 __acquire(&send_cq
->lock
);
1445 __acquire(&recv_cq
->lock
);
1449 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq
*send_cq
, struct mlx5_ib_cq
*recv_cq
)
1450 __releases(&send_cq
->lock
) __releases(&recv_cq
->lock
)
1454 if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
1455 spin_unlock(&recv_cq
->lock
);
1456 spin_unlock_irq(&send_cq
->lock
);
1457 } else if (send_cq
->mcq
.cqn
== recv_cq
->mcq
.cqn
) {
1458 __release(&recv_cq
->lock
);
1459 spin_unlock_irq(&send_cq
->lock
);
1461 spin_unlock(&send_cq
->lock
);
1462 spin_unlock_irq(&recv_cq
->lock
);
1465 __release(&recv_cq
->lock
);
1466 spin_unlock_irq(&send_cq
->lock
);
1468 } else if (recv_cq
) {
1469 __release(&send_cq
->lock
);
1470 spin_unlock_irq(&recv_cq
->lock
);
1472 __release(&recv_cq
->lock
);
1473 __release(&send_cq
->lock
);
1477 static struct mlx5_ib_pd
*get_pd(struct mlx5_ib_qp
*qp
)
1479 return to_mpd(qp
->ibqp
.pd
);
1482 static void get_cqs(struct mlx5_ib_qp
*qp
,
1483 struct mlx5_ib_cq
**send_cq
, struct mlx5_ib_cq
**recv_cq
)
1485 switch (qp
->ibqp
.qp_type
) {
1486 case IB_QPT_XRC_TGT
:
1490 case MLX5_IB_QPT_REG_UMR
:
1491 case IB_QPT_XRC_INI
:
1492 *send_cq
= to_mcq(qp
->ibqp
.send_cq
);
1501 case IB_QPT_RAW_IPV6
:
1502 case IB_QPT_RAW_ETHERTYPE
:
1503 case IB_QPT_RAW_PACKET
:
1504 *send_cq
= to_mcq(qp
->ibqp
.send_cq
);
1505 *recv_cq
= to_mcq(qp
->ibqp
.recv_cq
);
1516 static int modify_raw_packet_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
1519 static void destroy_qp_common(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
)
1521 struct mlx5_ib_cq
*send_cq
, *recv_cq
;
1522 struct mlx5_ib_qp_base
*base
= &qp
->trans_qp
.base
;
1523 struct mlx5_modify_qp_mbox_in
*in
;
1526 base
= qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
?
1527 &qp
->raw_packet_qp
.rq
.base
:
1530 in
= kzalloc(sizeof(*in
), GFP_KERNEL
);
1534 if (qp
->state
!= IB_QPS_RESET
) {
1535 if (qp
->ibqp
.qp_type
!= IB_QPT_RAW_PACKET
) {
1536 mlx5_ib_qp_disable_pagefaults(qp
);
1537 err
= mlx5_core_qp_modify(dev
->mdev
,
1538 MLX5_CMD_OP_2RST_QP
, in
, 0,
1541 err
= modify_raw_packet_qp(dev
, qp
,
1542 MLX5_CMD_OP_2RST_QP
);
1545 mlx5_ib_warn(dev
, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1549 get_cqs(qp
, &send_cq
, &recv_cq
);
1551 if (qp
->create_type
== MLX5_QP_KERNEL
) {
1552 mlx5_ib_lock_cqs(send_cq
, recv_cq
);
1553 __mlx5_ib_cq_clean(recv_cq
, base
->mqp
.qpn
,
1554 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
1555 if (send_cq
!= recv_cq
)
1556 __mlx5_ib_cq_clean(send_cq
, base
->mqp
.qpn
,
1558 mlx5_ib_unlock_cqs(send_cq
, recv_cq
);
1561 if (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
) {
1562 destroy_raw_packet_qp(dev
, qp
);
1564 err
= mlx5_core_destroy_qp(dev
->mdev
, &base
->mqp
);
1566 mlx5_ib_warn(dev
, "failed to destroy QP 0x%x\n",
1572 if (qp
->create_type
== MLX5_QP_KERNEL
)
1573 destroy_qp_kernel(dev
, qp
);
1574 else if (qp
->create_type
== MLX5_QP_USER
)
1575 destroy_qp_user(&get_pd(qp
)->ibpd
, qp
, base
);
1578 static const char *ib_qp_type_str(enum ib_qp_type type
)
1582 return "IB_QPT_SMI";
1584 return "IB_QPT_GSI";
1591 case IB_QPT_RAW_IPV6
:
1592 return "IB_QPT_RAW_IPV6";
1593 case IB_QPT_RAW_ETHERTYPE
:
1594 return "IB_QPT_RAW_ETHERTYPE";
1595 case IB_QPT_XRC_INI
:
1596 return "IB_QPT_XRC_INI";
1597 case IB_QPT_XRC_TGT
:
1598 return "IB_QPT_XRC_TGT";
1599 case IB_QPT_RAW_PACKET
:
1600 return "IB_QPT_RAW_PACKET";
1601 case MLX5_IB_QPT_REG_UMR
:
1602 return "MLX5_IB_QPT_REG_UMR";
1605 return "Invalid QP type";
1609 struct ib_qp
*mlx5_ib_create_qp(struct ib_pd
*pd
,
1610 struct ib_qp_init_attr
*init_attr
,
1611 struct ib_udata
*udata
)
1613 struct mlx5_ib_dev
*dev
;
1614 struct mlx5_ib_qp
*qp
;
1619 dev
= to_mdev(pd
->device
);
1621 if (init_attr
->qp_type
== IB_QPT_RAW_PACKET
) {
1623 mlx5_ib_dbg(dev
, "Raw Packet QP is not supported for kernel consumers\n");
1624 return ERR_PTR(-EINVAL
);
1625 } else if (!to_mucontext(pd
->uobject
->context
)->cqe_version
) {
1626 mlx5_ib_dbg(dev
, "Raw Packet QP is only supported for CQE version > 0\n");
1627 return ERR_PTR(-EINVAL
);
1631 /* being cautious here */
1632 if (init_attr
->qp_type
!= IB_QPT_XRC_TGT
&&
1633 init_attr
->qp_type
!= MLX5_IB_QPT_REG_UMR
) {
1634 pr_warn("%s: no PD for transport %s\n", __func__
,
1635 ib_qp_type_str(init_attr
->qp_type
));
1636 return ERR_PTR(-EINVAL
);
1638 dev
= to_mdev(to_mxrcd(init_attr
->xrcd
)->ibxrcd
.device
);
1641 switch (init_attr
->qp_type
) {
1642 case IB_QPT_XRC_TGT
:
1643 case IB_QPT_XRC_INI
:
1644 if (!MLX5_CAP_GEN(dev
->mdev
, xrc
)) {
1645 mlx5_ib_dbg(dev
, "XRC not supported\n");
1646 return ERR_PTR(-ENOSYS
);
1648 init_attr
->recv_cq
= NULL
;
1649 if (init_attr
->qp_type
== IB_QPT_XRC_TGT
) {
1650 xrcdn
= to_mxrcd(init_attr
->xrcd
)->xrcdn
;
1651 init_attr
->send_cq
= NULL
;
1655 case IB_QPT_RAW_PACKET
:
1661 case MLX5_IB_QPT_REG_UMR
:
1662 qp
= kzalloc(sizeof(*qp
), GFP_KERNEL
);
1664 return ERR_PTR(-ENOMEM
);
1666 err
= create_qp_common(dev
, pd
, init_attr
, udata
, qp
);
1668 mlx5_ib_dbg(dev
, "create_qp_common failed\n");
1670 return ERR_PTR(err
);
1673 if (is_qp0(init_attr
->qp_type
))
1674 qp
->ibqp
.qp_num
= 0;
1675 else if (is_qp1(init_attr
->qp_type
))
1676 qp
->ibqp
.qp_num
= 1;
1678 qp
->ibqp
.qp_num
= qp
->trans_qp
.base
.mqp
.qpn
;
1680 mlx5_ib_dbg(dev
, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1681 qp
->ibqp
.qp_num
, qp
->trans_qp
.base
.mqp
.qpn
,
1682 to_mcq(init_attr
->recv_cq
)->mcq
.cqn
,
1683 to_mcq(init_attr
->send_cq
)->mcq
.cqn
);
1685 qp
->trans_qp
.xrcdn
= xrcdn
;
1689 case IB_QPT_RAW_IPV6
:
1690 case IB_QPT_RAW_ETHERTYPE
:
1693 mlx5_ib_dbg(dev
, "unsupported qp type %d\n",
1694 init_attr
->qp_type
);
1695 /* Don't support raw QPs */
1696 return ERR_PTR(-EINVAL
);
1702 int mlx5_ib_destroy_qp(struct ib_qp
*qp
)
1704 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
1705 struct mlx5_ib_qp
*mqp
= to_mqp(qp
);
1707 destroy_qp_common(dev
, mqp
);
1714 static __be32
to_mlx5_access_flags(struct mlx5_ib_qp
*qp
, const struct ib_qp_attr
*attr
,
1717 u32 hw_access_flags
= 0;
1721 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
1722 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
1724 dest_rd_atomic
= qp
->trans_qp
.resp_depth
;
1726 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
1727 access_flags
= attr
->qp_access_flags
;
1729 access_flags
= qp
->trans_qp
.atomic_rd_en
;
1731 if (!dest_rd_atomic
)
1732 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
1734 if (access_flags
& IB_ACCESS_REMOTE_READ
)
1735 hw_access_flags
|= MLX5_QP_BIT_RRE
;
1736 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
1737 hw_access_flags
|= (MLX5_QP_BIT_RAE
| MLX5_ATOMIC_MODE_CX
);
1738 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
1739 hw_access_flags
|= MLX5_QP_BIT_RWE
;
1741 return cpu_to_be32(hw_access_flags
);
1745 MLX5_PATH_FLAG_FL
= 1 << 0,
1746 MLX5_PATH_FLAG_FREE_AR
= 1 << 1,
1747 MLX5_PATH_FLAG_COUNTER
= 1 << 2,
1750 static int ib_rate_to_mlx5(struct mlx5_ib_dev
*dev
, u8 rate
)
1752 if (rate
== IB_RATE_PORT_CURRENT
) {
1754 } else if (rate
< IB_RATE_2_5_GBPS
|| rate
> IB_RATE_300_GBPS
) {
1757 while (rate
!= IB_RATE_2_5_GBPS
&&
1758 !(1 << (rate
+ MLX5_STAT_RATE_OFFSET
) &
1759 MLX5_CAP_GEN(dev
->mdev
, stat_rate_support
)))
1763 return rate
+ MLX5_STAT_RATE_OFFSET
;
1766 static int modify_raw_packet_eth_prio(struct mlx5_core_dev
*dev
,
1767 struct mlx5_ib_sq
*sq
, u8 sl
)
1774 inlen
= MLX5_ST_SZ_BYTES(modify_tis_in
);
1775 in
= mlx5_vzalloc(inlen
);
1779 MLX5_SET(modify_tis_in
, in
, bitmask
.prio
, 1);
1781 tisc
= MLX5_ADDR_OF(modify_tis_in
, in
, ctx
);
1782 MLX5_SET(tisc
, tisc
, prio
, ((sl
& 0x7) << 1));
1784 err
= mlx5_core_modify_tis(dev
, sq
->tisn
, in
, inlen
);
1791 static int mlx5_set_path(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
1792 const struct ib_ah_attr
*ah
,
1793 struct mlx5_qp_path
*path
, u8 port
, int attr_mask
,
1794 u32 path_flags
, const struct ib_qp_attr
*attr
)
1796 enum rdma_link_layer ll
= rdma_port_get_link_layer(&dev
->ib_dev
, port
);
1799 if (attr_mask
& IB_QP_PKEY_INDEX
)
1800 path
->pkey_index
= attr
->pkey_index
;
1802 if (ah
->ah_flags
& IB_AH_GRH
) {
1803 if (ah
->grh
.sgid_index
>=
1804 dev
->mdev
->port_caps
[port
- 1].gid_table_len
) {
1805 pr_err("sgid_index (%u) too large. max is %d\n",
1807 dev
->mdev
->port_caps
[port
- 1].gid_table_len
);
1812 if (ll
== IB_LINK_LAYER_ETHERNET
) {
1813 if (!(ah
->ah_flags
& IB_AH_GRH
))
1815 memcpy(path
->rmac
, ah
->dmac
, sizeof(ah
->dmac
));
1816 path
->udp_sport
= mlx5_get_roce_udp_sport(dev
, port
,
1817 ah
->grh
.sgid_index
);
1818 path
->dci_cfi_prio_sl
= (ah
->sl
& 0x7) << 4;
1820 path
->fl
= (path_flags
& MLX5_PATH_FLAG_FL
) ? 0x80 : 0;
1821 path
->free_ar
= (path_flags
& MLX5_PATH_FLAG_FREE_AR
) ? 0x80 :
1823 path
->rlid
= cpu_to_be16(ah
->dlid
);
1824 path
->grh_mlid
= ah
->src_path_bits
& 0x7f;
1825 if (ah
->ah_flags
& IB_AH_GRH
)
1826 path
->grh_mlid
|= 1 << 7;
1827 path
->dci_cfi_prio_sl
= ah
->sl
& 0xf;
1830 if (ah
->ah_flags
& IB_AH_GRH
) {
1831 path
->mgid_index
= ah
->grh
.sgid_index
;
1832 path
->hop_limit
= ah
->grh
.hop_limit
;
1833 path
->tclass_flowlabel
=
1834 cpu_to_be32((ah
->grh
.traffic_class
<< 20) |
1835 (ah
->grh
.flow_label
));
1836 memcpy(path
->rgid
, ah
->grh
.dgid
.raw
, 16);
1839 err
= ib_rate_to_mlx5(dev
, ah
->static_rate
);
1842 path
->static_rate
= err
;
1845 if (attr_mask
& IB_QP_TIMEOUT
)
1846 path
->ackto_lt
= attr
->timeout
<< 3;
1848 if ((qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
) && qp
->sq
.wqe_cnt
)
1849 return modify_raw_packet_eth_prio(dev
->mdev
,
1850 &qp
->raw_packet_qp
.sq
,
1856 static enum mlx5_qp_optpar opt_mask
[MLX5_QP_NUM_STATE
][MLX5_QP_NUM_STATE
][MLX5_QP_ST_MAX
] = {
1857 [MLX5_QP_STATE_INIT
] = {
1858 [MLX5_QP_STATE_INIT
] = {
1859 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_RRE
|
1860 MLX5_QP_OPTPAR_RAE
|
1861 MLX5_QP_OPTPAR_RWE
|
1862 MLX5_QP_OPTPAR_PKEY_INDEX
|
1863 MLX5_QP_OPTPAR_PRI_PORT
,
1864 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_RWE
|
1865 MLX5_QP_OPTPAR_PKEY_INDEX
|
1866 MLX5_QP_OPTPAR_PRI_PORT
,
1867 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_PKEY_INDEX
|
1868 MLX5_QP_OPTPAR_Q_KEY
|
1869 MLX5_QP_OPTPAR_PRI_PORT
,
1871 [MLX5_QP_STATE_RTR
] = {
1872 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
1873 MLX5_QP_OPTPAR_RRE
|
1874 MLX5_QP_OPTPAR_RAE
|
1875 MLX5_QP_OPTPAR_RWE
|
1876 MLX5_QP_OPTPAR_PKEY_INDEX
,
1877 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
1878 MLX5_QP_OPTPAR_RWE
|
1879 MLX5_QP_OPTPAR_PKEY_INDEX
,
1880 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_PKEY_INDEX
|
1881 MLX5_QP_OPTPAR_Q_KEY
,
1882 [MLX5_QP_ST_MLX
] = MLX5_QP_OPTPAR_PKEY_INDEX
|
1883 MLX5_QP_OPTPAR_Q_KEY
,
1884 [MLX5_QP_ST_XRC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
1885 MLX5_QP_OPTPAR_RRE
|
1886 MLX5_QP_OPTPAR_RAE
|
1887 MLX5_QP_OPTPAR_RWE
|
1888 MLX5_QP_OPTPAR_PKEY_INDEX
,
1891 [MLX5_QP_STATE_RTR
] = {
1892 [MLX5_QP_STATE_RTS
] = {
1893 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
1894 MLX5_QP_OPTPAR_RRE
|
1895 MLX5_QP_OPTPAR_RAE
|
1896 MLX5_QP_OPTPAR_RWE
|
1897 MLX5_QP_OPTPAR_PM_STATE
|
1898 MLX5_QP_OPTPAR_RNR_TIMEOUT
,
1899 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
1900 MLX5_QP_OPTPAR_RWE
|
1901 MLX5_QP_OPTPAR_PM_STATE
,
1902 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_Q_KEY
,
1905 [MLX5_QP_STATE_RTS
] = {
1906 [MLX5_QP_STATE_RTS
] = {
1907 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_RRE
|
1908 MLX5_QP_OPTPAR_RAE
|
1909 MLX5_QP_OPTPAR_RWE
|
1910 MLX5_QP_OPTPAR_RNR_TIMEOUT
|
1911 MLX5_QP_OPTPAR_PM_STATE
|
1912 MLX5_QP_OPTPAR_ALT_ADDR_PATH
,
1913 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_RWE
|
1914 MLX5_QP_OPTPAR_PM_STATE
|
1915 MLX5_QP_OPTPAR_ALT_ADDR_PATH
,
1916 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_Q_KEY
|
1917 MLX5_QP_OPTPAR_SRQN
|
1918 MLX5_QP_OPTPAR_CQN_RCV
,
1921 [MLX5_QP_STATE_SQER
] = {
1922 [MLX5_QP_STATE_RTS
] = {
1923 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_Q_KEY
,
1924 [MLX5_QP_ST_MLX
] = MLX5_QP_OPTPAR_Q_KEY
,
1925 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_RWE
,
1926 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_RNR_TIMEOUT
|
1927 MLX5_QP_OPTPAR_RWE
|
1928 MLX5_QP_OPTPAR_RAE
|
1934 static int ib_nr_to_mlx5_nr(int ib_mask
)
1939 case IB_QP_CUR_STATE
:
1941 case IB_QP_EN_SQD_ASYNC_NOTIFY
:
1943 case IB_QP_ACCESS_FLAGS
:
1944 return MLX5_QP_OPTPAR_RWE
| MLX5_QP_OPTPAR_RRE
|
1946 case IB_QP_PKEY_INDEX
:
1947 return MLX5_QP_OPTPAR_PKEY_INDEX
;
1949 return MLX5_QP_OPTPAR_PRI_PORT
;
1951 return MLX5_QP_OPTPAR_Q_KEY
;
1953 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH
|
1954 MLX5_QP_OPTPAR_PRI_PORT
;
1955 case IB_QP_PATH_MTU
:
1958 return MLX5_QP_OPTPAR_ACK_TIMEOUT
;
1959 case IB_QP_RETRY_CNT
:
1960 return MLX5_QP_OPTPAR_RETRY_COUNT
;
1961 case IB_QP_RNR_RETRY
:
1962 return MLX5_QP_OPTPAR_RNR_RETRY
;
1965 case IB_QP_MAX_QP_RD_ATOMIC
:
1966 return MLX5_QP_OPTPAR_SRA_MAX
;
1967 case IB_QP_ALT_PATH
:
1968 return MLX5_QP_OPTPAR_ALT_ADDR_PATH
;
1969 case IB_QP_MIN_RNR_TIMER
:
1970 return MLX5_QP_OPTPAR_RNR_TIMEOUT
;
1973 case IB_QP_MAX_DEST_RD_ATOMIC
:
1974 return MLX5_QP_OPTPAR_RRA_MAX
| MLX5_QP_OPTPAR_RWE
|
1975 MLX5_QP_OPTPAR_RRE
| MLX5_QP_OPTPAR_RAE
;
1976 case IB_QP_PATH_MIG_STATE
:
1977 return MLX5_QP_OPTPAR_PM_STATE
;
1980 case IB_QP_DEST_QPN
:
1986 static int ib_mask_to_mlx5_opt(int ib_mask
)
1991 for (i
= 0; i
< 8 * sizeof(int); i
++) {
1992 if ((1 << i
) & ib_mask
)
1993 result
|= ib_nr_to_mlx5_nr(1 << i
);
1999 static int modify_raw_packet_qp_rq(struct mlx5_core_dev
*dev
,
2000 struct mlx5_ib_rq
*rq
, int new_state
)
2007 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
2008 in
= mlx5_vzalloc(inlen
);
2012 MLX5_SET(modify_rq_in
, in
, rq_state
, rq
->state
);
2014 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
2015 MLX5_SET(rqc
, rqc
, state
, new_state
);
2017 err
= mlx5_core_modify_rq(dev
, rq
->base
.mqp
.qpn
, in
, inlen
);
2021 rq
->state
= new_state
;
2028 static int modify_raw_packet_qp_sq(struct mlx5_core_dev
*dev
,
2029 struct mlx5_ib_sq
*sq
, int new_state
)
2036 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
2037 in
= mlx5_vzalloc(inlen
);
2041 MLX5_SET(modify_sq_in
, in
, sq_state
, sq
->state
);
2043 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
2044 MLX5_SET(sqc
, sqc
, state
, new_state
);
2046 err
= mlx5_core_modify_sq(dev
, sq
->base
.mqp
.qpn
, in
, inlen
);
2050 sq
->state
= new_state
;
2057 static int modify_raw_packet_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
2060 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
2061 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
2062 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
2067 switch (operation
) {
2068 case MLX5_CMD_OP_RST2INIT_QP
:
2069 rq_state
= MLX5_RQC_STATE_RDY
;
2070 sq_state
= MLX5_SQC_STATE_RDY
;
2072 case MLX5_CMD_OP_2ERR_QP
:
2073 rq_state
= MLX5_RQC_STATE_ERR
;
2074 sq_state
= MLX5_SQC_STATE_ERR
;
2076 case MLX5_CMD_OP_2RST_QP
:
2077 rq_state
= MLX5_RQC_STATE_RST
;
2078 sq_state
= MLX5_SQC_STATE_RST
;
2080 case MLX5_CMD_OP_INIT2INIT_QP
:
2081 case MLX5_CMD_OP_INIT2RTR_QP
:
2082 case MLX5_CMD_OP_RTR2RTS_QP
:
2083 case MLX5_CMD_OP_RTS2RTS_QP
:
2084 /* Nothing to do here... */
2091 if (qp
->rq
.wqe_cnt
) {
2092 err
= modify_raw_packet_qp_rq(dev
->mdev
, rq
, rq_state
);
2098 return modify_raw_packet_qp_sq(dev
->mdev
, sq
, sq_state
);
2103 static int __mlx5_ib_modify_qp(struct ib_qp
*ibqp
,
2104 const struct ib_qp_attr
*attr
, int attr_mask
,
2105 enum ib_qp_state cur_state
, enum ib_qp_state new_state
)
2107 static const u16 optab
[MLX5_QP_NUM_STATE
][MLX5_QP_NUM_STATE
] = {
2108 [MLX5_QP_STATE_RST
] = {
2109 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2110 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2111 [MLX5_QP_STATE_INIT
] = MLX5_CMD_OP_RST2INIT_QP
,
2113 [MLX5_QP_STATE_INIT
] = {
2114 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2115 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2116 [MLX5_QP_STATE_INIT
] = MLX5_CMD_OP_INIT2INIT_QP
,
2117 [MLX5_QP_STATE_RTR
] = MLX5_CMD_OP_INIT2RTR_QP
,
2119 [MLX5_QP_STATE_RTR
] = {
2120 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2121 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2122 [MLX5_QP_STATE_RTS
] = MLX5_CMD_OP_RTR2RTS_QP
,
2124 [MLX5_QP_STATE_RTS
] = {
2125 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2126 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2127 [MLX5_QP_STATE_RTS
] = MLX5_CMD_OP_RTS2RTS_QP
,
2129 [MLX5_QP_STATE_SQD
] = {
2130 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2131 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2133 [MLX5_QP_STATE_SQER
] = {
2134 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2135 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2136 [MLX5_QP_STATE_RTS
] = MLX5_CMD_OP_SQERR2RTS_QP
,
2138 [MLX5_QP_STATE_ERR
] = {
2139 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2140 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2144 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
2145 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
2146 struct mlx5_ib_qp_base
*base
= &qp
->trans_qp
.base
;
2147 struct mlx5_ib_cq
*send_cq
, *recv_cq
;
2148 struct mlx5_qp_context
*context
;
2149 struct mlx5_modify_qp_mbox_in
*in
;
2150 struct mlx5_ib_pd
*pd
;
2151 enum mlx5_qp_state mlx5_cur
, mlx5_new
;
2152 enum mlx5_qp_optpar optpar
;
2158 in
= kzalloc(sizeof(*in
), GFP_KERNEL
);
2163 err
= to_mlx5_st(ibqp
->qp_type
);
2167 context
->flags
= cpu_to_be32(err
<< 16);
2169 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
)) {
2170 context
->flags
|= cpu_to_be32(MLX5_QP_PM_MIGRATED
<< 11);
2172 switch (attr
->path_mig_state
) {
2173 case IB_MIG_MIGRATED
:
2174 context
->flags
|= cpu_to_be32(MLX5_QP_PM_MIGRATED
<< 11);
2177 context
->flags
|= cpu_to_be32(MLX5_QP_PM_REARM
<< 11);
2180 context
->flags
|= cpu_to_be32(MLX5_QP_PM_ARMED
<< 11);
2185 if (ibqp
->qp_type
== IB_QPT_GSI
|| ibqp
->qp_type
== IB_QPT_SMI
) {
2186 context
->mtu_msgmax
= (IB_MTU_256
<< 5) | 8;
2187 } else if (ibqp
->qp_type
== IB_QPT_UD
||
2188 ibqp
->qp_type
== MLX5_IB_QPT_REG_UMR
) {
2189 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) | 12;
2190 } else if (attr_mask
& IB_QP_PATH_MTU
) {
2191 if (attr
->path_mtu
< IB_MTU_256
||
2192 attr
->path_mtu
> IB_MTU_4096
) {
2193 mlx5_ib_warn(dev
, "invalid mtu %d\n", attr
->path_mtu
);
2197 context
->mtu_msgmax
= (attr
->path_mtu
<< 5) |
2198 (u8
)MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
2201 if (attr_mask
& IB_QP_DEST_QPN
)
2202 context
->log_pg_sz_remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
2204 if (attr_mask
& IB_QP_PKEY_INDEX
)
2205 context
->pri_path
.pkey_index
= attr
->pkey_index
;
2207 /* todo implement counter_index functionality */
2209 if (is_sqp(ibqp
->qp_type
))
2210 context
->pri_path
.port
= qp
->port
;
2212 if (attr_mask
& IB_QP_PORT
)
2213 context
->pri_path
.port
= attr
->port_num
;
2215 if (attr_mask
& IB_QP_AV
) {
2216 err
= mlx5_set_path(dev
, qp
, &attr
->ah_attr
, &context
->pri_path
,
2217 attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
,
2218 attr_mask
, 0, attr
);
2223 if (attr_mask
& IB_QP_TIMEOUT
)
2224 context
->pri_path
.ackto_lt
|= attr
->timeout
<< 3;
2226 if (attr_mask
& IB_QP_ALT_PATH
) {
2227 err
= mlx5_set_path(dev
, qp
, &attr
->alt_ah_attr
,
2229 attr
->alt_port_num
, attr_mask
, 0, attr
);
2235 get_cqs(qp
, &send_cq
, &recv_cq
);
2237 context
->flags_pd
= cpu_to_be32(pd
? pd
->pdn
: to_mpd(dev
->devr
.p0
)->pdn
);
2238 context
->cqn_send
= send_cq
? cpu_to_be32(send_cq
->mcq
.cqn
) : 0;
2239 context
->cqn_recv
= recv_cq
? cpu_to_be32(recv_cq
->mcq
.cqn
) : 0;
2240 context
->params1
= cpu_to_be32(MLX5_IB_ACK_REQ_FREQ
<< 28);
2242 if (attr_mask
& IB_QP_RNR_RETRY
)
2243 context
->params1
|= cpu_to_be32(attr
->rnr_retry
<< 13);
2245 if (attr_mask
& IB_QP_RETRY_CNT
)
2246 context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
2248 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
2249 if (attr
->max_rd_atomic
)
2251 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
2254 if (attr_mask
& IB_QP_SQ_PSN
)
2255 context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
2257 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
2258 if (attr
->max_dest_rd_atomic
)
2260 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
2263 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
))
2264 context
->params2
|= to_mlx5_access_flags(qp
, attr
, attr_mask
);
2266 if (attr_mask
& IB_QP_MIN_RNR_TIMER
)
2267 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
2269 if (attr_mask
& IB_QP_RQ_PSN
)
2270 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
2272 if (attr_mask
& IB_QP_QKEY
)
2273 context
->qkey
= cpu_to_be32(attr
->qkey
);
2275 if (qp
->rq
.wqe_cnt
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
2276 context
->db_rec_addr
= cpu_to_be64(qp
->db
.dma
);
2278 if (cur_state
== IB_QPS_RTS
&& new_state
== IB_QPS_SQD
&&
2279 attr_mask
& IB_QP_EN_SQD_ASYNC_NOTIFY
&& attr
->en_sqd_async_notify
)
2284 if (!ibqp
->uobject
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
2285 context
->sq_crq_size
|= cpu_to_be16(1 << 4);
2288 mlx5_cur
= to_mlx5_state(cur_state
);
2289 mlx5_new
= to_mlx5_state(new_state
);
2290 mlx5_st
= to_mlx5_st(ibqp
->qp_type
);
2294 /* If moving to a reset or error state, we must disable page faults on
2295 * this QP and flush all current page faults. Otherwise a stale page
2296 * fault may attempt to work on this QP after it is reset and moved
2297 * again to RTS, and may cause the driver and the device to get out of
2299 if (cur_state
!= IB_QPS_RESET
&& cur_state
!= IB_QPS_ERR
&&
2300 (new_state
== IB_QPS_RESET
|| new_state
== IB_QPS_ERR
) &&
2301 (qp
->ibqp
.qp_type
!= IB_QPT_RAW_PACKET
))
2302 mlx5_ib_qp_disable_pagefaults(qp
);
2304 if (mlx5_cur
>= MLX5_QP_NUM_STATE
|| mlx5_new
>= MLX5_QP_NUM_STATE
||
2305 !optab
[mlx5_cur
][mlx5_new
])
2308 op
= optab
[mlx5_cur
][mlx5_new
];
2309 optpar
= ib_mask_to_mlx5_opt(attr_mask
);
2310 optpar
&= opt_mask
[mlx5_cur
][mlx5_new
][mlx5_st
];
2311 in
->optparam
= cpu_to_be32(optpar
);
2313 if (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
)
2314 err
= modify_raw_packet_qp(dev
, qp
, op
);
2316 err
= mlx5_core_qp_modify(dev
->mdev
, op
, in
, sqd_event
,
2321 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
&&
2322 (qp
->ibqp
.qp_type
!= IB_QPT_RAW_PACKET
))
2323 mlx5_ib_qp_enable_pagefaults(qp
);
2325 qp
->state
= new_state
;
2327 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
2328 qp
->trans_qp
.atomic_rd_en
= attr
->qp_access_flags
;
2329 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
2330 qp
->trans_qp
.resp_depth
= attr
->max_dest_rd_atomic
;
2331 if (attr_mask
& IB_QP_PORT
)
2332 qp
->port
= attr
->port_num
;
2333 if (attr_mask
& IB_QP_ALT_PATH
)
2334 qp
->trans_qp
.alt_port
= attr
->alt_port_num
;
2337 * If we moved a kernel QP to RESET, clean up all old CQ
2338 * entries and reinitialize the QP.
2340 if (new_state
== IB_QPS_RESET
&& !ibqp
->uobject
) {
2341 mlx5_ib_cq_clean(recv_cq
, base
->mqp
.qpn
,
2342 ibqp
->srq
? to_msrq(ibqp
->srq
) : NULL
);
2343 if (send_cq
!= recv_cq
)
2344 mlx5_ib_cq_clean(send_cq
, base
->mqp
.qpn
, NULL
);
2350 qp
->sq
.cur_post
= 0;
2351 qp
->sq
.last_poll
= 0;
2352 qp
->db
.db
[MLX5_RCV_DBR
] = 0;
2353 qp
->db
.db
[MLX5_SND_DBR
] = 0;
2361 int mlx5_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
2362 int attr_mask
, struct ib_udata
*udata
)
2364 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
2365 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
2366 enum ib_qp_state cur_state
, new_state
;
2369 enum rdma_link_layer ll
= IB_LINK_LAYER_UNSPECIFIED
;
2371 mutex_lock(&qp
->mutex
);
2373 cur_state
= attr_mask
& IB_QP_CUR_STATE
? attr
->cur_qp_state
: qp
->state
;
2374 new_state
= attr_mask
& IB_QP_STATE
? attr
->qp_state
: cur_state
;
2376 if (!(cur_state
== new_state
&& cur_state
== IB_QPS_RESET
)) {
2377 port
= attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
;
2378 ll
= dev
->ib_dev
.get_link_layer(&dev
->ib_dev
, port
);
2381 if (ibqp
->qp_type
!= MLX5_IB_QPT_REG_UMR
&&
2382 !ib_modify_qp_is_ok(cur_state
, new_state
, ibqp
->qp_type
, attr_mask
,
2386 if ((attr_mask
& IB_QP_PORT
) &&
2387 (attr
->port_num
== 0 ||
2388 attr
->port_num
> MLX5_CAP_GEN(dev
->mdev
, num_ports
)))
2391 if (attr_mask
& IB_QP_PKEY_INDEX
) {
2392 port
= attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
;
2393 if (attr
->pkey_index
>=
2394 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
)
2398 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
2399 attr
->max_rd_atomic
>
2400 (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_ra_res_qp
)))
2403 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
2404 attr
->max_dest_rd_atomic
>
2405 (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_ra_req_qp
)))
2408 if (cur_state
== new_state
&& cur_state
== IB_QPS_RESET
) {
2413 err
= __mlx5_ib_modify_qp(ibqp
, attr
, attr_mask
, cur_state
, new_state
);
2416 mutex_unlock(&qp
->mutex
);
2420 static int mlx5_wq_overflow(struct mlx5_ib_wq
*wq
, int nreq
, struct ib_cq
*ib_cq
)
2422 struct mlx5_ib_cq
*cq
;
2425 cur
= wq
->head
- wq
->tail
;
2426 if (likely(cur
+ nreq
< wq
->max_post
))
2430 spin_lock(&cq
->lock
);
2431 cur
= wq
->head
- wq
->tail
;
2432 spin_unlock(&cq
->lock
);
2434 return cur
+ nreq
>= wq
->max_post
;
2437 static __always_inline
void set_raddr_seg(struct mlx5_wqe_raddr_seg
*rseg
,
2438 u64 remote_addr
, u32 rkey
)
2440 rseg
->raddr
= cpu_to_be64(remote_addr
);
2441 rseg
->rkey
= cpu_to_be32(rkey
);
2445 static void set_datagram_seg(struct mlx5_wqe_datagram_seg
*dseg
,
2446 struct ib_send_wr
*wr
)
2448 memcpy(&dseg
->av
, &to_mah(ud_wr(wr
)->ah
)->av
, sizeof(struct mlx5_av
));
2449 dseg
->av
.dqp_dct
= cpu_to_be32(ud_wr(wr
)->remote_qpn
| MLX5_EXTENDED_UD_AV
);
2450 dseg
->av
.key
.qkey
.qkey
= cpu_to_be32(ud_wr(wr
)->remote_qkey
);
2453 static void set_data_ptr_seg(struct mlx5_wqe_data_seg
*dseg
, struct ib_sge
*sg
)
2455 dseg
->byte_count
= cpu_to_be32(sg
->length
);
2456 dseg
->lkey
= cpu_to_be32(sg
->lkey
);
2457 dseg
->addr
= cpu_to_be64(sg
->addr
);
2460 static __be16
get_klm_octo(int npages
)
2462 return cpu_to_be16(ALIGN(npages
, 8) / 2);
2465 static __be64
frwr_mkey_mask(void)
2469 result
= MLX5_MKEY_MASK_LEN
|
2470 MLX5_MKEY_MASK_PAGE_SIZE
|
2471 MLX5_MKEY_MASK_START_ADDR
|
2472 MLX5_MKEY_MASK_EN_RINVAL
|
2473 MLX5_MKEY_MASK_KEY
|
2479 MLX5_MKEY_MASK_SMALL_FENCE
|
2480 MLX5_MKEY_MASK_FREE
;
2482 return cpu_to_be64(result
);
2485 static __be64
sig_mkey_mask(void)
2489 result
= MLX5_MKEY_MASK_LEN
|
2490 MLX5_MKEY_MASK_PAGE_SIZE
|
2491 MLX5_MKEY_MASK_START_ADDR
|
2492 MLX5_MKEY_MASK_EN_SIGERR
|
2493 MLX5_MKEY_MASK_EN_RINVAL
|
2494 MLX5_MKEY_MASK_KEY
|
2499 MLX5_MKEY_MASK_SMALL_FENCE
|
2500 MLX5_MKEY_MASK_FREE
|
2501 MLX5_MKEY_MASK_BSF_EN
;
2503 return cpu_to_be64(result
);
2506 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg
*umr
,
2507 struct mlx5_ib_mr
*mr
)
2509 int ndescs
= mr
->ndescs
;
2511 memset(umr
, 0, sizeof(*umr
));
2512 umr
->flags
= MLX5_UMR_CHECK_NOT_FREE
;
2513 umr
->klm_octowords
= get_klm_octo(ndescs
);
2514 umr
->mkey_mask
= frwr_mkey_mask();
2517 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg
*umr
)
2519 memset(umr
, 0, sizeof(*umr
));
2520 umr
->mkey_mask
= cpu_to_be64(MLX5_MKEY_MASK_FREE
);
2521 umr
->flags
= 1 << 7;
2524 static __be64
get_umr_reg_mr_mask(void)
2528 result
= MLX5_MKEY_MASK_LEN
|
2529 MLX5_MKEY_MASK_PAGE_SIZE
|
2530 MLX5_MKEY_MASK_START_ADDR
|
2534 MLX5_MKEY_MASK_KEY
|
2538 MLX5_MKEY_MASK_FREE
;
2540 return cpu_to_be64(result
);
2543 static __be64
get_umr_unreg_mr_mask(void)
2547 result
= MLX5_MKEY_MASK_FREE
;
2549 return cpu_to_be64(result
);
2552 static __be64
get_umr_update_mtt_mask(void)
2556 result
= MLX5_MKEY_MASK_FREE
;
2558 return cpu_to_be64(result
);
2561 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg
*umr
,
2562 struct ib_send_wr
*wr
)
2564 struct mlx5_umr_wr
*umrwr
= umr_wr(wr
);
2566 memset(umr
, 0, sizeof(*umr
));
2568 if (wr
->send_flags
& MLX5_IB_SEND_UMR_FAIL_IF_FREE
)
2569 umr
->flags
= MLX5_UMR_CHECK_FREE
; /* fail if free */
2571 umr
->flags
= MLX5_UMR_CHECK_NOT_FREE
; /* fail if not free */
2573 if (!(wr
->send_flags
& MLX5_IB_SEND_UMR_UNREG
)) {
2574 umr
->klm_octowords
= get_klm_octo(umrwr
->npages
);
2575 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_MTT
) {
2576 umr
->mkey_mask
= get_umr_update_mtt_mask();
2577 umr
->bsf_octowords
= get_klm_octo(umrwr
->target
.offset
);
2578 umr
->flags
|= MLX5_UMR_TRANSLATION_OFFSET_EN
;
2580 umr
->mkey_mask
= get_umr_reg_mr_mask();
2583 umr
->mkey_mask
= get_umr_unreg_mr_mask();
2587 umr
->flags
|= MLX5_UMR_INLINE
;
2590 static u8
get_umr_flags(int acc
)
2592 return (acc
& IB_ACCESS_REMOTE_ATOMIC
? MLX5_PERM_ATOMIC
: 0) |
2593 (acc
& IB_ACCESS_REMOTE_WRITE
? MLX5_PERM_REMOTE_WRITE
: 0) |
2594 (acc
& IB_ACCESS_REMOTE_READ
? MLX5_PERM_REMOTE_READ
: 0) |
2595 (acc
& IB_ACCESS_LOCAL_WRITE
? MLX5_PERM_LOCAL_WRITE
: 0) |
2596 MLX5_PERM_LOCAL_READ
| MLX5_PERM_UMR_EN
;
2599 static void set_reg_mkey_seg(struct mlx5_mkey_seg
*seg
,
2600 struct mlx5_ib_mr
*mr
,
2601 u32 key
, int access
)
2603 int ndescs
= ALIGN(mr
->ndescs
, 8) >> 1;
2605 memset(seg
, 0, sizeof(*seg
));
2606 seg
->flags
= get_umr_flags(access
) | MLX5_ACCESS_MODE_MTT
;
2607 seg
->qpn_mkey7_0
= cpu_to_be32((key
& 0xff) | 0xffffff00);
2608 seg
->flags_pd
= cpu_to_be32(MLX5_MKEY_REMOTE_INVAL
);
2609 seg
->start_addr
= cpu_to_be64(mr
->ibmr
.iova
);
2610 seg
->len
= cpu_to_be64(mr
->ibmr
.length
);
2611 seg
->xlt_oct_size
= cpu_to_be32(ndescs
);
2612 seg
->log2_page_size
= ilog2(mr
->ibmr
.page_size
);
2615 static void set_linv_mkey_seg(struct mlx5_mkey_seg
*seg
)
2617 memset(seg
, 0, sizeof(*seg
));
2618 seg
->status
= MLX5_MKEY_STATUS_FREE
;
2621 static void set_reg_mkey_segment(struct mlx5_mkey_seg
*seg
, struct ib_send_wr
*wr
)
2623 struct mlx5_umr_wr
*umrwr
= umr_wr(wr
);
2625 memset(seg
, 0, sizeof(*seg
));
2626 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UNREG
) {
2627 seg
->status
= MLX5_MKEY_STATUS_FREE
;
2631 seg
->flags
= convert_access(umrwr
->access_flags
);
2632 if (!(wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_MTT
)) {
2633 seg
->flags_pd
= cpu_to_be32(to_mpd(umrwr
->pd
)->pdn
);
2634 seg
->start_addr
= cpu_to_be64(umrwr
->target
.virt_addr
);
2636 seg
->len
= cpu_to_be64(umrwr
->length
);
2637 seg
->log2_page_size
= umrwr
->page_shift
;
2638 seg
->qpn_mkey7_0
= cpu_to_be32(0xffffff00 |
2639 mlx5_mkey_variant(umrwr
->mkey
));
2642 static void set_reg_data_seg(struct mlx5_wqe_data_seg
*dseg
,
2643 struct mlx5_ib_mr
*mr
,
2644 struct mlx5_ib_pd
*pd
)
2646 int bcount
= mr
->desc_size
* mr
->ndescs
;
2648 dseg
->addr
= cpu_to_be64(mr
->desc_map
);
2649 dseg
->byte_count
= cpu_to_be32(ALIGN(bcount
, 64));
2650 dseg
->lkey
= cpu_to_be32(pd
->ibpd
.local_dma_lkey
);
2653 static __be32
send_ieth(struct ib_send_wr
*wr
)
2655 switch (wr
->opcode
) {
2656 case IB_WR_SEND_WITH_IMM
:
2657 case IB_WR_RDMA_WRITE_WITH_IMM
:
2658 return wr
->ex
.imm_data
;
2660 case IB_WR_SEND_WITH_INV
:
2661 return cpu_to_be32(wr
->ex
.invalidate_rkey
);
2668 static u8
calc_sig(void *wqe
, int size
)
2674 for (i
= 0; i
< size
; i
++)
2680 static u8
wq_sig(void *wqe
)
2682 return calc_sig(wqe
, (*((u8
*)wqe
+ 8) & 0x3f) << 4);
2685 static int set_data_inl_seg(struct mlx5_ib_qp
*qp
, struct ib_send_wr
*wr
,
2688 struct mlx5_wqe_inline_seg
*seg
;
2689 void *qend
= qp
->sq
.qend
;
2697 wqe
+= sizeof(*seg
);
2698 for (i
= 0; i
< wr
->num_sge
; i
++) {
2699 addr
= (void *)(unsigned long)(wr
->sg_list
[i
].addr
);
2700 len
= wr
->sg_list
[i
].length
;
2703 if (unlikely(inl
> qp
->max_inline_data
))
2706 if (unlikely(wqe
+ len
> qend
)) {
2708 memcpy(wqe
, addr
, copy
);
2711 wqe
= mlx5_get_send_wqe(qp
, 0);
2713 memcpy(wqe
, addr
, len
);
2717 seg
->byte_count
= cpu_to_be32(inl
| MLX5_INLINE_SEG
);
2719 *sz
= ALIGN(inl
+ sizeof(seg
->byte_count
), 16) / 16;
2724 static u16
prot_field_size(enum ib_signature_type type
)
2727 case IB_SIG_TYPE_T10_DIF
:
2728 return MLX5_DIF_SIZE
;
2734 static u8
bs_selector(int block_size
)
2736 switch (block_size
) {
2737 case 512: return 0x1;
2738 case 520: return 0x2;
2739 case 4096: return 0x3;
2740 case 4160: return 0x4;
2741 case 1073741824: return 0x5;
2746 static void mlx5_fill_inl_bsf(struct ib_sig_domain
*domain
,
2747 struct mlx5_bsf_inl
*inl
)
2749 /* Valid inline section and allow BSF refresh */
2750 inl
->vld_refresh
= cpu_to_be16(MLX5_BSF_INL_VALID
|
2751 MLX5_BSF_REFRESH_DIF
);
2752 inl
->dif_apptag
= cpu_to_be16(domain
->sig
.dif
.app_tag
);
2753 inl
->dif_reftag
= cpu_to_be32(domain
->sig
.dif
.ref_tag
);
2754 /* repeating block */
2755 inl
->rp_inv_seed
= MLX5_BSF_REPEAT_BLOCK
;
2756 inl
->sig_type
= domain
->sig
.dif
.bg_type
== IB_T10DIF_CRC
?
2757 MLX5_DIF_CRC
: MLX5_DIF_IPCS
;
2759 if (domain
->sig
.dif
.ref_remap
)
2760 inl
->dif_inc_ref_guard_check
|= MLX5_BSF_INC_REFTAG
;
2762 if (domain
->sig
.dif
.app_escape
) {
2763 if (domain
->sig
.dif
.ref_escape
)
2764 inl
->dif_inc_ref_guard_check
|= MLX5_BSF_APPREF_ESCAPE
;
2766 inl
->dif_inc_ref_guard_check
|= MLX5_BSF_APPTAG_ESCAPE
;
2769 inl
->dif_app_bitmask_check
=
2770 cpu_to_be16(domain
->sig
.dif
.apptag_check_mask
);
2773 static int mlx5_set_bsf(struct ib_mr
*sig_mr
,
2774 struct ib_sig_attrs
*sig_attrs
,
2775 struct mlx5_bsf
*bsf
, u32 data_size
)
2777 struct mlx5_core_sig_ctx
*msig
= to_mmr(sig_mr
)->sig
;
2778 struct mlx5_bsf_basic
*basic
= &bsf
->basic
;
2779 struct ib_sig_domain
*mem
= &sig_attrs
->mem
;
2780 struct ib_sig_domain
*wire
= &sig_attrs
->wire
;
2782 memset(bsf
, 0, sizeof(*bsf
));
2784 /* Basic + Extended + Inline */
2785 basic
->bsf_size_sbs
= 1 << 7;
2786 /* Input domain check byte mask */
2787 basic
->check_byte_mask
= sig_attrs
->check_mask
;
2788 basic
->raw_data_size
= cpu_to_be32(data_size
);
2791 switch (sig_attrs
->mem
.sig_type
) {
2792 case IB_SIG_TYPE_NONE
:
2794 case IB_SIG_TYPE_T10_DIF
:
2795 basic
->mem
.bs_selector
= bs_selector(mem
->sig
.dif
.pi_interval
);
2796 basic
->m_bfs_psv
= cpu_to_be32(msig
->psv_memory
.psv_idx
);
2797 mlx5_fill_inl_bsf(mem
, &bsf
->m_inl
);
2804 switch (sig_attrs
->wire
.sig_type
) {
2805 case IB_SIG_TYPE_NONE
:
2807 case IB_SIG_TYPE_T10_DIF
:
2808 if (mem
->sig
.dif
.pi_interval
== wire
->sig
.dif
.pi_interval
&&
2809 mem
->sig_type
== wire
->sig_type
) {
2810 /* Same block structure */
2811 basic
->bsf_size_sbs
|= 1 << 4;
2812 if (mem
->sig
.dif
.bg_type
== wire
->sig
.dif
.bg_type
)
2813 basic
->wire
.copy_byte_mask
|= MLX5_CPY_GRD_MASK
;
2814 if (mem
->sig
.dif
.app_tag
== wire
->sig
.dif
.app_tag
)
2815 basic
->wire
.copy_byte_mask
|= MLX5_CPY_APP_MASK
;
2816 if (mem
->sig
.dif
.ref_tag
== wire
->sig
.dif
.ref_tag
)
2817 basic
->wire
.copy_byte_mask
|= MLX5_CPY_REF_MASK
;
2819 basic
->wire
.bs_selector
= bs_selector(wire
->sig
.dif
.pi_interval
);
2821 basic
->w_bfs_psv
= cpu_to_be32(msig
->psv_wire
.psv_idx
);
2822 mlx5_fill_inl_bsf(wire
, &bsf
->w_inl
);
2831 static int set_sig_data_segment(struct ib_sig_handover_wr
*wr
,
2832 struct mlx5_ib_qp
*qp
, void **seg
, int *size
)
2834 struct ib_sig_attrs
*sig_attrs
= wr
->sig_attrs
;
2835 struct ib_mr
*sig_mr
= wr
->sig_mr
;
2836 struct mlx5_bsf
*bsf
;
2837 u32 data_len
= wr
->wr
.sg_list
->length
;
2838 u32 data_key
= wr
->wr
.sg_list
->lkey
;
2839 u64 data_va
= wr
->wr
.sg_list
->addr
;
2844 (data_key
== wr
->prot
->lkey
&&
2845 data_va
== wr
->prot
->addr
&&
2846 data_len
== wr
->prot
->length
)) {
2848 * Source domain doesn't contain signature information
2849 * or data and protection are interleaved in memory.
2850 * So need construct:
2851 * ------------------
2853 * ------------------
2855 * ------------------
2857 struct mlx5_klm
*data_klm
= *seg
;
2859 data_klm
->bcount
= cpu_to_be32(data_len
);
2860 data_klm
->key
= cpu_to_be32(data_key
);
2861 data_klm
->va
= cpu_to_be64(data_va
);
2862 wqe_size
= ALIGN(sizeof(*data_klm
), 64);
2865 * Source domain contains signature information
2866 * So need construct a strided block format:
2867 * ---------------------------
2868 * | stride_block_ctrl |
2869 * ---------------------------
2871 * ---------------------------
2873 * ---------------------------
2875 * ---------------------------
2877 struct mlx5_stride_block_ctrl_seg
*sblock_ctrl
;
2878 struct mlx5_stride_block_entry
*data_sentry
;
2879 struct mlx5_stride_block_entry
*prot_sentry
;
2880 u32 prot_key
= wr
->prot
->lkey
;
2881 u64 prot_va
= wr
->prot
->addr
;
2882 u16 block_size
= sig_attrs
->mem
.sig
.dif
.pi_interval
;
2886 data_sentry
= (void *)sblock_ctrl
+ sizeof(*sblock_ctrl
);
2887 prot_sentry
= (void *)data_sentry
+ sizeof(*data_sentry
);
2889 prot_size
= prot_field_size(sig_attrs
->mem
.sig_type
);
2891 pr_err("Bad block size given: %u\n", block_size
);
2894 sblock_ctrl
->bcount_per_cycle
= cpu_to_be32(block_size
+
2896 sblock_ctrl
->op
= cpu_to_be32(MLX5_STRIDE_BLOCK_OP
);
2897 sblock_ctrl
->repeat_count
= cpu_to_be32(data_len
/ block_size
);
2898 sblock_ctrl
->num_entries
= cpu_to_be16(2);
2900 data_sentry
->bcount
= cpu_to_be16(block_size
);
2901 data_sentry
->key
= cpu_to_be32(data_key
);
2902 data_sentry
->va
= cpu_to_be64(data_va
);
2903 data_sentry
->stride
= cpu_to_be16(block_size
);
2905 prot_sentry
->bcount
= cpu_to_be16(prot_size
);
2906 prot_sentry
->key
= cpu_to_be32(prot_key
);
2907 prot_sentry
->va
= cpu_to_be64(prot_va
);
2908 prot_sentry
->stride
= cpu_to_be16(prot_size
);
2910 wqe_size
= ALIGN(sizeof(*sblock_ctrl
) + sizeof(*data_sentry
) +
2911 sizeof(*prot_sentry
), 64);
2915 *size
+= wqe_size
/ 16;
2916 if (unlikely((*seg
== qp
->sq
.qend
)))
2917 *seg
= mlx5_get_send_wqe(qp
, 0);
2920 ret
= mlx5_set_bsf(sig_mr
, sig_attrs
, bsf
, data_len
);
2924 *seg
+= sizeof(*bsf
);
2925 *size
+= sizeof(*bsf
) / 16;
2926 if (unlikely((*seg
== qp
->sq
.qend
)))
2927 *seg
= mlx5_get_send_wqe(qp
, 0);
2932 static void set_sig_mkey_segment(struct mlx5_mkey_seg
*seg
,
2933 struct ib_sig_handover_wr
*wr
, u32 nelements
,
2934 u32 length
, u32 pdn
)
2936 struct ib_mr
*sig_mr
= wr
->sig_mr
;
2937 u32 sig_key
= sig_mr
->rkey
;
2938 u8 sigerr
= to_mmr(sig_mr
)->sig
->sigerr_count
& 1;
2940 memset(seg
, 0, sizeof(*seg
));
2942 seg
->flags
= get_umr_flags(wr
->access_flags
) |
2943 MLX5_ACCESS_MODE_KLM
;
2944 seg
->qpn_mkey7_0
= cpu_to_be32((sig_key
& 0xff) | 0xffffff00);
2945 seg
->flags_pd
= cpu_to_be32(MLX5_MKEY_REMOTE_INVAL
| sigerr
<< 26 |
2946 MLX5_MKEY_BSF_EN
| pdn
);
2947 seg
->len
= cpu_to_be64(length
);
2948 seg
->xlt_oct_size
= cpu_to_be32(be16_to_cpu(get_klm_octo(nelements
)));
2949 seg
->bsfs_octo_size
= cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE
);
2952 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg
*umr
,
2955 memset(umr
, 0, sizeof(*umr
));
2957 umr
->flags
= MLX5_FLAGS_INLINE
| MLX5_FLAGS_CHECK_FREE
;
2958 umr
->klm_octowords
= get_klm_octo(nelements
);
2959 umr
->bsf_octowords
= cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE
);
2960 umr
->mkey_mask
= sig_mkey_mask();
2964 static int set_sig_umr_wr(struct ib_send_wr
*send_wr
, struct mlx5_ib_qp
*qp
,
2965 void **seg
, int *size
)
2967 struct ib_sig_handover_wr
*wr
= sig_handover_wr(send_wr
);
2968 struct mlx5_ib_mr
*sig_mr
= to_mmr(wr
->sig_mr
);
2969 u32 pdn
= get_pd(qp
)->pdn
;
2971 int region_len
, ret
;
2973 if (unlikely(wr
->wr
.num_sge
!= 1) ||
2974 unlikely(wr
->access_flags
& IB_ACCESS_REMOTE_ATOMIC
) ||
2975 unlikely(!sig_mr
->sig
) || unlikely(!qp
->signature_en
) ||
2976 unlikely(!sig_mr
->sig
->sig_status_checked
))
2979 /* length of the protected region, data + protection */
2980 region_len
= wr
->wr
.sg_list
->length
;
2982 (wr
->prot
->lkey
!= wr
->wr
.sg_list
->lkey
||
2983 wr
->prot
->addr
!= wr
->wr
.sg_list
->addr
||
2984 wr
->prot
->length
!= wr
->wr
.sg_list
->length
))
2985 region_len
+= wr
->prot
->length
;
2988 * KLM octoword size - if protection was provided
2989 * then we use strided block format (3 octowords),
2990 * else we use single KLM (1 octoword)
2992 klm_oct_size
= wr
->prot
? 3 : 1;
2994 set_sig_umr_segment(*seg
, klm_oct_size
);
2995 *seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
2996 *size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
2997 if (unlikely((*seg
== qp
->sq
.qend
)))
2998 *seg
= mlx5_get_send_wqe(qp
, 0);
3000 set_sig_mkey_segment(*seg
, wr
, klm_oct_size
, region_len
, pdn
);
3001 *seg
+= sizeof(struct mlx5_mkey_seg
);
3002 *size
+= sizeof(struct mlx5_mkey_seg
) / 16;
3003 if (unlikely((*seg
== qp
->sq
.qend
)))
3004 *seg
= mlx5_get_send_wqe(qp
, 0);
3006 ret
= set_sig_data_segment(wr
, qp
, seg
, size
);
3010 sig_mr
->sig
->sig_status_checked
= false;
3014 static int set_psv_wr(struct ib_sig_domain
*domain
,
3015 u32 psv_idx
, void **seg
, int *size
)
3017 struct mlx5_seg_set_psv
*psv_seg
= *seg
;
3019 memset(psv_seg
, 0, sizeof(*psv_seg
));
3020 psv_seg
->psv_num
= cpu_to_be32(psv_idx
);
3021 switch (domain
->sig_type
) {
3022 case IB_SIG_TYPE_NONE
:
3024 case IB_SIG_TYPE_T10_DIF
:
3025 psv_seg
->transient_sig
= cpu_to_be32(domain
->sig
.dif
.bg
<< 16 |
3026 domain
->sig
.dif
.app_tag
);
3027 psv_seg
->ref_tag
= cpu_to_be32(domain
->sig
.dif
.ref_tag
);
3030 pr_err("Bad signature type given.\n");
3034 *seg
+= sizeof(*psv_seg
);
3035 *size
+= sizeof(*psv_seg
) / 16;
3040 static int set_reg_wr(struct mlx5_ib_qp
*qp
,
3041 struct ib_reg_wr
*wr
,
3042 void **seg
, int *size
)
3044 struct mlx5_ib_mr
*mr
= to_mmr(wr
->mr
);
3045 struct mlx5_ib_pd
*pd
= to_mpd(qp
->ibqp
.pd
);
3047 if (unlikely(wr
->wr
.send_flags
& IB_SEND_INLINE
)) {
3048 mlx5_ib_warn(to_mdev(qp
->ibqp
.device
),
3049 "Invalid IB_SEND_INLINE send flag\n");
3053 set_reg_umr_seg(*seg
, mr
);
3054 *seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
3055 *size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
3056 if (unlikely((*seg
== qp
->sq
.qend
)))
3057 *seg
= mlx5_get_send_wqe(qp
, 0);
3059 set_reg_mkey_seg(*seg
, mr
, wr
->key
, wr
->access
);
3060 *seg
+= sizeof(struct mlx5_mkey_seg
);
3061 *size
+= sizeof(struct mlx5_mkey_seg
) / 16;
3062 if (unlikely((*seg
== qp
->sq
.qend
)))
3063 *seg
= mlx5_get_send_wqe(qp
, 0);
3065 set_reg_data_seg(*seg
, mr
, pd
);
3066 *seg
+= sizeof(struct mlx5_wqe_data_seg
);
3067 *size
+= (sizeof(struct mlx5_wqe_data_seg
) / 16);
3072 static void set_linv_wr(struct mlx5_ib_qp
*qp
, void **seg
, int *size
)
3074 set_linv_umr_seg(*seg
);
3075 *seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
3076 *size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
3077 if (unlikely((*seg
== qp
->sq
.qend
)))
3078 *seg
= mlx5_get_send_wqe(qp
, 0);
3079 set_linv_mkey_seg(*seg
);
3080 *seg
+= sizeof(struct mlx5_mkey_seg
);
3081 *size
+= sizeof(struct mlx5_mkey_seg
) / 16;
3082 if (unlikely((*seg
== qp
->sq
.qend
)))
3083 *seg
= mlx5_get_send_wqe(qp
, 0);
3086 static void dump_wqe(struct mlx5_ib_qp
*qp
, int idx
, int size_16
)
3092 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp
, tidx
));
3093 for (i
= 0, j
= 0; i
< size_16
* 4; i
+= 4, j
+= 4) {
3094 if ((i
& 0xf) == 0) {
3095 void *buf
= mlx5_get_send_wqe(qp
, tidx
);
3096 tidx
= (tidx
+ 1) & (qp
->sq
.wqe_cnt
- 1);
3100 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p
[j
]),
3101 be32_to_cpu(p
[j
+ 1]), be32_to_cpu(p
[j
+ 2]),
3102 be32_to_cpu(p
[j
+ 3]));
3106 static void mlx5_bf_copy(u64 __iomem
*dst
, u64
*src
,
3107 unsigned bytecnt
, struct mlx5_ib_qp
*qp
)
3109 while (bytecnt
> 0) {
3110 __iowrite64_copy(dst
++, src
++, 8);
3111 __iowrite64_copy(dst
++, src
++, 8);
3112 __iowrite64_copy(dst
++, src
++, 8);
3113 __iowrite64_copy(dst
++, src
++, 8);
3114 __iowrite64_copy(dst
++, src
++, 8);
3115 __iowrite64_copy(dst
++, src
++, 8);
3116 __iowrite64_copy(dst
++, src
++, 8);
3117 __iowrite64_copy(dst
++, src
++, 8);
3119 if (unlikely(src
== qp
->sq
.qend
))
3120 src
= mlx5_get_send_wqe(qp
, 0);
3124 static u8
get_fence(u8 fence
, struct ib_send_wr
*wr
)
3126 if (unlikely(wr
->opcode
== IB_WR_LOCAL_INV
&&
3127 wr
->send_flags
& IB_SEND_FENCE
))
3128 return MLX5_FENCE_MODE_STRONG_ORDERING
;
3130 if (unlikely(fence
)) {
3131 if (wr
->send_flags
& IB_SEND_FENCE
)
3132 return MLX5_FENCE_MODE_SMALL_AND_FENCE
;
3141 static int begin_wqe(struct mlx5_ib_qp
*qp
, void **seg
,
3142 struct mlx5_wqe_ctrl_seg
**ctrl
,
3143 struct ib_send_wr
*wr
, unsigned *idx
,
3144 int *size
, int nreq
)
3148 if (unlikely(mlx5_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
))) {
3153 *idx
= qp
->sq
.cur_post
& (qp
->sq
.wqe_cnt
- 1);
3154 *seg
= mlx5_get_send_wqe(qp
, *idx
);
3156 *(uint32_t *)(*seg
+ 8) = 0;
3157 (*ctrl
)->imm
= send_ieth(wr
);
3158 (*ctrl
)->fm_ce_se
= qp
->sq_signal_bits
|
3159 (wr
->send_flags
& IB_SEND_SIGNALED
?
3160 MLX5_WQE_CTRL_CQ_UPDATE
: 0) |
3161 (wr
->send_flags
& IB_SEND_SOLICITED
?
3162 MLX5_WQE_CTRL_SOLICITED
: 0);
3164 *seg
+= sizeof(**ctrl
);
3165 *size
= sizeof(**ctrl
) / 16;
3170 static void finish_wqe(struct mlx5_ib_qp
*qp
,
3171 struct mlx5_wqe_ctrl_seg
*ctrl
,
3172 u8 size
, unsigned idx
, u64 wr_id
,
3173 int nreq
, u8 fence
, u8 next_fence
,
3178 ctrl
->opmod_idx_opcode
= cpu_to_be32(((u32
)(qp
->sq
.cur_post
) << 8) |
3179 mlx5_opcode
| ((u32
)opmod
<< 24));
3180 ctrl
->qpn_ds
= cpu_to_be32(size
| (qp
->trans_qp
.base
.mqp
.qpn
<< 8));
3181 ctrl
->fm_ce_se
|= fence
;
3182 qp
->fm_cache
= next_fence
;
3183 if (unlikely(qp
->wq_sig
))
3184 ctrl
->signature
= wq_sig(ctrl
);
3186 qp
->sq
.wrid
[idx
] = wr_id
;
3187 qp
->sq
.w_list
[idx
].opcode
= mlx5_opcode
;
3188 qp
->sq
.wqe_head
[idx
] = qp
->sq
.head
+ nreq
;
3189 qp
->sq
.cur_post
+= DIV_ROUND_UP(size
* 16, MLX5_SEND_WQE_BB
);
3190 qp
->sq
.w_list
[idx
].next
= qp
->sq
.cur_post
;
3194 int mlx5_ib_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
3195 struct ib_send_wr
**bad_wr
)
3197 struct mlx5_wqe_ctrl_seg
*ctrl
= NULL
; /* compiler warning */
3198 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
3199 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
3200 struct mlx5_ib_mr
*mr
;
3201 struct mlx5_wqe_data_seg
*dpseg
;
3202 struct mlx5_wqe_xrc_seg
*xrc
;
3203 struct mlx5_bf
*bf
= qp
->bf
;
3204 int uninitialized_var(size
);
3205 void *qend
= qp
->sq
.qend
;
3206 unsigned long flags
;
3217 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
3219 for (nreq
= 0; wr
; nreq
++, wr
= wr
->next
) {
3220 if (unlikely(wr
->opcode
>= ARRAY_SIZE(mlx5_ib_opcode
))) {
3221 mlx5_ib_warn(dev
, "\n");
3227 fence
= qp
->fm_cache
;
3228 num_sge
= wr
->num_sge
;
3229 if (unlikely(num_sge
> qp
->sq
.max_gs
)) {
3230 mlx5_ib_warn(dev
, "\n");
3236 err
= begin_wqe(qp
, &seg
, &ctrl
, wr
, &idx
, &size
, nreq
);
3238 mlx5_ib_warn(dev
, "\n");
3244 switch (ibqp
->qp_type
) {
3245 case IB_QPT_XRC_INI
:
3247 seg
+= sizeof(*xrc
);
3248 size
+= sizeof(*xrc
) / 16;
3251 switch (wr
->opcode
) {
3252 case IB_WR_RDMA_READ
:
3253 case IB_WR_RDMA_WRITE
:
3254 case IB_WR_RDMA_WRITE_WITH_IMM
:
3255 set_raddr_seg(seg
, rdma_wr(wr
)->remote_addr
,
3257 seg
+= sizeof(struct mlx5_wqe_raddr_seg
);
3258 size
+= sizeof(struct mlx5_wqe_raddr_seg
) / 16;
3261 case IB_WR_ATOMIC_CMP_AND_SWP
:
3262 case IB_WR_ATOMIC_FETCH_AND_ADD
:
3263 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP
:
3264 mlx5_ib_warn(dev
, "Atomic operations are not supported yet\n");
3269 case IB_WR_LOCAL_INV
:
3270 next_fence
= MLX5_FENCE_MODE_INITIATOR_SMALL
;
3271 qp
->sq
.wr_data
[idx
] = IB_WR_LOCAL_INV
;
3272 ctrl
->imm
= cpu_to_be32(wr
->ex
.invalidate_rkey
);
3273 set_linv_wr(qp
, &seg
, &size
);
3278 next_fence
= MLX5_FENCE_MODE_INITIATOR_SMALL
;
3279 qp
->sq
.wr_data
[idx
] = IB_WR_REG_MR
;
3280 ctrl
->imm
= cpu_to_be32(reg_wr(wr
)->key
);
3281 err
= set_reg_wr(qp
, reg_wr(wr
), &seg
, &size
);
3289 case IB_WR_REG_SIG_MR
:
3290 qp
->sq
.wr_data
[idx
] = IB_WR_REG_SIG_MR
;
3291 mr
= to_mmr(sig_handover_wr(wr
)->sig_mr
);
3293 ctrl
->imm
= cpu_to_be32(mr
->ibmr
.rkey
);
3294 err
= set_sig_umr_wr(wr
, qp
, &seg
, &size
);
3296 mlx5_ib_warn(dev
, "\n");
3301 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
,
3302 nreq
, get_fence(fence
, wr
),
3303 next_fence
, MLX5_OPCODE_UMR
);
3305 * SET_PSV WQEs are not signaled and solicited
3308 wr
->send_flags
&= ~IB_SEND_SIGNALED
;
3309 wr
->send_flags
|= IB_SEND_SOLICITED
;
3310 err
= begin_wqe(qp
, &seg
, &ctrl
, wr
,
3313 mlx5_ib_warn(dev
, "\n");
3319 err
= set_psv_wr(&sig_handover_wr(wr
)->sig_attrs
->mem
,
3320 mr
->sig
->psv_memory
.psv_idx
, &seg
,
3323 mlx5_ib_warn(dev
, "\n");
3328 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
,
3329 nreq
, get_fence(fence
, wr
),
3330 next_fence
, MLX5_OPCODE_SET_PSV
);
3331 err
= begin_wqe(qp
, &seg
, &ctrl
, wr
,
3334 mlx5_ib_warn(dev
, "\n");
3340 next_fence
= MLX5_FENCE_MODE_INITIATOR_SMALL
;
3341 err
= set_psv_wr(&sig_handover_wr(wr
)->sig_attrs
->wire
,
3342 mr
->sig
->psv_wire
.psv_idx
, &seg
,
3345 mlx5_ib_warn(dev
, "\n");
3350 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
,
3351 nreq
, get_fence(fence
, wr
),
3352 next_fence
, MLX5_OPCODE_SET_PSV
);
3362 switch (wr
->opcode
) {
3363 case IB_WR_RDMA_WRITE
:
3364 case IB_WR_RDMA_WRITE_WITH_IMM
:
3365 set_raddr_seg(seg
, rdma_wr(wr
)->remote_addr
,
3367 seg
+= sizeof(struct mlx5_wqe_raddr_seg
);
3368 size
+= sizeof(struct mlx5_wqe_raddr_seg
) / 16;
3379 set_datagram_seg(seg
, wr
);
3380 seg
+= sizeof(struct mlx5_wqe_datagram_seg
);
3381 size
+= sizeof(struct mlx5_wqe_datagram_seg
) / 16;
3382 if (unlikely((seg
== qend
)))
3383 seg
= mlx5_get_send_wqe(qp
, 0);
3386 case MLX5_IB_QPT_REG_UMR
:
3387 if (wr
->opcode
!= MLX5_IB_WR_UMR
) {
3389 mlx5_ib_warn(dev
, "bad opcode\n");
3392 qp
->sq
.wr_data
[idx
] = MLX5_IB_WR_UMR
;
3393 ctrl
->imm
= cpu_to_be32(umr_wr(wr
)->mkey
);
3394 set_reg_umr_segment(seg
, wr
);
3395 seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
3396 size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
3397 if (unlikely((seg
== qend
)))
3398 seg
= mlx5_get_send_wqe(qp
, 0);
3399 set_reg_mkey_segment(seg
, wr
);
3400 seg
+= sizeof(struct mlx5_mkey_seg
);
3401 size
+= sizeof(struct mlx5_mkey_seg
) / 16;
3402 if (unlikely((seg
== qend
)))
3403 seg
= mlx5_get_send_wqe(qp
, 0);
3410 if (wr
->send_flags
& IB_SEND_INLINE
&& num_sge
) {
3411 int uninitialized_var(sz
);
3413 err
= set_data_inl_seg(qp
, wr
, seg
, &sz
);
3414 if (unlikely(err
)) {
3415 mlx5_ib_warn(dev
, "\n");
3423 for (i
= 0; i
< num_sge
; i
++) {
3424 if (unlikely(dpseg
== qend
)) {
3425 seg
= mlx5_get_send_wqe(qp
, 0);
3428 if (likely(wr
->sg_list
[i
].length
)) {
3429 set_data_ptr_seg(dpseg
, wr
->sg_list
+ i
);
3430 size
+= sizeof(struct mlx5_wqe_data_seg
) / 16;
3436 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
, nreq
,
3437 get_fence(fence
, wr
), next_fence
,
3438 mlx5_ib_opcode
[wr
->opcode
]);
3441 dump_wqe(qp
, idx
, size
);
3446 qp
->sq
.head
+= nreq
;
3448 /* Make sure that descriptors are written before
3449 * updating doorbell record and ringing the doorbell
3453 qp
->db
.db
[MLX5_SND_DBR
] = cpu_to_be32(qp
->sq
.cur_post
);
3455 /* Make sure doorbell record is visible to the HCA before
3456 * we hit doorbell */
3460 spin_lock(&bf
->lock
);
3462 __acquire(&bf
->lock
);
3465 if (0 && nreq
== 1 && bf
->uuarn
&& inl
&& size
> 1 && size
<= bf
->buf_size
/ 16) {
3466 mlx5_bf_copy(bf
->reg
+ bf
->offset
, (u64
*)ctrl
, ALIGN(size
* 16, 64), qp
);
3469 mlx5_write64((__be32
*)ctrl
, bf
->regreg
+ bf
->offset
,
3470 MLX5_GET_DOORBELL_LOCK(&bf
->lock32
));
3471 /* Make sure doorbells don't leak out of SQ spinlock
3472 * and reach the HCA out of order.
3476 bf
->offset
^= bf
->buf_size
;
3478 spin_unlock(&bf
->lock
);
3480 __release(&bf
->lock
);
3483 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
3488 static void set_sig_seg(struct mlx5_rwqe_sig
*sig
, int size
)
3490 sig
->signature
= calc_sig(sig
, size
);
3493 int mlx5_ib_post_recv(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
3494 struct ib_recv_wr
**bad_wr
)
3496 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
3497 struct mlx5_wqe_data_seg
*scat
;
3498 struct mlx5_rwqe_sig
*sig
;
3499 unsigned long flags
;
3505 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
3507 ind
= qp
->rq
.head
& (qp
->rq
.wqe_cnt
- 1);
3509 for (nreq
= 0; wr
; nreq
++, wr
= wr
->next
) {
3510 if (mlx5_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
3516 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
3522 scat
= get_recv_wqe(qp
, ind
);
3526 for (i
= 0; i
< wr
->num_sge
; i
++)
3527 set_data_ptr_seg(scat
+ i
, wr
->sg_list
+ i
);
3529 if (i
< qp
->rq
.max_gs
) {
3530 scat
[i
].byte_count
= 0;
3531 scat
[i
].lkey
= cpu_to_be32(MLX5_INVALID_LKEY
);
3536 sig
= (struct mlx5_rwqe_sig
*)scat
;
3537 set_sig_seg(sig
, (qp
->rq
.max_gs
+ 1) << 2);
3540 qp
->rq
.wrid
[ind
] = wr
->wr_id
;
3542 ind
= (ind
+ 1) & (qp
->rq
.wqe_cnt
- 1);
3547 qp
->rq
.head
+= nreq
;
3549 /* Make sure that descriptors are written before
3554 *qp
->db
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
3557 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
3562 static inline enum ib_qp_state
to_ib_qp_state(enum mlx5_qp_state mlx5_state
)
3564 switch (mlx5_state
) {
3565 case MLX5_QP_STATE_RST
: return IB_QPS_RESET
;
3566 case MLX5_QP_STATE_INIT
: return IB_QPS_INIT
;
3567 case MLX5_QP_STATE_RTR
: return IB_QPS_RTR
;
3568 case MLX5_QP_STATE_RTS
: return IB_QPS_RTS
;
3569 case MLX5_QP_STATE_SQ_DRAINING
:
3570 case MLX5_QP_STATE_SQD
: return IB_QPS_SQD
;
3571 case MLX5_QP_STATE_SQER
: return IB_QPS_SQE
;
3572 case MLX5_QP_STATE_ERR
: return IB_QPS_ERR
;
3577 static inline enum ib_mig_state
to_ib_mig_state(int mlx5_mig_state
)
3579 switch (mlx5_mig_state
) {
3580 case MLX5_QP_PM_ARMED
: return IB_MIG_ARMED
;
3581 case MLX5_QP_PM_REARM
: return IB_MIG_REARM
;
3582 case MLX5_QP_PM_MIGRATED
: return IB_MIG_MIGRATED
;
3587 static int to_ib_qp_access_flags(int mlx5_flags
)
3591 if (mlx5_flags
& MLX5_QP_BIT_RRE
)
3592 ib_flags
|= IB_ACCESS_REMOTE_READ
;
3593 if (mlx5_flags
& MLX5_QP_BIT_RWE
)
3594 ib_flags
|= IB_ACCESS_REMOTE_WRITE
;
3595 if (mlx5_flags
& MLX5_QP_BIT_RAE
)
3596 ib_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
3601 static void to_ib_ah_attr(struct mlx5_ib_dev
*ibdev
, struct ib_ah_attr
*ib_ah_attr
,
3602 struct mlx5_qp_path
*path
)
3604 struct mlx5_core_dev
*dev
= ibdev
->mdev
;
3606 memset(ib_ah_attr
, 0, sizeof(*ib_ah_attr
));
3607 ib_ah_attr
->port_num
= path
->port
;
3609 if (ib_ah_attr
->port_num
== 0 ||
3610 ib_ah_attr
->port_num
> MLX5_CAP_GEN(dev
, num_ports
))
3613 ib_ah_attr
->sl
= path
->dci_cfi_prio_sl
& 0xf;
3615 ib_ah_attr
->dlid
= be16_to_cpu(path
->rlid
);
3616 ib_ah_attr
->src_path_bits
= path
->grh_mlid
& 0x7f;
3617 ib_ah_attr
->static_rate
= path
->static_rate
? path
->static_rate
- 5 : 0;
3618 ib_ah_attr
->ah_flags
= (path
->grh_mlid
& (1 << 7)) ? IB_AH_GRH
: 0;
3619 if (ib_ah_attr
->ah_flags
) {
3620 ib_ah_attr
->grh
.sgid_index
= path
->mgid_index
;
3621 ib_ah_attr
->grh
.hop_limit
= path
->hop_limit
;
3622 ib_ah_attr
->grh
.traffic_class
=
3623 (be32_to_cpu(path
->tclass_flowlabel
) >> 20) & 0xff;
3624 ib_ah_attr
->grh
.flow_label
=
3625 be32_to_cpu(path
->tclass_flowlabel
) & 0xfffff;
3626 memcpy(ib_ah_attr
->grh
.dgid
.raw
,
3627 path
->rgid
, sizeof(ib_ah_attr
->grh
.dgid
.raw
));
3631 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev
*dev
,
3632 struct mlx5_ib_sq
*sq
,
3640 inlen
= MLX5_ST_SZ_BYTES(query_sq_out
);
3641 out
= mlx5_vzalloc(inlen
);
3645 err
= mlx5_core_query_sq(dev
->mdev
, sq
->base
.mqp
.qpn
, out
);
3649 sqc
= MLX5_ADDR_OF(query_sq_out
, out
, sq_context
);
3650 *sq_state
= MLX5_GET(sqc
, sqc
, state
);
3651 sq
->state
= *sq_state
;
3658 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev
*dev
,
3659 struct mlx5_ib_rq
*rq
,
3667 inlen
= MLX5_ST_SZ_BYTES(query_rq_out
);
3668 out
= mlx5_vzalloc(inlen
);
3672 err
= mlx5_core_query_rq(dev
->mdev
, rq
->base
.mqp
.qpn
, out
);
3676 rqc
= MLX5_ADDR_OF(query_rq_out
, out
, rq_context
);
3677 *rq_state
= MLX5_GET(rqc
, rqc
, state
);
3678 rq
->state
= *rq_state
;
3685 static int sqrq_state_to_qp_state(u8 sq_state
, u8 rq_state
,
3686 struct mlx5_ib_qp
*qp
, u8
*qp_state
)
3688 static const u8 sqrq_trans
[MLX5_RQ_NUM_STATE
][MLX5_SQ_NUM_STATE
] = {
3689 [MLX5_RQC_STATE_RST
] = {
3690 [MLX5_SQC_STATE_RST
] = IB_QPS_RESET
,
3691 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE_BAD
,
3692 [MLX5_SQC_STATE_ERR
] = MLX5_QP_STATE_BAD
,
3693 [MLX5_SQ_STATE_NA
] = IB_QPS_RESET
,
3695 [MLX5_RQC_STATE_RDY
] = {
3696 [MLX5_SQC_STATE_RST
] = MLX5_QP_STATE_BAD
,
3697 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE
,
3698 [MLX5_SQC_STATE_ERR
] = IB_QPS_SQE
,
3699 [MLX5_SQ_STATE_NA
] = MLX5_QP_STATE
,
3701 [MLX5_RQC_STATE_ERR
] = {
3702 [MLX5_SQC_STATE_RST
] = MLX5_QP_STATE_BAD
,
3703 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE_BAD
,
3704 [MLX5_SQC_STATE_ERR
] = IB_QPS_ERR
,
3705 [MLX5_SQ_STATE_NA
] = IB_QPS_ERR
,
3707 [MLX5_RQ_STATE_NA
] = {
3708 [MLX5_SQC_STATE_RST
] = IB_QPS_RESET
,
3709 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE
,
3710 [MLX5_SQC_STATE_ERR
] = MLX5_QP_STATE
,
3711 [MLX5_SQ_STATE_NA
] = MLX5_QP_STATE_BAD
,
3715 *qp_state
= sqrq_trans
[rq_state
][sq_state
];
3717 if (*qp_state
== MLX5_QP_STATE_BAD
) {
3718 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
3719 qp
->raw_packet_qp
.sq
.base
.mqp
.qpn
, sq_state
,
3720 qp
->raw_packet_qp
.rq
.base
.mqp
.qpn
, rq_state
);
3724 if (*qp_state
== MLX5_QP_STATE
)
3725 *qp_state
= qp
->state
;
3730 static int query_raw_packet_qp_state(struct mlx5_ib_dev
*dev
,
3731 struct mlx5_ib_qp
*qp
,
3732 u8
*raw_packet_qp_state
)
3734 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
3735 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
3736 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
3738 u8 sq_state
= MLX5_SQ_STATE_NA
;
3739 u8 rq_state
= MLX5_RQ_STATE_NA
;
3741 if (qp
->sq
.wqe_cnt
) {
3742 err
= query_raw_packet_qp_sq_state(dev
, sq
, &sq_state
);
3747 if (qp
->rq
.wqe_cnt
) {
3748 err
= query_raw_packet_qp_rq_state(dev
, rq
, &rq_state
);
3753 return sqrq_state_to_qp_state(sq_state
, rq_state
, qp
,
3754 raw_packet_qp_state
);
3757 static int query_qp_attr(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
3758 struct ib_qp_attr
*qp_attr
)
3760 struct mlx5_query_qp_mbox_out
*outb
;
3761 struct mlx5_qp_context
*context
;
3765 outb
= kzalloc(sizeof(*outb
), GFP_KERNEL
);
3769 context
= &outb
->ctx
;
3770 err
= mlx5_core_qp_query(dev
->mdev
, &qp
->trans_qp
.base
.mqp
, outb
,
3775 mlx5_state
= be32_to_cpu(context
->flags
) >> 28;
3777 qp
->state
= to_ib_qp_state(mlx5_state
);
3778 qp_attr
->path_mtu
= context
->mtu_msgmax
>> 5;
3779 qp_attr
->path_mig_state
=
3780 to_ib_mig_state((be32_to_cpu(context
->flags
) >> 11) & 0x3);
3781 qp_attr
->qkey
= be32_to_cpu(context
->qkey
);
3782 qp_attr
->rq_psn
= be32_to_cpu(context
->rnr_nextrecvpsn
) & 0xffffff;
3783 qp_attr
->sq_psn
= be32_to_cpu(context
->next_send_psn
) & 0xffffff;
3784 qp_attr
->dest_qp_num
= be32_to_cpu(context
->log_pg_sz_remote_qpn
) & 0xffffff;
3785 qp_attr
->qp_access_flags
=
3786 to_ib_qp_access_flags(be32_to_cpu(context
->params2
));
3788 if (qp
->ibqp
.qp_type
== IB_QPT_RC
|| qp
->ibqp
.qp_type
== IB_QPT_UC
) {
3789 to_ib_ah_attr(dev
, &qp_attr
->ah_attr
, &context
->pri_path
);
3790 to_ib_ah_attr(dev
, &qp_attr
->alt_ah_attr
, &context
->alt_path
);
3791 qp_attr
->alt_pkey_index
= context
->alt_path
.pkey_index
& 0x7f;
3792 qp_attr
->alt_port_num
= qp_attr
->alt_ah_attr
.port_num
;
3795 qp_attr
->pkey_index
= context
->pri_path
.pkey_index
& 0x7f;
3796 qp_attr
->port_num
= context
->pri_path
.port
;
3798 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3799 qp_attr
->sq_draining
= mlx5_state
== MLX5_QP_STATE_SQ_DRAINING
;
3801 qp_attr
->max_rd_atomic
= 1 << ((be32_to_cpu(context
->params1
) >> 21) & 0x7);
3803 qp_attr
->max_dest_rd_atomic
=
3804 1 << ((be32_to_cpu(context
->params2
) >> 21) & 0x7);
3805 qp_attr
->min_rnr_timer
=
3806 (be32_to_cpu(context
->rnr_nextrecvpsn
) >> 24) & 0x1f;
3807 qp_attr
->timeout
= context
->pri_path
.ackto_lt
>> 3;
3808 qp_attr
->retry_cnt
= (be32_to_cpu(context
->params1
) >> 16) & 0x7;
3809 qp_attr
->rnr_retry
= (be32_to_cpu(context
->params1
) >> 13) & 0x7;
3810 qp_attr
->alt_timeout
= context
->alt_path
.ackto_lt
>> 3;
3817 int mlx5_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
,
3818 int qp_attr_mask
, struct ib_qp_init_attr
*qp_init_attr
)
3820 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
3821 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
3823 u8 raw_packet_qp_state
;
3825 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3827 * Wait for any outstanding page faults, in case the user frees memory
3828 * based upon this query's result.
3830 flush_workqueue(mlx5_ib_page_fault_wq
);
3833 mutex_lock(&qp
->mutex
);
3835 if (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
) {
3836 err
= query_raw_packet_qp_state(dev
, qp
, &raw_packet_qp_state
);
3839 qp
->state
= raw_packet_qp_state
;
3840 qp_attr
->port_num
= 1;
3842 err
= query_qp_attr(dev
, qp
, qp_attr
);
3847 qp_attr
->qp_state
= qp
->state
;
3848 qp_attr
->cur_qp_state
= qp_attr
->qp_state
;
3849 qp_attr
->cap
.max_recv_wr
= qp
->rq
.wqe_cnt
;
3850 qp_attr
->cap
.max_recv_sge
= qp
->rq
.max_gs
;
3852 if (!ibqp
->uobject
) {
3853 qp_attr
->cap
.max_send_wr
= qp
->sq
.wqe_cnt
;
3854 qp_attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
3856 qp_attr
->cap
.max_send_wr
= 0;
3857 qp_attr
->cap
.max_send_sge
= 0;
3860 /* We don't support inline sends for kernel QPs (yet), and we
3861 * don't know what userspace's value should be.
3863 qp_attr
->cap
.max_inline_data
= 0;
3865 qp_init_attr
->cap
= qp_attr
->cap
;
3867 qp_init_attr
->create_flags
= 0;
3868 if (qp
->flags
& MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
)
3869 qp_init_attr
->create_flags
|= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
;
3871 if (qp
->flags
& MLX5_IB_QP_CROSS_CHANNEL
)
3872 qp_init_attr
->create_flags
|= IB_QP_CREATE_CROSS_CHANNEL
;
3873 if (qp
->flags
& MLX5_IB_QP_MANAGED_SEND
)
3874 qp_init_attr
->create_flags
|= IB_QP_CREATE_MANAGED_SEND
;
3875 if (qp
->flags
& MLX5_IB_QP_MANAGED_RECV
)
3876 qp_init_attr
->create_flags
|= IB_QP_CREATE_MANAGED_RECV
;
3878 qp_init_attr
->sq_sig_type
= qp
->sq_signal_bits
& MLX5_WQE_CTRL_CQ_UPDATE
?
3879 IB_SIGNAL_ALL_WR
: IB_SIGNAL_REQ_WR
;
3882 mutex_unlock(&qp
->mutex
);
3886 struct ib_xrcd
*mlx5_ib_alloc_xrcd(struct ib_device
*ibdev
,
3887 struct ib_ucontext
*context
,
3888 struct ib_udata
*udata
)
3890 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
3891 struct mlx5_ib_xrcd
*xrcd
;
3894 if (!MLX5_CAP_GEN(dev
->mdev
, xrc
))
3895 return ERR_PTR(-ENOSYS
);
3897 xrcd
= kmalloc(sizeof(*xrcd
), GFP_KERNEL
);
3899 return ERR_PTR(-ENOMEM
);
3901 err
= mlx5_core_xrcd_alloc(dev
->mdev
, &xrcd
->xrcdn
);
3904 return ERR_PTR(-ENOMEM
);
3907 return &xrcd
->ibxrcd
;
3910 int mlx5_ib_dealloc_xrcd(struct ib_xrcd
*xrcd
)
3912 struct mlx5_ib_dev
*dev
= to_mdev(xrcd
->device
);
3913 u32 xrcdn
= to_mxrcd(xrcd
)->xrcdn
;
3916 err
= mlx5_core_xrcd_dealloc(dev
->mdev
, xrcdn
);
3918 mlx5_ib_warn(dev
, "failed to dealloc xrcdn 0x%x\n", xrcdn
);