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Merge branch 'printk-cleanups'
[mirror_ubuntu-bionic-kernel.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
45 #include <asm/apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
50 #include <asm/gart.h>
51 #include <asm/dma.h>
52
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
56
57 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
58
59 #define LOOP_TIMEOUT 100000
60
61 /* IO virtual address start page frame number */
62 #define IOVA_START_PFN (1)
63 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
65
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
71
72 /*
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
76 * that we support.
77 *
78 * 512GB Pages are not supported due to a hardware bug
79 */
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
81
82 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
83
84 /* List of all available dev_data structures */
85 static LIST_HEAD(dev_data_list);
86 static DEFINE_SPINLOCK(dev_data_list_lock);
87
88 LIST_HEAD(ioapic_map);
89 LIST_HEAD(hpet_map);
90 LIST_HEAD(acpihid_map);
91
92 #define FLUSH_QUEUE_SIZE 256
93
94 struct flush_queue_entry {
95 unsigned long iova_pfn;
96 unsigned long pages;
97 struct dma_ops_domain *dma_dom;
98 };
99
100 struct flush_queue {
101 spinlock_t lock;
102 unsigned next;
103 struct flush_queue_entry *entries;
104 };
105
106 DEFINE_PER_CPU(struct flush_queue, flush_queue);
107
108 static atomic_t queue_timer_on;
109 static struct timer_list queue_timer;
110
111 /*
112 * Domain for untranslated devices - only allocated
113 * if iommu=pt passed on kernel cmd line.
114 */
115 static const struct iommu_ops amd_iommu_ops;
116
117 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
118 int amd_iommu_max_glx_val = -1;
119
120 static struct dma_map_ops amd_iommu_dma_ops;
121
122 /*
123 * This struct contains device specific data for the IOMMU
124 */
125 struct iommu_dev_data {
126 struct list_head list; /* For domain->dev_list */
127 struct list_head dev_data_list; /* For global dev_data_list */
128 struct protection_domain *domain; /* Domain the device is bound to */
129 u16 devid; /* PCI Device ID */
130 u16 alias; /* Alias Device ID */
131 bool iommu_v2; /* Device can make use of IOMMUv2 */
132 bool passthrough; /* Device is identity mapped */
133 struct {
134 bool enabled;
135 int qdep;
136 } ats; /* ATS state */
137 bool pri_tlp; /* PASID TLB required for
138 PPR completions */
139 u32 errata; /* Bitmap for errata to apply */
140 bool use_vapic; /* Enable device to use vapic mode */
141 };
142
143 /*
144 * general struct to manage commands send to an IOMMU
145 */
146 struct iommu_cmd {
147 u32 data[4];
148 };
149
150 struct kmem_cache *amd_iommu_irq_cache;
151
152 static void update_domain(struct protection_domain *domain);
153 static int protection_domain_init(struct protection_domain *domain);
154 static void detach_device(struct device *dev);
155
156 /*
157 * Data container for a dma_ops specific protection domain
158 */
159 struct dma_ops_domain {
160 /* generic protection domain information */
161 struct protection_domain domain;
162
163 /* IOVA RB-Tree */
164 struct iova_domain iovad;
165 };
166
167 static struct iova_domain reserved_iova_ranges;
168 static struct lock_class_key reserved_rbtree_key;
169
170 /****************************************************************************
171 *
172 * Helper functions
173 *
174 ****************************************************************************/
175
176 static inline int match_hid_uid(struct device *dev,
177 struct acpihid_map_entry *entry)
178 {
179 const char *hid, *uid;
180
181 hid = acpi_device_hid(ACPI_COMPANION(dev));
182 uid = acpi_device_uid(ACPI_COMPANION(dev));
183
184 if (!hid || !(*hid))
185 return -ENODEV;
186
187 if (!uid || !(*uid))
188 return strcmp(hid, entry->hid);
189
190 if (!(*entry->uid))
191 return strcmp(hid, entry->hid);
192
193 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
194 }
195
196 static inline u16 get_pci_device_id(struct device *dev)
197 {
198 struct pci_dev *pdev = to_pci_dev(dev);
199
200 return PCI_DEVID(pdev->bus->number, pdev->devfn);
201 }
202
203 static inline int get_acpihid_device_id(struct device *dev,
204 struct acpihid_map_entry **entry)
205 {
206 struct acpihid_map_entry *p;
207
208 list_for_each_entry(p, &acpihid_map, list) {
209 if (!match_hid_uid(dev, p)) {
210 if (entry)
211 *entry = p;
212 return p->devid;
213 }
214 }
215 return -EINVAL;
216 }
217
218 static inline int get_device_id(struct device *dev)
219 {
220 int devid;
221
222 if (dev_is_pci(dev))
223 devid = get_pci_device_id(dev);
224 else
225 devid = get_acpihid_device_id(dev, NULL);
226
227 return devid;
228 }
229
230 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
231 {
232 return container_of(dom, struct protection_domain, domain);
233 }
234
235 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
236 {
237 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
238 return container_of(domain, struct dma_ops_domain, domain);
239 }
240
241 static struct iommu_dev_data *alloc_dev_data(u16 devid)
242 {
243 struct iommu_dev_data *dev_data;
244 unsigned long flags;
245
246 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
247 if (!dev_data)
248 return NULL;
249
250 dev_data->devid = devid;
251
252 spin_lock_irqsave(&dev_data_list_lock, flags);
253 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
254 spin_unlock_irqrestore(&dev_data_list_lock, flags);
255
256 return dev_data;
257 }
258
259 static struct iommu_dev_data *search_dev_data(u16 devid)
260 {
261 struct iommu_dev_data *dev_data;
262 unsigned long flags;
263
264 spin_lock_irqsave(&dev_data_list_lock, flags);
265 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
266 if (dev_data->devid == devid)
267 goto out_unlock;
268 }
269
270 dev_data = NULL;
271
272 out_unlock:
273 spin_unlock_irqrestore(&dev_data_list_lock, flags);
274
275 return dev_data;
276 }
277
278 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
279 {
280 *(u16 *)data = alias;
281 return 0;
282 }
283
284 static u16 get_alias(struct device *dev)
285 {
286 struct pci_dev *pdev = to_pci_dev(dev);
287 u16 devid, ivrs_alias, pci_alias;
288
289 /* The callers make sure that get_device_id() does not fail here */
290 devid = get_device_id(dev);
291 ivrs_alias = amd_iommu_alias_table[devid];
292 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
293
294 if (ivrs_alias == pci_alias)
295 return ivrs_alias;
296
297 /*
298 * DMA alias showdown
299 *
300 * The IVRS is fairly reliable in telling us about aliases, but it
301 * can't know about every screwy device. If we don't have an IVRS
302 * reported alias, use the PCI reported alias. In that case we may
303 * still need to initialize the rlookup and dev_table entries if the
304 * alias is to a non-existent device.
305 */
306 if (ivrs_alias == devid) {
307 if (!amd_iommu_rlookup_table[pci_alias]) {
308 amd_iommu_rlookup_table[pci_alias] =
309 amd_iommu_rlookup_table[devid];
310 memcpy(amd_iommu_dev_table[pci_alias].data,
311 amd_iommu_dev_table[devid].data,
312 sizeof(amd_iommu_dev_table[pci_alias].data));
313 }
314
315 return pci_alias;
316 }
317
318 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
319 "for device %s[%04x:%04x], kernel reported alias "
320 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
321 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
322 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
323 PCI_FUNC(pci_alias));
324
325 /*
326 * If we don't have a PCI DMA alias and the IVRS alias is on the same
327 * bus, then the IVRS table may know about a quirk that we don't.
328 */
329 if (pci_alias == devid &&
330 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
331 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
332 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
333 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
334 dev_name(dev));
335 }
336
337 return ivrs_alias;
338 }
339
340 static struct iommu_dev_data *find_dev_data(u16 devid)
341 {
342 struct iommu_dev_data *dev_data;
343
344 dev_data = search_dev_data(devid);
345
346 if (dev_data == NULL)
347 dev_data = alloc_dev_data(devid);
348
349 return dev_data;
350 }
351
352 static struct iommu_dev_data *get_dev_data(struct device *dev)
353 {
354 return dev->archdata.iommu;
355 }
356
357 /*
358 * Find or create an IOMMU group for a acpihid device.
359 */
360 static struct iommu_group *acpihid_device_group(struct device *dev)
361 {
362 struct acpihid_map_entry *p, *entry = NULL;
363 int devid;
364
365 devid = get_acpihid_device_id(dev, &entry);
366 if (devid < 0)
367 return ERR_PTR(devid);
368
369 list_for_each_entry(p, &acpihid_map, list) {
370 if ((devid == p->devid) && p->group)
371 entry->group = p->group;
372 }
373
374 if (!entry->group)
375 entry->group = generic_device_group(dev);
376
377 return entry->group;
378 }
379
380 static bool pci_iommuv2_capable(struct pci_dev *pdev)
381 {
382 static const int caps[] = {
383 PCI_EXT_CAP_ID_ATS,
384 PCI_EXT_CAP_ID_PRI,
385 PCI_EXT_CAP_ID_PASID,
386 };
387 int i, pos;
388
389 for (i = 0; i < 3; ++i) {
390 pos = pci_find_ext_capability(pdev, caps[i]);
391 if (pos == 0)
392 return false;
393 }
394
395 return true;
396 }
397
398 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
399 {
400 struct iommu_dev_data *dev_data;
401
402 dev_data = get_dev_data(&pdev->dev);
403
404 return dev_data->errata & (1 << erratum) ? true : false;
405 }
406
407 /*
408 * This function checks if the driver got a valid device from the caller to
409 * avoid dereferencing invalid pointers.
410 */
411 static bool check_device(struct device *dev)
412 {
413 int devid;
414
415 if (!dev || !dev->dma_mask)
416 return false;
417
418 devid = get_device_id(dev);
419 if (devid < 0)
420 return false;
421
422 /* Out of our scope? */
423 if (devid > amd_iommu_last_bdf)
424 return false;
425
426 if (amd_iommu_rlookup_table[devid] == NULL)
427 return false;
428
429 return true;
430 }
431
432 static void init_iommu_group(struct device *dev)
433 {
434 struct iommu_group *group;
435
436 group = iommu_group_get_for_dev(dev);
437 if (IS_ERR(group))
438 return;
439
440 iommu_group_put(group);
441 }
442
443 static int iommu_init_device(struct device *dev)
444 {
445 struct iommu_dev_data *dev_data;
446 int devid;
447
448 if (dev->archdata.iommu)
449 return 0;
450
451 devid = get_device_id(dev);
452 if (devid < 0)
453 return devid;
454
455 dev_data = find_dev_data(devid);
456 if (!dev_data)
457 return -ENOMEM;
458
459 dev_data->alias = get_alias(dev);
460
461 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
462 struct amd_iommu *iommu;
463
464 iommu = amd_iommu_rlookup_table[dev_data->devid];
465 dev_data->iommu_v2 = iommu->is_iommu_v2;
466 }
467
468 dev->archdata.iommu = dev_data;
469
470 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
471 dev);
472
473 return 0;
474 }
475
476 static void iommu_ignore_device(struct device *dev)
477 {
478 u16 alias;
479 int devid;
480
481 devid = get_device_id(dev);
482 if (devid < 0)
483 return;
484
485 alias = get_alias(dev);
486
487 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
488 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
489
490 amd_iommu_rlookup_table[devid] = NULL;
491 amd_iommu_rlookup_table[alias] = NULL;
492 }
493
494 static void iommu_uninit_device(struct device *dev)
495 {
496 int devid;
497 struct iommu_dev_data *dev_data;
498
499 devid = get_device_id(dev);
500 if (devid < 0)
501 return;
502
503 dev_data = search_dev_data(devid);
504 if (!dev_data)
505 return;
506
507 if (dev_data->domain)
508 detach_device(dev);
509
510 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
511 dev);
512
513 iommu_group_remove_device(dev);
514
515 /* Remove dma-ops */
516 dev->archdata.dma_ops = NULL;
517
518 /*
519 * We keep dev_data around for unplugged devices and reuse it when the
520 * device is re-plugged - not doing so would introduce a ton of races.
521 */
522 }
523
524 /****************************************************************************
525 *
526 * Interrupt handling functions
527 *
528 ****************************************************************************/
529
530 static void dump_dte_entry(u16 devid)
531 {
532 int i;
533
534 for (i = 0; i < 4; ++i)
535 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
536 amd_iommu_dev_table[devid].data[i]);
537 }
538
539 static void dump_command(unsigned long phys_addr)
540 {
541 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
542 int i;
543
544 for (i = 0; i < 4; ++i)
545 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
546 }
547
548 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
549 {
550 int type, devid, domid, flags;
551 volatile u32 *event = __evt;
552 int count = 0;
553 u64 address;
554
555 retry:
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
561
562 if (type == 0) {
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
566 return;
567 }
568 udelay(1);
569 goto retry;
570 }
571
572 printk(KERN_ERR "AMD-Vi: Event logged [");
573
574 switch (type) {
575 case EVENT_TYPE_ILL_DEV:
576 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
577 "address=0x%016llx flags=0x%04x]\n",
578 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
579 address, flags);
580 dump_dte_entry(devid);
581 break;
582 case EVENT_TYPE_IO_FAULT:
583 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
584 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
585 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
586 domid, address, flags);
587 break;
588 case EVENT_TYPE_DEV_TAB_ERR:
589 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
590 "address=0x%016llx flags=0x%04x]\n",
591 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
592 address, flags);
593 break;
594 case EVENT_TYPE_PAGE_TAB_ERR:
595 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
596 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 domid, address, flags);
599 break;
600 case EVENT_TYPE_ILL_CMD:
601 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
602 dump_command(address);
603 break;
604 case EVENT_TYPE_CMD_HARD_ERR:
605 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
606 "flags=0x%04x]\n", address, flags);
607 break;
608 case EVENT_TYPE_IOTLB_INV_TO:
609 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
610 "address=0x%016llx]\n",
611 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
612 address);
613 break;
614 case EVENT_TYPE_INV_DEV_REQ:
615 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
616 "address=0x%016llx flags=0x%04x]\n",
617 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
618 address, flags);
619 break;
620 default:
621 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
622 }
623
624 memset(__evt, 0, 4 * sizeof(u32));
625 }
626
627 static void iommu_poll_events(struct amd_iommu *iommu)
628 {
629 u32 head, tail;
630
631 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
632 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
633
634 while (head != tail) {
635 iommu_print_event(iommu, iommu->evt_buf + head);
636 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
637 }
638
639 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
640 }
641
642 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
643 {
644 struct amd_iommu_fault fault;
645
646 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
647 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
648 return;
649 }
650
651 fault.address = raw[1];
652 fault.pasid = PPR_PASID(raw[0]);
653 fault.device_id = PPR_DEVID(raw[0]);
654 fault.tag = PPR_TAG(raw[0]);
655 fault.flags = PPR_FLAGS(raw[0]);
656
657 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
658 }
659
660 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
661 {
662 u32 head, tail;
663
664 if (iommu->ppr_log == NULL)
665 return;
666
667 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
668 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
669
670 while (head != tail) {
671 volatile u64 *raw;
672 u64 entry[2];
673 int i;
674
675 raw = (u64 *)(iommu->ppr_log + head);
676
677 /*
678 * Hardware bug: Interrupt may arrive before the entry is
679 * written to memory. If this happens we need to wait for the
680 * entry to arrive.
681 */
682 for (i = 0; i < LOOP_TIMEOUT; ++i) {
683 if (PPR_REQ_TYPE(raw[0]) != 0)
684 break;
685 udelay(1);
686 }
687
688 /* Avoid memcpy function-call overhead */
689 entry[0] = raw[0];
690 entry[1] = raw[1];
691
692 /*
693 * To detect the hardware bug we need to clear the entry
694 * back to zero.
695 */
696 raw[0] = raw[1] = 0UL;
697
698 /* Update head pointer of hardware ring-buffer */
699 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
700 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
701
702 /* Handle PPR entry */
703 iommu_handle_ppr_entry(iommu, entry);
704
705 /* Refresh ring-buffer information */
706 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
707 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
708 }
709 }
710
711 #ifdef CONFIG_IRQ_REMAP
712 static int (*iommu_ga_log_notifier)(u32);
713
714 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
715 {
716 iommu_ga_log_notifier = notifier;
717
718 return 0;
719 }
720 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
721
722 static void iommu_poll_ga_log(struct amd_iommu *iommu)
723 {
724 u32 head, tail, cnt = 0;
725
726 if (iommu->ga_log == NULL)
727 return;
728
729 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
730 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
731
732 while (head != tail) {
733 volatile u64 *raw;
734 u64 log_entry;
735
736 raw = (u64 *)(iommu->ga_log + head);
737 cnt++;
738
739 /* Avoid memcpy function-call overhead */
740 log_entry = *raw;
741
742 /* Update head pointer of hardware ring-buffer */
743 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
744 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
745
746 /* Handle GA entry */
747 switch (GA_REQ_TYPE(log_entry)) {
748 case GA_GUEST_NR:
749 if (!iommu_ga_log_notifier)
750 break;
751
752 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
753 __func__, GA_DEVID(log_entry),
754 GA_TAG(log_entry));
755
756 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
757 pr_err("AMD-Vi: GA log notifier failed.\n");
758 break;
759 default:
760 break;
761 }
762 }
763 }
764 #endif /* CONFIG_IRQ_REMAP */
765
766 #define AMD_IOMMU_INT_MASK \
767 (MMIO_STATUS_EVT_INT_MASK | \
768 MMIO_STATUS_PPR_INT_MASK | \
769 MMIO_STATUS_GALOG_INT_MASK)
770
771 irqreturn_t amd_iommu_int_thread(int irq, void *data)
772 {
773 struct amd_iommu *iommu = (struct amd_iommu *) data;
774 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
775
776 while (status & AMD_IOMMU_INT_MASK) {
777 /* Enable EVT and PPR and GA interrupts again */
778 writel(AMD_IOMMU_INT_MASK,
779 iommu->mmio_base + MMIO_STATUS_OFFSET);
780
781 if (status & MMIO_STATUS_EVT_INT_MASK) {
782 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
783 iommu_poll_events(iommu);
784 }
785
786 if (status & MMIO_STATUS_PPR_INT_MASK) {
787 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
788 iommu_poll_ppr_log(iommu);
789 }
790
791 #ifdef CONFIG_IRQ_REMAP
792 if (status & MMIO_STATUS_GALOG_INT_MASK) {
793 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
794 iommu_poll_ga_log(iommu);
795 }
796 #endif
797
798 /*
799 * Hardware bug: ERBT1312
800 * When re-enabling interrupt (by writing 1
801 * to clear the bit), the hardware might also try to set
802 * the interrupt bit in the event status register.
803 * In this scenario, the bit will be set, and disable
804 * subsequent interrupts.
805 *
806 * Workaround: The IOMMU driver should read back the
807 * status register and check if the interrupt bits are cleared.
808 * If not, driver will need to go through the interrupt handler
809 * again and re-clear the bits
810 */
811 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
812 }
813 return IRQ_HANDLED;
814 }
815
816 irqreturn_t amd_iommu_int_handler(int irq, void *data)
817 {
818 return IRQ_WAKE_THREAD;
819 }
820
821 /****************************************************************************
822 *
823 * IOMMU command queuing functions
824 *
825 ****************************************************************************/
826
827 static int wait_on_sem(volatile u64 *sem)
828 {
829 int i = 0;
830
831 while (*sem == 0 && i < LOOP_TIMEOUT) {
832 udelay(1);
833 i += 1;
834 }
835
836 if (i == LOOP_TIMEOUT) {
837 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
838 return -EIO;
839 }
840
841 return 0;
842 }
843
844 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
845 struct iommu_cmd *cmd,
846 u32 tail)
847 {
848 u8 *target;
849
850 target = iommu->cmd_buf + tail;
851 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
852
853 /* Copy command to buffer */
854 memcpy(target, cmd, sizeof(*cmd));
855
856 /* Tell the IOMMU about it */
857 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
858 }
859
860 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
861 {
862 WARN_ON(address & 0x7ULL);
863
864 memset(cmd, 0, sizeof(*cmd));
865 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
866 cmd->data[1] = upper_32_bits(__pa(address));
867 cmd->data[2] = 1;
868 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
869 }
870
871 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
872 {
873 memset(cmd, 0, sizeof(*cmd));
874 cmd->data[0] = devid;
875 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
876 }
877
878 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
879 size_t size, u16 domid, int pde)
880 {
881 u64 pages;
882 bool s;
883
884 pages = iommu_num_pages(address, size, PAGE_SIZE);
885 s = false;
886
887 if (pages > 1) {
888 /*
889 * If we have to flush more than one page, flush all
890 * TLB entries for this domain
891 */
892 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
893 s = true;
894 }
895
896 address &= PAGE_MASK;
897
898 memset(cmd, 0, sizeof(*cmd));
899 cmd->data[1] |= domid;
900 cmd->data[2] = lower_32_bits(address);
901 cmd->data[3] = upper_32_bits(address);
902 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
903 if (s) /* size bit - we flush more than one 4kb page */
904 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
905 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
906 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
907 }
908
909 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
910 u64 address, size_t size)
911 {
912 u64 pages;
913 bool s;
914
915 pages = iommu_num_pages(address, size, PAGE_SIZE);
916 s = false;
917
918 if (pages > 1) {
919 /*
920 * If we have to flush more than one page, flush all
921 * TLB entries for this domain
922 */
923 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
924 s = true;
925 }
926
927 address &= PAGE_MASK;
928
929 memset(cmd, 0, sizeof(*cmd));
930 cmd->data[0] = devid;
931 cmd->data[0] |= (qdep & 0xff) << 24;
932 cmd->data[1] = devid;
933 cmd->data[2] = lower_32_bits(address);
934 cmd->data[3] = upper_32_bits(address);
935 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
936 if (s)
937 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
938 }
939
940 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
941 u64 address, bool size)
942 {
943 memset(cmd, 0, sizeof(*cmd));
944
945 address &= ~(0xfffULL);
946
947 cmd->data[0] = pasid;
948 cmd->data[1] = domid;
949 cmd->data[2] = lower_32_bits(address);
950 cmd->data[3] = upper_32_bits(address);
951 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
952 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
953 if (size)
954 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
955 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
956 }
957
958 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
959 int qdep, u64 address, bool size)
960 {
961 memset(cmd, 0, sizeof(*cmd));
962
963 address &= ~(0xfffULL);
964
965 cmd->data[0] = devid;
966 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
967 cmd->data[0] |= (qdep & 0xff) << 24;
968 cmd->data[1] = devid;
969 cmd->data[1] |= (pasid & 0xff) << 16;
970 cmd->data[2] = lower_32_bits(address);
971 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
972 cmd->data[3] = upper_32_bits(address);
973 if (size)
974 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
975 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
976 }
977
978 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
979 int status, int tag, bool gn)
980 {
981 memset(cmd, 0, sizeof(*cmd));
982
983 cmd->data[0] = devid;
984 if (gn) {
985 cmd->data[1] = pasid;
986 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
987 }
988 cmd->data[3] = tag & 0x1ff;
989 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
990
991 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
992 }
993
994 static void build_inv_all(struct iommu_cmd *cmd)
995 {
996 memset(cmd, 0, sizeof(*cmd));
997 CMD_SET_TYPE(cmd, CMD_INV_ALL);
998 }
999
1000 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1001 {
1002 memset(cmd, 0, sizeof(*cmd));
1003 cmd->data[0] = devid;
1004 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1005 }
1006
1007 /*
1008 * Writes the command to the IOMMUs command buffer and informs the
1009 * hardware about the new command.
1010 */
1011 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1012 struct iommu_cmd *cmd,
1013 bool sync)
1014 {
1015 u32 left, tail, head, next_tail;
1016
1017 again:
1018
1019 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1020 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1021 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1022 left = (head - next_tail) % CMD_BUFFER_SIZE;
1023
1024 if (left <= 2) {
1025 struct iommu_cmd sync_cmd;
1026 int ret;
1027
1028 iommu->cmd_sem = 0;
1029
1030 build_completion_wait(&sync_cmd, (u64)&iommu->cmd_sem);
1031 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1032
1033 if ((ret = wait_on_sem(&iommu->cmd_sem)) != 0)
1034 return ret;
1035
1036 goto again;
1037 }
1038
1039 copy_cmd_to_buffer(iommu, cmd, tail);
1040
1041 /* We need to sync now to make sure all commands are processed */
1042 iommu->need_sync = sync;
1043
1044 return 0;
1045 }
1046
1047 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1048 struct iommu_cmd *cmd,
1049 bool sync)
1050 {
1051 unsigned long flags;
1052 int ret;
1053
1054 spin_lock_irqsave(&iommu->lock, flags);
1055 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1056 spin_unlock_irqrestore(&iommu->lock, flags);
1057
1058 return ret;
1059 }
1060
1061 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1062 {
1063 return iommu_queue_command_sync(iommu, cmd, true);
1064 }
1065
1066 /*
1067 * This function queues a completion wait command into the command
1068 * buffer of an IOMMU
1069 */
1070 static int iommu_completion_wait(struct amd_iommu *iommu)
1071 {
1072 struct iommu_cmd cmd;
1073 unsigned long flags;
1074 int ret;
1075
1076 if (!iommu->need_sync)
1077 return 0;
1078
1079
1080 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1081
1082 spin_lock_irqsave(&iommu->lock, flags);
1083
1084 iommu->cmd_sem = 0;
1085
1086 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1087 if (ret)
1088 goto out_unlock;
1089
1090 ret = wait_on_sem(&iommu->cmd_sem);
1091
1092 out_unlock:
1093 spin_unlock_irqrestore(&iommu->lock, flags);
1094
1095 return ret;
1096 }
1097
1098 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1099 {
1100 struct iommu_cmd cmd;
1101
1102 build_inv_dte(&cmd, devid);
1103
1104 return iommu_queue_command(iommu, &cmd);
1105 }
1106
1107 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1108 {
1109 u32 devid;
1110
1111 for (devid = 0; devid <= 0xffff; ++devid)
1112 iommu_flush_dte(iommu, devid);
1113
1114 iommu_completion_wait(iommu);
1115 }
1116
1117 /*
1118 * This function uses heavy locking and may disable irqs for some time. But
1119 * this is no issue because it is only called during resume.
1120 */
1121 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1122 {
1123 u32 dom_id;
1124
1125 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1126 struct iommu_cmd cmd;
1127 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1128 dom_id, 1);
1129 iommu_queue_command(iommu, &cmd);
1130 }
1131
1132 iommu_completion_wait(iommu);
1133 }
1134
1135 static void iommu_flush_all(struct amd_iommu *iommu)
1136 {
1137 struct iommu_cmd cmd;
1138
1139 build_inv_all(&cmd);
1140
1141 iommu_queue_command(iommu, &cmd);
1142 iommu_completion_wait(iommu);
1143 }
1144
1145 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1146 {
1147 struct iommu_cmd cmd;
1148
1149 build_inv_irt(&cmd, devid);
1150
1151 iommu_queue_command(iommu, &cmd);
1152 }
1153
1154 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1155 {
1156 u32 devid;
1157
1158 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1159 iommu_flush_irt(iommu, devid);
1160
1161 iommu_completion_wait(iommu);
1162 }
1163
1164 void iommu_flush_all_caches(struct amd_iommu *iommu)
1165 {
1166 if (iommu_feature(iommu, FEATURE_IA)) {
1167 iommu_flush_all(iommu);
1168 } else {
1169 iommu_flush_dte_all(iommu);
1170 iommu_flush_irt_all(iommu);
1171 iommu_flush_tlb_all(iommu);
1172 }
1173 }
1174
1175 /*
1176 * Command send function for flushing on-device TLB
1177 */
1178 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1179 u64 address, size_t size)
1180 {
1181 struct amd_iommu *iommu;
1182 struct iommu_cmd cmd;
1183 int qdep;
1184
1185 qdep = dev_data->ats.qdep;
1186 iommu = amd_iommu_rlookup_table[dev_data->devid];
1187
1188 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1189
1190 return iommu_queue_command(iommu, &cmd);
1191 }
1192
1193 /*
1194 * Command send function for invalidating a device table entry
1195 */
1196 static int device_flush_dte(struct iommu_dev_data *dev_data)
1197 {
1198 struct amd_iommu *iommu;
1199 u16 alias;
1200 int ret;
1201
1202 iommu = amd_iommu_rlookup_table[dev_data->devid];
1203 alias = dev_data->alias;
1204
1205 ret = iommu_flush_dte(iommu, dev_data->devid);
1206 if (!ret && alias != dev_data->devid)
1207 ret = iommu_flush_dte(iommu, alias);
1208 if (ret)
1209 return ret;
1210
1211 if (dev_data->ats.enabled)
1212 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1213
1214 return ret;
1215 }
1216
1217 /*
1218 * TLB invalidation function which is called from the mapping functions.
1219 * It invalidates a single PTE if the range to flush is within a single
1220 * page. Otherwise it flushes the whole TLB of the IOMMU.
1221 */
1222 static void __domain_flush_pages(struct protection_domain *domain,
1223 u64 address, size_t size, int pde)
1224 {
1225 struct iommu_dev_data *dev_data;
1226 struct iommu_cmd cmd;
1227 int ret = 0, i;
1228
1229 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1230
1231 for (i = 0; i < amd_iommus_present; ++i) {
1232 if (!domain->dev_iommu[i])
1233 continue;
1234
1235 /*
1236 * Devices of this domain are behind this IOMMU
1237 * We need a TLB flush
1238 */
1239 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1240 }
1241
1242 list_for_each_entry(dev_data, &domain->dev_list, list) {
1243
1244 if (!dev_data->ats.enabled)
1245 continue;
1246
1247 ret |= device_flush_iotlb(dev_data, address, size);
1248 }
1249
1250 WARN_ON(ret);
1251 }
1252
1253 static void domain_flush_pages(struct protection_domain *domain,
1254 u64 address, size_t size)
1255 {
1256 __domain_flush_pages(domain, address, size, 0);
1257 }
1258
1259 /* Flush the whole IO/TLB for a given protection domain */
1260 static void domain_flush_tlb(struct protection_domain *domain)
1261 {
1262 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1263 }
1264
1265 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1266 static void domain_flush_tlb_pde(struct protection_domain *domain)
1267 {
1268 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1269 }
1270
1271 static void domain_flush_complete(struct protection_domain *domain)
1272 {
1273 int i;
1274
1275 for (i = 0; i < amd_iommus_present; ++i) {
1276 if (domain && !domain->dev_iommu[i])
1277 continue;
1278
1279 /*
1280 * Devices of this domain are behind this IOMMU
1281 * We need to wait for completion of all commands.
1282 */
1283 iommu_completion_wait(amd_iommus[i]);
1284 }
1285 }
1286
1287
1288 /*
1289 * This function flushes the DTEs for all devices in domain
1290 */
1291 static void domain_flush_devices(struct protection_domain *domain)
1292 {
1293 struct iommu_dev_data *dev_data;
1294
1295 list_for_each_entry(dev_data, &domain->dev_list, list)
1296 device_flush_dte(dev_data);
1297 }
1298
1299 /****************************************************************************
1300 *
1301 * The functions below are used the create the page table mappings for
1302 * unity mapped regions.
1303 *
1304 ****************************************************************************/
1305
1306 /*
1307 * This function is used to add another level to an IO page table. Adding
1308 * another level increases the size of the address space by 9 bits to a size up
1309 * to 64 bits.
1310 */
1311 static bool increase_address_space(struct protection_domain *domain,
1312 gfp_t gfp)
1313 {
1314 u64 *pte;
1315
1316 if (domain->mode == PAGE_MODE_6_LEVEL)
1317 /* address space already 64 bit large */
1318 return false;
1319
1320 pte = (void *)get_zeroed_page(gfp);
1321 if (!pte)
1322 return false;
1323
1324 *pte = PM_LEVEL_PDE(domain->mode,
1325 virt_to_phys(domain->pt_root));
1326 domain->pt_root = pte;
1327 domain->mode += 1;
1328 domain->updated = true;
1329
1330 return true;
1331 }
1332
1333 static u64 *alloc_pte(struct protection_domain *domain,
1334 unsigned long address,
1335 unsigned long page_size,
1336 u64 **pte_page,
1337 gfp_t gfp)
1338 {
1339 int level, end_lvl;
1340 u64 *pte, *page;
1341
1342 BUG_ON(!is_power_of_2(page_size));
1343
1344 while (address > PM_LEVEL_SIZE(domain->mode))
1345 increase_address_space(domain, gfp);
1346
1347 level = domain->mode - 1;
1348 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1349 address = PAGE_SIZE_ALIGN(address, page_size);
1350 end_lvl = PAGE_SIZE_LEVEL(page_size);
1351
1352 while (level > end_lvl) {
1353 u64 __pte, __npte;
1354
1355 __pte = *pte;
1356
1357 if (!IOMMU_PTE_PRESENT(__pte)) {
1358 page = (u64 *)get_zeroed_page(gfp);
1359 if (!page)
1360 return NULL;
1361
1362 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1363
1364 if (cmpxchg64(pte, __pte, __npte)) {
1365 free_page((unsigned long)page);
1366 continue;
1367 }
1368 }
1369
1370 /* No level skipping support yet */
1371 if (PM_PTE_LEVEL(*pte) != level)
1372 return NULL;
1373
1374 level -= 1;
1375
1376 pte = IOMMU_PTE_PAGE(*pte);
1377
1378 if (pte_page && level == end_lvl)
1379 *pte_page = pte;
1380
1381 pte = &pte[PM_LEVEL_INDEX(level, address)];
1382 }
1383
1384 return pte;
1385 }
1386
1387 /*
1388 * This function checks if there is a PTE for a given dma address. If
1389 * there is one, it returns the pointer to it.
1390 */
1391 static u64 *fetch_pte(struct protection_domain *domain,
1392 unsigned long address,
1393 unsigned long *page_size)
1394 {
1395 int level;
1396 u64 *pte;
1397
1398 if (address > PM_LEVEL_SIZE(domain->mode))
1399 return NULL;
1400
1401 level = domain->mode - 1;
1402 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1403 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1404
1405 while (level > 0) {
1406
1407 /* Not Present */
1408 if (!IOMMU_PTE_PRESENT(*pte))
1409 return NULL;
1410
1411 /* Large PTE */
1412 if (PM_PTE_LEVEL(*pte) == 7 ||
1413 PM_PTE_LEVEL(*pte) == 0)
1414 break;
1415
1416 /* No level skipping support yet */
1417 if (PM_PTE_LEVEL(*pte) != level)
1418 return NULL;
1419
1420 level -= 1;
1421
1422 /* Walk to the next level */
1423 pte = IOMMU_PTE_PAGE(*pte);
1424 pte = &pte[PM_LEVEL_INDEX(level, address)];
1425 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1426 }
1427
1428 if (PM_PTE_LEVEL(*pte) == 0x07) {
1429 unsigned long pte_mask;
1430
1431 /*
1432 * If we have a series of large PTEs, make
1433 * sure to return a pointer to the first one.
1434 */
1435 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1436 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1437 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1438 }
1439
1440 return pte;
1441 }
1442
1443 /*
1444 * Generic mapping functions. It maps a physical address into a DMA
1445 * address space. It allocates the page table pages if necessary.
1446 * In the future it can be extended to a generic mapping function
1447 * supporting all features of AMD IOMMU page tables like level skipping
1448 * and full 64 bit address spaces.
1449 */
1450 static int iommu_map_page(struct protection_domain *dom,
1451 unsigned long bus_addr,
1452 unsigned long phys_addr,
1453 unsigned long page_size,
1454 int prot,
1455 gfp_t gfp)
1456 {
1457 u64 __pte, *pte;
1458 int i, count;
1459
1460 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1461 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1462
1463 if (!(prot & IOMMU_PROT_MASK))
1464 return -EINVAL;
1465
1466 count = PAGE_SIZE_PTE_COUNT(page_size);
1467 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1468
1469 if (!pte)
1470 return -ENOMEM;
1471
1472 for (i = 0; i < count; ++i)
1473 if (IOMMU_PTE_PRESENT(pte[i]))
1474 return -EBUSY;
1475
1476 if (count > 1) {
1477 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1478 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1479 } else
1480 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1481
1482 if (prot & IOMMU_PROT_IR)
1483 __pte |= IOMMU_PTE_IR;
1484 if (prot & IOMMU_PROT_IW)
1485 __pte |= IOMMU_PTE_IW;
1486
1487 for (i = 0; i < count; ++i)
1488 pte[i] = __pte;
1489
1490 update_domain(dom);
1491
1492 return 0;
1493 }
1494
1495 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1496 unsigned long bus_addr,
1497 unsigned long page_size)
1498 {
1499 unsigned long long unmapped;
1500 unsigned long unmap_size;
1501 u64 *pte;
1502
1503 BUG_ON(!is_power_of_2(page_size));
1504
1505 unmapped = 0;
1506
1507 while (unmapped < page_size) {
1508
1509 pte = fetch_pte(dom, bus_addr, &unmap_size);
1510
1511 if (pte) {
1512 int i, count;
1513
1514 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1515 for (i = 0; i < count; i++)
1516 pte[i] = 0ULL;
1517 }
1518
1519 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1520 unmapped += unmap_size;
1521 }
1522
1523 BUG_ON(unmapped && !is_power_of_2(unmapped));
1524
1525 return unmapped;
1526 }
1527
1528 /****************************************************************************
1529 *
1530 * The next functions belong to the address allocator for the dma_ops
1531 * interface functions.
1532 *
1533 ****************************************************************************/
1534
1535
1536 static unsigned long dma_ops_alloc_iova(struct device *dev,
1537 struct dma_ops_domain *dma_dom,
1538 unsigned int pages, u64 dma_mask)
1539 {
1540 unsigned long pfn = 0;
1541
1542 pages = __roundup_pow_of_two(pages);
1543
1544 if (dma_mask > DMA_BIT_MASK(32))
1545 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1546 IOVA_PFN(DMA_BIT_MASK(32)));
1547
1548 if (!pfn)
1549 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1550
1551 return (pfn << PAGE_SHIFT);
1552 }
1553
1554 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1555 unsigned long address,
1556 unsigned int pages)
1557 {
1558 pages = __roundup_pow_of_two(pages);
1559 address >>= PAGE_SHIFT;
1560
1561 free_iova_fast(&dma_dom->iovad, address, pages);
1562 }
1563
1564 /****************************************************************************
1565 *
1566 * The next functions belong to the domain allocation. A domain is
1567 * allocated for every IOMMU as the default domain. If device isolation
1568 * is enabled, every device get its own domain. The most important thing
1569 * about domains is the page table mapping the DMA address space they
1570 * contain.
1571 *
1572 ****************************************************************************/
1573
1574 /*
1575 * This function adds a protection domain to the global protection domain list
1576 */
1577 static void add_domain_to_list(struct protection_domain *domain)
1578 {
1579 unsigned long flags;
1580
1581 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1582 list_add(&domain->list, &amd_iommu_pd_list);
1583 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1584 }
1585
1586 /*
1587 * This function removes a protection domain to the global
1588 * protection domain list
1589 */
1590 static void del_domain_from_list(struct protection_domain *domain)
1591 {
1592 unsigned long flags;
1593
1594 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1595 list_del(&domain->list);
1596 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1597 }
1598
1599 static u16 domain_id_alloc(void)
1600 {
1601 unsigned long flags;
1602 int id;
1603
1604 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1605 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1606 BUG_ON(id == 0);
1607 if (id > 0 && id < MAX_DOMAIN_ID)
1608 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1609 else
1610 id = 0;
1611 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1612
1613 return id;
1614 }
1615
1616 static void domain_id_free(int id)
1617 {
1618 unsigned long flags;
1619
1620 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1621 if (id > 0 && id < MAX_DOMAIN_ID)
1622 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1623 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1624 }
1625
1626 #define DEFINE_FREE_PT_FN(LVL, FN) \
1627 static void free_pt_##LVL (unsigned long __pt) \
1628 { \
1629 unsigned long p; \
1630 u64 *pt; \
1631 int i; \
1632 \
1633 pt = (u64 *)__pt; \
1634 \
1635 for (i = 0; i < 512; ++i) { \
1636 /* PTE present? */ \
1637 if (!IOMMU_PTE_PRESENT(pt[i])) \
1638 continue; \
1639 \
1640 /* Large PTE? */ \
1641 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1642 PM_PTE_LEVEL(pt[i]) == 7) \
1643 continue; \
1644 \
1645 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1646 FN(p); \
1647 } \
1648 free_page((unsigned long)pt); \
1649 }
1650
1651 DEFINE_FREE_PT_FN(l2, free_page)
1652 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1653 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1654 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1655 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1656
1657 static void free_pagetable(struct protection_domain *domain)
1658 {
1659 unsigned long root = (unsigned long)domain->pt_root;
1660
1661 switch (domain->mode) {
1662 case PAGE_MODE_NONE:
1663 break;
1664 case PAGE_MODE_1_LEVEL:
1665 free_page(root);
1666 break;
1667 case PAGE_MODE_2_LEVEL:
1668 free_pt_l2(root);
1669 break;
1670 case PAGE_MODE_3_LEVEL:
1671 free_pt_l3(root);
1672 break;
1673 case PAGE_MODE_4_LEVEL:
1674 free_pt_l4(root);
1675 break;
1676 case PAGE_MODE_5_LEVEL:
1677 free_pt_l5(root);
1678 break;
1679 case PAGE_MODE_6_LEVEL:
1680 free_pt_l6(root);
1681 break;
1682 default:
1683 BUG();
1684 }
1685 }
1686
1687 static void free_gcr3_tbl_level1(u64 *tbl)
1688 {
1689 u64 *ptr;
1690 int i;
1691
1692 for (i = 0; i < 512; ++i) {
1693 if (!(tbl[i] & GCR3_VALID))
1694 continue;
1695
1696 ptr = __va(tbl[i] & PAGE_MASK);
1697
1698 free_page((unsigned long)ptr);
1699 }
1700 }
1701
1702 static void free_gcr3_tbl_level2(u64 *tbl)
1703 {
1704 u64 *ptr;
1705 int i;
1706
1707 for (i = 0; i < 512; ++i) {
1708 if (!(tbl[i] & GCR3_VALID))
1709 continue;
1710
1711 ptr = __va(tbl[i] & PAGE_MASK);
1712
1713 free_gcr3_tbl_level1(ptr);
1714 }
1715 }
1716
1717 static void free_gcr3_table(struct protection_domain *domain)
1718 {
1719 if (domain->glx == 2)
1720 free_gcr3_tbl_level2(domain->gcr3_tbl);
1721 else if (domain->glx == 1)
1722 free_gcr3_tbl_level1(domain->gcr3_tbl);
1723 else
1724 BUG_ON(domain->glx != 0);
1725
1726 free_page((unsigned long)domain->gcr3_tbl);
1727 }
1728
1729 /*
1730 * Free a domain, only used if something went wrong in the
1731 * allocation path and we need to free an already allocated page table
1732 */
1733 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1734 {
1735 if (!dom)
1736 return;
1737
1738 del_domain_from_list(&dom->domain);
1739
1740 put_iova_domain(&dom->iovad);
1741
1742 free_pagetable(&dom->domain);
1743
1744 kfree(dom);
1745 }
1746
1747 /*
1748 * Allocates a new protection domain usable for the dma_ops functions.
1749 * It also initializes the page table and the address allocator data
1750 * structures required for the dma_ops interface
1751 */
1752 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1753 {
1754 struct dma_ops_domain *dma_dom;
1755
1756 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1757 if (!dma_dom)
1758 return NULL;
1759
1760 if (protection_domain_init(&dma_dom->domain))
1761 goto free_dma_dom;
1762
1763 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1764 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1765 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1766 if (!dma_dom->domain.pt_root)
1767 goto free_dma_dom;
1768
1769 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1770 IOVA_START_PFN, DMA_32BIT_PFN);
1771
1772 /* Initialize reserved ranges */
1773 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1774
1775 add_domain_to_list(&dma_dom->domain);
1776
1777 return dma_dom;
1778
1779 free_dma_dom:
1780 dma_ops_domain_free(dma_dom);
1781
1782 return NULL;
1783 }
1784
1785 /*
1786 * little helper function to check whether a given protection domain is a
1787 * dma_ops domain
1788 */
1789 static bool dma_ops_domain(struct protection_domain *domain)
1790 {
1791 return domain->flags & PD_DMA_OPS_MASK;
1792 }
1793
1794 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1795 {
1796 u64 pte_root = 0;
1797 u64 flags = 0;
1798
1799 if (domain->mode != PAGE_MODE_NONE)
1800 pte_root = virt_to_phys(domain->pt_root);
1801
1802 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1803 << DEV_ENTRY_MODE_SHIFT;
1804 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1805
1806 flags = amd_iommu_dev_table[devid].data[1];
1807
1808 if (ats)
1809 flags |= DTE_FLAG_IOTLB;
1810
1811 if (domain->flags & PD_IOMMUV2_MASK) {
1812 u64 gcr3 = __pa(domain->gcr3_tbl);
1813 u64 glx = domain->glx;
1814 u64 tmp;
1815
1816 pte_root |= DTE_FLAG_GV;
1817 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1818
1819 /* First mask out possible old values for GCR3 table */
1820 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1821 flags &= ~tmp;
1822
1823 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1824 flags &= ~tmp;
1825
1826 /* Encode GCR3 table into DTE */
1827 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1828 pte_root |= tmp;
1829
1830 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1831 flags |= tmp;
1832
1833 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1834 flags |= tmp;
1835 }
1836
1837 flags &= ~(0xffffUL);
1838 flags |= domain->id;
1839
1840 amd_iommu_dev_table[devid].data[1] = flags;
1841 amd_iommu_dev_table[devid].data[0] = pte_root;
1842 }
1843
1844 static void clear_dte_entry(u16 devid)
1845 {
1846 /* remove entry from the device table seen by the hardware */
1847 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1848 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1849
1850 amd_iommu_apply_erratum_63(devid);
1851 }
1852
1853 static void do_attach(struct iommu_dev_data *dev_data,
1854 struct protection_domain *domain)
1855 {
1856 struct amd_iommu *iommu;
1857 u16 alias;
1858 bool ats;
1859
1860 iommu = amd_iommu_rlookup_table[dev_data->devid];
1861 alias = dev_data->alias;
1862 ats = dev_data->ats.enabled;
1863
1864 /* Update data structures */
1865 dev_data->domain = domain;
1866 list_add(&dev_data->list, &domain->dev_list);
1867
1868 /* Do reference counting */
1869 domain->dev_iommu[iommu->index] += 1;
1870 domain->dev_cnt += 1;
1871
1872 /* Update device table */
1873 set_dte_entry(dev_data->devid, domain, ats);
1874 if (alias != dev_data->devid)
1875 set_dte_entry(alias, domain, ats);
1876
1877 device_flush_dte(dev_data);
1878 }
1879
1880 static void do_detach(struct iommu_dev_data *dev_data)
1881 {
1882 struct amd_iommu *iommu;
1883 u16 alias;
1884
1885 /*
1886 * First check if the device is still attached. It might already
1887 * be detached from its domain because the generic
1888 * iommu_detach_group code detached it and we try again here in
1889 * our alias handling.
1890 */
1891 if (!dev_data->domain)
1892 return;
1893
1894 iommu = amd_iommu_rlookup_table[dev_data->devid];
1895 alias = dev_data->alias;
1896
1897 /* decrease reference counters */
1898 dev_data->domain->dev_iommu[iommu->index] -= 1;
1899 dev_data->domain->dev_cnt -= 1;
1900
1901 /* Update data structures */
1902 dev_data->domain = NULL;
1903 list_del(&dev_data->list);
1904 clear_dte_entry(dev_data->devid);
1905 if (alias != dev_data->devid)
1906 clear_dte_entry(alias);
1907
1908 /* Flush the DTE entry */
1909 device_flush_dte(dev_data);
1910 }
1911
1912 /*
1913 * If a device is not yet associated with a domain, this function does
1914 * assigns it visible for the hardware
1915 */
1916 static int __attach_device(struct iommu_dev_data *dev_data,
1917 struct protection_domain *domain)
1918 {
1919 int ret;
1920
1921 /*
1922 * Must be called with IRQs disabled. Warn here to detect early
1923 * when its not.
1924 */
1925 WARN_ON(!irqs_disabled());
1926
1927 /* lock domain */
1928 spin_lock(&domain->lock);
1929
1930 ret = -EBUSY;
1931 if (dev_data->domain != NULL)
1932 goto out_unlock;
1933
1934 /* Attach alias group root */
1935 do_attach(dev_data, domain);
1936
1937 ret = 0;
1938
1939 out_unlock:
1940
1941 /* ready */
1942 spin_unlock(&domain->lock);
1943
1944 return ret;
1945 }
1946
1947
1948 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1949 {
1950 pci_disable_ats(pdev);
1951 pci_disable_pri(pdev);
1952 pci_disable_pasid(pdev);
1953 }
1954
1955 /* FIXME: Change generic reset-function to do the same */
1956 static int pri_reset_while_enabled(struct pci_dev *pdev)
1957 {
1958 u16 control;
1959 int pos;
1960
1961 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1962 if (!pos)
1963 return -EINVAL;
1964
1965 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1966 control |= PCI_PRI_CTRL_RESET;
1967 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1968
1969 return 0;
1970 }
1971
1972 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1973 {
1974 bool reset_enable;
1975 int reqs, ret;
1976
1977 /* FIXME: Hardcode number of outstanding requests for now */
1978 reqs = 32;
1979 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1980 reqs = 1;
1981 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1982
1983 /* Only allow access to user-accessible pages */
1984 ret = pci_enable_pasid(pdev, 0);
1985 if (ret)
1986 goto out_err;
1987
1988 /* First reset the PRI state of the device */
1989 ret = pci_reset_pri(pdev);
1990 if (ret)
1991 goto out_err;
1992
1993 /* Enable PRI */
1994 ret = pci_enable_pri(pdev, reqs);
1995 if (ret)
1996 goto out_err;
1997
1998 if (reset_enable) {
1999 ret = pri_reset_while_enabled(pdev);
2000 if (ret)
2001 goto out_err;
2002 }
2003
2004 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2005 if (ret)
2006 goto out_err;
2007
2008 return 0;
2009
2010 out_err:
2011 pci_disable_pri(pdev);
2012 pci_disable_pasid(pdev);
2013
2014 return ret;
2015 }
2016
2017 /* FIXME: Move this to PCI code */
2018 #define PCI_PRI_TLP_OFF (1 << 15)
2019
2020 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2021 {
2022 u16 status;
2023 int pos;
2024
2025 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2026 if (!pos)
2027 return false;
2028
2029 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2030
2031 return (status & PCI_PRI_TLP_OFF) ? true : false;
2032 }
2033
2034 /*
2035 * If a device is not yet associated with a domain, this function
2036 * assigns it visible for the hardware
2037 */
2038 static int attach_device(struct device *dev,
2039 struct protection_domain *domain)
2040 {
2041 struct pci_dev *pdev;
2042 struct iommu_dev_data *dev_data;
2043 unsigned long flags;
2044 int ret;
2045
2046 dev_data = get_dev_data(dev);
2047
2048 if (!dev_is_pci(dev))
2049 goto skip_ats_check;
2050
2051 pdev = to_pci_dev(dev);
2052 if (domain->flags & PD_IOMMUV2_MASK) {
2053 if (!dev_data->passthrough)
2054 return -EINVAL;
2055
2056 if (dev_data->iommu_v2) {
2057 if (pdev_iommuv2_enable(pdev) != 0)
2058 return -EINVAL;
2059
2060 dev_data->ats.enabled = true;
2061 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2062 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2063 }
2064 } else if (amd_iommu_iotlb_sup &&
2065 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2066 dev_data->ats.enabled = true;
2067 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2068 }
2069
2070 skip_ats_check:
2071 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2072 ret = __attach_device(dev_data, domain);
2073 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2074
2075 /*
2076 * We might boot into a crash-kernel here. The crashed kernel
2077 * left the caches in the IOMMU dirty. So we have to flush
2078 * here to evict all dirty stuff.
2079 */
2080 domain_flush_tlb_pde(domain);
2081
2082 return ret;
2083 }
2084
2085 /*
2086 * Removes a device from a protection domain (unlocked)
2087 */
2088 static void __detach_device(struct iommu_dev_data *dev_data)
2089 {
2090 struct protection_domain *domain;
2091
2092 /*
2093 * Must be called with IRQs disabled. Warn here to detect early
2094 * when its not.
2095 */
2096 WARN_ON(!irqs_disabled());
2097
2098 if (WARN_ON(!dev_data->domain))
2099 return;
2100
2101 domain = dev_data->domain;
2102
2103 spin_lock(&domain->lock);
2104
2105 do_detach(dev_data);
2106
2107 spin_unlock(&domain->lock);
2108 }
2109
2110 /*
2111 * Removes a device from a protection domain (with devtable_lock held)
2112 */
2113 static void detach_device(struct device *dev)
2114 {
2115 struct protection_domain *domain;
2116 struct iommu_dev_data *dev_data;
2117 unsigned long flags;
2118
2119 dev_data = get_dev_data(dev);
2120 domain = dev_data->domain;
2121
2122 /* lock device table */
2123 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2124 __detach_device(dev_data);
2125 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2126
2127 if (!dev_is_pci(dev))
2128 return;
2129
2130 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2131 pdev_iommuv2_disable(to_pci_dev(dev));
2132 else if (dev_data->ats.enabled)
2133 pci_disable_ats(to_pci_dev(dev));
2134
2135 dev_data->ats.enabled = false;
2136 }
2137
2138 static int amd_iommu_add_device(struct device *dev)
2139 {
2140 struct iommu_dev_data *dev_data;
2141 struct iommu_domain *domain;
2142 struct amd_iommu *iommu;
2143 int ret, devid;
2144
2145 if (!check_device(dev) || get_dev_data(dev))
2146 return 0;
2147
2148 devid = get_device_id(dev);
2149 if (devid < 0)
2150 return devid;
2151
2152 iommu = amd_iommu_rlookup_table[devid];
2153
2154 ret = iommu_init_device(dev);
2155 if (ret) {
2156 if (ret != -ENOTSUPP)
2157 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2158 dev_name(dev));
2159
2160 iommu_ignore_device(dev);
2161 dev->archdata.dma_ops = &nommu_dma_ops;
2162 goto out;
2163 }
2164 init_iommu_group(dev);
2165
2166 dev_data = get_dev_data(dev);
2167
2168 BUG_ON(!dev_data);
2169
2170 if (iommu_pass_through || dev_data->iommu_v2)
2171 iommu_request_dm_for_dev(dev);
2172
2173 /* Domains are initialized for this device - have a look what we ended up with */
2174 domain = iommu_get_domain_for_dev(dev);
2175 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2176 dev_data->passthrough = true;
2177 else
2178 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2179
2180 out:
2181 iommu_completion_wait(iommu);
2182
2183 return 0;
2184 }
2185
2186 static void amd_iommu_remove_device(struct device *dev)
2187 {
2188 struct amd_iommu *iommu;
2189 int devid;
2190
2191 if (!check_device(dev))
2192 return;
2193
2194 devid = get_device_id(dev);
2195 if (devid < 0)
2196 return;
2197
2198 iommu = amd_iommu_rlookup_table[devid];
2199
2200 iommu_uninit_device(dev);
2201 iommu_completion_wait(iommu);
2202 }
2203
2204 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2205 {
2206 if (dev_is_pci(dev))
2207 return pci_device_group(dev);
2208
2209 return acpihid_device_group(dev);
2210 }
2211
2212 /*****************************************************************************
2213 *
2214 * The next functions belong to the dma_ops mapping/unmapping code.
2215 *
2216 *****************************************************************************/
2217
2218 static void __queue_flush(struct flush_queue *queue)
2219 {
2220 struct protection_domain *domain;
2221 unsigned long flags;
2222 int idx;
2223
2224 /* First flush TLB of all known domains */
2225 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
2226 list_for_each_entry(domain, &amd_iommu_pd_list, list)
2227 domain_flush_tlb(domain);
2228 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
2229
2230 /* Wait until flushes have completed */
2231 domain_flush_complete(NULL);
2232
2233 for (idx = 0; idx < queue->next; ++idx) {
2234 struct flush_queue_entry *entry;
2235
2236 entry = queue->entries + idx;
2237
2238 free_iova_fast(&entry->dma_dom->iovad,
2239 entry->iova_pfn,
2240 entry->pages);
2241
2242 /* Not really necessary, just to make sure we catch any bugs */
2243 entry->dma_dom = NULL;
2244 }
2245
2246 queue->next = 0;
2247 }
2248
2249 static void queue_flush_all(void)
2250 {
2251 int cpu;
2252
2253 for_each_possible_cpu(cpu) {
2254 struct flush_queue *queue;
2255 unsigned long flags;
2256
2257 queue = per_cpu_ptr(&flush_queue, cpu);
2258 spin_lock_irqsave(&queue->lock, flags);
2259 if (queue->next > 0)
2260 __queue_flush(queue);
2261 spin_unlock_irqrestore(&queue->lock, flags);
2262 }
2263 }
2264
2265 static void queue_flush_timeout(unsigned long unsused)
2266 {
2267 atomic_set(&queue_timer_on, 0);
2268 queue_flush_all();
2269 }
2270
2271 static void queue_add(struct dma_ops_domain *dma_dom,
2272 unsigned long address, unsigned long pages)
2273 {
2274 struct flush_queue_entry *entry;
2275 struct flush_queue *queue;
2276 unsigned long flags;
2277 int idx;
2278
2279 pages = __roundup_pow_of_two(pages);
2280 address >>= PAGE_SHIFT;
2281
2282 queue = get_cpu_ptr(&flush_queue);
2283 spin_lock_irqsave(&queue->lock, flags);
2284
2285 if (queue->next == FLUSH_QUEUE_SIZE)
2286 __queue_flush(queue);
2287
2288 idx = queue->next++;
2289 entry = queue->entries + idx;
2290
2291 entry->iova_pfn = address;
2292 entry->pages = pages;
2293 entry->dma_dom = dma_dom;
2294
2295 spin_unlock_irqrestore(&queue->lock, flags);
2296
2297 if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0)
2298 mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10));
2299
2300 put_cpu_ptr(&flush_queue);
2301 }
2302
2303
2304 /*
2305 * In the dma_ops path we only have the struct device. This function
2306 * finds the corresponding IOMMU, the protection domain and the
2307 * requestor id for a given device.
2308 * If the device is not yet associated with a domain this is also done
2309 * in this function.
2310 */
2311 static struct protection_domain *get_domain(struct device *dev)
2312 {
2313 struct protection_domain *domain;
2314
2315 if (!check_device(dev))
2316 return ERR_PTR(-EINVAL);
2317
2318 domain = get_dev_data(dev)->domain;
2319 if (!dma_ops_domain(domain))
2320 return ERR_PTR(-EBUSY);
2321
2322 return domain;
2323 }
2324
2325 static void update_device_table(struct protection_domain *domain)
2326 {
2327 struct iommu_dev_data *dev_data;
2328
2329 list_for_each_entry(dev_data, &domain->dev_list, list) {
2330 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2331
2332 if (dev_data->devid == dev_data->alias)
2333 continue;
2334
2335 /* There is an alias, update device table entry for it */
2336 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
2337 }
2338 }
2339
2340 static void update_domain(struct protection_domain *domain)
2341 {
2342 if (!domain->updated)
2343 return;
2344
2345 update_device_table(domain);
2346
2347 domain_flush_devices(domain);
2348 domain_flush_tlb_pde(domain);
2349
2350 domain->updated = false;
2351 }
2352
2353 static int dir2prot(enum dma_data_direction direction)
2354 {
2355 if (direction == DMA_TO_DEVICE)
2356 return IOMMU_PROT_IR;
2357 else if (direction == DMA_FROM_DEVICE)
2358 return IOMMU_PROT_IW;
2359 else if (direction == DMA_BIDIRECTIONAL)
2360 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2361 else
2362 return 0;
2363 }
2364 /*
2365 * This function contains common code for mapping of a physically
2366 * contiguous memory region into DMA address space. It is used by all
2367 * mapping functions provided with this IOMMU driver.
2368 * Must be called with the domain lock held.
2369 */
2370 static dma_addr_t __map_single(struct device *dev,
2371 struct dma_ops_domain *dma_dom,
2372 phys_addr_t paddr,
2373 size_t size,
2374 enum dma_data_direction direction,
2375 u64 dma_mask)
2376 {
2377 dma_addr_t offset = paddr & ~PAGE_MASK;
2378 dma_addr_t address, start, ret;
2379 unsigned int pages;
2380 int prot = 0;
2381 int i;
2382
2383 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2384 paddr &= PAGE_MASK;
2385
2386 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2387 if (address == DMA_ERROR_CODE)
2388 goto out;
2389
2390 prot = dir2prot(direction);
2391
2392 start = address;
2393 for (i = 0; i < pages; ++i) {
2394 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2395 PAGE_SIZE, prot, GFP_ATOMIC);
2396 if (ret)
2397 goto out_unmap;
2398
2399 paddr += PAGE_SIZE;
2400 start += PAGE_SIZE;
2401 }
2402 address += offset;
2403
2404 if (unlikely(amd_iommu_np_cache)) {
2405 domain_flush_pages(&dma_dom->domain, address, size);
2406 domain_flush_complete(&dma_dom->domain);
2407 }
2408
2409 out:
2410 return address;
2411
2412 out_unmap:
2413
2414 for (--i; i >= 0; --i) {
2415 start -= PAGE_SIZE;
2416 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2417 }
2418
2419 domain_flush_tlb(&dma_dom->domain);
2420 domain_flush_complete(&dma_dom->domain);
2421
2422 dma_ops_free_iova(dma_dom, address, pages);
2423
2424 return DMA_ERROR_CODE;
2425 }
2426
2427 /*
2428 * Does the reverse of the __map_single function. Must be called with
2429 * the domain lock held too
2430 */
2431 static void __unmap_single(struct dma_ops_domain *dma_dom,
2432 dma_addr_t dma_addr,
2433 size_t size,
2434 int dir)
2435 {
2436 dma_addr_t flush_addr;
2437 dma_addr_t i, start;
2438 unsigned int pages;
2439
2440 flush_addr = dma_addr;
2441 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2442 dma_addr &= PAGE_MASK;
2443 start = dma_addr;
2444
2445 for (i = 0; i < pages; ++i) {
2446 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2447 start += PAGE_SIZE;
2448 }
2449
2450 if (amd_iommu_unmap_flush) {
2451 dma_ops_free_iova(dma_dom, dma_addr, pages);
2452 domain_flush_tlb(&dma_dom->domain);
2453 domain_flush_complete(&dma_dom->domain);
2454 } else {
2455 queue_add(dma_dom, dma_addr, pages);
2456 }
2457 }
2458
2459 /*
2460 * The exported map_single function for dma_ops.
2461 */
2462 static dma_addr_t map_page(struct device *dev, struct page *page,
2463 unsigned long offset, size_t size,
2464 enum dma_data_direction dir,
2465 unsigned long attrs)
2466 {
2467 phys_addr_t paddr = page_to_phys(page) + offset;
2468 struct protection_domain *domain;
2469 struct dma_ops_domain *dma_dom;
2470 u64 dma_mask;
2471
2472 domain = get_domain(dev);
2473 if (PTR_ERR(domain) == -EINVAL)
2474 return (dma_addr_t)paddr;
2475 else if (IS_ERR(domain))
2476 return DMA_ERROR_CODE;
2477
2478 dma_mask = *dev->dma_mask;
2479 dma_dom = to_dma_ops_domain(domain);
2480
2481 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2482 }
2483
2484 /*
2485 * The exported unmap_single function for dma_ops.
2486 */
2487 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2488 enum dma_data_direction dir, unsigned long attrs)
2489 {
2490 struct protection_domain *domain;
2491 struct dma_ops_domain *dma_dom;
2492
2493 domain = get_domain(dev);
2494 if (IS_ERR(domain))
2495 return;
2496
2497 dma_dom = to_dma_ops_domain(domain);
2498
2499 __unmap_single(dma_dom, dma_addr, size, dir);
2500 }
2501
2502 static int sg_num_pages(struct device *dev,
2503 struct scatterlist *sglist,
2504 int nelems)
2505 {
2506 unsigned long mask, boundary_size;
2507 struct scatterlist *s;
2508 int i, npages = 0;
2509
2510 mask = dma_get_seg_boundary(dev);
2511 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2512 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2513
2514 for_each_sg(sglist, s, nelems, i) {
2515 int p, n;
2516
2517 s->dma_address = npages << PAGE_SHIFT;
2518 p = npages % boundary_size;
2519 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2520 if (p + n > boundary_size)
2521 npages += boundary_size - p;
2522 npages += n;
2523 }
2524
2525 return npages;
2526 }
2527
2528 /*
2529 * The exported map_sg function for dma_ops (handles scatter-gather
2530 * lists).
2531 */
2532 static int map_sg(struct device *dev, struct scatterlist *sglist,
2533 int nelems, enum dma_data_direction direction,
2534 unsigned long attrs)
2535 {
2536 int mapped_pages = 0, npages = 0, prot = 0, i;
2537 struct protection_domain *domain;
2538 struct dma_ops_domain *dma_dom;
2539 struct scatterlist *s;
2540 unsigned long address;
2541 u64 dma_mask;
2542
2543 domain = get_domain(dev);
2544 if (IS_ERR(domain))
2545 return 0;
2546
2547 dma_dom = to_dma_ops_domain(domain);
2548 dma_mask = *dev->dma_mask;
2549
2550 npages = sg_num_pages(dev, sglist, nelems);
2551
2552 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2553 if (address == DMA_ERROR_CODE)
2554 goto out_err;
2555
2556 prot = dir2prot(direction);
2557
2558 /* Map all sg entries */
2559 for_each_sg(sglist, s, nelems, i) {
2560 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2561
2562 for (j = 0; j < pages; ++j) {
2563 unsigned long bus_addr, phys_addr;
2564 int ret;
2565
2566 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2567 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2568 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2569 if (ret)
2570 goto out_unmap;
2571
2572 mapped_pages += 1;
2573 }
2574 }
2575
2576 /* Everything is mapped - write the right values into s->dma_address */
2577 for_each_sg(sglist, s, nelems, i) {
2578 s->dma_address += address + s->offset;
2579 s->dma_length = s->length;
2580 }
2581
2582 return nelems;
2583
2584 out_unmap:
2585 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2586 dev_name(dev), npages);
2587
2588 for_each_sg(sglist, s, nelems, i) {
2589 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2590
2591 for (j = 0; j < pages; ++j) {
2592 unsigned long bus_addr;
2593
2594 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2595 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2596
2597 if (--mapped_pages)
2598 goto out_free_iova;
2599 }
2600 }
2601
2602 out_free_iova:
2603 free_iova_fast(&dma_dom->iovad, address, npages);
2604
2605 out_err:
2606 return 0;
2607 }
2608
2609 /*
2610 * The exported map_sg function for dma_ops (handles scatter-gather
2611 * lists).
2612 */
2613 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2614 int nelems, enum dma_data_direction dir,
2615 unsigned long attrs)
2616 {
2617 struct protection_domain *domain;
2618 struct dma_ops_domain *dma_dom;
2619 unsigned long startaddr;
2620 int npages = 2;
2621
2622 domain = get_domain(dev);
2623 if (IS_ERR(domain))
2624 return;
2625
2626 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2627 dma_dom = to_dma_ops_domain(domain);
2628 npages = sg_num_pages(dev, sglist, nelems);
2629
2630 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2631 }
2632
2633 /*
2634 * The exported alloc_coherent function for dma_ops.
2635 */
2636 static void *alloc_coherent(struct device *dev, size_t size,
2637 dma_addr_t *dma_addr, gfp_t flag,
2638 unsigned long attrs)
2639 {
2640 u64 dma_mask = dev->coherent_dma_mask;
2641 struct protection_domain *domain;
2642 struct dma_ops_domain *dma_dom;
2643 struct page *page;
2644
2645 domain = get_domain(dev);
2646 if (PTR_ERR(domain) == -EINVAL) {
2647 page = alloc_pages(flag, get_order(size));
2648 *dma_addr = page_to_phys(page);
2649 return page_address(page);
2650 } else if (IS_ERR(domain))
2651 return NULL;
2652
2653 dma_dom = to_dma_ops_domain(domain);
2654 size = PAGE_ALIGN(size);
2655 dma_mask = dev->coherent_dma_mask;
2656 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2657 flag |= __GFP_ZERO;
2658
2659 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2660 if (!page) {
2661 if (!gfpflags_allow_blocking(flag))
2662 return NULL;
2663
2664 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2665 get_order(size));
2666 if (!page)
2667 return NULL;
2668 }
2669
2670 if (!dma_mask)
2671 dma_mask = *dev->dma_mask;
2672
2673 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2674 size, DMA_BIDIRECTIONAL, dma_mask);
2675
2676 if (*dma_addr == DMA_ERROR_CODE)
2677 goto out_free;
2678
2679 return page_address(page);
2680
2681 out_free:
2682
2683 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2684 __free_pages(page, get_order(size));
2685
2686 return NULL;
2687 }
2688
2689 /*
2690 * The exported free_coherent function for dma_ops.
2691 */
2692 static void free_coherent(struct device *dev, size_t size,
2693 void *virt_addr, dma_addr_t dma_addr,
2694 unsigned long attrs)
2695 {
2696 struct protection_domain *domain;
2697 struct dma_ops_domain *dma_dom;
2698 struct page *page;
2699
2700 page = virt_to_page(virt_addr);
2701 size = PAGE_ALIGN(size);
2702
2703 domain = get_domain(dev);
2704 if (IS_ERR(domain))
2705 goto free_mem;
2706
2707 dma_dom = to_dma_ops_domain(domain);
2708
2709 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2710
2711 free_mem:
2712 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2713 __free_pages(page, get_order(size));
2714 }
2715
2716 /*
2717 * This function is called by the DMA layer to find out if we can handle a
2718 * particular device. It is part of the dma_ops.
2719 */
2720 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2721 {
2722 return check_device(dev);
2723 }
2724
2725 static struct dma_map_ops amd_iommu_dma_ops = {
2726 .alloc = alloc_coherent,
2727 .free = free_coherent,
2728 .map_page = map_page,
2729 .unmap_page = unmap_page,
2730 .map_sg = map_sg,
2731 .unmap_sg = unmap_sg,
2732 .dma_supported = amd_iommu_dma_supported,
2733 };
2734
2735 static int init_reserved_iova_ranges(void)
2736 {
2737 struct pci_dev *pdev = NULL;
2738 struct iova *val;
2739
2740 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2741 IOVA_START_PFN, DMA_32BIT_PFN);
2742
2743 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2744 &reserved_rbtree_key);
2745
2746 /* MSI memory range */
2747 val = reserve_iova(&reserved_iova_ranges,
2748 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2749 if (!val) {
2750 pr_err("Reserving MSI range failed\n");
2751 return -ENOMEM;
2752 }
2753
2754 /* HT memory range */
2755 val = reserve_iova(&reserved_iova_ranges,
2756 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2757 if (!val) {
2758 pr_err("Reserving HT range failed\n");
2759 return -ENOMEM;
2760 }
2761
2762 /*
2763 * Memory used for PCI resources
2764 * FIXME: Check whether we can reserve the PCI-hole completly
2765 */
2766 for_each_pci_dev(pdev) {
2767 int i;
2768
2769 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2770 struct resource *r = &pdev->resource[i];
2771
2772 if (!(r->flags & IORESOURCE_MEM))
2773 continue;
2774
2775 val = reserve_iova(&reserved_iova_ranges,
2776 IOVA_PFN(r->start),
2777 IOVA_PFN(r->end));
2778 if (!val) {
2779 pr_err("Reserve pci-resource range failed\n");
2780 return -ENOMEM;
2781 }
2782 }
2783 }
2784
2785 return 0;
2786 }
2787
2788 int __init amd_iommu_init_api(void)
2789 {
2790 int ret, cpu, err = 0;
2791
2792 ret = iova_cache_get();
2793 if (ret)
2794 return ret;
2795
2796 ret = init_reserved_iova_ranges();
2797 if (ret)
2798 return ret;
2799
2800 for_each_possible_cpu(cpu) {
2801 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2802
2803 queue->entries = kzalloc(FLUSH_QUEUE_SIZE *
2804 sizeof(*queue->entries),
2805 GFP_KERNEL);
2806 if (!queue->entries)
2807 goto out_put_iova;
2808
2809 spin_lock_init(&queue->lock);
2810 }
2811
2812 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2813 if (err)
2814 return err;
2815 #ifdef CONFIG_ARM_AMBA
2816 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2817 if (err)
2818 return err;
2819 #endif
2820 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2821 if (err)
2822 return err;
2823 return 0;
2824
2825 out_put_iova:
2826 for_each_possible_cpu(cpu) {
2827 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2828
2829 kfree(queue->entries);
2830 }
2831
2832 return -ENOMEM;
2833 }
2834
2835 int __init amd_iommu_init_dma_ops(void)
2836 {
2837 setup_timer(&queue_timer, queue_flush_timeout, 0);
2838 atomic_set(&queue_timer_on, 0);
2839
2840 swiotlb = iommu_pass_through ? 1 : 0;
2841 iommu_detected = 1;
2842
2843 /*
2844 * In case we don't initialize SWIOTLB (actually the common case
2845 * when AMD IOMMU is enabled), make sure there are global
2846 * dma_ops set as a fall-back for devices not handled by this
2847 * driver (for example non-PCI devices).
2848 */
2849 if (!swiotlb)
2850 dma_ops = &nommu_dma_ops;
2851
2852 if (amd_iommu_unmap_flush)
2853 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2854 else
2855 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2856
2857 return 0;
2858
2859 }
2860
2861 /*****************************************************************************
2862 *
2863 * The following functions belong to the exported interface of AMD IOMMU
2864 *
2865 * This interface allows access to lower level functions of the IOMMU
2866 * like protection domain handling and assignement of devices to domains
2867 * which is not possible with the dma_ops interface.
2868 *
2869 *****************************************************************************/
2870
2871 static void cleanup_domain(struct protection_domain *domain)
2872 {
2873 struct iommu_dev_data *entry;
2874 unsigned long flags;
2875
2876 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2877
2878 while (!list_empty(&domain->dev_list)) {
2879 entry = list_first_entry(&domain->dev_list,
2880 struct iommu_dev_data, list);
2881 __detach_device(entry);
2882 }
2883
2884 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2885 }
2886
2887 static void protection_domain_free(struct protection_domain *domain)
2888 {
2889 if (!domain)
2890 return;
2891
2892 del_domain_from_list(domain);
2893
2894 if (domain->id)
2895 domain_id_free(domain->id);
2896
2897 kfree(domain);
2898 }
2899
2900 static int protection_domain_init(struct protection_domain *domain)
2901 {
2902 spin_lock_init(&domain->lock);
2903 mutex_init(&domain->api_lock);
2904 domain->id = domain_id_alloc();
2905 if (!domain->id)
2906 return -ENOMEM;
2907 INIT_LIST_HEAD(&domain->dev_list);
2908
2909 return 0;
2910 }
2911
2912 static struct protection_domain *protection_domain_alloc(void)
2913 {
2914 struct protection_domain *domain;
2915
2916 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2917 if (!domain)
2918 return NULL;
2919
2920 if (protection_domain_init(domain))
2921 goto out_err;
2922
2923 add_domain_to_list(domain);
2924
2925 return domain;
2926
2927 out_err:
2928 kfree(domain);
2929
2930 return NULL;
2931 }
2932
2933 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2934 {
2935 struct protection_domain *pdomain;
2936 struct dma_ops_domain *dma_domain;
2937
2938 switch (type) {
2939 case IOMMU_DOMAIN_UNMANAGED:
2940 pdomain = protection_domain_alloc();
2941 if (!pdomain)
2942 return NULL;
2943
2944 pdomain->mode = PAGE_MODE_3_LEVEL;
2945 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2946 if (!pdomain->pt_root) {
2947 protection_domain_free(pdomain);
2948 return NULL;
2949 }
2950
2951 pdomain->domain.geometry.aperture_start = 0;
2952 pdomain->domain.geometry.aperture_end = ~0ULL;
2953 pdomain->domain.geometry.force_aperture = true;
2954
2955 break;
2956 case IOMMU_DOMAIN_DMA:
2957 dma_domain = dma_ops_domain_alloc();
2958 if (!dma_domain) {
2959 pr_err("AMD-Vi: Failed to allocate\n");
2960 return NULL;
2961 }
2962 pdomain = &dma_domain->domain;
2963 break;
2964 case IOMMU_DOMAIN_IDENTITY:
2965 pdomain = protection_domain_alloc();
2966 if (!pdomain)
2967 return NULL;
2968
2969 pdomain->mode = PAGE_MODE_NONE;
2970 break;
2971 default:
2972 return NULL;
2973 }
2974
2975 return &pdomain->domain;
2976 }
2977
2978 static void amd_iommu_domain_free(struct iommu_domain *dom)
2979 {
2980 struct protection_domain *domain;
2981 struct dma_ops_domain *dma_dom;
2982
2983 domain = to_pdomain(dom);
2984
2985 if (domain->dev_cnt > 0)
2986 cleanup_domain(domain);
2987
2988 BUG_ON(domain->dev_cnt != 0);
2989
2990 if (!dom)
2991 return;
2992
2993 switch (dom->type) {
2994 case IOMMU_DOMAIN_DMA:
2995 /*
2996 * First make sure the domain is no longer referenced from the
2997 * flush queue
2998 */
2999 queue_flush_all();
3000
3001 /* Now release the domain */
3002 dma_dom = to_dma_ops_domain(domain);
3003 dma_ops_domain_free(dma_dom);
3004 break;
3005 default:
3006 if (domain->mode != PAGE_MODE_NONE)
3007 free_pagetable(domain);
3008
3009 if (domain->flags & PD_IOMMUV2_MASK)
3010 free_gcr3_table(domain);
3011
3012 protection_domain_free(domain);
3013 break;
3014 }
3015 }
3016
3017 static void amd_iommu_detach_device(struct iommu_domain *dom,
3018 struct device *dev)
3019 {
3020 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3021 struct amd_iommu *iommu;
3022 int devid;
3023
3024 if (!check_device(dev))
3025 return;
3026
3027 devid = get_device_id(dev);
3028 if (devid < 0)
3029 return;
3030
3031 if (dev_data->domain != NULL)
3032 detach_device(dev);
3033
3034 iommu = amd_iommu_rlookup_table[devid];
3035 if (!iommu)
3036 return;
3037
3038 #ifdef CONFIG_IRQ_REMAP
3039 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3040 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3041 dev_data->use_vapic = 0;
3042 #endif
3043
3044 iommu_completion_wait(iommu);
3045 }
3046
3047 static int amd_iommu_attach_device(struct iommu_domain *dom,
3048 struct device *dev)
3049 {
3050 struct protection_domain *domain = to_pdomain(dom);
3051 struct iommu_dev_data *dev_data;
3052 struct amd_iommu *iommu;
3053 int ret;
3054
3055 if (!check_device(dev))
3056 return -EINVAL;
3057
3058 dev_data = dev->archdata.iommu;
3059
3060 iommu = amd_iommu_rlookup_table[dev_data->devid];
3061 if (!iommu)
3062 return -EINVAL;
3063
3064 if (dev_data->domain)
3065 detach_device(dev);
3066
3067 ret = attach_device(dev, domain);
3068
3069 #ifdef CONFIG_IRQ_REMAP
3070 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3071 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3072 dev_data->use_vapic = 1;
3073 else
3074 dev_data->use_vapic = 0;
3075 }
3076 #endif
3077
3078 iommu_completion_wait(iommu);
3079
3080 return ret;
3081 }
3082
3083 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3084 phys_addr_t paddr, size_t page_size, int iommu_prot)
3085 {
3086 struct protection_domain *domain = to_pdomain(dom);
3087 int prot = 0;
3088 int ret;
3089
3090 if (domain->mode == PAGE_MODE_NONE)
3091 return -EINVAL;
3092
3093 if (iommu_prot & IOMMU_READ)
3094 prot |= IOMMU_PROT_IR;
3095 if (iommu_prot & IOMMU_WRITE)
3096 prot |= IOMMU_PROT_IW;
3097
3098 mutex_lock(&domain->api_lock);
3099 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3100 mutex_unlock(&domain->api_lock);
3101
3102 return ret;
3103 }
3104
3105 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3106 size_t page_size)
3107 {
3108 struct protection_domain *domain = to_pdomain(dom);
3109 size_t unmap_size;
3110
3111 if (domain->mode == PAGE_MODE_NONE)
3112 return -EINVAL;
3113
3114 mutex_lock(&domain->api_lock);
3115 unmap_size = iommu_unmap_page(domain, iova, page_size);
3116 mutex_unlock(&domain->api_lock);
3117
3118 domain_flush_tlb_pde(domain);
3119
3120 return unmap_size;
3121 }
3122
3123 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3124 dma_addr_t iova)
3125 {
3126 struct protection_domain *domain = to_pdomain(dom);
3127 unsigned long offset_mask, pte_pgsize;
3128 u64 *pte, __pte;
3129
3130 if (domain->mode == PAGE_MODE_NONE)
3131 return iova;
3132
3133 pte = fetch_pte(domain, iova, &pte_pgsize);
3134
3135 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3136 return 0;
3137
3138 offset_mask = pte_pgsize - 1;
3139 __pte = *pte & PM_ADDR_MASK;
3140
3141 return (__pte & ~offset_mask) | (iova & offset_mask);
3142 }
3143
3144 static bool amd_iommu_capable(enum iommu_cap cap)
3145 {
3146 switch (cap) {
3147 case IOMMU_CAP_CACHE_COHERENCY:
3148 return true;
3149 case IOMMU_CAP_INTR_REMAP:
3150 return (irq_remapping_enabled == 1);
3151 case IOMMU_CAP_NOEXEC:
3152 return false;
3153 }
3154
3155 return false;
3156 }
3157
3158 static void amd_iommu_get_dm_regions(struct device *dev,
3159 struct list_head *head)
3160 {
3161 struct unity_map_entry *entry;
3162 int devid;
3163
3164 devid = get_device_id(dev);
3165 if (devid < 0)
3166 return;
3167
3168 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3169 struct iommu_dm_region *region;
3170
3171 if (devid < entry->devid_start || devid > entry->devid_end)
3172 continue;
3173
3174 region = kzalloc(sizeof(*region), GFP_KERNEL);
3175 if (!region) {
3176 pr_err("Out of memory allocating dm-regions for %s\n",
3177 dev_name(dev));
3178 return;
3179 }
3180
3181 region->start = entry->address_start;
3182 region->length = entry->address_end - entry->address_start;
3183 if (entry->prot & IOMMU_PROT_IR)
3184 region->prot |= IOMMU_READ;
3185 if (entry->prot & IOMMU_PROT_IW)
3186 region->prot |= IOMMU_WRITE;
3187
3188 list_add_tail(&region->list, head);
3189 }
3190 }
3191
3192 static void amd_iommu_put_dm_regions(struct device *dev,
3193 struct list_head *head)
3194 {
3195 struct iommu_dm_region *entry, *next;
3196
3197 list_for_each_entry_safe(entry, next, head, list)
3198 kfree(entry);
3199 }
3200
3201 static void amd_iommu_apply_dm_region(struct device *dev,
3202 struct iommu_domain *domain,
3203 struct iommu_dm_region *region)
3204 {
3205 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3206 unsigned long start, end;
3207
3208 start = IOVA_PFN(region->start);
3209 end = IOVA_PFN(region->start + region->length);
3210
3211 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3212 }
3213
3214 static const struct iommu_ops amd_iommu_ops = {
3215 .capable = amd_iommu_capable,
3216 .domain_alloc = amd_iommu_domain_alloc,
3217 .domain_free = amd_iommu_domain_free,
3218 .attach_dev = amd_iommu_attach_device,
3219 .detach_dev = amd_iommu_detach_device,
3220 .map = amd_iommu_map,
3221 .unmap = amd_iommu_unmap,
3222 .map_sg = default_iommu_map_sg,
3223 .iova_to_phys = amd_iommu_iova_to_phys,
3224 .add_device = amd_iommu_add_device,
3225 .remove_device = amd_iommu_remove_device,
3226 .device_group = amd_iommu_device_group,
3227 .get_dm_regions = amd_iommu_get_dm_regions,
3228 .put_dm_regions = amd_iommu_put_dm_regions,
3229 .apply_dm_region = amd_iommu_apply_dm_region,
3230 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3231 };
3232
3233 /*****************************************************************************
3234 *
3235 * The next functions do a basic initialization of IOMMU for pass through
3236 * mode
3237 *
3238 * In passthrough mode the IOMMU is initialized and enabled but not used for
3239 * DMA-API translation.
3240 *
3241 *****************************************************************************/
3242
3243 /* IOMMUv2 specific functions */
3244 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3245 {
3246 return atomic_notifier_chain_register(&ppr_notifier, nb);
3247 }
3248 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3249
3250 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3251 {
3252 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3253 }
3254 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3255
3256 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3257 {
3258 struct protection_domain *domain = to_pdomain(dom);
3259 unsigned long flags;
3260
3261 spin_lock_irqsave(&domain->lock, flags);
3262
3263 /* Update data structure */
3264 domain->mode = PAGE_MODE_NONE;
3265 domain->updated = true;
3266
3267 /* Make changes visible to IOMMUs */
3268 update_domain(domain);
3269
3270 /* Page-table is not visible to IOMMU anymore, so free it */
3271 free_pagetable(domain);
3272
3273 spin_unlock_irqrestore(&domain->lock, flags);
3274 }
3275 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3276
3277 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3278 {
3279 struct protection_domain *domain = to_pdomain(dom);
3280 unsigned long flags;
3281 int levels, ret;
3282
3283 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3284 return -EINVAL;
3285
3286 /* Number of GCR3 table levels required */
3287 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3288 levels += 1;
3289
3290 if (levels > amd_iommu_max_glx_val)
3291 return -EINVAL;
3292
3293 spin_lock_irqsave(&domain->lock, flags);
3294
3295 /*
3296 * Save us all sanity checks whether devices already in the
3297 * domain support IOMMUv2. Just force that the domain has no
3298 * devices attached when it is switched into IOMMUv2 mode.
3299 */
3300 ret = -EBUSY;
3301 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3302 goto out;
3303
3304 ret = -ENOMEM;
3305 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3306 if (domain->gcr3_tbl == NULL)
3307 goto out;
3308
3309 domain->glx = levels;
3310 domain->flags |= PD_IOMMUV2_MASK;
3311 domain->updated = true;
3312
3313 update_domain(domain);
3314
3315 ret = 0;
3316
3317 out:
3318 spin_unlock_irqrestore(&domain->lock, flags);
3319
3320 return ret;
3321 }
3322 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3323
3324 static int __flush_pasid(struct protection_domain *domain, int pasid,
3325 u64 address, bool size)
3326 {
3327 struct iommu_dev_data *dev_data;
3328 struct iommu_cmd cmd;
3329 int i, ret;
3330
3331 if (!(domain->flags & PD_IOMMUV2_MASK))
3332 return -EINVAL;
3333
3334 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3335
3336 /*
3337 * IOMMU TLB needs to be flushed before Device TLB to
3338 * prevent device TLB refill from IOMMU TLB
3339 */
3340 for (i = 0; i < amd_iommus_present; ++i) {
3341 if (domain->dev_iommu[i] == 0)
3342 continue;
3343
3344 ret = iommu_queue_command(amd_iommus[i], &cmd);
3345 if (ret != 0)
3346 goto out;
3347 }
3348
3349 /* Wait until IOMMU TLB flushes are complete */
3350 domain_flush_complete(domain);
3351
3352 /* Now flush device TLBs */
3353 list_for_each_entry(dev_data, &domain->dev_list, list) {
3354 struct amd_iommu *iommu;
3355 int qdep;
3356
3357 /*
3358 There might be non-IOMMUv2 capable devices in an IOMMUv2
3359 * domain.
3360 */
3361 if (!dev_data->ats.enabled)
3362 continue;
3363
3364 qdep = dev_data->ats.qdep;
3365 iommu = amd_iommu_rlookup_table[dev_data->devid];
3366
3367 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3368 qdep, address, size);
3369
3370 ret = iommu_queue_command(iommu, &cmd);
3371 if (ret != 0)
3372 goto out;
3373 }
3374
3375 /* Wait until all device TLBs are flushed */
3376 domain_flush_complete(domain);
3377
3378 ret = 0;
3379
3380 out:
3381
3382 return ret;
3383 }
3384
3385 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3386 u64 address)
3387 {
3388 return __flush_pasid(domain, pasid, address, false);
3389 }
3390
3391 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3392 u64 address)
3393 {
3394 struct protection_domain *domain = to_pdomain(dom);
3395 unsigned long flags;
3396 int ret;
3397
3398 spin_lock_irqsave(&domain->lock, flags);
3399 ret = __amd_iommu_flush_page(domain, pasid, address);
3400 spin_unlock_irqrestore(&domain->lock, flags);
3401
3402 return ret;
3403 }
3404 EXPORT_SYMBOL(amd_iommu_flush_page);
3405
3406 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3407 {
3408 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3409 true);
3410 }
3411
3412 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3413 {
3414 struct protection_domain *domain = to_pdomain(dom);
3415 unsigned long flags;
3416 int ret;
3417
3418 spin_lock_irqsave(&domain->lock, flags);
3419 ret = __amd_iommu_flush_tlb(domain, pasid);
3420 spin_unlock_irqrestore(&domain->lock, flags);
3421
3422 return ret;
3423 }
3424 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3425
3426 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3427 {
3428 int index;
3429 u64 *pte;
3430
3431 while (true) {
3432
3433 index = (pasid >> (9 * level)) & 0x1ff;
3434 pte = &root[index];
3435
3436 if (level == 0)
3437 break;
3438
3439 if (!(*pte & GCR3_VALID)) {
3440 if (!alloc)
3441 return NULL;
3442
3443 root = (void *)get_zeroed_page(GFP_ATOMIC);
3444 if (root == NULL)
3445 return NULL;
3446
3447 *pte = __pa(root) | GCR3_VALID;
3448 }
3449
3450 root = __va(*pte & PAGE_MASK);
3451
3452 level -= 1;
3453 }
3454
3455 return pte;
3456 }
3457
3458 static int __set_gcr3(struct protection_domain *domain, int pasid,
3459 unsigned long cr3)
3460 {
3461 u64 *pte;
3462
3463 if (domain->mode != PAGE_MODE_NONE)
3464 return -EINVAL;
3465
3466 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3467 if (pte == NULL)
3468 return -ENOMEM;
3469
3470 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3471
3472 return __amd_iommu_flush_tlb(domain, pasid);
3473 }
3474
3475 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3476 {
3477 u64 *pte;
3478
3479 if (domain->mode != PAGE_MODE_NONE)
3480 return -EINVAL;
3481
3482 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3483 if (pte == NULL)
3484 return 0;
3485
3486 *pte = 0;
3487
3488 return __amd_iommu_flush_tlb(domain, pasid);
3489 }
3490
3491 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3492 unsigned long cr3)
3493 {
3494 struct protection_domain *domain = to_pdomain(dom);
3495 unsigned long flags;
3496 int ret;
3497
3498 spin_lock_irqsave(&domain->lock, flags);
3499 ret = __set_gcr3(domain, pasid, cr3);
3500 spin_unlock_irqrestore(&domain->lock, flags);
3501
3502 return ret;
3503 }
3504 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3505
3506 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3507 {
3508 struct protection_domain *domain = to_pdomain(dom);
3509 unsigned long flags;
3510 int ret;
3511
3512 spin_lock_irqsave(&domain->lock, flags);
3513 ret = __clear_gcr3(domain, pasid);
3514 spin_unlock_irqrestore(&domain->lock, flags);
3515
3516 return ret;
3517 }
3518 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3519
3520 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3521 int status, int tag)
3522 {
3523 struct iommu_dev_data *dev_data;
3524 struct amd_iommu *iommu;
3525 struct iommu_cmd cmd;
3526
3527 dev_data = get_dev_data(&pdev->dev);
3528 iommu = amd_iommu_rlookup_table[dev_data->devid];
3529
3530 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3531 tag, dev_data->pri_tlp);
3532
3533 return iommu_queue_command(iommu, &cmd);
3534 }
3535 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3536
3537 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3538 {
3539 struct protection_domain *pdomain;
3540
3541 pdomain = get_domain(&pdev->dev);
3542 if (IS_ERR(pdomain))
3543 return NULL;
3544
3545 /* Only return IOMMUv2 domains */
3546 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3547 return NULL;
3548
3549 return &pdomain->domain;
3550 }
3551 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3552
3553 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3554 {
3555 struct iommu_dev_data *dev_data;
3556
3557 if (!amd_iommu_v2_supported())
3558 return;
3559
3560 dev_data = get_dev_data(&pdev->dev);
3561 dev_data->errata |= (1 << erratum);
3562 }
3563 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3564
3565 int amd_iommu_device_info(struct pci_dev *pdev,
3566 struct amd_iommu_device_info *info)
3567 {
3568 int max_pasids;
3569 int pos;
3570
3571 if (pdev == NULL || info == NULL)
3572 return -EINVAL;
3573
3574 if (!amd_iommu_v2_supported())
3575 return -EINVAL;
3576
3577 memset(info, 0, sizeof(*info));
3578
3579 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3580 if (pos)
3581 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3582
3583 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3584 if (pos)
3585 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3586
3587 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3588 if (pos) {
3589 int features;
3590
3591 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3592 max_pasids = min(max_pasids, (1 << 20));
3593
3594 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3595 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3596
3597 features = pci_pasid_features(pdev);
3598 if (features & PCI_PASID_CAP_EXEC)
3599 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3600 if (features & PCI_PASID_CAP_PRIV)
3601 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3602 }
3603
3604 return 0;
3605 }
3606 EXPORT_SYMBOL(amd_iommu_device_info);
3607
3608 #ifdef CONFIG_IRQ_REMAP
3609
3610 /*****************************************************************************
3611 *
3612 * Interrupt Remapping Implementation
3613 *
3614 *****************************************************************************/
3615
3616 static struct irq_chip amd_ir_chip;
3617
3618 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3619 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3620 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3621 #define DTE_IRQ_REMAP_ENABLE 1ULL
3622
3623 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3624 {
3625 u64 dte;
3626
3627 dte = amd_iommu_dev_table[devid].data[2];
3628 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3629 dte |= virt_to_phys(table->table);
3630 dte |= DTE_IRQ_REMAP_INTCTL;
3631 dte |= DTE_IRQ_TABLE_LEN;
3632 dte |= DTE_IRQ_REMAP_ENABLE;
3633
3634 amd_iommu_dev_table[devid].data[2] = dte;
3635 }
3636
3637 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3638 {
3639 struct irq_remap_table *table = NULL;
3640 struct amd_iommu *iommu;
3641 unsigned long flags;
3642 u16 alias;
3643
3644 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3645
3646 iommu = amd_iommu_rlookup_table[devid];
3647 if (!iommu)
3648 goto out_unlock;
3649
3650 table = irq_lookup_table[devid];
3651 if (table)
3652 goto out;
3653
3654 alias = amd_iommu_alias_table[devid];
3655 table = irq_lookup_table[alias];
3656 if (table) {
3657 irq_lookup_table[devid] = table;
3658 set_dte_irq_entry(devid, table);
3659 iommu_flush_dte(iommu, devid);
3660 goto out;
3661 }
3662
3663 /* Nothing there yet, allocate new irq remapping table */
3664 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3665 if (!table)
3666 goto out;
3667
3668 /* Initialize table spin-lock */
3669 spin_lock_init(&table->lock);
3670
3671 if (ioapic)
3672 /* Keep the first 32 indexes free for IOAPIC interrupts */
3673 table->min_index = 32;
3674
3675 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3676 if (!table->table) {
3677 kfree(table);
3678 table = NULL;
3679 goto out;
3680 }
3681
3682 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3683 memset(table->table, 0,
3684 MAX_IRQS_PER_TABLE * sizeof(u32));
3685 else
3686 memset(table->table, 0,
3687 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3688
3689 if (ioapic) {
3690 int i;
3691
3692 for (i = 0; i < 32; ++i)
3693 iommu->irte_ops->set_allocated(table, i);
3694 }
3695
3696 irq_lookup_table[devid] = table;
3697 set_dte_irq_entry(devid, table);
3698 iommu_flush_dte(iommu, devid);
3699 if (devid != alias) {
3700 irq_lookup_table[alias] = table;
3701 set_dte_irq_entry(alias, table);
3702 iommu_flush_dte(iommu, alias);
3703 }
3704
3705 out:
3706 iommu_completion_wait(iommu);
3707
3708 out_unlock:
3709 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3710
3711 return table;
3712 }
3713
3714 static int alloc_irq_index(u16 devid, int count)
3715 {
3716 struct irq_remap_table *table;
3717 unsigned long flags;
3718 int index, c;
3719 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3720
3721 if (!iommu)
3722 return -ENODEV;
3723
3724 table = get_irq_table(devid, false);
3725 if (!table)
3726 return -ENODEV;
3727
3728 spin_lock_irqsave(&table->lock, flags);
3729
3730 /* Scan table for free entries */
3731 for (c = 0, index = table->min_index;
3732 index < MAX_IRQS_PER_TABLE;
3733 ++index) {
3734 if (!iommu->irte_ops->is_allocated(table, index))
3735 c += 1;
3736 else
3737 c = 0;
3738
3739 if (c == count) {
3740 for (; c != 0; --c)
3741 iommu->irte_ops->set_allocated(table, index - c + 1);
3742
3743 index -= count - 1;
3744 goto out;
3745 }
3746 }
3747
3748 index = -ENOSPC;
3749
3750 out:
3751 spin_unlock_irqrestore(&table->lock, flags);
3752
3753 return index;
3754 }
3755
3756 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3757 struct amd_ir_data *data)
3758 {
3759 struct irq_remap_table *table;
3760 struct amd_iommu *iommu;
3761 unsigned long flags;
3762 struct irte_ga *entry;
3763
3764 iommu = amd_iommu_rlookup_table[devid];
3765 if (iommu == NULL)
3766 return -EINVAL;
3767
3768 table = get_irq_table(devid, false);
3769 if (!table)
3770 return -ENOMEM;
3771
3772 spin_lock_irqsave(&table->lock, flags);
3773
3774 entry = (struct irte_ga *)table->table;
3775 entry = &entry[index];
3776 entry->lo.fields_remap.valid = 0;
3777 entry->hi.val = irte->hi.val;
3778 entry->lo.val = irte->lo.val;
3779 entry->lo.fields_remap.valid = 1;
3780 if (data)
3781 data->ref = entry;
3782
3783 spin_unlock_irqrestore(&table->lock, flags);
3784
3785 iommu_flush_irt(iommu, devid);
3786 iommu_completion_wait(iommu);
3787
3788 return 0;
3789 }
3790
3791 static int modify_irte(u16 devid, int index, union irte *irte)
3792 {
3793 struct irq_remap_table *table;
3794 struct amd_iommu *iommu;
3795 unsigned long flags;
3796
3797 iommu = amd_iommu_rlookup_table[devid];
3798 if (iommu == NULL)
3799 return -EINVAL;
3800
3801 table = get_irq_table(devid, false);
3802 if (!table)
3803 return -ENOMEM;
3804
3805 spin_lock_irqsave(&table->lock, flags);
3806 table->table[index] = irte->val;
3807 spin_unlock_irqrestore(&table->lock, flags);
3808
3809 iommu_flush_irt(iommu, devid);
3810 iommu_completion_wait(iommu);
3811
3812 return 0;
3813 }
3814
3815 static void free_irte(u16 devid, int index)
3816 {
3817 struct irq_remap_table *table;
3818 struct amd_iommu *iommu;
3819 unsigned long flags;
3820
3821 iommu = amd_iommu_rlookup_table[devid];
3822 if (iommu == NULL)
3823 return;
3824
3825 table = get_irq_table(devid, false);
3826 if (!table)
3827 return;
3828
3829 spin_lock_irqsave(&table->lock, flags);
3830 iommu->irte_ops->clear_allocated(table, index);
3831 spin_unlock_irqrestore(&table->lock, flags);
3832
3833 iommu_flush_irt(iommu, devid);
3834 iommu_completion_wait(iommu);
3835 }
3836
3837 static void irte_prepare(void *entry,
3838 u32 delivery_mode, u32 dest_mode,
3839 u8 vector, u32 dest_apicid, int devid)
3840 {
3841 union irte *irte = (union irte *) entry;
3842
3843 irte->val = 0;
3844 irte->fields.vector = vector;
3845 irte->fields.int_type = delivery_mode;
3846 irte->fields.destination = dest_apicid;
3847 irte->fields.dm = dest_mode;
3848 irte->fields.valid = 1;
3849 }
3850
3851 static void irte_ga_prepare(void *entry,
3852 u32 delivery_mode, u32 dest_mode,
3853 u8 vector, u32 dest_apicid, int devid)
3854 {
3855 struct irte_ga *irte = (struct irte_ga *) entry;
3856 struct iommu_dev_data *dev_data = search_dev_data(devid);
3857
3858 irte->lo.val = 0;
3859 irte->hi.val = 0;
3860 irte->lo.fields_remap.guest_mode = dev_data ? dev_data->use_vapic : 0;
3861 irte->lo.fields_remap.int_type = delivery_mode;
3862 irte->lo.fields_remap.dm = dest_mode;
3863 irte->hi.fields.vector = vector;
3864 irte->lo.fields_remap.destination = dest_apicid;
3865 irte->lo.fields_remap.valid = 1;
3866 }
3867
3868 static void irte_activate(void *entry, u16 devid, u16 index)
3869 {
3870 union irte *irte = (union irte *) entry;
3871
3872 irte->fields.valid = 1;
3873 modify_irte(devid, index, irte);
3874 }
3875
3876 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3877 {
3878 struct irte_ga *irte = (struct irte_ga *) entry;
3879
3880 irte->lo.fields_remap.valid = 1;
3881 modify_irte_ga(devid, index, irte, NULL);
3882 }
3883
3884 static void irte_deactivate(void *entry, u16 devid, u16 index)
3885 {
3886 union irte *irte = (union irte *) entry;
3887
3888 irte->fields.valid = 0;
3889 modify_irte(devid, index, irte);
3890 }
3891
3892 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3893 {
3894 struct irte_ga *irte = (struct irte_ga *) entry;
3895
3896 irte->lo.fields_remap.valid = 0;
3897 modify_irte_ga(devid, index, irte, NULL);
3898 }
3899
3900 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3901 u8 vector, u32 dest_apicid)
3902 {
3903 union irte *irte = (union irte *) entry;
3904
3905 irte->fields.vector = vector;
3906 irte->fields.destination = dest_apicid;
3907 modify_irte(devid, index, irte);
3908 }
3909
3910 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3911 u8 vector, u32 dest_apicid)
3912 {
3913 struct irte_ga *irte = (struct irte_ga *) entry;
3914 struct iommu_dev_data *dev_data = search_dev_data(devid);
3915
3916 if (!dev_data || !dev_data->use_vapic) {
3917 irte->hi.fields.vector = vector;
3918 irte->lo.fields_remap.destination = dest_apicid;
3919 irte->lo.fields_remap.guest_mode = 0;
3920 modify_irte_ga(devid, index, irte, NULL);
3921 }
3922 }
3923
3924 #define IRTE_ALLOCATED (~1U)
3925 static void irte_set_allocated(struct irq_remap_table *table, int index)
3926 {
3927 table->table[index] = IRTE_ALLOCATED;
3928 }
3929
3930 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3931 {
3932 struct irte_ga *ptr = (struct irte_ga *)table->table;
3933 struct irte_ga *irte = &ptr[index];
3934
3935 memset(&irte->lo.val, 0, sizeof(u64));
3936 memset(&irte->hi.val, 0, sizeof(u64));
3937 irte->hi.fields.vector = 0xff;
3938 }
3939
3940 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3941 {
3942 union irte *ptr = (union irte *)table->table;
3943 union irte *irte = &ptr[index];
3944
3945 return irte->val != 0;
3946 }
3947
3948 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3949 {
3950 struct irte_ga *ptr = (struct irte_ga *)table->table;
3951 struct irte_ga *irte = &ptr[index];
3952
3953 return irte->hi.fields.vector != 0;
3954 }
3955
3956 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3957 {
3958 table->table[index] = 0;
3959 }
3960
3961 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3962 {
3963 struct irte_ga *ptr = (struct irte_ga *)table->table;
3964 struct irte_ga *irte = &ptr[index];
3965
3966 memset(&irte->lo.val, 0, sizeof(u64));
3967 memset(&irte->hi.val, 0, sizeof(u64));
3968 }
3969
3970 static int get_devid(struct irq_alloc_info *info)
3971 {
3972 int devid = -1;
3973
3974 switch (info->type) {
3975 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3976 devid = get_ioapic_devid(info->ioapic_id);
3977 break;
3978 case X86_IRQ_ALLOC_TYPE_HPET:
3979 devid = get_hpet_devid(info->hpet_id);
3980 break;
3981 case X86_IRQ_ALLOC_TYPE_MSI:
3982 case X86_IRQ_ALLOC_TYPE_MSIX:
3983 devid = get_device_id(&info->msi_dev->dev);
3984 break;
3985 default:
3986 BUG_ON(1);
3987 break;
3988 }
3989
3990 return devid;
3991 }
3992
3993 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3994 {
3995 struct amd_iommu *iommu;
3996 int devid;
3997
3998 if (!info)
3999 return NULL;
4000
4001 devid = get_devid(info);
4002 if (devid >= 0) {
4003 iommu = amd_iommu_rlookup_table[devid];
4004 if (iommu)
4005 return iommu->ir_domain;
4006 }
4007
4008 return NULL;
4009 }
4010
4011 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4012 {
4013 struct amd_iommu *iommu;
4014 int devid;
4015
4016 if (!info)
4017 return NULL;
4018
4019 switch (info->type) {
4020 case X86_IRQ_ALLOC_TYPE_MSI:
4021 case X86_IRQ_ALLOC_TYPE_MSIX:
4022 devid = get_device_id(&info->msi_dev->dev);
4023 if (devid < 0)
4024 return NULL;
4025
4026 iommu = amd_iommu_rlookup_table[devid];
4027 if (iommu)
4028 return iommu->msi_domain;
4029 break;
4030 default:
4031 break;
4032 }
4033
4034 return NULL;
4035 }
4036
4037 struct irq_remap_ops amd_iommu_irq_ops = {
4038 .prepare = amd_iommu_prepare,
4039 .enable = amd_iommu_enable,
4040 .disable = amd_iommu_disable,
4041 .reenable = amd_iommu_reenable,
4042 .enable_faulting = amd_iommu_enable_faulting,
4043 .get_ir_irq_domain = get_ir_irq_domain,
4044 .get_irq_domain = get_irq_domain,
4045 };
4046
4047 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4048 struct irq_cfg *irq_cfg,
4049 struct irq_alloc_info *info,
4050 int devid, int index, int sub_handle)
4051 {
4052 struct irq_2_irte *irte_info = &data->irq_2_irte;
4053 struct msi_msg *msg = &data->msi_entry;
4054 struct IO_APIC_route_entry *entry;
4055 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4056
4057 if (!iommu)
4058 return;
4059
4060 data->irq_2_irte.devid = devid;
4061 data->irq_2_irte.index = index + sub_handle;
4062 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4063 apic->irq_dest_mode, irq_cfg->vector,
4064 irq_cfg->dest_apicid, devid);
4065
4066 switch (info->type) {
4067 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4068 /* Setup IOAPIC entry */
4069 entry = info->ioapic_entry;
4070 info->ioapic_entry = NULL;
4071 memset(entry, 0, sizeof(*entry));
4072 entry->vector = index;
4073 entry->mask = 0;
4074 entry->trigger = info->ioapic_trigger;
4075 entry->polarity = info->ioapic_polarity;
4076 /* Mask level triggered irqs. */
4077 if (info->ioapic_trigger)
4078 entry->mask = 1;
4079 break;
4080
4081 case X86_IRQ_ALLOC_TYPE_HPET:
4082 case X86_IRQ_ALLOC_TYPE_MSI:
4083 case X86_IRQ_ALLOC_TYPE_MSIX:
4084 msg->address_hi = MSI_ADDR_BASE_HI;
4085 msg->address_lo = MSI_ADDR_BASE_LO;
4086 msg->data = irte_info->index;
4087 break;
4088
4089 default:
4090 BUG_ON(1);
4091 break;
4092 }
4093 }
4094
4095 struct amd_irte_ops irte_32_ops = {
4096 .prepare = irte_prepare,
4097 .activate = irte_activate,
4098 .deactivate = irte_deactivate,
4099 .set_affinity = irte_set_affinity,
4100 .set_allocated = irte_set_allocated,
4101 .is_allocated = irte_is_allocated,
4102 .clear_allocated = irte_clear_allocated,
4103 };
4104
4105 struct amd_irte_ops irte_128_ops = {
4106 .prepare = irte_ga_prepare,
4107 .activate = irte_ga_activate,
4108 .deactivate = irte_ga_deactivate,
4109 .set_affinity = irte_ga_set_affinity,
4110 .set_allocated = irte_ga_set_allocated,
4111 .is_allocated = irte_ga_is_allocated,
4112 .clear_allocated = irte_ga_clear_allocated,
4113 };
4114
4115 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4116 unsigned int nr_irqs, void *arg)
4117 {
4118 struct irq_alloc_info *info = arg;
4119 struct irq_data *irq_data;
4120 struct amd_ir_data *data = NULL;
4121 struct irq_cfg *cfg;
4122 int i, ret, devid;
4123 int index = -1;
4124
4125 if (!info)
4126 return -EINVAL;
4127 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4128 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4129 return -EINVAL;
4130
4131 /*
4132 * With IRQ remapping enabled, don't need contiguous CPU vectors
4133 * to support multiple MSI interrupts.
4134 */
4135 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4136 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4137
4138 devid = get_devid(info);
4139 if (devid < 0)
4140 return -EINVAL;
4141
4142 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4143 if (ret < 0)
4144 return ret;
4145
4146 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4147 if (get_irq_table(devid, true))
4148 index = info->ioapic_pin;
4149 else
4150 ret = -ENOMEM;
4151 } else {
4152 index = alloc_irq_index(devid, nr_irqs);
4153 }
4154 if (index < 0) {
4155 pr_warn("Failed to allocate IRTE\n");
4156 goto out_free_parent;
4157 }
4158
4159 for (i = 0; i < nr_irqs; i++) {
4160 irq_data = irq_domain_get_irq_data(domain, virq + i);
4161 cfg = irqd_cfg(irq_data);
4162 if (!irq_data || !cfg) {
4163 ret = -EINVAL;
4164 goto out_free_data;
4165 }
4166
4167 ret = -ENOMEM;
4168 data = kzalloc(sizeof(*data), GFP_KERNEL);
4169 if (!data)
4170 goto out_free_data;
4171
4172 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4173 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4174 else
4175 data->entry = kzalloc(sizeof(struct irte_ga),
4176 GFP_KERNEL);
4177 if (!data->entry) {
4178 kfree(data);
4179 goto out_free_data;
4180 }
4181
4182 irq_data->hwirq = (devid << 16) + i;
4183 irq_data->chip_data = data;
4184 irq_data->chip = &amd_ir_chip;
4185 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4186 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4187 }
4188
4189 return 0;
4190
4191 out_free_data:
4192 for (i--; i >= 0; i--) {
4193 irq_data = irq_domain_get_irq_data(domain, virq + i);
4194 if (irq_data)
4195 kfree(irq_data->chip_data);
4196 }
4197 for (i = 0; i < nr_irqs; i++)
4198 free_irte(devid, index + i);
4199 out_free_parent:
4200 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4201 return ret;
4202 }
4203
4204 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4205 unsigned int nr_irqs)
4206 {
4207 struct irq_2_irte *irte_info;
4208 struct irq_data *irq_data;
4209 struct amd_ir_data *data;
4210 int i;
4211
4212 for (i = 0; i < nr_irqs; i++) {
4213 irq_data = irq_domain_get_irq_data(domain, virq + i);
4214 if (irq_data && irq_data->chip_data) {
4215 data = irq_data->chip_data;
4216 irte_info = &data->irq_2_irte;
4217 free_irte(irte_info->devid, irte_info->index);
4218 kfree(data->entry);
4219 kfree(data);
4220 }
4221 }
4222 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4223 }
4224
4225 static void irq_remapping_activate(struct irq_domain *domain,
4226 struct irq_data *irq_data)
4227 {
4228 struct amd_ir_data *data = irq_data->chip_data;
4229 struct irq_2_irte *irte_info = &data->irq_2_irte;
4230 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4231
4232 if (iommu)
4233 iommu->irte_ops->activate(data->entry, irte_info->devid,
4234 irte_info->index);
4235 }
4236
4237 static void irq_remapping_deactivate(struct irq_domain *domain,
4238 struct irq_data *irq_data)
4239 {
4240 struct amd_ir_data *data = irq_data->chip_data;
4241 struct irq_2_irte *irte_info = &data->irq_2_irte;
4242 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4243
4244 if (iommu)
4245 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4246 irte_info->index);
4247 }
4248
4249 static struct irq_domain_ops amd_ir_domain_ops = {
4250 .alloc = irq_remapping_alloc,
4251 .free = irq_remapping_free,
4252 .activate = irq_remapping_activate,
4253 .deactivate = irq_remapping_deactivate,
4254 };
4255
4256 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4257 {
4258 struct amd_iommu *iommu;
4259 struct amd_iommu_pi_data *pi_data = vcpu_info;
4260 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4261 struct amd_ir_data *ir_data = data->chip_data;
4262 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4263 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4264 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4265
4266 /* Note:
4267 * This device has never been set up for guest mode.
4268 * we should not modify the IRTE
4269 */
4270 if (!dev_data || !dev_data->use_vapic)
4271 return 0;
4272
4273 pi_data->ir_data = ir_data;
4274
4275 /* Note:
4276 * SVM tries to set up for VAPIC mode, but we are in
4277 * legacy mode. So, we force legacy mode instead.
4278 */
4279 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4280 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4281 __func__);
4282 pi_data->is_guest_mode = false;
4283 }
4284
4285 iommu = amd_iommu_rlookup_table[irte_info->devid];
4286 if (iommu == NULL)
4287 return -EINVAL;
4288
4289 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4290 if (pi_data->is_guest_mode) {
4291 /* Setting */
4292 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4293 irte->hi.fields.vector = vcpu_pi_info->vector;
4294 irte->lo.fields_vapic.guest_mode = 1;
4295 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4296
4297 ir_data->cached_ga_tag = pi_data->ga_tag;
4298 } else {
4299 /* Un-Setting */
4300 struct irq_cfg *cfg = irqd_cfg(data);
4301
4302 irte->hi.val = 0;
4303 irte->lo.val = 0;
4304 irte->hi.fields.vector = cfg->vector;
4305 irte->lo.fields_remap.guest_mode = 0;
4306 irte->lo.fields_remap.destination = cfg->dest_apicid;
4307 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4308 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4309
4310 /*
4311 * This communicates the ga_tag back to the caller
4312 * so that it can do all the necessary clean up.
4313 */
4314 ir_data->cached_ga_tag = 0;
4315 }
4316
4317 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4318 }
4319
4320 static int amd_ir_set_affinity(struct irq_data *data,
4321 const struct cpumask *mask, bool force)
4322 {
4323 struct amd_ir_data *ir_data = data->chip_data;
4324 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4325 struct irq_cfg *cfg = irqd_cfg(data);
4326 struct irq_data *parent = data->parent_data;
4327 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4328 int ret;
4329
4330 if (!iommu)
4331 return -ENODEV;
4332
4333 ret = parent->chip->irq_set_affinity(parent, mask, force);
4334 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4335 return ret;
4336
4337 /*
4338 * Atomically updates the IRTE with the new destination, vector
4339 * and flushes the interrupt entry cache.
4340 */
4341 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4342 irte_info->index, cfg->vector, cfg->dest_apicid);
4343
4344 /*
4345 * After this point, all the interrupts will start arriving
4346 * at the new destination. So, time to cleanup the previous
4347 * vector allocation.
4348 */
4349 send_cleanup_vector(cfg);
4350
4351 return IRQ_SET_MASK_OK_DONE;
4352 }
4353
4354 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4355 {
4356 struct amd_ir_data *ir_data = irq_data->chip_data;
4357
4358 *msg = ir_data->msi_entry;
4359 }
4360
4361 static struct irq_chip amd_ir_chip = {
4362 .irq_ack = ir_ack_apic_edge,
4363 .irq_set_affinity = amd_ir_set_affinity,
4364 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4365 .irq_compose_msi_msg = ir_compose_msi_msg,
4366 };
4367
4368 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4369 {
4370 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4371 if (!iommu->ir_domain)
4372 return -ENOMEM;
4373
4374 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4375 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4376
4377 return 0;
4378 }
4379
4380 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4381 {
4382 unsigned long flags;
4383 struct amd_iommu *iommu;
4384 struct irq_remap_table *irt;
4385 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4386 int devid = ir_data->irq_2_irte.devid;
4387 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4388 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4389
4390 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4391 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4392 return 0;
4393
4394 iommu = amd_iommu_rlookup_table[devid];
4395 if (!iommu)
4396 return -ENODEV;
4397
4398 irt = get_irq_table(devid, false);
4399 if (!irt)
4400 return -ENODEV;
4401
4402 spin_lock_irqsave(&irt->lock, flags);
4403
4404 if (ref->lo.fields_vapic.guest_mode) {
4405 if (cpu >= 0)
4406 ref->lo.fields_vapic.destination = cpu;
4407 ref->lo.fields_vapic.is_run = is_run;
4408 barrier();
4409 }
4410
4411 spin_unlock_irqrestore(&irt->lock, flags);
4412
4413 iommu_flush_irt(iommu, devid);
4414 iommu_completion_wait(iommu);
4415 return 0;
4416 }
4417 EXPORT_SYMBOL(amd_iommu_update_ga);
4418 #endif
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