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Merge tag 'drm-for-v4.9' of git://people.freedesktop.org/~airlied/linux
[mirror_ubuntu-bionic-kernel.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
45 #include <asm/apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
50 #include <asm/gart.h>
51 #include <asm/dma.h>
52
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
56
57 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
58
59 #define LOOP_TIMEOUT 100000
60
61 /* IO virtual address start page frame number */
62 #define IOVA_START_PFN (1)
63 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
65
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
71
72 /*
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
76 * that we support.
77 *
78 * 512GB Pages are not supported due to a hardware bug
79 */
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
81
82 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
83
84 /* List of all available dev_data structures */
85 static LIST_HEAD(dev_data_list);
86 static DEFINE_SPINLOCK(dev_data_list_lock);
87
88 LIST_HEAD(ioapic_map);
89 LIST_HEAD(hpet_map);
90 LIST_HEAD(acpihid_map);
91
92 #define FLUSH_QUEUE_SIZE 256
93
94 struct flush_queue_entry {
95 unsigned long iova_pfn;
96 unsigned long pages;
97 struct dma_ops_domain *dma_dom;
98 };
99
100 struct flush_queue {
101 spinlock_t lock;
102 unsigned next;
103 struct flush_queue_entry *entries;
104 };
105
106 static DEFINE_PER_CPU(struct flush_queue, flush_queue);
107
108 static atomic_t queue_timer_on;
109 static struct timer_list queue_timer;
110
111 /*
112 * Domain for untranslated devices - only allocated
113 * if iommu=pt passed on kernel cmd line.
114 */
115 static const struct iommu_ops amd_iommu_ops;
116
117 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
118 int amd_iommu_max_glx_val = -1;
119
120 static struct dma_map_ops amd_iommu_dma_ops;
121
122 /*
123 * This struct contains device specific data for the IOMMU
124 */
125 struct iommu_dev_data {
126 struct list_head list; /* For domain->dev_list */
127 struct list_head dev_data_list; /* For global dev_data_list */
128 struct protection_domain *domain; /* Domain the device is bound to */
129 u16 devid; /* PCI Device ID */
130 u16 alias; /* Alias Device ID */
131 bool iommu_v2; /* Device can make use of IOMMUv2 */
132 bool passthrough; /* Device is identity mapped */
133 struct {
134 bool enabled;
135 int qdep;
136 } ats; /* ATS state */
137 bool pri_tlp; /* PASID TLB required for
138 PPR completions */
139 u32 errata; /* Bitmap for errata to apply */
140 bool use_vapic; /* Enable device to use vapic mode */
141 };
142
143 /*
144 * general struct to manage commands send to an IOMMU
145 */
146 struct iommu_cmd {
147 u32 data[4];
148 };
149
150 struct kmem_cache *amd_iommu_irq_cache;
151
152 static void update_domain(struct protection_domain *domain);
153 static int protection_domain_init(struct protection_domain *domain);
154 static void detach_device(struct device *dev);
155
156 /*
157 * Data container for a dma_ops specific protection domain
158 */
159 struct dma_ops_domain {
160 /* generic protection domain information */
161 struct protection_domain domain;
162
163 /* IOVA RB-Tree */
164 struct iova_domain iovad;
165 };
166
167 static struct iova_domain reserved_iova_ranges;
168 static struct lock_class_key reserved_rbtree_key;
169
170 /****************************************************************************
171 *
172 * Helper functions
173 *
174 ****************************************************************************/
175
176 static inline int match_hid_uid(struct device *dev,
177 struct acpihid_map_entry *entry)
178 {
179 const char *hid, *uid;
180
181 hid = acpi_device_hid(ACPI_COMPANION(dev));
182 uid = acpi_device_uid(ACPI_COMPANION(dev));
183
184 if (!hid || !(*hid))
185 return -ENODEV;
186
187 if (!uid || !(*uid))
188 return strcmp(hid, entry->hid);
189
190 if (!(*entry->uid))
191 return strcmp(hid, entry->hid);
192
193 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
194 }
195
196 static inline u16 get_pci_device_id(struct device *dev)
197 {
198 struct pci_dev *pdev = to_pci_dev(dev);
199
200 return PCI_DEVID(pdev->bus->number, pdev->devfn);
201 }
202
203 static inline int get_acpihid_device_id(struct device *dev,
204 struct acpihid_map_entry **entry)
205 {
206 struct acpihid_map_entry *p;
207
208 list_for_each_entry(p, &acpihid_map, list) {
209 if (!match_hid_uid(dev, p)) {
210 if (entry)
211 *entry = p;
212 return p->devid;
213 }
214 }
215 return -EINVAL;
216 }
217
218 static inline int get_device_id(struct device *dev)
219 {
220 int devid;
221
222 if (dev_is_pci(dev))
223 devid = get_pci_device_id(dev);
224 else
225 devid = get_acpihid_device_id(dev, NULL);
226
227 return devid;
228 }
229
230 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
231 {
232 return container_of(dom, struct protection_domain, domain);
233 }
234
235 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
236 {
237 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
238 return container_of(domain, struct dma_ops_domain, domain);
239 }
240
241 static struct iommu_dev_data *alloc_dev_data(u16 devid)
242 {
243 struct iommu_dev_data *dev_data;
244 unsigned long flags;
245
246 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
247 if (!dev_data)
248 return NULL;
249
250 dev_data->devid = devid;
251
252 spin_lock_irqsave(&dev_data_list_lock, flags);
253 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
254 spin_unlock_irqrestore(&dev_data_list_lock, flags);
255
256 return dev_data;
257 }
258
259 static struct iommu_dev_data *search_dev_data(u16 devid)
260 {
261 struct iommu_dev_data *dev_data;
262 unsigned long flags;
263
264 spin_lock_irqsave(&dev_data_list_lock, flags);
265 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
266 if (dev_data->devid == devid)
267 goto out_unlock;
268 }
269
270 dev_data = NULL;
271
272 out_unlock:
273 spin_unlock_irqrestore(&dev_data_list_lock, flags);
274
275 return dev_data;
276 }
277
278 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
279 {
280 *(u16 *)data = alias;
281 return 0;
282 }
283
284 static u16 get_alias(struct device *dev)
285 {
286 struct pci_dev *pdev = to_pci_dev(dev);
287 u16 devid, ivrs_alias, pci_alias;
288
289 /* The callers make sure that get_device_id() does not fail here */
290 devid = get_device_id(dev);
291 ivrs_alias = amd_iommu_alias_table[devid];
292 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
293
294 if (ivrs_alias == pci_alias)
295 return ivrs_alias;
296
297 /*
298 * DMA alias showdown
299 *
300 * The IVRS is fairly reliable in telling us about aliases, but it
301 * can't know about every screwy device. If we don't have an IVRS
302 * reported alias, use the PCI reported alias. In that case we may
303 * still need to initialize the rlookup and dev_table entries if the
304 * alias is to a non-existent device.
305 */
306 if (ivrs_alias == devid) {
307 if (!amd_iommu_rlookup_table[pci_alias]) {
308 amd_iommu_rlookup_table[pci_alias] =
309 amd_iommu_rlookup_table[devid];
310 memcpy(amd_iommu_dev_table[pci_alias].data,
311 amd_iommu_dev_table[devid].data,
312 sizeof(amd_iommu_dev_table[pci_alias].data));
313 }
314
315 return pci_alias;
316 }
317
318 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
319 "for device %s[%04x:%04x], kernel reported alias "
320 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
321 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
322 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
323 PCI_FUNC(pci_alias));
324
325 /*
326 * If we don't have a PCI DMA alias and the IVRS alias is on the same
327 * bus, then the IVRS table may know about a quirk that we don't.
328 */
329 if (pci_alias == devid &&
330 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
331 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
332 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
333 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
334 dev_name(dev));
335 }
336
337 return ivrs_alias;
338 }
339
340 static struct iommu_dev_data *find_dev_data(u16 devid)
341 {
342 struct iommu_dev_data *dev_data;
343
344 dev_data = search_dev_data(devid);
345
346 if (dev_data == NULL)
347 dev_data = alloc_dev_data(devid);
348
349 return dev_data;
350 }
351
352 static struct iommu_dev_data *get_dev_data(struct device *dev)
353 {
354 return dev->archdata.iommu;
355 }
356
357 /*
358 * Find or create an IOMMU group for a acpihid device.
359 */
360 static struct iommu_group *acpihid_device_group(struct device *dev)
361 {
362 struct acpihid_map_entry *p, *entry = NULL;
363 int devid;
364
365 devid = get_acpihid_device_id(dev, &entry);
366 if (devid < 0)
367 return ERR_PTR(devid);
368
369 list_for_each_entry(p, &acpihid_map, list) {
370 if ((devid == p->devid) && p->group)
371 entry->group = p->group;
372 }
373
374 if (!entry->group)
375 entry->group = generic_device_group(dev);
376
377 return entry->group;
378 }
379
380 static bool pci_iommuv2_capable(struct pci_dev *pdev)
381 {
382 static const int caps[] = {
383 PCI_EXT_CAP_ID_ATS,
384 PCI_EXT_CAP_ID_PRI,
385 PCI_EXT_CAP_ID_PASID,
386 };
387 int i, pos;
388
389 for (i = 0; i < 3; ++i) {
390 pos = pci_find_ext_capability(pdev, caps[i]);
391 if (pos == 0)
392 return false;
393 }
394
395 return true;
396 }
397
398 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
399 {
400 struct iommu_dev_data *dev_data;
401
402 dev_data = get_dev_data(&pdev->dev);
403
404 return dev_data->errata & (1 << erratum) ? true : false;
405 }
406
407 /*
408 * This function checks if the driver got a valid device from the caller to
409 * avoid dereferencing invalid pointers.
410 */
411 static bool check_device(struct device *dev)
412 {
413 int devid;
414
415 if (!dev || !dev->dma_mask)
416 return false;
417
418 devid = get_device_id(dev);
419 if (devid < 0)
420 return false;
421
422 /* Out of our scope? */
423 if (devid > amd_iommu_last_bdf)
424 return false;
425
426 if (amd_iommu_rlookup_table[devid] == NULL)
427 return false;
428
429 return true;
430 }
431
432 static void init_iommu_group(struct device *dev)
433 {
434 struct iommu_group *group;
435
436 group = iommu_group_get_for_dev(dev);
437 if (IS_ERR(group))
438 return;
439
440 iommu_group_put(group);
441 }
442
443 static int iommu_init_device(struct device *dev)
444 {
445 struct iommu_dev_data *dev_data;
446 int devid;
447
448 if (dev->archdata.iommu)
449 return 0;
450
451 devid = get_device_id(dev);
452 if (devid < 0)
453 return devid;
454
455 dev_data = find_dev_data(devid);
456 if (!dev_data)
457 return -ENOMEM;
458
459 dev_data->alias = get_alias(dev);
460
461 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
462 struct amd_iommu *iommu;
463
464 iommu = amd_iommu_rlookup_table[dev_data->devid];
465 dev_data->iommu_v2 = iommu->is_iommu_v2;
466 }
467
468 dev->archdata.iommu = dev_data;
469
470 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
471 dev);
472
473 return 0;
474 }
475
476 static void iommu_ignore_device(struct device *dev)
477 {
478 u16 alias;
479 int devid;
480
481 devid = get_device_id(dev);
482 if (devid < 0)
483 return;
484
485 alias = get_alias(dev);
486
487 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
488 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
489
490 amd_iommu_rlookup_table[devid] = NULL;
491 amd_iommu_rlookup_table[alias] = NULL;
492 }
493
494 static void iommu_uninit_device(struct device *dev)
495 {
496 int devid;
497 struct iommu_dev_data *dev_data;
498
499 devid = get_device_id(dev);
500 if (devid < 0)
501 return;
502
503 dev_data = search_dev_data(devid);
504 if (!dev_data)
505 return;
506
507 if (dev_data->domain)
508 detach_device(dev);
509
510 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
511 dev);
512
513 iommu_group_remove_device(dev);
514
515 /* Remove dma-ops */
516 dev->archdata.dma_ops = NULL;
517
518 /*
519 * We keep dev_data around for unplugged devices and reuse it when the
520 * device is re-plugged - not doing so would introduce a ton of races.
521 */
522 }
523
524 /****************************************************************************
525 *
526 * Interrupt handling functions
527 *
528 ****************************************************************************/
529
530 static void dump_dte_entry(u16 devid)
531 {
532 int i;
533
534 for (i = 0; i < 4; ++i)
535 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
536 amd_iommu_dev_table[devid].data[i]);
537 }
538
539 static void dump_command(unsigned long phys_addr)
540 {
541 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
542 int i;
543
544 for (i = 0; i < 4; ++i)
545 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
546 }
547
548 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
549 {
550 int type, devid, domid, flags;
551 volatile u32 *event = __evt;
552 int count = 0;
553 u64 address;
554
555 retry:
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
561
562 if (type == 0) {
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
566 return;
567 }
568 udelay(1);
569 goto retry;
570 }
571
572 printk(KERN_ERR "AMD-Vi: Event logged [");
573
574 switch (type) {
575 case EVENT_TYPE_ILL_DEV:
576 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
577 "address=0x%016llx flags=0x%04x]\n",
578 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
579 address, flags);
580 dump_dte_entry(devid);
581 break;
582 case EVENT_TYPE_IO_FAULT:
583 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
584 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
585 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
586 domid, address, flags);
587 break;
588 case EVENT_TYPE_DEV_TAB_ERR:
589 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
590 "address=0x%016llx flags=0x%04x]\n",
591 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
592 address, flags);
593 break;
594 case EVENT_TYPE_PAGE_TAB_ERR:
595 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
596 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 domid, address, flags);
599 break;
600 case EVENT_TYPE_ILL_CMD:
601 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
602 dump_command(address);
603 break;
604 case EVENT_TYPE_CMD_HARD_ERR:
605 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
606 "flags=0x%04x]\n", address, flags);
607 break;
608 case EVENT_TYPE_IOTLB_INV_TO:
609 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
610 "address=0x%016llx]\n",
611 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
612 address);
613 break;
614 case EVENT_TYPE_INV_DEV_REQ:
615 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
616 "address=0x%016llx flags=0x%04x]\n",
617 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
618 address, flags);
619 break;
620 default:
621 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
622 }
623
624 memset(__evt, 0, 4 * sizeof(u32));
625 }
626
627 static void iommu_poll_events(struct amd_iommu *iommu)
628 {
629 u32 head, tail;
630
631 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
632 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
633
634 while (head != tail) {
635 iommu_print_event(iommu, iommu->evt_buf + head);
636 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
637 }
638
639 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
640 }
641
642 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
643 {
644 struct amd_iommu_fault fault;
645
646 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
647 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
648 return;
649 }
650
651 fault.address = raw[1];
652 fault.pasid = PPR_PASID(raw[0]);
653 fault.device_id = PPR_DEVID(raw[0]);
654 fault.tag = PPR_TAG(raw[0]);
655 fault.flags = PPR_FLAGS(raw[0]);
656
657 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
658 }
659
660 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
661 {
662 u32 head, tail;
663
664 if (iommu->ppr_log == NULL)
665 return;
666
667 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
668 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
669
670 while (head != tail) {
671 volatile u64 *raw;
672 u64 entry[2];
673 int i;
674
675 raw = (u64 *)(iommu->ppr_log + head);
676
677 /*
678 * Hardware bug: Interrupt may arrive before the entry is
679 * written to memory. If this happens we need to wait for the
680 * entry to arrive.
681 */
682 for (i = 0; i < LOOP_TIMEOUT; ++i) {
683 if (PPR_REQ_TYPE(raw[0]) != 0)
684 break;
685 udelay(1);
686 }
687
688 /* Avoid memcpy function-call overhead */
689 entry[0] = raw[0];
690 entry[1] = raw[1];
691
692 /*
693 * To detect the hardware bug we need to clear the entry
694 * back to zero.
695 */
696 raw[0] = raw[1] = 0UL;
697
698 /* Update head pointer of hardware ring-buffer */
699 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
700 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
701
702 /* Handle PPR entry */
703 iommu_handle_ppr_entry(iommu, entry);
704
705 /* Refresh ring-buffer information */
706 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
707 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
708 }
709 }
710
711 #ifdef CONFIG_IRQ_REMAP
712 static int (*iommu_ga_log_notifier)(u32);
713
714 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
715 {
716 iommu_ga_log_notifier = notifier;
717
718 return 0;
719 }
720 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
721
722 static void iommu_poll_ga_log(struct amd_iommu *iommu)
723 {
724 u32 head, tail, cnt = 0;
725
726 if (iommu->ga_log == NULL)
727 return;
728
729 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
730 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
731
732 while (head != tail) {
733 volatile u64 *raw;
734 u64 log_entry;
735
736 raw = (u64 *)(iommu->ga_log + head);
737 cnt++;
738
739 /* Avoid memcpy function-call overhead */
740 log_entry = *raw;
741
742 /* Update head pointer of hardware ring-buffer */
743 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
744 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
745
746 /* Handle GA entry */
747 switch (GA_REQ_TYPE(log_entry)) {
748 case GA_GUEST_NR:
749 if (!iommu_ga_log_notifier)
750 break;
751
752 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
753 __func__, GA_DEVID(log_entry),
754 GA_TAG(log_entry));
755
756 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
757 pr_err("AMD-Vi: GA log notifier failed.\n");
758 break;
759 default:
760 break;
761 }
762 }
763 }
764 #endif /* CONFIG_IRQ_REMAP */
765
766 #define AMD_IOMMU_INT_MASK \
767 (MMIO_STATUS_EVT_INT_MASK | \
768 MMIO_STATUS_PPR_INT_MASK | \
769 MMIO_STATUS_GALOG_INT_MASK)
770
771 irqreturn_t amd_iommu_int_thread(int irq, void *data)
772 {
773 struct amd_iommu *iommu = (struct amd_iommu *) data;
774 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
775
776 while (status & AMD_IOMMU_INT_MASK) {
777 /* Enable EVT and PPR and GA interrupts again */
778 writel(AMD_IOMMU_INT_MASK,
779 iommu->mmio_base + MMIO_STATUS_OFFSET);
780
781 if (status & MMIO_STATUS_EVT_INT_MASK) {
782 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
783 iommu_poll_events(iommu);
784 }
785
786 if (status & MMIO_STATUS_PPR_INT_MASK) {
787 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
788 iommu_poll_ppr_log(iommu);
789 }
790
791 #ifdef CONFIG_IRQ_REMAP
792 if (status & MMIO_STATUS_GALOG_INT_MASK) {
793 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
794 iommu_poll_ga_log(iommu);
795 }
796 #endif
797
798 /*
799 * Hardware bug: ERBT1312
800 * When re-enabling interrupt (by writing 1
801 * to clear the bit), the hardware might also try to set
802 * the interrupt bit in the event status register.
803 * In this scenario, the bit will be set, and disable
804 * subsequent interrupts.
805 *
806 * Workaround: The IOMMU driver should read back the
807 * status register and check if the interrupt bits are cleared.
808 * If not, driver will need to go through the interrupt handler
809 * again and re-clear the bits
810 */
811 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
812 }
813 return IRQ_HANDLED;
814 }
815
816 irqreturn_t amd_iommu_int_handler(int irq, void *data)
817 {
818 return IRQ_WAKE_THREAD;
819 }
820
821 /****************************************************************************
822 *
823 * IOMMU command queuing functions
824 *
825 ****************************************************************************/
826
827 static int wait_on_sem(volatile u64 *sem)
828 {
829 int i = 0;
830
831 while (*sem == 0 && i < LOOP_TIMEOUT) {
832 udelay(1);
833 i += 1;
834 }
835
836 if (i == LOOP_TIMEOUT) {
837 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
838 return -EIO;
839 }
840
841 return 0;
842 }
843
844 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
845 struct iommu_cmd *cmd,
846 u32 tail)
847 {
848 u8 *target;
849
850 target = iommu->cmd_buf + tail;
851 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
852
853 /* Copy command to buffer */
854 memcpy(target, cmd, sizeof(*cmd));
855
856 /* Tell the IOMMU about it */
857 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
858 }
859
860 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
861 {
862 WARN_ON(address & 0x7ULL);
863
864 memset(cmd, 0, sizeof(*cmd));
865 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
866 cmd->data[1] = upper_32_bits(__pa(address));
867 cmd->data[2] = 1;
868 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
869 }
870
871 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
872 {
873 memset(cmd, 0, sizeof(*cmd));
874 cmd->data[0] = devid;
875 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
876 }
877
878 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
879 size_t size, u16 domid, int pde)
880 {
881 u64 pages;
882 bool s;
883
884 pages = iommu_num_pages(address, size, PAGE_SIZE);
885 s = false;
886
887 if (pages > 1) {
888 /*
889 * If we have to flush more than one page, flush all
890 * TLB entries for this domain
891 */
892 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
893 s = true;
894 }
895
896 address &= PAGE_MASK;
897
898 memset(cmd, 0, sizeof(*cmd));
899 cmd->data[1] |= domid;
900 cmd->data[2] = lower_32_bits(address);
901 cmd->data[3] = upper_32_bits(address);
902 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
903 if (s) /* size bit - we flush more than one 4kb page */
904 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
905 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
906 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
907 }
908
909 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
910 u64 address, size_t size)
911 {
912 u64 pages;
913 bool s;
914
915 pages = iommu_num_pages(address, size, PAGE_SIZE);
916 s = false;
917
918 if (pages > 1) {
919 /*
920 * If we have to flush more than one page, flush all
921 * TLB entries for this domain
922 */
923 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
924 s = true;
925 }
926
927 address &= PAGE_MASK;
928
929 memset(cmd, 0, sizeof(*cmd));
930 cmd->data[0] = devid;
931 cmd->data[0] |= (qdep & 0xff) << 24;
932 cmd->data[1] = devid;
933 cmd->data[2] = lower_32_bits(address);
934 cmd->data[3] = upper_32_bits(address);
935 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
936 if (s)
937 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
938 }
939
940 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
941 u64 address, bool size)
942 {
943 memset(cmd, 0, sizeof(*cmd));
944
945 address &= ~(0xfffULL);
946
947 cmd->data[0] = pasid;
948 cmd->data[1] = domid;
949 cmd->data[2] = lower_32_bits(address);
950 cmd->data[3] = upper_32_bits(address);
951 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
952 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
953 if (size)
954 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
955 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
956 }
957
958 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
959 int qdep, u64 address, bool size)
960 {
961 memset(cmd, 0, sizeof(*cmd));
962
963 address &= ~(0xfffULL);
964
965 cmd->data[0] = devid;
966 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
967 cmd->data[0] |= (qdep & 0xff) << 24;
968 cmd->data[1] = devid;
969 cmd->data[1] |= (pasid & 0xff) << 16;
970 cmd->data[2] = lower_32_bits(address);
971 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
972 cmd->data[3] = upper_32_bits(address);
973 if (size)
974 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
975 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
976 }
977
978 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
979 int status, int tag, bool gn)
980 {
981 memset(cmd, 0, sizeof(*cmd));
982
983 cmd->data[0] = devid;
984 if (gn) {
985 cmd->data[1] = pasid;
986 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
987 }
988 cmd->data[3] = tag & 0x1ff;
989 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
990
991 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
992 }
993
994 static void build_inv_all(struct iommu_cmd *cmd)
995 {
996 memset(cmd, 0, sizeof(*cmd));
997 CMD_SET_TYPE(cmd, CMD_INV_ALL);
998 }
999
1000 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1001 {
1002 memset(cmd, 0, sizeof(*cmd));
1003 cmd->data[0] = devid;
1004 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1005 }
1006
1007 /*
1008 * Writes the command to the IOMMUs command buffer and informs the
1009 * hardware about the new command.
1010 */
1011 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1012 struct iommu_cmd *cmd,
1013 bool sync)
1014 {
1015 u32 left, tail, head, next_tail;
1016
1017 again:
1018
1019 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1020 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1021 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1022 left = (head - next_tail) % CMD_BUFFER_SIZE;
1023
1024 if (left <= 2) {
1025 struct iommu_cmd sync_cmd;
1026 int ret;
1027
1028 iommu->cmd_sem = 0;
1029
1030 build_completion_wait(&sync_cmd, (u64)&iommu->cmd_sem);
1031 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1032
1033 if ((ret = wait_on_sem(&iommu->cmd_sem)) != 0)
1034 return ret;
1035
1036 goto again;
1037 }
1038
1039 copy_cmd_to_buffer(iommu, cmd, tail);
1040
1041 /* We need to sync now to make sure all commands are processed */
1042 iommu->need_sync = sync;
1043
1044 return 0;
1045 }
1046
1047 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1048 struct iommu_cmd *cmd,
1049 bool sync)
1050 {
1051 unsigned long flags;
1052 int ret;
1053
1054 spin_lock_irqsave(&iommu->lock, flags);
1055 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1056 spin_unlock_irqrestore(&iommu->lock, flags);
1057
1058 return ret;
1059 }
1060
1061 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1062 {
1063 return iommu_queue_command_sync(iommu, cmd, true);
1064 }
1065
1066 /*
1067 * This function queues a completion wait command into the command
1068 * buffer of an IOMMU
1069 */
1070 static int iommu_completion_wait(struct amd_iommu *iommu)
1071 {
1072 struct iommu_cmd cmd;
1073 unsigned long flags;
1074 int ret;
1075
1076 if (!iommu->need_sync)
1077 return 0;
1078
1079
1080 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1081
1082 spin_lock_irqsave(&iommu->lock, flags);
1083
1084 iommu->cmd_sem = 0;
1085
1086 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1087 if (ret)
1088 goto out_unlock;
1089
1090 ret = wait_on_sem(&iommu->cmd_sem);
1091
1092 out_unlock:
1093 spin_unlock_irqrestore(&iommu->lock, flags);
1094
1095 return ret;
1096 }
1097
1098 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1099 {
1100 struct iommu_cmd cmd;
1101
1102 build_inv_dte(&cmd, devid);
1103
1104 return iommu_queue_command(iommu, &cmd);
1105 }
1106
1107 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1108 {
1109 u32 devid;
1110
1111 for (devid = 0; devid <= 0xffff; ++devid)
1112 iommu_flush_dte(iommu, devid);
1113
1114 iommu_completion_wait(iommu);
1115 }
1116
1117 /*
1118 * This function uses heavy locking and may disable irqs for some time. But
1119 * this is no issue because it is only called during resume.
1120 */
1121 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1122 {
1123 u32 dom_id;
1124
1125 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1126 struct iommu_cmd cmd;
1127 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1128 dom_id, 1);
1129 iommu_queue_command(iommu, &cmd);
1130 }
1131
1132 iommu_completion_wait(iommu);
1133 }
1134
1135 static void iommu_flush_all(struct amd_iommu *iommu)
1136 {
1137 struct iommu_cmd cmd;
1138
1139 build_inv_all(&cmd);
1140
1141 iommu_queue_command(iommu, &cmd);
1142 iommu_completion_wait(iommu);
1143 }
1144
1145 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1146 {
1147 struct iommu_cmd cmd;
1148
1149 build_inv_irt(&cmd, devid);
1150
1151 iommu_queue_command(iommu, &cmd);
1152 }
1153
1154 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1155 {
1156 u32 devid;
1157
1158 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1159 iommu_flush_irt(iommu, devid);
1160
1161 iommu_completion_wait(iommu);
1162 }
1163
1164 void iommu_flush_all_caches(struct amd_iommu *iommu)
1165 {
1166 if (iommu_feature(iommu, FEATURE_IA)) {
1167 iommu_flush_all(iommu);
1168 } else {
1169 iommu_flush_dte_all(iommu);
1170 iommu_flush_irt_all(iommu);
1171 iommu_flush_tlb_all(iommu);
1172 }
1173 }
1174
1175 /*
1176 * Command send function for flushing on-device TLB
1177 */
1178 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1179 u64 address, size_t size)
1180 {
1181 struct amd_iommu *iommu;
1182 struct iommu_cmd cmd;
1183 int qdep;
1184
1185 qdep = dev_data->ats.qdep;
1186 iommu = amd_iommu_rlookup_table[dev_data->devid];
1187
1188 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1189
1190 return iommu_queue_command(iommu, &cmd);
1191 }
1192
1193 /*
1194 * Command send function for invalidating a device table entry
1195 */
1196 static int device_flush_dte(struct iommu_dev_data *dev_data)
1197 {
1198 struct amd_iommu *iommu;
1199 u16 alias;
1200 int ret;
1201
1202 iommu = amd_iommu_rlookup_table[dev_data->devid];
1203 alias = dev_data->alias;
1204
1205 ret = iommu_flush_dte(iommu, dev_data->devid);
1206 if (!ret && alias != dev_data->devid)
1207 ret = iommu_flush_dte(iommu, alias);
1208 if (ret)
1209 return ret;
1210
1211 if (dev_data->ats.enabled)
1212 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1213
1214 return ret;
1215 }
1216
1217 /*
1218 * TLB invalidation function which is called from the mapping functions.
1219 * It invalidates a single PTE if the range to flush is within a single
1220 * page. Otherwise it flushes the whole TLB of the IOMMU.
1221 */
1222 static void __domain_flush_pages(struct protection_domain *domain,
1223 u64 address, size_t size, int pde)
1224 {
1225 struct iommu_dev_data *dev_data;
1226 struct iommu_cmd cmd;
1227 int ret = 0, i;
1228
1229 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1230
1231 for (i = 0; i < amd_iommus_present; ++i) {
1232 if (!domain->dev_iommu[i])
1233 continue;
1234
1235 /*
1236 * Devices of this domain are behind this IOMMU
1237 * We need a TLB flush
1238 */
1239 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1240 }
1241
1242 list_for_each_entry(dev_data, &domain->dev_list, list) {
1243
1244 if (!dev_data->ats.enabled)
1245 continue;
1246
1247 ret |= device_flush_iotlb(dev_data, address, size);
1248 }
1249
1250 WARN_ON(ret);
1251 }
1252
1253 static void domain_flush_pages(struct protection_domain *domain,
1254 u64 address, size_t size)
1255 {
1256 __domain_flush_pages(domain, address, size, 0);
1257 }
1258
1259 /* Flush the whole IO/TLB for a given protection domain */
1260 static void domain_flush_tlb(struct protection_domain *domain)
1261 {
1262 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1263 }
1264
1265 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1266 static void domain_flush_tlb_pde(struct protection_domain *domain)
1267 {
1268 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1269 }
1270
1271 static void domain_flush_complete(struct protection_domain *domain)
1272 {
1273 int i;
1274
1275 for (i = 0; i < amd_iommus_present; ++i) {
1276 if (domain && !domain->dev_iommu[i])
1277 continue;
1278
1279 /*
1280 * Devices of this domain are behind this IOMMU
1281 * We need to wait for completion of all commands.
1282 */
1283 iommu_completion_wait(amd_iommus[i]);
1284 }
1285 }
1286
1287
1288 /*
1289 * This function flushes the DTEs for all devices in domain
1290 */
1291 static void domain_flush_devices(struct protection_domain *domain)
1292 {
1293 struct iommu_dev_data *dev_data;
1294
1295 list_for_each_entry(dev_data, &domain->dev_list, list)
1296 device_flush_dte(dev_data);
1297 }
1298
1299 /****************************************************************************
1300 *
1301 * The functions below are used the create the page table mappings for
1302 * unity mapped regions.
1303 *
1304 ****************************************************************************/
1305
1306 /*
1307 * This function is used to add another level to an IO page table. Adding
1308 * another level increases the size of the address space by 9 bits to a size up
1309 * to 64 bits.
1310 */
1311 static bool increase_address_space(struct protection_domain *domain,
1312 gfp_t gfp)
1313 {
1314 u64 *pte;
1315
1316 if (domain->mode == PAGE_MODE_6_LEVEL)
1317 /* address space already 64 bit large */
1318 return false;
1319
1320 pte = (void *)get_zeroed_page(gfp);
1321 if (!pte)
1322 return false;
1323
1324 *pte = PM_LEVEL_PDE(domain->mode,
1325 virt_to_phys(domain->pt_root));
1326 domain->pt_root = pte;
1327 domain->mode += 1;
1328 domain->updated = true;
1329
1330 return true;
1331 }
1332
1333 static u64 *alloc_pte(struct protection_domain *domain,
1334 unsigned long address,
1335 unsigned long page_size,
1336 u64 **pte_page,
1337 gfp_t gfp)
1338 {
1339 int level, end_lvl;
1340 u64 *pte, *page;
1341
1342 BUG_ON(!is_power_of_2(page_size));
1343
1344 while (address > PM_LEVEL_SIZE(domain->mode))
1345 increase_address_space(domain, gfp);
1346
1347 level = domain->mode - 1;
1348 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1349 address = PAGE_SIZE_ALIGN(address, page_size);
1350 end_lvl = PAGE_SIZE_LEVEL(page_size);
1351
1352 while (level > end_lvl) {
1353 u64 __pte, __npte;
1354
1355 __pte = *pte;
1356
1357 if (!IOMMU_PTE_PRESENT(__pte)) {
1358 page = (u64 *)get_zeroed_page(gfp);
1359 if (!page)
1360 return NULL;
1361
1362 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1363
1364 /* pte could have been changed somewhere. */
1365 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1366 free_page((unsigned long)page);
1367 continue;
1368 }
1369 }
1370
1371 /* No level skipping support yet */
1372 if (PM_PTE_LEVEL(*pte) != level)
1373 return NULL;
1374
1375 level -= 1;
1376
1377 pte = IOMMU_PTE_PAGE(*pte);
1378
1379 if (pte_page && level == end_lvl)
1380 *pte_page = pte;
1381
1382 pte = &pte[PM_LEVEL_INDEX(level, address)];
1383 }
1384
1385 return pte;
1386 }
1387
1388 /*
1389 * This function checks if there is a PTE for a given dma address. If
1390 * there is one, it returns the pointer to it.
1391 */
1392 static u64 *fetch_pte(struct protection_domain *domain,
1393 unsigned long address,
1394 unsigned long *page_size)
1395 {
1396 int level;
1397 u64 *pte;
1398
1399 if (address > PM_LEVEL_SIZE(domain->mode))
1400 return NULL;
1401
1402 level = domain->mode - 1;
1403 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1404 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1405
1406 while (level > 0) {
1407
1408 /* Not Present */
1409 if (!IOMMU_PTE_PRESENT(*pte))
1410 return NULL;
1411
1412 /* Large PTE */
1413 if (PM_PTE_LEVEL(*pte) == 7 ||
1414 PM_PTE_LEVEL(*pte) == 0)
1415 break;
1416
1417 /* No level skipping support yet */
1418 if (PM_PTE_LEVEL(*pte) != level)
1419 return NULL;
1420
1421 level -= 1;
1422
1423 /* Walk to the next level */
1424 pte = IOMMU_PTE_PAGE(*pte);
1425 pte = &pte[PM_LEVEL_INDEX(level, address)];
1426 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1427 }
1428
1429 if (PM_PTE_LEVEL(*pte) == 0x07) {
1430 unsigned long pte_mask;
1431
1432 /*
1433 * If we have a series of large PTEs, make
1434 * sure to return a pointer to the first one.
1435 */
1436 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1437 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1438 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1439 }
1440
1441 return pte;
1442 }
1443
1444 /*
1445 * Generic mapping functions. It maps a physical address into a DMA
1446 * address space. It allocates the page table pages if necessary.
1447 * In the future it can be extended to a generic mapping function
1448 * supporting all features of AMD IOMMU page tables like level skipping
1449 * and full 64 bit address spaces.
1450 */
1451 static int iommu_map_page(struct protection_domain *dom,
1452 unsigned long bus_addr,
1453 unsigned long phys_addr,
1454 unsigned long page_size,
1455 int prot,
1456 gfp_t gfp)
1457 {
1458 u64 __pte, *pte;
1459 int i, count;
1460
1461 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1462 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1463
1464 if (!(prot & IOMMU_PROT_MASK))
1465 return -EINVAL;
1466
1467 count = PAGE_SIZE_PTE_COUNT(page_size);
1468 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1469
1470 if (!pte)
1471 return -ENOMEM;
1472
1473 for (i = 0; i < count; ++i)
1474 if (IOMMU_PTE_PRESENT(pte[i]))
1475 return -EBUSY;
1476
1477 if (count > 1) {
1478 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1479 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1480 } else
1481 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1482
1483 if (prot & IOMMU_PROT_IR)
1484 __pte |= IOMMU_PTE_IR;
1485 if (prot & IOMMU_PROT_IW)
1486 __pte |= IOMMU_PTE_IW;
1487
1488 for (i = 0; i < count; ++i)
1489 pte[i] = __pte;
1490
1491 update_domain(dom);
1492
1493 return 0;
1494 }
1495
1496 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1497 unsigned long bus_addr,
1498 unsigned long page_size)
1499 {
1500 unsigned long long unmapped;
1501 unsigned long unmap_size;
1502 u64 *pte;
1503
1504 BUG_ON(!is_power_of_2(page_size));
1505
1506 unmapped = 0;
1507
1508 while (unmapped < page_size) {
1509
1510 pte = fetch_pte(dom, bus_addr, &unmap_size);
1511
1512 if (pte) {
1513 int i, count;
1514
1515 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1516 for (i = 0; i < count; i++)
1517 pte[i] = 0ULL;
1518 }
1519
1520 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1521 unmapped += unmap_size;
1522 }
1523
1524 BUG_ON(unmapped && !is_power_of_2(unmapped));
1525
1526 return unmapped;
1527 }
1528
1529 /****************************************************************************
1530 *
1531 * The next functions belong to the address allocator for the dma_ops
1532 * interface functions.
1533 *
1534 ****************************************************************************/
1535
1536
1537 static unsigned long dma_ops_alloc_iova(struct device *dev,
1538 struct dma_ops_domain *dma_dom,
1539 unsigned int pages, u64 dma_mask)
1540 {
1541 unsigned long pfn = 0;
1542
1543 pages = __roundup_pow_of_two(pages);
1544
1545 if (dma_mask > DMA_BIT_MASK(32))
1546 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1547 IOVA_PFN(DMA_BIT_MASK(32)));
1548
1549 if (!pfn)
1550 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1551
1552 return (pfn << PAGE_SHIFT);
1553 }
1554
1555 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1556 unsigned long address,
1557 unsigned int pages)
1558 {
1559 pages = __roundup_pow_of_two(pages);
1560 address >>= PAGE_SHIFT;
1561
1562 free_iova_fast(&dma_dom->iovad, address, pages);
1563 }
1564
1565 /****************************************************************************
1566 *
1567 * The next functions belong to the domain allocation. A domain is
1568 * allocated for every IOMMU as the default domain. If device isolation
1569 * is enabled, every device get its own domain. The most important thing
1570 * about domains is the page table mapping the DMA address space they
1571 * contain.
1572 *
1573 ****************************************************************************/
1574
1575 /*
1576 * This function adds a protection domain to the global protection domain list
1577 */
1578 static void add_domain_to_list(struct protection_domain *domain)
1579 {
1580 unsigned long flags;
1581
1582 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1583 list_add(&domain->list, &amd_iommu_pd_list);
1584 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1585 }
1586
1587 /*
1588 * This function removes a protection domain to the global
1589 * protection domain list
1590 */
1591 static void del_domain_from_list(struct protection_domain *domain)
1592 {
1593 unsigned long flags;
1594
1595 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1596 list_del(&domain->list);
1597 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1598 }
1599
1600 static u16 domain_id_alloc(void)
1601 {
1602 unsigned long flags;
1603 int id;
1604
1605 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1606 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1607 BUG_ON(id == 0);
1608 if (id > 0 && id < MAX_DOMAIN_ID)
1609 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1610 else
1611 id = 0;
1612 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1613
1614 return id;
1615 }
1616
1617 static void domain_id_free(int id)
1618 {
1619 unsigned long flags;
1620
1621 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1622 if (id > 0 && id < MAX_DOMAIN_ID)
1623 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1624 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1625 }
1626
1627 #define DEFINE_FREE_PT_FN(LVL, FN) \
1628 static void free_pt_##LVL (unsigned long __pt) \
1629 { \
1630 unsigned long p; \
1631 u64 *pt; \
1632 int i; \
1633 \
1634 pt = (u64 *)__pt; \
1635 \
1636 for (i = 0; i < 512; ++i) { \
1637 /* PTE present? */ \
1638 if (!IOMMU_PTE_PRESENT(pt[i])) \
1639 continue; \
1640 \
1641 /* Large PTE? */ \
1642 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1643 PM_PTE_LEVEL(pt[i]) == 7) \
1644 continue; \
1645 \
1646 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1647 FN(p); \
1648 } \
1649 free_page((unsigned long)pt); \
1650 }
1651
1652 DEFINE_FREE_PT_FN(l2, free_page)
1653 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1654 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1655 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1656 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1657
1658 static void free_pagetable(struct protection_domain *domain)
1659 {
1660 unsigned long root = (unsigned long)domain->pt_root;
1661
1662 switch (domain->mode) {
1663 case PAGE_MODE_NONE:
1664 break;
1665 case PAGE_MODE_1_LEVEL:
1666 free_page(root);
1667 break;
1668 case PAGE_MODE_2_LEVEL:
1669 free_pt_l2(root);
1670 break;
1671 case PAGE_MODE_3_LEVEL:
1672 free_pt_l3(root);
1673 break;
1674 case PAGE_MODE_4_LEVEL:
1675 free_pt_l4(root);
1676 break;
1677 case PAGE_MODE_5_LEVEL:
1678 free_pt_l5(root);
1679 break;
1680 case PAGE_MODE_6_LEVEL:
1681 free_pt_l6(root);
1682 break;
1683 default:
1684 BUG();
1685 }
1686 }
1687
1688 static void free_gcr3_tbl_level1(u64 *tbl)
1689 {
1690 u64 *ptr;
1691 int i;
1692
1693 for (i = 0; i < 512; ++i) {
1694 if (!(tbl[i] & GCR3_VALID))
1695 continue;
1696
1697 ptr = __va(tbl[i] & PAGE_MASK);
1698
1699 free_page((unsigned long)ptr);
1700 }
1701 }
1702
1703 static void free_gcr3_tbl_level2(u64 *tbl)
1704 {
1705 u64 *ptr;
1706 int i;
1707
1708 for (i = 0; i < 512; ++i) {
1709 if (!(tbl[i] & GCR3_VALID))
1710 continue;
1711
1712 ptr = __va(tbl[i] & PAGE_MASK);
1713
1714 free_gcr3_tbl_level1(ptr);
1715 }
1716 }
1717
1718 static void free_gcr3_table(struct protection_domain *domain)
1719 {
1720 if (domain->glx == 2)
1721 free_gcr3_tbl_level2(domain->gcr3_tbl);
1722 else if (domain->glx == 1)
1723 free_gcr3_tbl_level1(domain->gcr3_tbl);
1724 else
1725 BUG_ON(domain->glx != 0);
1726
1727 free_page((unsigned long)domain->gcr3_tbl);
1728 }
1729
1730 /*
1731 * Free a domain, only used if something went wrong in the
1732 * allocation path and we need to free an already allocated page table
1733 */
1734 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1735 {
1736 if (!dom)
1737 return;
1738
1739 del_domain_from_list(&dom->domain);
1740
1741 put_iova_domain(&dom->iovad);
1742
1743 free_pagetable(&dom->domain);
1744
1745 if (dom->domain.id)
1746 domain_id_free(dom->domain.id);
1747
1748 kfree(dom);
1749 }
1750
1751 /*
1752 * Allocates a new protection domain usable for the dma_ops functions.
1753 * It also initializes the page table and the address allocator data
1754 * structures required for the dma_ops interface
1755 */
1756 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1757 {
1758 struct dma_ops_domain *dma_dom;
1759
1760 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1761 if (!dma_dom)
1762 return NULL;
1763
1764 if (protection_domain_init(&dma_dom->domain))
1765 goto free_dma_dom;
1766
1767 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1768 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1769 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1770 if (!dma_dom->domain.pt_root)
1771 goto free_dma_dom;
1772
1773 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1774 IOVA_START_PFN, DMA_32BIT_PFN);
1775
1776 /* Initialize reserved ranges */
1777 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1778
1779 add_domain_to_list(&dma_dom->domain);
1780
1781 return dma_dom;
1782
1783 free_dma_dom:
1784 dma_ops_domain_free(dma_dom);
1785
1786 return NULL;
1787 }
1788
1789 /*
1790 * little helper function to check whether a given protection domain is a
1791 * dma_ops domain
1792 */
1793 static bool dma_ops_domain(struct protection_domain *domain)
1794 {
1795 return domain->flags & PD_DMA_OPS_MASK;
1796 }
1797
1798 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1799 {
1800 u64 pte_root = 0;
1801 u64 flags = 0;
1802
1803 if (domain->mode != PAGE_MODE_NONE)
1804 pte_root = virt_to_phys(domain->pt_root);
1805
1806 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1807 << DEV_ENTRY_MODE_SHIFT;
1808 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1809
1810 flags = amd_iommu_dev_table[devid].data[1];
1811
1812 if (ats)
1813 flags |= DTE_FLAG_IOTLB;
1814
1815 if (domain->flags & PD_IOMMUV2_MASK) {
1816 u64 gcr3 = __pa(domain->gcr3_tbl);
1817 u64 glx = domain->glx;
1818 u64 tmp;
1819
1820 pte_root |= DTE_FLAG_GV;
1821 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1822
1823 /* First mask out possible old values for GCR3 table */
1824 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1825 flags &= ~tmp;
1826
1827 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1828 flags &= ~tmp;
1829
1830 /* Encode GCR3 table into DTE */
1831 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1832 pte_root |= tmp;
1833
1834 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1835 flags |= tmp;
1836
1837 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1838 flags |= tmp;
1839 }
1840
1841 flags &= ~(0xffffUL);
1842 flags |= domain->id;
1843
1844 amd_iommu_dev_table[devid].data[1] = flags;
1845 amd_iommu_dev_table[devid].data[0] = pte_root;
1846 }
1847
1848 static void clear_dte_entry(u16 devid)
1849 {
1850 /* remove entry from the device table seen by the hardware */
1851 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1852 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1853
1854 amd_iommu_apply_erratum_63(devid);
1855 }
1856
1857 static void do_attach(struct iommu_dev_data *dev_data,
1858 struct protection_domain *domain)
1859 {
1860 struct amd_iommu *iommu;
1861 u16 alias;
1862 bool ats;
1863
1864 iommu = amd_iommu_rlookup_table[dev_data->devid];
1865 alias = dev_data->alias;
1866 ats = dev_data->ats.enabled;
1867
1868 /* Update data structures */
1869 dev_data->domain = domain;
1870 list_add(&dev_data->list, &domain->dev_list);
1871
1872 /* Do reference counting */
1873 domain->dev_iommu[iommu->index] += 1;
1874 domain->dev_cnt += 1;
1875
1876 /* Update device table */
1877 set_dte_entry(dev_data->devid, domain, ats);
1878 if (alias != dev_data->devid)
1879 set_dte_entry(alias, domain, ats);
1880
1881 device_flush_dte(dev_data);
1882 }
1883
1884 static void do_detach(struct iommu_dev_data *dev_data)
1885 {
1886 struct amd_iommu *iommu;
1887 u16 alias;
1888
1889 /*
1890 * First check if the device is still attached. It might already
1891 * be detached from its domain because the generic
1892 * iommu_detach_group code detached it and we try again here in
1893 * our alias handling.
1894 */
1895 if (!dev_data->domain)
1896 return;
1897
1898 iommu = amd_iommu_rlookup_table[dev_data->devid];
1899 alias = dev_data->alias;
1900
1901 /* decrease reference counters */
1902 dev_data->domain->dev_iommu[iommu->index] -= 1;
1903 dev_data->domain->dev_cnt -= 1;
1904
1905 /* Update data structures */
1906 dev_data->domain = NULL;
1907 list_del(&dev_data->list);
1908 clear_dte_entry(dev_data->devid);
1909 if (alias != dev_data->devid)
1910 clear_dte_entry(alias);
1911
1912 /* Flush the DTE entry */
1913 device_flush_dte(dev_data);
1914 }
1915
1916 /*
1917 * If a device is not yet associated with a domain, this function does
1918 * assigns it visible for the hardware
1919 */
1920 static int __attach_device(struct iommu_dev_data *dev_data,
1921 struct protection_domain *domain)
1922 {
1923 int ret;
1924
1925 /*
1926 * Must be called with IRQs disabled. Warn here to detect early
1927 * when its not.
1928 */
1929 WARN_ON(!irqs_disabled());
1930
1931 /* lock domain */
1932 spin_lock(&domain->lock);
1933
1934 ret = -EBUSY;
1935 if (dev_data->domain != NULL)
1936 goto out_unlock;
1937
1938 /* Attach alias group root */
1939 do_attach(dev_data, domain);
1940
1941 ret = 0;
1942
1943 out_unlock:
1944
1945 /* ready */
1946 spin_unlock(&domain->lock);
1947
1948 return ret;
1949 }
1950
1951
1952 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1953 {
1954 pci_disable_ats(pdev);
1955 pci_disable_pri(pdev);
1956 pci_disable_pasid(pdev);
1957 }
1958
1959 /* FIXME: Change generic reset-function to do the same */
1960 static int pri_reset_while_enabled(struct pci_dev *pdev)
1961 {
1962 u16 control;
1963 int pos;
1964
1965 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1966 if (!pos)
1967 return -EINVAL;
1968
1969 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1970 control |= PCI_PRI_CTRL_RESET;
1971 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1972
1973 return 0;
1974 }
1975
1976 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1977 {
1978 bool reset_enable;
1979 int reqs, ret;
1980
1981 /* FIXME: Hardcode number of outstanding requests for now */
1982 reqs = 32;
1983 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1984 reqs = 1;
1985 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1986
1987 /* Only allow access to user-accessible pages */
1988 ret = pci_enable_pasid(pdev, 0);
1989 if (ret)
1990 goto out_err;
1991
1992 /* First reset the PRI state of the device */
1993 ret = pci_reset_pri(pdev);
1994 if (ret)
1995 goto out_err;
1996
1997 /* Enable PRI */
1998 ret = pci_enable_pri(pdev, reqs);
1999 if (ret)
2000 goto out_err;
2001
2002 if (reset_enable) {
2003 ret = pri_reset_while_enabled(pdev);
2004 if (ret)
2005 goto out_err;
2006 }
2007
2008 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2009 if (ret)
2010 goto out_err;
2011
2012 return 0;
2013
2014 out_err:
2015 pci_disable_pri(pdev);
2016 pci_disable_pasid(pdev);
2017
2018 return ret;
2019 }
2020
2021 /* FIXME: Move this to PCI code */
2022 #define PCI_PRI_TLP_OFF (1 << 15)
2023
2024 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2025 {
2026 u16 status;
2027 int pos;
2028
2029 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2030 if (!pos)
2031 return false;
2032
2033 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2034
2035 return (status & PCI_PRI_TLP_OFF) ? true : false;
2036 }
2037
2038 /*
2039 * If a device is not yet associated with a domain, this function
2040 * assigns it visible for the hardware
2041 */
2042 static int attach_device(struct device *dev,
2043 struct protection_domain *domain)
2044 {
2045 struct pci_dev *pdev;
2046 struct iommu_dev_data *dev_data;
2047 unsigned long flags;
2048 int ret;
2049
2050 dev_data = get_dev_data(dev);
2051
2052 if (!dev_is_pci(dev))
2053 goto skip_ats_check;
2054
2055 pdev = to_pci_dev(dev);
2056 if (domain->flags & PD_IOMMUV2_MASK) {
2057 if (!dev_data->passthrough)
2058 return -EINVAL;
2059
2060 if (dev_data->iommu_v2) {
2061 if (pdev_iommuv2_enable(pdev) != 0)
2062 return -EINVAL;
2063
2064 dev_data->ats.enabled = true;
2065 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2066 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2067 }
2068 } else if (amd_iommu_iotlb_sup &&
2069 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2070 dev_data->ats.enabled = true;
2071 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2072 }
2073
2074 skip_ats_check:
2075 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2076 ret = __attach_device(dev_data, domain);
2077 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2078
2079 /*
2080 * We might boot into a crash-kernel here. The crashed kernel
2081 * left the caches in the IOMMU dirty. So we have to flush
2082 * here to evict all dirty stuff.
2083 */
2084 domain_flush_tlb_pde(domain);
2085
2086 return ret;
2087 }
2088
2089 /*
2090 * Removes a device from a protection domain (unlocked)
2091 */
2092 static void __detach_device(struct iommu_dev_data *dev_data)
2093 {
2094 struct protection_domain *domain;
2095
2096 /*
2097 * Must be called with IRQs disabled. Warn here to detect early
2098 * when its not.
2099 */
2100 WARN_ON(!irqs_disabled());
2101
2102 if (WARN_ON(!dev_data->domain))
2103 return;
2104
2105 domain = dev_data->domain;
2106
2107 spin_lock(&domain->lock);
2108
2109 do_detach(dev_data);
2110
2111 spin_unlock(&domain->lock);
2112 }
2113
2114 /*
2115 * Removes a device from a protection domain (with devtable_lock held)
2116 */
2117 static void detach_device(struct device *dev)
2118 {
2119 struct protection_domain *domain;
2120 struct iommu_dev_data *dev_data;
2121 unsigned long flags;
2122
2123 dev_data = get_dev_data(dev);
2124 domain = dev_data->domain;
2125
2126 /* lock device table */
2127 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2128 __detach_device(dev_data);
2129 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2130
2131 if (!dev_is_pci(dev))
2132 return;
2133
2134 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2135 pdev_iommuv2_disable(to_pci_dev(dev));
2136 else if (dev_data->ats.enabled)
2137 pci_disable_ats(to_pci_dev(dev));
2138
2139 dev_data->ats.enabled = false;
2140 }
2141
2142 static int amd_iommu_add_device(struct device *dev)
2143 {
2144 struct iommu_dev_data *dev_data;
2145 struct iommu_domain *domain;
2146 struct amd_iommu *iommu;
2147 int ret, devid;
2148
2149 if (!check_device(dev) || get_dev_data(dev))
2150 return 0;
2151
2152 devid = get_device_id(dev);
2153 if (devid < 0)
2154 return devid;
2155
2156 iommu = amd_iommu_rlookup_table[devid];
2157
2158 ret = iommu_init_device(dev);
2159 if (ret) {
2160 if (ret != -ENOTSUPP)
2161 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2162 dev_name(dev));
2163
2164 iommu_ignore_device(dev);
2165 dev->archdata.dma_ops = &nommu_dma_ops;
2166 goto out;
2167 }
2168 init_iommu_group(dev);
2169
2170 dev_data = get_dev_data(dev);
2171
2172 BUG_ON(!dev_data);
2173
2174 if (iommu_pass_through || dev_data->iommu_v2)
2175 iommu_request_dm_for_dev(dev);
2176
2177 /* Domains are initialized for this device - have a look what we ended up with */
2178 domain = iommu_get_domain_for_dev(dev);
2179 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2180 dev_data->passthrough = true;
2181 else
2182 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2183
2184 out:
2185 iommu_completion_wait(iommu);
2186
2187 return 0;
2188 }
2189
2190 static void amd_iommu_remove_device(struct device *dev)
2191 {
2192 struct amd_iommu *iommu;
2193 int devid;
2194
2195 if (!check_device(dev))
2196 return;
2197
2198 devid = get_device_id(dev);
2199 if (devid < 0)
2200 return;
2201
2202 iommu = amd_iommu_rlookup_table[devid];
2203
2204 iommu_uninit_device(dev);
2205 iommu_completion_wait(iommu);
2206 }
2207
2208 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2209 {
2210 if (dev_is_pci(dev))
2211 return pci_device_group(dev);
2212
2213 return acpihid_device_group(dev);
2214 }
2215
2216 /*****************************************************************************
2217 *
2218 * The next functions belong to the dma_ops mapping/unmapping code.
2219 *
2220 *****************************************************************************/
2221
2222 static void __queue_flush(struct flush_queue *queue)
2223 {
2224 struct protection_domain *domain;
2225 unsigned long flags;
2226 int idx;
2227
2228 /* First flush TLB of all known domains */
2229 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
2230 list_for_each_entry(domain, &amd_iommu_pd_list, list)
2231 domain_flush_tlb(domain);
2232 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
2233
2234 /* Wait until flushes have completed */
2235 domain_flush_complete(NULL);
2236
2237 for (idx = 0; idx < queue->next; ++idx) {
2238 struct flush_queue_entry *entry;
2239
2240 entry = queue->entries + idx;
2241
2242 free_iova_fast(&entry->dma_dom->iovad,
2243 entry->iova_pfn,
2244 entry->pages);
2245
2246 /* Not really necessary, just to make sure we catch any bugs */
2247 entry->dma_dom = NULL;
2248 }
2249
2250 queue->next = 0;
2251 }
2252
2253 static void queue_flush_all(void)
2254 {
2255 int cpu;
2256
2257 for_each_possible_cpu(cpu) {
2258 struct flush_queue *queue;
2259 unsigned long flags;
2260
2261 queue = per_cpu_ptr(&flush_queue, cpu);
2262 spin_lock_irqsave(&queue->lock, flags);
2263 if (queue->next > 0)
2264 __queue_flush(queue);
2265 spin_unlock_irqrestore(&queue->lock, flags);
2266 }
2267 }
2268
2269 static void queue_flush_timeout(unsigned long unsused)
2270 {
2271 atomic_set(&queue_timer_on, 0);
2272 queue_flush_all();
2273 }
2274
2275 static void queue_add(struct dma_ops_domain *dma_dom,
2276 unsigned long address, unsigned long pages)
2277 {
2278 struct flush_queue_entry *entry;
2279 struct flush_queue *queue;
2280 unsigned long flags;
2281 int idx;
2282
2283 pages = __roundup_pow_of_two(pages);
2284 address >>= PAGE_SHIFT;
2285
2286 queue = get_cpu_ptr(&flush_queue);
2287 spin_lock_irqsave(&queue->lock, flags);
2288
2289 if (queue->next == FLUSH_QUEUE_SIZE)
2290 __queue_flush(queue);
2291
2292 idx = queue->next++;
2293 entry = queue->entries + idx;
2294
2295 entry->iova_pfn = address;
2296 entry->pages = pages;
2297 entry->dma_dom = dma_dom;
2298
2299 spin_unlock_irqrestore(&queue->lock, flags);
2300
2301 if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0)
2302 mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10));
2303
2304 put_cpu_ptr(&flush_queue);
2305 }
2306
2307
2308 /*
2309 * In the dma_ops path we only have the struct device. This function
2310 * finds the corresponding IOMMU, the protection domain and the
2311 * requestor id for a given device.
2312 * If the device is not yet associated with a domain this is also done
2313 * in this function.
2314 */
2315 static struct protection_domain *get_domain(struct device *dev)
2316 {
2317 struct protection_domain *domain;
2318
2319 if (!check_device(dev))
2320 return ERR_PTR(-EINVAL);
2321
2322 domain = get_dev_data(dev)->domain;
2323 if (!dma_ops_domain(domain))
2324 return ERR_PTR(-EBUSY);
2325
2326 return domain;
2327 }
2328
2329 static void update_device_table(struct protection_domain *domain)
2330 {
2331 struct iommu_dev_data *dev_data;
2332
2333 list_for_each_entry(dev_data, &domain->dev_list, list) {
2334 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2335
2336 if (dev_data->devid == dev_data->alias)
2337 continue;
2338
2339 /* There is an alias, update device table entry for it */
2340 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
2341 }
2342 }
2343
2344 static void update_domain(struct protection_domain *domain)
2345 {
2346 if (!domain->updated)
2347 return;
2348
2349 update_device_table(domain);
2350
2351 domain_flush_devices(domain);
2352 domain_flush_tlb_pde(domain);
2353
2354 domain->updated = false;
2355 }
2356
2357 static int dir2prot(enum dma_data_direction direction)
2358 {
2359 if (direction == DMA_TO_DEVICE)
2360 return IOMMU_PROT_IR;
2361 else if (direction == DMA_FROM_DEVICE)
2362 return IOMMU_PROT_IW;
2363 else if (direction == DMA_BIDIRECTIONAL)
2364 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2365 else
2366 return 0;
2367 }
2368 /*
2369 * This function contains common code for mapping of a physically
2370 * contiguous memory region into DMA address space. It is used by all
2371 * mapping functions provided with this IOMMU driver.
2372 * Must be called with the domain lock held.
2373 */
2374 static dma_addr_t __map_single(struct device *dev,
2375 struct dma_ops_domain *dma_dom,
2376 phys_addr_t paddr,
2377 size_t size,
2378 enum dma_data_direction direction,
2379 u64 dma_mask)
2380 {
2381 dma_addr_t offset = paddr & ~PAGE_MASK;
2382 dma_addr_t address, start, ret;
2383 unsigned int pages;
2384 int prot = 0;
2385 int i;
2386
2387 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2388 paddr &= PAGE_MASK;
2389
2390 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2391 if (address == DMA_ERROR_CODE)
2392 goto out;
2393
2394 prot = dir2prot(direction);
2395
2396 start = address;
2397 for (i = 0; i < pages; ++i) {
2398 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2399 PAGE_SIZE, prot, GFP_ATOMIC);
2400 if (ret)
2401 goto out_unmap;
2402
2403 paddr += PAGE_SIZE;
2404 start += PAGE_SIZE;
2405 }
2406 address += offset;
2407
2408 if (unlikely(amd_iommu_np_cache)) {
2409 domain_flush_pages(&dma_dom->domain, address, size);
2410 domain_flush_complete(&dma_dom->domain);
2411 }
2412
2413 out:
2414 return address;
2415
2416 out_unmap:
2417
2418 for (--i; i >= 0; --i) {
2419 start -= PAGE_SIZE;
2420 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2421 }
2422
2423 domain_flush_tlb(&dma_dom->domain);
2424 domain_flush_complete(&dma_dom->domain);
2425
2426 dma_ops_free_iova(dma_dom, address, pages);
2427
2428 return DMA_ERROR_CODE;
2429 }
2430
2431 /*
2432 * Does the reverse of the __map_single function. Must be called with
2433 * the domain lock held too
2434 */
2435 static void __unmap_single(struct dma_ops_domain *dma_dom,
2436 dma_addr_t dma_addr,
2437 size_t size,
2438 int dir)
2439 {
2440 dma_addr_t flush_addr;
2441 dma_addr_t i, start;
2442 unsigned int pages;
2443
2444 flush_addr = dma_addr;
2445 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2446 dma_addr &= PAGE_MASK;
2447 start = dma_addr;
2448
2449 for (i = 0; i < pages; ++i) {
2450 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2451 start += PAGE_SIZE;
2452 }
2453
2454 if (amd_iommu_unmap_flush) {
2455 dma_ops_free_iova(dma_dom, dma_addr, pages);
2456 domain_flush_tlb(&dma_dom->domain);
2457 domain_flush_complete(&dma_dom->domain);
2458 } else {
2459 queue_add(dma_dom, dma_addr, pages);
2460 }
2461 }
2462
2463 /*
2464 * The exported map_single function for dma_ops.
2465 */
2466 static dma_addr_t map_page(struct device *dev, struct page *page,
2467 unsigned long offset, size_t size,
2468 enum dma_data_direction dir,
2469 unsigned long attrs)
2470 {
2471 phys_addr_t paddr = page_to_phys(page) + offset;
2472 struct protection_domain *domain;
2473 struct dma_ops_domain *dma_dom;
2474 u64 dma_mask;
2475
2476 domain = get_domain(dev);
2477 if (PTR_ERR(domain) == -EINVAL)
2478 return (dma_addr_t)paddr;
2479 else if (IS_ERR(domain))
2480 return DMA_ERROR_CODE;
2481
2482 dma_mask = *dev->dma_mask;
2483 dma_dom = to_dma_ops_domain(domain);
2484
2485 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2486 }
2487
2488 /*
2489 * The exported unmap_single function for dma_ops.
2490 */
2491 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2492 enum dma_data_direction dir, unsigned long attrs)
2493 {
2494 struct protection_domain *domain;
2495 struct dma_ops_domain *dma_dom;
2496
2497 domain = get_domain(dev);
2498 if (IS_ERR(domain))
2499 return;
2500
2501 dma_dom = to_dma_ops_domain(domain);
2502
2503 __unmap_single(dma_dom, dma_addr, size, dir);
2504 }
2505
2506 static int sg_num_pages(struct device *dev,
2507 struct scatterlist *sglist,
2508 int nelems)
2509 {
2510 unsigned long mask, boundary_size;
2511 struct scatterlist *s;
2512 int i, npages = 0;
2513
2514 mask = dma_get_seg_boundary(dev);
2515 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2516 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2517
2518 for_each_sg(sglist, s, nelems, i) {
2519 int p, n;
2520
2521 s->dma_address = npages << PAGE_SHIFT;
2522 p = npages % boundary_size;
2523 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2524 if (p + n > boundary_size)
2525 npages += boundary_size - p;
2526 npages += n;
2527 }
2528
2529 return npages;
2530 }
2531
2532 /*
2533 * The exported map_sg function for dma_ops (handles scatter-gather
2534 * lists).
2535 */
2536 static int map_sg(struct device *dev, struct scatterlist *sglist,
2537 int nelems, enum dma_data_direction direction,
2538 unsigned long attrs)
2539 {
2540 int mapped_pages = 0, npages = 0, prot = 0, i;
2541 struct protection_domain *domain;
2542 struct dma_ops_domain *dma_dom;
2543 struct scatterlist *s;
2544 unsigned long address;
2545 u64 dma_mask;
2546
2547 domain = get_domain(dev);
2548 if (IS_ERR(domain))
2549 return 0;
2550
2551 dma_dom = to_dma_ops_domain(domain);
2552 dma_mask = *dev->dma_mask;
2553
2554 npages = sg_num_pages(dev, sglist, nelems);
2555
2556 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2557 if (address == DMA_ERROR_CODE)
2558 goto out_err;
2559
2560 prot = dir2prot(direction);
2561
2562 /* Map all sg entries */
2563 for_each_sg(sglist, s, nelems, i) {
2564 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2565
2566 for (j = 0; j < pages; ++j) {
2567 unsigned long bus_addr, phys_addr;
2568 int ret;
2569
2570 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2571 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2572 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2573 if (ret)
2574 goto out_unmap;
2575
2576 mapped_pages += 1;
2577 }
2578 }
2579
2580 /* Everything is mapped - write the right values into s->dma_address */
2581 for_each_sg(sglist, s, nelems, i) {
2582 s->dma_address += address + s->offset;
2583 s->dma_length = s->length;
2584 }
2585
2586 return nelems;
2587
2588 out_unmap:
2589 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2590 dev_name(dev), npages);
2591
2592 for_each_sg(sglist, s, nelems, i) {
2593 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2594
2595 for (j = 0; j < pages; ++j) {
2596 unsigned long bus_addr;
2597
2598 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2599 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2600
2601 if (--mapped_pages)
2602 goto out_free_iova;
2603 }
2604 }
2605
2606 out_free_iova:
2607 free_iova_fast(&dma_dom->iovad, address, npages);
2608
2609 out_err:
2610 return 0;
2611 }
2612
2613 /*
2614 * The exported map_sg function for dma_ops (handles scatter-gather
2615 * lists).
2616 */
2617 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2618 int nelems, enum dma_data_direction dir,
2619 unsigned long attrs)
2620 {
2621 struct protection_domain *domain;
2622 struct dma_ops_domain *dma_dom;
2623 unsigned long startaddr;
2624 int npages = 2;
2625
2626 domain = get_domain(dev);
2627 if (IS_ERR(domain))
2628 return;
2629
2630 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2631 dma_dom = to_dma_ops_domain(domain);
2632 npages = sg_num_pages(dev, sglist, nelems);
2633
2634 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2635 }
2636
2637 /*
2638 * The exported alloc_coherent function for dma_ops.
2639 */
2640 static void *alloc_coherent(struct device *dev, size_t size,
2641 dma_addr_t *dma_addr, gfp_t flag,
2642 unsigned long attrs)
2643 {
2644 u64 dma_mask = dev->coherent_dma_mask;
2645 struct protection_domain *domain;
2646 struct dma_ops_domain *dma_dom;
2647 struct page *page;
2648
2649 domain = get_domain(dev);
2650 if (PTR_ERR(domain) == -EINVAL) {
2651 page = alloc_pages(flag, get_order(size));
2652 *dma_addr = page_to_phys(page);
2653 return page_address(page);
2654 } else if (IS_ERR(domain))
2655 return NULL;
2656
2657 dma_dom = to_dma_ops_domain(domain);
2658 size = PAGE_ALIGN(size);
2659 dma_mask = dev->coherent_dma_mask;
2660 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2661 flag |= __GFP_ZERO;
2662
2663 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2664 if (!page) {
2665 if (!gfpflags_allow_blocking(flag))
2666 return NULL;
2667
2668 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2669 get_order(size));
2670 if (!page)
2671 return NULL;
2672 }
2673
2674 if (!dma_mask)
2675 dma_mask = *dev->dma_mask;
2676
2677 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2678 size, DMA_BIDIRECTIONAL, dma_mask);
2679
2680 if (*dma_addr == DMA_ERROR_CODE)
2681 goto out_free;
2682
2683 return page_address(page);
2684
2685 out_free:
2686
2687 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2688 __free_pages(page, get_order(size));
2689
2690 return NULL;
2691 }
2692
2693 /*
2694 * The exported free_coherent function for dma_ops.
2695 */
2696 static void free_coherent(struct device *dev, size_t size,
2697 void *virt_addr, dma_addr_t dma_addr,
2698 unsigned long attrs)
2699 {
2700 struct protection_domain *domain;
2701 struct dma_ops_domain *dma_dom;
2702 struct page *page;
2703
2704 page = virt_to_page(virt_addr);
2705 size = PAGE_ALIGN(size);
2706
2707 domain = get_domain(dev);
2708 if (IS_ERR(domain))
2709 goto free_mem;
2710
2711 dma_dom = to_dma_ops_domain(domain);
2712
2713 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2714
2715 free_mem:
2716 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2717 __free_pages(page, get_order(size));
2718 }
2719
2720 /*
2721 * This function is called by the DMA layer to find out if we can handle a
2722 * particular device. It is part of the dma_ops.
2723 */
2724 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2725 {
2726 return check_device(dev);
2727 }
2728
2729 static struct dma_map_ops amd_iommu_dma_ops = {
2730 .alloc = alloc_coherent,
2731 .free = free_coherent,
2732 .map_page = map_page,
2733 .unmap_page = unmap_page,
2734 .map_sg = map_sg,
2735 .unmap_sg = unmap_sg,
2736 .dma_supported = amd_iommu_dma_supported,
2737 };
2738
2739 static int init_reserved_iova_ranges(void)
2740 {
2741 struct pci_dev *pdev = NULL;
2742 struct iova *val;
2743
2744 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2745 IOVA_START_PFN, DMA_32BIT_PFN);
2746
2747 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2748 &reserved_rbtree_key);
2749
2750 /* MSI memory range */
2751 val = reserve_iova(&reserved_iova_ranges,
2752 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2753 if (!val) {
2754 pr_err("Reserving MSI range failed\n");
2755 return -ENOMEM;
2756 }
2757
2758 /* HT memory range */
2759 val = reserve_iova(&reserved_iova_ranges,
2760 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2761 if (!val) {
2762 pr_err("Reserving HT range failed\n");
2763 return -ENOMEM;
2764 }
2765
2766 /*
2767 * Memory used for PCI resources
2768 * FIXME: Check whether we can reserve the PCI-hole completly
2769 */
2770 for_each_pci_dev(pdev) {
2771 int i;
2772
2773 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2774 struct resource *r = &pdev->resource[i];
2775
2776 if (!(r->flags & IORESOURCE_MEM))
2777 continue;
2778
2779 val = reserve_iova(&reserved_iova_ranges,
2780 IOVA_PFN(r->start),
2781 IOVA_PFN(r->end));
2782 if (!val) {
2783 pr_err("Reserve pci-resource range failed\n");
2784 return -ENOMEM;
2785 }
2786 }
2787 }
2788
2789 return 0;
2790 }
2791
2792 int __init amd_iommu_init_api(void)
2793 {
2794 int ret, cpu, err = 0;
2795
2796 ret = iova_cache_get();
2797 if (ret)
2798 return ret;
2799
2800 ret = init_reserved_iova_ranges();
2801 if (ret)
2802 return ret;
2803
2804 for_each_possible_cpu(cpu) {
2805 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2806
2807 queue->entries = kzalloc(FLUSH_QUEUE_SIZE *
2808 sizeof(*queue->entries),
2809 GFP_KERNEL);
2810 if (!queue->entries)
2811 goto out_put_iova;
2812
2813 spin_lock_init(&queue->lock);
2814 }
2815
2816 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2817 if (err)
2818 return err;
2819 #ifdef CONFIG_ARM_AMBA
2820 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2821 if (err)
2822 return err;
2823 #endif
2824 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2825 if (err)
2826 return err;
2827 return 0;
2828
2829 out_put_iova:
2830 for_each_possible_cpu(cpu) {
2831 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2832
2833 kfree(queue->entries);
2834 }
2835
2836 return -ENOMEM;
2837 }
2838
2839 int __init amd_iommu_init_dma_ops(void)
2840 {
2841 setup_timer(&queue_timer, queue_flush_timeout, 0);
2842 atomic_set(&queue_timer_on, 0);
2843
2844 swiotlb = iommu_pass_through ? 1 : 0;
2845 iommu_detected = 1;
2846
2847 /*
2848 * In case we don't initialize SWIOTLB (actually the common case
2849 * when AMD IOMMU is enabled), make sure there are global
2850 * dma_ops set as a fall-back for devices not handled by this
2851 * driver (for example non-PCI devices).
2852 */
2853 if (!swiotlb)
2854 dma_ops = &nommu_dma_ops;
2855
2856 if (amd_iommu_unmap_flush)
2857 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2858 else
2859 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2860
2861 return 0;
2862
2863 }
2864
2865 /*****************************************************************************
2866 *
2867 * The following functions belong to the exported interface of AMD IOMMU
2868 *
2869 * This interface allows access to lower level functions of the IOMMU
2870 * like protection domain handling and assignement of devices to domains
2871 * which is not possible with the dma_ops interface.
2872 *
2873 *****************************************************************************/
2874
2875 static void cleanup_domain(struct protection_domain *domain)
2876 {
2877 struct iommu_dev_data *entry;
2878 unsigned long flags;
2879
2880 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2881
2882 while (!list_empty(&domain->dev_list)) {
2883 entry = list_first_entry(&domain->dev_list,
2884 struct iommu_dev_data, list);
2885 __detach_device(entry);
2886 }
2887
2888 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2889 }
2890
2891 static void protection_domain_free(struct protection_domain *domain)
2892 {
2893 if (!domain)
2894 return;
2895
2896 del_domain_from_list(domain);
2897
2898 if (domain->id)
2899 domain_id_free(domain->id);
2900
2901 kfree(domain);
2902 }
2903
2904 static int protection_domain_init(struct protection_domain *domain)
2905 {
2906 spin_lock_init(&domain->lock);
2907 mutex_init(&domain->api_lock);
2908 domain->id = domain_id_alloc();
2909 if (!domain->id)
2910 return -ENOMEM;
2911 INIT_LIST_HEAD(&domain->dev_list);
2912
2913 return 0;
2914 }
2915
2916 static struct protection_domain *protection_domain_alloc(void)
2917 {
2918 struct protection_domain *domain;
2919
2920 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2921 if (!domain)
2922 return NULL;
2923
2924 if (protection_domain_init(domain))
2925 goto out_err;
2926
2927 add_domain_to_list(domain);
2928
2929 return domain;
2930
2931 out_err:
2932 kfree(domain);
2933
2934 return NULL;
2935 }
2936
2937 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2938 {
2939 struct protection_domain *pdomain;
2940 struct dma_ops_domain *dma_domain;
2941
2942 switch (type) {
2943 case IOMMU_DOMAIN_UNMANAGED:
2944 pdomain = protection_domain_alloc();
2945 if (!pdomain)
2946 return NULL;
2947
2948 pdomain->mode = PAGE_MODE_3_LEVEL;
2949 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2950 if (!pdomain->pt_root) {
2951 protection_domain_free(pdomain);
2952 return NULL;
2953 }
2954
2955 pdomain->domain.geometry.aperture_start = 0;
2956 pdomain->domain.geometry.aperture_end = ~0ULL;
2957 pdomain->domain.geometry.force_aperture = true;
2958
2959 break;
2960 case IOMMU_DOMAIN_DMA:
2961 dma_domain = dma_ops_domain_alloc();
2962 if (!dma_domain) {
2963 pr_err("AMD-Vi: Failed to allocate\n");
2964 return NULL;
2965 }
2966 pdomain = &dma_domain->domain;
2967 break;
2968 case IOMMU_DOMAIN_IDENTITY:
2969 pdomain = protection_domain_alloc();
2970 if (!pdomain)
2971 return NULL;
2972
2973 pdomain->mode = PAGE_MODE_NONE;
2974 break;
2975 default:
2976 return NULL;
2977 }
2978
2979 return &pdomain->domain;
2980 }
2981
2982 static void amd_iommu_domain_free(struct iommu_domain *dom)
2983 {
2984 struct protection_domain *domain;
2985 struct dma_ops_domain *dma_dom;
2986
2987 domain = to_pdomain(dom);
2988
2989 if (domain->dev_cnt > 0)
2990 cleanup_domain(domain);
2991
2992 BUG_ON(domain->dev_cnt != 0);
2993
2994 if (!dom)
2995 return;
2996
2997 switch (dom->type) {
2998 case IOMMU_DOMAIN_DMA:
2999 /*
3000 * First make sure the domain is no longer referenced from the
3001 * flush queue
3002 */
3003 queue_flush_all();
3004
3005 /* Now release the domain */
3006 dma_dom = to_dma_ops_domain(domain);
3007 dma_ops_domain_free(dma_dom);
3008 break;
3009 default:
3010 if (domain->mode != PAGE_MODE_NONE)
3011 free_pagetable(domain);
3012
3013 if (domain->flags & PD_IOMMUV2_MASK)
3014 free_gcr3_table(domain);
3015
3016 protection_domain_free(domain);
3017 break;
3018 }
3019 }
3020
3021 static void amd_iommu_detach_device(struct iommu_domain *dom,
3022 struct device *dev)
3023 {
3024 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3025 struct amd_iommu *iommu;
3026 int devid;
3027
3028 if (!check_device(dev))
3029 return;
3030
3031 devid = get_device_id(dev);
3032 if (devid < 0)
3033 return;
3034
3035 if (dev_data->domain != NULL)
3036 detach_device(dev);
3037
3038 iommu = amd_iommu_rlookup_table[devid];
3039 if (!iommu)
3040 return;
3041
3042 #ifdef CONFIG_IRQ_REMAP
3043 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3044 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3045 dev_data->use_vapic = 0;
3046 #endif
3047
3048 iommu_completion_wait(iommu);
3049 }
3050
3051 static int amd_iommu_attach_device(struct iommu_domain *dom,
3052 struct device *dev)
3053 {
3054 struct protection_domain *domain = to_pdomain(dom);
3055 struct iommu_dev_data *dev_data;
3056 struct amd_iommu *iommu;
3057 int ret;
3058
3059 if (!check_device(dev))
3060 return -EINVAL;
3061
3062 dev_data = dev->archdata.iommu;
3063
3064 iommu = amd_iommu_rlookup_table[dev_data->devid];
3065 if (!iommu)
3066 return -EINVAL;
3067
3068 if (dev_data->domain)
3069 detach_device(dev);
3070
3071 ret = attach_device(dev, domain);
3072
3073 #ifdef CONFIG_IRQ_REMAP
3074 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3075 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3076 dev_data->use_vapic = 1;
3077 else
3078 dev_data->use_vapic = 0;
3079 }
3080 #endif
3081
3082 iommu_completion_wait(iommu);
3083
3084 return ret;
3085 }
3086
3087 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3088 phys_addr_t paddr, size_t page_size, int iommu_prot)
3089 {
3090 struct protection_domain *domain = to_pdomain(dom);
3091 int prot = 0;
3092 int ret;
3093
3094 if (domain->mode == PAGE_MODE_NONE)
3095 return -EINVAL;
3096
3097 if (iommu_prot & IOMMU_READ)
3098 prot |= IOMMU_PROT_IR;
3099 if (iommu_prot & IOMMU_WRITE)
3100 prot |= IOMMU_PROT_IW;
3101
3102 mutex_lock(&domain->api_lock);
3103 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3104 mutex_unlock(&domain->api_lock);
3105
3106 return ret;
3107 }
3108
3109 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3110 size_t page_size)
3111 {
3112 struct protection_domain *domain = to_pdomain(dom);
3113 size_t unmap_size;
3114
3115 if (domain->mode == PAGE_MODE_NONE)
3116 return -EINVAL;
3117
3118 mutex_lock(&domain->api_lock);
3119 unmap_size = iommu_unmap_page(domain, iova, page_size);
3120 mutex_unlock(&domain->api_lock);
3121
3122 domain_flush_tlb_pde(domain);
3123
3124 return unmap_size;
3125 }
3126
3127 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3128 dma_addr_t iova)
3129 {
3130 struct protection_domain *domain = to_pdomain(dom);
3131 unsigned long offset_mask, pte_pgsize;
3132 u64 *pte, __pte;
3133
3134 if (domain->mode == PAGE_MODE_NONE)
3135 return iova;
3136
3137 pte = fetch_pte(domain, iova, &pte_pgsize);
3138
3139 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3140 return 0;
3141
3142 offset_mask = pte_pgsize - 1;
3143 __pte = *pte & PM_ADDR_MASK;
3144
3145 return (__pte & ~offset_mask) | (iova & offset_mask);
3146 }
3147
3148 static bool amd_iommu_capable(enum iommu_cap cap)
3149 {
3150 switch (cap) {
3151 case IOMMU_CAP_CACHE_COHERENCY:
3152 return true;
3153 case IOMMU_CAP_INTR_REMAP:
3154 return (irq_remapping_enabled == 1);
3155 case IOMMU_CAP_NOEXEC:
3156 return false;
3157 }
3158
3159 return false;
3160 }
3161
3162 static void amd_iommu_get_dm_regions(struct device *dev,
3163 struct list_head *head)
3164 {
3165 struct unity_map_entry *entry;
3166 int devid;
3167
3168 devid = get_device_id(dev);
3169 if (devid < 0)
3170 return;
3171
3172 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3173 struct iommu_dm_region *region;
3174
3175 if (devid < entry->devid_start || devid > entry->devid_end)
3176 continue;
3177
3178 region = kzalloc(sizeof(*region), GFP_KERNEL);
3179 if (!region) {
3180 pr_err("Out of memory allocating dm-regions for %s\n",
3181 dev_name(dev));
3182 return;
3183 }
3184
3185 region->start = entry->address_start;
3186 region->length = entry->address_end - entry->address_start;
3187 if (entry->prot & IOMMU_PROT_IR)
3188 region->prot |= IOMMU_READ;
3189 if (entry->prot & IOMMU_PROT_IW)
3190 region->prot |= IOMMU_WRITE;
3191
3192 list_add_tail(&region->list, head);
3193 }
3194 }
3195
3196 static void amd_iommu_put_dm_regions(struct device *dev,
3197 struct list_head *head)
3198 {
3199 struct iommu_dm_region *entry, *next;
3200
3201 list_for_each_entry_safe(entry, next, head, list)
3202 kfree(entry);
3203 }
3204
3205 static void amd_iommu_apply_dm_region(struct device *dev,
3206 struct iommu_domain *domain,
3207 struct iommu_dm_region *region)
3208 {
3209 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3210 unsigned long start, end;
3211
3212 start = IOVA_PFN(region->start);
3213 end = IOVA_PFN(region->start + region->length);
3214
3215 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3216 }
3217
3218 static const struct iommu_ops amd_iommu_ops = {
3219 .capable = amd_iommu_capable,
3220 .domain_alloc = amd_iommu_domain_alloc,
3221 .domain_free = amd_iommu_domain_free,
3222 .attach_dev = amd_iommu_attach_device,
3223 .detach_dev = amd_iommu_detach_device,
3224 .map = amd_iommu_map,
3225 .unmap = amd_iommu_unmap,
3226 .map_sg = default_iommu_map_sg,
3227 .iova_to_phys = amd_iommu_iova_to_phys,
3228 .add_device = amd_iommu_add_device,
3229 .remove_device = amd_iommu_remove_device,
3230 .device_group = amd_iommu_device_group,
3231 .get_dm_regions = amd_iommu_get_dm_regions,
3232 .put_dm_regions = amd_iommu_put_dm_regions,
3233 .apply_dm_region = amd_iommu_apply_dm_region,
3234 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3235 };
3236
3237 /*****************************************************************************
3238 *
3239 * The next functions do a basic initialization of IOMMU for pass through
3240 * mode
3241 *
3242 * In passthrough mode the IOMMU is initialized and enabled but not used for
3243 * DMA-API translation.
3244 *
3245 *****************************************************************************/
3246
3247 /* IOMMUv2 specific functions */
3248 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3249 {
3250 return atomic_notifier_chain_register(&ppr_notifier, nb);
3251 }
3252 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3253
3254 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3255 {
3256 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3257 }
3258 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3259
3260 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3261 {
3262 struct protection_domain *domain = to_pdomain(dom);
3263 unsigned long flags;
3264
3265 spin_lock_irqsave(&domain->lock, flags);
3266
3267 /* Update data structure */
3268 domain->mode = PAGE_MODE_NONE;
3269 domain->updated = true;
3270
3271 /* Make changes visible to IOMMUs */
3272 update_domain(domain);
3273
3274 /* Page-table is not visible to IOMMU anymore, so free it */
3275 free_pagetable(domain);
3276
3277 spin_unlock_irqrestore(&domain->lock, flags);
3278 }
3279 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3280
3281 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3282 {
3283 struct protection_domain *domain = to_pdomain(dom);
3284 unsigned long flags;
3285 int levels, ret;
3286
3287 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3288 return -EINVAL;
3289
3290 /* Number of GCR3 table levels required */
3291 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3292 levels += 1;
3293
3294 if (levels > amd_iommu_max_glx_val)
3295 return -EINVAL;
3296
3297 spin_lock_irqsave(&domain->lock, flags);
3298
3299 /*
3300 * Save us all sanity checks whether devices already in the
3301 * domain support IOMMUv2. Just force that the domain has no
3302 * devices attached when it is switched into IOMMUv2 mode.
3303 */
3304 ret = -EBUSY;
3305 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3306 goto out;
3307
3308 ret = -ENOMEM;
3309 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3310 if (domain->gcr3_tbl == NULL)
3311 goto out;
3312
3313 domain->glx = levels;
3314 domain->flags |= PD_IOMMUV2_MASK;
3315 domain->updated = true;
3316
3317 update_domain(domain);
3318
3319 ret = 0;
3320
3321 out:
3322 spin_unlock_irqrestore(&domain->lock, flags);
3323
3324 return ret;
3325 }
3326 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3327
3328 static int __flush_pasid(struct protection_domain *domain, int pasid,
3329 u64 address, bool size)
3330 {
3331 struct iommu_dev_data *dev_data;
3332 struct iommu_cmd cmd;
3333 int i, ret;
3334
3335 if (!(domain->flags & PD_IOMMUV2_MASK))
3336 return -EINVAL;
3337
3338 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3339
3340 /*
3341 * IOMMU TLB needs to be flushed before Device TLB to
3342 * prevent device TLB refill from IOMMU TLB
3343 */
3344 for (i = 0; i < amd_iommus_present; ++i) {
3345 if (domain->dev_iommu[i] == 0)
3346 continue;
3347
3348 ret = iommu_queue_command(amd_iommus[i], &cmd);
3349 if (ret != 0)
3350 goto out;
3351 }
3352
3353 /* Wait until IOMMU TLB flushes are complete */
3354 domain_flush_complete(domain);
3355
3356 /* Now flush device TLBs */
3357 list_for_each_entry(dev_data, &domain->dev_list, list) {
3358 struct amd_iommu *iommu;
3359 int qdep;
3360
3361 /*
3362 There might be non-IOMMUv2 capable devices in an IOMMUv2
3363 * domain.
3364 */
3365 if (!dev_data->ats.enabled)
3366 continue;
3367
3368 qdep = dev_data->ats.qdep;
3369 iommu = amd_iommu_rlookup_table[dev_data->devid];
3370
3371 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3372 qdep, address, size);
3373
3374 ret = iommu_queue_command(iommu, &cmd);
3375 if (ret != 0)
3376 goto out;
3377 }
3378
3379 /* Wait until all device TLBs are flushed */
3380 domain_flush_complete(domain);
3381
3382 ret = 0;
3383
3384 out:
3385
3386 return ret;
3387 }
3388
3389 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3390 u64 address)
3391 {
3392 return __flush_pasid(domain, pasid, address, false);
3393 }
3394
3395 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3396 u64 address)
3397 {
3398 struct protection_domain *domain = to_pdomain(dom);
3399 unsigned long flags;
3400 int ret;
3401
3402 spin_lock_irqsave(&domain->lock, flags);
3403 ret = __amd_iommu_flush_page(domain, pasid, address);
3404 spin_unlock_irqrestore(&domain->lock, flags);
3405
3406 return ret;
3407 }
3408 EXPORT_SYMBOL(amd_iommu_flush_page);
3409
3410 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3411 {
3412 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3413 true);
3414 }
3415
3416 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3417 {
3418 struct protection_domain *domain = to_pdomain(dom);
3419 unsigned long flags;
3420 int ret;
3421
3422 spin_lock_irqsave(&domain->lock, flags);
3423 ret = __amd_iommu_flush_tlb(domain, pasid);
3424 spin_unlock_irqrestore(&domain->lock, flags);
3425
3426 return ret;
3427 }
3428 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3429
3430 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3431 {
3432 int index;
3433 u64 *pte;
3434
3435 while (true) {
3436
3437 index = (pasid >> (9 * level)) & 0x1ff;
3438 pte = &root[index];
3439
3440 if (level == 0)
3441 break;
3442
3443 if (!(*pte & GCR3_VALID)) {
3444 if (!alloc)
3445 return NULL;
3446
3447 root = (void *)get_zeroed_page(GFP_ATOMIC);
3448 if (root == NULL)
3449 return NULL;
3450
3451 *pte = __pa(root) | GCR3_VALID;
3452 }
3453
3454 root = __va(*pte & PAGE_MASK);
3455
3456 level -= 1;
3457 }
3458
3459 return pte;
3460 }
3461
3462 static int __set_gcr3(struct protection_domain *domain, int pasid,
3463 unsigned long cr3)
3464 {
3465 u64 *pte;
3466
3467 if (domain->mode != PAGE_MODE_NONE)
3468 return -EINVAL;
3469
3470 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3471 if (pte == NULL)
3472 return -ENOMEM;
3473
3474 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3475
3476 return __amd_iommu_flush_tlb(domain, pasid);
3477 }
3478
3479 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3480 {
3481 u64 *pte;
3482
3483 if (domain->mode != PAGE_MODE_NONE)
3484 return -EINVAL;
3485
3486 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3487 if (pte == NULL)
3488 return 0;
3489
3490 *pte = 0;
3491
3492 return __amd_iommu_flush_tlb(domain, pasid);
3493 }
3494
3495 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3496 unsigned long cr3)
3497 {
3498 struct protection_domain *domain = to_pdomain(dom);
3499 unsigned long flags;
3500 int ret;
3501
3502 spin_lock_irqsave(&domain->lock, flags);
3503 ret = __set_gcr3(domain, pasid, cr3);
3504 spin_unlock_irqrestore(&domain->lock, flags);
3505
3506 return ret;
3507 }
3508 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3509
3510 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3511 {
3512 struct protection_domain *domain = to_pdomain(dom);
3513 unsigned long flags;
3514 int ret;
3515
3516 spin_lock_irqsave(&domain->lock, flags);
3517 ret = __clear_gcr3(domain, pasid);
3518 spin_unlock_irqrestore(&domain->lock, flags);
3519
3520 return ret;
3521 }
3522 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3523
3524 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3525 int status, int tag)
3526 {
3527 struct iommu_dev_data *dev_data;
3528 struct amd_iommu *iommu;
3529 struct iommu_cmd cmd;
3530
3531 dev_data = get_dev_data(&pdev->dev);
3532 iommu = amd_iommu_rlookup_table[dev_data->devid];
3533
3534 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3535 tag, dev_data->pri_tlp);
3536
3537 return iommu_queue_command(iommu, &cmd);
3538 }
3539 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3540
3541 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3542 {
3543 struct protection_domain *pdomain;
3544
3545 pdomain = get_domain(&pdev->dev);
3546 if (IS_ERR(pdomain))
3547 return NULL;
3548
3549 /* Only return IOMMUv2 domains */
3550 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3551 return NULL;
3552
3553 return &pdomain->domain;
3554 }
3555 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3556
3557 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3558 {
3559 struct iommu_dev_data *dev_data;
3560
3561 if (!amd_iommu_v2_supported())
3562 return;
3563
3564 dev_data = get_dev_data(&pdev->dev);
3565 dev_data->errata |= (1 << erratum);
3566 }
3567 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3568
3569 int amd_iommu_device_info(struct pci_dev *pdev,
3570 struct amd_iommu_device_info *info)
3571 {
3572 int max_pasids;
3573 int pos;
3574
3575 if (pdev == NULL || info == NULL)
3576 return -EINVAL;
3577
3578 if (!amd_iommu_v2_supported())
3579 return -EINVAL;
3580
3581 memset(info, 0, sizeof(*info));
3582
3583 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3584 if (pos)
3585 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3586
3587 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3588 if (pos)
3589 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3590
3591 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3592 if (pos) {
3593 int features;
3594
3595 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3596 max_pasids = min(max_pasids, (1 << 20));
3597
3598 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3599 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3600
3601 features = pci_pasid_features(pdev);
3602 if (features & PCI_PASID_CAP_EXEC)
3603 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3604 if (features & PCI_PASID_CAP_PRIV)
3605 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3606 }
3607
3608 return 0;
3609 }
3610 EXPORT_SYMBOL(amd_iommu_device_info);
3611
3612 #ifdef CONFIG_IRQ_REMAP
3613
3614 /*****************************************************************************
3615 *
3616 * Interrupt Remapping Implementation
3617 *
3618 *****************************************************************************/
3619
3620 static struct irq_chip amd_ir_chip;
3621
3622 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3623 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3624 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3625 #define DTE_IRQ_REMAP_ENABLE 1ULL
3626
3627 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3628 {
3629 u64 dte;
3630
3631 dte = amd_iommu_dev_table[devid].data[2];
3632 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3633 dte |= virt_to_phys(table->table);
3634 dte |= DTE_IRQ_REMAP_INTCTL;
3635 dte |= DTE_IRQ_TABLE_LEN;
3636 dte |= DTE_IRQ_REMAP_ENABLE;
3637
3638 amd_iommu_dev_table[devid].data[2] = dte;
3639 }
3640
3641 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3642 {
3643 struct irq_remap_table *table = NULL;
3644 struct amd_iommu *iommu;
3645 unsigned long flags;
3646 u16 alias;
3647
3648 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3649
3650 iommu = amd_iommu_rlookup_table[devid];
3651 if (!iommu)
3652 goto out_unlock;
3653
3654 table = irq_lookup_table[devid];
3655 if (table)
3656 goto out_unlock;
3657
3658 alias = amd_iommu_alias_table[devid];
3659 table = irq_lookup_table[alias];
3660 if (table) {
3661 irq_lookup_table[devid] = table;
3662 set_dte_irq_entry(devid, table);
3663 iommu_flush_dte(iommu, devid);
3664 goto out;
3665 }
3666
3667 /* Nothing there yet, allocate new irq remapping table */
3668 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3669 if (!table)
3670 goto out_unlock;
3671
3672 /* Initialize table spin-lock */
3673 spin_lock_init(&table->lock);
3674
3675 if (ioapic)
3676 /* Keep the first 32 indexes free for IOAPIC interrupts */
3677 table->min_index = 32;
3678
3679 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3680 if (!table->table) {
3681 kfree(table);
3682 table = NULL;
3683 goto out_unlock;
3684 }
3685
3686 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3687 memset(table->table, 0,
3688 MAX_IRQS_PER_TABLE * sizeof(u32));
3689 else
3690 memset(table->table, 0,
3691 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3692
3693 if (ioapic) {
3694 int i;
3695
3696 for (i = 0; i < 32; ++i)
3697 iommu->irte_ops->set_allocated(table, i);
3698 }
3699
3700 irq_lookup_table[devid] = table;
3701 set_dte_irq_entry(devid, table);
3702 iommu_flush_dte(iommu, devid);
3703 if (devid != alias) {
3704 irq_lookup_table[alias] = table;
3705 set_dte_irq_entry(alias, table);
3706 iommu_flush_dte(iommu, alias);
3707 }
3708
3709 out:
3710 iommu_completion_wait(iommu);
3711
3712 out_unlock:
3713 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3714
3715 return table;
3716 }
3717
3718 static int alloc_irq_index(u16 devid, int count)
3719 {
3720 struct irq_remap_table *table;
3721 unsigned long flags;
3722 int index, c;
3723 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3724
3725 if (!iommu)
3726 return -ENODEV;
3727
3728 table = get_irq_table(devid, false);
3729 if (!table)
3730 return -ENODEV;
3731
3732 spin_lock_irqsave(&table->lock, flags);
3733
3734 /* Scan table for free entries */
3735 for (c = 0, index = table->min_index;
3736 index < MAX_IRQS_PER_TABLE;
3737 ++index) {
3738 if (!iommu->irte_ops->is_allocated(table, index))
3739 c += 1;
3740 else
3741 c = 0;
3742
3743 if (c == count) {
3744 for (; c != 0; --c)
3745 iommu->irte_ops->set_allocated(table, index - c + 1);
3746
3747 index -= count - 1;
3748 goto out;
3749 }
3750 }
3751
3752 index = -ENOSPC;
3753
3754 out:
3755 spin_unlock_irqrestore(&table->lock, flags);
3756
3757 return index;
3758 }
3759
3760 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3761 struct amd_ir_data *data)
3762 {
3763 struct irq_remap_table *table;
3764 struct amd_iommu *iommu;
3765 unsigned long flags;
3766 struct irte_ga *entry;
3767
3768 iommu = amd_iommu_rlookup_table[devid];
3769 if (iommu == NULL)
3770 return -EINVAL;
3771
3772 table = get_irq_table(devid, false);
3773 if (!table)
3774 return -ENOMEM;
3775
3776 spin_lock_irqsave(&table->lock, flags);
3777
3778 entry = (struct irte_ga *)table->table;
3779 entry = &entry[index];
3780 entry->lo.fields_remap.valid = 0;
3781 entry->hi.val = irte->hi.val;
3782 entry->lo.val = irte->lo.val;
3783 entry->lo.fields_remap.valid = 1;
3784 if (data)
3785 data->ref = entry;
3786
3787 spin_unlock_irqrestore(&table->lock, flags);
3788
3789 iommu_flush_irt(iommu, devid);
3790 iommu_completion_wait(iommu);
3791
3792 return 0;
3793 }
3794
3795 static int modify_irte(u16 devid, int index, union irte *irte)
3796 {
3797 struct irq_remap_table *table;
3798 struct amd_iommu *iommu;
3799 unsigned long flags;
3800
3801 iommu = amd_iommu_rlookup_table[devid];
3802 if (iommu == NULL)
3803 return -EINVAL;
3804
3805 table = get_irq_table(devid, false);
3806 if (!table)
3807 return -ENOMEM;
3808
3809 spin_lock_irqsave(&table->lock, flags);
3810 table->table[index] = irte->val;
3811 spin_unlock_irqrestore(&table->lock, flags);
3812
3813 iommu_flush_irt(iommu, devid);
3814 iommu_completion_wait(iommu);
3815
3816 return 0;
3817 }
3818
3819 static void free_irte(u16 devid, int index)
3820 {
3821 struct irq_remap_table *table;
3822 struct amd_iommu *iommu;
3823 unsigned long flags;
3824
3825 iommu = amd_iommu_rlookup_table[devid];
3826 if (iommu == NULL)
3827 return;
3828
3829 table = get_irq_table(devid, false);
3830 if (!table)
3831 return;
3832
3833 spin_lock_irqsave(&table->lock, flags);
3834 iommu->irte_ops->clear_allocated(table, index);
3835 spin_unlock_irqrestore(&table->lock, flags);
3836
3837 iommu_flush_irt(iommu, devid);
3838 iommu_completion_wait(iommu);
3839 }
3840
3841 static void irte_prepare(void *entry,
3842 u32 delivery_mode, u32 dest_mode,
3843 u8 vector, u32 dest_apicid, int devid)
3844 {
3845 union irte *irte = (union irte *) entry;
3846
3847 irte->val = 0;
3848 irte->fields.vector = vector;
3849 irte->fields.int_type = delivery_mode;
3850 irte->fields.destination = dest_apicid;
3851 irte->fields.dm = dest_mode;
3852 irte->fields.valid = 1;
3853 }
3854
3855 static void irte_ga_prepare(void *entry,
3856 u32 delivery_mode, u32 dest_mode,
3857 u8 vector, u32 dest_apicid, int devid)
3858 {
3859 struct irte_ga *irte = (struct irte_ga *) entry;
3860 struct iommu_dev_data *dev_data = search_dev_data(devid);
3861
3862 irte->lo.val = 0;
3863 irte->hi.val = 0;
3864 irte->lo.fields_remap.guest_mode = dev_data ? dev_data->use_vapic : 0;
3865 irte->lo.fields_remap.int_type = delivery_mode;
3866 irte->lo.fields_remap.dm = dest_mode;
3867 irte->hi.fields.vector = vector;
3868 irte->lo.fields_remap.destination = dest_apicid;
3869 irte->lo.fields_remap.valid = 1;
3870 }
3871
3872 static void irte_activate(void *entry, u16 devid, u16 index)
3873 {
3874 union irte *irte = (union irte *) entry;
3875
3876 irte->fields.valid = 1;
3877 modify_irte(devid, index, irte);
3878 }
3879
3880 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3881 {
3882 struct irte_ga *irte = (struct irte_ga *) entry;
3883
3884 irte->lo.fields_remap.valid = 1;
3885 modify_irte_ga(devid, index, irte, NULL);
3886 }
3887
3888 static void irte_deactivate(void *entry, u16 devid, u16 index)
3889 {
3890 union irte *irte = (union irte *) entry;
3891
3892 irte->fields.valid = 0;
3893 modify_irte(devid, index, irte);
3894 }
3895
3896 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3897 {
3898 struct irte_ga *irte = (struct irte_ga *) entry;
3899
3900 irte->lo.fields_remap.valid = 0;
3901 modify_irte_ga(devid, index, irte, NULL);
3902 }
3903
3904 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3905 u8 vector, u32 dest_apicid)
3906 {
3907 union irte *irte = (union irte *) entry;
3908
3909 irte->fields.vector = vector;
3910 irte->fields.destination = dest_apicid;
3911 modify_irte(devid, index, irte);
3912 }
3913
3914 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3915 u8 vector, u32 dest_apicid)
3916 {
3917 struct irte_ga *irte = (struct irte_ga *) entry;
3918 struct iommu_dev_data *dev_data = search_dev_data(devid);
3919
3920 if (!dev_data || !dev_data->use_vapic) {
3921 irte->hi.fields.vector = vector;
3922 irte->lo.fields_remap.destination = dest_apicid;
3923 irte->lo.fields_remap.guest_mode = 0;
3924 modify_irte_ga(devid, index, irte, NULL);
3925 }
3926 }
3927
3928 #define IRTE_ALLOCATED (~1U)
3929 static void irte_set_allocated(struct irq_remap_table *table, int index)
3930 {
3931 table->table[index] = IRTE_ALLOCATED;
3932 }
3933
3934 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3935 {
3936 struct irte_ga *ptr = (struct irte_ga *)table->table;
3937 struct irte_ga *irte = &ptr[index];
3938
3939 memset(&irte->lo.val, 0, sizeof(u64));
3940 memset(&irte->hi.val, 0, sizeof(u64));
3941 irte->hi.fields.vector = 0xff;
3942 }
3943
3944 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3945 {
3946 union irte *ptr = (union irte *)table->table;
3947 union irte *irte = &ptr[index];
3948
3949 return irte->val != 0;
3950 }
3951
3952 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3953 {
3954 struct irte_ga *ptr = (struct irte_ga *)table->table;
3955 struct irte_ga *irte = &ptr[index];
3956
3957 return irte->hi.fields.vector != 0;
3958 }
3959
3960 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3961 {
3962 table->table[index] = 0;
3963 }
3964
3965 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3966 {
3967 struct irte_ga *ptr = (struct irte_ga *)table->table;
3968 struct irte_ga *irte = &ptr[index];
3969
3970 memset(&irte->lo.val, 0, sizeof(u64));
3971 memset(&irte->hi.val, 0, sizeof(u64));
3972 }
3973
3974 static int get_devid(struct irq_alloc_info *info)
3975 {
3976 int devid = -1;
3977
3978 switch (info->type) {
3979 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3980 devid = get_ioapic_devid(info->ioapic_id);
3981 break;
3982 case X86_IRQ_ALLOC_TYPE_HPET:
3983 devid = get_hpet_devid(info->hpet_id);
3984 break;
3985 case X86_IRQ_ALLOC_TYPE_MSI:
3986 case X86_IRQ_ALLOC_TYPE_MSIX:
3987 devid = get_device_id(&info->msi_dev->dev);
3988 break;
3989 default:
3990 BUG_ON(1);
3991 break;
3992 }
3993
3994 return devid;
3995 }
3996
3997 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3998 {
3999 struct amd_iommu *iommu;
4000 int devid;
4001
4002 if (!info)
4003 return NULL;
4004
4005 devid = get_devid(info);
4006 if (devid >= 0) {
4007 iommu = amd_iommu_rlookup_table[devid];
4008 if (iommu)
4009 return iommu->ir_domain;
4010 }
4011
4012 return NULL;
4013 }
4014
4015 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4016 {
4017 struct amd_iommu *iommu;
4018 int devid;
4019
4020 if (!info)
4021 return NULL;
4022
4023 switch (info->type) {
4024 case X86_IRQ_ALLOC_TYPE_MSI:
4025 case X86_IRQ_ALLOC_TYPE_MSIX:
4026 devid = get_device_id(&info->msi_dev->dev);
4027 if (devid < 0)
4028 return NULL;
4029
4030 iommu = amd_iommu_rlookup_table[devid];
4031 if (iommu)
4032 return iommu->msi_domain;
4033 break;
4034 default:
4035 break;
4036 }
4037
4038 return NULL;
4039 }
4040
4041 struct irq_remap_ops amd_iommu_irq_ops = {
4042 .prepare = amd_iommu_prepare,
4043 .enable = amd_iommu_enable,
4044 .disable = amd_iommu_disable,
4045 .reenable = amd_iommu_reenable,
4046 .enable_faulting = amd_iommu_enable_faulting,
4047 .get_ir_irq_domain = get_ir_irq_domain,
4048 .get_irq_domain = get_irq_domain,
4049 };
4050
4051 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4052 struct irq_cfg *irq_cfg,
4053 struct irq_alloc_info *info,
4054 int devid, int index, int sub_handle)
4055 {
4056 struct irq_2_irte *irte_info = &data->irq_2_irte;
4057 struct msi_msg *msg = &data->msi_entry;
4058 struct IO_APIC_route_entry *entry;
4059 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4060
4061 if (!iommu)
4062 return;
4063
4064 data->irq_2_irte.devid = devid;
4065 data->irq_2_irte.index = index + sub_handle;
4066 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4067 apic->irq_dest_mode, irq_cfg->vector,
4068 irq_cfg->dest_apicid, devid);
4069
4070 switch (info->type) {
4071 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4072 /* Setup IOAPIC entry */
4073 entry = info->ioapic_entry;
4074 info->ioapic_entry = NULL;
4075 memset(entry, 0, sizeof(*entry));
4076 entry->vector = index;
4077 entry->mask = 0;
4078 entry->trigger = info->ioapic_trigger;
4079 entry->polarity = info->ioapic_polarity;
4080 /* Mask level triggered irqs. */
4081 if (info->ioapic_trigger)
4082 entry->mask = 1;
4083 break;
4084
4085 case X86_IRQ_ALLOC_TYPE_HPET:
4086 case X86_IRQ_ALLOC_TYPE_MSI:
4087 case X86_IRQ_ALLOC_TYPE_MSIX:
4088 msg->address_hi = MSI_ADDR_BASE_HI;
4089 msg->address_lo = MSI_ADDR_BASE_LO;
4090 msg->data = irte_info->index;
4091 break;
4092
4093 default:
4094 BUG_ON(1);
4095 break;
4096 }
4097 }
4098
4099 struct amd_irte_ops irte_32_ops = {
4100 .prepare = irte_prepare,
4101 .activate = irte_activate,
4102 .deactivate = irte_deactivate,
4103 .set_affinity = irte_set_affinity,
4104 .set_allocated = irte_set_allocated,
4105 .is_allocated = irte_is_allocated,
4106 .clear_allocated = irte_clear_allocated,
4107 };
4108
4109 struct amd_irte_ops irte_128_ops = {
4110 .prepare = irte_ga_prepare,
4111 .activate = irte_ga_activate,
4112 .deactivate = irte_ga_deactivate,
4113 .set_affinity = irte_ga_set_affinity,
4114 .set_allocated = irte_ga_set_allocated,
4115 .is_allocated = irte_ga_is_allocated,
4116 .clear_allocated = irte_ga_clear_allocated,
4117 };
4118
4119 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4120 unsigned int nr_irqs, void *arg)
4121 {
4122 struct irq_alloc_info *info = arg;
4123 struct irq_data *irq_data;
4124 struct amd_ir_data *data = NULL;
4125 struct irq_cfg *cfg;
4126 int i, ret, devid;
4127 int index = -1;
4128
4129 if (!info)
4130 return -EINVAL;
4131 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4132 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4133 return -EINVAL;
4134
4135 /*
4136 * With IRQ remapping enabled, don't need contiguous CPU vectors
4137 * to support multiple MSI interrupts.
4138 */
4139 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4140 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4141
4142 devid = get_devid(info);
4143 if (devid < 0)
4144 return -EINVAL;
4145
4146 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4147 if (ret < 0)
4148 return ret;
4149
4150 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4151 if (get_irq_table(devid, true))
4152 index = info->ioapic_pin;
4153 else
4154 ret = -ENOMEM;
4155 } else {
4156 index = alloc_irq_index(devid, nr_irqs);
4157 }
4158 if (index < 0) {
4159 pr_warn("Failed to allocate IRTE\n");
4160 ret = index;
4161 goto out_free_parent;
4162 }
4163
4164 for (i = 0; i < nr_irqs; i++) {
4165 irq_data = irq_domain_get_irq_data(domain, virq + i);
4166 cfg = irqd_cfg(irq_data);
4167 if (!irq_data || !cfg) {
4168 ret = -EINVAL;
4169 goto out_free_data;
4170 }
4171
4172 ret = -ENOMEM;
4173 data = kzalloc(sizeof(*data), GFP_KERNEL);
4174 if (!data)
4175 goto out_free_data;
4176
4177 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4178 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4179 else
4180 data->entry = kzalloc(sizeof(struct irte_ga),
4181 GFP_KERNEL);
4182 if (!data->entry) {
4183 kfree(data);
4184 goto out_free_data;
4185 }
4186
4187 irq_data->hwirq = (devid << 16) + i;
4188 irq_data->chip_data = data;
4189 irq_data->chip = &amd_ir_chip;
4190 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4191 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4192 }
4193
4194 return 0;
4195
4196 out_free_data:
4197 for (i--; i >= 0; i--) {
4198 irq_data = irq_domain_get_irq_data(domain, virq + i);
4199 if (irq_data)
4200 kfree(irq_data->chip_data);
4201 }
4202 for (i = 0; i < nr_irqs; i++)
4203 free_irte(devid, index + i);
4204 out_free_parent:
4205 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4206 return ret;
4207 }
4208
4209 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4210 unsigned int nr_irqs)
4211 {
4212 struct irq_2_irte *irte_info;
4213 struct irq_data *irq_data;
4214 struct amd_ir_data *data;
4215 int i;
4216
4217 for (i = 0; i < nr_irqs; i++) {
4218 irq_data = irq_domain_get_irq_data(domain, virq + i);
4219 if (irq_data && irq_data->chip_data) {
4220 data = irq_data->chip_data;
4221 irte_info = &data->irq_2_irte;
4222 free_irte(irte_info->devid, irte_info->index);
4223 kfree(data->entry);
4224 kfree(data);
4225 }
4226 }
4227 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4228 }
4229
4230 static void irq_remapping_activate(struct irq_domain *domain,
4231 struct irq_data *irq_data)
4232 {
4233 struct amd_ir_data *data = irq_data->chip_data;
4234 struct irq_2_irte *irte_info = &data->irq_2_irte;
4235 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4236
4237 if (iommu)
4238 iommu->irte_ops->activate(data->entry, irte_info->devid,
4239 irte_info->index);
4240 }
4241
4242 static void irq_remapping_deactivate(struct irq_domain *domain,
4243 struct irq_data *irq_data)
4244 {
4245 struct amd_ir_data *data = irq_data->chip_data;
4246 struct irq_2_irte *irte_info = &data->irq_2_irte;
4247 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4248
4249 if (iommu)
4250 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4251 irte_info->index);
4252 }
4253
4254 static struct irq_domain_ops amd_ir_domain_ops = {
4255 .alloc = irq_remapping_alloc,
4256 .free = irq_remapping_free,
4257 .activate = irq_remapping_activate,
4258 .deactivate = irq_remapping_deactivate,
4259 };
4260
4261 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4262 {
4263 struct amd_iommu *iommu;
4264 struct amd_iommu_pi_data *pi_data = vcpu_info;
4265 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4266 struct amd_ir_data *ir_data = data->chip_data;
4267 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4268 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4269 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4270
4271 /* Note:
4272 * This device has never been set up for guest mode.
4273 * we should not modify the IRTE
4274 */
4275 if (!dev_data || !dev_data->use_vapic)
4276 return 0;
4277
4278 pi_data->ir_data = ir_data;
4279
4280 /* Note:
4281 * SVM tries to set up for VAPIC mode, but we are in
4282 * legacy mode. So, we force legacy mode instead.
4283 */
4284 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4285 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4286 __func__);
4287 pi_data->is_guest_mode = false;
4288 }
4289
4290 iommu = amd_iommu_rlookup_table[irte_info->devid];
4291 if (iommu == NULL)
4292 return -EINVAL;
4293
4294 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4295 if (pi_data->is_guest_mode) {
4296 /* Setting */
4297 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4298 irte->hi.fields.vector = vcpu_pi_info->vector;
4299 irte->lo.fields_vapic.guest_mode = 1;
4300 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4301
4302 ir_data->cached_ga_tag = pi_data->ga_tag;
4303 } else {
4304 /* Un-Setting */
4305 struct irq_cfg *cfg = irqd_cfg(data);
4306
4307 irte->hi.val = 0;
4308 irte->lo.val = 0;
4309 irte->hi.fields.vector = cfg->vector;
4310 irte->lo.fields_remap.guest_mode = 0;
4311 irte->lo.fields_remap.destination = cfg->dest_apicid;
4312 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4313 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4314
4315 /*
4316 * This communicates the ga_tag back to the caller
4317 * so that it can do all the necessary clean up.
4318 */
4319 ir_data->cached_ga_tag = 0;
4320 }
4321
4322 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4323 }
4324
4325 static int amd_ir_set_affinity(struct irq_data *data,
4326 const struct cpumask *mask, bool force)
4327 {
4328 struct amd_ir_data *ir_data = data->chip_data;
4329 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4330 struct irq_cfg *cfg = irqd_cfg(data);
4331 struct irq_data *parent = data->parent_data;
4332 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4333 int ret;
4334
4335 if (!iommu)
4336 return -ENODEV;
4337
4338 ret = parent->chip->irq_set_affinity(parent, mask, force);
4339 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4340 return ret;
4341
4342 /*
4343 * Atomically updates the IRTE with the new destination, vector
4344 * and flushes the interrupt entry cache.
4345 */
4346 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4347 irte_info->index, cfg->vector, cfg->dest_apicid);
4348
4349 /*
4350 * After this point, all the interrupts will start arriving
4351 * at the new destination. So, time to cleanup the previous
4352 * vector allocation.
4353 */
4354 send_cleanup_vector(cfg);
4355
4356 return IRQ_SET_MASK_OK_DONE;
4357 }
4358
4359 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4360 {
4361 struct amd_ir_data *ir_data = irq_data->chip_data;
4362
4363 *msg = ir_data->msi_entry;
4364 }
4365
4366 static struct irq_chip amd_ir_chip = {
4367 .irq_ack = ir_ack_apic_edge,
4368 .irq_set_affinity = amd_ir_set_affinity,
4369 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4370 .irq_compose_msi_msg = ir_compose_msi_msg,
4371 };
4372
4373 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4374 {
4375 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4376 if (!iommu->ir_domain)
4377 return -ENOMEM;
4378
4379 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4380 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4381
4382 return 0;
4383 }
4384
4385 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4386 {
4387 unsigned long flags;
4388 struct amd_iommu *iommu;
4389 struct irq_remap_table *irt;
4390 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4391 int devid = ir_data->irq_2_irte.devid;
4392 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4393 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4394
4395 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4396 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4397 return 0;
4398
4399 iommu = amd_iommu_rlookup_table[devid];
4400 if (!iommu)
4401 return -ENODEV;
4402
4403 irt = get_irq_table(devid, false);
4404 if (!irt)
4405 return -ENODEV;
4406
4407 spin_lock_irqsave(&irt->lock, flags);
4408
4409 if (ref->lo.fields_vapic.guest_mode) {
4410 if (cpu >= 0)
4411 ref->lo.fields_vapic.destination = cpu;
4412 ref->lo.fields_vapic.is_run = is_run;
4413 barrier();
4414 }
4415
4416 spin_unlock_irqrestore(&irt->lock, flags);
4417
4418 iommu_flush_irt(iommu, devid);
4419 iommu_completion_wait(iommu);
4420 return 0;
4421 }
4422 EXPORT_SYMBOL(amd_iommu_update_ga);
4423 #endif
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