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KVM: VMX: Read & store IDT_VECTORING_INFO_FIELD
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "kvm.h"
19 #include "x86.h"
20 #include "x86_emulate.h"
21 #include "irq.h"
22 #include "vmx.h"
23 #include "segment_descriptor.h"
24
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/mm.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31
32 #include <asm/io.h>
33 #include <asm/desc.h>
34
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
37
38 static int bypass_guest_pf = 1;
39 module_param(bypass_guest_pf, bool, 0);
40
41 struct vmcs {
42 u32 revision_id;
43 u32 abort;
44 char data[0];
45 };
46
47 struct vcpu_vmx {
48 struct kvm_vcpu vcpu;
49 int launched;
50 u8 fail;
51 u32 idt_vectoring_info;
52 struct kvm_msr_entry *guest_msrs;
53 struct kvm_msr_entry *host_msrs;
54 int nmsrs;
55 int save_nmsrs;
56 int msr_offset_efer;
57 #ifdef CONFIG_X86_64
58 int msr_offset_kernel_gs_base;
59 #endif
60 struct vmcs *vmcs;
61 struct {
62 int loaded;
63 u16 fs_sel, gs_sel, ldt_sel;
64 int gs_ldt_reload_needed;
65 int fs_reload_needed;
66 int guest_efer_loaded;
67 } host_state;
68
69 };
70
71 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
72 {
73 return container_of(vcpu, struct vcpu_vmx, vcpu);
74 }
75
76 static int init_rmode_tss(struct kvm *kvm);
77
78 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
79 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
80
81 static struct page *vmx_io_bitmap_a;
82 static struct page *vmx_io_bitmap_b;
83
84 static struct vmcs_config {
85 int size;
86 int order;
87 u32 revision_id;
88 u32 pin_based_exec_ctrl;
89 u32 cpu_based_exec_ctrl;
90 u32 cpu_based_2nd_exec_ctrl;
91 u32 vmexit_ctrl;
92 u32 vmentry_ctrl;
93 } vmcs_config;
94
95 #define VMX_SEGMENT_FIELD(seg) \
96 [VCPU_SREG_##seg] = { \
97 .selector = GUEST_##seg##_SELECTOR, \
98 .base = GUEST_##seg##_BASE, \
99 .limit = GUEST_##seg##_LIMIT, \
100 .ar_bytes = GUEST_##seg##_AR_BYTES, \
101 }
102
103 static struct kvm_vmx_segment_field {
104 unsigned selector;
105 unsigned base;
106 unsigned limit;
107 unsigned ar_bytes;
108 } kvm_vmx_segment_fields[] = {
109 VMX_SEGMENT_FIELD(CS),
110 VMX_SEGMENT_FIELD(DS),
111 VMX_SEGMENT_FIELD(ES),
112 VMX_SEGMENT_FIELD(FS),
113 VMX_SEGMENT_FIELD(GS),
114 VMX_SEGMENT_FIELD(SS),
115 VMX_SEGMENT_FIELD(TR),
116 VMX_SEGMENT_FIELD(LDTR),
117 };
118
119 /*
120 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
121 * away by decrementing the array size.
122 */
123 static const u32 vmx_msr_index[] = {
124 #ifdef CONFIG_X86_64
125 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
126 #endif
127 MSR_EFER, MSR_K6_STAR,
128 };
129 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
130
131 static void load_msrs(struct kvm_msr_entry *e, int n)
132 {
133 int i;
134
135 for (i = 0; i < n; ++i)
136 wrmsrl(e[i].index, e[i].data);
137 }
138
139 static void save_msrs(struct kvm_msr_entry *e, int n)
140 {
141 int i;
142
143 for (i = 0; i < n; ++i)
144 rdmsrl(e[i].index, e[i].data);
145 }
146
147 static inline int is_page_fault(u32 intr_info)
148 {
149 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
150 INTR_INFO_VALID_MASK)) ==
151 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
152 }
153
154 static inline int is_no_device(u32 intr_info)
155 {
156 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
157 INTR_INFO_VALID_MASK)) ==
158 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
159 }
160
161 static inline int is_invalid_opcode(u32 intr_info)
162 {
163 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
164 INTR_INFO_VALID_MASK)) ==
165 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
166 }
167
168 static inline int is_external_interrupt(u32 intr_info)
169 {
170 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
171 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
172 }
173
174 static inline int cpu_has_vmx_tpr_shadow(void)
175 {
176 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
177 }
178
179 static inline int vm_need_tpr_shadow(struct kvm *kvm)
180 {
181 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
182 }
183
184 static inline int cpu_has_secondary_exec_ctrls(void)
185 {
186 return (vmcs_config.cpu_based_exec_ctrl &
187 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
188 }
189
190 static inline int vm_need_secondary_exec_ctrls(struct kvm *kvm)
191 {
192 return ((cpu_has_secondary_exec_ctrls()) && (irqchip_in_kernel(kvm)));
193 }
194
195 static inline int cpu_has_vmx_virtualize_apic_accesses(void)
196 {
197 return (vmcs_config.cpu_based_2nd_exec_ctrl &
198 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
199 }
200
201 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
202 {
203 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
204 (irqchip_in_kernel(kvm)));
205 }
206
207 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
208 {
209 int i;
210
211 for (i = 0; i < vmx->nmsrs; ++i)
212 if (vmx->guest_msrs[i].index == msr)
213 return i;
214 return -1;
215 }
216
217 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
218 {
219 int i;
220
221 i = __find_msr_index(vmx, msr);
222 if (i >= 0)
223 return &vmx->guest_msrs[i];
224 return NULL;
225 }
226
227 static void vmcs_clear(struct vmcs *vmcs)
228 {
229 u64 phys_addr = __pa(vmcs);
230 u8 error;
231
232 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
233 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
234 : "cc", "memory");
235 if (error)
236 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
237 vmcs, phys_addr);
238 }
239
240 static void __vcpu_clear(void *arg)
241 {
242 struct vcpu_vmx *vmx = arg;
243 int cpu = raw_smp_processor_id();
244
245 if (vmx->vcpu.cpu == cpu)
246 vmcs_clear(vmx->vmcs);
247 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
248 per_cpu(current_vmcs, cpu) = NULL;
249 rdtscll(vmx->vcpu.host_tsc);
250 }
251
252 static void vcpu_clear(struct vcpu_vmx *vmx)
253 {
254 if (vmx->vcpu.cpu == -1)
255 return;
256 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
257 vmx->launched = 0;
258 }
259
260 static unsigned long vmcs_readl(unsigned long field)
261 {
262 unsigned long value;
263
264 asm volatile (ASM_VMX_VMREAD_RDX_RAX
265 : "=a"(value) : "d"(field) : "cc");
266 return value;
267 }
268
269 static u16 vmcs_read16(unsigned long field)
270 {
271 return vmcs_readl(field);
272 }
273
274 static u32 vmcs_read32(unsigned long field)
275 {
276 return vmcs_readl(field);
277 }
278
279 static u64 vmcs_read64(unsigned long field)
280 {
281 #ifdef CONFIG_X86_64
282 return vmcs_readl(field);
283 #else
284 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
285 #endif
286 }
287
288 static noinline void vmwrite_error(unsigned long field, unsigned long value)
289 {
290 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
291 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
292 dump_stack();
293 }
294
295 static void vmcs_writel(unsigned long field, unsigned long value)
296 {
297 u8 error;
298
299 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
300 : "=q"(error) : "a"(value), "d"(field) : "cc");
301 if (unlikely(error))
302 vmwrite_error(field, value);
303 }
304
305 static void vmcs_write16(unsigned long field, u16 value)
306 {
307 vmcs_writel(field, value);
308 }
309
310 static void vmcs_write32(unsigned long field, u32 value)
311 {
312 vmcs_writel(field, value);
313 }
314
315 static void vmcs_write64(unsigned long field, u64 value)
316 {
317 #ifdef CONFIG_X86_64
318 vmcs_writel(field, value);
319 #else
320 vmcs_writel(field, value);
321 asm volatile ("");
322 vmcs_writel(field+1, value >> 32);
323 #endif
324 }
325
326 static void vmcs_clear_bits(unsigned long field, u32 mask)
327 {
328 vmcs_writel(field, vmcs_readl(field) & ~mask);
329 }
330
331 static void vmcs_set_bits(unsigned long field, u32 mask)
332 {
333 vmcs_writel(field, vmcs_readl(field) | mask);
334 }
335
336 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
337 {
338 u32 eb;
339
340 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
341 if (!vcpu->fpu_active)
342 eb |= 1u << NM_VECTOR;
343 if (vcpu->guest_debug.enabled)
344 eb |= 1u << 1;
345 if (vcpu->rmode.active)
346 eb = ~0;
347 vmcs_write32(EXCEPTION_BITMAP, eb);
348 }
349
350 static void reload_tss(void)
351 {
352 #ifndef CONFIG_X86_64
353
354 /*
355 * VT restores TR but not its size. Useless.
356 */
357 struct descriptor_table gdt;
358 struct segment_descriptor *descs;
359
360 get_gdt(&gdt);
361 descs = (void *)gdt.base;
362 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
363 load_TR_desc();
364 #endif
365 }
366
367 static void load_transition_efer(struct vcpu_vmx *vmx)
368 {
369 int efer_offset = vmx->msr_offset_efer;
370 u64 host_efer = vmx->host_msrs[efer_offset].data;
371 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
372 u64 ignore_bits;
373
374 if (efer_offset < 0)
375 return;
376 /*
377 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
378 * outside long mode
379 */
380 ignore_bits = EFER_NX | EFER_SCE;
381 #ifdef CONFIG_X86_64
382 ignore_bits |= EFER_LMA | EFER_LME;
383 /* SCE is meaningful only in long mode on Intel */
384 if (guest_efer & EFER_LMA)
385 ignore_bits &= ~(u64)EFER_SCE;
386 #endif
387 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
388 return;
389
390 vmx->host_state.guest_efer_loaded = 1;
391 guest_efer &= ~ignore_bits;
392 guest_efer |= host_efer & ignore_bits;
393 wrmsrl(MSR_EFER, guest_efer);
394 vmx->vcpu.stat.efer_reload++;
395 }
396
397 static void reload_host_efer(struct vcpu_vmx *vmx)
398 {
399 if (vmx->host_state.guest_efer_loaded) {
400 vmx->host_state.guest_efer_loaded = 0;
401 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
402 }
403 }
404
405 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
406 {
407 struct vcpu_vmx *vmx = to_vmx(vcpu);
408
409 if (vmx->host_state.loaded)
410 return;
411
412 vmx->host_state.loaded = 1;
413 /*
414 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
415 * allow segment selectors with cpl > 0 or ti == 1.
416 */
417 vmx->host_state.ldt_sel = read_ldt();
418 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
419 vmx->host_state.fs_sel = read_fs();
420 if (!(vmx->host_state.fs_sel & 7)) {
421 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
422 vmx->host_state.fs_reload_needed = 0;
423 } else {
424 vmcs_write16(HOST_FS_SELECTOR, 0);
425 vmx->host_state.fs_reload_needed = 1;
426 }
427 vmx->host_state.gs_sel = read_gs();
428 if (!(vmx->host_state.gs_sel & 7))
429 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
430 else {
431 vmcs_write16(HOST_GS_SELECTOR, 0);
432 vmx->host_state.gs_ldt_reload_needed = 1;
433 }
434
435 #ifdef CONFIG_X86_64
436 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
437 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
438 #else
439 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
440 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
441 #endif
442
443 #ifdef CONFIG_X86_64
444 if (is_long_mode(&vmx->vcpu))
445 save_msrs(vmx->host_msrs +
446 vmx->msr_offset_kernel_gs_base, 1);
447
448 #endif
449 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
450 load_transition_efer(vmx);
451 }
452
453 static void vmx_load_host_state(struct vcpu_vmx *vmx)
454 {
455 unsigned long flags;
456
457 if (!vmx->host_state.loaded)
458 return;
459
460 vmx->host_state.loaded = 0;
461 if (vmx->host_state.fs_reload_needed)
462 load_fs(vmx->host_state.fs_sel);
463 if (vmx->host_state.gs_ldt_reload_needed) {
464 load_ldt(vmx->host_state.ldt_sel);
465 /*
466 * If we have to reload gs, we must take care to
467 * preserve our gs base.
468 */
469 local_irq_save(flags);
470 load_gs(vmx->host_state.gs_sel);
471 #ifdef CONFIG_X86_64
472 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
473 #endif
474 local_irq_restore(flags);
475 }
476 reload_tss();
477 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
478 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
479 reload_host_efer(vmx);
480 }
481
482 /*
483 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
484 * vcpu mutex is already taken.
485 */
486 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
487 {
488 struct vcpu_vmx *vmx = to_vmx(vcpu);
489 u64 phys_addr = __pa(vmx->vmcs);
490 u64 tsc_this, delta;
491
492 if (vcpu->cpu != cpu) {
493 vcpu_clear(vmx);
494 kvm_migrate_apic_timer(vcpu);
495 }
496
497 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
498 u8 error;
499
500 per_cpu(current_vmcs, cpu) = vmx->vmcs;
501 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
502 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
503 : "cc");
504 if (error)
505 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
506 vmx->vmcs, phys_addr);
507 }
508
509 if (vcpu->cpu != cpu) {
510 struct descriptor_table dt;
511 unsigned long sysenter_esp;
512
513 vcpu->cpu = cpu;
514 /*
515 * Linux uses per-cpu TSS and GDT, so set these when switching
516 * processors.
517 */
518 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
519 get_gdt(&dt);
520 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
521
522 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
523 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
524
525 /*
526 * Make sure the time stamp counter is monotonous.
527 */
528 rdtscll(tsc_this);
529 delta = vcpu->host_tsc - tsc_this;
530 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
531 }
532 }
533
534 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
535 {
536 vmx_load_host_state(to_vmx(vcpu));
537 kvm_put_guest_fpu(vcpu);
538 }
539
540 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
541 {
542 if (vcpu->fpu_active)
543 return;
544 vcpu->fpu_active = 1;
545 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
546 if (vcpu->cr0 & X86_CR0_TS)
547 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
548 update_exception_bitmap(vcpu);
549 }
550
551 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
552 {
553 if (!vcpu->fpu_active)
554 return;
555 vcpu->fpu_active = 0;
556 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
557 update_exception_bitmap(vcpu);
558 }
559
560 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
561 {
562 vcpu_clear(to_vmx(vcpu));
563 }
564
565 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
566 {
567 return vmcs_readl(GUEST_RFLAGS);
568 }
569
570 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
571 {
572 if (vcpu->rmode.active)
573 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
574 vmcs_writel(GUEST_RFLAGS, rflags);
575 }
576
577 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
578 {
579 unsigned long rip;
580 u32 interruptibility;
581
582 rip = vmcs_readl(GUEST_RIP);
583 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
584 vmcs_writel(GUEST_RIP, rip);
585
586 /*
587 * We emulated an instruction, so temporary interrupt blocking
588 * should be removed, if set.
589 */
590 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
591 if (interruptibility & 3)
592 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
593 interruptibility & ~3);
594 vcpu->interrupt_window_open = 1;
595 }
596
597 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
598 {
599 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
600 vmcs_readl(GUEST_RIP));
601 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
602 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
603 GP_VECTOR |
604 INTR_TYPE_EXCEPTION |
605 INTR_INFO_DELIEVER_CODE_MASK |
606 INTR_INFO_VALID_MASK);
607 }
608
609 static void vmx_inject_ud(struct kvm_vcpu *vcpu)
610 {
611 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
612 UD_VECTOR |
613 INTR_TYPE_EXCEPTION |
614 INTR_INFO_VALID_MASK);
615 }
616
617 /*
618 * Swap MSR entry in host/guest MSR entry array.
619 */
620 #ifdef CONFIG_X86_64
621 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
622 {
623 struct kvm_msr_entry tmp;
624
625 tmp = vmx->guest_msrs[to];
626 vmx->guest_msrs[to] = vmx->guest_msrs[from];
627 vmx->guest_msrs[from] = tmp;
628 tmp = vmx->host_msrs[to];
629 vmx->host_msrs[to] = vmx->host_msrs[from];
630 vmx->host_msrs[from] = tmp;
631 }
632 #endif
633
634 /*
635 * Set up the vmcs to automatically save and restore system
636 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
637 * mode, as fiddling with msrs is very expensive.
638 */
639 static void setup_msrs(struct vcpu_vmx *vmx)
640 {
641 int save_nmsrs;
642
643 save_nmsrs = 0;
644 #ifdef CONFIG_X86_64
645 if (is_long_mode(&vmx->vcpu)) {
646 int index;
647
648 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
649 if (index >= 0)
650 move_msr_up(vmx, index, save_nmsrs++);
651 index = __find_msr_index(vmx, MSR_LSTAR);
652 if (index >= 0)
653 move_msr_up(vmx, index, save_nmsrs++);
654 index = __find_msr_index(vmx, MSR_CSTAR);
655 if (index >= 0)
656 move_msr_up(vmx, index, save_nmsrs++);
657 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
658 if (index >= 0)
659 move_msr_up(vmx, index, save_nmsrs++);
660 /*
661 * MSR_K6_STAR is only needed on long mode guests, and only
662 * if efer.sce is enabled.
663 */
664 index = __find_msr_index(vmx, MSR_K6_STAR);
665 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
666 move_msr_up(vmx, index, save_nmsrs++);
667 }
668 #endif
669 vmx->save_nmsrs = save_nmsrs;
670
671 #ifdef CONFIG_X86_64
672 vmx->msr_offset_kernel_gs_base =
673 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
674 #endif
675 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
676 }
677
678 /*
679 * reads and returns guest's timestamp counter "register"
680 * guest_tsc = host_tsc + tsc_offset -- 21.3
681 */
682 static u64 guest_read_tsc(void)
683 {
684 u64 host_tsc, tsc_offset;
685
686 rdtscll(host_tsc);
687 tsc_offset = vmcs_read64(TSC_OFFSET);
688 return host_tsc + tsc_offset;
689 }
690
691 /*
692 * writes 'guest_tsc' into guest's timestamp counter "register"
693 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
694 */
695 static void guest_write_tsc(u64 guest_tsc)
696 {
697 u64 host_tsc;
698
699 rdtscll(host_tsc);
700 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
701 }
702
703 /*
704 * Reads an msr value (of 'msr_index') into 'pdata'.
705 * Returns 0 on success, non-0 otherwise.
706 * Assumes vcpu_load() was already called.
707 */
708 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
709 {
710 u64 data;
711 struct kvm_msr_entry *msr;
712
713 if (!pdata) {
714 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
715 return -EINVAL;
716 }
717
718 switch (msr_index) {
719 #ifdef CONFIG_X86_64
720 case MSR_FS_BASE:
721 data = vmcs_readl(GUEST_FS_BASE);
722 break;
723 case MSR_GS_BASE:
724 data = vmcs_readl(GUEST_GS_BASE);
725 break;
726 case MSR_EFER:
727 return kvm_get_msr_common(vcpu, msr_index, pdata);
728 #endif
729 case MSR_IA32_TIME_STAMP_COUNTER:
730 data = guest_read_tsc();
731 break;
732 case MSR_IA32_SYSENTER_CS:
733 data = vmcs_read32(GUEST_SYSENTER_CS);
734 break;
735 case MSR_IA32_SYSENTER_EIP:
736 data = vmcs_readl(GUEST_SYSENTER_EIP);
737 break;
738 case MSR_IA32_SYSENTER_ESP:
739 data = vmcs_readl(GUEST_SYSENTER_ESP);
740 break;
741 default:
742 msr = find_msr_entry(to_vmx(vcpu), msr_index);
743 if (msr) {
744 data = msr->data;
745 break;
746 }
747 return kvm_get_msr_common(vcpu, msr_index, pdata);
748 }
749
750 *pdata = data;
751 return 0;
752 }
753
754 /*
755 * Writes msr value into into the appropriate "register".
756 * Returns 0 on success, non-0 otherwise.
757 * Assumes vcpu_load() was already called.
758 */
759 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
760 {
761 struct vcpu_vmx *vmx = to_vmx(vcpu);
762 struct kvm_msr_entry *msr;
763 int ret = 0;
764
765 switch (msr_index) {
766 #ifdef CONFIG_X86_64
767 case MSR_EFER:
768 ret = kvm_set_msr_common(vcpu, msr_index, data);
769 if (vmx->host_state.loaded) {
770 reload_host_efer(vmx);
771 load_transition_efer(vmx);
772 }
773 break;
774 case MSR_FS_BASE:
775 vmcs_writel(GUEST_FS_BASE, data);
776 break;
777 case MSR_GS_BASE:
778 vmcs_writel(GUEST_GS_BASE, data);
779 break;
780 #endif
781 case MSR_IA32_SYSENTER_CS:
782 vmcs_write32(GUEST_SYSENTER_CS, data);
783 break;
784 case MSR_IA32_SYSENTER_EIP:
785 vmcs_writel(GUEST_SYSENTER_EIP, data);
786 break;
787 case MSR_IA32_SYSENTER_ESP:
788 vmcs_writel(GUEST_SYSENTER_ESP, data);
789 break;
790 case MSR_IA32_TIME_STAMP_COUNTER:
791 guest_write_tsc(data);
792 break;
793 default:
794 msr = find_msr_entry(vmx, msr_index);
795 if (msr) {
796 msr->data = data;
797 if (vmx->host_state.loaded)
798 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
799 break;
800 }
801 ret = kvm_set_msr_common(vcpu, msr_index, data);
802 }
803
804 return ret;
805 }
806
807 /*
808 * Sync the rsp and rip registers into the vcpu structure. This allows
809 * registers to be accessed by indexing vcpu->regs.
810 */
811 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
812 {
813 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
814 vcpu->rip = vmcs_readl(GUEST_RIP);
815 }
816
817 /*
818 * Syncs rsp and rip back into the vmcs. Should be called after possible
819 * modification.
820 */
821 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
822 {
823 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
824 vmcs_writel(GUEST_RIP, vcpu->rip);
825 }
826
827 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
828 {
829 unsigned long dr7 = 0x400;
830 int old_singlestep;
831
832 old_singlestep = vcpu->guest_debug.singlestep;
833
834 vcpu->guest_debug.enabled = dbg->enabled;
835 if (vcpu->guest_debug.enabled) {
836 int i;
837
838 dr7 |= 0x200; /* exact */
839 for (i = 0; i < 4; ++i) {
840 if (!dbg->breakpoints[i].enabled)
841 continue;
842 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
843 dr7 |= 2 << (i*2); /* global enable */
844 dr7 |= 0 << (i*4+16); /* execution breakpoint */
845 }
846
847 vcpu->guest_debug.singlestep = dbg->singlestep;
848 } else
849 vcpu->guest_debug.singlestep = 0;
850
851 if (old_singlestep && !vcpu->guest_debug.singlestep) {
852 unsigned long flags;
853
854 flags = vmcs_readl(GUEST_RFLAGS);
855 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
856 vmcs_writel(GUEST_RFLAGS, flags);
857 }
858
859 update_exception_bitmap(vcpu);
860 vmcs_writel(GUEST_DR7, dr7);
861
862 return 0;
863 }
864
865 static int vmx_get_irq(struct kvm_vcpu *vcpu)
866 {
867 struct vcpu_vmx *vmx = to_vmx(vcpu);
868 u32 idtv_info_field;
869
870 idtv_info_field = vmx->idt_vectoring_info;
871 if (idtv_info_field & INTR_INFO_VALID_MASK) {
872 if (is_external_interrupt(idtv_info_field))
873 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
874 else
875 printk(KERN_DEBUG "pending exception: not handled yet\n");
876 }
877 return -1;
878 }
879
880 static __init int cpu_has_kvm_support(void)
881 {
882 unsigned long ecx = cpuid_ecx(1);
883 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
884 }
885
886 static __init int vmx_disabled_by_bios(void)
887 {
888 u64 msr;
889
890 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
891 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
892 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
893 == MSR_IA32_FEATURE_CONTROL_LOCKED;
894 /* locked but not enabled */
895 }
896
897 static void hardware_enable(void *garbage)
898 {
899 int cpu = raw_smp_processor_id();
900 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
901 u64 old;
902
903 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
904 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
905 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
906 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
907 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
908 /* enable and lock */
909 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
910 MSR_IA32_FEATURE_CONTROL_LOCKED |
911 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
912 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
913 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
914 : "memory", "cc");
915 }
916
917 static void hardware_disable(void *garbage)
918 {
919 asm volatile (ASM_VMX_VMXOFF : : : "cc");
920 }
921
922 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
923 u32 msr, u32 *result)
924 {
925 u32 vmx_msr_low, vmx_msr_high;
926 u32 ctl = ctl_min | ctl_opt;
927
928 rdmsr(msr, vmx_msr_low, vmx_msr_high);
929
930 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
931 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
932
933 /* Ensure minimum (required) set of control bits are supported. */
934 if (ctl_min & ~ctl)
935 return -EIO;
936
937 *result = ctl;
938 return 0;
939 }
940
941 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
942 {
943 u32 vmx_msr_low, vmx_msr_high;
944 u32 min, opt;
945 u32 _pin_based_exec_control = 0;
946 u32 _cpu_based_exec_control = 0;
947 u32 _cpu_based_2nd_exec_control = 0;
948 u32 _vmexit_control = 0;
949 u32 _vmentry_control = 0;
950
951 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
952 opt = 0;
953 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
954 &_pin_based_exec_control) < 0)
955 return -EIO;
956
957 min = CPU_BASED_HLT_EXITING |
958 #ifdef CONFIG_X86_64
959 CPU_BASED_CR8_LOAD_EXITING |
960 CPU_BASED_CR8_STORE_EXITING |
961 #endif
962 CPU_BASED_USE_IO_BITMAPS |
963 CPU_BASED_MOV_DR_EXITING |
964 CPU_BASED_USE_TSC_OFFSETING;
965 opt = CPU_BASED_TPR_SHADOW |
966 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
967 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
968 &_cpu_based_exec_control) < 0)
969 return -EIO;
970 #ifdef CONFIG_X86_64
971 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
972 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
973 ~CPU_BASED_CR8_STORE_EXITING;
974 #endif
975 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
976 min = 0;
977 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
978 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
979 &_cpu_based_2nd_exec_control) < 0)
980 return -EIO;
981 }
982 #ifndef CONFIG_X86_64
983 if (!(_cpu_based_2nd_exec_control &
984 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
985 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
986 #endif
987
988 min = 0;
989 #ifdef CONFIG_X86_64
990 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
991 #endif
992 opt = 0;
993 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
994 &_vmexit_control) < 0)
995 return -EIO;
996
997 min = opt = 0;
998 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
999 &_vmentry_control) < 0)
1000 return -EIO;
1001
1002 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1003
1004 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1005 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1006 return -EIO;
1007
1008 #ifdef CONFIG_X86_64
1009 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1010 if (vmx_msr_high & (1u<<16))
1011 return -EIO;
1012 #endif
1013
1014 /* Require Write-Back (WB) memory type for VMCS accesses. */
1015 if (((vmx_msr_high >> 18) & 15) != 6)
1016 return -EIO;
1017
1018 vmcs_conf->size = vmx_msr_high & 0x1fff;
1019 vmcs_conf->order = get_order(vmcs_config.size);
1020 vmcs_conf->revision_id = vmx_msr_low;
1021
1022 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1023 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1024 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1025 vmcs_conf->vmexit_ctrl = _vmexit_control;
1026 vmcs_conf->vmentry_ctrl = _vmentry_control;
1027
1028 return 0;
1029 }
1030
1031 static struct vmcs *alloc_vmcs_cpu(int cpu)
1032 {
1033 int node = cpu_to_node(cpu);
1034 struct page *pages;
1035 struct vmcs *vmcs;
1036
1037 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1038 if (!pages)
1039 return NULL;
1040 vmcs = page_address(pages);
1041 memset(vmcs, 0, vmcs_config.size);
1042 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1043 return vmcs;
1044 }
1045
1046 static struct vmcs *alloc_vmcs(void)
1047 {
1048 return alloc_vmcs_cpu(raw_smp_processor_id());
1049 }
1050
1051 static void free_vmcs(struct vmcs *vmcs)
1052 {
1053 free_pages((unsigned long)vmcs, vmcs_config.order);
1054 }
1055
1056 static void free_kvm_area(void)
1057 {
1058 int cpu;
1059
1060 for_each_online_cpu(cpu)
1061 free_vmcs(per_cpu(vmxarea, cpu));
1062 }
1063
1064 static __init int alloc_kvm_area(void)
1065 {
1066 int cpu;
1067
1068 for_each_online_cpu(cpu) {
1069 struct vmcs *vmcs;
1070
1071 vmcs = alloc_vmcs_cpu(cpu);
1072 if (!vmcs) {
1073 free_kvm_area();
1074 return -ENOMEM;
1075 }
1076
1077 per_cpu(vmxarea, cpu) = vmcs;
1078 }
1079 return 0;
1080 }
1081
1082 static __init int hardware_setup(void)
1083 {
1084 if (setup_vmcs_config(&vmcs_config) < 0)
1085 return -EIO;
1086 return alloc_kvm_area();
1087 }
1088
1089 static __exit void hardware_unsetup(void)
1090 {
1091 free_kvm_area();
1092 }
1093
1094 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1095 {
1096 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1097
1098 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1099 vmcs_write16(sf->selector, save->selector);
1100 vmcs_writel(sf->base, save->base);
1101 vmcs_write32(sf->limit, save->limit);
1102 vmcs_write32(sf->ar_bytes, save->ar);
1103 } else {
1104 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1105 << AR_DPL_SHIFT;
1106 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1107 }
1108 }
1109
1110 static void enter_pmode(struct kvm_vcpu *vcpu)
1111 {
1112 unsigned long flags;
1113
1114 vcpu->rmode.active = 0;
1115
1116 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1117 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1118 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1119
1120 flags = vmcs_readl(GUEST_RFLAGS);
1121 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1122 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1123 vmcs_writel(GUEST_RFLAGS, flags);
1124
1125 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1126 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1127
1128 update_exception_bitmap(vcpu);
1129
1130 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1131 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1132 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1133 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1134
1135 vmcs_write16(GUEST_SS_SELECTOR, 0);
1136 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1137
1138 vmcs_write16(GUEST_CS_SELECTOR,
1139 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1140 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1141 }
1142
1143 static gva_t rmode_tss_base(struct kvm *kvm)
1144 {
1145 if (!kvm->tss_addr) {
1146 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1147 kvm->memslots[0].npages - 3;
1148 return base_gfn << PAGE_SHIFT;
1149 }
1150 return kvm->tss_addr;
1151 }
1152
1153 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1154 {
1155 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1156
1157 save->selector = vmcs_read16(sf->selector);
1158 save->base = vmcs_readl(sf->base);
1159 save->limit = vmcs_read32(sf->limit);
1160 save->ar = vmcs_read32(sf->ar_bytes);
1161 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1162 vmcs_write32(sf->limit, 0xffff);
1163 vmcs_write32(sf->ar_bytes, 0xf3);
1164 }
1165
1166 static void enter_rmode(struct kvm_vcpu *vcpu)
1167 {
1168 unsigned long flags;
1169
1170 vcpu->rmode.active = 1;
1171
1172 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1173 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1174
1175 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1176 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1177
1178 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1179 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1180
1181 flags = vmcs_readl(GUEST_RFLAGS);
1182 vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1183
1184 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1185
1186 vmcs_writel(GUEST_RFLAGS, flags);
1187 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1188 update_exception_bitmap(vcpu);
1189
1190 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1191 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1192 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1193
1194 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1195 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1196 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1197 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1198 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1199
1200 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1201 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1202 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1203 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1204
1205 kvm_mmu_reset_context(vcpu);
1206 init_rmode_tss(vcpu->kvm);
1207 }
1208
1209 #ifdef CONFIG_X86_64
1210
1211 static void enter_lmode(struct kvm_vcpu *vcpu)
1212 {
1213 u32 guest_tr_ar;
1214
1215 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1216 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1217 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1218 __FUNCTION__);
1219 vmcs_write32(GUEST_TR_AR_BYTES,
1220 (guest_tr_ar & ~AR_TYPE_MASK)
1221 | AR_TYPE_BUSY_64_TSS);
1222 }
1223
1224 vcpu->shadow_efer |= EFER_LMA;
1225
1226 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1227 vmcs_write32(VM_ENTRY_CONTROLS,
1228 vmcs_read32(VM_ENTRY_CONTROLS)
1229 | VM_ENTRY_IA32E_MODE);
1230 }
1231
1232 static void exit_lmode(struct kvm_vcpu *vcpu)
1233 {
1234 vcpu->shadow_efer &= ~EFER_LMA;
1235
1236 vmcs_write32(VM_ENTRY_CONTROLS,
1237 vmcs_read32(VM_ENTRY_CONTROLS)
1238 & ~VM_ENTRY_IA32E_MODE);
1239 }
1240
1241 #endif
1242
1243 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1244 {
1245 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1246 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1247 }
1248
1249 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1250 {
1251 vmx_fpu_deactivate(vcpu);
1252
1253 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1254 enter_pmode(vcpu);
1255
1256 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1257 enter_rmode(vcpu);
1258
1259 #ifdef CONFIG_X86_64
1260 if (vcpu->shadow_efer & EFER_LME) {
1261 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1262 enter_lmode(vcpu);
1263 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1264 exit_lmode(vcpu);
1265 }
1266 #endif
1267
1268 vmcs_writel(CR0_READ_SHADOW, cr0);
1269 vmcs_writel(GUEST_CR0,
1270 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1271 vcpu->cr0 = cr0;
1272
1273 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1274 vmx_fpu_activate(vcpu);
1275 }
1276
1277 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1278 {
1279 vmcs_writel(GUEST_CR3, cr3);
1280 if (vcpu->cr0 & X86_CR0_PE)
1281 vmx_fpu_deactivate(vcpu);
1282 }
1283
1284 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1285 {
1286 vmcs_writel(CR4_READ_SHADOW, cr4);
1287 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1288 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1289 vcpu->cr4 = cr4;
1290 }
1291
1292 #ifdef CONFIG_X86_64
1293
1294 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1295 {
1296 struct vcpu_vmx *vmx = to_vmx(vcpu);
1297 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1298
1299 vcpu->shadow_efer = efer;
1300 if (efer & EFER_LMA) {
1301 vmcs_write32(VM_ENTRY_CONTROLS,
1302 vmcs_read32(VM_ENTRY_CONTROLS) |
1303 VM_ENTRY_IA32E_MODE);
1304 msr->data = efer;
1305
1306 } else {
1307 vmcs_write32(VM_ENTRY_CONTROLS,
1308 vmcs_read32(VM_ENTRY_CONTROLS) &
1309 ~VM_ENTRY_IA32E_MODE);
1310
1311 msr->data = efer & ~EFER_LME;
1312 }
1313 setup_msrs(vmx);
1314 }
1315
1316 #endif
1317
1318 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1319 {
1320 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1321
1322 return vmcs_readl(sf->base);
1323 }
1324
1325 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1326 struct kvm_segment *var, int seg)
1327 {
1328 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1329 u32 ar;
1330
1331 var->base = vmcs_readl(sf->base);
1332 var->limit = vmcs_read32(sf->limit);
1333 var->selector = vmcs_read16(sf->selector);
1334 ar = vmcs_read32(sf->ar_bytes);
1335 if (ar & AR_UNUSABLE_MASK)
1336 ar = 0;
1337 var->type = ar & 15;
1338 var->s = (ar >> 4) & 1;
1339 var->dpl = (ar >> 5) & 3;
1340 var->present = (ar >> 7) & 1;
1341 var->avl = (ar >> 12) & 1;
1342 var->l = (ar >> 13) & 1;
1343 var->db = (ar >> 14) & 1;
1344 var->g = (ar >> 15) & 1;
1345 var->unusable = (ar >> 16) & 1;
1346 }
1347
1348 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1349 {
1350 u32 ar;
1351
1352 if (var->unusable)
1353 ar = 1 << 16;
1354 else {
1355 ar = var->type & 15;
1356 ar |= (var->s & 1) << 4;
1357 ar |= (var->dpl & 3) << 5;
1358 ar |= (var->present & 1) << 7;
1359 ar |= (var->avl & 1) << 12;
1360 ar |= (var->l & 1) << 13;
1361 ar |= (var->db & 1) << 14;
1362 ar |= (var->g & 1) << 15;
1363 }
1364 if (ar == 0) /* a 0 value means unusable */
1365 ar = AR_UNUSABLE_MASK;
1366
1367 return ar;
1368 }
1369
1370 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1371 struct kvm_segment *var, int seg)
1372 {
1373 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1374 u32 ar;
1375
1376 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1377 vcpu->rmode.tr.selector = var->selector;
1378 vcpu->rmode.tr.base = var->base;
1379 vcpu->rmode.tr.limit = var->limit;
1380 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1381 return;
1382 }
1383 vmcs_writel(sf->base, var->base);
1384 vmcs_write32(sf->limit, var->limit);
1385 vmcs_write16(sf->selector, var->selector);
1386 if (vcpu->rmode.active && var->s) {
1387 /*
1388 * Hack real-mode segments into vm86 compatibility.
1389 */
1390 if (var->base == 0xffff0000 && var->selector == 0xf000)
1391 vmcs_writel(sf->base, 0xf0000);
1392 ar = 0xf3;
1393 } else
1394 ar = vmx_segment_access_rights(var);
1395 vmcs_write32(sf->ar_bytes, ar);
1396 }
1397
1398 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1399 {
1400 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1401
1402 *db = (ar >> 14) & 1;
1403 *l = (ar >> 13) & 1;
1404 }
1405
1406 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1407 {
1408 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1409 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1410 }
1411
1412 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1413 {
1414 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1415 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1416 }
1417
1418 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1419 {
1420 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1421 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1422 }
1423
1424 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1425 {
1426 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1427 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1428 }
1429
1430 static int init_rmode_tss(struct kvm *kvm)
1431 {
1432 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1433 u16 data = 0;
1434 int r;
1435
1436 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1437 if (r < 0)
1438 return 0;
1439 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1440 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1441 if (r < 0)
1442 return 0;
1443 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1444 if (r < 0)
1445 return 0;
1446 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1447 if (r < 0)
1448 return 0;
1449 data = ~0;
1450 r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1451 sizeof(u8));
1452 if (r < 0)
1453 return 0;
1454 return 1;
1455 }
1456
1457 static void seg_setup(int seg)
1458 {
1459 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1460
1461 vmcs_write16(sf->selector, 0);
1462 vmcs_writel(sf->base, 0);
1463 vmcs_write32(sf->limit, 0xffff);
1464 vmcs_write32(sf->ar_bytes, 0x93);
1465 }
1466
1467 static int alloc_apic_access_page(struct kvm *kvm)
1468 {
1469 struct kvm_userspace_memory_region kvm_userspace_mem;
1470 int r = 0;
1471
1472 mutex_lock(&kvm->lock);
1473 if (kvm->apic_access_page)
1474 goto out;
1475 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1476 kvm_userspace_mem.flags = 0;
1477 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1478 kvm_userspace_mem.memory_size = PAGE_SIZE;
1479 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1480 if (r)
1481 goto out;
1482 kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1483 out:
1484 mutex_unlock(&kvm->lock);
1485 return r;
1486 }
1487
1488 /*
1489 * Sets up the vmcs for emulated real mode.
1490 */
1491 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1492 {
1493 u32 host_sysenter_cs;
1494 u32 junk;
1495 unsigned long a;
1496 struct descriptor_table dt;
1497 int i;
1498 unsigned long kvm_vmx_return;
1499 u32 exec_control;
1500
1501 /* I/O */
1502 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1503 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1504
1505 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1506
1507 /* Control */
1508 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1509 vmcs_config.pin_based_exec_ctrl);
1510
1511 exec_control = vmcs_config.cpu_based_exec_ctrl;
1512 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1513 exec_control &= ~CPU_BASED_TPR_SHADOW;
1514 #ifdef CONFIG_X86_64
1515 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1516 CPU_BASED_CR8_LOAD_EXITING;
1517 #endif
1518 }
1519 if (!vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1520 exec_control &= ~CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1521 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1522
1523 if (vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1524 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
1525 vmcs_config.cpu_based_2nd_exec_ctrl);
1526
1527 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1528 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1529 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1530
1531 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1532 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1533 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1534
1535 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1536 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1537 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1538 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1539 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1540 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1541 #ifdef CONFIG_X86_64
1542 rdmsrl(MSR_FS_BASE, a);
1543 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1544 rdmsrl(MSR_GS_BASE, a);
1545 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1546 #else
1547 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1548 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1549 #endif
1550
1551 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1552
1553 get_idt(&dt);
1554 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1555
1556 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1557 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1558 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1559 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1560 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1561
1562 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1563 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1564 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1565 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1566 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1567 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1568
1569 for (i = 0; i < NR_VMX_MSR; ++i) {
1570 u32 index = vmx_msr_index[i];
1571 u32 data_low, data_high;
1572 u64 data;
1573 int j = vmx->nmsrs;
1574
1575 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1576 continue;
1577 if (wrmsr_safe(index, data_low, data_high) < 0)
1578 continue;
1579 data = data_low | ((u64)data_high << 32);
1580 vmx->host_msrs[j].index = index;
1581 vmx->host_msrs[j].reserved = 0;
1582 vmx->host_msrs[j].data = data;
1583 vmx->guest_msrs[j] = vmx->host_msrs[j];
1584 ++vmx->nmsrs;
1585 }
1586
1587 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1588
1589 /* 22.2.1, 20.8.1 */
1590 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1591
1592 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1593 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1594
1595 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1596 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1597 return -ENOMEM;
1598
1599 return 0;
1600 }
1601
1602 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1603 {
1604 struct vcpu_vmx *vmx = to_vmx(vcpu);
1605 u64 msr;
1606 int ret;
1607
1608 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1609 ret = -ENOMEM;
1610 goto out;
1611 }
1612
1613 vmx->vcpu.rmode.active = 0;
1614
1615 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1616 set_cr8(&vmx->vcpu, 0);
1617 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1618 if (vmx->vcpu.vcpu_id == 0)
1619 msr |= MSR_IA32_APICBASE_BSP;
1620 kvm_set_apic_base(&vmx->vcpu, msr);
1621
1622 fx_init(&vmx->vcpu);
1623
1624 /*
1625 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1626 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1627 */
1628 if (vmx->vcpu.vcpu_id == 0) {
1629 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1630 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1631 } else {
1632 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1633 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1634 }
1635 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1636 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1637
1638 seg_setup(VCPU_SREG_DS);
1639 seg_setup(VCPU_SREG_ES);
1640 seg_setup(VCPU_SREG_FS);
1641 seg_setup(VCPU_SREG_GS);
1642 seg_setup(VCPU_SREG_SS);
1643
1644 vmcs_write16(GUEST_TR_SELECTOR, 0);
1645 vmcs_writel(GUEST_TR_BASE, 0);
1646 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1647 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1648
1649 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1650 vmcs_writel(GUEST_LDTR_BASE, 0);
1651 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1652 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1653
1654 vmcs_write32(GUEST_SYSENTER_CS, 0);
1655 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1656 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1657
1658 vmcs_writel(GUEST_RFLAGS, 0x02);
1659 if (vmx->vcpu.vcpu_id == 0)
1660 vmcs_writel(GUEST_RIP, 0xfff0);
1661 else
1662 vmcs_writel(GUEST_RIP, 0);
1663 vmcs_writel(GUEST_RSP, 0);
1664
1665 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1666 vmcs_writel(GUEST_DR7, 0x400);
1667
1668 vmcs_writel(GUEST_GDTR_BASE, 0);
1669 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1670
1671 vmcs_writel(GUEST_IDTR_BASE, 0);
1672 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1673
1674 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1675 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1676 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1677
1678 guest_write_tsc(0);
1679
1680 /* Special registers */
1681 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1682
1683 setup_msrs(vmx);
1684
1685 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1686
1687 if (cpu_has_vmx_tpr_shadow()) {
1688 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1689 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1690 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1691 page_to_phys(vmx->vcpu.apic->regs_page));
1692 vmcs_write32(TPR_THRESHOLD, 0);
1693 }
1694
1695 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1696 vmcs_write64(APIC_ACCESS_ADDR,
1697 page_to_phys(vmx->vcpu.kvm->apic_access_page));
1698
1699 vmx->vcpu.cr0 = 0x60000010;
1700 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
1701 vmx_set_cr4(&vmx->vcpu, 0);
1702 #ifdef CONFIG_X86_64
1703 vmx_set_efer(&vmx->vcpu, 0);
1704 #endif
1705 vmx_fpu_activate(&vmx->vcpu);
1706 update_exception_bitmap(&vmx->vcpu);
1707
1708 return 0;
1709
1710 out:
1711 return ret;
1712 }
1713
1714 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1715 {
1716 if (vcpu->rmode.active) {
1717 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1718 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1719 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1720 vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) - 1);
1721 return;
1722 }
1723 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1724 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1725 }
1726
1727 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1728 {
1729 int word_index = __ffs(vcpu->irq_summary);
1730 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1731 int irq = word_index * BITS_PER_LONG + bit_index;
1732
1733 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1734 if (!vcpu->irq_pending[word_index])
1735 clear_bit(word_index, &vcpu->irq_summary);
1736 vmx_inject_irq(vcpu, irq);
1737 }
1738
1739
1740 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1741 struct kvm_run *kvm_run)
1742 {
1743 u32 cpu_based_vm_exec_control;
1744
1745 vcpu->interrupt_window_open =
1746 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1747 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1748
1749 if (vcpu->interrupt_window_open &&
1750 vcpu->irq_summary &&
1751 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1752 /*
1753 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1754 */
1755 kvm_do_inject_irq(vcpu);
1756
1757 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1758 if (!vcpu->interrupt_window_open &&
1759 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1760 /*
1761 * Interrupts blocked. Wait for unblock.
1762 */
1763 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1764 else
1765 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1766 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1767 }
1768
1769 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1770 {
1771 int ret;
1772 struct kvm_userspace_memory_region tss_mem = {
1773 .slot = 8,
1774 .guest_phys_addr = addr,
1775 .memory_size = PAGE_SIZE * 3,
1776 .flags = 0,
1777 };
1778
1779 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1780 if (ret)
1781 return ret;
1782 kvm->tss_addr = addr;
1783 return 0;
1784 }
1785
1786 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1787 {
1788 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1789
1790 set_debugreg(dbg->bp[0], 0);
1791 set_debugreg(dbg->bp[1], 1);
1792 set_debugreg(dbg->bp[2], 2);
1793 set_debugreg(dbg->bp[3], 3);
1794
1795 if (dbg->singlestep) {
1796 unsigned long flags;
1797
1798 flags = vmcs_readl(GUEST_RFLAGS);
1799 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1800 vmcs_writel(GUEST_RFLAGS, flags);
1801 }
1802 }
1803
1804 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1805 int vec, u32 err_code)
1806 {
1807 if (!vcpu->rmode.active)
1808 return 0;
1809
1810 /*
1811 * Instruction with address size override prefix opcode 0x67
1812 * Cause the #SS fault with 0 error code in VM86 mode.
1813 */
1814 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1815 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1816 return 1;
1817 return 0;
1818 }
1819
1820 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1821 {
1822 struct vcpu_vmx *vmx = to_vmx(vcpu);
1823 u32 intr_info, error_code;
1824 unsigned long cr2, rip;
1825 u32 vect_info;
1826 enum emulation_result er;
1827
1828 vect_info = vmx->idt_vectoring_info;
1829 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1830
1831 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1832 !is_page_fault(intr_info))
1833 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1834 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1835
1836 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1837 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1838 set_bit(irq, vcpu->irq_pending);
1839 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1840 }
1841
1842 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1843 return 1; /* already handled by vmx_vcpu_run() */
1844
1845 if (is_no_device(intr_info)) {
1846 vmx_fpu_activate(vcpu);
1847 return 1;
1848 }
1849
1850 if (is_invalid_opcode(intr_info)) {
1851 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1852 if (er != EMULATE_DONE)
1853 vmx_inject_ud(vcpu);
1854
1855 return 1;
1856 }
1857
1858 error_code = 0;
1859 rip = vmcs_readl(GUEST_RIP);
1860 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1861 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1862 if (is_page_fault(intr_info)) {
1863 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1864 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1865 }
1866
1867 if (vcpu->rmode.active &&
1868 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1869 error_code)) {
1870 if (vcpu->halt_request) {
1871 vcpu->halt_request = 0;
1872 return kvm_emulate_halt(vcpu);
1873 }
1874 return 1;
1875 }
1876
1877 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1878 (INTR_TYPE_EXCEPTION | 1)) {
1879 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1880 return 0;
1881 }
1882 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1883 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1884 kvm_run->ex.error_code = error_code;
1885 return 0;
1886 }
1887
1888 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1889 struct kvm_run *kvm_run)
1890 {
1891 ++vcpu->stat.irq_exits;
1892 return 1;
1893 }
1894
1895 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1896 {
1897 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1898 return 0;
1899 }
1900
1901 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1902 {
1903 unsigned long exit_qualification;
1904 int size, down, in, string, rep;
1905 unsigned port;
1906
1907 ++vcpu->stat.io_exits;
1908 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1909 string = (exit_qualification & 16) != 0;
1910
1911 if (string) {
1912 if (emulate_instruction(vcpu,
1913 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1914 return 0;
1915 return 1;
1916 }
1917
1918 size = (exit_qualification & 7) + 1;
1919 in = (exit_qualification & 8) != 0;
1920 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1921 rep = (exit_qualification & 32) != 0;
1922 port = exit_qualification >> 16;
1923
1924 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1925 }
1926
1927 static void
1928 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1929 {
1930 /*
1931 * Patch in the VMCALL instruction:
1932 */
1933 hypercall[0] = 0x0f;
1934 hypercall[1] = 0x01;
1935 hypercall[2] = 0xc1;
1936 }
1937
1938 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1939 {
1940 unsigned long exit_qualification;
1941 int cr;
1942 int reg;
1943
1944 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1945 cr = exit_qualification & 15;
1946 reg = (exit_qualification >> 8) & 15;
1947 switch ((exit_qualification >> 4) & 3) {
1948 case 0: /* mov to cr */
1949 switch (cr) {
1950 case 0:
1951 vcpu_load_rsp_rip(vcpu);
1952 set_cr0(vcpu, vcpu->regs[reg]);
1953 skip_emulated_instruction(vcpu);
1954 return 1;
1955 case 3:
1956 vcpu_load_rsp_rip(vcpu);
1957 set_cr3(vcpu, vcpu->regs[reg]);
1958 skip_emulated_instruction(vcpu);
1959 return 1;
1960 case 4:
1961 vcpu_load_rsp_rip(vcpu);
1962 set_cr4(vcpu, vcpu->regs[reg]);
1963 skip_emulated_instruction(vcpu);
1964 return 1;
1965 case 8:
1966 vcpu_load_rsp_rip(vcpu);
1967 set_cr8(vcpu, vcpu->regs[reg]);
1968 skip_emulated_instruction(vcpu);
1969 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1970 return 0;
1971 };
1972 break;
1973 case 2: /* clts */
1974 vcpu_load_rsp_rip(vcpu);
1975 vmx_fpu_deactivate(vcpu);
1976 vcpu->cr0 &= ~X86_CR0_TS;
1977 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1978 vmx_fpu_activate(vcpu);
1979 skip_emulated_instruction(vcpu);
1980 return 1;
1981 case 1: /*mov from cr*/
1982 switch (cr) {
1983 case 3:
1984 vcpu_load_rsp_rip(vcpu);
1985 vcpu->regs[reg] = vcpu->cr3;
1986 vcpu_put_rsp_rip(vcpu);
1987 skip_emulated_instruction(vcpu);
1988 return 1;
1989 case 8:
1990 vcpu_load_rsp_rip(vcpu);
1991 vcpu->regs[reg] = get_cr8(vcpu);
1992 vcpu_put_rsp_rip(vcpu);
1993 skip_emulated_instruction(vcpu);
1994 return 1;
1995 }
1996 break;
1997 case 3: /* lmsw */
1998 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1999
2000 skip_emulated_instruction(vcpu);
2001 return 1;
2002 default:
2003 break;
2004 }
2005 kvm_run->exit_reason = 0;
2006 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2007 (int)(exit_qualification >> 4) & 3, cr);
2008 return 0;
2009 }
2010
2011 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2012 {
2013 unsigned long exit_qualification;
2014 unsigned long val;
2015 int dr, reg;
2016
2017 /*
2018 * FIXME: this code assumes the host is debugging the guest.
2019 * need to deal with guest debugging itself too.
2020 */
2021 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2022 dr = exit_qualification & 7;
2023 reg = (exit_qualification >> 8) & 15;
2024 vcpu_load_rsp_rip(vcpu);
2025 if (exit_qualification & 16) {
2026 /* mov from dr */
2027 switch (dr) {
2028 case 6:
2029 val = 0xffff0ff0;
2030 break;
2031 case 7:
2032 val = 0x400;
2033 break;
2034 default:
2035 val = 0;
2036 }
2037 vcpu->regs[reg] = val;
2038 } else {
2039 /* mov to dr */
2040 }
2041 vcpu_put_rsp_rip(vcpu);
2042 skip_emulated_instruction(vcpu);
2043 return 1;
2044 }
2045
2046 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2047 {
2048 kvm_emulate_cpuid(vcpu);
2049 return 1;
2050 }
2051
2052 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2053 {
2054 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2055 u64 data;
2056
2057 if (vmx_get_msr(vcpu, ecx, &data)) {
2058 vmx_inject_gp(vcpu, 0);
2059 return 1;
2060 }
2061
2062 /* FIXME: handling of bits 32:63 of rax, rdx */
2063 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2064 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2065 skip_emulated_instruction(vcpu);
2066 return 1;
2067 }
2068
2069 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2070 {
2071 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2072 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2073 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2074
2075 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2076 vmx_inject_gp(vcpu, 0);
2077 return 1;
2078 }
2079
2080 skip_emulated_instruction(vcpu);
2081 return 1;
2082 }
2083
2084 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2085 struct kvm_run *kvm_run)
2086 {
2087 return 1;
2088 }
2089
2090 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2091 struct kvm_run *kvm_run)
2092 {
2093 u32 cpu_based_vm_exec_control;
2094
2095 /* clear pending irq */
2096 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2097 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2098 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2099 /*
2100 * If the user space waits to inject interrupts, exit as soon as
2101 * possible
2102 */
2103 if (kvm_run->request_interrupt_window &&
2104 !vcpu->irq_summary) {
2105 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2106 ++vcpu->stat.irq_window_exits;
2107 return 0;
2108 }
2109 return 1;
2110 }
2111
2112 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2113 {
2114 skip_emulated_instruction(vcpu);
2115 return kvm_emulate_halt(vcpu);
2116 }
2117
2118 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2119 {
2120 skip_emulated_instruction(vcpu);
2121 kvm_emulate_hypercall(vcpu);
2122 return 1;
2123 }
2124
2125 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2126 {
2127 u64 exit_qualification;
2128 enum emulation_result er;
2129 unsigned long offset;
2130
2131 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2132 offset = exit_qualification & 0xffful;
2133
2134 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2135
2136 if (er != EMULATE_DONE) {
2137 printk(KERN_ERR
2138 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2139 offset);
2140 return -ENOTSUPP;
2141 }
2142 return 1;
2143 }
2144
2145 /*
2146 * The exit handlers return 1 if the exit was handled fully and guest execution
2147 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2148 * to be done to userspace and return 0.
2149 */
2150 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2151 struct kvm_run *kvm_run) = {
2152 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2153 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2154 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2155 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2156 [EXIT_REASON_CR_ACCESS] = handle_cr,
2157 [EXIT_REASON_DR_ACCESS] = handle_dr,
2158 [EXIT_REASON_CPUID] = handle_cpuid,
2159 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2160 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2161 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2162 [EXIT_REASON_HLT] = handle_halt,
2163 [EXIT_REASON_VMCALL] = handle_vmcall,
2164 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2165 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
2166 };
2167
2168 static const int kvm_vmx_max_exit_handlers =
2169 ARRAY_SIZE(kvm_vmx_exit_handlers);
2170
2171 /*
2172 * The guest has exited. See if we can fix it or if we need userspace
2173 * assistance.
2174 */
2175 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2176 {
2177 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2178 struct vcpu_vmx *vmx = to_vmx(vcpu);
2179 u32 vectoring_info = vmx->idt_vectoring_info;
2180
2181 if (unlikely(vmx->fail)) {
2182 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2183 kvm_run->fail_entry.hardware_entry_failure_reason
2184 = vmcs_read32(VM_INSTRUCTION_ERROR);
2185 return 0;
2186 }
2187
2188 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2189 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2190 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2191 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2192 if (exit_reason < kvm_vmx_max_exit_handlers
2193 && kvm_vmx_exit_handlers[exit_reason])
2194 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2195 else {
2196 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2197 kvm_run->hw.hardware_exit_reason = exit_reason;
2198 }
2199 return 0;
2200 }
2201
2202 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2203 {
2204 }
2205
2206 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2207 {
2208 int max_irr, tpr;
2209
2210 if (!vm_need_tpr_shadow(vcpu->kvm))
2211 return;
2212
2213 if (!kvm_lapic_enabled(vcpu) ||
2214 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2215 vmcs_write32(TPR_THRESHOLD, 0);
2216 return;
2217 }
2218
2219 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2220 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2221 }
2222
2223 static void enable_irq_window(struct kvm_vcpu *vcpu)
2224 {
2225 u32 cpu_based_vm_exec_control;
2226
2227 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2228 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2229 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2230 }
2231
2232 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2233 {
2234 struct vcpu_vmx *vmx = to_vmx(vcpu);
2235 u32 idtv_info_field, intr_info_field;
2236 int has_ext_irq, interrupt_window_open;
2237 int vector;
2238
2239 update_tpr_threshold(vcpu);
2240
2241 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2242 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2243 idtv_info_field = vmx->idt_vectoring_info;
2244 if (intr_info_field & INTR_INFO_VALID_MASK) {
2245 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2246 /* TODO: fault when IDT_Vectoring */
2247 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2248 }
2249 if (has_ext_irq)
2250 enable_irq_window(vcpu);
2251 return;
2252 }
2253 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2254 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2255 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2256 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2257
2258 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2259 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2260 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2261 if (unlikely(has_ext_irq))
2262 enable_irq_window(vcpu);
2263 return;
2264 }
2265 if (!has_ext_irq)
2266 return;
2267 interrupt_window_open =
2268 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2269 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2270 if (interrupt_window_open) {
2271 vector = kvm_cpu_get_interrupt(vcpu);
2272 vmx_inject_irq(vcpu, vector);
2273 kvm_timer_intr_post(vcpu, vector);
2274 } else
2275 enable_irq_window(vcpu);
2276 }
2277
2278 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2279 {
2280 struct vcpu_vmx *vmx = to_vmx(vcpu);
2281 u32 intr_info;
2282
2283 /*
2284 * Loading guest fpu may have cleared host cr0.ts
2285 */
2286 vmcs_writel(HOST_CR0, read_cr0());
2287
2288 asm(
2289 /* Store host registers */
2290 #ifdef CONFIG_X86_64
2291 "push %%rdx; push %%rbp;"
2292 "push %%rcx \n\t"
2293 #else
2294 "push %%edx; push %%ebp;"
2295 "push %%ecx \n\t"
2296 #endif
2297 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2298 /* Check if vmlaunch of vmresume is needed */
2299 "cmp $0, %1 \n\t"
2300 /* Load guest registers. Don't clobber flags. */
2301 #ifdef CONFIG_X86_64
2302 "mov %c[cr2](%3), %%rax \n\t"
2303 "mov %%rax, %%cr2 \n\t"
2304 "mov %c[rax](%3), %%rax \n\t"
2305 "mov %c[rbx](%3), %%rbx \n\t"
2306 "mov %c[rdx](%3), %%rdx \n\t"
2307 "mov %c[rsi](%3), %%rsi \n\t"
2308 "mov %c[rdi](%3), %%rdi \n\t"
2309 "mov %c[rbp](%3), %%rbp \n\t"
2310 "mov %c[r8](%3), %%r8 \n\t"
2311 "mov %c[r9](%3), %%r9 \n\t"
2312 "mov %c[r10](%3), %%r10 \n\t"
2313 "mov %c[r11](%3), %%r11 \n\t"
2314 "mov %c[r12](%3), %%r12 \n\t"
2315 "mov %c[r13](%3), %%r13 \n\t"
2316 "mov %c[r14](%3), %%r14 \n\t"
2317 "mov %c[r15](%3), %%r15 \n\t"
2318 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2319 #else
2320 "mov %c[cr2](%3), %%eax \n\t"
2321 "mov %%eax, %%cr2 \n\t"
2322 "mov %c[rax](%3), %%eax \n\t"
2323 "mov %c[rbx](%3), %%ebx \n\t"
2324 "mov %c[rdx](%3), %%edx \n\t"
2325 "mov %c[rsi](%3), %%esi \n\t"
2326 "mov %c[rdi](%3), %%edi \n\t"
2327 "mov %c[rbp](%3), %%ebp \n\t"
2328 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2329 #endif
2330 /* Enter guest mode */
2331 "jne .Llaunched \n\t"
2332 ASM_VMX_VMLAUNCH "\n\t"
2333 "jmp .Lkvm_vmx_return \n\t"
2334 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2335 ".Lkvm_vmx_return: "
2336 /* Save guest registers, load host registers, keep flags */
2337 #ifdef CONFIG_X86_64
2338 "xchg %3, (%%rsp) \n\t"
2339 "mov %%rax, %c[rax](%3) \n\t"
2340 "mov %%rbx, %c[rbx](%3) \n\t"
2341 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
2342 "mov %%rdx, %c[rdx](%3) \n\t"
2343 "mov %%rsi, %c[rsi](%3) \n\t"
2344 "mov %%rdi, %c[rdi](%3) \n\t"
2345 "mov %%rbp, %c[rbp](%3) \n\t"
2346 "mov %%r8, %c[r8](%3) \n\t"
2347 "mov %%r9, %c[r9](%3) \n\t"
2348 "mov %%r10, %c[r10](%3) \n\t"
2349 "mov %%r11, %c[r11](%3) \n\t"
2350 "mov %%r12, %c[r12](%3) \n\t"
2351 "mov %%r13, %c[r13](%3) \n\t"
2352 "mov %%r14, %c[r14](%3) \n\t"
2353 "mov %%r15, %c[r15](%3) \n\t"
2354 "mov %%cr2, %%rax \n\t"
2355 "mov %%rax, %c[cr2](%3) \n\t"
2356
2357 "pop %%rcx; pop %%rbp; pop %%rdx \n\t"
2358 #else
2359 "xchg %3, (%%esp) \n\t"
2360 "mov %%eax, %c[rax](%3) \n\t"
2361 "mov %%ebx, %c[rbx](%3) \n\t"
2362 "pushl (%%esp); popl %c[rcx](%3) \n\t"
2363 "mov %%edx, %c[rdx](%3) \n\t"
2364 "mov %%esi, %c[rsi](%3) \n\t"
2365 "mov %%edi, %c[rdi](%3) \n\t"
2366 "mov %%ebp, %c[rbp](%3) \n\t"
2367 "mov %%cr2, %%eax \n\t"
2368 "mov %%eax, %c[cr2](%3) \n\t"
2369
2370 "pop %%ecx; pop %%ebp; pop %%edx \n\t"
2371 #endif
2372 "setbe %0 \n\t"
2373 : "=q" (vmx->fail)
2374 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
2375 "c"(vcpu),
2376 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2377 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2378 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2379 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2380 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2381 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2382 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
2383 #ifdef CONFIG_X86_64
2384 [r8]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8])),
2385 [r9]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9])),
2386 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2387 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2388 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2389 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2390 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2391 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2392 #endif
2393 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2394 : "cc", "memory"
2395 #ifdef CONFIG_X86_64
2396 , "rbx", "rdi", "rsi"
2397 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2398 #else
2399 , "ebx", "edi", "rsi"
2400 #endif
2401 );
2402
2403 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2404
2405 vcpu->interrupt_window_open =
2406 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2407
2408 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2409 vmx->launched = 1;
2410
2411 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2412
2413 /* We need to handle NMIs before interrupts are enabled */
2414 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2415 asm("int $2");
2416 }
2417
2418 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2419 unsigned long addr,
2420 u32 err_code)
2421 {
2422 struct vcpu_vmx *vmx = to_vmx(vcpu);
2423 u32 vect_info = vmx->idt_vectoring_info;
2424
2425 ++vcpu->stat.pf_guest;
2426
2427 if (is_page_fault(vect_info)) {
2428 printk(KERN_DEBUG "inject_page_fault: "
2429 "double fault 0x%lx @ 0x%lx\n",
2430 addr, vmcs_readl(GUEST_RIP));
2431 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2432 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2433 DF_VECTOR |
2434 INTR_TYPE_EXCEPTION |
2435 INTR_INFO_DELIEVER_CODE_MASK |
2436 INTR_INFO_VALID_MASK);
2437 return;
2438 }
2439 vcpu->cr2 = addr;
2440 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2441 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2442 PF_VECTOR |
2443 INTR_TYPE_EXCEPTION |
2444 INTR_INFO_DELIEVER_CODE_MASK |
2445 INTR_INFO_VALID_MASK);
2446
2447 }
2448
2449 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2450 {
2451 struct vcpu_vmx *vmx = to_vmx(vcpu);
2452
2453 if (vmx->vmcs) {
2454 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2455 free_vmcs(vmx->vmcs);
2456 vmx->vmcs = NULL;
2457 }
2458 }
2459
2460 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2461 {
2462 struct vcpu_vmx *vmx = to_vmx(vcpu);
2463
2464 vmx_free_vmcs(vcpu);
2465 kfree(vmx->host_msrs);
2466 kfree(vmx->guest_msrs);
2467 kvm_vcpu_uninit(vcpu);
2468 kmem_cache_free(kvm_vcpu_cache, vmx);
2469 }
2470
2471 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2472 {
2473 int err;
2474 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2475 int cpu;
2476
2477 if (!vmx)
2478 return ERR_PTR(-ENOMEM);
2479
2480 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2481 if (err)
2482 goto free_vcpu;
2483
2484 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2485 if (!vmx->guest_msrs) {
2486 err = -ENOMEM;
2487 goto uninit_vcpu;
2488 }
2489
2490 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2491 if (!vmx->host_msrs)
2492 goto free_guest_msrs;
2493
2494 vmx->vmcs = alloc_vmcs();
2495 if (!vmx->vmcs)
2496 goto free_msrs;
2497
2498 vmcs_clear(vmx->vmcs);
2499
2500 cpu = get_cpu();
2501 vmx_vcpu_load(&vmx->vcpu, cpu);
2502 err = vmx_vcpu_setup(vmx);
2503 vmx_vcpu_put(&vmx->vcpu);
2504 put_cpu();
2505 if (err)
2506 goto free_vmcs;
2507
2508 return &vmx->vcpu;
2509
2510 free_vmcs:
2511 free_vmcs(vmx->vmcs);
2512 free_msrs:
2513 kfree(vmx->host_msrs);
2514 free_guest_msrs:
2515 kfree(vmx->guest_msrs);
2516 uninit_vcpu:
2517 kvm_vcpu_uninit(&vmx->vcpu);
2518 free_vcpu:
2519 kmem_cache_free(kvm_vcpu_cache, vmx);
2520 return ERR_PTR(err);
2521 }
2522
2523 static void __init vmx_check_processor_compat(void *rtn)
2524 {
2525 struct vmcs_config vmcs_conf;
2526
2527 *(int *)rtn = 0;
2528 if (setup_vmcs_config(&vmcs_conf) < 0)
2529 *(int *)rtn = -EIO;
2530 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2531 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2532 smp_processor_id());
2533 *(int *)rtn = -EIO;
2534 }
2535 }
2536
2537 static struct kvm_x86_ops vmx_x86_ops = {
2538 .cpu_has_kvm_support = cpu_has_kvm_support,
2539 .disabled_by_bios = vmx_disabled_by_bios,
2540 .hardware_setup = hardware_setup,
2541 .hardware_unsetup = hardware_unsetup,
2542 .check_processor_compatibility = vmx_check_processor_compat,
2543 .hardware_enable = hardware_enable,
2544 .hardware_disable = hardware_disable,
2545
2546 .vcpu_create = vmx_create_vcpu,
2547 .vcpu_free = vmx_free_vcpu,
2548 .vcpu_reset = vmx_vcpu_reset,
2549
2550 .prepare_guest_switch = vmx_save_host_state,
2551 .vcpu_load = vmx_vcpu_load,
2552 .vcpu_put = vmx_vcpu_put,
2553 .vcpu_decache = vmx_vcpu_decache,
2554
2555 .set_guest_debug = set_guest_debug,
2556 .guest_debug_pre = kvm_guest_debug_pre,
2557 .get_msr = vmx_get_msr,
2558 .set_msr = vmx_set_msr,
2559 .get_segment_base = vmx_get_segment_base,
2560 .get_segment = vmx_get_segment,
2561 .set_segment = vmx_set_segment,
2562 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2563 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2564 .set_cr0 = vmx_set_cr0,
2565 .set_cr3 = vmx_set_cr3,
2566 .set_cr4 = vmx_set_cr4,
2567 #ifdef CONFIG_X86_64
2568 .set_efer = vmx_set_efer,
2569 #endif
2570 .get_idt = vmx_get_idt,
2571 .set_idt = vmx_set_idt,
2572 .get_gdt = vmx_get_gdt,
2573 .set_gdt = vmx_set_gdt,
2574 .cache_regs = vcpu_load_rsp_rip,
2575 .decache_regs = vcpu_put_rsp_rip,
2576 .get_rflags = vmx_get_rflags,
2577 .set_rflags = vmx_set_rflags,
2578
2579 .tlb_flush = vmx_flush_tlb,
2580 .inject_page_fault = vmx_inject_page_fault,
2581
2582 .inject_gp = vmx_inject_gp,
2583
2584 .run = vmx_vcpu_run,
2585 .handle_exit = kvm_handle_exit,
2586 .skip_emulated_instruction = skip_emulated_instruction,
2587 .patch_hypercall = vmx_patch_hypercall,
2588 .get_irq = vmx_get_irq,
2589 .set_irq = vmx_inject_irq,
2590 .inject_pending_irq = vmx_intr_assist,
2591 .inject_pending_vectors = do_interrupt_requests,
2592
2593 .set_tss_addr = vmx_set_tss_addr,
2594 };
2595
2596 static int __init vmx_init(void)
2597 {
2598 void *iova;
2599 int r;
2600
2601 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2602 if (!vmx_io_bitmap_a)
2603 return -ENOMEM;
2604
2605 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2606 if (!vmx_io_bitmap_b) {
2607 r = -ENOMEM;
2608 goto out;
2609 }
2610
2611 /*
2612 * Allow direct access to the PC debug port (it is often used for I/O
2613 * delays, but the vmexits simply slow things down).
2614 */
2615 iova = kmap(vmx_io_bitmap_a);
2616 memset(iova, 0xff, PAGE_SIZE);
2617 clear_bit(0x80, iova);
2618 kunmap(vmx_io_bitmap_a);
2619
2620 iova = kmap(vmx_io_bitmap_b);
2621 memset(iova, 0xff, PAGE_SIZE);
2622 kunmap(vmx_io_bitmap_b);
2623
2624 r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2625 if (r)
2626 goto out1;
2627
2628 if (bypass_guest_pf)
2629 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2630
2631 return 0;
2632
2633 out1:
2634 __free_page(vmx_io_bitmap_b);
2635 out:
2636 __free_page(vmx_io_bitmap_a);
2637 return r;
2638 }
2639
2640 static void __exit vmx_exit(void)
2641 {
2642 __free_page(vmx_io_bitmap_b);
2643 __free_page(vmx_io_bitmap_a);
2644
2645 kvm_exit_x86();
2646 }
2647
2648 module_init(vmx_init)
2649 module_exit(vmx_exit)
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