2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
19 #include "x86_emulate.h"
21 #include "segment_descriptor.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/profile.h>
28 #include <linux/sched.h>
33 MODULE_AUTHOR("Qumranet");
34 MODULE_LICENSE("GPL");
45 struct kvm_msr_entry
*guest_msrs
;
46 struct kvm_msr_entry
*host_msrs
;
51 int msr_offset_kernel_gs_base
;
56 u16 fs_sel
, gs_sel
, ldt_sel
;
57 int fs_gs_ldt_reload_needed
;
62 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
64 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
67 static int init_rmode_tss(struct kvm
*kvm
);
69 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
70 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
72 static struct page
*vmx_io_bitmap_a
;
73 static struct page
*vmx_io_bitmap_b
;
75 #define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE)
77 static struct vmcs_config
{
81 u32 pin_based_exec_ctrl
;
82 u32 cpu_based_exec_ctrl
;
87 #define VMX_SEGMENT_FIELD(seg) \
88 [VCPU_SREG_##seg] = { \
89 .selector = GUEST_##seg##_SELECTOR, \
90 .base = GUEST_##seg##_BASE, \
91 .limit = GUEST_##seg##_LIMIT, \
92 .ar_bytes = GUEST_##seg##_AR_BYTES, \
95 static struct kvm_vmx_segment_field
{
100 } kvm_vmx_segment_fields
[] = {
101 VMX_SEGMENT_FIELD(CS
),
102 VMX_SEGMENT_FIELD(DS
),
103 VMX_SEGMENT_FIELD(ES
),
104 VMX_SEGMENT_FIELD(FS
),
105 VMX_SEGMENT_FIELD(GS
),
106 VMX_SEGMENT_FIELD(SS
),
107 VMX_SEGMENT_FIELD(TR
),
108 VMX_SEGMENT_FIELD(LDTR
),
112 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
113 * away by decrementing the array size.
115 static const u32 vmx_msr_index
[] = {
117 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
, MSR_KERNEL_GS_BASE
,
119 MSR_EFER
, MSR_K6_STAR
,
121 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
123 static void load_msrs(struct kvm_msr_entry
*e
, int n
)
127 for (i
= 0; i
< n
; ++i
)
128 wrmsrl(e
[i
].index
, e
[i
].data
);
131 static void save_msrs(struct kvm_msr_entry
*e
, int n
)
135 for (i
= 0; i
< n
; ++i
)
136 rdmsrl(e
[i
].index
, e
[i
].data
);
139 static inline u64
msr_efer_save_restore_bits(struct kvm_msr_entry msr
)
141 return (u64
)msr
.data
& EFER_SAVE_RESTORE_BITS
;
144 static inline int msr_efer_need_save_restore(struct vcpu_vmx
*vmx
)
146 int efer_offset
= vmx
->msr_offset_efer
;
147 return msr_efer_save_restore_bits(vmx
->host_msrs
[efer_offset
]) !=
148 msr_efer_save_restore_bits(vmx
->guest_msrs
[efer_offset
]);
151 static inline int is_page_fault(u32 intr_info
)
153 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
154 INTR_INFO_VALID_MASK
)) ==
155 (INTR_TYPE_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
158 static inline int is_no_device(u32 intr_info
)
160 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
161 INTR_INFO_VALID_MASK
)) ==
162 (INTR_TYPE_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
165 static inline int is_external_interrupt(u32 intr_info
)
167 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
168 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
171 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
175 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
176 if (vmx
->guest_msrs
[i
].index
== msr
)
181 static struct kvm_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
185 i
= __find_msr_index(vmx
, msr
);
187 return &vmx
->guest_msrs
[i
];
191 static void vmcs_clear(struct vmcs
*vmcs
)
193 u64 phys_addr
= __pa(vmcs
);
196 asm volatile (ASM_VMX_VMCLEAR_RAX
"; setna %0"
197 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
200 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
204 static void __vcpu_clear(void *arg
)
206 struct vcpu_vmx
*vmx
= arg
;
207 int cpu
= raw_smp_processor_id();
209 if (vmx
->vcpu
.cpu
== cpu
)
210 vmcs_clear(vmx
->vmcs
);
211 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
212 per_cpu(current_vmcs
, cpu
) = NULL
;
213 rdtscll(vmx
->vcpu
.host_tsc
);
216 static void vcpu_clear(struct vcpu_vmx
*vmx
)
218 if (vmx
->vcpu
.cpu
!= raw_smp_processor_id() && vmx
->vcpu
.cpu
!= -1)
219 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
,
226 static unsigned long vmcs_readl(unsigned long field
)
230 asm volatile (ASM_VMX_VMREAD_RDX_RAX
231 : "=a"(value
) : "d"(field
) : "cc");
235 static u16
vmcs_read16(unsigned long field
)
237 return vmcs_readl(field
);
240 static u32
vmcs_read32(unsigned long field
)
242 return vmcs_readl(field
);
245 static u64
vmcs_read64(unsigned long field
)
248 return vmcs_readl(field
);
250 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
254 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
256 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
257 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
261 static void vmcs_writel(unsigned long field
, unsigned long value
)
265 asm volatile (ASM_VMX_VMWRITE_RAX_RDX
"; setna %0"
266 : "=q"(error
) : "a"(value
), "d"(field
) : "cc" );
268 vmwrite_error(field
, value
);
271 static void vmcs_write16(unsigned long field
, u16 value
)
273 vmcs_writel(field
, value
);
276 static void vmcs_write32(unsigned long field
, u32 value
)
278 vmcs_writel(field
, value
);
281 static void vmcs_write64(unsigned long field
, u64 value
)
284 vmcs_writel(field
, value
);
286 vmcs_writel(field
, value
);
288 vmcs_writel(field
+1, value
>> 32);
292 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
294 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
297 static void vmcs_set_bits(unsigned long field
, u32 mask
)
299 vmcs_writel(field
, vmcs_readl(field
) | mask
);
302 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
306 eb
= 1u << PF_VECTOR
;
307 if (!vcpu
->fpu_active
)
308 eb
|= 1u << NM_VECTOR
;
309 if (vcpu
->guest_debug
.enabled
)
311 if (vcpu
->rmode
.active
)
313 vmcs_write32(EXCEPTION_BITMAP
, eb
);
316 static void reload_tss(void)
318 #ifndef CONFIG_X86_64
321 * VT restores TR but not its size. Useless.
323 struct descriptor_table gdt
;
324 struct segment_descriptor
*descs
;
327 descs
= (void *)gdt
.base
;
328 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
333 static void load_transition_efer(struct vcpu_vmx
*vmx
)
336 int efer_offset
= vmx
->msr_offset_efer
;
338 trans_efer
= vmx
->host_msrs
[efer_offset
].data
;
339 trans_efer
&= ~EFER_SAVE_RESTORE_BITS
;
340 trans_efer
|= msr_efer_save_restore_bits(vmx
->guest_msrs
[efer_offset
]);
341 wrmsrl(MSR_EFER
, trans_efer
);
342 vmx
->vcpu
.stat
.efer_reload
++;
345 static void vmx_save_host_state(struct vcpu_vmx
*vmx
)
347 if (vmx
->host_state
.loaded
)
350 vmx
->host_state
.loaded
= 1;
352 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
353 * allow segment selectors with cpl > 0 or ti == 1.
355 vmx
->host_state
.ldt_sel
= read_ldt();
356 vmx
->host_state
.fs_gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
357 vmx
->host_state
.fs_sel
= read_fs();
358 if (!(vmx
->host_state
.fs_sel
& 7))
359 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
361 vmcs_write16(HOST_FS_SELECTOR
, 0);
362 vmx
->host_state
.fs_gs_ldt_reload_needed
= 1;
364 vmx
->host_state
.gs_sel
= read_gs();
365 if (!(vmx
->host_state
.gs_sel
& 7))
366 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
368 vmcs_write16(HOST_GS_SELECTOR
, 0);
369 vmx
->host_state
.fs_gs_ldt_reload_needed
= 1;
373 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
374 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
376 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
377 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
381 if (is_long_mode(&vmx
->vcpu
)) {
382 save_msrs(vmx
->host_msrs
+
383 vmx
->msr_offset_kernel_gs_base
, 1);
386 load_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
387 if (msr_efer_need_save_restore(vmx
))
388 load_transition_efer(vmx
);
391 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
395 if (!vmx
->host_state
.loaded
)
398 vmx
->host_state
.loaded
= 0;
399 if (vmx
->host_state
.fs_gs_ldt_reload_needed
) {
400 load_ldt(vmx
->host_state
.ldt_sel
);
401 load_fs(vmx
->host_state
.fs_sel
);
403 * If we have to reload gs, we must take care to
404 * preserve our gs base.
406 local_irq_save(flags
);
407 load_gs(vmx
->host_state
.gs_sel
);
409 wrmsrl(MSR_GS_BASE
, vmcs_readl(HOST_GS_BASE
));
411 local_irq_restore(flags
);
415 save_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
416 load_msrs(vmx
->host_msrs
, vmx
->save_nmsrs
);
417 if (msr_efer_need_save_restore(vmx
))
418 load_msrs(vmx
->host_msrs
+ vmx
->msr_offset_efer
, 1);
422 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
423 * vcpu mutex is already taken.
425 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
427 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
428 u64 phys_addr
= __pa(vmx
->vmcs
);
431 if (vcpu
->cpu
!= cpu
)
434 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
437 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
438 asm volatile (ASM_VMX_VMPTRLD_RAX
"; setna %0"
439 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
442 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
443 vmx
->vmcs
, phys_addr
);
446 if (vcpu
->cpu
!= cpu
) {
447 struct descriptor_table dt
;
448 unsigned long sysenter_esp
;
452 * Linux uses per-cpu TSS and GDT, so set these when switching
455 vmcs_writel(HOST_TR_BASE
, read_tr_base()); /* 22.2.4 */
457 vmcs_writel(HOST_GDTR_BASE
, dt
.base
); /* 22.2.4 */
459 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
460 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
463 * Make sure the time stamp counter is monotonous.
466 delta
= vcpu
->host_tsc
- tsc_this
;
467 vmcs_write64(TSC_OFFSET
, vmcs_read64(TSC_OFFSET
) + delta
);
471 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
473 vmx_load_host_state(to_vmx(vcpu
));
474 kvm_put_guest_fpu(vcpu
);
477 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
479 if (vcpu
->fpu_active
)
481 vcpu
->fpu_active
= 1;
482 vmcs_clear_bits(GUEST_CR0
, X86_CR0_TS
);
483 if (vcpu
->cr0
& X86_CR0_TS
)
484 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
485 update_exception_bitmap(vcpu
);
488 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
490 if (!vcpu
->fpu_active
)
492 vcpu
->fpu_active
= 0;
493 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
494 update_exception_bitmap(vcpu
);
497 static void vmx_vcpu_decache(struct kvm_vcpu
*vcpu
)
499 vcpu_clear(to_vmx(vcpu
));
502 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
504 return vmcs_readl(GUEST_RFLAGS
);
507 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
509 vmcs_writel(GUEST_RFLAGS
, rflags
);
512 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
515 u32 interruptibility
;
517 rip
= vmcs_readl(GUEST_RIP
);
518 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
519 vmcs_writel(GUEST_RIP
, rip
);
522 * We emulated an instruction, so temporary interrupt blocking
523 * should be removed, if set.
525 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
526 if (interruptibility
& 3)
527 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
528 interruptibility
& ~3);
529 vcpu
->interrupt_window_open
= 1;
532 static void vmx_inject_gp(struct kvm_vcpu
*vcpu
, unsigned error_code
)
534 printk(KERN_DEBUG
"inject_general_protection: rip 0x%lx\n",
535 vmcs_readl(GUEST_RIP
));
536 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
537 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
539 INTR_TYPE_EXCEPTION
|
540 INTR_INFO_DELIEVER_CODE_MASK
|
541 INTR_INFO_VALID_MASK
);
545 * Swap MSR entry in host/guest MSR entry array.
548 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
550 struct kvm_msr_entry tmp
;
552 tmp
= vmx
->guest_msrs
[to
];
553 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
554 vmx
->guest_msrs
[from
] = tmp
;
555 tmp
= vmx
->host_msrs
[to
];
556 vmx
->host_msrs
[to
] = vmx
->host_msrs
[from
];
557 vmx
->host_msrs
[from
] = tmp
;
562 * Set up the vmcs to automatically save and restore system
563 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
564 * mode, as fiddling with msrs is very expensive.
566 static void setup_msrs(struct vcpu_vmx
*vmx
)
572 if (is_long_mode(&vmx
->vcpu
)) {
575 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
577 move_msr_up(vmx
, index
, save_nmsrs
++);
578 index
= __find_msr_index(vmx
, MSR_LSTAR
);
580 move_msr_up(vmx
, index
, save_nmsrs
++);
581 index
= __find_msr_index(vmx
, MSR_CSTAR
);
583 move_msr_up(vmx
, index
, save_nmsrs
++);
584 index
= __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
586 move_msr_up(vmx
, index
, save_nmsrs
++);
588 * MSR_K6_STAR is only needed on long mode guests, and only
589 * if efer.sce is enabled.
591 index
= __find_msr_index(vmx
, MSR_K6_STAR
);
592 if ((index
>= 0) && (vmx
->vcpu
.shadow_efer
& EFER_SCE
))
593 move_msr_up(vmx
, index
, save_nmsrs
++);
596 vmx
->save_nmsrs
= save_nmsrs
;
599 vmx
->msr_offset_kernel_gs_base
=
600 __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
602 vmx
->msr_offset_efer
= __find_msr_index(vmx
, MSR_EFER
);
606 * reads and returns guest's timestamp counter "register"
607 * guest_tsc = host_tsc + tsc_offset -- 21.3
609 static u64
guest_read_tsc(void)
611 u64 host_tsc
, tsc_offset
;
614 tsc_offset
= vmcs_read64(TSC_OFFSET
);
615 return host_tsc
+ tsc_offset
;
619 * writes 'guest_tsc' into guest's timestamp counter "register"
620 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
622 static void guest_write_tsc(u64 guest_tsc
)
627 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
631 * Reads an msr value (of 'msr_index') into 'pdata'.
632 * Returns 0 on success, non-0 otherwise.
633 * Assumes vcpu_load() was already called.
635 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
638 struct kvm_msr_entry
*msr
;
641 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
648 data
= vmcs_readl(GUEST_FS_BASE
);
651 data
= vmcs_readl(GUEST_GS_BASE
);
654 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
656 case MSR_IA32_TIME_STAMP_COUNTER
:
657 data
= guest_read_tsc();
659 case MSR_IA32_SYSENTER_CS
:
660 data
= vmcs_read32(GUEST_SYSENTER_CS
);
662 case MSR_IA32_SYSENTER_EIP
:
663 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
665 case MSR_IA32_SYSENTER_ESP
:
666 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
669 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
674 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
682 * Writes msr value into into the appropriate "register".
683 * Returns 0 on success, non-0 otherwise.
684 * Assumes vcpu_load() was already called.
686 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
688 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
689 struct kvm_msr_entry
*msr
;
695 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
696 if (vmx
->host_state
.loaded
)
697 load_transition_efer(vmx
);
700 vmcs_writel(GUEST_FS_BASE
, data
);
703 vmcs_writel(GUEST_GS_BASE
, data
);
706 case MSR_IA32_SYSENTER_CS
:
707 vmcs_write32(GUEST_SYSENTER_CS
, data
);
709 case MSR_IA32_SYSENTER_EIP
:
710 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
712 case MSR_IA32_SYSENTER_ESP
:
713 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
715 case MSR_IA32_TIME_STAMP_COUNTER
:
716 guest_write_tsc(data
);
719 msr
= find_msr_entry(vmx
, msr_index
);
722 if (vmx
->host_state
.loaded
)
723 load_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
726 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
733 * Sync the rsp and rip registers into the vcpu structure. This allows
734 * registers to be accessed by indexing vcpu->regs.
736 static void vcpu_load_rsp_rip(struct kvm_vcpu
*vcpu
)
738 vcpu
->regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
739 vcpu
->rip
= vmcs_readl(GUEST_RIP
);
743 * Syncs rsp and rip back into the vmcs. Should be called after possible
746 static void vcpu_put_rsp_rip(struct kvm_vcpu
*vcpu
)
748 vmcs_writel(GUEST_RSP
, vcpu
->regs
[VCPU_REGS_RSP
]);
749 vmcs_writel(GUEST_RIP
, vcpu
->rip
);
752 static int set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_debug_guest
*dbg
)
754 unsigned long dr7
= 0x400;
757 old_singlestep
= vcpu
->guest_debug
.singlestep
;
759 vcpu
->guest_debug
.enabled
= dbg
->enabled
;
760 if (vcpu
->guest_debug
.enabled
) {
763 dr7
|= 0x200; /* exact */
764 for (i
= 0; i
< 4; ++i
) {
765 if (!dbg
->breakpoints
[i
].enabled
)
767 vcpu
->guest_debug
.bp
[i
] = dbg
->breakpoints
[i
].address
;
768 dr7
|= 2 << (i
*2); /* global enable */
769 dr7
|= 0 << (i
*4+16); /* execution breakpoint */
772 vcpu
->guest_debug
.singlestep
= dbg
->singlestep
;
774 vcpu
->guest_debug
.singlestep
= 0;
776 if (old_singlestep
&& !vcpu
->guest_debug
.singlestep
) {
779 flags
= vmcs_readl(GUEST_RFLAGS
);
780 flags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
781 vmcs_writel(GUEST_RFLAGS
, flags
);
784 update_exception_bitmap(vcpu
);
785 vmcs_writel(GUEST_DR7
, dr7
);
790 static __init
int cpu_has_kvm_support(void)
792 unsigned long ecx
= cpuid_ecx(1);
793 return test_bit(5, &ecx
); /* CPUID.1:ECX.VMX[bit 5] -> VT */
796 static __init
int vmx_disabled_by_bios(void)
800 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
801 return (msr
& (MSR_IA32_FEATURE_CONTROL_LOCKED
|
802 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
))
803 == MSR_IA32_FEATURE_CONTROL_LOCKED
;
804 /* locked but not enabled */
807 static void hardware_enable(void *garbage
)
809 int cpu
= raw_smp_processor_id();
810 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
813 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
814 if ((old
& (MSR_IA32_FEATURE_CONTROL_LOCKED
|
815 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
))
816 != (MSR_IA32_FEATURE_CONTROL_LOCKED
|
817 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
))
818 /* enable and lock */
819 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
|
820 MSR_IA32_FEATURE_CONTROL_LOCKED
|
821 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED
);
822 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
823 asm volatile (ASM_VMX_VMXON_RAX
: : "a"(&phys_addr
), "m"(phys_addr
)
827 static void hardware_disable(void *garbage
)
829 asm volatile (ASM_VMX_VMXOFF
: : : "cc");
832 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
833 u32 msr
, u32
* result
)
835 u32 vmx_msr_low
, vmx_msr_high
;
836 u32 ctl
= ctl_min
| ctl_opt
;
838 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
840 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
841 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
843 /* Ensure minimum (required) set of control bits are supported. */
851 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
853 u32 vmx_msr_low
, vmx_msr_high
;
855 u32 _pin_based_exec_control
= 0;
856 u32 _cpu_based_exec_control
= 0;
857 u32 _vmexit_control
= 0;
858 u32 _vmentry_control
= 0;
860 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
862 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
863 &_pin_based_exec_control
) < 0)
866 min
= CPU_BASED_HLT_EXITING
|
868 CPU_BASED_CR8_LOAD_EXITING
|
869 CPU_BASED_CR8_STORE_EXITING
|
871 CPU_BASED_USE_IO_BITMAPS
|
872 CPU_BASED_MOV_DR_EXITING
|
873 CPU_BASED_USE_TSC_OFFSETING
;
875 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
876 &_cpu_based_exec_control
) < 0)
881 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
884 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
885 &_vmexit_control
) < 0)
889 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
890 &_vmentry_control
) < 0)
893 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
895 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
896 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
900 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
901 if (vmx_msr_high
& (1u<<16))
905 /* Require Write-Back (WB) memory type for VMCS accesses. */
906 if (((vmx_msr_high
>> 18) & 15) != 6)
909 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
910 vmcs_conf
->order
= get_order(vmcs_config
.size
);
911 vmcs_conf
->revision_id
= vmx_msr_low
;
913 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
914 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
915 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
916 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
921 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
923 int node
= cpu_to_node(cpu
);
927 pages
= alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
930 vmcs
= page_address(pages
);
931 memset(vmcs
, 0, vmcs_config
.size
);
932 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
936 static struct vmcs
*alloc_vmcs(void)
938 return alloc_vmcs_cpu(raw_smp_processor_id());
941 static void free_vmcs(struct vmcs
*vmcs
)
943 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
946 static void free_kvm_area(void)
950 for_each_online_cpu(cpu
)
951 free_vmcs(per_cpu(vmxarea
, cpu
));
954 static __init
int alloc_kvm_area(void)
958 for_each_online_cpu(cpu
) {
961 vmcs
= alloc_vmcs_cpu(cpu
);
967 per_cpu(vmxarea
, cpu
) = vmcs
;
972 static __init
int hardware_setup(void)
974 if (setup_vmcs_config(&vmcs_config
) < 0)
976 return alloc_kvm_area();
979 static __exit
void hardware_unsetup(void)
984 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
986 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
988 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
989 vmcs_write16(sf
->selector
, save
->selector
);
990 vmcs_writel(sf
->base
, save
->base
);
991 vmcs_write32(sf
->limit
, save
->limit
);
992 vmcs_write32(sf
->ar_bytes
, save
->ar
);
994 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
996 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1000 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1002 unsigned long flags
;
1004 vcpu
->rmode
.active
= 0;
1006 vmcs_writel(GUEST_TR_BASE
, vcpu
->rmode
.tr
.base
);
1007 vmcs_write32(GUEST_TR_LIMIT
, vcpu
->rmode
.tr
.limit
);
1008 vmcs_write32(GUEST_TR_AR_BYTES
, vcpu
->rmode
.tr
.ar
);
1010 flags
= vmcs_readl(GUEST_RFLAGS
);
1011 flags
&= ~(IOPL_MASK
| X86_EFLAGS_VM
);
1012 flags
|= (vcpu
->rmode
.save_iopl
<< IOPL_SHIFT
);
1013 vmcs_writel(GUEST_RFLAGS
, flags
);
1015 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1016 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1018 update_exception_bitmap(vcpu
);
1020 fix_pmode_dataseg(VCPU_SREG_ES
, &vcpu
->rmode
.es
);
1021 fix_pmode_dataseg(VCPU_SREG_DS
, &vcpu
->rmode
.ds
);
1022 fix_pmode_dataseg(VCPU_SREG_GS
, &vcpu
->rmode
.gs
);
1023 fix_pmode_dataseg(VCPU_SREG_FS
, &vcpu
->rmode
.fs
);
1025 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1026 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1028 vmcs_write16(GUEST_CS_SELECTOR
,
1029 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1030 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1033 static int rmode_tss_base(struct kvm
* kvm
)
1035 gfn_t base_gfn
= kvm
->memslots
[0].base_gfn
+ kvm
->memslots
[0].npages
- 3;
1036 return base_gfn
<< PAGE_SHIFT
;
1039 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1041 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1043 save
->selector
= vmcs_read16(sf
->selector
);
1044 save
->base
= vmcs_readl(sf
->base
);
1045 save
->limit
= vmcs_read32(sf
->limit
);
1046 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1047 vmcs_write16(sf
->selector
, vmcs_readl(sf
->base
) >> 4);
1048 vmcs_write32(sf
->limit
, 0xffff);
1049 vmcs_write32(sf
->ar_bytes
, 0xf3);
1052 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1054 unsigned long flags
;
1056 vcpu
->rmode
.active
= 1;
1058 vcpu
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1059 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1061 vcpu
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1062 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1064 vcpu
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1065 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1067 flags
= vmcs_readl(GUEST_RFLAGS
);
1068 vcpu
->rmode
.save_iopl
= (flags
& IOPL_MASK
) >> IOPL_SHIFT
;
1070 flags
|= IOPL_MASK
| X86_EFLAGS_VM
;
1072 vmcs_writel(GUEST_RFLAGS
, flags
);
1073 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1074 update_exception_bitmap(vcpu
);
1076 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1077 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1078 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1080 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1081 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1082 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1083 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1084 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1086 fix_rmode_seg(VCPU_SREG_ES
, &vcpu
->rmode
.es
);
1087 fix_rmode_seg(VCPU_SREG_DS
, &vcpu
->rmode
.ds
);
1088 fix_rmode_seg(VCPU_SREG_GS
, &vcpu
->rmode
.gs
);
1089 fix_rmode_seg(VCPU_SREG_FS
, &vcpu
->rmode
.fs
);
1091 init_rmode_tss(vcpu
->kvm
);
1094 #ifdef CONFIG_X86_64
1096 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1100 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1101 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1102 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1104 vmcs_write32(GUEST_TR_AR_BYTES
,
1105 (guest_tr_ar
& ~AR_TYPE_MASK
)
1106 | AR_TYPE_BUSY_64_TSS
);
1109 vcpu
->shadow_efer
|= EFER_LMA
;
1111 find_msr_entry(to_vmx(vcpu
), MSR_EFER
)->data
|= EFER_LMA
| EFER_LME
;
1112 vmcs_write32(VM_ENTRY_CONTROLS
,
1113 vmcs_read32(VM_ENTRY_CONTROLS
)
1114 | VM_ENTRY_CONTROLS_IA32E_MASK
);
1117 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1119 vcpu
->shadow_efer
&= ~EFER_LMA
;
1121 vmcs_write32(VM_ENTRY_CONTROLS
,
1122 vmcs_read32(VM_ENTRY_CONTROLS
)
1123 & ~VM_ENTRY_CONTROLS_IA32E_MASK
);
1128 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1130 vcpu
->cr4
&= KVM_GUEST_CR4_MASK
;
1131 vcpu
->cr4
|= vmcs_readl(GUEST_CR4
) & ~KVM_GUEST_CR4_MASK
;
1134 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1136 vmx_fpu_deactivate(vcpu
);
1138 if (vcpu
->rmode
.active
&& (cr0
& X86_CR0_PE
))
1141 if (!vcpu
->rmode
.active
&& !(cr0
& X86_CR0_PE
))
1144 #ifdef CONFIG_X86_64
1145 if (vcpu
->shadow_efer
& EFER_LME
) {
1146 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1148 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1153 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1154 vmcs_writel(GUEST_CR0
,
1155 (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
);
1158 if (!(cr0
& X86_CR0_TS
) || !(cr0
& X86_CR0_PE
))
1159 vmx_fpu_activate(vcpu
);
1162 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1164 vmcs_writel(GUEST_CR3
, cr3
);
1165 if (vcpu
->cr0
& X86_CR0_PE
)
1166 vmx_fpu_deactivate(vcpu
);
1169 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1171 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1172 vmcs_writel(GUEST_CR4
, cr4
| (vcpu
->rmode
.active
?
1173 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
));
1177 #ifdef CONFIG_X86_64
1179 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1181 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1182 struct kvm_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1184 vcpu
->shadow_efer
= efer
;
1185 if (efer
& EFER_LMA
) {
1186 vmcs_write32(VM_ENTRY_CONTROLS
,
1187 vmcs_read32(VM_ENTRY_CONTROLS
) |
1188 VM_ENTRY_CONTROLS_IA32E_MASK
);
1192 vmcs_write32(VM_ENTRY_CONTROLS
,
1193 vmcs_read32(VM_ENTRY_CONTROLS
) &
1194 ~VM_ENTRY_CONTROLS_IA32E_MASK
);
1196 msr
->data
= efer
& ~EFER_LME
;
1203 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1205 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1207 return vmcs_readl(sf
->base
);
1210 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1211 struct kvm_segment
*var
, int seg
)
1213 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1216 var
->base
= vmcs_readl(sf
->base
);
1217 var
->limit
= vmcs_read32(sf
->limit
);
1218 var
->selector
= vmcs_read16(sf
->selector
);
1219 ar
= vmcs_read32(sf
->ar_bytes
);
1220 if (ar
& AR_UNUSABLE_MASK
)
1222 var
->type
= ar
& 15;
1223 var
->s
= (ar
>> 4) & 1;
1224 var
->dpl
= (ar
>> 5) & 3;
1225 var
->present
= (ar
>> 7) & 1;
1226 var
->avl
= (ar
>> 12) & 1;
1227 var
->l
= (ar
>> 13) & 1;
1228 var
->db
= (ar
>> 14) & 1;
1229 var
->g
= (ar
>> 15) & 1;
1230 var
->unusable
= (ar
>> 16) & 1;
1233 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
1240 ar
= var
->type
& 15;
1241 ar
|= (var
->s
& 1) << 4;
1242 ar
|= (var
->dpl
& 3) << 5;
1243 ar
|= (var
->present
& 1) << 7;
1244 ar
|= (var
->avl
& 1) << 12;
1245 ar
|= (var
->l
& 1) << 13;
1246 ar
|= (var
->db
& 1) << 14;
1247 ar
|= (var
->g
& 1) << 15;
1249 if (ar
== 0) /* a 0 value means unusable */
1250 ar
= AR_UNUSABLE_MASK
;
1255 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1256 struct kvm_segment
*var
, int seg
)
1258 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1261 if (vcpu
->rmode
.active
&& seg
== VCPU_SREG_TR
) {
1262 vcpu
->rmode
.tr
.selector
= var
->selector
;
1263 vcpu
->rmode
.tr
.base
= var
->base
;
1264 vcpu
->rmode
.tr
.limit
= var
->limit
;
1265 vcpu
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
1268 vmcs_writel(sf
->base
, var
->base
);
1269 vmcs_write32(sf
->limit
, var
->limit
);
1270 vmcs_write16(sf
->selector
, var
->selector
);
1271 if (vcpu
->rmode
.active
&& var
->s
) {
1273 * Hack real-mode segments into vm86 compatibility.
1275 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
1276 vmcs_writel(sf
->base
, 0xf0000);
1279 ar
= vmx_segment_access_rights(var
);
1280 vmcs_write32(sf
->ar_bytes
, ar
);
1283 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
1285 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
1287 *db
= (ar
>> 14) & 1;
1288 *l
= (ar
>> 13) & 1;
1291 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1293 dt
->limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
1294 dt
->base
= vmcs_readl(GUEST_IDTR_BASE
);
1297 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1299 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->limit
);
1300 vmcs_writel(GUEST_IDTR_BASE
, dt
->base
);
1303 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1305 dt
->limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
1306 dt
->base
= vmcs_readl(GUEST_GDTR_BASE
);
1309 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1311 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->limit
);
1312 vmcs_writel(GUEST_GDTR_BASE
, dt
->base
);
1315 static int init_rmode_tss(struct kvm
* kvm
)
1317 struct page
*p1
, *p2
, *p3
;
1318 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
1321 p1
= gfn_to_page(kvm
, fn
++);
1322 p2
= gfn_to_page(kvm
, fn
++);
1323 p3
= gfn_to_page(kvm
, fn
);
1325 if (!p1
|| !p2
|| !p3
) {
1326 kvm_printf(kvm
,"%s: gfn_to_page failed\n", __FUNCTION__
);
1330 page
= kmap_atomic(p1
, KM_USER0
);
1332 *(u16
*)(page
+ 0x66) = TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
1333 kunmap_atomic(page
, KM_USER0
);
1335 page
= kmap_atomic(p2
, KM_USER0
);
1337 kunmap_atomic(page
, KM_USER0
);
1339 page
= kmap_atomic(p3
, KM_USER0
);
1341 *(page
+ RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1) = ~0;
1342 kunmap_atomic(page
, KM_USER0
);
1347 static void seg_setup(int seg
)
1349 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1351 vmcs_write16(sf
->selector
, 0);
1352 vmcs_writel(sf
->base
, 0);
1353 vmcs_write32(sf
->limit
, 0xffff);
1354 vmcs_write32(sf
->ar_bytes
, 0x93);
1358 * Sets up the vmcs for emulated real mode.
1360 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
1362 u32 host_sysenter_cs
;
1365 struct descriptor_table dt
;
1368 unsigned long kvm_vmx_return
;
1370 if (!init_rmode_tss(vmx
->vcpu
.kvm
)) {
1375 vmx
->vcpu
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
1377 vmx
->vcpu
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1378 if (vmx
->vcpu
.vcpu_id
== 0)
1379 vmx
->vcpu
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1381 fx_init(&vmx
->vcpu
);
1384 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1385 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1387 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
1388 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
1389 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1390 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1392 seg_setup(VCPU_SREG_DS
);
1393 seg_setup(VCPU_SREG_ES
);
1394 seg_setup(VCPU_SREG_FS
);
1395 seg_setup(VCPU_SREG_GS
);
1396 seg_setup(VCPU_SREG_SS
);
1398 vmcs_write16(GUEST_TR_SELECTOR
, 0);
1399 vmcs_writel(GUEST_TR_BASE
, 0);
1400 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
1401 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1403 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
1404 vmcs_writel(GUEST_LDTR_BASE
, 0);
1405 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
1406 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
1408 vmcs_write32(GUEST_SYSENTER_CS
, 0);
1409 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
1410 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
1412 vmcs_writel(GUEST_RFLAGS
, 0x02);
1413 vmcs_writel(GUEST_RIP
, 0xfff0);
1414 vmcs_writel(GUEST_RSP
, 0);
1416 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1417 vmcs_writel(GUEST_DR7
, 0x400);
1419 vmcs_writel(GUEST_GDTR_BASE
, 0);
1420 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
1422 vmcs_writel(GUEST_IDTR_BASE
, 0);
1423 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
1425 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
1426 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
1427 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
1430 vmcs_write64(IO_BITMAP_A
, page_to_phys(vmx_io_bitmap_a
));
1431 vmcs_write64(IO_BITMAP_B
, page_to_phys(vmx_io_bitmap_b
));
1435 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
1437 /* Special registers */
1438 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
1441 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
1442 vmcs_config
.pin_based_exec_ctrl
);
1443 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1444 vmcs_config
.cpu_based_exec_ctrl
);
1446 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
1447 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
1448 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
1450 vmcs_writel(HOST_CR0
, read_cr0()); /* 22.2.3 */
1451 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
1452 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1454 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
1455 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
1456 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
1457 vmcs_write16(HOST_FS_SELECTOR
, read_fs()); /* 22.2.4 */
1458 vmcs_write16(HOST_GS_SELECTOR
, read_gs()); /* 22.2.4 */
1459 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
1460 #ifdef CONFIG_X86_64
1461 rdmsrl(MSR_FS_BASE
, a
);
1462 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
1463 rdmsrl(MSR_GS_BASE
, a
);
1464 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
1466 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
1467 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
1470 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
1473 vmcs_writel(HOST_IDTR_BASE
, dt
.base
); /* 22.2.4 */
1475 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
1476 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
1477 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
1478 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
1479 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
1481 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
1482 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
1483 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
1484 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
1485 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
1486 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
1488 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
1489 u32 index
= vmx_msr_index
[i
];
1490 u32 data_low
, data_high
;
1494 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
1496 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
1498 data
= data_low
| ((u64
)data_high
<< 32);
1499 vmx
->host_msrs
[j
].index
= index
;
1500 vmx
->host_msrs
[j
].reserved
= 0;
1501 vmx
->host_msrs
[j
].data
= data
;
1502 vmx
->guest_msrs
[j
] = vmx
->host_msrs
[j
];
1508 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
1510 /* 22.2.1, 20.8.1 */
1511 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
1513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
1515 #ifdef CONFIG_X86_64
1516 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR
, 0);
1517 vmcs_writel(TPR_THRESHOLD
, 0);
1520 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
1521 vmcs_writel(CR4_GUEST_HOST_MASK
, KVM_GUEST_CR4_MASK
);
1523 vmx
->vcpu
.cr0
= 0x60000010;
1524 vmx_set_cr0(&vmx
->vcpu
, vmx
->vcpu
.cr0
); // enter rmode
1525 vmx_set_cr4(&vmx
->vcpu
, 0);
1526 #ifdef CONFIG_X86_64
1527 vmx_set_efer(&vmx
->vcpu
, 0);
1529 vmx_fpu_activate(&vmx
->vcpu
);
1530 update_exception_bitmap(&vmx
->vcpu
);
1538 static void inject_rmode_irq(struct kvm_vcpu
*vcpu
, int irq
)
1543 unsigned long flags
;
1544 unsigned long ss_base
= vmcs_readl(GUEST_SS_BASE
);
1545 u16 sp
= vmcs_readl(GUEST_RSP
);
1546 u32 ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
1548 if (sp
> ss_limit
|| sp
< 6 ) {
1549 vcpu_printf(vcpu
, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1551 vmcs_readl(GUEST_RSP
),
1552 vmcs_readl(GUEST_SS_BASE
),
1553 vmcs_read32(GUEST_SS_LIMIT
));
1557 if (emulator_read_std(irq
* sizeof(ent
), &ent
, sizeof(ent
), vcpu
) !=
1559 vcpu_printf(vcpu
, "%s: read guest err\n", __FUNCTION__
);
1563 flags
= vmcs_readl(GUEST_RFLAGS
);
1564 cs
= vmcs_readl(GUEST_CS_BASE
) >> 4;
1565 ip
= vmcs_readl(GUEST_RIP
);
1568 if (emulator_write_emulated(ss_base
+ sp
- 2, &flags
, 2, vcpu
) != X86EMUL_CONTINUE
||
1569 emulator_write_emulated(ss_base
+ sp
- 4, &cs
, 2, vcpu
) != X86EMUL_CONTINUE
||
1570 emulator_write_emulated(ss_base
+ sp
- 6, &ip
, 2, vcpu
) != X86EMUL_CONTINUE
) {
1571 vcpu_printf(vcpu
, "%s: write guest err\n", __FUNCTION__
);
1575 vmcs_writel(GUEST_RFLAGS
, flags
&
1576 ~( X86_EFLAGS_IF
| X86_EFLAGS_AC
| X86_EFLAGS_TF
));
1577 vmcs_write16(GUEST_CS_SELECTOR
, ent
[1]) ;
1578 vmcs_writel(GUEST_CS_BASE
, ent
[1] << 4);
1579 vmcs_writel(GUEST_RIP
, ent
[0]);
1580 vmcs_writel(GUEST_RSP
, (vmcs_readl(GUEST_RSP
) & ~0xffff) | (sp
- 6));
1583 static void kvm_do_inject_irq(struct kvm_vcpu
*vcpu
)
1585 int word_index
= __ffs(vcpu
->irq_summary
);
1586 int bit_index
= __ffs(vcpu
->irq_pending
[word_index
]);
1587 int irq
= word_index
* BITS_PER_LONG
+ bit_index
;
1589 clear_bit(bit_index
, &vcpu
->irq_pending
[word_index
]);
1590 if (!vcpu
->irq_pending
[word_index
])
1591 clear_bit(word_index
, &vcpu
->irq_summary
);
1593 if (vcpu
->rmode
.active
) {
1594 inject_rmode_irq(vcpu
, irq
);
1597 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
1598 irq
| INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1602 static void do_interrupt_requests(struct kvm_vcpu
*vcpu
,
1603 struct kvm_run
*kvm_run
)
1605 u32 cpu_based_vm_exec_control
;
1607 vcpu
->interrupt_window_open
=
1608 ((vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
1609 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & 3) == 0);
1611 if (vcpu
->interrupt_window_open
&&
1612 vcpu
->irq_summary
&&
1613 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
) & INTR_INFO_VALID_MASK
))
1615 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1617 kvm_do_inject_irq(vcpu
);
1619 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
1620 if (!vcpu
->interrupt_window_open
&&
1621 (vcpu
->irq_summary
|| kvm_run
->request_interrupt_window
))
1623 * Interrupts blocked. Wait for unblock.
1625 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
1627 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
1628 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
1631 static void kvm_guest_debug_pre(struct kvm_vcpu
*vcpu
)
1633 struct kvm_guest_debug
*dbg
= &vcpu
->guest_debug
;
1635 set_debugreg(dbg
->bp
[0], 0);
1636 set_debugreg(dbg
->bp
[1], 1);
1637 set_debugreg(dbg
->bp
[2], 2);
1638 set_debugreg(dbg
->bp
[3], 3);
1640 if (dbg
->singlestep
) {
1641 unsigned long flags
;
1643 flags
= vmcs_readl(GUEST_RFLAGS
);
1644 flags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
1645 vmcs_writel(GUEST_RFLAGS
, flags
);
1649 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
1650 int vec
, u32 err_code
)
1652 if (!vcpu
->rmode
.active
)
1656 * Instruction with address size override prefix opcode 0x67
1657 * Cause the #SS fault with 0 error code in VM86 mode.
1659 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
1660 if (emulate_instruction(vcpu
, NULL
, 0, 0) == EMULATE_DONE
)
1665 static int handle_exception(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1667 u32 intr_info
, error_code
;
1668 unsigned long cr2
, rip
;
1670 enum emulation_result er
;
1673 vect_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
1674 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
1676 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
1677 !is_page_fault(intr_info
)) {
1678 printk(KERN_ERR
"%s: unexpected, vectoring info 0x%x "
1679 "intr info 0x%x\n", __FUNCTION__
, vect_info
, intr_info
);
1682 if (is_external_interrupt(vect_info
)) {
1683 int irq
= vect_info
& VECTORING_INFO_VECTOR_MASK
;
1684 set_bit(irq
, vcpu
->irq_pending
);
1685 set_bit(irq
/ BITS_PER_LONG
, &vcpu
->irq_summary
);
1688 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == 0x200) { /* nmi */
1693 if (is_no_device(intr_info
)) {
1694 vmx_fpu_activate(vcpu
);
1699 rip
= vmcs_readl(GUEST_RIP
);
1700 if (intr_info
& INTR_INFO_DELIEVER_CODE_MASK
)
1701 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
1702 if (is_page_fault(intr_info
)) {
1703 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
1705 mutex_lock(&vcpu
->kvm
->lock
);
1706 r
= kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
1708 mutex_unlock(&vcpu
->kvm
->lock
);
1712 mutex_unlock(&vcpu
->kvm
->lock
);
1716 er
= emulate_instruction(vcpu
, kvm_run
, cr2
, error_code
);
1717 mutex_unlock(&vcpu
->kvm
->lock
);
1722 case EMULATE_DO_MMIO
:
1723 ++vcpu
->stat
.mmio_exits
;
1726 vcpu_printf(vcpu
, "%s: emulate fail\n", __FUNCTION__
);
1733 if (vcpu
->rmode
.active
&&
1734 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
1736 if (vcpu
->halt_request
) {
1737 vcpu
->halt_request
= 0;
1738 return kvm_emulate_halt(vcpu
);
1743 if ((intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
)) == (INTR_TYPE_EXCEPTION
| 1)) {
1744 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1747 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
1748 kvm_run
->ex
.exception
= intr_info
& INTR_INFO_VECTOR_MASK
;
1749 kvm_run
->ex
.error_code
= error_code
;
1753 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
,
1754 struct kvm_run
*kvm_run
)
1756 ++vcpu
->stat
.irq_exits
;
1760 static int handle_triple_fault(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1762 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1766 static int get_io_count(struct kvm_vcpu
*vcpu
, unsigned long *count
)
1773 if ((vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_VM
)) {
1776 u32 cs_ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
1778 countr_size
= (cs_ar
& AR_L_MASK
) ? 8:
1779 (cs_ar
& AR_DB_MASK
) ? 4: 2;
1782 rip
= vmcs_readl(GUEST_RIP
);
1783 if (countr_size
!= 8)
1784 rip
+= vmcs_readl(GUEST_CS_BASE
);
1786 if (emulator_read_std(rip
, &inst
, sizeof(inst
), vcpu
) !=
1790 for (i
= 0; i
< sizeof(inst
); i
++) {
1791 switch (((u8
*)&inst
)[i
]) {
1804 countr_size
= (countr_size
== 2) ? 4: (countr_size
>> 1);
1812 *count
= vcpu
->regs
[VCPU_REGS_RCX
] & (~0ULL >> (64 - countr_size
));
1813 //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]);
1817 static int handle_io(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1819 u64 exit_qualification
;
1820 int size
, down
, in
, string
, rep
;
1822 unsigned long count
;
1825 ++vcpu
->stat
.io_exits
;
1826 exit_qualification
= vmcs_read64(EXIT_QUALIFICATION
);
1827 in
= (exit_qualification
& 8) != 0;
1828 size
= (exit_qualification
& 7) + 1;
1829 string
= (exit_qualification
& 16) != 0;
1830 down
= (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_DF
) != 0;
1832 rep
= (exit_qualification
& 32) != 0;
1833 port
= exit_qualification
>> 16;
1836 if (rep
&& !get_io_count(vcpu
, &count
))
1838 address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
1840 return kvm_setup_pio(vcpu
, kvm_run
, in
, size
, count
, string
, down
,
1841 address
, rep
, port
);
1845 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
1848 * Patch in the VMCALL instruction:
1850 hypercall
[0] = 0x0f;
1851 hypercall
[1] = 0x01;
1852 hypercall
[2] = 0xc1;
1853 hypercall
[3] = 0xc3;
1856 static int handle_cr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1858 u64 exit_qualification
;
1862 exit_qualification
= vmcs_read64(EXIT_QUALIFICATION
);
1863 cr
= exit_qualification
& 15;
1864 reg
= (exit_qualification
>> 8) & 15;
1865 switch ((exit_qualification
>> 4) & 3) {
1866 case 0: /* mov to cr */
1869 vcpu_load_rsp_rip(vcpu
);
1870 set_cr0(vcpu
, vcpu
->regs
[reg
]);
1871 skip_emulated_instruction(vcpu
);
1874 vcpu_load_rsp_rip(vcpu
);
1875 set_cr3(vcpu
, vcpu
->regs
[reg
]);
1876 skip_emulated_instruction(vcpu
);
1879 vcpu_load_rsp_rip(vcpu
);
1880 set_cr4(vcpu
, vcpu
->regs
[reg
]);
1881 skip_emulated_instruction(vcpu
);
1884 vcpu_load_rsp_rip(vcpu
);
1885 set_cr8(vcpu
, vcpu
->regs
[reg
]);
1886 skip_emulated_instruction(vcpu
);
1891 vcpu_load_rsp_rip(vcpu
);
1892 vmx_fpu_deactivate(vcpu
);
1893 vcpu
->cr0
&= ~X86_CR0_TS
;
1894 vmcs_writel(CR0_READ_SHADOW
, vcpu
->cr0
);
1895 vmx_fpu_activate(vcpu
);
1896 skip_emulated_instruction(vcpu
);
1898 case 1: /*mov from cr*/
1901 vcpu_load_rsp_rip(vcpu
);
1902 vcpu
->regs
[reg
] = vcpu
->cr3
;
1903 vcpu_put_rsp_rip(vcpu
);
1904 skip_emulated_instruction(vcpu
);
1907 vcpu_load_rsp_rip(vcpu
);
1908 vcpu
->regs
[reg
] = vcpu
->cr8
;
1909 vcpu_put_rsp_rip(vcpu
);
1910 skip_emulated_instruction(vcpu
);
1915 lmsw(vcpu
, (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f);
1917 skip_emulated_instruction(vcpu
);
1922 kvm_run
->exit_reason
= 0;
1923 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
1924 (int)(exit_qualification
>> 4) & 3, cr
);
1928 static int handle_dr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1930 u64 exit_qualification
;
1935 * FIXME: this code assumes the host is debugging the guest.
1936 * need to deal with guest debugging itself too.
1938 exit_qualification
= vmcs_read64(EXIT_QUALIFICATION
);
1939 dr
= exit_qualification
& 7;
1940 reg
= (exit_qualification
>> 8) & 15;
1941 vcpu_load_rsp_rip(vcpu
);
1942 if (exit_qualification
& 16) {
1954 vcpu
->regs
[reg
] = val
;
1958 vcpu_put_rsp_rip(vcpu
);
1959 skip_emulated_instruction(vcpu
);
1963 static int handle_cpuid(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1965 kvm_emulate_cpuid(vcpu
);
1969 static int handle_rdmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1971 u32 ecx
= vcpu
->regs
[VCPU_REGS_RCX
];
1974 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
1975 vmx_inject_gp(vcpu
, 0);
1979 /* FIXME: handling of bits 32:63 of rax, rdx */
1980 vcpu
->regs
[VCPU_REGS_RAX
] = data
& -1u;
1981 vcpu
->regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
1982 skip_emulated_instruction(vcpu
);
1986 static int handle_wrmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
1988 u32 ecx
= vcpu
->regs
[VCPU_REGS_RCX
];
1989 u64 data
= (vcpu
->regs
[VCPU_REGS_RAX
] & -1u)
1990 | ((u64
)(vcpu
->regs
[VCPU_REGS_RDX
] & -1u) << 32);
1992 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
1993 vmx_inject_gp(vcpu
, 0);
1997 skip_emulated_instruction(vcpu
);
2001 static void post_kvm_run_save(struct kvm_vcpu
*vcpu
,
2002 struct kvm_run
*kvm_run
)
2004 kvm_run
->if_flag
= (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) != 0;
2005 kvm_run
->cr8
= vcpu
->cr8
;
2006 kvm_run
->apic_base
= vcpu
->apic_base
;
2007 kvm_run
->ready_for_interrupt_injection
= (vcpu
->interrupt_window_open
&&
2008 vcpu
->irq_summary
== 0);
2011 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
,
2012 struct kvm_run
*kvm_run
)
2015 * If the user space waits to inject interrupts, exit as soon as
2018 if (kvm_run
->request_interrupt_window
&&
2019 !vcpu
->irq_summary
) {
2020 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2021 ++vcpu
->stat
.irq_window_exits
;
2027 static int handle_halt(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2029 skip_emulated_instruction(vcpu
);
2030 return kvm_emulate_halt(vcpu
);
2033 static int handle_vmcall(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2035 skip_emulated_instruction(vcpu
);
2036 return kvm_hypercall(vcpu
, kvm_run
);
2040 * The exit handlers return 1 if the exit was handled fully and guest execution
2041 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2042 * to be done to userspace and return 0.
2044 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
,
2045 struct kvm_run
*kvm_run
) = {
2046 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
2047 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
2048 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
2049 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
2050 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
2051 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
2052 [EXIT_REASON_CPUID
] = handle_cpuid
,
2053 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
2054 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
2055 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
2056 [EXIT_REASON_HLT
] = handle_halt
,
2057 [EXIT_REASON_VMCALL
] = handle_vmcall
,
2060 static const int kvm_vmx_max_exit_handlers
=
2061 ARRAY_SIZE(kvm_vmx_exit_handlers
);
2064 * The guest has exited. See if we can fix it or if we need userspace
2067 static int kvm_handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
2069 u32 vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
2070 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
2072 if ( (vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
2073 exit_reason
!= EXIT_REASON_EXCEPTION_NMI
)
2074 printk(KERN_WARNING
"%s: unexpected, valid vectoring info and "
2075 "exit reason is 0x%x\n", __FUNCTION__
, exit_reason
);
2076 if (exit_reason
< kvm_vmx_max_exit_handlers
2077 && kvm_vmx_exit_handlers
[exit_reason
])
2078 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
, kvm_run
);
2080 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2081 kvm_run
->hw
.hardware_exit_reason
= exit_reason
;
2087 * Check if userspace requested an interrupt window, and that the
2088 * interrupt window is open.
2090 * No need to exit to userspace if we already have an interrupt queued.
2092 static int dm_request_for_irq_injection(struct kvm_vcpu
*vcpu
,
2093 struct kvm_run
*kvm_run
)
2095 return (!vcpu
->irq_summary
&&
2096 kvm_run
->request_interrupt_window
&&
2097 vcpu
->interrupt_window_open
&&
2098 (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
));
2101 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
2105 static int vmx_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2107 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2112 if (vcpu
->guest_debug
.enabled
)
2113 kvm_guest_debug_pre(vcpu
);
2116 r
= kvm_mmu_reload(vcpu
);
2122 if (!vcpu
->mmio_read_completed
)
2123 do_interrupt_requests(vcpu
, kvm_run
);
2125 vmx_save_host_state(vmx
);
2126 kvm_load_guest_fpu(vcpu
);
2129 * Loading guest fpu may have cleared host cr0.ts
2131 vmcs_writel(HOST_CR0
, read_cr0());
2133 local_irq_disable();
2135 vcpu
->guest_mode
= 1;
2137 if (test_and_clear_bit(KVM_TLB_FLUSH
, &vcpu
->requests
))
2138 vmx_flush_tlb(vcpu
);
2141 /* Store host registers */
2142 #ifdef CONFIG_X86_64
2143 "push %%rax; push %%rbx; push %%rdx;"
2144 "push %%rsi; push %%rdi; push %%rbp;"
2145 "push %%r8; push %%r9; push %%r10; push %%r11;"
2146 "push %%r12; push %%r13; push %%r14; push %%r15;"
2148 ASM_VMX_VMWRITE_RSP_RDX
"\n\t"
2150 "pusha; push %%ecx \n\t"
2151 ASM_VMX_VMWRITE_RSP_RDX
"\n\t"
2153 /* Check if vmlaunch of vmresume is needed */
2155 /* Load guest registers. Don't clobber flags. */
2156 #ifdef CONFIG_X86_64
2157 "mov %c[cr2](%3), %%rax \n\t"
2158 "mov %%rax, %%cr2 \n\t"
2159 "mov %c[rax](%3), %%rax \n\t"
2160 "mov %c[rbx](%3), %%rbx \n\t"
2161 "mov %c[rdx](%3), %%rdx \n\t"
2162 "mov %c[rsi](%3), %%rsi \n\t"
2163 "mov %c[rdi](%3), %%rdi \n\t"
2164 "mov %c[rbp](%3), %%rbp \n\t"
2165 "mov %c[r8](%3), %%r8 \n\t"
2166 "mov %c[r9](%3), %%r9 \n\t"
2167 "mov %c[r10](%3), %%r10 \n\t"
2168 "mov %c[r11](%3), %%r11 \n\t"
2169 "mov %c[r12](%3), %%r12 \n\t"
2170 "mov %c[r13](%3), %%r13 \n\t"
2171 "mov %c[r14](%3), %%r14 \n\t"
2172 "mov %c[r15](%3), %%r15 \n\t"
2173 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2175 "mov %c[cr2](%3), %%eax \n\t"
2176 "mov %%eax, %%cr2 \n\t"
2177 "mov %c[rax](%3), %%eax \n\t"
2178 "mov %c[rbx](%3), %%ebx \n\t"
2179 "mov %c[rdx](%3), %%edx \n\t"
2180 "mov %c[rsi](%3), %%esi \n\t"
2181 "mov %c[rdi](%3), %%edi \n\t"
2182 "mov %c[rbp](%3), %%ebp \n\t"
2183 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2185 /* Enter guest mode */
2186 "jne .Llaunched \n\t"
2187 ASM_VMX_VMLAUNCH
"\n\t"
2188 "jmp .Lkvm_vmx_return \n\t"
2189 ".Llaunched: " ASM_VMX_VMRESUME
"\n\t"
2190 ".Lkvm_vmx_return: "
2191 /* Save guest registers, load host registers, keep flags */
2192 #ifdef CONFIG_X86_64
2193 "xchg %3, (%%rsp) \n\t"
2194 "mov %%rax, %c[rax](%3) \n\t"
2195 "mov %%rbx, %c[rbx](%3) \n\t"
2196 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
2197 "mov %%rdx, %c[rdx](%3) \n\t"
2198 "mov %%rsi, %c[rsi](%3) \n\t"
2199 "mov %%rdi, %c[rdi](%3) \n\t"
2200 "mov %%rbp, %c[rbp](%3) \n\t"
2201 "mov %%r8, %c[r8](%3) \n\t"
2202 "mov %%r9, %c[r9](%3) \n\t"
2203 "mov %%r10, %c[r10](%3) \n\t"
2204 "mov %%r11, %c[r11](%3) \n\t"
2205 "mov %%r12, %c[r12](%3) \n\t"
2206 "mov %%r13, %c[r13](%3) \n\t"
2207 "mov %%r14, %c[r14](%3) \n\t"
2208 "mov %%r15, %c[r15](%3) \n\t"
2209 "mov %%cr2, %%rax \n\t"
2210 "mov %%rax, %c[cr2](%3) \n\t"
2211 "mov (%%rsp), %3 \n\t"
2213 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2214 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2215 "pop %%rbp; pop %%rdi; pop %%rsi;"
2216 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2218 "xchg %3, (%%esp) \n\t"
2219 "mov %%eax, %c[rax](%3) \n\t"
2220 "mov %%ebx, %c[rbx](%3) \n\t"
2221 "pushl (%%esp); popl %c[rcx](%3) \n\t"
2222 "mov %%edx, %c[rdx](%3) \n\t"
2223 "mov %%esi, %c[rsi](%3) \n\t"
2224 "mov %%edi, %c[rdi](%3) \n\t"
2225 "mov %%ebp, %c[rbp](%3) \n\t"
2226 "mov %%cr2, %%eax \n\t"
2227 "mov %%eax, %c[cr2](%3) \n\t"
2228 "mov (%%esp), %3 \n\t"
2230 "pop %%ecx; popa \n\t"
2234 : "r"(vmx
->launched
), "d"((unsigned long)HOST_RSP
),
2236 [rax
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_RAX
])),
2237 [rbx
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_RBX
])),
2238 [rcx
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_RCX
])),
2239 [rdx
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_RDX
])),
2240 [rsi
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_RSI
])),
2241 [rdi
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_RDI
])),
2242 [rbp
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_RBP
])),
2243 #ifdef CONFIG_X86_64
2244 [r8
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_R8
])),
2245 [r9
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_R9
])),
2246 [r10
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_R10
])),
2247 [r11
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_R11
])),
2248 [r12
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_R12
])),
2249 [r13
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_R13
])),
2250 [r14
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_R14
])),
2251 [r15
]"i"(offsetof(struct kvm_vcpu
, regs
[VCPU_REGS_R15
])),
2253 [cr2
]"i"(offsetof(struct kvm_vcpu
, cr2
))
2256 vcpu
->guest_mode
= 0;
2261 vcpu
->interrupt_window_open
= (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & 3) == 0;
2263 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
2268 if (unlikely(fail
)) {
2269 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2270 kvm_run
->fail_entry
.hardware_entry_failure_reason
2271 = vmcs_read32(VM_INSTRUCTION_ERROR
);
2276 * Profile KVM exit RIPs:
2278 if (unlikely(prof_on
== KVM_PROFILING
))
2279 profile_hit(KVM_PROFILING
, (void *)vmcs_readl(GUEST_RIP
));
2281 r
= kvm_handle_exit(kvm_run
, vcpu
);
2283 /* Give scheduler a change to reschedule. */
2284 if (signal_pending(current
)) {
2286 kvm_run
->exit_reason
= KVM_EXIT_INTR
;
2287 ++vcpu
->stat
.signal_exits
;
2291 if (dm_request_for_irq_injection(vcpu
, kvm_run
)) {
2293 kvm_run
->exit_reason
= KVM_EXIT_INTR
;
2294 ++vcpu
->stat
.request_irq_exits
;
2297 if (!need_resched()) {
2298 ++vcpu
->stat
.light_exits
;
2309 post_kvm_run_save(vcpu
, kvm_run
);
2313 static void vmx_inject_page_fault(struct kvm_vcpu
*vcpu
,
2317 u32 vect_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
2319 ++vcpu
->stat
.pf_guest
;
2321 if (is_page_fault(vect_info
)) {
2322 printk(KERN_DEBUG
"inject_page_fault: "
2323 "double fault 0x%lx @ 0x%lx\n",
2324 addr
, vmcs_readl(GUEST_RIP
));
2325 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, 0);
2326 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2328 INTR_TYPE_EXCEPTION
|
2329 INTR_INFO_DELIEVER_CODE_MASK
|
2330 INTR_INFO_VALID_MASK
);
2334 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, err_code
);
2335 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2337 INTR_TYPE_EXCEPTION
|
2338 INTR_INFO_DELIEVER_CODE_MASK
|
2339 INTR_INFO_VALID_MASK
);
2343 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
2345 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2348 on_each_cpu(__vcpu_clear
, vmx
, 0, 1);
2349 free_vmcs(vmx
->vmcs
);
2354 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
2356 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2358 vmx_free_vmcs(vcpu
);
2359 kfree(vmx
->host_msrs
);
2360 kfree(vmx
->guest_msrs
);
2361 kvm_vcpu_uninit(vcpu
);
2365 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
2368 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
2372 return ERR_PTR(-ENOMEM
);
2374 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
2378 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
2379 if (!vmx
->guest_msrs
) {
2384 vmx
->host_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
2385 if (!vmx
->host_msrs
)
2386 goto free_guest_msrs
;
2388 vmx
->vmcs
= alloc_vmcs();
2392 vmcs_clear(vmx
->vmcs
);
2395 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
2396 err
= vmx_vcpu_setup(vmx
);
2397 vmx_vcpu_put(&vmx
->vcpu
);
2405 free_vmcs(vmx
->vmcs
);
2407 kfree(vmx
->host_msrs
);
2409 kfree(vmx
->guest_msrs
);
2411 kvm_vcpu_uninit(&vmx
->vcpu
);
2414 return ERR_PTR(err
);
2417 static void __init
vmx_check_processor_compat(void *rtn
)
2419 struct vmcs_config vmcs_conf
;
2422 if (setup_vmcs_config(&vmcs_conf
) < 0)
2424 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
2425 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
2426 smp_processor_id());
2431 static struct kvm_arch_ops vmx_arch_ops
= {
2432 .cpu_has_kvm_support
= cpu_has_kvm_support
,
2433 .disabled_by_bios
= vmx_disabled_by_bios
,
2434 .hardware_setup
= hardware_setup
,
2435 .hardware_unsetup
= hardware_unsetup
,
2436 .check_processor_compatibility
= vmx_check_processor_compat
,
2437 .hardware_enable
= hardware_enable
,
2438 .hardware_disable
= hardware_disable
,
2440 .vcpu_create
= vmx_create_vcpu
,
2441 .vcpu_free
= vmx_free_vcpu
,
2443 .vcpu_load
= vmx_vcpu_load
,
2444 .vcpu_put
= vmx_vcpu_put
,
2445 .vcpu_decache
= vmx_vcpu_decache
,
2447 .set_guest_debug
= set_guest_debug
,
2448 .get_msr
= vmx_get_msr
,
2449 .set_msr
= vmx_set_msr
,
2450 .get_segment_base
= vmx_get_segment_base
,
2451 .get_segment
= vmx_get_segment
,
2452 .set_segment
= vmx_set_segment
,
2453 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
2454 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
2455 .set_cr0
= vmx_set_cr0
,
2456 .set_cr3
= vmx_set_cr3
,
2457 .set_cr4
= vmx_set_cr4
,
2458 #ifdef CONFIG_X86_64
2459 .set_efer
= vmx_set_efer
,
2461 .get_idt
= vmx_get_idt
,
2462 .set_idt
= vmx_set_idt
,
2463 .get_gdt
= vmx_get_gdt
,
2464 .set_gdt
= vmx_set_gdt
,
2465 .cache_regs
= vcpu_load_rsp_rip
,
2466 .decache_regs
= vcpu_put_rsp_rip
,
2467 .get_rflags
= vmx_get_rflags
,
2468 .set_rflags
= vmx_set_rflags
,
2470 .tlb_flush
= vmx_flush_tlb
,
2471 .inject_page_fault
= vmx_inject_page_fault
,
2473 .inject_gp
= vmx_inject_gp
,
2475 .run
= vmx_vcpu_run
,
2476 .skip_emulated_instruction
= skip_emulated_instruction
,
2477 .patch_hypercall
= vmx_patch_hypercall
,
2480 static int __init
vmx_init(void)
2485 vmx_io_bitmap_a
= alloc_page(GFP_KERNEL
| __GFP_HIGHMEM
);
2486 if (!vmx_io_bitmap_a
)
2489 vmx_io_bitmap_b
= alloc_page(GFP_KERNEL
| __GFP_HIGHMEM
);
2490 if (!vmx_io_bitmap_b
) {
2496 * Allow direct access to the PC debug port (it is often used for I/O
2497 * delays, but the vmexits simply slow things down).
2499 iova
= kmap(vmx_io_bitmap_a
);
2500 memset(iova
, 0xff, PAGE_SIZE
);
2501 clear_bit(0x80, iova
);
2502 kunmap(vmx_io_bitmap_a
);
2504 iova
= kmap(vmx_io_bitmap_b
);
2505 memset(iova
, 0xff, PAGE_SIZE
);
2506 kunmap(vmx_io_bitmap_b
);
2508 r
= kvm_init_arch(&vmx_arch_ops
, sizeof(struct vcpu_vmx
), THIS_MODULE
);
2515 __free_page(vmx_io_bitmap_b
);
2517 __free_page(vmx_io_bitmap_a
);
2521 static void __exit
vmx_exit(void)
2523 __free_page(vmx_io_bitmap_b
);
2524 __free_page(vmx_io_bitmap_a
);
2529 module_init(vmx_init
)
2530 module_exit(vmx_exit
)