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KVM: VMX: Enable memory mapped TPR shadow (FlexPriority)
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "kvm.h"
19 #include "x86.h"
20 #include "x86_emulate.h"
21 #include "irq.h"
22 #include "vmx.h"
23 #include "segment_descriptor.h"
24
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/mm.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31
32 #include <asm/io.h>
33 #include <asm/desc.h>
34
35 MODULE_AUTHOR("Qumranet");
36 MODULE_LICENSE("GPL");
37
38 static int bypass_guest_pf = 1;
39 module_param(bypass_guest_pf, bool, 0);
40
41 struct vmcs {
42 u32 revision_id;
43 u32 abort;
44 char data[0];
45 };
46
47 struct vcpu_vmx {
48 struct kvm_vcpu vcpu;
49 int launched;
50 u8 fail;
51 struct kvm_msr_entry *guest_msrs;
52 struct kvm_msr_entry *host_msrs;
53 int nmsrs;
54 int save_nmsrs;
55 int msr_offset_efer;
56 #ifdef CONFIG_X86_64
57 int msr_offset_kernel_gs_base;
58 #endif
59 struct vmcs *vmcs;
60 struct {
61 int loaded;
62 u16 fs_sel, gs_sel, ldt_sel;
63 int gs_ldt_reload_needed;
64 int fs_reload_needed;
65 int guest_efer_loaded;
66 } host_state;
67
68 };
69
70 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
71 {
72 return container_of(vcpu, struct vcpu_vmx, vcpu);
73 }
74
75 static int init_rmode_tss(struct kvm *kvm);
76
77 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
78 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
79
80 static struct page *vmx_io_bitmap_a;
81 static struct page *vmx_io_bitmap_b;
82
83 static struct vmcs_config {
84 int size;
85 int order;
86 u32 revision_id;
87 u32 pin_based_exec_ctrl;
88 u32 cpu_based_exec_ctrl;
89 u32 cpu_based_2nd_exec_ctrl;
90 u32 vmexit_ctrl;
91 u32 vmentry_ctrl;
92 } vmcs_config;
93
94 #define VMX_SEGMENT_FIELD(seg) \
95 [VCPU_SREG_##seg] = { \
96 .selector = GUEST_##seg##_SELECTOR, \
97 .base = GUEST_##seg##_BASE, \
98 .limit = GUEST_##seg##_LIMIT, \
99 .ar_bytes = GUEST_##seg##_AR_BYTES, \
100 }
101
102 static struct kvm_vmx_segment_field {
103 unsigned selector;
104 unsigned base;
105 unsigned limit;
106 unsigned ar_bytes;
107 } kvm_vmx_segment_fields[] = {
108 VMX_SEGMENT_FIELD(CS),
109 VMX_SEGMENT_FIELD(DS),
110 VMX_SEGMENT_FIELD(ES),
111 VMX_SEGMENT_FIELD(FS),
112 VMX_SEGMENT_FIELD(GS),
113 VMX_SEGMENT_FIELD(SS),
114 VMX_SEGMENT_FIELD(TR),
115 VMX_SEGMENT_FIELD(LDTR),
116 };
117
118 /*
119 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
120 * away by decrementing the array size.
121 */
122 static const u32 vmx_msr_index[] = {
123 #ifdef CONFIG_X86_64
124 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
125 #endif
126 MSR_EFER, MSR_K6_STAR,
127 };
128 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
129
130 static void load_msrs(struct kvm_msr_entry *e, int n)
131 {
132 int i;
133
134 for (i = 0; i < n; ++i)
135 wrmsrl(e[i].index, e[i].data);
136 }
137
138 static void save_msrs(struct kvm_msr_entry *e, int n)
139 {
140 int i;
141
142 for (i = 0; i < n; ++i)
143 rdmsrl(e[i].index, e[i].data);
144 }
145
146 static inline int is_page_fault(u32 intr_info)
147 {
148 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
149 INTR_INFO_VALID_MASK)) ==
150 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
151 }
152
153 static inline int is_no_device(u32 intr_info)
154 {
155 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
156 INTR_INFO_VALID_MASK)) ==
157 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
158 }
159
160 static inline int is_invalid_opcode(u32 intr_info)
161 {
162 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
163 INTR_INFO_VALID_MASK)) ==
164 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
165 }
166
167 static inline int is_external_interrupt(u32 intr_info)
168 {
169 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
170 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
171 }
172
173 static inline int cpu_has_vmx_tpr_shadow(void)
174 {
175 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
176 }
177
178 static inline int vm_need_tpr_shadow(struct kvm *kvm)
179 {
180 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
181 }
182
183 static inline int cpu_has_secondary_exec_ctrls(void)
184 {
185 return (vmcs_config.cpu_based_exec_ctrl &
186 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
187 }
188
189 static inline int vm_need_secondary_exec_ctrls(struct kvm *kvm)
190 {
191 return ((cpu_has_secondary_exec_ctrls()) && (irqchip_in_kernel(kvm)));
192 }
193
194 static inline int cpu_has_vmx_virtualize_apic_accesses(void)
195 {
196 return (vmcs_config.cpu_based_2nd_exec_ctrl &
197 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
198 }
199
200 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
201 {
202 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
203 (irqchip_in_kernel(kvm)));
204 }
205
206 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
207 {
208 int i;
209
210 for (i = 0; i < vmx->nmsrs; ++i)
211 if (vmx->guest_msrs[i].index == msr)
212 return i;
213 return -1;
214 }
215
216 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
217 {
218 int i;
219
220 i = __find_msr_index(vmx, msr);
221 if (i >= 0)
222 return &vmx->guest_msrs[i];
223 return NULL;
224 }
225
226 static void vmcs_clear(struct vmcs *vmcs)
227 {
228 u64 phys_addr = __pa(vmcs);
229 u8 error;
230
231 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
232 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
233 : "cc", "memory");
234 if (error)
235 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
236 vmcs, phys_addr);
237 }
238
239 static void __vcpu_clear(void *arg)
240 {
241 struct vcpu_vmx *vmx = arg;
242 int cpu = raw_smp_processor_id();
243
244 if (vmx->vcpu.cpu == cpu)
245 vmcs_clear(vmx->vmcs);
246 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
247 per_cpu(current_vmcs, cpu) = NULL;
248 rdtscll(vmx->vcpu.host_tsc);
249 }
250
251 static void vcpu_clear(struct vcpu_vmx *vmx)
252 {
253 if (vmx->vcpu.cpu == -1)
254 return;
255 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
256 vmx->launched = 0;
257 }
258
259 static unsigned long vmcs_readl(unsigned long field)
260 {
261 unsigned long value;
262
263 asm volatile (ASM_VMX_VMREAD_RDX_RAX
264 : "=a"(value) : "d"(field) : "cc");
265 return value;
266 }
267
268 static u16 vmcs_read16(unsigned long field)
269 {
270 return vmcs_readl(field);
271 }
272
273 static u32 vmcs_read32(unsigned long field)
274 {
275 return vmcs_readl(field);
276 }
277
278 static u64 vmcs_read64(unsigned long field)
279 {
280 #ifdef CONFIG_X86_64
281 return vmcs_readl(field);
282 #else
283 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
284 #endif
285 }
286
287 static noinline void vmwrite_error(unsigned long field, unsigned long value)
288 {
289 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
290 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
291 dump_stack();
292 }
293
294 static void vmcs_writel(unsigned long field, unsigned long value)
295 {
296 u8 error;
297
298 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
299 : "=q"(error) : "a"(value), "d"(field) : "cc");
300 if (unlikely(error))
301 vmwrite_error(field, value);
302 }
303
304 static void vmcs_write16(unsigned long field, u16 value)
305 {
306 vmcs_writel(field, value);
307 }
308
309 static void vmcs_write32(unsigned long field, u32 value)
310 {
311 vmcs_writel(field, value);
312 }
313
314 static void vmcs_write64(unsigned long field, u64 value)
315 {
316 #ifdef CONFIG_X86_64
317 vmcs_writel(field, value);
318 #else
319 vmcs_writel(field, value);
320 asm volatile ("");
321 vmcs_writel(field+1, value >> 32);
322 #endif
323 }
324
325 static void vmcs_clear_bits(unsigned long field, u32 mask)
326 {
327 vmcs_writel(field, vmcs_readl(field) & ~mask);
328 }
329
330 static void vmcs_set_bits(unsigned long field, u32 mask)
331 {
332 vmcs_writel(field, vmcs_readl(field) | mask);
333 }
334
335 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
336 {
337 u32 eb;
338
339 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
340 if (!vcpu->fpu_active)
341 eb |= 1u << NM_VECTOR;
342 if (vcpu->guest_debug.enabled)
343 eb |= 1u << 1;
344 if (vcpu->rmode.active)
345 eb = ~0;
346 vmcs_write32(EXCEPTION_BITMAP, eb);
347 }
348
349 static void reload_tss(void)
350 {
351 #ifndef CONFIG_X86_64
352
353 /*
354 * VT restores TR but not its size. Useless.
355 */
356 struct descriptor_table gdt;
357 struct segment_descriptor *descs;
358
359 get_gdt(&gdt);
360 descs = (void *)gdt.base;
361 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
362 load_TR_desc();
363 #endif
364 }
365
366 static void load_transition_efer(struct vcpu_vmx *vmx)
367 {
368 int efer_offset = vmx->msr_offset_efer;
369 u64 host_efer = vmx->host_msrs[efer_offset].data;
370 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
371 u64 ignore_bits;
372
373 if (efer_offset < 0)
374 return;
375 /*
376 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
377 * outside long mode
378 */
379 ignore_bits = EFER_NX | EFER_SCE;
380 #ifdef CONFIG_X86_64
381 ignore_bits |= EFER_LMA | EFER_LME;
382 /* SCE is meaningful only in long mode on Intel */
383 if (guest_efer & EFER_LMA)
384 ignore_bits &= ~(u64)EFER_SCE;
385 #endif
386 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
387 return;
388
389 vmx->host_state.guest_efer_loaded = 1;
390 guest_efer &= ~ignore_bits;
391 guest_efer |= host_efer & ignore_bits;
392 wrmsrl(MSR_EFER, guest_efer);
393 vmx->vcpu.stat.efer_reload++;
394 }
395
396 static void reload_host_efer(struct vcpu_vmx *vmx)
397 {
398 if (vmx->host_state.guest_efer_loaded) {
399 vmx->host_state.guest_efer_loaded = 0;
400 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
401 }
402 }
403
404 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
405 {
406 struct vcpu_vmx *vmx = to_vmx(vcpu);
407
408 if (vmx->host_state.loaded)
409 return;
410
411 vmx->host_state.loaded = 1;
412 /*
413 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
414 * allow segment selectors with cpl > 0 or ti == 1.
415 */
416 vmx->host_state.ldt_sel = read_ldt();
417 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
418 vmx->host_state.fs_sel = read_fs();
419 if (!(vmx->host_state.fs_sel & 7)) {
420 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
421 vmx->host_state.fs_reload_needed = 0;
422 } else {
423 vmcs_write16(HOST_FS_SELECTOR, 0);
424 vmx->host_state.fs_reload_needed = 1;
425 }
426 vmx->host_state.gs_sel = read_gs();
427 if (!(vmx->host_state.gs_sel & 7))
428 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
429 else {
430 vmcs_write16(HOST_GS_SELECTOR, 0);
431 vmx->host_state.gs_ldt_reload_needed = 1;
432 }
433
434 #ifdef CONFIG_X86_64
435 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
436 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
437 #else
438 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
439 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
440 #endif
441
442 #ifdef CONFIG_X86_64
443 if (is_long_mode(&vmx->vcpu))
444 save_msrs(vmx->host_msrs +
445 vmx->msr_offset_kernel_gs_base, 1);
446
447 #endif
448 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
449 load_transition_efer(vmx);
450 }
451
452 static void vmx_load_host_state(struct vcpu_vmx *vmx)
453 {
454 unsigned long flags;
455
456 if (!vmx->host_state.loaded)
457 return;
458
459 vmx->host_state.loaded = 0;
460 if (vmx->host_state.fs_reload_needed)
461 load_fs(vmx->host_state.fs_sel);
462 if (vmx->host_state.gs_ldt_reload_needed) {
463 load_ldt(vmx->host_state.ldt_sel);
464 /*
465 * If we have to reload gs, we must take care to
466 * preserve our gs base.
467 */
468 local_irq_save(flags);
469 load_gs(vmx->host_state.gs_sel);
470 #ifdef CONFIG_X86_64
471 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
472 #endif
473 local_irq_restore(flags);
474 }
475 reload_tss();
476 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
477 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
478 reload_host_efer(vmx);
479 }
480
481 /*
482 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
483 * vcpu mutex is already taken.
484 */
485 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
486 {
487 struct vcpu_vmx *vmx = to_vmx(vcpu);
488 u64 phys_addr = __pa(vmx->vmcs);
489 u64 tsc_this, delta;
490
491 if (vcpu->cpu != cpu) {
492 vcpu_clear(vmx);
493 kvm_migrate_apic_timer(vcpu);
494 }
495
496 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
497 u8 error;
498
499 per_cpu(current_vmcs, cpu) = vmx->vmcs;
500 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
501 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
502 : "cc");
503 if (error)
504 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
505 vmx->vmcs, phys_addr);
506 }
507
508 if (vcpu->cpu != cpu) {
509 struct descriptor_table dt;
510 unsigned long sysenter_esp;
511
512 vcpu->cpu = cpu;
513 /*
514 * Linux uses per-cpu TSS and GDT, so set these when switching
515 * processors.
516 */
517 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
518 get_gdt(&dt);
519 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
520
521 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
522 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
523
524 /*
525 * Make sure the time stamp counter is monotonous.
526 */
527 rdtscll(tsc_this);
528 delta = vcpu->host_tsc - tsc_this;
529 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
530 }
531 }
532
533 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
534 {
535 vmx_load_host_state(to_vmx(vcpu));
536 kvm_put_guest_fpu(vcpu);
537 }
538
539 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
540 {
541 if (vcpu->fpu_active)
542 return;
543 vcpu->fpu_active = 1;
544 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
545 if (vcpu->cr0 & X86_CR0_TS)
546 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
547 update_exception_bitmap(vcpu);
548 }
549
550 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
551 {
552 if (!vcpu->fpu_active)
553 return;
554 vcpu->fpu_active = 0;
555 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
556 update_exception_bitmap(vcpu);
557 }
558
559 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
560 {
561 vcpu_clear(to_vmx(vcpu));
562 }
563
564 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
565 {
566 return vmcs_readl(GUEST_RFLAGS);
567 }
568
569 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
570 {
571 if (vcpu->rmode.active)
572 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
573 vmcs_writel(GUEST_RFLAGS, rflags);
574 }
575
576 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
577 {
578 unsigned long rip;
579 u32 interruptibility;
580
581 rip = vmcs_readl(GUEST_RIP);
582 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
583 vmcs_writel(GUEST_RIP, rip);
584
585 /*
586 * We emulated an instruction, so temporary interrupt blocking
587 * should be removed, if set.
588 */
589 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
590 if (interruptibility & 3)
591 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
592 interruptibility & ~3);
593 vcpu->interrupt_window_open = 1;
594 }
595
596 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
597 {
598 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
599 vmcs_readl(GUEST_RIP));
600 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
601 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
602 GP_VECTOR |
603 INTR_TYPE_EXCEPTION |
604 INTR_INFO_DELIEVER_CODE_MASK |
605 INTR_INFO_VALID_MASK);
606 }
607
608 static void vmx_inject_ud(struct kvm_vcpu *vcpu)
609 {
610 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
611 UD_VECTOR |
612 INTR_TYPE_EXCEPTION |
613 INTR_INFO_VALID_MASK);
614 }
615
616 /*
617 * Swap MSR entry in host/guest MSR entry array.
618 */
619 #ifdef CONFIG_X86_64
620 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
621 {
622 struct kvm_msr_entry tmp;
623
624 tmp = vmx->guest_msrs[to];
625 vmx->guest_msrs[to] = vmx->guest_msrs[from];
626 vmx->guest_msrs[from] = tmp;
627 tmp = vmx->host_msrs[to];
628 vmx->host_msrs[to] = vmx->host_msrs[from];
629 vmx->host_msrs[from] = tmp;
630 }
631 #endif
632
633 /*
634 * Set up the vmcs to automatically save and restore system
635 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
636 * mode, as fiddling with msrs is very expensive.
637 */
638 static void setup_msrs(struct vcpu_vmx *vmx)
639 {
640 int save_nmsrs;
641
642 save_nmsrs = 0;
643 #ifdef CONFIG_X86_64
644 if (is_long_mode(&vmx->vcpu)) {
645 int index;
646
647 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
648 if (index >= 0)
649 move_msr_up(vmx, index, save_nmsrs++);
650 index = __find_msr_index(vmx, MSR_LSTAR);
651 if (index >= 0)
652 move_msr_up(vmx, index, save_nmsrs++);
653 index = __find_msr_index(vmx, MSR_CSTAR);
654 if (index >= 0)
655 move_msr_up(vmx, index, save_nmsrs++);
656 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
657 if (index >= 0)
658 move_msr_up(vmx, index, save_nmsrs++);
659 /*
660 * MSR_K6_STAR is only needed on long mode guests, and only
661 * if efer.sce is enabled.
662 */
663 index = __find_msr_index(vmx, MSR_K6_STAR);
664 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
665 move_msr_up(vmx, index, save_nmsrs++);
666 }
667 #endif
668 vmx->save_nmsrs = save_nmsrs;
669
670 #ifdef CONFIG_X86_64
671 vmx->msr_offset_kernel_gs_base =
672 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
673 #endif
674 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
675 }
676
677 /*
678 * reads and returns guest's timestamp counter "register"
679 * guest_tsc = host_tsc + tsc_offset -- 21.3
680 */
681 static u64 guest_read_tsc(void)
682 {
683 u64 host_tsc, tsc_offset;
684
685 rdtscll(host_tsc);
686 tsc_offset = vmcs_read64(TSC_OFFSET);
687 return host_tsc + tsc_offset;
688 }
689
690 /*
691 * writes 'guest_tsc' into guest's timestamp counter "register"
692 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
693 */
694 static void guest_write_tsc(u64 guest_tsc)
695 {
696 u64 host_tsc;
697
698 rdtscll(host_tsc);
699 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
700 }
701
702 /*
703 * Reads an msr value (of 'msr_index') into 'pdata'.
704 * Returns 0 on success, non-0 otherwise.
705 * Assumes vcpu_load() was already called.
706 */
707 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
708 {
709 u64 data;
710 struct kvm_msr_entry *msr;
711
712 if (!pdata) {
713 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
714 return -EINVAL;
715 }
716
717 switch (msr_index) {
718 #ifdef CONFIG_X86_64
719 case MSR_FS_BASE:
720 data = vmcs_readl(GUEST_FS_BASE);
721 break;
722 case MSR_GS_BASE:
723 data = vmcs_readl(GUEST_GS_BASE);
724 break;
725 case MSR_EFER:
726 return kvm_get_msr_common(vcpu, msr_index, pdata);
727 #endif
728 case MSR_IA32_TIME_STAMP_COUNTER:
729 data = guest_read_tsc();
730 break;
731 case MSR_IA32_SYSENTER_CS:
732 data = vmcs_read32(GUEST_SYSENTER_CS);
733 break;
734 case MSR_IA32_SYSENTER_EIP:
735 data = vmcs_readl(GUEST_SYSENTER_EIP);
736 break;
737 case MSR_IA32_SYSENTER_ESP:
738 data = vmcs_readl(GUEST_SYSENTER_ESP);
739 break;
740 default:
741 msr = find_msr_entry(to_vmx(vcpu), msr_index);
742 if (msr) {
743 data = msr->data;
744 break;
745 }
746 return kvm_get_msr_common(vcpu, msr_index, pdata);
747 }
748
749 *pdata = data;
750 return 0;
751 }
752
753 /*
754 * Writes msr value into into the appropriate "register".
755 * Returns 0 on success, non-0 otherwise.
756 * Assumes vcpu_load() was already called.
757 */
758 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
759 {
760 struct vcpu_vmx *vmx = to_vmx(vcpu);
761 struct kvm_msr_entry *msr;
762 int ret = 0;
763
764 switch (msr_index) {
765 #ifdef CONFIG_X86_64
766 case MSR_EFER:
767 ret = kvm_set_msr_common(vcpu, msr_index, data);
768 if (vmx->host_state.loaded) {
769 reload_host_efer(vmx);
770 load_transition_efer(vmx);
771 }
772 break;
773 case MSR_FS_BASE:
774 vmcs_writel(GUEST_FS_BASE, data);
775 break;
776 case MSR_GS_BASE:
777 vmcs_writel(GUEST_GS_BASE, data);
778 break;
779 #endif
780 case MSR_IA32_SYSENTER_CS:
781 vmcs_write32(GUEST_SYSENTER_CS, data);
782 break;
783 case MSR_IA32_SYSENTER_EIP:
784 vmcs_writel(GUEST_SYSENTER_EIP, data);
785 break;
786 case MSR_IA32_SYSENTER_ESP:
787 vmcs_writel(GUEST_SYSENTER_ESP, data);
788 break;
789 case MSR_IA32_TIME_STAMP_COUNTER:
790 guest_write_tsc(data);
791 break;
792 default:
793 msr = find_msr_entry(vmx, msr_index);
794 if (msr) {
795 msr->data = data;
796 if (vmx->host_state.loaded)
797 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
798 break;
799 }
800 ret = kvm_set_msr_common(vcpu, msr_index, data);
801 }
802
803 return ret;
804 }
805
806 /*
807 * Sync the rsp and rip registers into the vcpu structure. This allows
808 * registers to be accessed by indexing vcpu->regs.
809 */
810 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
811 {
812 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
813 vcpu->rip = vmcs_readl(GUEST_RIP);
814 }
815
816 /*
817 * Syncs rsp and rip back into the vmcs. Should be called after possible
818 * modification.
819 */
820 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
821 {
822 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
823 vmcs_writel(GUEST_RIP, vcpu->rip);
824 }
825
826 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
827 {
828 unsigned long dr7 = 0x400;
829 int old_singlestep;
830
831 old_singlestep = vcpu->guest_debug.singlestep;
832
833 vcpu->guest_debug.enabled = dbg->enabled;
834 if (vcpu->guest_debug.enabled) {
835 int i;
836
837 dr7 |= 0x200; /* exact */
838 for (i = 0; i < 4; ++i) {
839 if (!dbg->breakpoints[i].enabled)
840 continue;
841 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
842 dr7 |= 2 << (i*2); /* global enable */
843 dr7 |= 0 << (i*4+16); /* execution breakpoint */
844 }
845
846 vcpu->guest_debug.singlestep = dbg->singlestep;
847 } else
848 vcpu->guest_debug.singlestep = 0;
849
850 if (old_singlestep && !vcpu->guest_debug.singlestep) {
851 unsigned long flags;
852
853 flags = vmcs_readl(GUEST_RFLAGS);
854 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
855 vmcs_writel(GUEST_RFLAGS, flags);
856 }
857
858 update_exception_bitmap(vcpu);
859 vmcs_writel(GUEST_DR7, dr7);
860
861 return 0;
862 }
863
864 static int vmx_get_irq(struct kvm_vcpu *vcpu)
865 {
866 u32 idtv_info_field;
867
868 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
869 if (idtv_info_field & INTR_INFO_VALID_MASK) {
870 if (is_external_interrupt(idtv_info_field))
871 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
872 else
873 printk(KERN_DEBUG "pending exception: not handled yet\n");
874 }
875 return -1;
876 }
877
878 static __init int cpu_has_kvm_support(void)
879 {
880 unsigned long ecx = cpuid_ecx(1);
881 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
882 }
883
884 static __init int vmx_disabled_by_bios(void)
885 {
886 u64 msr;
887
888 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
889 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
890 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
891 == MSR_IA32_FEATURE_CONTROL_LOCKED;
892 /* locked but not enabled */
893 }
894
895 static void hardware_enable(void *garbage)
896 {
897 int cpu = raw_smp_processor_id();
898 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
899 u64 old;
900
901 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
902 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
903 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
904 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
905 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
906 /* enable and lock */
907 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
908 MSR_IA32_FEATURE_CONTROL_LOCKED |
909 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
910 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
911 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
912 : "memory", "cc");
913 }
914
915 static void hardware_disable(void *garbage)
916 {
917 asm volatile (ASM_VMX_VMXOFF : : : "cc");
918 }
919
920 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
921 u32 msr, u32 *result)
922 {
923 u32 vmx_msr_low, vmx_msr_high;
924 u32 ctl = ctl_min | ctl_opt;
925
926 rdmsr(msr, vmx_msr_low, vmx_msr_high);
927
928 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
929 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
930
931 /* Ensure minimum (required) set of control bits are supported. */
932 if (ctl_min & ~ctl)
933 return -EIO;
934
935 *result = ctl;
936 return 0;
937 }
938
939 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
940 {
941 u32 vmx_msr_low, vmx_msr_high;
942 u32 min, opt;
943 u32 _pin_based_exec_control = 0;
944 u32 _cpu_based_exec_control = 0;
945 u32 _cpu_based_2nd_exec_control = 0;
946 u32 _vmexit_control = 0;
947 u32 _vmentry_control = 0;
948
949 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
950 opt = 0;
951 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
952 &_pin_based_exec_control) < 0)
953 return -EIO;
954
955 min = CPU_BASED_HLT_EXITING |
956 #ifdef CONFIG_X86_64
957 CPU_BASED_CR8_LOAD_EXITING |
958 CPU_BASED_CR8_STORE_EXITING |
959 #endif
960 CPU_BASED_USE_IO_BITMAPS |
961 CPU_BASED_MOV_DR_EXITING |
962 CPU_BASED_USE_TSC_OFFSETING;
963 opt = CPU_BASED_TPR_SHADOW |
964 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
965 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
966 &_cpu_based_exec_control) < 0)
967 return -EIO;
968 #ifdef CONFIG_X86_64
969 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
970 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
971 ~CPU_BASED_CR8_STORE_EXITING;
972 #endif
973 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
974 min = 0;
975 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
976 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
977 &_cpu_based_2nd_exec_control) < 0)
978 return -EIO;
979 }
980 #ifndef CONFIG_X86_64
981 if (!(_cpu_based_2nd_exec_control &
982 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
983 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
984 #endif
985
986 min = 0;
987 #ifdef CONFIG_X86_64
988 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
989 #endif
990 opt = 0;
991 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
992 &_vmexit_control) < 0)
993 return -EIO;
994
995 min = opt = 0;
996 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
997 &_vmentry_control) < 0)
998 return -EIO;
999
1000 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1001
1002 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1003 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1004 return -EIO;
1005
1006 #ifdef CONFIG_X86_64
1007 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1008 if (vmx_msr_high & (1u<<16))
1009 return -EIO;
1010 #endif
1011
1012 /* Require Write-Back (WB) memory type for VMCS accesses. */
1013 if (((vmx_msr_high >> 18) & 15) != 6)
1014 return -EIO;
1015
1016 vmcs_conf->size = vmx_msr_high & 0x1fff;
1017 vmcs_conf->order = get_order(vmcs_config.size);
1018 vmcs_conf->revision_id = vmx_msr_low;
1019
1020 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1021 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1022 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1023 vmcs_conf->vmexit_ctrl = _vmexit_control;
1024 vmcs_conf->vmentry_ctrl = _vmentry_control;
1025
1026 return 0;
1027 }
1028
1029 static struct vmcs *alloc_vmcs_cpu(int cpu)
1030 {
1031 int node = cpu_to_node(cpu);
1032 struct page *pages;
1033 struct vmcs *vmcs;
1034
1035 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1036 if (!pages)
1037 return NULL;
1038 vmcs = page_address(pages);
1039 memset(vmcs, 0, vmcs_config.size);
1040 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1041 return vmcs;
1042 }
1043
1044 static struct vmcs *alloc_vmcs(void)
1045 {
1046 return alloc_vmcs_cpu(raw_smp_processor_id());
1047 }
1048
1049 static void free_vmcs(struct vmcs *vmcs)
1050 {
1051 free_pages((unsigned long)vmcs, vmcs_config.order);
1052 }
1053
1054 static void free_kvm_area(void)
1055 {
1056 int cpu;
1057
1058 for_each_online_cpu(cpu)
1059 free_vmcs(per_cpu(vmxarea, cpu));
1060 }
1061
1062 static __init int alloc_kvm_area(void)
1063 {
1064 int cpu;
1065
1066 for_each_online_cpu(cpu) {
1067 struct vmcs *vmcs;
1068
1069 vmcs = alloc_vmcs_cpu(cpu);
1070 if (!vmcs) {
1071 free_kvm_area();
1072 return -ENOMEM;
1073 }
1074
1075 per_cpu(vmxarea, cpu) = vmcs;
1076 }
1077 return 0;
1078 }
1079
1080 static __init int hardware_setup(void)
1081 {
1082 if (setup_vmcs_config(&vmcs_config) < 0)
1083 return -EIO;
1084 return alloc_kvm_area();
1085 }
1086
1087 static __exit void hardware_unsetup(void)
1088 {
1089 free_kvm_area();
1090 }
1091
1092 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1093 {
1094 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1095
1096 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1097 vmcs_write16(sf->selector, save->selector);
1098 vmcs_writel(sf->base, save->base);
1099 vmcs_write32(sf->limit, save->limit);
1100 vmcs_write32(sf->ar_bytes, save->ar);
1101 } else {
1102 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1103 << AR_DPL_SHIFT;
1104 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1105 }
1106 }
1107
1108 static void enter_pmode(struct kvm_vcpu *vcpu)
1109 {
1110 unsigned long flags;
1111
1112 vcpu->rmode.active = 0;
1113
1114 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1115 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1116 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1117
1118 flags = vmcs_readl(GUEST_RFLAGS);
1119 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1120 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1121 vmcs_writel(GUEST_RFLAGS, flags);
1122
1123 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1124 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1125
1126 update_exception_bitmap(vcpu);
1127
1128 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1129 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1130 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1131 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1132
1133 vmcs_write16(GUEST_SS_SELECTOR, 0);
1134 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1135
1136 vmcs_write16(GUEST_CS_SELECTOR,
1137 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1138 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1139 }
1140
1141 static gva_t rmode_tss_base(struct kvm *kvm)
1142 {
1143 if (!kvm->tss_addr) {
1144 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1145 kvm->memslots[0].npages - 3;
1146 return base_gfn << PAGE_SHIFT;
1147 }
1148 return kvm->tss_addr;
1149 }
1150
1151 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1152 {
1153 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1154
1155 save->selector = vmcs_read16(sf->selector);
1156 save->base = vmcs_readl(sf->base);
1157 save->limit = vmcs_read32(sf->limit);
1158 save->ar = vmcs_read32(sf->ar_bytes);
1159 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1160 vmcs_write32(sf->limit, 0xffff);
1161 vmcs_write32(sf->ar_bytes, 0xf3);
1162 }
1163
1164 static void enter_rmode(struct kvm_vcpu *vcpu)
1165 {
1166 unsigned long flags;
1167
1168 vcpu->rmode.active = 1;
1169
1170 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1171 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1172
1173 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1174 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1175
1176 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1177 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1178
1179 flags = vmcs_readl(GUEST_RFLAGS);
1180 vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1181
1182 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1183
1184 vmcs_writel(GUEST_RFLAGS, flags);
1185 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1186 update_exception_bitmap(vcpu);
1187
1188 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1189 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1190 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1191
1192 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1193 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1194 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1195 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1196 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1197
1198 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1199 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1200 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1201 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1202
1203 kvm_mmu_reset_context(vcpu);
1204 init_rmode_tss(vcpu->kvm);
1205 }
1206
1207 #ifdef CONFIG_X86_64
1208
1209 static void enter_lmode(struct kvm_vcpu *vcpu)
1210 {
1211 u32 guest_tr_ar;
1212
1213 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1214 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1215 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1216 __FUNCTION__);
1217 vmcs_write32(GUEST_TR_AR_BYTES,
1218 (guest_tr_ar & ~AR_TYPE_MASK)
1219 | AR_TYPE_BUSY_64_TSS);
1220 }
1221
1222 vcpu->shadow_efer |= EFER_LMA;
1223
1224 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1225 vmcs_write32(VM_ENTRY_CONTROLS,
1226 vmcs_read32(VM_ENTRY_CONTROLS)
1227 | VM_ENTRY_IA32E_MODE);
1228 }
1229
1230 static void exit_lmode(struct kvm_vcpu *vcpu)
1231 {
1232 vcpu->shadow_efer &= ~EFER_LMA;
1233
1234 vmcs_write32(VM_ENTRY_CONTROLS,
1235 vmcs_read32(VM_ENTRY_CONTROLS)
1236 & ~VM_ENTRY_IA32E_MODE);
1237 }
1238
1239 #endif
1240
1241 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1242 {
1243 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1244 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1245 }
1246
1247 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1248 {
1249 vmx_fpu_deactivate(vcpu);
1250
1251 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1252 enter_pmode(vcpu);
1253
1254 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1255 enter_rmode(vcpu);
1256
1257 #ifdef CONFIG_X86_64
1258 if (vcpu->shadow_efer & EFER_LME) {
1259 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1260 enter_lmode(vcpu);
1261 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1262 exit_lmode(vcpu);
1263 }
1264 #endif
1265
1266 vmcs_writel(CR0_READ_SHADOW, cr0);
1267 vmcs_writel(GUEST_CR0,
1268 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1269 vcpu->cr0 = cr0;
1270
1271 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1272 vmx_fpu_activate(vcpu);
1273 }
1274
1275 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1276 {
1277 vmcs_writel(GUEST_CR3, cr3);
1278 if (vcpu->cr0 & X86_CR0_PE)
1279 vmx_fpu_deactivate(vcpu);
1280 }
1281
1282 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1283 {
1284 vmcs_writel(CR4_READ_SHADOW, cr4);
1285 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1286 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1287 vcpu->cr4 = cr4;
1288 }
1289
1290 #ifdef CONFIG_X86_64
1291
1292 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1293 {
1294 struct vcpu_vmx *vmx = to_vmx(vcpu);
1295 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1296
1297 vcpu->shadow_efer = efer;
1298 if (efer & EFER_LMA) {
1299 vmcs_write32(VM_ENTRY_CONTROLS,
1300 vmcs_read32(VM_ENTRY_CONTROLS) |
1301 VM_ENTRY_IA32E_MODE);
1302 msr->data = efer;
1303
1304 } else {
1305 vmcs_write32(VM_ENTRY_CONTROLS,
1306 vmcs_read32(VM_ENTRY_CONTROLS) &
1307 ~VM_ENTRY_IA32E_MODE);
1308
1309 msr->data = efer & ~EFER_LME;
1310 }
1311 setup_msrs(vmx);
1312 }
1313
1314 #endif
1315
1316 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1317 {
1318 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1319
1320 return vmcs_readl(sf->base);
1321 }
1322
1323 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1324 struct kvm_segment *var, int seg)
1325 {
1326 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1327 u32 ar;
1328
1329 var->base = vmcs_readl(sf->base);
1330 var->limit = vmcs_read32(sf->limit);
1331 var->selector = vmcs_read16(sf->selector);
1332 ar = vmcs_read32(sf->ar_bytes);
1333 if (ar & AR_UNUSABLE_MASK)
1334 ar = 0;
1335 var->type = ar & 15;
1336 var->s = (ar >> 4) & 1;
1337 var->dpl = (ar >> 5) & 3;
1338 var->present = (ar >> 7) & 1;
1339 var->avl = (ar >> 12) & 1;
1340 var->l = (ar >> 13) & 1;
1341 var->db = (ar >> 14) & 1;
1342 var->g = (ar >> 15) & 1;
1343 var->unusable = (ar >> 16) & 1;
1344 }
1345
1346 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1347 {
1348 u32 ar;
1349
1350 if (var->unusable)
1351 ar = 1 << 16;
1352 else {
1353 ar = var->type & 15;
1354 ar |= (var->s & 1) << 4;
1355 ar |= (var->dpl & 3) << 5;
1356 ar |= (var->present & 1) << 7;
1357 ar |= (var->avl & 1) << 12;
1358 ar |= (var->l & 1) << 13;
1359 ar |= (var->db & 1) << 14;
1360 ar |= (var->g & 1) << 15;
1361 }
1362 if (ar == 0) /* a 0 value means unusable */
1363 ar = AR_UNUSABLE_MASK;
1364
1365 return ar;
1366 }
1367
1368 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1369 struct kvm_segment *var, int seg)
1370 {
1371 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1372 u32 ar;
1373
1374 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1375 vcpu->rmode.tr.selector = var->selector;
1376 vcpu->rmode.tr.base = var->base;
1377 vcpu->rmode.tr.limit = var->limit;
1378 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1379 return;
1380 }
1381 vmcs_writel(sf->base, var->base);
1382 vmcs_write32(sf->limit, var->limit);
1383 vmcs_write16(sf->selector, var->selector);
1384 if (vcpu->rmode.active && var->s) {
1385 /*
1386 * Hack real-mode segments into vm86 compatibility.
1387 */
1388 if (var->base == 0xffff0000 && var->selector == 0xf000)
1389 vmcs_writel(sf->base, 0xf0000);
1390 ar = 0xf3;
1391 } else
1392 ar = vmx_segment_access_rights(var);
1393 vmcs_write32(sf->ar_bytes, ar);
1394 }
1395
1396 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1397 {
1398 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1399
1400 *db = (ar >> 14) & 1;
1401 *l = (ar >> 13) & 1;
1402 }
1403
1404 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1405 {
1406 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1407 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1408 }
1409
1410 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1411 {
1412 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1413 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1414 }
1415
1416 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1417 {
1418 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1419 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1420 }
1421
1422 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1423 {
1424 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1425 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1426 }
1427
1428 static int init_rmode_tss(struct kvm *kvm)
1429 {
1430 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1431 u16 data = 0;
1432 int r;
1433
1434 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1435 if (r < 0)
1436 return 0;
1437 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1438 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1439 if (r < 0)
1440 return 0;
1441 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1442 if (r < 0)
1443 return 0;
1444 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1445 if (r < 0)
1446 return 0;
1447 data = ~0;
1448 r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1449 sizeof(u8));
1450 if (r < 0)
1451 return 0;
1452 return 1;
1453 }
1454
1455 static void seg_setup(int seg)
1456 {
1457 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1458
1459 vmcs_write16(sf->selector, 0);
1460 vmcs_writel(sf->base, 0);
1461 vmcs_write32(sf->limit, 0xffff);
1462 vmcs_write32(sf->ar_bytes, 0x93);
1463 }
1464
1465 static int alloc_apic_access_page(struct kvm *kvm)
1466 {
1467 struct kvm_userspace_memory_region kvm_userspace_mem;
1468 int r = 0;
1469
1470 mutex_lock(&kvm->lock);
1471 if (kvm->apic_access_page)
1472 goto out;
1473 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1474 kvm_userspace_mem.flags = 0;
1475 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1476 kvm_userspace_mem.memory_size = PAGE_SIZE;
1477 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1478 if (r)
1479 goto out;
1480 kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1481 out:
1482 mutex_unlock(&kvm->lock);
1483 return r;
1484 }
1485
1486 /*
1487 * Sets up the vmcs for emulated real mode.
1488 */
1489 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1490 {
1491 u32 host_sysenter_cs;
1492 u32 junk;
1493 unsigned long a;
1494 struct descriptor_table dt;
1495 int i;
1496 unsigned long kvm_vmx_return;
1497 u32 exec_control;
1498
1499 /* I/O */
1500 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1501 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1502
1503 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1504
1505 /* Control */
1506 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1507 vmcs_config.pin_based_exec_ctrl);
1508
1509 exec_control = vmcs_config.cpu_based_exec_ctrl;
1510 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1511 exec_control &= ~CPU_BASED_TPR_SHADOW;
1512 #ifdef CONFIG_X86_64
1513 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1514 CPU_BASED_CR8_LOAD_EXITING;
1515 #endif
1516 }
1517 if (!vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1518 exec_control &= ~CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1519 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1520
1521 if (vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1522 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
1523 vmcs_config.cpu_based_2nd_exec_ctrl);
1524
1525 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1526 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1527 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1528
1529 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1530 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1531 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1532
1533 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1534 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1535 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1536 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1537 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1538 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1539 #ifdef CONFIG_X86_64
1540 rdmsrl(MSR_FS_BASE, a);
1541 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1542 rdmsrl(MSR_GS_BASE, a);
1543 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1544 #else
1545 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1546 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1547 #endif
1548
1549 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1550
1551 get_idt(&dt);
1552 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1553
1554 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1555 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1556 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1557 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1558 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1559
1560 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1561 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1562 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1563 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1564 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1565 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1566
1567 for (i = 0; i < NR_VMX_MSR; ++i) {
1568 u32 index = vmx_msr_index[i];
1569 u32 data_low, data_high;
1570 u64 data;
1571 int j = vmx->nmsrs;
1572
1573 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1574 continue;
1575 if (wrmsr_safe(index, data_low, data_high) < 0)
1576 continue;
1577 data = data_low | ((u64)data_high << 32);
1578 vmx->host_msrs[j].index = index;
1579 vmx->host_msrs[j].reserved = 0;
1580 vmx->host_msrs[j].data = data;
1581 vmx->guest_msrs[j] = vmx->host_msrs[j];
1582 ++vmx->nmsrs;
1583 }
1584
1585 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1586
1587 /* 22.2.1, 20.8.1 */
1588 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1589
1590 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1591 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1592
1593 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1594 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1595 return -ENOMEM;
1596
1597 return 0;
1598 }
1599
1600 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1601 {
1602 struct vcpu_vmx *vmx = to_vmx(vcpu);
1603 u64 msr;
1604 int ret;
1605
1606 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1607 ret = -ENOMEM;
1608 goto out;
1609 }
1610
1611 vmx->vcpu.rmode.active = 0;
1612
1613 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1614 set_cr8(&vmx->vcpu, 0);
1615 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1616 if (vmx->vcpu.vcpu_id == 0)
1617 msr |= MSR_IA32_APICBASE_BSP;
1618 kvm_set_apic_base(&vmx->vcpu, msr);
1619
1620 fx_init(&vmx->vcpu);
1621
1622 /*
1623 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1624 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1625 */
1626 if (vmx->vcpu.vcpu_id == 0) {
1627 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1628 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1629 } else {
1630 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1631 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1632 }
1633 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1634 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1635
1636 seg_setup(VCPU_SREG_DS);
1637 seg_setup(VCPU_SREG_ES);
1638 seg_setup(VCPU_SREG_FS);
1639 seg_setup(VCPU_SREG_GS);
1640 seg_setup(VCPU_SREG_SS);
1641
1642 vmcs_write16(GUEST_TR_SELECTOR, 0);
1643 vmcs_writel(GUEST_TR_BASE, 0);
1644 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1645 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1646
1647 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1648 vmcs_writel(GUEST_LDTR_BASE, 0);
1649 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1650 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1651
1652 vmcs_write32(GUEST_SYSENTER_CS, 0);
1653 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1654 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1655
1656 vmcs_writel(GUEST_RFLAGS, 0x02);
1657 if (vmx->vcpu.vcpu_id == 0)
1658 vmcs_writel(GUEST_RIP, 0xfff0);
1659 else
1660 vmcs_writel(GUEST_RIP, 0);
1661 vmcs_writel(GUEST_RSP, 0);
1662
1663 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1664 vmcs_writel(GUEST_DR7, 0x400);
1665
1666 vmcs_writel(GUEST_GDTR_BASE, 0);
1667 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1668
1669 vmcs_writel(GUEST_IDTR_BASE, 0);
1670 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1671
1672 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1673 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1674 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1675
1676 guest_write_tsc(0);
1677
1678 /* Special registers */
1679 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1680
1681 setup_msrs(vmx);
1682
1683 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1684
1685 if (cpu_has_vmx_tpr_shadow()) {
1686 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1687 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1688 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1689 page_to_phys(vmx->vcpu.apic->regs_page));
1690 vmcs_write32(TPR_THRESHOLD, 0);
1691 }
1692
1693 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1694 vmcs_write64(APIC_ACCESS_ADDR,
1695 page_to_phys(vmx->vcpu.kvm->apic_access_page));
1696
1697 vmx->vcpu.cr0 = 0x60000010;
1698 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
1699 vmx_set_cr4(&vmx->vcpu, 0);
1700 #ifdef CONFIG_X86_64
1701 vmx_set_efer(&vmx->vcpu, 0);
1702 #endif
1703 vmx_fpu_activate(&vmx->vcpu);
1704 update_exception_bitmap(&vmx->vcpu);
1705
1706 return 0;
1707
1708 out:
1709 return ret;
1710 }
1711
1712 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1713 {
1714 u16 ent[2];
1715 u16 cs;
1716 u16 ip;
1717 unsigned long flags;
1718 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1719 u16 sp = vmcs_readl(GUEST_RSP);
1720 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1721
1722 if (sp > ss_limit || sp < 6) {
1723 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1724 __FUNCTION__,
1725 vmcs_readl(GUEST_RSP),
1726 vmcs_readl(GUEST_SS_BASE),
1727 vmcs_read32(GUEST_SS_LIMIT));
1728 return;
1729 }
1730
1731 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1732 X86EMUL_CONTINUE) {
1733 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1734 return;
1735 }
1736
1737 flags = vmcs_readl(GUEST_RFLAGS);
1738 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1739 ip = vmcs_readl(GUEST_RIP);
1740
1741
1742 if (emulator_write_emulated(
1743 ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1744 emulator_write_emulated(
1745 ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1746 emulator_write_emulated(
1747 ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
1748 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1749 return;
1750 }
1751
1752 vmcs_writel(GUEST_RFLAGS, flags &
1753 ~(X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1754 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1755 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1756 vmcs_writel(GUEST_RIP, ent[0]);
1757 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1758 }
1759
1760 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1761 {
1762 if (vcpu->rmode.active) {
1763 inject_rmode_irq(vcpu, irq);
1764 return;
1765 }
1766 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1767 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1768 }
1769
1770 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1771 {
1772 int word_index = __ffs(vcpu->irq_summary);
1773 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1774 int irq = word_index * BITS_PER_LONG + bit_index;
1775
1776 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1777 if (!vcpu->irq_pending[word_index])
1778 clear_bit(word_index, &vcpu->irq_summary);
1779 vmx_inject_irq(vcpu, irq);
1780 }
1781
1782
1783 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1784 struct kvm_run *kvm_run)
1785 {
1786 u32 cpu_based_vm_exec_control;
1787
1788 vcpu->interrupt_window_open =
1789 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1790 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1791
1792 if (vcpu->interrupt_window_open &&
1793 vcpu->irq_summary &&
1794 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1795 /*
1796 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1797 */
1798 kvm_do_inject_irq(vcpu);
1799
1800 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1801 if (!vcpu->interrupt_window_open &&
1802 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1803 /*
1804 * Interrupts blocked. Wait for unblock.
1805 */
1806 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1807 else
1808 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1809 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1810 }
1811
1812 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1813 {
1814 int ret;
1815 struct kvm_userspace_memory_region tss_mem = {
1816 .slot = 8,
1817 .guest_phys_addr = addr,
1818 .memory_size = PAGE_SIZE * 3,
1819 .flags = 0,
1820 };
1821
1822 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1823 if (ret)
1824 return ret;
1825 kvm->tss_addr = addr;
1826 return 0;
1827 }
1828
1829 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1830 {
1831 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1832
1833 set_debugreg(dbg->bp[0], 0);
1834 set_debugreg(dbg->bp[1], 1);
1835 set_debugreg(dbg->bp[2], 2);
1836 set_debugreg(dbg->bp[3], 3);
1837
1838 if (dbg->singlestep) {
1839 unsigned long flags;
1840
1841 flags = vmcs_readl(GUEST_RFLAGS);
1842 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1843 vmcs_writel(GUEST_RFLAGS, flags);
1844 }
1845 }
1846
1847 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1848 int vec, u32 err_code)
1849 {
1850 if (!vcpu->rmode.active)
1851 return 0;
1852
1853 /*
1854 * Instruction with address size override prefix opcode 0x67
1855 * Cause the #SS fault with 0 error code in VM86 mode.
1856 */
1857 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1858 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1859 return 1;
1860 return 0;
1861 }
1862
1863 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1864 {
1865 u32 intr_info, error_code;
1866 unsigned long cr2, rip;
1867 u32 vect_info;
1868 enum emulation_result er;
1869
1870 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1871 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1872
1873 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1874 !is_page_fault(intr_info))
1875 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1876 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1877
1878 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1879 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1880 set_bit(irq, vcpu->irq_pending);
1881 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1882 }
1883
1884 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1885 return 1; /* already handled by vmx_vcpu_run() */
1886
1887 if (is_no_device(intr_info)) {
1888 vmx_fpu_activate(vcpu);
1889 return 1;
1890 }
1891
1892 if (is_invalid_opcode(intr_info)) {
1893 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1894 if (er != EMULATE_DONE)
1895 vmx_inject_ud(vcpu);
1896
1897 return 1;
1898 }
1899
1900 error_code = 0;
1901 rip = vmcs_readl(GUEST_RIP);
1902 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1903 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1904 if (is_page_fault(intr_info)) {
1905 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1906 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1907 }
1908
1909 if (vcpu->rmode.active &&
1910 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1911 error_code)) {
1912 if (vcpu->halt_request) {
1913 vcpu->halt_request = 0;
1914 return kvm_emulate_halt(vcpu);
1915 }
1916 return 1;
1917 }
1918
1919 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1920 (INTR_TYPE_EXCEPTION | 1)) {
1921 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1922 return 0;
1923 }
1924 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1925 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1926 kvm_run->ex.error_code = error_code;
1927 return 0;
1928 }
1929
1930 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1931 struct kvm_run *kvm_run)
1932 {
1933 ++vcpu->stat.irq_exits;
1934 return 1;
1935 }
1936
1937 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1938 {
1939 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1940 return 0;
1941 }
1942
1943 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1944 {
1945 unsigned long exit_qualification;
1946 int size, down, in, string, rep;
1947 unsigned port;
1948
1949 ++vcpu->stat.io_exits;
1950 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1951 string = (exit_qualification & 16) != 0;
1952
1953 if (string) {
1954 if (emulate_instruction(vcpu,
1955 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1956 return 0;
1957 return 1;
1958 }
1959
1960 size = (exit_qualification & 7) + 1;
1961 in = (exit_qualification & 8) != 0;
1962 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1963 rep = (exit_qualification & 32) != 0;
1964 port = exit_qualification >> 16;
1965
1966 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1967 }
1968
1969 static void
1970 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1971 {
1972 /*
1973 * Patch in the VMCALL instruction:
1974 */
1975 hypercall[0] = 0x0f;
1976 hypercall[1] = 0x01;
1977 hypercall[2] = 0xc1;
1978 }
1979
1980 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1981 {
1982 unsigned long exit_qualification;
1983 int cr;
1984 int reg;
1985
1986 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1987 cr = exit_qualification & 15;
1988 reg = (exit_qualification >> 8) & 15;
1989 switch ((exit_qualification >> 4) & 3) {
1990 case 0: /* mov to cr */
1991 switch (cr) {
1992 case 0:
1993 vcpu_load_rsp_rip(vcpu);
1994 set_cr0(vcpu, vcpu->regs[reg]);
1995 skip_emulated_instruction(vcpu);
1996 return 1;
1997 case 3:
1998 vcpu_load_rsp_rip(vcpu);
1999 set_cr3(vcpu, vcpu->regs[reg]);
2000 skip_emulated_instruction(vcpu);
2001 return 1;
2002 case 4:
2003 vcpu_load_rsp_rip(vcpu);
2004 set_cr4(vcpu, vcpu->regs[reg]);
2005 skip_emulated_instruction(vcpu);
2006 return 1;
2007 case 8:
2008 vcpu_load_rsp_rip(vcpu);
2009 set_cr8(vcpu, vcpu->regs[reg]);
2010 skip_emulated_instruction(vcpu);
2011 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2012 return 0;
2013 };
2014 break;
2015 case 2: /* clts */
2016 vcpu_load_rsp_rip(vcpu);
2017 vmx_fpu_deactivate(vcpu);
2018 vcpu->cr0 &= ~X86_CR0_TS;
2019 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
2020 vmx_fpu_activate(vcpu);
2021 skip_emulated_instruction(vcpu);
2022 return 1;
2023 case 1: /*mov from cr*/
2024 switch (cr) {
2025 case 3:
2026 vcpu_load_rsp_rip(vcpu);
2027 vcpu->regs[reg] = vcpu->cr3;
2028 vcpu_put_rsp_rip(vcpu);
2029 skip_emulated_instruction(vcpu);
2030 return 1;
2031 case 8:
2032 vcpu_load_rsp_rip(vcpu);
2033 vcpu->regs[reg] = get_cr8(vcpu);
2034 vcpu_put_rsp_rip(vcpu);
2035 skip_emulated_instruction(vcpu);
2036 return 1;
2037 }
2038 break;
2039 case 3: /* lmsw */
2040 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2041
2042 skip_emulated_instruction(vcpu);
2043 return 1;
2044 default:
2045 break;
2046 }
2047 kvm_run->exit_reason = 0;
2048 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2049 (int)(exit_qualification >> 4) & 3, cr);
2050 return 0;
2051 }
2052
2053 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2054 {
2055 unsigned long exit_qualification;
2056 unsigned long val;
2057 int dr, reg;
2058
2059 /*
2060 * FIXME: this code assumes the host is debugging the guest.
2061 * need to deal with guest debugging itself too.
2062 */
2063 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2064 dr = exit_qualification & 7;
2065 reg = (exit_qualification >> 8) & 15;
2066 vcpu_load_rsp_rip(vcpu);
2067 if (exit_qualification & 16) {
2068 /* mov from dr */
2069 switch (dr) {
2070 case 6:
2071 val = 0xffff0ff0;
2072 break;
2073 case 7:
2074 val = 0x400;
2075 break;
2076 default:
2077 val = 0;
2078 }
2079 vcpu->regs[reg] = val;
2080 } else {
2081 /* mov to dr */
2082 }
2083 vcpu_put_rsp_rip(vcpu);
2084 skip_emulated_instruction(vcpu);
2085 return 1;
2086 }
2087
2088 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2089 {
2090 kvm_emulate_cpuid(vcpu);
2091 return 1;
2092 }
2093
2094 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2095 {
2096 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2097 u64 data;
2098
2099 if (vmx_get_msr(vcpu, ecx, &data)) {
2100 vmx_inject_gp(vcpu, 0);
2101 return 1;
2102 }
2103
2104 /* FIXME: handling of bits 32:63 of rax, rdx */
2105 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2106 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2107 skip_emulated_instruction(vcpu);
2108 return 1;
2109 }
2110
2111 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2112 {
2113 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2114 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2115 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2116
2117 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2118 vmx_inject_gp(vcpu, 0);
2119 return 1;
2120 }
2121
2122 skip_emulated_instruction(vcpu);
2123 return 1;
2124 }
2125
2126 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2127 struct kvm_run *kvm_run)
2128 {
2129 return 1;
2130 }
2131
2132 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2133 struct kvm_run *kvm_run)
2134 {
2135 u32 cpu_based_vm_exec_control;
2136
2137 /* clear pending irq */
2138 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2139 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2140 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2141 /*
2142 * If the user space waits to inject interrupts, exit as soon as
2143 * possible
2144 */
2145 if (kvm_run->request_interrupt_window &&
2146 !vcpu->irq_summary) {
2147 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2148 ++vcpu->stat.irq_window_exits;
2149 return 0;
2150 }
2151 return 1;
2152 }
2153
2154 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2155 {
2156 skip_emulated_instruction(vcpu);
2157 return kvm_emulate_halt(vcpu);
2158 }
2159
2160 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2161 {
2162 skip_emulated_instruction(vcpu);
2163 kvm_emulate_hypercall(vcpu);
2164 return 1;
2165 }
2166
2167 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2168 {
2169 u64 exit_qualification;
2170 enum emulation_result er;
2171 unsigned long offset;
2172
2173 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2174 offset = exit_qualification & 0xffful;
2175
2176 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2177
2178 if (er != EMULATE_DONE) {
2179 printk(KERN_ERR
2180 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2181 offset);
2182 return -ENOTSUPP;
2183 }
2184 return 1;
2185 }
2186
2187 /*
2188 * The exit handlers return 1 if the exit was handled fully and guest execution
2189 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2190 * to be done to userspace and return 0.
2191 */
2192 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2193 struct kvm_run *kvm_run) = {
2194 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2195 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2196 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2197 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2198 [EXIT_REASON_CR_ACCESS] = handle_cr,
2199 [EXIT_REASON_DR_ACCESS] = handle_dr,
2200 [EXIT_REASON_CPUID] = handle_cpuid,
2201 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2202 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2203 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2204 [EXIT_REASON_HLT] = handle_halt,
2205 [EXIT_REASON_VMCALL] = handle_vmcall,
2206 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2207 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
2208 };
2209
2210 static const int kvm_vmx_max_exit_handlers =
2211 ARRAY_SIZE(kvm_vmx_exit_handlers);
2212
2213 /*
2214 * The guest has exited. See if we can fix it or if we need userspace
2215 * assistance.
2216 */
2217 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2218 {
2219 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2220 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2221 struct vcpu_vmx *vmx = to_vmx(vcpu);
2222
2223 if (unlikely(vmx->fail)) {
2224 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2225 kvm_run->fail_entry.hardware_entry_failure_reason
2226 = vmcs_read32(VM_INSTRUCTION_ERROR);
2227 return 0;
2228 }
2229
2230 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2231 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2232 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2233 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2234 if (exit_reason < kvm_vmx_max_exit_handlers
2235 && kvm_vmx_exit_handlers[exit_reason])
2236 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2237 else {
2238 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2239 kvm_run->hw.hardware_exit_reason = exit_reason;
2240 }
2241 return 0;
2242 }
2243
2244 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2245 {
2246 }
2247
2248 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2249 {
2250 int max_irr, tpr;
2251
2252 if (!vm_need_tpr_shadow(vcpu->kvm))
2253 return;
2254
2255 if (!kvm_lapic_enabled(vcpu) ||
2256 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2257 vmcs_write32(TPR_THRESHOLD, 0);
2258 return;
2259 }
2260
2261 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2262 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2263 }
2264
2265 static void enable_irq_window(struct kvm_vcpu *vcpu)
2266 {
2267 u32 cpu_based_vm_exec_control;
2268
2269 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2270 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2271 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2272 }
2273
2274 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2275 {
2276 u32 idtv_info_field, intr_info_field;
2277 int has_ext_irq, interrupt_window_open;
2278 int vector;
2279
2280 update_tpr_threshold(vcpu);
2281
2282 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2283 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2284 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2285 if (intr_info_field & INTR_INFO_VALID_MASK) {
2286 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2287 /* TODO: fault when IDT_Vectoring */
2288 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2289 }
2290 if (has_ext_irq)
2291 enable_irq_window(vcpu);
2292 return;
2293 }
2294 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2295 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2296 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2297 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2298
2299 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2300 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2301 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2302 if (unlikely(has_ext_irq))
2303 enable_irq_window(vcpu);
2304 return;
2305 }
2306 if (!has_ext_irq)
2307 return;
2308 interrupt_window_open =
2309 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2310 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2311 if (interrupt_window_open) {
2312 vector = kvm_cpu_get_interrupt(vcpu);
2313 vmx_inject_irq(vcpu, vector);
2314 kvm_timer_intr_post(vcpu, vector);
2315 } else
2316 enable_irq_window(vcpu);
2317 }
2318
2319 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2320 {
2321 struct vcpu_vmx *vmx = to_vmx(vcpu);
2322 u32 intr_info;
2323
2324 /*
2325 * Loading guest fpu may have cleared host cr0.ts
2326 */
2327 vmcs_writel(HOST_CR0, read_cr0());
2328
2329 asm(
2330 /* Store host registers */
2331 #ifdef CONFIG_X86_64
2332 "push %%rdx; push %%rbp;"
2333 "push %%rcx \n\t"
2334 #else
2335 "push %%edx; push %%ebp;"
2336 "push %%ecx \n\t"
2337 #endif
2338 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2339 /* Check if vmlaunch of vmresume is needed */
2340 "cmp $0, %1 \n\t"
2341 /* Load guest registers. Don't clobber flags. */
2342 #ifdef CONFIG_X86_64
2343 "mov %c[cr2](%3), %%rax \n\t"
2344 "mov %%rax, %%cr2 \n\t"
2345 "mov %c[rax](%3), %%rax \n\t"
2346 "mov %c[rbx](%3), %%rbx \n\t"
2347 "mov %c[rdx](%3), %%rdx \n\t"
2348 "mov %c[rsi](%3), %%rsi \n\t"
2349 "mov %c[rdi](%3), %%rdi \n\t"
2350 "mov %c[rbp](%3), %%rbp \n\t"
2351 "mov %c[r8](%3), %%r8 \n\t"
2352 "mov %c[r9](%3), %%r9 \n\t"
2353 "mov %c[r10](%3), %%r10 \n\t"
2354 "mov %c[r11](%3), %%r11 \n\t"
2355 "mov %c[r12](%3), %%r12 \n\t"
2356 "mov %c[r13](%3), %%r13 \n\t"
2357 "mov %c[r14](%3), %%r14 \n\t"
2358 "mov %c[r15](%3), %%r15 \n\t"
2359 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2360 #else
2361 "mov %c[cr2](%3), %%eax \n\t"
2362 "mov %%eax, %%cr2 \n\t"
2363 "mov %c[rax](%3), %%eax \n\t"
2364 "mov %c[rbx](%3), %%ebx \n\t"
2365 "mov %c[rdx](%3), %%edx \n\t"
2366 "mov %c[rsi](%3), %%esi \n\t"
2367 "mov %c[rdi](%3), %%edi \n\t"
2368 "mov %c[rbp](%3), %%ebp \n\t"
2369 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2370 #endif
2371 /* Enter guest mode */
2372 "jne .Llaunched \n\t"
2373 ASM_VMX_VMLAUNCH "\n\t"
2374 "jmp .Lkvm_vmx_return \n\t"
2375 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2376 ".Lkvm_vmx_return: "
2377 /* Save guest registers, load host registers, keep flags */
2378 #ifdef CONFIG_X86_64
2379 "xchg %3, (%%rsp) \n\t"
2380 "mov %%rax, %c[rax](%3) \n\t"
2381 "mov %%rbx, %c[rbx](%3) \n\t"
2382 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
2383 "mov %%rdx, %c[rdx](%3) \n\t"
2384 "mov %%rsi, %c[rsi](%3) \n\t"
2385 "mov %%rdi, %c[rdi](%3) \n\t"
2386 "mov %%rbp, %c[rbp](%3) \n\t"
2387 "mov %%r8, %c[r8](%3) \n\t"
2388 "mov %%r9, %c[r9](%3) \n\t"
2389 "mov %%r10, %c[r10](%3) \n\t"
2390 "mov %%r11, %c[r11](%3) \n\t"
2391 "mov %%r12, %c[r12](%3) \n\t"
2392 "mov %%r13, %c[r13](%3) \n\t"
2393 "mov %%r14, %c[r14](%3) \n\t"
2394 "mov %%r15, %c[r15](%3) \n\t"
2395 "mov %%cr2, %%rax \n\t"
2396 "mov %%rax, %c[cr2](%3) \n\t"
2397
2398 "pop %%rcx; pop %%rbp; pop %%rdx \n\t"
2399 #else
2400 "xchg %3, (%%esp) \n\t"
2401 "mov %%eax, %c[rax](%3) \n\t"
2402 "mov %%ebx, %c[rbx](%3) \n\t"
2403 "pushl (%%esp); popl %c[rcx](%3) \n\t"
2404 "mov %%edx, %c[rdx](%3) \n\t"
2405 "mov %%esi, %c[rsi](%3) \n\t"
2406 "mov %%edi, %c[rdi](%3) \n\t"
2407 "mov %%ebp, %c[rbp](%3) \n\t"
2408 "mov %%cr2, %%eax \n\t"
2409 "mov %%eax, %c[cr2](%3) \n\t"
2410
2411 "pop %%ecx; pop %%ebp; pop %%edx \n\t"
2412 #endif
2413 "setbe %0 \n\t"
2414 : "=q" (vmx->fail)
2415 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
2416 "c"(vcpu),
2417 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2418 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2419 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2420 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2421 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2422 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2423 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
2424 #ifdef CONFIG_X86_64
2425 [r8]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8])),
2426 [r9]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9])),
2427 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2428 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2429 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2430 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2431 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2432 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2433 #endif
2434 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2435 : "cc", "memory"
2436 #ifdef CONFIG_X86_64
2437 , "rbx", "rdi", "rsi"
2438 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2439 #else
2440 , "ebx", "edi", "rsi"
2441 #endif
2442 );
2443
2444 vcpu->interrupt_window_open =
2445 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2446
2447 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2448 vmx->launched = 1;
2449
2450 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2451
2452 /* We need to handle NMIs before interrupts are enabled */
2453 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2454 asm("int $2");
2455 }
2456
2457 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2458 unsigned long addr,
2459 u32 err_code)
2460 {
2461 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2462
2463 ++vcpu->stat.pf_guest;
2464
2465 if (is_page_fault(vect_info)) {
2466 printk(KERN_DEBUG "inject_page_fault: "
2467 "double fault 0x%lx @ 0x%lx\n",
2468 addr, vmcs_readl(GUEST_RIP));
2469 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2470 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2471 DF_VECTOR |
2472 INTR_TYPE_EXCEPTION |
2473 INTR_INFO_DELIEVER_CODE_MASK |
2474 INTR_INFO_VALID_MASK);
2475 return;
2476 }
2477 vcpu->cr2 = addr;
2478 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2479 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2480 PF_VECTOR |
2481 INTR_TYPE_EXCEPTION |
2482 INTR_INFO_DELIEVER_CODE_MASK |
2483 INTR_INFO_VALID_MASK);
2484
2485 }
2486
2487 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2488 {
2489 struct vcpu_vmx *vmx = to_vmx(vcpu);
2490
2491 if (vmx->vmcs) {
2492 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2493 free_vmcs(vmx->vmcs);
2494 vmx->vmcs = NULL;
2495 }
2496 }
2497
2498 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2499 {
2500 struct vcpu_vmx *vmx = to_vmx(vcpu);
2501
2502 vmx_free_vmcs(vcpu);
2503 kfree(vmx->host_msrs);
2504 kfree(vmx->guest_msrs);
2505 kvm_vcpu_uninit(vcpu);
2506 kmem_cache_free(kvm_vcpu_cache, vmx);
2507 }
2508
2509 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2510 {
2511 int err;
2512 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2513 int cpu;
2514
2515 if (!vmx)
2516 return ERR_PTR(-ENOMEM);
2517
2518 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2519 if (err)
2520 goto free_vcpu;
2521
2522 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2523 if (!vmx->guest_msrs) {
2524 err = -ENOMEM;
2525 goto uninit_vcpu;
2526 }
2527
2528 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2529 if (!vmx->host_msrs)
2530 goto free_guest_msrs;
2531
2532 vmx->vmcs = alloc_vmcs();
2533 if (!vmx->vmcs)
2534 goto free_msrs;
2535
2536 vmcs_clear(vmx->vmcs);
2537
2538 cpu = get_cpu();
2539 vmx_vcpu_load(&vmx->vcpu, cpu);
2540 err = vmx_vcpu_setup(vmx);
2541 vmx_vcpu_put(&vmx->vcpu);
2542 put_cpu();
2543 if (err)
2544 goto free_vmcs;
2545
2546 return &vmx->vcpu;
2547
2548 free_vmcs:
2549 free_vmcs(vmx->vmcs);
2550 free_msrs:
2551 kfree(vmx->host_msrs);
2552 free_guest_msrs:
2553 kfree(vmx->guest_msrs);
2554 uninit_vcpu:
2555 kvm_vcpu_uninit(&vmx->vcpu);
2556 free_vcpu:
2557 kmem_cache_free(kvm_vcpu_cache, vmx);
2558 return ERR_PTR(err);
2559 }
2560
2561 static void __init vmx_check_processor_compat(void *rtn)
2562 {
2563 struct vmcs_config vmcs_conf;
2564
2565 *(int *)rtn = 0;
2566 if (setup_vmcs_config(&vmcs_conf) < 0)
2567 *(int *)rtn = -EIO;
2568 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2569 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2570 smp_processor_id());
2571 *(int *)rtn = -EIO;
2572 }
2573 }
2574
2575 static struct kvm_x86_ops vmx_x86_ops = {
2576 .cpu_has_kvm_support = cpu_has_kvm_support,
2577 .disabled_by_bios = vmx_disabled_by_bios,
2578 .hardware_setup = hardware_setup,
2579 .hardware_unsetup = hardware_unsetup,
2580 .check_processor_compatibility = vmx_check_processor_compat,
2581 .hardware_enable = hardware_enable,
2582 .hardware_disable = hardware_disable,
2583
2584 .vcpu_create = vmx_create_vcpu,
2585 .vcpu_free = vmx_free_vcpu,
2586 .vcpu_reset = vmx_vcpu_reset,
2587
2588 .prepare_guest_switch = vmx_save_host_state,
2589 .vcpu_load = vmx_vcpu_load,
2590 .vcpu_put = vmx_vcpu_put,
2591 .vcpu_decache = vmx_vcpu_decache,
2592
2593 .set_guest_debug = set_guest_debug,
2594 .guest_debug_pre = kvm_guest_debug_pre,
2595 .get_msr = vmx_get_msr,
2596 .set_msr = vmx_set_msr,
2597 .get_segment_base = vmx_get_segment_base,
2598 .get_segment = vmx_get_segment,
2599 .set_segment = vmx_set_segment,
2600 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2601 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2602 .set_cr0 = vmx_set_cr0,
2603 .set_cr3 = vmx_set_cr3,
2604 .set_cr4 = vmx_set_cr4,
2605 #ifdef CONFIG_X86_64
2606 .set_efer = vmx_set_efer,
2607 #endif
2608 .get_idt = vmx_get_idt,
2609 .set_idt = vmx_set_idt,
2610 .get_gdt = vmx_get_gdt,
2611 .set_gdt = vmx_set_gdt,
2612 .cache_regs = vcpu_load_rsp_rip,
2613 .decache_regs = vcpu_put_rsp_rip,
2614 .get_rflags = vmx_get_rflags,
2615 .set_rflags = vmx_set_rflags,
2616
2617 .tlb_flush = vmx_flush_tlb,
2618 .inject_page_fault = vmx_inject_page_fault,
2619
2620 .inject_gp = vmx_inject_gp,
2621
2622 .run = vmx_vcpu_run,
2623 .handle_exit = kvm_handle_exit,
2624 .skip_emulated_instruction = skip_emulated_instruction,
2625 .patch_hypercall = vmx_patch_hypercall,
2626 .get_irq = vmx_get_irq,
2627 .set_irq = vmx_inject_irq,
2628 .inject_pending_irq = vmx_intr_assist,
2629 .inject_pending_vectors = do_interrupt_requests,
2630
2631 .set_tss_addr = vmx_set_tss_addr,
2632 };
2633
2634 static int __init vmx_init(void)
2635 {
2636 void *iova;
2637 int r;
2638
2639 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2640 if (!vmx_io_bitmap_a)
2641 return -ENOMEM;
2642
2643 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2644 if (!vmx_io_bitmap_b) {
2645 r = -ENOMEM;
2646 goto out;
2647 }
2648
2649 /*
2650 * Allow direct access to the PC debug port (it is often used for I/O
2651 * delays, but the vmexits simply slow things down).
2652 */
2653 iova = kmap(vmx_io_bitmap_a);
2654 memset(iova, 0xff, PAGE_SIZE);
2655 clear_bit(0x80, iova);
2656 kunmap(vmx_io_bitmap_a);
2657
2658 iova = kmap(vmx_io_bitmap_b);
2659 memset(iova, 0xff, PAGE_SIZE);
2660 kunmap(vmx_io_bitmap_b);
2661
2662 r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2663 if (r)
2664 goto out1;
2665
2666 if (bypass_guest_pf)
2667 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2668
2669 return 0;
2670
2671 out1:
2672 __free_page(vmx_io_bitmap_b);
2673 out:
2674 __free_page(vmx_io_bitmap_a);
2675 return r;
2676 }
2677
2678 static void __exit vmx_exit(void)
2679 {
2680 __free_page(vmx_io_bitmap_b);
2681 __free_page(vmx_io_bitmap_a);
2682
2683 kvm_exit_x86();
2684 }
2685
2686 module_init(vmx_init)
2687 module_exit(vmx_exit)
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