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[mirror_ubuntu-bionic-kernel.git] / drivers / media / platform / ti-vpe / vpe.c
1 /*
2 * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
3 *
4 * Copyright (c) 2013 Texas Instruments Inc.
5 * David Griego, <dagriego@biglakesoftware.com>
6 * Dale Farnsworth, <dale@farnsworth.org>
7 * Archit Taneja, <archit@ti.com>
8 *
9 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
10 * Pawel Osciak, <pawel@osciak.com>
11 * Marek Szyprowski, <m.szyprowski@samsung.com>
12 *
13 * Based on the virtual v4l2-mem2mem example device
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published by
17 * the Free Software Foundation
18 */
19
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/err.h>
23 #include <linux/fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/ioctl.h>
27 #include <linux/module.h>
28 #include <linux/of.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/videodev2.h>
34 #include <linux/log2.h>
35 #include <linux/sizes.h>
36
37 #include <media/v4l2-common.h>
38 #include <media/v4l2-ctrls.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-event.h>
41 #include <media/v4l2-ioctl.h>
42 #include <media/v4l2-mem2mem.h>
43 #include <media/videobuf2-v4l2.h>
44 #include <media/videobuf2-dma-contig.h>
45
46 #include "vpdma.h"
47 #include "vpdma_priv.h"
48 #include "vpe_regs.h"
49 #include "sc.h"
50 #include "csc.h"
51
52 #define VPE_MODULE_NAME "vpe"
53
54 /* minimum and maximum frame sizes */
55 #define MIN_W 32
56 #define MIN_H 32
57 #define MAX_W 2048
58 #define MAX_H 1184
59
60 /* required alignments */
61 #define S_ALIGN 0 /* multiple of 1 */
62 #define H_ALIGN 1 /* multiple of 2 */
63
64 /* flags that indicate a format can be used for capture/output */
65 #define VPE_FMT_TYPE_CAPTURE (1 << 0)
66 #define VPE_FMT_TYPE_OUTPUT (1 << 1)
67
68 /* used as plane indices */
69 #define VPE_MAX_PLANES 2
70 #define VPE_LUMA 0
71 #define VPE_CHROMA 1
72
73 /* per m2m context info */
74 #define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */
75
76 #define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */
77
78 /*
79 * each VPE context can need up to 3 config descriptors, 7 input descriptors,
80 * 3 output descriptors, and 10 control descriptors
81 */
82 #define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
83 13 * VPDMA_CFD_CTD_DESC_SIZE)
84
85 #define vpe_dbg(vpedev, fmt, arg...) \
86 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
87 #define vpe_err(vpedev, fmt, arg...) \
88 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
89
90 struct vpe_us_coeffs {
91 unsigned short anchor_fid0_c0;
92 unsigned short anchor_fid0_c1;
93 unsigned short anchor_fid0_c2;
94 unsigned short anchor_fid0_c3;
95 unsigned short interp_fid0_c0;
96 unsigned short interp_fid0_c1;
97 unsigned short interp_fid0_c2;
98 unsigned short interp_fid0_c3;
99 unsigned short anchor_fid1_c0;
100 unsigned short anchor_fid1_c1;
101 unsigned short anchor_fid1_c2;
102 unsigned short anchor_fid1_c3;
103 unsigned short interp_fid1_c0;
104 unsigned short interp_fid1_c1;
105 unsigned short interp_fid1_c2;
106 unsigned short interp_fid1_c3;
107 };
108
109 /*
110 * Default upsampler coefficients
111 */
112 static const struct vpe_us_coeffs us_coeffs[] = {
113 {
114 /* Coefficients for progressive input */
115 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
116 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
117 },
118 {
119 /* Coefficients for Top Field Interlaced input */
120 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
121 /* Coefficients for Bottom Field Interlaced input */
122 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
123 },
124 };
125
126 /*
127 * the following registers are for configuring some of the parameters of the
128 * motion and edge detection blocks inside DEI, these generally remain the same,
129 * these could be passed later via userspace if some one needs to tweak these.
130 */
131 struct vpe_dei_regs {
132 unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */
133 unsigned long edi_config_reg; /* VPE_DEI_REG3 */
134 unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */
135 unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */
136 unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */
137 unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */
138 };
139
140 /*
141 * default expert DEI register values, unlikely to be modified.
142 */
143 static const struct vpe_dei_regs dei_regs = {
144 .mdt_spacial_freq_thr_reg = 0x020C0804u,
145 .edi_config_reg = 0x0118100Cu,
146 .edi_lut_reg0 = 0x08040200u,
147 .edi_lut_reg1 = 0x1010100Cu,
148 .edi_lut_reg2 = 0x10101010u,
149 .edi_lut_reg3 = 0x10101010u,
150 };
151
152 /*
153 * The port_data structure contains per-port data.
154 */
155 struct vpe_port_data {
156 enum vpdma_channel channel; /* VPDMA channel */
157 u8 vb_index; /* input frame f, f-1, f-2 index */
158 u8 vb_part; /* plane index for co-panar formats */
159 };
160
161 /*
162 * Define indices into the port_data tables
163 */
164 #define VPE_PORT_LUMA1_IN 0
165 #define VPE_PORT_CHROMA1_IN 1
166 #define VPE_PORT_LUMA2_IN 2
167 #define VPE_PORT_CHROMA2_IN 3
168 #define VPE_PORT_LUMA3_IN 4
169 #define VPE_PORT_CHROMA3_IN 5
170 #define VPE_PORT_MV_IN 6
171 #define VPE_PORT_MV_OUT 7
172 #define VPE_PORT_LUMA_OUT 8
173 #define VPE_PORT_CHROMA_OUT 9
174 #define VPE_PORT_RGB_OUT 10
175
176 static const struct vpe_port_data port_data[11] = {
177 [VPE_PORT_LUMA1_IN] = {
178 .channel = VPE_CHAN_LUMA1_IN,
179 .vb_index = 0,
180 .vb_part = VPE_LUMA,
181 },
182 [VPE_PORT_CHROMA1_IN] = {
183 .channel = VPE_CHAN_CHROMA1_IN,
184 .vb_index = 0,
185 .vb_part = VPE_CHROMA,
186 },
187 [VPE_PORT_LUMA2_IN] = {
188 .channel = VPE_CHAN_LUMA2_IN,
189 .vb_index = 1,
190 .vb_part = VPE_LUMA,
191 },
192 [VPE_PORT_CHROMA2_IN] = {
193 .channel = VPE_CHAN_CHROMA2_IN,
194 .vb_index = 1,
195 .vb_part = VPE_CHROMA,
196 },
197 [VPE_PORT_LUMA3_IN] = {
198 .channel = VPE_CHAN_LUMA3_IN,
199 .vb_index = 2,
200 .vb_part = VPE_LUMA,
201 },
202 [VPE_PORT_CHROMA3_IN] = {
203 .channel = VPE_CHAN_CHROMA3_IN,
204 .vb_index = 2,
205 .vb_part = VPE_CHROMA,
206 },
207 [VPE_PORT_MV_IN] = {
208 .channel = VPE_CHAN_MV_IN,
209 },
210 [VPE_PORT_MV_OUT] = {
211 .channel = VPE_CHAN_MV_OUT,
212 },
213 [VPE_PORT_LUMA_OUT] = {
214 .channel = VPE_CHAN_LUMA_OUT,
215 .vb_part = VPE_LUMA,
216 },
217 [VPE_PORT_CHROMA_OUT] = {
218 .channel = VPE_CHAN_CHROMA_OUT,
219 .vb_part = VPE_CHROMA,
220 },
221 [VPE_PORT_RGB_OUT] = {
222 .channel = VPE_CHAN_RGB_OUT,
223 .vb_part = VPE_LUMA,
224 },
225 };
226
227
228 /* driver info for each of the supported video formats */
229 struct vpe_fmt {
230 char *name; /* human-readable name */
231 u32 fourcc; /* standard format identifier */
232 u8 types; /* CAPTURE and/or OUTPUT */
233 u8 coplanar; /* set for unpacked Luma and Chroma */
234 /* vpdma format info for each plane */
235 struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
236 };
237
238 static struct vpe_fmt vpe_formats[] = {
239 {
240 .name = "NV16 YUV 422 co-planar",
241 .fourcc = V4L2_PIX_FMT_NV16,
242 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
243 .coplanar = 1,
244 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
245 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
246 },
247 },
248 {
249 .name = "NV12 YUV 420 co-planar",
250 .fourcc = V4L2_PIX_FMT_NV12,
251 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
252 .coplanar = 1,
253 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
254 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
255 },
256 },
257 {
258 .name = "YUYV 422 packed",
259 .fourcc = V4L2_PIX_FMT_YUYV,
260 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
261 .coplanar = 0,
262 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCB422],
263 },
264 },
265 {
266 .name = "UYVY 422 packed",
267 .fourcc = V4L2_PIX_FMT_UYVY,
268 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
269 .coplanar = 0,
270 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CBY422],
271 },
272 },
273 {
274 .name = "RGB888 packed",
275 .fourcc = V4L2_PIX_FMT_RGB24,
276 .types = VPE_FMT_TYPE_CAPTURE,
277 .coplanar = 0,
278 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
279 },
280 },
281 {
282 .name = "ARGB32",
283 .fourcc = V4L2_PIX_FMT_RGB32,
284 .types = VPE_FMT_TYPE_CAPTURE,
285 .coplanar = 0,
286 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
287 },
288 },
289 {
290 .name = "BGR888 packed",
291 .fourcc = V4L2_PIX_FMT_BGR24,
292 .types = VPE_FMT_TYPE_CAPTURE,
293 .coplanar = 0,
294 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
295 },
296 },
297 {
298 .name = "ABGR32",
299 .fourcc = V4L2_PIX_FMT_BGR32,
300 .types = VPE_FMT_TYPE_CAPTURE,
301 .coplanar = 0,
302 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
303 },
304 },
305 {
306 .name = "RGB565",
307 .fourcc = V4L2_PIX_FMT_RGB565,
308 .types = VPE_FMT_TYPE_CAPTURE,
309 .coplanar = 0,
310 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB565],
311 },
312 },
313 {
314 .name = "RGB5551",
315 .fourcc = V4L2_PIX_FMT_RGB555,
316 .types = VPE_FMT_TYPE_CAPTURE,
317 .coplanar = 0,
318 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGBA16_5551],
319 },
320 },
321 };
322
323 /*
324 * per-queue, driver-specific private data.
325 * there is one source queue and one destination queue for each m2m context.
326 */
327 struct vpe_q_data {
328 unsigned int width; /* frame width */
329 unsigned int height; /* frame height */
330 unsigned int nplanes; /* Current number of planes */
331 unsigned int bytesperline[VPE_MAX_PLANES]; /* bytes per line in memory */
332 enum v4l2_colorspace colorspace;
333 enum v4l2_field field; /* supported field value */
334 unsigned int flags;
335 unsigned int sizeimage[VPE_MAX_PLANES]; /* image size in memory */
336 struct v4l2_rect c_rect; /* crop/compose rectangle */
337 struct vpe_fmt *fmt; /* format info */
338 };
339
340 /* vpe_q_data flag bits */
341 #define Q_DATA_FRAME_1D BIT(0)
342 #define Q_DATA_MODE_TILED BIT(1)
343 #define Q_DATA_INTERLACED_ALTERNATE BIT(2)
344 #define Q_DATA_INTERLACED_SEQ_TB BIT(3)
345
346 #define Q_IS_INTERLACED (Q_DATA_INTERLACED_ALTERNATE | \
347 Q_DATA_INTERLACED_SEQ_TB)
348
349 enum {
350 Q_DATA_SRC = 0,
351 Q_DATA_DST = 1,
352 };
353
354 /* find our format description corresponding to the passed v4l2_format */
355 static struct vpe_fmt *find_format(struct v4l2_format *f)
356 {
357 struct vpe_fmt *fmt;
358 unsigned int k;
359
360 for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
361 fmt = &vpe_formats[k];
362 if (fmt->fourcc == f->fmt.pix.pixelformat)
363 return fmt;
364 }
365
366 return NULL;
367 }
368
369 /*
370 * there is one vpe_dev structure in the driver, it is shared by
371 * all instances.
372 */
373 struct vpe_dev {
374 struct v4l2_device v4l2_dev;
375 struct video_device vfd;
376 struct v4l2_m2m_dev *m2m_dev;
377
378 atomic_t num_instances; /* count of driver instances */
379 dma_addr_t loaded_mmrs; /* shadow mmrs in device */
380 struct mutex dev_mutex;
381 spinlock_t lock;
382
383 int irq;
384 void __iomem *base;
385 struct resource *res;
386
387 struct vpdma_data vpdma_data;
388 struct vpdma_data *vpdma; /* vpdma data handle */
389 struct sc_data *sc; /* scaler data handle */
390 struct csc_data *csc; /* csc data handle */
391 };
392
393 /*
394 * There is one vpe_ctx structure for each m2m context.
395 */
396 struct vpe_ctx {
397 struct v4l2_fh fh;
398 struct vpe_dev *dev;
399 struct v4l2_ctrl_handler hdl;
400
401 unsigned int field; /* current field */
402 unsigned int sequence; /* current frame/field seq */
403 unsigned int aborting; /* abort after next irq */
404
405 unsigned int bufs_per_job; /* input buffers per batch */
406 unsigned int bufs_completed; /* bufs done in this batch */
407
408 struct vpe_q_data q_data[2]; /* src & dst queue data */
409 struct vb2_v4l2_buffer *src_vbs[VPE_MAX_SRC_BUFS];
410 struct vb2_v4l2_buffer *dst_vb;
411
412 dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */
413 void *mv_buf[2]; /* virtual addrs of motion vector bufs */
414 size_t mv_buf_size; /* current motion vector buffer size */
415 struct vpdma_buf mmr_adb; /* shadow reg addr/data block */
416 struct vpdma_buf sc_coeff_h; /* h coeff buffer */
417 struct vpdma_buf sc_coeff_v; /* v coeff buffer */
418 struct vpdma_desc_list desc_list; /* DMA descriptor list */
419
420 bool deinterlacing; /* using de-interlacer */
421 bool load_mmrs; /* have new shadow reg values */
422
423 unsigned int src_mv_buf_selector;
424 };
425
426
427 /*
428 * M2M devices get 2 queues.
429 * Return the queue given the type.
430 */
431 static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
432 enum v4l2_buf_type type)
433 {
434 switch (type) {
435 case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
436 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
437 return &ctx->q_data[Q_DATA_SRC];
438 case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
439 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
440 return &ctx->q_data[Q_DATA_DST];
441 default:
442 return NULL;
443 }
444 return NULL;
445 }
446
447 static u32 read_reg(struct vpe_dev *dev, int offset)
448 {
449 return ioread32(dev->base + offset);
450 }
451
452 static void write_reg(struct vpe_dev *dev, int offset, u32 value)
453 {
454 iowrite32(value, dev->base + offset);
455 }
456
457 /* register field read/write helpers */
458 static int get_field(u32 value, u32 mask, int shift)
459 {
460 return (value & (mask << shift)) >> shift;
461 }
462
463 static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
464 {
465 return get_field(read_reg(dev, offset), mask, shift);
466 }
467
468 static void write_field(u32 *valp, u32 field, u32 mask, int shift)
469 {
470 u32 val = *valp;
471
472 val &= ~(mask << shift);
473 val |= (field & mask) << shift;
474 *valp = val;
475 }
476
477 static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
478 u32 mask, int shift)
479 {
480 u32 val = read_reg(dev, offset);
481
482 write_field(&val, field, mask, shift);
483
484 write_reg(dev, offset, val);
485 }
486
487 /*
488 * DMA address/data block for the shadow registers
489 */
490 struct vpe_mmr_adb {
491 struct vpdma_adb_hdr out_fmt_hdr;
492 u32 out_fmt_reg[1];
493 u32 out_fmt_pad[3];
494 struct vpdma_adb_hdr us1_hdr;
495 u32 us1_regs[8];
496 struct vpdma_adb_hdr us2_hdr;
497 u32 us2_regs[8];
498 struct vpdma_adb_hdr us3_hdr;
499 u32 us3_regs[8];
500 struct vpdma_adb_hdr dei_hdr;
501 u32 dei_regs[8];
502 struct vpdma_adb_hdr sc_hdr0;
503 u32 sc_regs0[7];
504 u32 sc_pad0[1];
505 struct vpdma_adb_hdr sc_hdr8;
506 u32 sc_regs8[6];
507 u32 sc_pad8[2];
508 struct vpdma_adb_hdr sc_hdr17;
509 u32 sc_regs17[9];
510 u32 sc_pad17[3];
511 struct vpdma_adb_hdr csc_hdr;
512 u32 csc_regs[6];
513 u32 csc_pad[2];
514 };
515
516 #define GET_OFFSET_TOP(ctx, obj, reg) \
517 ((obj)->res->start - ctx->dev->res->start + reg)
518
519 #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
520 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
521 /*
522 * Set the headers for all of the address/data block structures.
523 */
524 static void init_adb_hdrs(struct vpe_ctx *ctx)
525 {
526 VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
527 VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
528 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
529 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
530 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
531 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,
532 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
533 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,
534 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));
535 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,
536 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));
537 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,
538 GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));
539 };
540
541 /*
542 * Allocate or re-allocate the motion vector DMA buffers
543 * There are two buffers, one for input and one for output.
544 * However, the roles are reversed after each field is processed.
545 * In other words, after each field is processed, the previous
546 * output (dst) MV buffer becomes the new input (src) MV buffer.
547 */
548 static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
549 {
550 struct device *dev = ctx->dev->v4l2_dev.dev;
551
552 if (ctx->mv_buf_size == size)
553 return 0;
554
555 if (ctx->mv_buf[0])
556 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
557 ctx->mv_buf_dma[0]);
558
559 if (ctx->mv_buf[1])
560 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
561 ctx->mv_buf_dma[1]);
562
563 if (size == 0)
564 return 0;
565
566 ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
567 GFP_KERNEL);
568 if (!ctx->mv_buf[0]) {
569 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
570 return -ENOMEM;
571 }
572
573 ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
574 GFP_KERNEL);
575 if (!ctx->mv_buf[1]) {
576 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
577 dma_free_coherent(dev, size, ctx->mv_buf[0],
578 ctx->mv_buf_dma[0]);
579
580 return -ENOMEM;
581 }
582
583 ctx->mv_buf_size = size;
584 ctx->src_mv_buf_selector = 0;
585
586 return 0;
587 }
588
589 static void free_mv_buffers(struct vpe_ctx *ctx)
590 {
591 realloc_mv_buffers(ctx, 0);
592 }
593
594 /*
595 * While de-interlacing, we keep the two most recent input buffers
596 * around. This function frees those two buffers when we have
597 * finished processing the current stream.
598 */
599 static void free_vbs(struct vpe_ctx *ctx)
600 {
601 struct vpe_dev *dev = ctx->dev;
602 unsigned long flags;
603
604 if (ctx->src_vbs[2] == NULL)
605 return;
606
607 spin_lock_irqsave(&dev->lock, flags);
608 if (ctx->src_vbs[2]) {
609 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
610 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
611 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
612 ctx->src_vbs[2] = NULL;
613 ctx->src_vbs[1] = NULL;
614 }
615 spin_unlock_irqrestore(&dev->lock, flags);
616 }
617
618 /*
619 * Enable or disable the VPE clocks
620 */
621 static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
622 {
623 u32 val = 0;
624
625 if (on)
626 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
627 write_reg(dev, VPE_CLK_ENABLE, val);
628 }
629
630 static void vpe_top_reset(struct vpe_dev *dev)
631 {
632
633 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
634 VPE_DATA_PATH_CLK_RESET_SHIFT);
635
636 usleep_range(100, 150);
637
638 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
639 VPE_DATA_PATH_CLK_RESET_SHIFT);
640 }
641
642 static void vpe_top_vpdma_reset(struct vpe_dev *dev)
643 {
644 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
645 VPE_VPDMA_CLK_RESET_SHIFT);
646
647 usleep_range(100, 150);
648
649 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
650 VPE_VPDMA_CLK_RESET_SHIFT);
651 }
652
653 /*
654 * Load the correct of upsampler coefficients into the shadow MMRs
655 */
656 static void set_us_coefficients(struct vpe_ctx *ctx)
657 {
658 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
659 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
660 u32 *us1_reg = &mmr_adb->us1_regs[0];
661 u32 *us2_reg = &mmr_adb->us2_regs[0];
662 u32 *us3_reg = &mmr_adb->us3_regs[0];
663 const unsigned short *cp, *end_cp;
664
665 cp = &us_coeffs[0].anchor_fid0_c0;
666
667 if (s_q_data->flags & Q_IS_INTERLACED) /* interlaced */
668 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
669
670 end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
671
672 while (cp < end_cp) {
673 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
674 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
675 *us2_reg++ = *us1_reg;
676 *us3_reg++ = *us1_reg++;
677 }
678 ctx->load_mmrs = true;
679 }
680
681 /*
682 * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
683 */
684 static void set_cfg_modes(struct vpe_ctx *ctx)
685 {
686 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
687 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
688 u32 *us1_reg0 = &mmr_adb->us1_regs[0];
689 u32 *us2_reg0 = &mmr_adb->us2_regs[0];
690 u32 *us3_reg0 = &mmr_adb->us3_regs[0];
691 int cfg_mode = 1;
692
693 /*
694 * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
695 * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
696 */
697
698 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
699 cfg_mode = 0;
700
701 write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
702 write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
703 write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
704
705 ctx->load_mmrs = true;
706 }
707
708 static void set_line_modes(struct vpe_ctx *ctx)
709 {
710 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
711 int line_mode = 1;
712
713 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
714 line_mode = 0; /* double lines to line buffer */
715
716 /* regs for now */
717 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
718 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
719 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
720
721 /* frame start for input luma */
722 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
723 VPE_CHAN_LUMA1_IN);
724 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
725 VPE_CHAN_LUMA2_IN);
726 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
727 VPE_CHAN_LUMA3_IN);
728
729 /* frame start for input chroma */
730 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
731 VPE_CHAN_CHROMA1_IN);
732 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
733 VPE_CHAN_CHROMA2_IN);
734 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
735 VPE_CHAN_CHROMA3_IN);
736
737 /* frame start for MV in client */
738 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
739 VPE_CHAN_MV_IN);
740 }
741
742 /*
743 * Set the shadow registers that are modified when the source
744 * format changes.
745 */
746 static void set_src_registers(struct vpe_ctx *ctx)
747 {
748 set_us_coefficients(ctx);
749 }
750
751 /*
752 * Set the shadow registers that are modified when the destination
753 * format changes.
754 */
755 static void set_dst_registers(struct vpe_ctx *ctx)
756 {
757 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
758 enum v4l2_colorspace clrspc = ctx->q_data[Q_DATA_DST].colorspace;
759 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
760 u32 val = 0;
761
762 if (clrspc == V4L2_COLORSPACE_SRGB) {
763 val |= VPE_RGB_OUT_SELECT;
764 vpdma_set_bg_color(ctx->dev->vpdma,
765 (struct vpdma_data_format *)fmt->vpdma_fmt[0], 0xff);
766 } else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
767 val |= VPE_COLOR_SEPARATE_422;
768
769 /*
770 * the source of CHR_DS and CSC is always the scaler, irrespective of
771 * whether it's used or not
772 */
773 val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER;
774
775 if (fmt->fourcc != V4L2_PIX_FMT_NV12)
776 val |= VPE_DS_BYPASS;
777
778 mmr_adb->out_fmt_reg[0] = val;
779
780 ctx->load_mmrs = true;
781 }
782
783 /*
784 * Set the de-interlacer shadow register values
785 */
786 static void set_dei_regs(struct vpe_ctx *ctx)
787 {
788 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
789 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
790 unsigned int src_h = s_q_data->c_rect.height;
791 unsigned int src_w = s_q_data->c_rect.width;
792 u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
793 bool deinterlace = true;
794 u32 val = 0;
795
796 /*
797 * according to TRM, we should set DEI in progressive bypass mode when
798 * the input content is progressive, however, DEI is bypassed correctly
799 * for both progressive and interlace content in interlace bypass mode.
800 * It has been recommended not to use progressive bypass mode.
801 */
802 if (!(s_q_data->flags & Q_IS_INTERLACED) || !ctx->deinterlacing) {
803 deinterlace = false;
804 val = VPE_DEI_INTERLACE_BYPASS;
805 }
806
807 src_h = deinterlace ? src_h * 2 : src_h;
808
809 val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
810 (src_w << VPE_DEI_WIDTH_SHIFT) |
811 VPE_DEI_FIELD_FLUSH;
812
813 *dei_mmr0 = val;
814
815 ctx->load_mmrs = true;
816 }
817
818 static void set_dei_shadow_registers(struct vpe_ctx *ctx)
819 {
820 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
821 u32 *dei_mmr = &mmr_adb->dei_regs[0];
822 const struct vpe_dei_regs *cur = &dei_regs;
823
824 dei_mmr[2] = cur->mdt_spacial_freq_thr_reg;
825 dei_mmr[3] = cur->edi_config_reg;
826 dei_mmr[4] = cur->edi_lut_reg0;
827 dei_mmr[5] = cur->edi_lut_reg1;
828 dei_mmr[6] = cur->edi_lut_reg2;
829 dei_mmr[7] = cur->edi_lut_reg3;
830
831 ctx->load_mmrs = true;
832 }
833
834 static void config_edi_input_mode(struct vpe_ctx *ctx, int mode)
835 {
836 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
837 u32 *edi_config_reg = &mmr_adb->dei_regs[3];
838
839 if (mode & 0x2)
840 write_field(edi_config_reg, 1, 1, 2); /* EDI_ENABLE_3D */
841
842 if (mode & 0x3)
843 write_field(edi_config_reg, 1, 1, 3); /* EDI_CHROMA_3D */
844
845 write_field(edi_config_reg, mode, VPE_EDI_INP_MODE_MASK,
846 VPE_EDI_INP_MODE_SHIFT);
847
848 ctx->load_mmrs = true;
849 }
850
851 /*
852 * Set the shadow registers whose values are modified when either the
853 * source or destination format is changed.
854 */
855 static int set_srcdst_params(struct vpe_ctx *ctx)
856 {
857 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
858 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
859 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
860 unsigned int src_w = s_q_data->c_rect.width;
861 unsigned int src_h = s_q_data->c_rect.height;
862 unsigned int dst_w = d_q_data->c_rect.width;
863 unsigned int dst_h = d_q_data->c_rect.height;
864 size_t mv_buf_size;
865 int ret;
866
867 ctx->sequence = 0;
868 ctx->field = V4L2_FIELD_TOP;
869
870 if ((s_q_data->flags & Q_IS_INTERLACED) &&
871 !(d_q_data->flags & Q_IS_INTERLACED)) {
872 int bytes_per_line;
873 const struct vpdma_data_format *mv =
874 &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
875
876 /*
877 * we make sure that the source image has a 16 byte aligned
878 * stride, we need to do the same for the motion vector buffer
879 * by aligning it's stride to the next 16 byte boundry. this
880 * extra space will not be used by the de-interlacer, but will
881 * ensure that vpdma operates correctly
882 */
883 bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3,
884 VPDMA_STRIDE_ALIGN);
885 mv_buf_size = bytes_per_line * s_q_data->height;
886
887 ctx->deinterlacing = true;
888 src_h <<= 1;
889 } else {
890 ctx->deinterlacing = false;
891 mv_buf_size = 0;
892 }
893
894 free_vbs(ctx);
895 ctx->src_vbs[2] = ctx->src_vbs[1] = ctx->src_vbs[0] = NULL;
896
897 ret = realloc_mv_buffers(ctx, mv_buf_size);
898 if (ret)
899 return ret;
900
901 set_cfg_modes(ctx);
902 set_dei_regs(ctx);
903
904 csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0],
905 s_q_data->colorspace, d_q_data->colorspace);
906
907 sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
908 sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
909
910 sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0],
911 &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
912 src_w, src_h, dst_w, dst_h);
913
914 return 0;
915 }
916
917 /*
918 * Return the vpe_ctx structure for a given struct file
919 */
920 static struct vpe_ctx *file2ctx(struct file *file)
921 {
922 return container_of(file->private_data, struct vpe_ctx, fh);
923 }
924
925 /*
926 * mem2mem callbacks
927 */
928
929 /**
930 * job_ready() - check whether an instance is ready to be scheduled to run
931 */
932 static int job_ready(void *priv)
933 {
934 struct vpe_ctx *ctx = priv;
935
936 /*
937 * This check is needed as this might be called directly from driver
938 * When called by m2m framework, this will always satisfy, but when
939 * called from vpe_irq, this might fail. (src stream with zero buffers)
940 */
941 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) <= 0 ||
942 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) <= 0)
943 return 0;
944
945 return 1;
946 }
947
948 static void job_abort(void *priv)
949 {
950 struct vpe_ctx *ctx = priv;
951
952 /* Will cancel the transaction in the next interrupt handler */
953 ctx->aborting = 1;
954 }
955
956 /*
957 * Lock access to the device
958 */
959 static void vpe_lock(void *priv)
960 {
961 struct vpe_ctx *ctx = priv;
962 struct vpe_dev *dev = ctx->dev;
963 mutex_lock(&dev->dev_mutex);
964 }
965
966 static void vpe_unlock(void *priv)
967 {
968 struct vpe_ctx *ctx = priv;
969 struct vpe_dev *dev = ctx->dev;
970 mutex_unlock(&dev->dev_mutex);
971 }
972
973 static void vpe_dump_regs(struct vpe_dev *dev)
974 {
975 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
976
977 vpe_dbg(dev, "VPE Registers:\n");
978
979 DUMPREG(PID);
980 DUMPREG(SYSCONFIG);
981 DUMPREG(INT0_STATUS0_RAW);
982 DUMPREG(INT0_STATUS0);
983 DUMPREG(INT0_ENABLE0);
984 DUMPREG(INT0_STATUS1_RAW);
985 DUMPREG(INT0_STATUS1);
986 DUMPREG(INT0_ENABLE1);
987 DUMPREG(CLK_ENABLE);
988 DUMPREG(CLK_RESET);
989 DUMPREG(CLK_FORMAT_SELECT);
990 DUMPREG(CLK_RANGE_MAP);
991 DUMPREG(US1_R0);
992 DUMPREG(US1_R1);
993 DUMPREG(US1_R2);
994 DUMPREG(US1_R3);
995 DUMPREG(US1_R4);
996 DUMPREG(US1_R5);
997 DUMPREG(US1_R6);
998 DUMPREG(US1_R7);
999 DUMPREG(US2_R0);
1000 DUMPREG(US2_R1);
1001 DUMPREG(US2_R2);
1002 DUMPREG(US2_R3);
1003 DUMPREG(US2_R4);
1004 DUMPREG(US2_R5);
1005 DUMPREG(US2_R6);
1006 DUMPREG(US2_R7);
1007 DUMPREG(US3_R0);
1008 DUMPREG(US3_R1);
1009 DUMPREG(US3_R2);
1010 DUMPREG(US3_R3);
1011 DUMPREG(US3_R4);
1012 DUMPREG(US3_R5);
1013 DUMPREG(US3_R6);
1014 DUMPREG(US3_R7);
1015 DUMPREG(DEI_FRAME_SIZE);
1016 DUMPREG(MDT_BYPASS);
1017 DUMPREG(MDT_SF_THRESHOLD);
1018 DUMPREG(EDI_CONFIG);
1019 DUMPREG(DEI_EDI_LUT_R0);
1020 DUMPREG(DEI_EDI_LUT_R1);
1021 DUMPREG(DEI_EDI_LUT_R2);
1022 DUMPREG(DEI_EDI_LUT_R3);
1023 DUMPREG(DEI_FMD_WINDOW_R0);
1024 DUMPREG(DEI_FMD_WINDOW_R1);
1025 DUMPREG(DEI_FMD_CONTROL_R0);
1026 DUMPREG(DEI_FMD_CONTROL_R1);
1027 DUMPREG(DEI_FMD_STATUS_R0);
1028 DUMPREG(DEI_FMD_STATUS_R1);
1029 DUMPREG(DEI_FMD_STATUS_R2);
1030 #undef DUMPREG
1031
1032 sc_dump_regs(dev->sc);
1033 csc_dump_regs(dev->csc);
1034 }
1035
1036 static void add_out_dtd(struct vpe_ctx *ctx, int port)
1037 {
1038 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
1039 const struct vpe_port_data *p_data = &port_data[port];
1040 struct vb2_buffer *vb = &ctx->dst_vb->vb2_buf;
1041 struct vpe_fmt *fmt = q_data->fmt;
1042 const struct vpdma_data_format *vpdma_fmt;
1043 int mv_buf_selector = !ctx->src_mv_buf_selector;
1044 dma_addr_t dma_addr;
1045 u32 flags = 0;
1046 u32 offset = 0;
1047
1048 if (port == VPE_PORT_MV_OUT) {
1049 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1050 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1051 q_data = &ctx->q_data[Q_DATA_SRC];
1052 } else {
1053 /* to incorporate interleaved formats */
1054 int plane = fmt->coplanar ? p_data->vb_part : 0;
1055
1056 vpdma_fmt = fmt->vpdma_fmt[plane];
1057 /*
1058 * If we are using a single plane buffer and
1059 * we need to set a separate vpdma chroma channel.
1060 */
1061 if (q_data->nplanes == 1 && plane) {
1062 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1063 /* Compute required offset */
1064 offset = q_data->bytesperline[0] * q_data->height;
1065 } else {
1066 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1067 /* Use address as is, no offset */
1068 offset = 0;
1069 }
1070 if (!dma_addr) {
1071 vpe_err(ctx->dev,
1072 "acquiring output buffer(%d) dma_addr failed\n",
1073 port);
1074 return;
1075 }
1076 /* Apply the offset */
1077 dma_addr += offset;
1078 }
1079
1080 if (q_data->flags & Q_DATA_FRAME_1D)
1081 flags |= VPDMA_DATA_FRAME_1D;
1082 if (q_data->flags & Q_DATA_MODE_TILED)
1083 flags |= VPDMA_DATA_MODE_TILED;
1084
1085 vpdma_set_max_size(ctx->dev->vpdma, VPDMA_MAX_SIZE1,
1086 MAX_W, MAX_H);
1087
1088 vpdma_add_out_dtd(&ctx->desc_list, q_data->width, &q_data->c_rect,
1089 vpdma_fmt, dma_addr, MAX_OUT_WIDTH_REG1,
1090 MAX_OUT_HEIGHT_REG1, p_data->channel, flags);
1091 }
1092
1093 static void add_in_dtd(struct vpe_ctx *ctx, int port)
1094 {
1095 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
1096 const struct vpe_port_data *p_data = &port_data[port];
1097 struct vb2_buffer *vb = &ctx->src_vbs[p_data->vb_index]->vb2_buf;
1098 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1099 struct vpe_fmt *fmt = q_data->fmt;
1100 const struct vpdma_data_format *vpdma_fmt;
1101 int mv_buf_selector = ctx->src_mv_buf_selector;
1102 int field = vbuf->field == V4L2_FIELD_BOTTOM;
1103 int frame_width, frame_height;
1104 dma_addr_t dma_addr;
1105 u32 flags = 0;
1106 u32 offset = 0;
1107
1108 if (port == VPE_PORT_MV_IN) {
1109 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1110 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1111 } else {
1112 /* to incorporate interleaved formats */
1113 int plane = fmt->coplanar ? p_data->vb_part : 0;
1114
1115 vpdma_fmt = fmt->vpdma_fmt[plane];
1116 /*
1117 * If we are using a single plane buffer and
1118 * we need to set a separate vpdma chroma channel.
1119 */
1120 if (q_data->nplanes == 1 && plane) {
1121 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1122 /* Compute required offset */
1123 offset = q_data->bytesperline[0] * q_data->height;
1124 } else {
1125 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1126 /* Use address as is, no offset */
1127 offset = 0;
1128 }
1129 if (!dma_addr) {
1130 vpe_err(ctx->dev,
1131 "acquiring output buffer(%d) dma_addr failed\n",
1132 port);
1133 return;
1134 }
1135 /* Apply the offset */
1136 dma_addr += offset;
1137
1138 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB) {
1139 /*
1140 * Use top or bottom field from same vb alternately
1141 * f,f-1,f-2 = TBT when seq is even
1142 * f,f-1,f-2 = BTB when seq is odd
1143 */
1144 field = (p_data->vb_index + (ctx->sequence % 2)) % 2;
1145
1146 if (field) {
1147 /*
1148 * bottom field of a SEQ_TB buffer
1149 * Skip the top field data by
1150 */
1151 int height = q_data->height / 2;
1152 int bpp = fmt->fourcc == V4L2_PIX_FMT_NV12 ?
1153 1 : (vpdma_fmt->depth >> 3);
1154 if (plane)
1155 height /= 2;
1156 dma_addr += q_data->width * height * bpp;
1157 }
1158 }
1159 }
1160
1161 if (q_data->flags & Q_DATA_FRAME_1D)
1162 flags |= VPDMA_DATA_FRAME_1D;
1163 if (q_data->flags & Q_DATA_MODE_TILED)
1164 flags |= VPDMA_DATA_MODE_TILED;
1165
1166 frame_width = q_data->c_rect.width;
1167 frame_height = q_data->c_rect.height;
1168
1169 if (p_data->vb_part && fmt->fourcc == V4L2_PIX_FMT_NV12)
1170 frame_height /= 2;
1171
1172 vpdma_add_in_dtd(&ctx->desc_list, q_data->width, &q_data->c_rect,
1173 vpdma_fmt, dma_addr, p_data->channel, field, flags, frame_width,
1174 frame_height, 0, 0);
1175 }
1176
1177 /*
1178 * Enable the expected IRQ sources
1179 */
1180 static void enable_irqs(struct vpe_ctx *ctx)
1181 {
1182 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
1183 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1184 VPE_DS1_UV_ERROR_INT);
1185
1186 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, true);
1187 }
1188
1189 static void disable_irqs(struct vpe_ctx *ctx)
1190 {
1191 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1192 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1193
1194 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, false);
1195 }
1196
1197 /* device_run() - prepares and starts the device
1198 *
1199 * This function is only called when both the source and destination
1200 * buffers are in place.
1201 */
1202 static void device_run(void *priv)
1203 {
1204 struct vpe_ctx *ctx = priv;
1205 struct sc_data *sc = ctx->dev->sc;
1206 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1207 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
1208
1209 if (ctx->deinterlacing && s_q_data->flags & Q_DATA_INTERLACED_SEQ_TB &&
1210 ctx->sequence % 2 == 0) {
1211 /* When using SEQ_TB buffers, When using it first time,
1212 * No need to remove the buffer as the next field is present
1213 * in the same buffer. (so that job_ready won't fail)
1214 * It will be removed when using bottom field
1215 */
1216 ctx->src_vbs[0] = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1217 WARN_ON(ctx->src_vbs[0] == NULL);
1218 } else {
1219 ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1220 WARN_ON(ctx->src_vbs[0] == NULL);
1221 }
1222
1223 ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1224 WARN_ON(ctx->dst_vb == NULL);
1225
1226 if (ctx->deinterlacing) {
1227
1228 if (ctx->src_vbs[2] == NULL) {
1229 ctx->src_vbs[2] = ctx->src_vbs[0];
1230 WARN_ON(ctx->src_vbs[2] == NULL);
1231 ctx->src_vbs[1] = ctx->src_vbs[0];
1232 WARN_ON(ctx->src_vbs[1] == NULL);
1233 }
1234
1235 /*
1236 * we have output the first 2 frames through line average, we
1237 * now switch to EDI de-interlacer
1238 */
1239 if (ctx->sequence == 2)
1240 config_edi_input_mode(ctx, 0x3); /* EDI (Y + UV) */
1241 }
1242
1243 /* config descriptors */
1244 if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1245 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1246 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1247
1248 set_line_modes(ctx);
1249
1250 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1251 ctx->load_mmrs = false;
1252 }
1253
1254 if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1255 sc->load_coeff_h) {
1256 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1257 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1258 &ctx->sc_coeff_h, 0);
1259
1260 sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1261 sc->load_coeff_h = false;
1262 }
1263
1264 if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1265 sc->load_coeff_v) {
1266 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1267 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1268 &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1269
1270 sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1271 sc->load_coeff_v = false;
1272 }
1273
1274 /* output data descriptors */
1275 if (ctx->deinterlacing)
1276 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1277
1278 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1279 add_out_dtd(ctx, VPE_PORT_RGB_OUT);
1280 } else {
1281 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1282 if (d_q_data->fmt->coplanar)
1283 add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1284 }
1285
1286 /* input data descriptors */
1287 if (ctx->deinterlacing) {
1288 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1289 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1290
1291 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1292 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1293 }
1294
1295 add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1296 add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1297
1298 if (ctx->deinterlacing)
1299 add_in_dtd(ctx, VPE_PORT_MV_IN);
1300
1301 /* sync on channel control descriptors for input ports */
1302 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1303 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1304
1305 if (ctx->deinterlacing) {
1306 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1307 VPE_CHAN_LUMA2_IN);
1308 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1309 VPE_CHAN_CHROMA2_IN);
1310
1311 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1312 VPE_CHAN_LUMA3_IN);
1313 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1314 VPE_CHAN_CHROMA3_IN);
1315
1316 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1317 }
1318
1319 /* sync on channel control descriptors for output ports */
1320 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1321 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1322 VPE_CHAN_RGB_OUT);
1323 } else {
1324 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1325 VPE_CHAN_LUMA_OUT);
1326 if (d_q_data->fmt->coplanar)
1327 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1328 VPE_CHAN_CHROMA_OUT);
1329 }
1330
1331 if (ctx->deinterlacing)
1332 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1333
1334 enable_irqs(ctx);
1335
1336 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1337 vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list, 0);
1338 }
1339
1340 static void dei_error(struct vpe_ctx *ctx)
1341 {
1342 dev_warn(ctx->dev->v4l2_dev.dev,
1343 "received DEI error interrupt\n");
1344 }
1345
1346 static void ds1_uv_error(struct vpe_ctx *ctx)
1347 {
1348 dev_warn(ctx->dev->v4l2_dev.dev,
1349 "received downsampler error interrupt\n");
1350 }
1351
1352 static irqreturn_t vpe_irq(int irq_vpe, void *data)
1353 {
1354 struct vpe_dev *dev = (struct vpe_dev *)data;
1355 struct vpe_ctx *ctx;
1356 struct vpe_q_data *d_q_data;
1357 struct vb2_v4l2_buffer *s_vb, *d_vb;
1358 unsigned long flags;
1359 u32 irqst0, irqst1;
1360 bool list_complete = false;
1361
1362 irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1363 if (irqst0) {
1364 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1365 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1366 }
1367
1368 irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1369 if (irqst1) {
1370 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1371 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1372 }
1373
1374 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1375 if (!ctx) {
1376 vpe_err(dev, "instance released before end of transaction\n");
1377 goto handled;
1378 }
1379
1380 if (irqst1) {
1381 if (irqst1 & VPE_DEI_ERROR_INT) {
1382 irqst1 &= ~VPE_DEI_ERROR_INT;
1383 dei_error(ctx);
1384 }
1385 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1386 irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1387 ds1_uv_error(ctx);
1388 }
1389 }
1390
1391 if (irqst0) {
1392 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1393 vpdma_clear_list_stat(ctx->dev->vpdma, 0, 0);
1394
1395 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1396 list_complete = true;
1397 }
1398
1399 if (irqst0 | irqst1) {
1400 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1401 irqst0, irqst1);
1402 }
1403
1404 /*
1405 * Setup next operation only when list complete IRQ occurs
1406 * otherwise, skip the following code
1407 */
1408 if (!list_complete)
1409 goto handled;
1410
1411 disable_irqs(ctx);
1412
1413 vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1414 vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1415 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1416 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
1417
1418 vpdma_reset_desc_list(&ctx->desc_list);
1419
1420 /* the previous dst mv buffer becomes the next src mv buffer */
1421 ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1422
1423 if (ctx->aborting)
1424 goto finished;
1425
1426 s_vb = ctx->src_vbs[0];
1427 d_vb = ctx->dst_vb;
1428
1429 d_vb->flags = s_vb->flags;
1430 d_vb->vb2_buf.timestamp = s_vb->vb2_buf.timestamp;
1431
1432 if (s_vb->flags & V4L2_BUF_FLAG_TIMECODE)
1433 d_vb->timecode = s_vb->timecode;
1434
1435 d_vb->sequence = ctx->sequence;
1436
1437 d_q_data = &ctx->q_data[Q_DATA_DST];
1438 if (d_q_data->flags & Q_IS_INTERLACED) {
1439 d_vb->field = ctx->field;
1440 if (ctx->field == V4L2_FIELD_BOTTOM) {
1441 ctx->sequence++;
1442 ctx->field = V4L2_FIELD_TOP;
1443 } else {
1444 WARN_ON(ctx->field != V4L2_FIELD_TOP);
1445 ctx->field = V4L2_FIELD_BOTTOM;
1446 }
1447 } else {
1448 d_vb->field = V4L2_FIELD_NONE;
1449 ctx->sequence++;
1450 }
1451
1452 if (ctx->deinterlacing) {
1453 /*
1454 * Allow source buffer to be dequeued only if it won't be used
1455 * in the next iteration. All vbs are initialized to first
1456 * buffer and we are shifting buffers every iteration, for the
1457 * first two iterations, no buffer will be dequeued.
1458 * This ensures that driver will keep (n-2)th (n-1)th and (n)th
1459 * field when deinterlacing is enabled
1460 */
1461 if (ctx->src_vbs[2] != ctx->src_vbs[1])
1462 s_vb = ctx->src_vbs[2];
1463 else
1464 s_vb = NULL;
1465 }
1466
1467 spin_lock_irqsave(&dev->lock, flags);
1468
1469 if (s_vb)
1470 v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1471
1472 v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1473
1474 spin_unlock_irqrestore(&dev->lock, flags);
1475
1476 if (ctx->deinterlacing) {
1477 ctx->src_vbs[2] = ctx->src_vbs[1];
1478 ctx->src_vbs[1] = ctx->src_vbs[0];
1479 }
1480
1481 /*
1482 * Since the vb2_buf_done has already been called fir therse
1483 * buffer we can now NULL them out so that we won't try
1484 * to clean out stray pointer later on.
1485 */
1486 ctx->src_vbs[0] = NULL;
1487 ctx->dst_vb = NULL;
1488
1489 ctx->bufs_completed++;
1490 if (ctx->bufs_completed < ctx->bufs_per_job && job_ready(ctx)) {
1491 device_run(ctx);
1492 goto handled;
1493 }
1494
1495 finished:
1496 vpe_dbg(ctx->dev, "finishing transaction\n");
1497 ctx->bufs_completed = 0;
1498 v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
1499 handled:
1500 return IRQ_HANDLED;
1501 }
1502
1503 /*
1504 * video ioctls
1505 */
1506 static int vpe_querycap(struct file *file, void *priv,
1507 struct v4l2_capability *cap)
1508 {
1509 strncpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver) - 1);
1510 strncpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card) - 1);
1511 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1512 VPE_MODULE_NAME);
1513 cap->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1514 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1515 return 0;
1516 }
1517
1518 static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1519 {
1520 int i, index;
1521 struct vpe_fmt *fmt = NULL;
1522
1523 index = 0;
1524 for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1525 if (vpe_formats[i].types & type) {
1526 if (index == f->index) {
1527 fmt = &vpe_formats[i];
1528 break;
1529 }
1530 index++;
1531 }
1532 }
1533
1534 if (!fmt)
1535 return -EINVAL;
1536
1537 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
1538 f->pixelformat = fmt->fourcc;
1539 return 0;
1540 }
1541
1542 static int vpe_enum_fmt(struct file *file, void *priv,
1543 struct v4l2_fmtdesc *f)
1544 {
1545 if (V4L2_TYPE_IS_OUTPUT(f->type))
1546 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1547
1548 return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1549 }
1550
1551 static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1552 {
1553 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1554 struct vpe_ctx *ctx = file2ctx(file);
1555 struct vb2_queue *vq;
1556 struct vpe_q_data *q_data;
1557 int i;
1558
1559 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1560 if (!vq)
1561 return -EINVAL;
1562
1563 q_data = get_q_data(ctx, f->type);
1564
1565 pix->width = q_data->width;
1566 pix->height = q_data->height;
1567 pix->pixelformat = q_data->fmt->fourcc;
1568 pix->field = q_data->field;
1569
1570 if (V4L2_TYPE_IS_OUTPUT(f->type)) {
1571 pix->colorspace = q_data->colorspace;
1572 } else {
1573 struct vpe_q_data *s_q_data;
1574
1575 /* get colorspace from the source queue */
1576 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1577
1578 pix->colorspace = s_q_data->colorspace;
1579 }
1580
1581 pix->num_planes = q_data->nplanes;
1582
1583 for (i = 0; i < pix->num_planes; i++) {
1584 pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
1585 pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
1586 }
1587
1588 return 0;
1589 }
1590
1591 static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1592 struct vpe_fmt *fmt, int type)
1593 {
1594 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1595 struct v4l2_plane_pix_format *plane_fmt;
1596 unsigned int w_align;
1597 int i, depth, depth_bytes, height;
1598
1599 if (!fmt || !(fmt->types & type)) {
1600 vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1601 pix->pixelformat);
1602 return -EINVAL;
1603 }
1604
1605 if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE
1606 && pix->field != V4L2_FIELD_SEQ_TB)
1607 pix->field = V4L2_FIELD_NONE;
1608
1609 depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1610
1611 /*
1612 * the line stride should 16 byte aligned for VPDMA to work, based on
1613 * the bytes per pixel, figure out how much the width should be aligned
1614 * to make sure line stride is 16 byte aligned
1615 */
1616 depth_bytes = depth >> 3;
1617
1618 if (depth_bytes == 3) {
1619 /*
1620 * if bpp is 3(as in some RGB formats), the pixel width doesn't
1621 * really help in ensuring line stride is 16 byte aligned
1622 */
1623 w_align = 4;
1624 } else {
1625 /*
1626 * for the remainder bpp(4, 2 and 1), the pixel width alignment
1627 * can ensure a line stride alignment of 16 bytes. For example,
1628 * if bpp is 2, then the line stride can be 16 byte aligned if
1629 * the width is 8 byte aligned
1630 */
1631
1632 /*
1633 * HACK: using order_base_2() here causes lots of asm output
1634 * errors with smatch, on i386:
1635 * ./arch/x86/include/asm/bitops.h:457:22:
1636 * warning: asm output is not an lvalue
1637 * Perhaps some gcc optimization is doing the wrong thing
1638 * there.
1639 * Let's get rid of them by doing the calculus on two steps
1640 */
1641 w_align = roundup_pow_of_two(VPDMA_DESC_ALIGN / depth_bytes);
1642 w_align = ilog2(w_align);
1643 }
1644
1645 v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
1646 &pix->height, MIN_H, MAX_H, H_ALIGN,
1647 S_ALIGN);
1648
1649 if (!pix->num_planes)
1650 pix->num_planes = fmt->coplanar ? 2 : 1;
1651 else if (pix->num_planes > 1 && !fmt->coplanar)
1652 pix->num_planes = 1;
1653
1654 pix->pixelformat = fmt->fourcc;
1655
1656 /*
1657 * For the actual image parameters, we need to consider the field
1658 * height of the image for SEQ_TB buffers.
1659 */
1660 if (pix->field == V4L2_FIELD_SEQ_TB)
1661 height = pix->height / 2;
1662 else
1663 height = pix->height;
1664
1665 if (!pix->colorspace) {
1666 if (fmt->fourcc == V4L2_PIX_FMT_RGB24 ||
1667 fmt->fourcc == V4L2_PIX_FMT_BGR24 ||
1668 fmt->fourcc == V4L2_PIX_FMT_RGB32 ||
1669 fmt->fourcc == V4L2_PIX_FMT_BGR32) {
1670 pix->colorspace = V4L2_COLORSPACE_SRGB;
1671 } else {
1672 if (height > 1280) /* HD */
1673 pix->colorspace = V4L2_COLORSPACE_REC709;
1674 else /* SD */
1675 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1676 }
1677 }
1678
1679 memset(pix->reserved, 0, sizeof(pix->reserved));
1680 for (i = 0; i < pix->num_planes; i++) {
1681 plane_fmt = &pix->plane_fmt[i];
1682 depth = fmt->vpdma_fmt[i]->depth;
1683
1684 if (i == VPE_LUMA)
1685 plane_fmt->bytesperline = (pix->width * depth) >> 3;
1686 else
1687 plane_fmt->bytesperline = pix->width;
1688
1689 if (pix->num_planes == 1 && fmt->coplanar)
1690 depth += fmt->vpdma_fmt[VPE_CHROMA]->depth;
1691 plane_fmt->sizeimage =
1692 (pix->height * pix->width * depth) >> 3;
1693
1694 memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
1695 }
1696
1697 return 0;
1698 }
1699
1700 static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1701 {
1702 struct vpe_ctx *ctx = file2ctx(file);
1703 struct vpe_fmt *fmt = find_format(f);
1704
1705 if (V4L2_TYPE_IS_OUTPUT(f->type))
1706 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1707 else
1708 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1709 }
1710
1711 static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1712 {
1713 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1714 struct v4l2_plane_pix_format *plane_fmt;
1715 struct vpe_q_data *q_data;
1716 struct vb2_queue *vq;
1717 int i;
1718
1719 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1720 if (!vq)
1721 return -EINVAL;
1722
1723 if (vb2_is_busy(vq)) {
1724 vpe_err(ctx->dev, "queue busy\n");
1725 return -EBUSY;
1726 }
1727
1728 q_data = get_q_data(ctx, f->type);
1729 if (!q_data)
1730 return -EINVAL;
1731
1732 q_data->fmt = find_format(f);
1733 q_data->width = pix->width;
1734 q_data->height = pix->height;
1735 q_data->colorspace = pix->colorspace;
1736 q_data->field = pix->field;
1737 q_data->nplanes = pix->num_planes;
1738
1739 for (i = 0; i < pix->num_planes; i++) {
1740 plane_fmt = &pix->plane_fmt[i];
1741
1742 q_data->bytesperline[i] = plane_fmt->bytesperline;
1743 q_data->sizeimage[i] = plane_fmt->sizeimage;
1744 }
1745
1746 q_data->c_rect.left = 0;
1747 q_data->c_rect.top = 0;
1748 q_data->c_rect.width = q_data->width;
1749 q_data->c_rect.height = q_data->height;
1750
1751 if (q_data->field == V4L2_FIELD_ALTERNATE)
1752 q_data->flags |= Q_DATA_INTERLACED_ALTERNATE;
1753 else if (q_data->field == V4L2_FIELD_SEQ_TB)
1754 q_data->flags |= Q_DATA_INTERLACED_SEQ_TB;
1755 else
1756 q_data->flags &= ~Q_IS_INTERLACED;
1757
1758 /* the crop height is halved for the case of SEQ_TB buffers */
1759 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1760 q_data->c_rect.height /= 2;
1761
1762 vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1763 f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
1764 q_data->bytesperline[VPE_LUMA]);
1765 if (q_data->nplanes == 2)
1766 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1767 q_data->bytesperline[VPE_CHROMA]);
1768
1769 return 0;
1770 }
1771
1772 static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1773 {
1774 int ret;
1775 struct vpe_ctx *ctx = file2ctx(file);
1776
1777 ret = vpe_try_fmt(file, priv, f);
1778 if (ret)
1779 return ret;
1780
1781 ret = __vpe_s_fmt(ctx, f);
1782 if (ret)
1783 return ret;
1784
1785 if (V4L2_TYPE_IS_OUTPUT(f->type))
1786 set_src_registers(ctx);
1787 else
1788 set_dst_registers(ctx);
1789
1790 return set_srcdst_params(ctx);
1791 }
1792
1793 static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s)
1794 {
1795 struct vpe_q_data *q_data;
1796 int height;
1797
1798 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1799 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1800 return -EINVAL;
1801
1802 q_data = get_q_data(ctx, s->type);
1803 if (!q_data)
1804 return -EINVAL;
1805
1806 switch (s->target) {
1807 case V4L2_SEL_TGT_COMPOSE:
1808 /*
1809 * COMPOSE target is only valid for capture buffer type, return
1810 * error for output buffer type
1811 */
1812 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1813 return -EINVAL;
1814 break;
1815 case V4L2_SEL_TGT_CROP:
1816 /*
1817 * CROP target is only valid for output buffer type, return
1818 * error for capture buffer type
1819 */
1820 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1821 return -EINVAL;
1822 break;
1823 /*
1824 * bound and default crop/compose targets are invalid targets to
1825 * try/set
1826 */
1827 default:
1828 return -EINVAL;
1829 }
1830
1831 /*
1832 * For SEQ_TB buffers, crop height should be less than the height of
1833 * the field height, not the buffer height
1834 */
1835 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1836 height = q_data->height / 2;
1837 else
1838 height = q_data->height;
1839
1840 if (s->r.top < 0 || s->r.left < 0) {
1841 vpe_err(ctx->dev, "negative values for top and left\n");
1842 s->r.top = s->r.left = 0;
1843 }
1844
1845 v4l_bound_align_image(&s->r.width, MIN_W, q_data->width, 1,
1846 &s->r.height, MIN_H, height, H_ALIGN, S_ALIGN);
1847
1848 /* adjust left/top if cropping rectangle is out of bounds */
1849 if (s->r.left + s->r.width > q_data->width)
1850 s->r.left = q_data->width - s->r.width;
1851 if (s->r.top + s->r.height > q_data->height)
1852 s->r.top = q_data->height - s->r.height;
1853
1854 return 0;
1855 }
1856
1857 static int vpe_g_selection(struct file *file, void *fh,
1858 struct v4l2_selection *s)
1859 {
1860 struct vpe_ctx *ctx = file2ctx(file);
1861 struct vpe_q_data *q_data;
1862 bool use_c_rect = false;
1863
1864 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1865 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1866 return -EINVAL;
1867
1868 q_data = get_q_data(ctx, s->type);
1869 if (!q_data)
1870 return -EINVAL;
1871
1872 switch (s->target) {
1873 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1874 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1875 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1876 return -EINVAL;
1877 break;
1878 case V4L2_SEL_TGT_CROP_BOUNDS:
1879 case V4L2_SEL_TGT_CROP_DEFAULT:
1880 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1881 return -EINVAL;
1882 break;
1883 case V4L2_SEL_TGT_COMPOSE:
1884 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1885 return -EINVAL;
1886 use_c_rect = true;
1887 break;
1888 case V4L2_SEL_TGT_CROP:
1889 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1890 return -EINVAL;
1891 use_c_rect = true;
1892 break;
1893 default:
1894 return -EINVAL;
1895 }
1896
1897 if (use_c_rect) {
1898 /*
1899 * for CROP/COMPOSE target type, return c_rect params from the
1900 * respective buffer type
1901 */
1902 s->r = q_data->c_rect;
1903 } else {
1904 /*
1905 * for DEFAULT/BOUNDS target type, return width and height from
1906 * S_FMT of the respective buffer type
1907 */
1908 s->r.left = 0;
1909 s->r.top = 0;
1910 s->r.width = q_data->width;
1911 s->r.height = q_data->height;
1912 }
1913
1914 return 0;
1915 }
1916
1917
1918 static int vpe_s_selection(struct file *file, void *fh,
1919 struct v4l2_selection *s)
1920 {
1921 struct vpe_ctx *ctx = file2ctx(file);
1922 struct vpe_q_data *q_data;
1923 struct v4l2_selection sel = *s;
1924 int ret;
1925
1926 ret = __vpe_try_selection(ctx, &sel);
1927 if (ret)
1928 return ret;
1929
1930 q_data = get_q_data(ctx, sel.type);
1931 if (!q_data)
1932 return -EINVAL;
1933
1934 if ((q_data->c_rect.left == sel.r.left) &&
1935 (q_data->c_rect.top == sel.r.top) &&
1936 (q_data->c_rect.width == sel.r.width) &&
1937 (q_data->c_rect.height == sel.r.height)) {
1938 vpe_dbg(ctx->dev,
1939 "requested crop/compose values are already set\n");
1940 return 0;
1941 }
1942
1943 q_data->c_rect = sel.r;
1944
1945 return set_srcdst_params(ctx);
1946 }
1947
1948 /*
1949 * defines number of buffers/frames a context can process with VPE before
1950 * switching to a different context. default value is 1 buffer per context
1951 */
1952 #define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
1953
1954 static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1955 {
1956 struct vpe_ctx *ctx =
1957 container_of(ctrl->handler, struct vpe_ctx, hdl);
1958
1959 switch (ctrl->id) {
1960 case V4L2_CID_VPE_BUFS_PER_JOB:
1961 ctx->bufs_per_job = ctrl->val;
1962 break;
1963
1964 default:
1965 vpe_err(ctx->dev, "Invalid control\n");
1966 return -EINVAL;
1967 }
1968
1969 return 0;
1970 }
1971
1972 static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1973 .s_ctrl = vpe_s_ctrl,
1974 };
1975
1976 static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1977 .vidioc_querycap = vpe_querycap,
1978
1979 .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt,
1980 .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt,
1981 .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt,
1982 .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt,
1983
1984 .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt,
1985 .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt,
1986 .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt,
1987 .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt,
1988
1989 .vidioc_g_selection = vpe_g_selection,
1990 .vidioc_s_selection = vpe_s_selection,
1991
1992 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
1993 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
1994 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
1995 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
1996 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
1997 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
1998 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
1999
2000 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
2001 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
2002 };
2003
2004 /*
2005 * Queue operations
2006 */
2007 static int vpe_queue_setup(struct vb2_queue *vq,
2008 unsigned int *nbuffers, unsigned int *nplanes,
2009 unsigned int sizes[], struct device *alloc_devs[])
2010 {
2011 int i;
2012 struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
2013 struct vpe_q_data *q_data;
2014
2015 q_data = get_q_data(ctx, vq->type);
2016
2017 *nplanes = q_data->nplanes;
2018
2019 for (i = 0; i < *nplanes; i++)
2020 sizes[i] = q_data->sizeimage[i];
2021
2022 vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
2023 sizes[VPE_LUMA]);
2024 if (q_data->nplanes == 2)
2025 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
2026
2027 return 0;
2028 }
2029
2030 static int vpe_buf_prepare(struct vb2_buffer *vb)
2031 {
2032 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2033 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2034 struct vpe_q_data *q_data;
2035 int i, num_planes;
2036
2037 vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
2038
2039 q_data = get_q_data(ctx, vb->vb2_queue->type);
2040 num_planes = q_data->nplanes;
2041
2042 if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
2043 if (!(q_data->flags & Q_IS_INTERLACED)) {
2044 vbuf->field = V4L2_FIELD_NONE;
2045 } else {
2046 if (vbuf->field != V4L2_FIELD_TOP &&
2047 vbuf->field != V4L2_FIELD_BOTTOM &&
2048 vbuf->field != V4L2_FIELD_SEQ_TB)
2049 return -EINVAL;
2050 }
2051 }
2052
2053 for (i = 0; i < num_planes; i++) {
2054 if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
2055 vpe_err(ctx->dev,
2056 "data will not fit into plane (%lu < %lu)\n",
2057 vb2_plane_size(vb, i),
2058 (long) q_data->sizeimage[i]);
2059 return -EINVAL;
2060 }
2061 }
2062
2063 for (i = 0; i < num_planes; i++)
2064 vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
2065
2066 return 0;
2067 }
2068
2069 static void vpe_buf_queue(struct vb2_buffer *vb)
2070 {
2071 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2072 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2073
2074 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
2075 }
2076
2077 static int check_srcdst_sizes(struct vpe_ctx *ctx)
2078 {
2079 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
2080 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
2081 unsigned int src_w = s_q_data->c_rect.width;
2082 unsigned int src_h = s_q_data->c_rect.height;
2083 unsigned int dst_w = d_q_data->c_rect.width;
2084 unsigned int dst_h = d_q_data->c_rect.height;
2085
2086 if (src_w == dst_w && src_h == dst_h)
2087 return 0;
2088
2089 if (src_h <= SC_MAX_PIXEL_HEIGHT &&
2090 src_w <= SC_MAX_PIXEL_WIDTH &&
2091 dst_h <= SC_MAX_PIXEL_HEIGHT &&
2092 dst_w <= SC_MAX_PIXEL_WIDTH)
2093 return 0;
2094
2095 return -1;
2096 }
2097
2098 static void vpe_return_all_buffers(struct vpe_ctx *ctx, struct vb2_queue *q,
2099 enum vb2_buffer_state state)
2100 {
2101 struct vb2_v4l2_buffer *vb;
2102 unsigned long flags;
2103
2104 for (;;) {
2105 if (V4L2_TYPE_IS_OUTPUT(q->type))
2106 vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
2107 else
2108 vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2109 if (!vb)
2110 break;
2111 spin_lock_irqsave(&ctx->dev->lock, flags);
2112 v4l2_m2m_buf_done(vb, state);
2113 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2114 }
2115
2116 /*
2117 * Cleanup the in-transit vb2 buffers that have been
2118 * removed from their respective queue already but for
2119 * which procecessing has not been completed yet.
2120 */
2121 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2122 spin_lock_irqsave(&ctx->dev->lock, flags);
2123
2124 if (ctx->src_vbs[2])
2125 v4l2_m2m_buf_done(ctx->src_vbs[2], state);
2126
2127 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
2128 v4l2_m2m_buf_done(ctx->src_vbs[1], state);
2129
2130 if (ctx->src_vbs[0] &&
2131 (ctx->src_vbs[0] != ctx->src_vbs[1]) &&
2132 (ctx->src_vbs[0] != ctx->src_vbs[2]))
2133 v4l2_m2m_buf_done(ctx->src_vbs[0], state);
2134
2135 ctx->src_vbs[2] = NULL;
2136 ctx->src_vbs[1] = NULL;
2137 ctx->src_vbs[0] = NULL;
2138
2139 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2140 } else {
2141 if (ctx->dst_vb) {
2142 spin_lock_irqsave(&ctx->dev->lock, flags);
2143
2144 v4l2_m2m_buf_done(ctx->dst_vb, state);
2145 ctx->dst_vb = NULL;
2146 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2147 }
2148 }
2149 }
2150
2151 static int vpe_start_streaming(struct vb2_queue *q, unsigned int count)
2152 {
2153 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2154
2155 /* Check any of the size exceed maximum scaling sizes */
2156 if (check_srcdst_sizes(ctx)) {
2157 vpe_err(ctx->dev,
2158 "Conversion setup failed, check source and destination parameters\n"
2159 );
2160 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_QUEUED);
2161 return -EINVAL;
2162 }
2163
2164 if (ctx->deinterlacing)
2165 config_edi_input_mode(ctx, 0x0);
2166
2167 if (ctx->sequence != 0)
2168 set_srcdst_params(ctx);
2169
2170 return 0;
2171 }
2172
2173 static void vpe_stop_streaming(struct vb2_queue *q)
2174 {
2175 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2176
2177 vpe_dump_regs(ctx->dev);
2178 vpdma_dump_regs(ctx->dev->vpdma);
2179
2180 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_ERROR);
2181 }
2182
2183 static const struct vb2_ops vpe_qops = {
2184 .queue_setup = vpe_queue_setup,
2185 .buf_prepare = vpe_buf_prepare,
2186 .buf_queue = vpe_buf_queue,
2187 .wait_prepare = vb2_ops_wait_prepare,
2188 .wait_finish = vb2_ops_wait_finish,
2189 .start_streaming = vpe_start_streaming,
2190 .stop_streaming = vpe_stop_streaming,
2191 };
2192
2193 static int queue_init(void *priv, struct vb2_queue *src_vq,
2194 struct vb2_queue *dst_vq)
2195 {
2196 struct vpe_ctx *ctx = priv;
2197 struct vpe_dev *dev = ctx->dev;
2198 int ret;
2199
2200 memset(src_vq, 0, sizeof(*src_vq));
2201 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2202 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2203 src_vq->drv_priv = ctx;
2204 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2205 src_vq->ops = &vpe_qops;
2206 src_vq->mem_ops = &vb2_dma_contig_memops;
2207 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2208 src_vq->lock = &dev->dev_mutex;
2209 src_vq->dev = dev->v4l2_dev.dev;
2210
2211 ret = vb2_queue_init(src_vq);
2212 if (ret)
2213 return ret;
2214
2215 memset(dst_vq, 0, sizeof(*dst_vq));
2216 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2217 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2218 dst_vq->drv_priv = ctx;
2219 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2220 dst_vq->ops = &vpe_qops;
2221 dst_vq->mem_ops = &vb2_dma_contig_memops;
2222 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2223 dst_vq->lock = &dev->dev_mutex;
2224 dst_vq->dev = dev->v4l2_dev.dev;
2225
2226 return vb2_queue_init(dst_vq);
2227 }
2228
2229 static const struct v4l2_ctrl_config vpe_bufs_per_job = {
2230 .ops = &vpe_ctrl_ops,
2231 .id = V4L2_CID_VPE_BUFS_PER_JOB,
2232 .name = "Buffers Per Transaction",
2233 .type = V4L2_CTRL_TYPE_INTEGER,
2234 .def = VPE_DEF_BUFS_PER_JOB,
2235 .min = 1,
2236 .max = VIDEO_MAX_FRAME,
2237 .step = 1,
2238 };
2239
2240 /*
2241 * File operations
2242 */
2243 static int vpe_open(struct file *file)
2244 {
2245 struct vpe_dev *dev = video_drvdata(file);
2246 struct vpe_q_data *s_q_data;
2247 struct v4l2_ctrl_handler *hdl;
2248 struct vpe_ctx *ctx;
2249 int ret;
2250
2251 vpe_dbg(dev, "vpe_open\n");
2252
2253 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2254 if (!ctx)
2255 return -ENOMEM;
2256
2257 ctx->dev = dev;
2258
2259 if (mutex_lock_interruptible(&dev->dev_mutex)) {
2260 ret = -ERESTARTSYS;
2261 goto free_ctx;
2262 }
2263
2264 ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
2265 VPDMA_LIST_TYPE_NORMAL);
2266 if (ret != 0)
2267 goto unlock;
2268
2269 ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
2270 if (ret != 0)
2271 goto free_desc_list;
2272
2273 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
2274 if (ret != 0)
2275 goto free_mmr_adb;
2276
2277 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
2278 if (ret != 0)
2279 goto free_sc_h;
2280
2281 init_adb_hdrs(ctx);
2282
2283 v4l2_fh_init(&ctx->fh, video_devdata(file));
2284 file->private_data = &ctx->fh;
2285
2286 hdl = &ctx->hdl;
2287 v4l2_ctrl_handler_init(hdl, 1);
2288 v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
2289 if (hdl->error) {
2290 ret = hdl->error;
2291 goto exit_fh;
2292 }
2293 ctx->fh.ctrl_handler = hdl;
2294 v4l2_ctrl_handler_setup(hdl);
2295
2296 s_q_data = &ctx->q_data[Q_DATA_SRC];
2297 s_q_data->fmt = &vpe_formats[2];
2298 s_q_data->width = 1920;
2299 s_q_data->height = 1080;
2300 s_q_data->nplanes = 1;
2301 s_q_data->bytesperline[VPE_LUMA] = (s_q_data->width *
2302 s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
2303 s_q_data->sizeimage[VPE_LUMA] = (s_q_data->bytesperline[VPE_LUMA] *
2304 s_q_data->height);
2305 s_q_data->colorspace = V4L2_COLORSPACE_REC709;
2306 s_q_data->field = V4L2_FIELD_NONE;
2307 s_q_data->c_rect.left = 0;
2308 s_q_data->c_rect.top = 0;
2309 s_q_data->c_rect.width = s_q_data->width;
2310 s_q_data->c_rect.height = s_q_data->height;
2311 s_q_data->flags = 0;
2312
2313 ctx->q_data[Q_DATA_DST] = *s_q_data;
2314
2315 set_dei_shadow_registers(ctx);
2316 set_src_registers(ctx);
2317 set_dst_registers(ctx);
2318 ret = set_srcdst_params(ctx);
2319 if (ret)
2320 goto exit_fh;
2321
2322 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
2323
2324 if (IS_ERR(ctx->fh.m2m_ctx)) {
2325 ret = PTR_ERR(ctx->fh.m2m_ctx);
2326 goto exit_fh;
2327 }
2328
2329 v4l2_fh_add(&ctx->fh);
2330
2331 /*
2332 * for now, just report the creation of the first instance, we can later
2333 * optimize the driver to enable or disable clocks when the first
2334 * instance is created or the last instance released
2335 */
2336 if (atomic_inc_return(&dev->num_instances) == 1)
2337 vpe_dbg(dev, "first instance created\n");
2338
2339 ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
2340
2341 ctx->load_mmrs = true;
2342
2343 vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
2344 ctx, ctx->fh.m2m_ctx);
2345
2346 mutex_unlock(&dev->dev_mutex);
2347
2348 return 0;
2349 exit_fh:
2350 v4l2_ctrl_handler_free(hdl);
2351 v4l2_fh_exit(&ctx->fh);
2352 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2353 free_sc_h:
2354 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2355 free_mmr_adb:
2356 vpdma_free_desc_buf(&ctx->mmr_adb);
2357 free_desc_list:
2358 vpdma_free_desc_list(&ctx->desc_list);
2359 unlock:
2360 mutex_unlock(&dev->dev_mutex);
2361 free_ctx:
2362 kfree(ctx);
2363 return ret;
2364 }
2365
2366 static int vpe_release(struct file *file)
2367 {
2368 struct vpe_dev *dev = video_drvdata(file);
2369 struct vpe_ctx *ctx = file2ctx(file);
2370
2371 vpe_dbg(dev, "releasing instance %p\n", ctx);
2372
2373 mutex_lock(&dev->dev_mutex);
2374 free_mv_buffers(ctx);
2375 vpdma_free_desc_list(&ctx->desc_list);
2376 vpdma_free_desc_buf(&ctx->mmr_adb);
2377
2378 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2379 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2380
2381 v4l2_fh_del(&ctx->fh);
2382 v4l2_fh_exit(&ctx->fh);
2383 v4l2_ctrl_handler_free(&ctx->hdl);
2384 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2385
2386 kfree(ctx);
2387
2388 /*
2389 * for now, just report the release of the last instance, we can later
2390 * optimize the driver to enable or disable clocks when the first
2391 * instance is created or the last instance released
2392 */
2393 if (atomic_dec_return(&dev->num_instances) == 0)
2394 vpe_dbg(dev, "last instance released\n");
2395
2396 mutex_unlock(&dev->dev_mutex);
2397
2398 return 0;
2399 }
2400
2401 static const struct v4l2_file_operations vpe_fops = {
2402 .owner = THIS_MODULE,
2403 .open = vpe_open,
2404 .release = vpe_release,
2405 .poll = v4l2_m2m_fop_poll,
2406 .unlocked_ioctl = video_ioctl2,
2407 .mmap = v4l2_m2m_fop_mmap,
2408 };
2409
2410 static struct video_device vpe_videodev = {
2411 .name = VPE_MODULE_NAME,
2412 .fops = &vpe_fops,
2413 .ioctl_ops = &vpe_ioctl_ops,
2414 .minor = -1,
2415 .release = video_device_release_empty,
2416 .vfl_dir = VFL_DIR_M2M,
2417 };
2418
2419 static struct v4l2_m2m_ops m2m_ops = {
2420 .device_run = device_run,
2421 .job_ready = job_ready,
2422 .job_abort = job_abort,
2423 .lock = vpe_lock,
2424 .unlock = vpe_unlock,
2425 };
2426
2427 static int vpe_runtime_get(struct platform_device *pdev)
2428 {
2429 int r;
2430
2431 dev_dbg(&pdev->dev, "vpe_runtime_get\n");
2432
2433 r = pm_runtime_get_sync(&pdev->dev);
2434 WARN_ON(r < 0);
2435 return r < 0 ? r : 0;
2436 }
2437
2438 static void vpe_runtime_put(struct platform_device *pdev)
2439 {
2440
2441 int r;
2442
2443 dev_dbg(&pdev->dev, "vpe_runtime_put\n");
2444
2445 r = pm_runtime_put_sync(&pdev->dev);
2446 WARN_ON(r < 0 && r != -ENOSYS);
2447 }
2448
2449 static void vpe_fw_cb(struct platform_device *pdev)
2450 {
2451 struct vpe_dev *dev = platform_get_drvdata(pdev);
2452 struct video_device *vfd;
2453 int ret;
2454
2455 vfd = &dev->vfd;
2456 *vfd = vpe_videodev;
2457 vfd->lock = &dev->dev_mutex;
2458 vfd->v4l2_dev = &dev->v4l2_dev;
2459
2460 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2461 if (ret) {
2462 vpe_err(dev, "Failed to register video device\n");
2463
2464 vpe_set_clock_enable(dev, 0);
2465 vpe_runtime_put(pdev);
2466 pm_runtime_disable(&pdev->dev);
2467 v4l2_m2m_release(dev->m2m_dev);
2468 v4l2_device_unregister(&dev->v4l2_dev);
2469
2470 return;
2471 }
2472
2473 video_set_drvdata(vfd, dev);
2474 snprintf(vfd->name, sizeof(vfd->name), "%s", vpe_videodev.name);
2475 dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2476 vfd->num);
2477 }
2478
2479 static int vpe_probe(struct platform_device *pdev)
2480 {
2481 struct vpe_dev *dev;
2482 int ret, irq, func;
2483
2484 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2485 if (!dev)
2486 return -ENOMEM;
2487
2488 spin_lock_init(&dev->lock);
2489
2490 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2491 if (ret)
2492 return ret;
2493
2494 atomic_set(&dev->num_instances, 0);
2495 mutex_init(&dev->dev_mutex);
2496
2497 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2498 "vpe_top");
2499 /*
2500 * HACK: we get resource info from device tree in the form of a list of
2501 * VPE sub blocks, the driver currently uses only the base of vpe_top
2502 * for register access, the driver should be changed later to access
2503 * registers based on the sub block base addresses
2504 */
2505 dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
2506 if (!dev->base) {
2507 ret = -ENOMEM;
2508 goto v4l2_dev_unreg;
2509 }
2510
2511 irq = platform_get_irq(pdev, 0);
2512 ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2513 dev);
2514 if (ret)
2515 goto v4l2_dev_unreg;
2516
2517 platform_set_drvdata(pdev, dev);
2518
2519 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2520 if (IS_ERR(dev->m2m_dev)) {
2521 vpe_err(dev, "Failed to init mem2mem device\n");
2522 ret = PTR_ERR(dev->m2m_dev);
2523 goto v4l2_dev_unreg;
2524 }
2525
2526 pm_runtime_enable(&pdev->dev);
2527
2528 ret = vpe_runtime_get(pdev);
2529 if (ret)
2530 goto rel_m2m;
2531
2532 /* Perform clk enable followed by reset */
2533 vpe_set_clock_enable(dev, 1);
2534
2535 vpe_top_reset(dev);
2536
2537 func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2538 VPE_PID_FUNC_SHIFT);
2539 vpe_dbg(dev, "VPE PID function %x\n", func);
2540
2541 vpe_top_vpdma_reset(dev);
2542
2543 dev->sc = sc_create(pdev, "sc");
2544 if (IS_ERR(dev->sc)) {
2545 ret = PTR_ERR(dev->sc);
2546 goto runtime_put;
2547 }
2548
2549 dev->csc = csc_create(pdev, "csc");
2550 if (IS_ERR(dev->csc)) {
2551 ret = PTR_ERR(dev->csc);
2552 goto runtime_put;
2553 }
2554
2555 dev->vpdma = &dev->vpdma_data;
2556 ret = vpdma_create(pdev, dev->vpdma, vpe_fw_cb);
2557 if (ret)
2558 goto runtime_put;
2559
2560 return 0;
2561
2562 runtime_put:
2563 vpe_runtime_put(pdev);
2564 rel_m2m:
2565 pm_runtime_disable(&pdev->dev);
2566 v4l2_m2m_release(dev->m2m_dev);
2567 v4l2_dev_unreg:
2568 v4l2_device_unregister(&dev->v4l2_dev);
2569
2570 return ret;
2571 }
2572
2573 static int vpe_remove(struct platform_device *pdev)
2574 {
2575 struct vpe_dev *dev = platform_get_drvdata(pdev);
2576
2577 v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2578
2579 v4l2_m2m_release(dev->m2m_dev);
2580 video_unregister_device(&dev->vfd);
2581 v4l2_device_unregister(&dev->v4l2_dev);
2582
2583 vpe_set_clock_enable(dev, 0);
2584 vpe_runtime_put(pdev);
2585 pm_runtime_disable(&pdev->dev);
2586
2587 return 0;
2588 }
2589
2590 #if defined(CONFIG_OF)
2591 static const struct of_device_id vpe_of_match[] = {
2592 {
2593 .compatible = "ti,vpe",
2594 },
2595 {},
2596 };
2597 MODULE_DEVICE_TABLE(of, vpe_of_match);
2598 #endif
2599
2600 static struct platform_driver vpe_pdrv = {
2601 .probe = vpe_probe,
2602 .remove = vpe_remove,
2603 .driver = {
2604 .name = VPE_MODULE_NAME,
2605 .of_match_table = of_match_ptr(vpe_of_match),
2606 },
2607 };
2608
2609 module_platform_driver(vpe_pdrv);
2610
2611 MODULE_DESCRIPTION("TI VPE driver");
2612 MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2613 MODULE_LICENSE("GPL");
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