2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/blkdev.h>
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/err.h>
20 #include <linux/init.h>
21 #include <linux/interrupt.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/seq_file.h>
28 #include <linux/slab.h>
29 #include <linux/stat.h>
30 #include <linux/delay.h>
31 #include <linux/irq.h>
32 #include <linux/mmc/card.h>
33 #include <linux/mmc/host.h>
34 #include <linux/mmc/mmc.h>
35 #include <linux/mmc/sd.h>
36 #include <linux/mmc/sdio.h>
37 #include <linux/bitops.h>
38 #include <linux/regulator/consumer.h>
40 #include <linux/of_gpio.h>
41 #include <linux/mmc/slot-gpio.h>
45 /* Common flag combinations */
46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
48 SDMMC_INT_EBE | SDMMC_INT_HLE)
49 #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
51 #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
52 DW_MCI_CMD_ERROR_FLAGS)
53 #define DW_MCI_SEND_STATUS 1
54 #define DW_MCI_RECV_STATUS 2
55 #define DW_MCI_DMA_THRESHOLD 16
57 #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
58 #define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
60 #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
65 #define DESC_RING_BUF_SZ PAGE_SIZE
67 struct idmac_desc_64addr
{
68 u32 des0
; /* Control Descriptor */
69 #define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
72 u32 des1
; /* Reserved */
74 u32 des2
; /*Buffer sizes */
75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
79 u32 des3
; /* Reserved */
81 u32 des4
; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5
; /* Upper 32-bits of Buffer Address Pointer 1*/
84 u32 des6
; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7
; /* Upper 32-bits of Next Descriptor Address */
89 __le32 des0
; /* Control Descriptor */
90 #define IDMAC_DES0_DIC BIT(1)
91 #define IDMAC_DES0_LD BIT(2)
92 #define IDMAC_DES0_FD BIT(3)
93 #define IDMAC_DES0_CH BIT(4)
94 #define IDMAC_DES0_ER BIT(5)
95 #define IDMAC_DES0_CES BIT(30)
96 #define IDMAC_DES0_OWN BIT(31)
98 __le32 des1
; /* Buffer sizes */
99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
102 __le32 des2
; /* buffer 1 physical address */
104 __le32 des3
; /* buffer 2 physical address */
107 /* Each descriptor can transfer up to 4KB of data in chained mode */
108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
110 #if defined(CONFIG_DEBUG_FS)
111 static int dw_mci_req_show(struct seq_file
*s
, void *v
)
113 struct dw_mci_slot
*slot
= s
->private;
114 struct mmc_request
*mrq
;
115 struct mmc_command
*cmd
;
116 struct mmc_command
*stop
;
117 struct mmc_data
*data
;
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot
->host
->lock
);
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd
->opcode
, cmd
->arg
, cmd
->flags
,
132 cmd
->resp
[0], cmd
->resp
[1], cmd
->resp
[2],
133 cmd
->resp
[2], cmd
->error
);
135 seq_printf(s
, "DATA %u / %u * %u flg %x err %d\n",
136 data
->bytes_xfered
, data
->blocks
,
137 data
->blksz
, data
->flags
, data
->error
);
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop
->opcode
, stop
->arg
, stop
->flags
,
142 stop
->resp
[0], stop
->resp
[1], stop
->resp
[2],
143 stop
->resp
[2], stop
->error
);
146 spin_unlock_bh(&slot
->host
->lock
);
151 static int dw_mci_req_open(struct inode
*inode
, struct file
*file
)
153 return single_open(file
, dw_mci_req_show
, inode
->i_private
);
156 static const struct file_operations dw_mci_req_fops
= {
157 .owner
= THIS_MODULE
,
158 .open
= dw_mci_req_open
,
161 .release
= single_release
,
164 static int dw_mci_regs_show(struct seq_file
*s
, void *v
)
166 struct dw_mci
*host
= s
->private;
168 seq_printf(s
, "STATUS:\t0x%08x\n", mci_readl(host
, STATUS
));
169 seq_printf(s
, "RINTSTS:\t0x%08x\n", mci_readl(host
, RINTSTS
));
170 seq_printf(s
, "CMD:\t0x%08x\n", mci_readl(host
, CMD
));
171 seq_printf(s
, "CTRL:\t0x%08x\n", mci_readl(host
, CTRL
));
172 seq_printf(s
, "INTMASK:\t0x%08x\n", mci_readl(host
, INTMASK
));
173 seq_printf(s
, "CLKENA:\t0x%08x\n", mci_readl(host
, CLKENA
));
178 static int dw_mci_regs_open(struct inode
*inode
, struct file
*file
)
180 return single_open(file
, dw_mci_regs_show
, inode
->i_private
);
183 static const struct file_operations dw_mci_regs_fops
= {
184 .owner
= THIS_MODULE
,
185 .open
= dw_mci_regs_open
,
188 .release
= single_release
,
191 static void dw_mci_init_debugfs(struct dw_mci_slot
*slot
)
193 struct mmc_host
*mmc
= slot
->mmc
;
194 struct dw_mci
*host
= slot
->host
;
198 root
= mmc
->debugfs_root
;
202 node
= debugfs_create_file("regs", S_IRUSR
, root
, host
,
207 node
= debugfs_create_file("req", S_IRUSR
, root
, slot
,
212 node
= debugfs_create_u32("state", S_IRUSR
, root
, (u32
*)&host
->state
);
216 node
= debugfs_create_x32("pending_events", S_IRUSR
, root
,
217 (u32
*)&host
->pending_events
);
221 node
= debugfs_create_x32("completed_events", S_IRUSR
, root
,
222 (u32
*)&host
->completed_events
);
229 dev_err(&mmc
->class_dev
, "failed to initialize debugfs for slot\n");
231 #endif /* defined(CONFIG_DEBUG_FS) */
233 static bool dw_mci_ctrl_reset(struct dw_mci
*host
, u32 reset
)
237 ctrl
= mci_readl(host
, CTRL
);
239 mci_writel(host
, CTRL
, ctrl
);
241 /* wait till resets clear */
242 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_CTRL
, ctrl
,
244 1, 500 * USEC_PER_MSEC
)) {
246 "Timeout resetting block (ctrl reset %#x)\n",
254 static void dw_mci_wait_while_busy(struct dw_mci
*host
, u32 cmd_flags
)
259 * Databook says that before issuing a new data transfer command
260 * we need to check to see if the card is busy. Data transfer commands
261 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
263 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
266 if ((cmd_flags
& SDMMC_CMD_PRV_DAT_WAIT
) &&
267 !(cmd_flags
& SDMMC_CMD_VOLT_SWITCH
)) {
268 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_STATUS
,
270 !(status
& SDMMC_STATUS_BUSY
),
271 10, 500 * USEC_PER_MSEC
))
272 dev_err(host
->dev
, "Busy; trying anyway\n");
276 static void mci_send_cmd(struct dw_mci_slot
*slot
, u32 cmd
, u32 arg
)
278 struct dw_mci
*host
= slot
->host
;
279 unsigned int cmd_status
= 0;
281 mci_writel(host
, CMDARG
, arg
);
282 wmb(); /* drain writebuffer */
283 dw_mci_wait_while_busy(host
, cmd
);
284 mci_writel(host
, CMD
, SDMMC_CMD_START
| cmd
);
286 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_CMD
, cmd_status
,
287 !(cmd_status
& SDMMC_CMD_START
),
288 1, 500 * USEC_PER_MSEC
))
289 dev_err(&slot
->mmc
->class_dev
,
290 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
291 cmd
, arg
, cmd_status
);
294 static u32
dw_mci_prepare_command(struct mmc_host
*mmc
, struct mmc_command
*cmd
)
296 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
297 struct dw_mci
*host
= slot
->host
;
300 cmd
->error
= -EINPROGRESS
;
303 if (cmd
->opcode
== MMC_STOP_TRANSMISSION
||
304 cmd
->opcode
== MMC_GO_IDLE_STATE
||
305 cmd
->opcode
== MMC_GO_INACTIVE_STATE
||
306 (cmd
->opcode
== SD_IO_RW_DIRECT
&&
307 ((cmd
->arg
>> 9) & 0x1FFFF) == SDIO_CCCR_ABORT
))
308 cmdr
|= SDMMC_CMD_STOP
;
309 else if (cmd
->opcode
!= MMC_SEND_STATUS
&& cmd
->data
)
310 cmdr
|= SDMMC_CMD_PRV_DAT_WAIT
;
312 if (cmd
->opcode
== SD_SWITCH_VOLTAGE
) {
315 /* Special bit makes CMD11 not die */
316 cmdr
|= SDMMC_CMD_VOLT_SWITCH
;
318 /* Change state to continue to handle CMD11 weirdness */
319 WARN_ON(slot
->host
->state
!= STATE_SENDING_CMD
);
320 slot
->host
->state
= STATE_SENDING_CMD11
;
323 * We need to disable low power mode (automatic clock stop)
324 * while doing voltage switch so we don't confuse the card,
325 * since stopping the clock is a specific part of the UHS
326 * voltage change dance.
328 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
329 * unconditionally turned back on in dw_mci_setup_bus() if it's
330 * ever called with a non-zero clock. That shouldn't happen
331 * until the voltage change is all done.
333 clk_en_a
= mci_readl(host
, CLKENA
);
334 clk_en_a
&= ~(SDMMC_CLKEN_LOW_PWR
<< slot
->id
);
335 mci_writel(host
, CLKENA
, clk_en_a
);
336 mci_send_cmd(slot
, SDMMC_CMD_UPD_CLK
|
337 SDMMC_CMD_PRV_DAT_WAIT
, 0);
340 if (cmd
->flags
& MMC_RSP_PRESENT
) {
341 /* We expect a response, so set this bit */
342 cmdr
|= SDMMC_CMD_RESP_EXP
;
343 if (cmd
->flags
& MMC_RSP_136
)
344 cmdr
|= SDMMC_CMD_RESP_LONG
;
347 if (cmd
->flags
& MMC_RSP_CRC
)
348 cmdr
|= SDMMC_CMD_RESP_CRC
;
351 cmdr
|= SDMMC_CMD_DAT_EXP
;
352 if (cmd
->data
->flags
& MMC_DATA_WRITE
)
353 cmdr
|= SDMMC_CMD_DAT_WR
;
356 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD
, &slot
->flags
))
357 cmdr
|= SDMMC_CMD_USE_HOLD_REG
;
362 static u32
dw_mci_prep_stop_abort(struct dw_mci
*host
, struct mmc_command
*cmd
)
364 struct mmc_command
*stop
;
370 stop
= &host
->stop_abort
;
372 memset(stop
, 0, sizeof(struct mmc_command
));
374 if (cmdr
== MMC_READ_SINGLE_BLOCK
||
375 cmdr
== MMC_READ_MULTIPLE_BLOCK
||
376 cmdr
== MMC_WRITE_BLOCK
||
377 cmdr
== MMC_WRITE_MULTIPLE_BLOCK
||
378 cmdr
== MMC_SEND_TUNING_BLOCK
||
379 cmdr
== MMC_SEND_TUNING_BLOCK_HS200
) {
380 stop
->opcode
= MMC_STOP_TRANSMISSION
;
382 stop
->flags
= MMC_RSP_R1B
| MMC_CMD_AC
;
383 } else if (cmdr
== SD_IO_RW_EXTENDED
) {
384 stop
->opcode
= SD_IO_RW_DIRECT
;
385 stop
->arg
|= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT
<< 9) |
386 ((cmd
->arg
>> 28) & 0x7);
387 stop
->flags
= MMC_RSP_SPI_R5
| MMC_RSP_R5
| MMC_CMD_AC
;
392 cmdr
= stop
->opcode
| SDMMC_CMD_STOP
|
393 SDMMC_CMD_RESP_CRC
| SDMMC_CMD_RESP_EXP
;
395 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD
, &host
->slot
->flags
))
396 cmdr
|= SDMMC_CMD_USE_HOLD_REG
;
401 static void dw_mci_start_command(struct dw_mci
*host
,
402 struct mmc_command
*cmd
, u32 cmd_flags
)
406 "start command: ARGR=0x%08x CMDR=0x%08x\n",
407 cmd
->arg
, cmd_flags
);
409 mci_writel(host
, CMDARG
, cmd
->arg
);
410 wmb(); /* drain writebuffer */
411 dw_mci_wait_while_busy(host
, cmd_flags
);
413 mci_writel(host
, CMD
, cmd_flags
| SDMMC_CMD_START
);
416 static inline void send_stop_abort(struct dw_mci
*host
, struct mmc_data
*data
)
418 struct mmc_command
*stop
= &host
->stop_abort
;
420 dw_mci_start_command(host
, stop
, host
->stop_cmdr
);
423 /* DMA interface functions */
424 static void dw_mci_stop_dma(struct dw_mci
*host
)
426 if (host
->using_dma
) {
427 host
->dma_ops
->stop(host
);
428 host
->dma_ops
->cleanup(host
);
431 /* Data transfer was stopped by the interrupt handler */
432 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
435 static void dw_mci_dma_cleanup(struct dw_mci
*host
)
437 struct mmc_data
*data
= host
->data
;
439 if (data
&& data
->host_cookie
== COOKIE_MAPPED
) {
440 dma_unmap_sg(host
->dev
,
443 mmc_get_dma_dir(data
));
444 data
->host_cookie
= COOKIE_UNMAPPED
;
448 static void dw_mci_idmac_reset(struct dw_mci
*host
)
450 u32 bmod
= mci_readl(host
, BMOD
);
451 /* Software reset of DMA */
452 bmod
|= SDMMC_IDMAC_SWRESET
;
453 mci_writel(host
, BMOD
, bmod
);
456 static void dw_mci_idmac_stop_dma(struct dw_mci
*host
)
460 /* Disable and reset the IDMAC interface */
461 temp
= mci_readl(host
, CTRL
);
462 temp
&= ~SDMMC_CTRL_USE_IDMAC
;
463 temp
|= SDMMC_CTRL_DMA_RESET
;
464 mci_writel(host
, CTRL
, temp
);
466 /* Stop the IDMAC running */
467 temp
= mci_readl(host
, BMOD
);
468 temp
&= ~(SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
);
469 temp
|= SDMMC_IDMAC_SWRESET
;
470 mci_writel(host
, BMOD
, temp
);
473 static void dw_mci_dmac_complete_dma(void *arg
)
475 struct dw_mci
*host
= arg
;
476 struct mmc_data
*data
= host
->data
;
478 dev_vdbg(host
->dev
, "DMA complete\n");
480 if ((host
->use_dma
== TRANS_MODE_EDMAC
) &&
481 data
&& (data
->flags
& MMC_DATA_READ
))
482 /* Invalidate cache after read */
483 dma_sync_sg_for_cpu(mmc_dev(host
->slot
->mmc
),
488 host
->dma_ops
->cleanup(host
);
491 * If the card was removed, data will be NULL. No point in trying to
492 * send the stop command or waiting for NBUSY in this case.
495 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
496 tasklet_schedule(&host
->tasklet
);
500 static int dw_mci_idmac_init(struct dw_mci
*host
)
504 if (host
->dma_64bit_address
== 1) {
505 struct idmac_desc_64addr
*p
;
506 /* Number of descriptors in the ring buffer */
508 DESC_RING_BUF_SZ
/ sizeof(struct idmac_desc_64addr
);
510 /* Forward link the descriptor list */
511 for (i
= 0, p
= host
->sg_cpu
; i
< host
->ring_size
- 1;
513 p
->des6
= (host
->sg_dma
+
514 (sizeof(struct idmac_desc_64addr
) *
515 (i
+ 1))) & 0xffffffff;
517 p
->des7
= (u64
)(host
->sg_dma
+
518 (sizeof(struct idmac_desc_64addr
) *
520 /* Initialize reserved and buffer size fields to "0" */
526 /* Set the last descriptor as the end-of-ring descriptor */
527 p
->des6
= host
->sg_dma
& 0xffffffff;
528 p
->des7
= (u64
)host
->sg_dma
>> 32;
529 p
->des0
= IDMAC_DES0_ER
;
532 struct idmac_desc
*p
;
533 /* Number of descriptors in the ring buffer */
535 DESC_RING_BUF_SZ
/ sizeof(struct idmac_desc
);
537 /* Forward link the descriptor list */
538 for (i
= 0, p
= host
->sg_cpu
;
539 i
< host
->ring_size
- 1;
541 p
->des3
= cpu_to_le32(host
->sg_dma
+
542 (sizeof(struct idmac_desc
) * (i
+ 1)));
546 /* Set the last descriptor as the end-of-ring descriptor */
547 p
->des3
= cpu_to_le32(host
->sg_dma
);
548 p
->des0
= cpu_to_le32(IDMAC_DES0_ER
);
551 dw_mci_idmac_reset(host
);
553 if (host
->dma_64bit_address
== 1) {
554 /* Mask out interrupts - get Tx & Rx complete only */
555 mci_writel(host
, IDSTS64
, IDMAC_INT_CLR
);
556 mci_writel(host
, IDINTEN64
, SDMMC_IDMAC_INT_NI
|
557 SDMMC_IDMAC_INT_RI
| SDMMC_IDMAC_INT_TI
);
559 /* Set the descriptor base address */
560 mci_writel(host
, DBADDRL
, host
->sg_dma
& 0xffffffff);
561 mci_writel(host
, DBADDRU
, (u64
)host
->sg_dma
>> 32);
564 /* Mask out interrupts - get Tx & Rx complete only */
565 mci_writel(host
, IDSTS
, IDMAC_INT_CLR
);
566 mci_writel(host
, IDINTEN
, SDMMC_IDMAC_INT_NI
|
567 SDMMC_IDMAC_INT_RI
| SDMMC_IDMAC_INT_TI
);
569 /* Set the descriptor base address */
570 mci_writel(host
, DBADDR
, host
->sg_dma
);
576 static inline int dw_mci_prepare_desc64(struct dw_mci
*host
,
577 struct mmc_data
*data
,
580 unsigned int desc_len
;
581 struct idmac_desc_64addr
*desc_first
, *desc_last
, *desc
;
585 desc_first
= desc_last
= desc
= host
->sg_cpu
;
587 for (i
= 0; i
< sg_len
; i
++) {
588 unsigned int length
= sg_dma_len(&data
->sg
[i
]);
590 u64 mem_addr
= sg_dma_address(&data
->sg
[i
]);
592 for ( ; length
; desc
++) {
593 desc_len
= (length
<= DW_MCI_DESC_DATA_LENGTH
) ?
594 length
: DW_MCI_DESC_DATA_LENGTH
;
599 * Wait for the former clear OWN bit operation
600 * of IDMAC to make sure that this descriptor
601 * isn't still owned by IDMAC as IDMAC's write
602 * ops and CPU's read ops are asynchronous.
604 if (readl_poll_timeout_atomic(&desc
->des0
, val
,
605 !(val
& IDMAC_DES0_OWN
),
606 10, 100 * USEC_PER_MSEC
))
610 * Set the OWN bit and disable interrupts
611 * for this descriptor
613 desc
->des0
= IDMAC_DES0_OWN
| IDMAC_DES0_DIC
|
617 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc
, desc_len
);
619 /* Physical address to DMA to/from */
620 desc
->des4
= mem_addr
& 0xffffffff;
621 desc
->des5
= mem_addr
>> 32;
623 /* Update physical address for the next desc */
624 mem_addr
+= desc_len
;
626 /* Save pointer to the last descriptor */
631 /* Set first descriptor */
632 desc_first
->des0
|= IDMAC_DES0_FD
;
634 /* Set last descriptor */
635 desc_last
->des0
&= ~(IDMAC_DES0_CH
| IDMAC_DES0_DIC
);
636 desc_last
->des0
|= IDMAC_DES0_LD
;
640 /* restore the descriptor chain as it's polluted */
641 dev_dbg(host
->dev
, "descriptor is still owned by IDMAC.\n");
642 memset(host
->sg_cpu
, 0, DESC_RING_BUF_SZ
);
643 dw_mci_idmac_init(host
);
648 static inline int dw_mci_prepare_desc32(struct dw_mci
*host
,
649 struct mmc_data
*data
,
652 unsigned int desc_len
;
653 struct idmac_desc
*desc_first
, *desc_last
, *desc
;
657 desc_first
= desc_last
= desc
= host
->sg_cpu
;
659 for (i
= 0; i
< sg_len
; i
++) {
660 unsigned int length
= sg_dma_len(&data
->sg
[i
]);
662 u32 mem_addr
= sg_dma_address(&data
->sg
[i
]);
664 for ( ; length
; desc
++) {
665 desc_len
= (length
<= DW_MCI_DESC_DATA_LENGTH
) ?
666 length
: DW_MCI_DESC_DATA_LENGTH
;
671 * Wait for the former clear OWN bit operation
672 * of IDMAC to make sure that this descriptor
673 * isn't still owned by IDMAC as IDMAC's write
674 * ops and CPU's read ops are asynchronous.
676 if (readl_poll_timeout_atomic(&desc
->des0
, val
,
677 IDMAC_OWN_CLR64(val
),
679 100 * USEC_PER_MSEC
))
683 * Set the OWN bit and disable interrupts
684 * for this descriptor
686 desc
->des0
= cpu_to_le32(IDMAC_DES0_OWN
|
691 IDMAC_SET_BUFFER1_SIZE(desc
, desc_len
);
693 /* Physical address to DMA to/from */
694 desc
->des2
= cpu_to_le32(mem_addr
);
696 /* Update physical address for the next desc */
697 mem_addr
+= desc_len
;
699 /* Save pointer to the last descriptor */
704 /* Set first descriptor */
705 desc_first
->des0
|= cpu_to_le32(IDMAC_DES0_FD
);
707 /* Set last descriptor */
708 desc_last
->des0
&= cpu_to_le32(~(IDMAC_DES0_CH
|
710 desc_last
->des0
|= cpu_to_le32(IDMAC_DES0_LD
);
714 /* restore the descriptor chain as it's polluted */
715 dev_dbg(host
->dev
, "descriptor is still owned by IDMAC.\n");
716 memset(host
->sg_cpu
, 0, DESC_RING_BUF_SZ
);
717 dw_mci_idmac_init(host
);
721 static int dw_mci_idmac_start_dma(struct dw_mci
*host
, unsigned int sg_len
)
726 if (host
->dma_64bit_address
== 1)
727 ret
= dw_mci_prepare_desc64(host
, host
->data
, sg_len
);
729 ret
= dw_mci_prepare_desc32(host
, host
->data
, sg_len
);
734 /* drain writebuffer */
737 /* Make sure to reset DMA in case we did PIO before this */
738 dw_mci_ctrl_reset(host
, SDMMC_CTRL_DMA_RESET
);
739 dw_mci_idmac_reset(host
);
741 /* Select IDMAC interface */
742 temp
= mci_readl(host
, CTRL
);
743 temp
|= SDMMC_CTRL_USE_IDMAC
;
744 mci_writel(host
, CTRL
, temp
);
746 /* drain writebuffer */
749 /* Enable the IDMAC */
750 temp
= mci_readl(host
, BMOD
);
751 temp
|= SDMMC_IDMAC_ENABLE
| SDMMC_IDMAC_FB
;
752 mci_writel(host
, BMOD
, temp
);
754 /* Start it running */
755 mci_writel(host
, PLDMND
, 1);
761 static const struct dw_mci_dma_ops dw_mci_idmac_ops
= {
762 .init
= dw_mci_idmac_init
,
763 .start
= dw_mci_idmac_start_dma
,
764 .stop
= dw_mci_idmac_stop_dma
,
765 .complete
= dw_mci_dmac_complete_dma
,
766 .cleanup
= dw_mci_dma_cleanup
,
769 static void dw_mci_edmac_stop_dma(struct dw_mci
*host
)
771 dmaengine_terminate_async(host
->dms
->ch
);
774 static int dw_mci_edmac_start_dma(struct dw_mci
*host
,
777 struct dma_slave_config cfg
;
778 struct dma_async_tx_descriptor
*desc
= NULL
;
779 struct scatterlist
*sgl
= host
->data
->sg
;
780 const u32 mszs
[] = {1, 4, 8, 16, 32, 64, 128, 256};
781 u32 sg_elems
= host
->data
->sg_len
;
783 u32 fifo_offset
= host
->fifo_reg
- host
->regs
;
786 /* Set external dma config: burst size, burst width */
787 cfg
.dst_addr
= host
->phy_regs
+ fifo_offset
;
788 cfg
.src_addr
= cfg
.dst_addr
;
789 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
790 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
792 /* Match burst msize with external dma config */
793 fifoth_val
= mci_readl(host
, FIFOTH
);
794 cfg
.dst_maxburst
= mszs
[(fifoth_val
>> 28) & 0x7];
795 cfg
.src_maxburst
= cfg
.dst_maxburst
;
797 if (host
->data
->flags
& MMC_DATA_WRITE
)
798 cfg
.direction
= DMA_MEM_TO_DEV
;
800 cfg
.direction
= DMA_DEV_TO_MEM
;
802 ret
= dmaengine_slave_config(host
->dms
->ch
, &cfg
);
804 dev_err(host
->dev
, "Failed to config edmac.\n");
808 desc
= dmaengine_prep_slave_sg(host
->dms
->ch
, sgl
,
809 sg_len
, cfg
.direction
,
810 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
812 dev_err(host
->dev
, "Can't prepare slave sg.\n");
816 /* Set dw_mci_dmac_complete_dma as callback */
817 desc
->callback
= dw_mci_dmac_complete_dma
;
818 desc
->callback_param
= (void *)host
;
819 dmaengine_submit(desc
);
821 /* Flush cache before write */
822 if (host
->data
->flags
& MMC_DATA_WRITE
)
823 dma_sync_sg_for_device(mmc_dev(host
->slot
->mmc
), sgl
,
824 sg_elems
, DMA_TO_DEVICE
);
826 dma_async_issue_pending(host
->dms
->ch
);
831 static int dw_mci_edmac_init(struct dw_mci
*host
)
833 /* Request external dma channel */
834 host
->dms
= kzalloc(sizeof(struct dw_mci_dma_slave
), GFP_KERNEL
);
838 host
->dms
->ch
= dma_request_slave_channel(host
->dev
, "rx-tx");
839 if (!host
->dms
->ch
) {
840 dev_err(host
->dev
, "Failed to get external DMA channel.\n");
849 static void dw_mci_edmac_exit(struct dw_mci
*host
)
853 dma_release_channel(host
->dms
->ch
);
854 host
->dms
->ch
= NULL
;
861 static const struct dw_mci_dma_ops dw_mci_edmac_ops
= {
862 .init
= dw_mci_edmac_init
,
863 .exit
= dw_mci_edmac_exit
,
864 .start
= dw_mci_edmac_start_dma
,
865 .stop
= dw_mci_edmac_stop_dma
,
866 .complete
= dw_mci_dmac_complete_dma
,
867 .cleanup
= dw_mci_dma_cleanup
,
870 static int dw_mci_pre_dma_transfer(struct dw_mci
*host
,
871 struct mmc_data
*data
,
874 struct scatterlist
*sg
;
875 unsigned int i
, sg_len
;
877 if (data
->host_cookie
== COOKIE_PRE_MAPPED
)
881 * We don't do DMA on "complex" transfers, i.e. with
882 * non-word-aligned buffers or lengths. Also, we don't bother
883 * with all the DMA setup overhead for short transfers.
885 if (data
->blocks
* data
->blksz
< DW_MCI_DMA_THRESHOLD
)
891 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
892 if (sg
->offset
& 3 || sg
->length
& 3)
896 sg_len
= dma_map_sg(host
->dev
,
899 mmc_get_dma_dir(data
));
903 data
->host_cookie
= cookie
;
908 static void dw_mci_pre_req(struct mmc_host
*mmc
,
909 struct mmc_request
*mrq
)
911 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
912 struct mmc_data
*data
= mrq
->data
;
914 if (!slot
->host
->use_dma
|| !data
)
917 /* This data might be unmapped at this time */
918 data
->host_cookie
= COOKIE_UNMAPPED
;
920 if (dw_mci_pre_dma_transfer(slot
->host
, mrq
->data
,
921 COOKIE_PRE_MAPPED
) < 0)
922 data
->host_cookie
= COOKIE_UNMAPPED
;
925 static void dw_mci_post_req(struct mmc_host
*mmc
,
926 struct mmc_request
*mrq
,
929 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
930 struct mmc_data
*data
= mrq
->data
;
932 if (!slot
->host
->use_dma
|| !data
)
935 if (data
->host_cookie
!= COOKIE_UNMAPPED
)
936 dma_unmap_sg(slot
->host
->dev
,
939 mmc_get_dma_dir(data
));
940 data
->host_cookie
= COOKIE_UNMAPPED
;
943 static int dw_mci_get_cd(struct mmc_host
*mmc
)
946 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
947 struct dw_mci
*host
= slot
->host
;
948 int gpio_cd
= mmc_gpio_get_cd(mmc
);
950 /* Use platform get_cd function, else try onboard card detect */
951 if (((mmc
->caps
& MMC_CAP_NEEDS_POLL
)
952 || !mmc_card_is_removable(mmc
))) {
955 if (!test_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
)) {
956 if (mmc
->caps
& MMC_CAP_NEEDS_POLL
) {
957 dev_info(&mmc
->class_dev
,
958 "card is polling.\n");
960 dev_info(&mmc
->class_dev
,
961 "card is non-removable.\n");
963 set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
);
967 } else if (gpio_cd
>= 0)
970 present
= (mci_readl(slot
->host
, CDETECT
) & (1 << slot
->id
))
973 spin_lock_bh(&host
->lock
);
974 if (present
&& !test_and_set_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
))
975 dev_dbg(&mmc
->class_dev
, "card is present\n");
977 !test_and_clear_bit(DW_MMC_CARD_PRESENT
, &slot
->flags
))
978 dev_dbg(&mmc
->class_dev
, "card is not present\n");
979 spin_unlock_bh(&host
->lock
);
984 static void dw_mci_adjust_fifoth(struct dw_mci
*host
, struct mmc_data
*data
)
986 unsigned int blksz
= data
->blksz
;
987 const u32 mszs
[] = {1, 4, 8, 16, 32, 64, 128, 256};
988 u32 fifo_width
= 1 << host
->data_shift
;
989 u32 blksz_depth
= blksz
/ fifo_width
, fifoth_val
;
990 u32 msize
= 0, rx_wmark
= 1, tx_wmark
, tx_wmark_invers
;
991 int idx
= ARRAY_SIZE(mszs
) - 1;
993 /* pio should ship this scenario */
997 tx_wmark
= (host
->fifo_depth
) / 2;
998 tx_wmark_invers
= host
->fifo_depth
- tx_wmark
;
1002 * if blksz is not a multiple of the FIFO width
1004 if (blksz
% fifo_width
)
1008 if (!((blksz_depth
% mszs
[idx
]) ||
1009 (tx_wmark_invers
% mszs
[idx
]))) {
1011 rx_wmark
= mszs
[idx
] - 1;
1014 } while (--idx
> 0);
1016 * If idx is '0', it won't be tried
1017 * Thus, initial values are uesed
1020 fifoth_val
= SDMMC_SET_FIFOTH(msize
, rx_wmark
, tx_wmark
);
1021 mci_writel(host
, FIFOTH
, fifoth_val
);
1024 static void dw_mci_ctrl_thld(struct dw_mci
*host
, struct mmc_data
*data
)
1026 unsigned int blksz
= data
->blksz
;
1027 u32 blksz_depth
, fifo_depth
;
1032 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1033 * in the FIFO region, so we really shouldn't access it).
1035 if (host
->verid
< DW_MMC_240A
||
1036 (host
->verid
< DW_MMC_280A
&& data
->flags
& MMC_DATA_WRITE
))
1040 * Card write Threshold is introduced since 2.80a
1041 * It's used when HS400 mode is enabled.
1043 if (data
->flags
& MMC_DATA_WRITE
&&
1044 !(host
->timing
!= MMC_TIMING_MMC_HS400
))
1047 if (data
->flags
& MMC_DATA_WRITE
)
1048 enable
= SDMMC_CARD_WR_THR_EN
;
1050 enable
= SDMMC_CARD_RD_THR_EN
;
1052 if (host
->timing
!= MMC_TIMING_MMC_HS200
&&
1053 host
->timing
!= MMC_TIMING_UHS_SDR104
)
1056 blksz_depth
= blksz
/ (1 << host
->data_shift
);
1057 fifo_depth
= host
->fifo_depth
;
1059 if (blksz_depth
> fifo_depth
)
1063 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1064 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1065 * Currently just choose blksz.
1068 mci_writel(host
, CDTHRCTL
, SDMMC_SET_THLD(thld_size
, enable
));
1072 mci_writel(host
, CDTHRCTL
, 0);
1075 static int dw_mci_submit_data_dma(struct dw_mci
*host
, struct mmc_data
*data
)
1077 unsigned long irqflags
;
1081 host
->using_dma
= 0;
1083 /* If we don't have a channel, we can't do DMA */
1087 sg_len
= dw_mci_pre_dma_transfer(host
, data
, COOKIE_MAPPED
);
1089 host
->dma_ops
->stop(host
);
1093 host
->using_dma
= 1;
1095 if (host
->use_dma
== TRANS_MODE_IDMAC
)
1097 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1098 (unsigned long)host
->sg_cpu
,
1099 (unsigned long)host
->sg_dma
,
1103 * Decide the MSIZE and RX/TX Watermark.
1104 * If current block size is same with previous size,
1105 * no need to update fifoth.
1107 if (host
->prev_blksz
!= data
->blksz
)
1108 dw_mci_adjust_fifoth(host
, data
);
1110 /* Enable the DMA interface */
1111 temp
= mci_readl(host
, CTRL
);
1112 temp
|= SDMMC_CTRL_DMA_ENABLE
;
1113 mci_writel(host
, CTRL
, temp
);
1115 /* Disable RX/TX IRQs, let DMA handle it */
1116 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1117 temp
= mci_readl(host
, INTMASK
);
1118 temp
&= ~(SDMMC_INT_RXDR
| SDMMC_INT_TXDR
);
1119 mci_writel(host
, INTMASK
, temp
);
1120 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1122 if (host
->dma_ops
->start(host
, sg_len
)) {
1123 host
->dma_ops
->stop(host
);
1124 /* We can't do DMA, try PIO for this one */
1126 "%s: fall back to PIO mode for current transfer\n",
1134 static void dw_mci_submit_data(struct dw_mci
*host
, struct mmc_data
*data
)
1136 unsigned long irqflags
;
1137 int flags
= SG_MITER_ATOMIC
;
1140 data
->error
= -EINPROGRESS
;
1142 WARN_ON(host
->data
);
1146 if (data
->flags
& MMC_DATA_READ
)
1147 host
->dir_status
= DW_MCI_RECV_STATUS
;
1149 host
->dir_status
= DW_MCI_SEND_STATUS
;
1151 dw_mci_ctrl_thld(host
, data
);
1153 if (dw_mci_submit_data_dma(host
, data
)) {
1154 if (host
->data
->flags
& MMC_DATA_READ
)
1155 flags
|= SG_MITER_TO_SG
;
1157 flags
|= SG_MITER_FROM_SG
;
1159 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
1160 host
->sg
= data
->sg
;
1161 host
->part_buf_start
= 0;
1162 host
->part_buf_count
= 0;
1164 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
| SDMMC_INT_RXDR
);
1166 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1167 temp
= mci_readl(host
, INTMASK
);
1168 temp
|= SDMMC_INT_TXDR
| SDMMC_INT_RXDR
;
1169 mci_writel(host
, INTMASK
, temp
);
1170 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1172 temp
= mci_readl(host
, CTRL
);
1173 temp
&= ~SDMMC_CTRL_DMA_ENABLE
;
1174 mci_writel(host
, CTRL
, temp
);
1177 * Use the initial fifoth_val for PIO mode. If wm_algined
1178 * is set, we set watermark same as data size.
1179 * If next issued data may be transfered by DMA mode,
1180 * prev_blksz should be invalidated.
1182 if (host
->wm_aligned
)
1183 dw_mci_adjust_fifoth(host
, data
);
1185 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
1186 host
->prev_blksz
= 0;
1189 * Keep the current block size.
1190 * It will be used to decide whether to update
1191 * fifoth register next time.
1193 host
->prev_blksz
= data
->blksz
;
1197 static void dw_mci_setup_bus(struct dw_mci_slot
*slot
, bool force_clkinit
)
1199 struct dw_mci
*host
= slot
->host
;
1200 unsigned int clock
= slot
->clock
;
1203 u32 sdmmc_cmd_bits
= SDMMC_CMD_UPD_CLK
| SDMMC_CMD_PRV_DAT_WAIT
;
1205 /* We must continue to set bit 28 in CMD until the change is complete */
1206 if (host
->state
== STATE_WAITING_CMD11_DONE
)
1207 sdmmc_cmd_bits
|= SDMMC_CMD_VOLT_SWITCH
;
1210 mci_writel(host
, CLKENA
, 0);
1211 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1212 } else if (clock
!= host
->current_speed
|| force_clkinit
) {
1213 div
= host
->bus_hz
/ clock
;
1214 if (host
->bus_hz
% clock
&& host
->bus_hz
> clock
)
1216 * move the + 1 after the divide to prevent
1217 * over-clocking the card.
1221 div
= (host
->bus_hz
!= clock
) ? DIV_ROUND_UP(div
, 2) : 0;
1223 if ((clock
!= slot
->__clk_old
&&
1224 !test_bit(DW_MMC_CARD_NEEDS_POLL
, &slot
->flags
)) ||
1226 /* Silent the verbose log if calling from PM context */
1228 dev_info(&slot
->mmc
->class_dev
,
1229 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1230 slot
->id
, host
->bus_hz
, clock
,
1231 div
? ((host
->bus_hz
/ div
) >> 1) :
1235 * If card is polling, display the message only
1236 * one time at boot time.
1238 if (slot
->mmc
->caps
& MMC_CAP_NEEDS_POLL
&&
1239 slot
->mmc
->f_min
== clock
)
1240 set_bit(DW_MMC_CARD_NEEDS_POLL
, &slot
->flags
);
1244 mci_writel(host
, CLKENA
, 0);
1245 mci_writel(host
, CLKSRC
, 0);
1248 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1250 /* set clock to desired speed */
1251 mci_writel(host
, CLKDIV
, div
);
1254 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1256 /* enable clock; only low power if no SDIO */
1257 clk_en_a
= SDMMC_CLKEN_ENABLE
<< slot
->id
;
1258 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
))
1259 clk_en_a
|= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
1260 mci_writel(host
, CLKENA
, clk_en_a
);
1263 mci_send_cmd(slot
, sdmmc_cmd_bits
, 0);
1265 /* keep the last clock value that was requested from core */
1266 slot
->__clk_old
= clock
;
1269 host
->current_speed
= clock
;
1271 /* Set the current slot bus width */
1272 mci_writel(host
, CTYPE
, (slot
->ctype
<< slot
->id
));
1275 static void __dw_mci_start_request(struct dw_mci
*host
,
1276 struct dw_mci_slot
*slot
,
1277 struct mmc_command
*cmd
)
1279 struct mmc_request
*mrq
;
1280 struct mmc_data
*data
;
1287 host
->pending_events
= 0;
1288 host
->completed_events
= 0;
1289 host
->cmd_status
= 0;
1290 host
->data_status
= 0;
1291 host
->dir_status
= 0;
1295 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
1296 mci_writel(host
, BYTCNT
, data
->blksz
*data
->blocks
);
1297 mci_writel(host
, BLKSIZ
, data
->blksz
);
1300 cmdflags
= dw_mci_prepare_command(slot
->mmc
, cmd
);
1302 /* this is the first command, send the initialization clock */
1303 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
))
1304 cmdflags
|= SDMMC_CMD_INIT
;
1307 dw_mci_submit_data(host
, data
);
1308 wmb(); /* drain writebuffer */
1311 dw_mci_start_command(host
, cmd
, cmdflags
);
1313 if (cmd
->opcode
== SD_SWITCH_VOLTAGE
) {
1314 unsigned long irqflags
;
1317 * Databook says to fail after 2ms w/ no response, but evidence
1318 * shows that sometimes the cmd11 interrupt takes over 130ms.
1319 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1320 * is just about to roll over.
1322 * We do this whole thing under spinlock and only if the
1323 * command hasn't already completed (indicating the the irq
1324 * already ran so we don't want the timeout).
1326 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1327 if (!test_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
))
1328 mod_timer(&host
->cmd11_timer
,
1329 jiffies
+ msecs_to_jiffies(500) + 1);
1330 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1333 host
->stop_cmdr
= dw_mci_prep_stop_abort(host
, cmd
);
1336 static void dw_mci_start_request(struct dw_mci
*host
,
1337 struct dw_mci_slot
*slot
)
1339 struct mmc_request
*mrq
= slot
->mrq
;
1340 struct mmc_command
*cmd
;
1342 cmd
= mrq
->sbc
? mrq
->sbc
: mrq
->cmd
;
1343 __dw_mci_start_request(host
, slot
, cmd
);
1346 /* must be called with host->lock held */
1347 static void dw_mci_queue_request(struct dw_mci
*host
, struct dw_mci_slot
*slot
,
1348 struct mmc_request
*mrq
)
1350 dev_vdbg(&slot
->mmc
->class_dev
, "queue request: state=%d\n",
1355 if (host
->state
== STATE_WAITING_CMD11_DONE
) {
1356 dev_warn(&slot
->mmc
->class_dev
,
1357 "Voltage change didn't complete\n");
1359 * this case isn't expected to happen, so we can
1360 * either crash here or just try to continue on
1361 * in the closest possible state
1363 host
->state
= STATE_IDLE
;
1366 if (host
->state
== STATE_IDLE
) {
1367 host
->state
= STATE_SENDING_CMD
;
1368 dw_mci_start_request(host
, slot
);
1370 list_add_tail(&slot
->queue_node
, &host
->queue
);
1374 static void dw_mci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1376 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1377 struct dw_mci
*host
= slot
->host
;
1382 * The check for card presence and queueing of the request must be
1383 * atomic, otherwise the card could be removed in between and the
1384 * request wouldn't fail until another card was inserted.
1387 if (!dw_mci_get_cd(mmc
)) {
1388 mrq
->cmd
->error
= -ENOMEDIUM
;
1389 mmc_request_done(mmc
, mrq
);
1393 spin_lock_bh(&host
->lock
);
1395 dw_mci_queue_request(host
, slot
, mrq
);
1397 spin_unlock_bh(&host
->lock
);
1400 static void dw_mci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1402 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1403 const struct dw_mci_drv_data
*drv_data
= slot
->host
->drv_data
;
1407 switch (ios
->bus_width
) {
1408 case MMC_BUS_WIDTH_4
:
1409 slot
->ctype
= SDMMC_CTYPE_4BIT
;
1411 case MMC_BUS_WIDTH_8
:
1412 slot
->ctype
= SDMMC_CTYPE_8BIT
;
1415 /* set default 1 bit mode */
1416 slot
->ctype
= SDMMC_CTYPE_1BIT
;
1419 regs
= mci_readl(slot
->host
, UHS_REG
);
1422 if (ios
->timing
== MMC_TIMING_MMC_DDR52
||
1423 ios
->timing
== MMC_TIMING_UHS_DDR50
||
1424 ios
->timing
== MMC_TIMING_MMC_HS400
)
1425 regs
|= ((0x1 << slot
->id
) << 16);
1427 regs
&= ~((0x1 << slot
->id
) << 16);
1429 mci_writel(slot
->host
, UHS_REG
, regs
);
1430 slot
->host
->timing
= ios
->timing
;
1433 * Use mirror of ios->clock to prevent race with mmc
1434 * core ios update when finding the minimum.
1436 slot
->clock
= ios
->clock
;
1438 if (drv_data
&& drv_data
->set_ios
)
1439 drv_data
->set_ios(slot
->host
, ios
);
1441 switch (ios
->power_mode
) {
1443 if (!IS_ERR(mmc
->supply
.vmmc
)) {
1444 ret
= mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
,
1447 dev_err(slot
->host
->dev
,
1448 "failed to enable vmmc regulator\n");
1449 /*return, if failed turn on vmmc*/
1453 set_bit(DW_MMC_CARD_NEED_INIT
, &slot
->flags
);
1454 regs
= mci_readl(slot
->host
, PWREN
);
1455 regs
|= (1 << slot
->id
);
1456 mci_writel(slot
->host
, PWREN
, regs
);
1459 if (!slot
->host
->vqmmc_enabled
) {
1460 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1461 ret
= regulator_enable(mmc
->supply
.vqmmc
);
1463 dev_err(slot
->host
->dev
,
1464 "failed to enable vqmmc\n");
1466 slot
->host
->vqmmc_enabled
= true;
1469 /* Keep track so we don't reset again */
1470 slot
->host
->vqmmc_enabled
= true;
1473 /* Reset our state machine after powering on */
1474 dw_mci_ctrl_reset(slot
->host
,
1475 SDMMC_CTRL_ALL_RESET_FLAGS
);
1478 /* Adjust clock / bus width after power is up */
1479 dw_mci_setup_bus(slot
, false);
1483 /* Turn clock off before power goes down */
1484 dw_mci_setup_bus(slot
, false);
1486 if (!IS_ERR(mmc
->supply
.vmmc
))
1487 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1489 if (!IS_ERR(mmc
->supply
.vqmmc
) && slot
->host
->vqmmc_enabled
)
1490 regulator_disable(mmc
->supply
.vqmmc
);
1491 slot
->host
->vqmmc_enabled
= false;
1493 regs
= mci_readl(slot
->host
, PWREN
);
1494 regs
&= ~(1 << slot
->id
);
1495 mci_writel(slot
->host
, PWREN
, regs
);
1501 if (slot
->host
->state
== STATE_WAITING_CMD11_DONE
&& ios
->clock
!= 0)
1502 slot
->host
->state
= STATE_IDLE
;
1505 static int dw_mci_card_busy(struct mmc_host
*mmc
)
1507 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1511 * Check the busy bit which is low when DAT[3:0]
1512 * (the data lines) are 0000
1514 status
= mci_readl(slot
->host
, STATUS
);
1516 return !!(status
& SDMMC_STATUS_BUSY
);
1519 static int dw_mci_switch_voltage(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1521 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1522 struct dw_mci
*host
= slot
->host
;
1523 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1525 u32 v18
= SDMMC_UHS_18V
<< slot
->id
;
1528 if (drv_data
&& drv_data
->switch_voltage
)
1529 return drv_data
->switch_voltage(mmc
, ios
);
1532 * Program the voltage. Note that some instances of dw_mmc may use
1533 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1534 * does no harm but you need to set the regulator directly. Try both.
1536 uhs
= mci_readl(host
, UHS_REG
);
1537 if (ios
->signal_voltage
== MMC_SIGNAL_VOLTAGE_330
)
1542 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1543 ret
= mmc_regulator_set_vqmmc(mmc
, ios
);
1546 dev_dbg(&mmc
->class_dev
,
1547 "Regulator set error %d - %s V\n",
1548 ret
, uhs
& v18
? "1.8" : "3.3");
1552 mci_writel(host
, UHS_REG
, uhs
);
1557 static int dw_mci_get_ro(struct mmc_host
*mmc
)
1560 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1561 int gpio_ro
= mmc_gpio_get_ro(mmc
);
1563 /* Use platform get_ro function, else try on board write protect */
1565 read_only
= gpio_ro
;
1568 mci_readl(slot
->host
, WRTPRT
) & (1 << slot
->id
) ? 1 : 0;
1570 dev_dbg(&mmc
->class_dev
, "card is %s\n",
1571 read_only
? "read-only" : "read-write");
1576 static void dw_mci_hw_reset(struct mmc_host
*mmc
)
1578 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1579 struct dw_mci
*host
= slot
->host
;
1582 if (host
->use_dma
== TRANS_MODE_IDMAC
)
1583 dw_mci_idmac_reset(host
);
1585 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_DMA_RESET
|
1586 SDMMC_CTRL_FIFO_RESET
))
1590 * According to eMMC spec, card reset procedure:
1591 * tRstW >= 1us: RST_n pulse width
1592 * tRSCA >= 200us: RST_n to Command time
1593 * tRSTH >= 1us: RST_n high period
1595 reset
= mci_readl(host
, RST_N
);
1596 reset
&= ~(SDMMC_RST_HWACTIVE
<< slot
->id
);
1597 mci_writel(host
, RST_N
, reset
);
1599 reset
|= SDMMC_RST_HWACTIVE
<< slot
->id
;
1600 mci_writel(host
, RST_N
, reset
);
1601 usleep_range(200, 300);
1604 static void dw_mci_init_card(struct mmc_host
*mmc
, struct mmc_card
*card
)
1606 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1607 struct dw_mci
*host
= slot
->host
;
1610 * Low power mode will stop the card clock when idle. According to the
1611 * description of the CLKENA register we should disable low power mode
1612 * for SDIO cards if we need SDIO interrupts to work.
1614 if (mmc
->caps
& MMC_CAP_SDIO_IRQ
) {
1615 const u32 clken_low_pwr
= SDMMC_CLKEN_LOW_PWR
<< slot
->id
;
1619 clk_en_a_old
= mci_readl(host
, CLKENA
);
1621 if (card
->type
== MMC_TYPE_SDIO
||
1622 card
->type
== MMC_TYPE_SD_COMBO
) {
1623 set_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
);
1624 clk_en_a
= clk_en_a_old
& ~clken_low_pwr
;
1626 clear_bit(DW_MMC_CARD_NO_LOW_PWR
, &slot
->flags
);
1627 clk_en_a
= clk_en_a_old
| clken_low_pwr
;
1630 if (clk_en_a
!= clk_en_a_old
) {
1631 mci_writel(host
, CLKENA
, clk_en_a
);
1632 mci_send_cmd(slot
, SDMMC_CMD_UPD_CLK
|
1633 SDMMC_CMD_PRV_DAT_WAIT
, 0);
1638 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot
*slot
, int enb
)
1640 struct dw_mci
*host
= slot
->host
;
1641 unsigned long irqflags
;
1644 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
1646 /* Enable/disable Slot Specific SDIO interrupt */
1647 int_mask
= mci_readl(host
, INTMASK
);
1649 int_mask
|= SDMMC_INT_SDIO(slot
->sdio_id
);
1651 int_mask
&= ~SDMMC_INT_SDIO(slot
->sdio_id
);
1652 mci_writel(host
, INTMASK
, int_mask
);
1654 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
1657 static void dw_mci_enable_sdio_irq(struct mmc_host
*mmc
, int enb
)
1659 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1660 struct dw_mci
*host
= slot
->host
;
1662 __dw_mci_enable_sdio_irq(slot
, enb
);
1664 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1666 pm_runtime_get_noresume(host
->dev
);
1668 pm_runtime_put_noidle(host
->dev
);
1671 static void dw_mci_ack_sdio_irq(struct mmc_host
*mmc
)
1673 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1675 __dw_mci_enable_sdio_irq(slot
, 1);
1678 static int dw_mci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1680 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1681 struct dw_mci
*host
= slot
->host
;
1682 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1685 if (drv_data
&& drv_data
->execute_tuning
)
1686 err
= drv_data
->execute_tuning(slot
, opcode
);
1690 static int dw_mci_prepare_hs400_tuning(struct mmc_host
*mmc
,
1691 struct mmc_ios
*ios
)
1693 struct dw_mci_slot
*slot
= mmc_priv(mmc
);
1694 struct dw_mci
*host
= slot
->host
;
1695 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
1697 if (drv_data
&& drv_data
->prepare_hs400_tuning
)
1698 return drv_data
->prepare_hs400_tuning(host
, ios
);
1703 static bool dw_mci_reset(struct dw_mci
*host
)
1705 u32 flags
= SDMMC_CTRL_RESET
| SDMMC_CTRL_FIFO_RESET
;
1710 * Resetting generates a block interrupt, hence setting
1711 * the scatter-gather pointer to NULL.
1714 sg_miter_stop(&host
->sg_miter
);
1719 flags
|= SDMMC_CTRL_DMA_RESET
;
1721 if (dw_mci_ctrl_reset(host
, flags
)) {
1723 * In all cases we clear the RAWINTS
1724 * register to clear any interrupts.
1726 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
1728 if (!host
->use_dma
) {
1733 /* Wait for dma_req to be cleared */
1734 if (readl_poll_timeout_atomic(host
->regs
+ SDMMC_STATUS
,
1736 !(status
& SDMMC_STATUS_DMA_REQ
),
1737 1, 500 * USEC_PER_MSEC
)) {
1739 "%s: Timeout waiting for dma_req to be cleared\n",
1744 /* when using DMA next we reset the fifo again */
1745 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_FIFO_RESET
))
1748 /* if the controller reset bit did clear, then set clock regs */
1749 if (!(mci_readl(host
, CTRL
) & SDMMC_CTRL_RESET
)) {
1751 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1757 if (host
->use_dma
== TRANS_MODE_IDMAC
)
1758 /* It is also recommended that we reset and reprogram idmac */
1759 dw_mci_idmac_reset(host
);
1764 /* After a CTRL reset we need to have CIU set clock registers */
1765 mci_send_cmd(host
->slot
, SDMMC_CMD_UPD_CLK
, 0);
1770 static const struct mmc_host_ops dw_mci_ops
= {
1771 .request
= dw_mci_request
,
1772 .pre_req
= dw_mci_pre_req
,
1773 .post_req
= dw_mci_post_req
,
1774 .set_ios
= dw_mci_set_ios
,
1775 .get_ro
= dw_mci_get_ro
,
1776 .get_cd
= dw_mci_get_cd
,
1777 .hw_reset
= dw_mci_hw_reset
,
1778 .enable_sdio_irq
= dw_mci_enable_sdio_irq
,
1779 .ack_sdio_irq
= dw_mci_ack_sdio_irq
,
1780 .execute_tuning
= dw_mci_execute_tuning
,
1781 .card_busy
= dw_mci_card_busy
,
1782 .start_signal_voltage_switch
= dw_mci_switch_voltage
,
1783 .init_card
= dw_mci_init_card
,
1784 .prepare_hs400_tuning
= dw_mci_prepare_hs400_tuning
,
1787 static void dw_mci_request_end(struct dw_mci
*host
, struct mmc_request
*mrq
)
1788 __releases(&host
->lock
)
1789 __acquires(&host
->lock
)
1791 struct dw_mci_slot
*slot
;
1792 struct mmc_host
*prev_mmc
= host
->slot
->mmc
;
1794 WARN_ON(host
->cmd
|| host
->data
);
1796 host
->slot
->mrq
= NULL
;
1798 if (!list_empty(&host
->queue
)) {
1799 slot
= list_entry(host
->queue
.next
,
1800 struct dw_mci_slot
, queue_node
);
1801 list_del(&slot
->queue_node
);
1802 dev_vdbg(host
->dev
, "list not empty: %s is next\n",
1803 mmc_hostname(slot
->mmc
));
1804 host
->state
= STATE_SENDING_CMD
;
1805 dw_mci_start_request(host
, slot
);
1807 dev_vdbg(host
->dev
, "list empty\n");
1809 if (host
->state
== STATE_SENDING_CMD11
)
1810 host
->state
= STATE_WAITING_CMD11_DONE
;
1812 host
->state
= STATE_IDLE
;
1815 spin_unlock(&host
->lock
);
1816 mmc_request_done(prev_mmc
, mrq
);
1817 spin_lock(&host
->lock
);
1820 static int dw_mci_command_complete(struct dw_mci
*host
, struct mmc_command
*cmd
)
1822 u32 status
= host
->cmd_status
;
1824 host
->cmd_status
= 0;
1826 /* Read the response from the card (up to 16 bytes) */
1827 if (cmd
->flags
& MMC_RSP_PRESENT
) {
1828 if (cmd
->flags
& MMC_RSP_136
) {
1829 cmd
->resp
[3] = mci_readl(host
, RESP0
);
1830 cmd
->resp
[2] = mci_readl(host
, RESP1
);
1831 cmd
->resp
[1] = mci_readl(host
, RESP2
);
1832 cmd
->resp
[0] = mci_readl(host
, RESP3
);
1834 cmd
->resp
[0] = mci_readl(host
, RESP0
);
1841 if (status
& SDMMC_INT_RTO
)
1842 cmd
->error
= -ETIMEDOUT
;
1843 else if ((cmd
->flags
& MMC_RSP_CRC
) && (status
& SDMMC_INT_RCRC
))
1844 cmd
->error
= -EILSEQ
;
1845 else if (status
& SDMMC_INT_RESP_ERR
)
1853 static int dw_mci_data_complete(struct dw_mci
*host
, struct mmc_data
*data
)
1855 u32 status
= host
->data_status
;
1857 if (status
& DW_MCI_DATA_ERROR_FLAGS
) {
1858 if (status
& SDMMC_INT_DRTO
) {
1859 data
->error
= -ETIMEDOUT
;
1860 } else if (status
& SDMMC_INT_DCRC
) {
1861 data
->error
= -EILSEQ
;
1862 } else if (status
& SDMMC_INT_EBE
) {
1863 if (host
->dir_status
==
1864 DW_MCI_SEND_STATUS
) {
1866 * No data CRC status was returned.
1867 * The number of bytes transferred
1868 * will be exaggerated in PIO mode.
1870 data
->bytes_xfered
= 0;
1871 data
->error
= -ETIMEDOUT
;
1872 } else if (host
->dir_status
==
1873 DW_MCI_RECV_STATUS
) {
1874 data
->error
= -EILSEQ
;
1877 /* SDMMC_INT_SBE is included */
1878 data
->error
= -EILSEQ
;
1881 dev_dbg(host
->dev
, "data error, status 0x%08x\n", status
);
1884 * After an error, there may be data lingering
1889 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
1896 static void dw_mci_set_drto(struct dw_mci
*host
)
1898 unsigned int drto_clks
;
1899 unsigned int drto_ms
;
1901 drto_clks
= mci_readl(host
, TMOUT
) >> 8;
1902 drto_ms
= DIV_ROUND_UP(drto_clks
, host
->bus_hz
/ 1000);
1904 /* add a bit spare time */
1907 mod_timer(&host
->dto_timer
, jiffies
+ msecs_to_jiffies(drto_ms
));
1910 static void dw_mci_tasklet_func(unsigned long priv
)
1912 struct dw_mci
*host
= (struct dw_mci
*)priv
;
1913 struct mmc_data
*data
;
1914 struct mmc_command
*cmd
;
1915 struct mmc_request
*mrq
;
1916 enum dw_mci_state state
;
1917 enum dw_mci_state prev_state
;
1920 spin_lock(&host
->lock
);
1922 state
= host
->state
;
1931 case STATE_WAITING_CMD11_DONE
:
1934 case STATE_SENDING_CMD11
:
1935 case STATE_SENDING_CMD
:
1936 if (!test_and_clear_bit(EVENT_CMD_COMPLETE
,
1937 &host
->pending_events
))
1942 set_bit(EVENT_CMD_COMPLETE
, &host
->completed_events
);
1943 err
= dw_mci_command_complete(host
, cmd
);
1944 if (cmd
== mrq
->sbc
&& !err
) {
1945 prev_state
= state
= STATE_SENDING_CMD
;
1946 __dw_mci_start_request(host
, host
->slot
,
1951 if (cmd
->data
&& err
) {
1953 * During UHS tuning sequence, sending the stop
1954 * command after the response CRC error would
1955 * throw the system into a confused state
1956 * causing all future tuning phases to report
1959 * In such case controller will move into a data
1960 * transfer state after a response error or
1961 * response CRC error. Let's let that finish
1962 * before trying to send a stop, so we'll go to
1963 * STATE_SENDING_DATA.
1965 * Although letting the data transfer take place
1966 * will waste a bit of time (we already know
1967 * the command was bad), it can't cause any
1968 * errors since it's possible it would have
1969 * taken place anyway if this tasklet got
1970 * delayed. Allowing the transfer to take place
1971 * avoids races and keeps things simple.
1973 if ((err
!= -ETIMEDOUT
) &&
1974 (cmd
->opcode
== MMC_SEND_TUNING_BLOCK
)) {
1975 state
= STATE_SENDING_DATA
;
1979 dw_mci_stop_dma(host
);
1980 send_stop_abort(host
, data
);
1981 state
= STATE_SENDING_STOP
;
1985 if (!cmd
->data
|| err
) {
1986 dw_mci_request_end(host
, mrq
);
1990 prev_state
= state
= STATE_SENDING_DATA
;
1993 case STATE_SENDING_DATA
:
1995 * We could get a data error and never a transfer
1996 * complete so we'd better check for it here.
1998 * Note that we don't really care if we also got a
1999 * transfer complete; stopping the DMA and sending an
2002 if (test_and_clear_bit(EVENT_DATA_ERROR
,
2003 &host
->pending_events
)) {
2004 dw_mci_stop_dma(host
);
2005 if (!(host
->data_status
& (SDMMC_INT_DRTO
|
2007 send_stop_abort(host
, data
);
2008 state
= STATE_DATA_ERROR
;
2012 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
2013 &host
->pending_events
)) {
2015 * If all data-related interrupts don't come
2016 * within the given time in reading data state.
2018 if (host
->dir_status
== DW_MCI_RECV_STATUS
)
2019 dw_mci_set_drto(host
);
2023 set_bit(EVENT_XFER_COMPLETE
, &host
->completed_events
);
2026 * Handle an EVENT_DATA_ERROR that might have shown up
2027 * before the transfer completed. This might not have
2028 * been caught by the check above because the interrupt
2029 * could have gone off between the previous check and
2030 * the check for transfer complete.
2032 * Technically this ought not be needed assuming we
2033 * get a DATA_COMPLETE eventually (we'll notice the
2034 * error and end the request), but it shouldn't hurt.
2036 * This has the advantage of sending the stop command.
2038 if (test_and_clear_bit(EVENT_DATA_ERROR
,
2039 &host
->pending_events
)) {
2040 dw_mci_stop_dma(host
);
2041 if (!(host
->data_status
& (SDMMC_INT_DRTO
|
2043 send_stop_abort(host
, data
);
2044 state
= STATE_DATA_ERROR
;
2047 prev_state
= state
= STATE_DATA_BUSY
;
2051 case STATE_DATA_BUSY
:
2052 if (!test_and_clear_bit(EVENT_DATA_COMPLETE
,
2053 &host
->pending_events
)) {
2055 * If data error interrupt comes but data over
2056 * interrupt doesn't come within the given time.
2057 * in reading data state.
2059 if (host
->dir_status
== DW_MCI_RECV_STATUS
)
2060 dw_mci_set_drto(host
);
2065 set_bit(EVENT_DATA_COMPLETE
, &host
->completed_events
);
2066 err
= dw_mci_data_complete(host
, data
);
2069 if (!data
->stop
|| mrq
->sbc
) {
2070 if (mrq
->sbc
&& data
->stop
)
2071 data
->stop
->error
= 0;
2072 dw_mci_request_end(host
, mrq
);
2076 /* stop command for open-ended transfer*/
2078 send_stop_abort(host
, data
);
2081 * If we don't have a command complete now we'll
2082 * never get one since we just reset everything;
2083 * better end the request.
2085 * If we do have a command complete we'll fall
2086 * through to the SENDING_STOP command and
2087 * everything will be peachy keen.
2089 if (!test_bit(EVENT_CMD_COMPLETE
,
2090 &host
->pending_events
)) {
2092 dw_mci_request_end(host
, mrq
);
2098 * If err has non-zero,
2099 * stop-abort command has been already issued.
2101 prev_state
= state
= STATE_SENDING_STOP
;
2105 case STATE_SENDING_STOP
:
2106 if (!test_and_clear_bit(EVENT_CMD_COMPLETE
,
2107 &host
->pending_events
))
2110 /* CMD error in data command */
2111 if (mrq
->cmd
->error
&& mrq
->data
)
2117 if (!mrq
->sbc
&& mrq
->stop
)
2118 dw_mci_command_complete(host
, mrq
->stop
);
2120 host
->cmd_status
= 0;
2122 dw_mci_request_end(host
, mrq
);
2125 case STATE_DATA_ERROR
:
2126 if (!test_and_clear_bit(EVENT_XFER_COMPLETE
,
2127 &host
->pending_events
))
2130 state
= STATE_DATA_BUSY
;
2133 } while (state
!= prev_state
);
2135 host
->state
= state
;
2137 spin_unlock(&host
->lock
);
2141 /* push final bytes to part_buf, only use during push */
2142 static void dw_mci_set_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2144 memcpy((void *)&host
->part_buf
, buf
, cnt
);
2145 host
->part_buf_count
= cnt
;
2148 /* append bytes to part_buf, only use during push */
2149 static int dw_mci_push_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2151 cnt
= min(cnt
, (1 << host
->data_shift
) - host
->part_buf_count
);
2152 memcpy((void *)&host
->part_buf
+ host
->part_buf_count
, buf
, cnt
);
2153 host
->part_buf_count
+= cnt
;
2157 /* pull first bytes from part_buf, only use during pull */
2158 static int dw_mci_pull_part_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2160 cnt
= min_t(int, cnt
, host
->part_buf_count
);
2162 memcpy(buf
, (void *)&host
->part_buf
+ host
->part_buf_start
,
2164 host
->part_buf_count
-= cnt
;
2165 host
->part_buf_start
+= cnt
;
2170 /* pull final bytes from the part_buf, assuming it's just been filled */
2171 static void dw_mci_pull_final_bytes(struct dw_mci
*host
, void *buf
, int cnt
)
2173 memcpy(buf
, &host
->part_buf
, cnt
);
2174 host
->part_buf_start
= cnt
;
2175 host
->part_buf_count
= (1 << host
->data_shift
) - cnt
;
2178 static void dw_mci_push_data16(struct dw_mci
*host
, void *buf
, int cnt
)
2180 struct mmc_data
*data
= host
->data
;
2183 /* try and push anything in the part_buf */
2184 if (unlikely(host
->part_buf_count
)) {
2185 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2189 if (host
->part_buf_count
== 2) {
2190 mci_fifo_writew(host
->fifo_reg
, host
->part_buf16
);
2191 host
->part_buf_count
= 0;
2194 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2195 if (unlikely((unsigned long)buf
& 0x1)) {
2197 u16 aligned_buf
[64];
2198 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
2199 int items
= len
>> 1;
2201 /* memcpy from input buffer into aligned buffer */
2202 memcpy(aligned_buf
, buf
, len
);
2205 /* push data from aligned buffer into fifo */
2206 for (i
= 0; i
< items
; ++i
)
2207 mci_fifo_writew(host
->fifo_reg
, aligned_buf
[i
]);
2214 for (; cnt
>= 2; cnt
-= 2)
2215 mci_fifo_writew(host
->fifo_reg
, *pdata
++);
2218 /* put anything remaining in the part_buf */
2220 dw_mci_set_part_bytes(host
, buf
, cnt
);
2221 /* Push data if we have reached the expected data length */
2222 if ((data
->bytes_xfered
+ init_cnt
) ==
2223 (data
->blksz
* data
->blocks
))
2224 mci_fifo_writew(host
->fifo_reg
, host
->part_buf16
);
2228 static void dw_mci_pull_data16(struct dw_mci
*host
, void *buf
, int cnt
)
2230 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2231 if (unlikely((unsigned long)buf
& 0x1)) {
2233 /* pull data from fifo into aligned buffer */
2234 u16 aligned_buf
[64];
2235 int len
= min(cnt
& -2, (int)sizeof(aligned_buf
));
2236 int items
= len
>> 1;
2239 for (i
= 0; i
< items
; ++i
)
2240 aligned_buf
[i
] = mci_fifo_readw(host
->fifo_reg
);
2241 /* memcpy from aligned buffer into output buffer */
2242 memcpy(buf
, aligned_buf
, len
);
2251 for (; cnt
>= 2; cnt
-= 2)
2252 *pdata
++ = mci_fifo_readw(host
->fifo_reg
);
2256 host
->part_buf16
= mci_fifo_readw(host
->fifo_reg
);
2257 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2261 static void dw_mci_push_data32(struct dw_mci
*host
, void *buf
, int cnt
)
2263 struct mmc_data
*data
= host
->data
;
2266 /* try and push anything in the part_buf */
2267 if (unlikely(host
->part_buf_count
)) {
2268 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2272 if (host
->part_buf_count
== 4) {
2273 mci_fifo_writel(host
->fifo_reg
, host
->part_buf32
);
2274 host
->part_buf_count
= 0;
2277 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2278 if (unlikely((unsigned long)buf
& 0x3)) {
2280 u32 aligned_buf
[32];
2281 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
2282 int items
= len
>> 2;
2284 /* memcpy from input buffer into aligned buffer */
2285 memcpy(aligned_buf
, buf
, len
);
2288 /* push data from aligned buffer into fifo */
2289 for (i
= 0; i
< items
; ++i
)
2290 mci_fifo_writel(host
->fifo_reg
, aligned_buf
[i
]);
2297 for (; cnt
>= 4; cnt
-= 4)
2298 mci_fifo_writel(host
->fifo_reg
, *pdata
++);
2301 /* put anything remaining in the part_buf */
2303 dw_mci_set_part_bytes(host
, buf
, cnt
);
2304 /* Push data if we have reached the expected data length */
2305 if ((data
->bytes_xfered
+ init_cnt
) ==
2306 (data
->blksz
* data
->blocks
))
2307 mci_fifo_writel(host
->fifo_reg
, host
->part_buf32
);
2311 static void dw_mci_pull_data32(struct dw_mci
*host
, void *buf
, int cnt
)
2313 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2314 if (unlikely((unsigned long)buf
& 0x3)) {
2316 /* pull data from fifo into aligned buffer */
2317 u32 aligned_buf
[32];
2318 int len
= min(cnt
& -4, (int)sizeof(aligned_buf
));
2319 int items
= len
>> 2;
2322 for (i
= 0; i
< items
; ++i
)
2323 aligned_buf
[i
] = mci_fifo_readl(host
->fifo_reg
);
2324 /* memcpy from aligned buffer into output buffer */
2325 memcpy(buf
, aligned_buf
, len
);
2334 for (; cnt
>= 4; cnt
-= 4)
2335 *pdata
++ = mci_fifo_readl(host
->fifo_reg
);
2339 host
->part_buf32
= mci_fifo_readl(host
->fifo_reg
);
2340 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2344 static void dw_mci_push_data64(struct dw_mci
*host
, void *buf
, int cnt
)
2346 struct mmc_data
*data
= host
->data
;
2349 /* try and push anything in the part_buf */
2350 if (unlikely(host
->part_buf_count
)) {
2351 int len
= dw_mci_push_part_bytes(host
, buf
, cnt
);
2356 if (host
->part_buf_count
== 8) {
2357 mci_fifo_writeq(host
->fifo_reg
, host
->part_buf
);
2358 host
->part_buf_count
= 0;
2361 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2362 if (unlikely((unsigned long)buf
& 0x7)) {
2364 u64 aligned_buf
[16];
2365 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
2366 int items
= len
>> 3;
2368 /* memcpy from input buffer into aligned buffer */
2369 memcpy(aligned_buf
, buf
, len
);
2372 /* push data from aligned buffer into fifo */
2373 for (i
= 0; i
< items
; ++i
)
2374 mci_fifo_writeq(host
->fifo_reg
, aligned_buf
[i
]);
2381 for (; cnt
>= 8; cnt
-= 8)
2382 mci_fifo_writeq(host
->fifo_reg
, *pdata
++);
2385 /* put anything remaining in the part_buf */
2387 dw_mci_set_part_bytes(host
, buf
, cnt
);
2388 /* Push data if we have reached the expected data length */
2389 if ((data
->bytes_xfered
+ init_cnt
) ==
2390 (data
->blksz
* data
->blocks
))
2391 mci_fifo_writeq(host
->fifo_reg
, host
->part_buf
);
2395 static void dw_mci_pull_data64(struct dw_mci
*host
, void *buf
, int cnt
)
2397 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2398 if (unlikely((unsigned long)buf
& 0x7)) {
2400 /* pull data from fifo into aligned buffer */
2401 u64 aligned_buf
[16];
2402 int len
= min(cnt
& -8, (int)sizeof(aligned_buf
));
2403 int items
= len
>> 3;
2406 for (i
= 0; i
< items
; ++i
)
2407 aligned_buf
[i
] = mci_fifo_readq(host
->fifo_reg
);
2409 /* memcpy from aligned buffer into output buffer */
2410 memcpy(buf
, aligned_buf
, len
);
2419 for (; cnt
>= 8; cnt
-= 8)
2420 *pdata
++ = mci_fifo_readq(host
->fifo_reg
);
2424 host
->part_buf
= mci_fifo_readq(host
->fifo_reg
);
2425 dw_mci_pull_final_bytes(host
, buf
, cnt
);
2429 static void dw_mci_pull_data(struct dw_mci
*host
, void *buf
, int cnt
)
2433 /* get remaining partial bytes */
2434 len
= dw_mci_pull_part_bytes(host
, buf
, cnt
);
2435 if (unlikely(len
== cnt
))
2440 /* get the rest of the data */
2441 host
->pull_data(host
, buf
, cnt
);
2444 static void dw_mci_read_data_pio(struct dw_mci
*host
, bool dto
)
2446 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
2448 unsigned int offset
;
2449 struct mmc_data
*data
= host
->data
;
2450 int shift
= host
->data_shift
;
2453 unsigned int remain
, fcnt
;
2456 if (!sg_miter_next(sg_miter
))
2459 host
->sg
= sg_miter
->piter
.sg
;
2460 buf
= sg_miter
->addr
;
2461 remain
= sg_miter
->length
;
2465 fcnt
= (SDMMC_GET_FCNT(mci_readl(host
, STATUS
))
2466 << shift
) + host
->part_buf_count
;
2467 len
= min(remain
, fcnt
);
2470 dw_mci_pull_data(host
, (void *)(buf
+ offset
), len
);
2471 data
->bytes_xfered
+= len
;
2476 sg_miter
->consumed
= offset
;
2477 status
= mci_readl(host
, MINTSTS
);
2478 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
2479 /* if the RXDR is ready read again */
2480 } while ((status
& SDMMC_INT_RXDR
) ||
2481 (dto
&& SDMMC_GET_FCNT(mci_readl(host
, STATUS
))));
2484 if (!sg_miter_next(sg_miter
))
2486 sg_miter
->consumed
= 0;
2488 sg_miter_stop(sg_miter
);
2492 sg_miter_stop(sg_miter
);
2494 smp_wmb(); /* drain writebuffer */
2495 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
2498 static void dw_mci_write_data_pio(struct dw_mci
*host
)
2500 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
2502 unsigned int offset
;
2503 struct mmc_data
*data
= host
->data
;
2504 int shift
= host
->data_shift
;
2507 unsigned int fifo_depth
= host
->fifo_depth
;
2508 unsigned int remain
, fcnt
;
2511 if (!sg_miter_next(sg_miter
))
2514 host
->sg
= sg_miter
->piter
.sg
;
2515 buf
= sg_miter
->addr
;
2516 remain
= sg_miter
->length
;
2520 fcnt
= ((fifo_depth
-
2521 SDMMC_GET_FCNT(mci_readl(host
, STATUS
)))
2522 << shift
) - host
->part_buf_count
;
2523 len
= min(remain
, fcnt
);
2526 host
->push_data(host
, (void *)(buf
+ offset
), len
);
2527 data
->bytes_xfered
+= len
;
2532 sg_miter
->consumed
= offset
;
2533 status
= mci_readl(host
, MINTSTS
);
2534 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
2535 } while (status
& SDMMC_INT_TXDR
); /* if TXDR write again */
2538 if (!sg_miter_next(sg_miter
))
2540 sg_miter
->consumed
= 0;
2542 sg_miter_stop(sg_miter
);
2546 sg_miter_stop(sg_miter
);
2548 smp_wmb(); /* drain writebuffer */
2549 set_bit(EVENT_XFER_COMPLETE
, &host
->pending_events
);
2552 static void dw_mci_cmd_interrupt(struct dw_mci
*host
, u32 status
)
2554 if (!host
->cmd_status
)
2555 host
->cmd_status
= status
;
2557 smp_wmb(); /* drain writebuffer */
2559 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2560 tasklet_schedule(&host
->tasklet
);
2563 static void dw_mci_handle_cd(struct dw_mci
*host
)
2565 struct dw_mci_slot
*slot
= host
->slot
;
2567 if (slot
->mmc
->ops
->card_event
)
2568 slot
->mmc
->ops
->card_event(slot
->mmc
);
2569 mmc_detect_change(slot
->mmc
,
2570 msecs_to_jiffies(host
->pdata
->detect_delay_ms
));
2573 static irqreturn_t
dw_mci_interrupt(int irq
, void *dev_id
)
2575 struct dw_mci
*host
= dev_id
;
2577 struct dw_mci_slot
*slot
= host
->slot
;
2579 pending
= mci_readl(host
, MINTSTS
); /* read-only mask reg */
2582 /* Check volt switch first, since it can look like an error */
2583 if ((host
->state
== STATE_SENDING_CMD11
) &&
2584 (pending
& SDMMC_INT_VOLT_SWITCH
)) {
2585 unsigned long irqflags
;
2587 mci_writel(host
, RINTSTS
, SDMMC_INT_VOLT_SWITCH
);
2588 pending
&= ~SDMMC_INT_VOLT_SWITCH
;
2591 * Hold the lock; we know cmd11_timer can't be kicked
2592 * off after the lock is released, so safe to delete.
2594 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
2595 dw_mci_cmd_interrupt(host
, pending
);
2596 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
2598 del_timer(&host
->cmd11_timer
);
2601 if (pending
& DW_MCI_CMD_ERROR_FLAGS
) {
2602 mci_writel(host
, RINTSTS
, DW_MCI_CMD_ERROR_FLAGS
);
2603 host
->cmd_status
= pending
;
2604 smp_wmb(); /* drain writebuffer */
2605 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2608 if (pending
& DW_MCI_DATA_ERROR_FLAGS
) {
2609 /* if there is an error report DATA_ERROR */
2610 mci_writel(host
, RINTSTS
, DW_MCI_DATA_ERROR_FLAGS
);
2611 host
->data_status
= pending
;
2612 smp_wmb(); /* drain writebuffer */
2613 set_bit(EVENT_DATA_ERROR
, &host
->pending_events
);
2614 tasklet_schedule(&host
->tasklet
);
2617 if (pending
& SDMMC_INT_DATA_OVER
) {
2618 del_timer(&host
->dto_timer
);
2620 mci_writel(host
, RINTSTS
, SDMMC_INT_DATA_OVER
);
2621 if (!host
->data_status
)
2622 host
->data_status
= pending
;
2623 smp_wmb(); /* drain writebuffer */
2624 if (host
->dir_status
== DW_MCI_RECV_STATUS
) {
2625 if (host
->sg
!= NULL
)
2626 dw_mci_read_data_pio(host
, true);
2628 set_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
2629 tasklet_schedule(&host
->tasklet
);
2632 if (pending
& SDMMC_INT_RXDR
) {
2633 mci_writel(host
, RINTSTS
, SDMMC_INT_RXDR
);
2634 if (host
->dir_status
== DW_MCI_RECV_STATUS
&& host
->sg
)
2635 dw_mci_read_data_pio(host
, false);
2638 if (pending
& SDMMC_INT_TXDR
) {
2639 mci_writel(host
, RINTSTS
, SDMMC_INT_TXDR
);
2640 if (host
->dir_status
== DW_MCI_SEND_STATUS
&& host
->sg
)
2641 dw_mci_write_data_pio(host
);
2644 if (pending
& SDMMC_INT_CMD_DONE
) {
2645 mci_writel(host
, RINTSTS
, SDMMC_INT_CMD_DONE
);
2646 dw_mci_cmd_interrupt(host
, pending
);
2649 if (pending
& SDMMC_INT_CD
) {
2650 mci_writel(host
, RINTSTS
, SDMMC_INT_CD
);
2651 dw_mci_handle_cd(host
);
2654 if (pending
& SDMMC_INT_SDIO(slot
->sdio_id
)) {
2655 mci_writel(host
, RINTSTS
,
2656 SDMMC_INT_SDIO(slot
->sdio_id
));
2657 __dw_mci_enable_sdio_irq(slot
, 0);
2658 sdio_signal_irq(slot
->mmc
);
2663 if (host
->use_dma
!= TRANS_MODE_IDMAC
)
2666 /* Handle IDMA interrupts */
2667 if (host
->dma_64bit_address
== 1) {
2668 pending
= mci_readl(host
, IDSTS64
);
2669 if (pending
& (SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
)) {
2670 mci_writel(host
, IDSTS64
, SDMMC_IDMAC_INT_TI
|
2671 SDMMC_IDMAC_INT_RI
);
2672 mci_writel(host
, IDSTS64
, SDMMC_IDMAC_INT_NI
);
2673 if (!test_bit(EVENT_DATA_ERROR
, &host
->pending_events
))
2674 host
->dma_ops
->complete((void *)host
);
2677 pending
= mci_readl(host
, IDSTS
);
2678 if (pending
& (SDMMC_IDMAC_INT_TI
| SDMMC_IDMAC_INT_RI
)) {
2679 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_TI
|
2680 SDMMC_IDMAC_INT_RI
);
2681 mci_writel(host
, IDSTS
, SDMMC_IDMAC_INT_NI
);
2682 if (!test_bit(EVENT_DATA_ERROR
, &host
->pending_events
))
2683 host
->dma_ops
->complete((void *)host
);
2690 static int dw_mci_init_slot(struct dw_mci
*host
)
2692 struct mmc_host
*mmc
;
2693 struct dw_mci_slot
*slot
;
2694 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
2698 mmc
= mmc_alloc_host(sizeof(struct dw_mci_slot
), host
->dev
);
2702 slot
= mmc_priv(mmc
);
2704 slot
->sdio_id
= host
->sdio_id0
+ slot
->id
;
2709 mmc
->ops
= &dw_mci_ops
;
2710 if (device_property_read_u32_array(host
->dev
, "clock-freq-min-max",
2712 mmc
->f_min
= DW_MCI_FREQ_MIN
;
2713 mmc
->f_max
= DW_MCI_FREQ_MAX
;
2716 "'clock-freq-min-max' property was deprecated.\n");
2717 mmc
->f_min
= freq
[0];
2718 mmc
->f_max
= freq
[1];
2721 /*if there are external regulators, get them*/
2722 ret
= mmc_regulator_get_supply(mmc
);
2723 if (ret
== -EPROBE_DEFER
)
2724 goto err_host_allocated
;
2726 if (!mmc
->ocr_avail
)
2727 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
2729 if (host
->pdata
->caps
)
2730 mmc
->caps
= host
->pdata
->caps
;
2733 * Support MMC_CAP_ERASE by default.
2734 * It needs to use trim/discard/erase commands.
2736 mmc
->caps
|= MMC_CAP_ERASE
;
2738 if (host
->pdata
->pm_caps
)
2739 mmc
->pm_caps
= host
->pdata
->pm_caps
;
2741 if (host
->dev
->of_node
) {
2742 ctrl_id
= of_alias_get_id(host
->dev
->of_node
, "mshc");
2746 ctrl_id
= to_platform_device(host
->dev
)->id
;
2748 if (drv_data
&& drv_data
->caps
)
2749 mmc
->caps
|= drv_data
->caps
[ctrl_id
];
2751 if (host
->pdata
->caps2
)
2752 mmc
->caps2
= host
->pdata
->caps2
;
2754 ret
= mmc_of_parse(mmc
);
2756 goto err_host_allocated
;
2758 /* Process SDIO IRQs through the sdio_irq_work. */
2759 if (mmc
->caps
& MMC_CAP_SDIO_IRQ
)
2760 mmc
->caps2
|= MMC_CAP2_SDIO_IRQ_NOTHREAD
;
2762 /* Useful defaults if platform data is unset. */
2763 if (host
->use_dma
== TRANS_MODE_IDMAC
) {
2764 mmc
->max_segs
= host
->ring_size
;
2765 mmc
->max_blk_size
= 65535;
2766 mmc
->max_seg_size
= 0x1000;
2767 mmc
->max_req_size
= mmc
->max_seg_size
* host
->ring_size
;
2768 mmc
->max_blk_count
= mmc
->max_req_size
/ 512;
2769 } else if (host
->use_dma
== TRANS_MODE_EDMAC
) {
2771 mmc
->max_blk_size
= 65535;
2772 mmc
->max_blk_count
= 65535;
2774 mmc
->max_blk_size
* mmc
->max_blk_count
;
2775 mmc
->max_seg_size
= mmc
->max_req_size
;
2777 /* TRANS_MODE_PIO */
2779 mmc
->max_blk_size
= 65535; /* BLKSIZ is 16 bits */
2780 mmc
->max_blk_count
= 512;
2781 mmc
->max_req_size
= mmc
->max_blk_size
*
2783 mmc
->max_seg_size
= mmc
->max_req_size
;
2788 ret
= mmc_add_host(mmc
);
2790 goto err_host_allocated
;
2792 #if defined(CONFIG_DEBUG_FS)
2793 dw_mci_init_debugfs(slot
);
2803 static void dw_mci_cleanup_slot(struct dw_mci_slot
*slot
)
2805 /* Debugfs stuff is cleaned up by mmc core */
2806 mmc_remove_host(slot
->mmc
);
2807 slot
->host
->slot
= NULL
;
2808 mmc_free_host(slot
->mmc
);
2811 static void dw_mci_init_dma(struct dw_mci
*host
)
2814 struct device
*dev
= host
->dev
;
2817 * Check tansfer mode from HCON[17:16]
2818 * Clear the ambiguous description of dw_mmc databook:
2819 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2820 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2821 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2822 * 2b'11: Non DW DMA Interface -> pio only
2823 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2824 * simpler request/acknowledge handshake mechanism and both of them
2825 * are regarded as external dma master for dw_mmc.
2827 host
->use_dma
= SDMMC_GET_TRANS_MODE(mci_readl(host
, HCON
));
2828 if (host
->use_dma
== DMA_INTERFACE_IDMA
) {
2829 host
->use_dma
= TRANS_MODE_IDMAC
;
2830 } else if (host
->use_dma
== DMA_INTERFACE_DWDMA
||
2831 host
->use_dma
== DMA_INTERFACE_GDMA
) {
2832 host
->use_dma
= TRANS_MODE_EDMAC
;
2837 /* Determine which DMA interface to use */
2838 if (host
->use_dma
== TRANS_MODE_IDMAC
) {
2840 * Check ADDR_CONFIG bit in HCON to find
2841 * IDMAC address bus width
2843 addr_config
= SDMMC_GET_ADDR_CONFIG(mci_readl(host
, HCON
));
2845 if (addr_config
== 1) {
2846 /* host supports IDMAC in 64-bit address mode */
2847 host
->dma_64bit_address
= 1;
2849 "IDMAC supports 64-bit address mode.\n");
2850 if (!dma_set_mask(host
->dev
, DMA_BIT_MASK(64)))
2851 dma_set_coherent_mask(host
->dev
,
2854 /* host supports IDMAC in 32-bit address mode */
2855 host
->dma_64bit_address
= 0;
2857 "IDMAC supports 32-bit address mode.\n");
2860 /* Alloc memory for sg translation */
2861 host
->sg_cpu
= dmam_alloc_coherent(host
->dev
,
2863 &host
->sg_dma
, GFP_KERNEL
);
2864 if (!host
->sg_cpu
) {
2866 "%s: could not alloc DMA memory\n",
2871 host
->dma_ops
= &dw_mci_idmac_ops
;
2872 dev_info(host
->dev
, "Using internal DMA controller.\n");
2874 /* TRANS_MODE_EDMAC: check dma bindings again */
2875 if ((device_property_read_string_array(dev
, "dma-names",
2877 !device_property_present(dev
, "dmas")) {
2880 host
->dma_ops
= &dw_mci_edmac_ops
;
2881 dev_info(host
->dev
, "Using external DMA controller.\n");
2884 if (host
->dma_ops
->init
&& host
->dma_ops
->start
&&
2885 host
->dma_ops
->stop
&& host
->dma_ops
->cleanup
) {
2886 if (host
->dma_ops
->init(host
)) {
2887 dev_err(host
->dev
, "%s: Unable to initialize DMA Controller.\n",
2892 dev_err(host
->dev
, "DMA initialization not found.\n");
2899 dev_info(host
->dev
, "Using PIO mode.\n");
2900 host
->use_dma
= TRANS_MODE_PIO
;
2903 static void dw_mci_cmd11_timer(unsigned long arg
)
2905 struct dw_mci
*host
= (struct dw_mci
*)arg
;
2907 if (host
->state
!= STATE_SENDING_CMD11
) {
2908 dev_warn(host
->dev
, "Unexpected CMD11 timeout\n");
2912 host
->cmd_status
= SDMMC_INT_RTO
;
2913 set_bit(EVENT_CMD_COMPLETE
, &host
->pending_events
);
2914 tasklet_schedule(&host
->tasklet
);
2917 static void dw_mci_dto_timer(unsigned long arg
)
2919 struct dw_mci
*host
= (struct dw_mci
*)arg
;
2921 switch (host
->state
) {
2922 case STATE_SENDING_DATA
:
2923 case STATE_DATA_BUSY
:
2925 * If DTO interrupt does NOT come in sending data state,
2926 * we should notify the driver to terminate current transfer
2927 * and report a data timeout to the core.
2929 host
->data_status
= SDMMC_INT_DRTO
;
2930 set_bit(EVENT_DATA_ERROR
, &host
->pending_events
);
2931 set_bit(EVENT_DATA_COMPLETE
, &host
->pending_events
);
2932 tasklet_schedule(&host
->tasklet
);
2940 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
2942 struct dw_mci_board
*pdata
;
2943 struct device
*dev
= host
->dev
;
2944 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
2946 u32 clock_frequency
;
2948 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
2950 return ERR_PTR(-ENOMEM
);
2952 /* find reset controller when exist */
2953 pdata
->rstc
= devm_reset_control_get_optional(dev
, "reset");
2954 if (IS_ERR(pdata
->rstc
)) {
2955 if (PTR_ERR(pdata
->rstc
) == -EPROBE_DEFER
)
2956 return ERR_PTR(-EPROBE_DEFER
);
2959 /* find out number of slots supported */
2960 if (device_property_read_u32(dev
, "num-slots", &pdata
->num_slots
))
2961 dev_info(dev
, "'num-slots' was deprecated.\n");
2963 if (device_property_read_u32(dev
, "fifo-depth", &pdata
->fifo_depth
))
2965 "fifo-depth property not found, using value of FIFOTH register as default\n");
2967 device_property_read_u32(dev
, "card-detect-delay",
2968 &pdata
->detect_delay_ms
);
2970 device_property_read_u32(dev
, "data-addr", &host
->data_addr_override
);
2972 if (device_property_present(dev
, "fifo-watermark-aligned"))
2973 host
->wm_aligned
= true;
2975 if (!device_property_read_u32(dev
, "clock-frequency", &clock_frequency
))
2976 pdata
->bus_hz
= clock_frequency
;
2978 if (drv_data
&& drv_data
->parse_dt
) {
2979 ret
= drv_data
->parse_dt(host
);
2981 return ERR_PTR(ret
);
2987 #else /* CONFIG_OF */
2988 static struct dw_mci_board
*dw_mci_parse_dt(struct dw_mci
*host
)
2990 return ERR_PTR(-EINVAL
);
2992 #endif /* CONFIG_OF */
2994 static void dw_mci_enable_cd(struct dw_mci
*host
)
2996 unsigned long irqflags
;
3000 * No need for CD if all slots have a non-error GPIO
3001 * as well as broken card detection is found.
3003 if (host
->slot
->mmc
->caps
& MMC_CAP_NEEDS_POLL
)
3006 if (mmc_gpio_get_cd(host
->slot
->mmc
) < 0) {
3007 spin_lock_irqsave(&host
->irq_lock
, irqflags
);
3008 temp
= mci_readl(host
, INTMASK
);
3009 temp
|= SDMMC_INT_CD
;
3010 mci_writel(host
, INTMASK
, temp
);
3011 spin_unlock_irqrestore(&host
->irq_lock
, irqflags
);
3015 int dw_mci_probe(struct dw_mci
*host
)
3017 const struct dw_mci_drv_data
*drv_data
= host
->drv_data
;
3018 int width
, i
, ret
= 0;
3022 host
->pdata
= dw_mci_parse_dt(host
);
3023 if (PTR_ERR(host
->pdata
) == -EPROBE_DEFER
) {
3024 return -EPROBE_DEFER
;
3025 } else if (IS_ERR(host
->pdata
)) {
3026 dev_err(host
->dev
, "platform data not available\n");
3031 host
->biu_clk
= devm_clk_get(host
->dev
, "biu");
3032 if (IS_ERR(host
->biu_clk
)) {
3033 dev_dbg(host
->dev
, "biu clock not available\n");
3035 ret
= clk_prepare_enable(host
->biu_clk
);
3037 dev_err(host
->dev
, "failed to enable biu clock\n");
3042 host
->ciu_clk
= devm_clk_get(host
->dev
, "ciu");
3043 if (IS_ERR(host
->ciu_clk
)) {
3044 dev_dbg(host
->dev
, "ciu clock not available\n");
3045 host
->bus_hz
= host
->pdata
->bus_hz
;
3047 ret
= clk_prepare_enable(host
->ciu_clk
);
3049 dev_err(host
->dev
, "failed to enable ciu clock\n");
3053 if (host
->pdata
->bus_hz
) {
3054 ret
= clk_set_rate(host
->ciu_clk
, host
->pdata
->bus_hz
);
3057 "Unable to set bus rate to %uHz\n",
3058 host
->pdata
->bus_hz
);
3060 host
->bus_hz
= clk_get_rate(host
->ciu_clk
);
3063 if (!host
->bus_hz
) {
3065 "Platform data must supply bus speed\n");
3070 if (drv_data
&& drv_data
->init
) {
3071 ret
= drv_data
->init(host
);
3074 "implementation specific init failed\n");
3079 if (!IS_ERR(host
->pdata
->rstc
)) {
3080 reset_control_assert(host
->pdata
->rstc
);
3081 usleep_range(10, 50);
3082 reset_control_deassert(host
->pdata
->rstc
);
3085 setup_timer(&host
->cmd11_timer
,
3086 dw_mci_cmd11_timer
, (unsigned long)host
);
3088 setup_timer(&host
->dto_timer
,
3089 dw_mci_dto_timer
, (unsigned long)host
);
3091 spin_lock_init(&host
->lock
);
3092 spin_lock_init(&host
->irq_lock
);
3093 INIT_LIST_HEAD(&host
->queue
);
3096 * Get the host data width - this assumes that HCON has been set with
3097 * the correct values.
3099 i
= SDMMC_GET_HDATA_WIDTH(mci_readl(host
, HCON
));
3101 host
->push_data
= dw_mci_push_data16
;
3102 host
->pull_data
= dw_mci_pull_data16
;
3104 host
->data_shift
= 1;
3105 } else if (i
== 2) {
3106 host
->push_data
= dw_mci_push_data64
;
3107 host
->pull_data
= dw_mci_pull_data64
;
3109 host
->data_shift
= 3;
3111 /* Check for a reserved value, and warn if it is */
3113 "HCON reports a reserved host data width!\n"
3114 "Defaulting to 32-bit access.\n");
3115 host
->push_data
= dw_mci_push_data32
;
3116 host
->pull_data
= dw_mci_pull_data32
;
3118 host
->data_shift
= 2;
3121 /* Reset all blocks */
3122 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_ALL_RESET_FLAGS
)) {
3127 host
->dma_ops
= host
->pdata
->dma_ops
;
3128 dw_mci_init_dma(host
);
3130 /* Clear the interrupts for the host controller */
3131 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3132 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
3134 /* Put in max timeout */
3135 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
3138 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3139 * Tx Mark = fifo_size / 2 DMA Size = 8
3141 if (!host
->pdata
->fifo_depth
) {
3143 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3144 * have been overwritten by the bootloader, just like we're
3145 * about to do, so if you know the value for your hardware, you
3146 * should put it in the platform data.
3148 fifo_size
= mci_readl(host
, FIFOTH
);
3149 fifo_size
= 1 + ((fifo_size
>> 16) & 0xfff);
3151 fifo_size
= host
->pdata
->fifo_depth
;
3153 host
->fifo_depth
= fifo_size
;
3155 SDMMC_SET_FIFOTH(0x2, fifo_size
/ 2 - 1, fifo_size
/ 2);
3156 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
3158 /* disable clock to CIU */
3159 mci_writel(host
, CLKENA
, 0);
3160 mci_writel(host
, CLKSRC
, 0);
3163 * In 2.40a spec, Data offset is changed.
3164 * Need to check the version-id and set data-offset for DATA register.
3166 host
->verid
= SDMMC_GET_VERID(mci_readl(host
, VERID
));
3167 dev_info(host
->dev
, "Version ID is %04x\n", host
->verid
);
3169 if (host
->data_addr_override
)
3170 host
->fifo_reg
= host
->regs
+ host
->data_addr_override
;
3171 else if (host
->verid
< DW_MMC_240A
)
3172 host
->fifo_reg
= host
->regs
+ DATA_OFFSET
;
3174 host
->fifo_reg
= host
->regs
+ DATA_240A_OFFSET
;
3176 tasklet_init(&host
->tasklet
, dw_mci_tasklet_func
, (unsigned long)host
);
3177 ret
= devm_request_irq(host
->dev
, host
->irq
, dw_mci_interrupt
,
3178 host
->irq_flags
, "dw-mci", host
);
3183 * Enable interrupts for command done, data over, data empty,
3184 * receive ready and error such as transmit, receive timeout, crc error
3186 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
3187 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
3188 DW_MCI_ERROR_FLAGS
);
3189 /* Enable mci interrupt */
3190 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
);
3193 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3194 host
->irq
, width
, fifo_size
);
3196 /* We need at least one slot to succeed */
3197 ret
= dw_mci_init_slot(host
);
3199 dev_dbg(host
->dev
, "slot %d init failed\n", i
);
3203 /* Now that slots are all setup, we can enable card detect */
3204 dw_mci_enable_cd(host
);
3209 if (host
->use_dma
&& host
->dma_ops
->exit
)
3210 host
->dma_ops
->exit(host
);
3212 if (!IS_ERR(host
->pdata
->rstc
))
3213 reset_control_assert(host
->pdata
->rstc
);
3216 clk_disable_unprepare(host
->ciu_clk
);
3219 clk_disable_unprepare(host
->biu_clk
);
3223 EXPORT_SYMBOL(dw_mci_probe
);
3225 void dw_mci_remove(struct dw_mci
*host
)
3227 dev_dbg(host
->dev
, "remove slot\n");
3229 dw_mci_cleanup_slot(host
->slot
);
3231 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3232 mci_writel(host
, INTMASK
, 0); /* disable all mmc interrupt first */
3234 /* disable clock to CIU */
3235 mci_writel(host
, CLKENA
, 0);
3236 mci_writel(host
, CLKSRC
, 0);
3238 if (host
->use_dma
&& host
->dma_ops
->exit
)
3239 host
->dma_ops
->exit(host
);
3241 if (!IS_ERR(host
->pdata
->rstc
))
3242 reset_control_assert(host
->pdata
->rstc
);
3244 clk_disable_unprepare(host
->ciu_clk
);
3245 clk_disable_unprepare(host
->biu_clk
);
3247 EXPORT_SYMBOL(dw_mci_remove
);
3252 int dw_mci_runtime_suspend(struct device
*dev
)
3254 struct dw_mci
*host
= dev_get_drvdata(dev
);
3256 if (host
->use_dma
&& host
->dma_ops
->exit
)
3257 host
->dma_ops
->exit(host
);
3259 clk_disable_unprepare(host
->ciu_clk
);
3262 (mmc_can_gpio_cd(host
->slot
->mmc
) ||
3263 !mmc_card_is_removable(host
->slot
->mmc
)))
3264 clk_disable_unprepare(host
->biu_clk
);
3268 EXPORT_SYMBOL(dw_mci_runtime_suspend
);
3270 int dw_mci_runtime_resume(struct device
*dev
)
3273 struct dw_mci
*host
= dev_get_drvdata(dev
);
3276 (mmc_can_gpio_cd(host
->slot
->mmc
) ||
3277 !mmc_card_is_removable(host
->slot
->mmc
))) {
3278 ret
= clk_prepare_enable(host
->biu_clk
);
3283 ret
= clk_prepare_enable(host
->ciu_clk
);
3287 if (!dw_mci_ctrl_reset(host
, SDMMC_CTRL_ALL_RESET_FLAGS
)) {
3288 clk_disable_unprepare(host
->ciu_clk
);
3293 if (host
->use_dma
&& host
->dma_ops
->init
)
3294 host
->dma_ops
->init(host
);
3297 * Restore the initial value at FIFOTH register
3298 * And Invalidate the prev_blksz with zero
3300 mci_writel(host
, FIFOTH
, host
->fifoth_val
);
3301 host
->prev_blksz
= 0;
3303 /* Put in max timeout */
3304 mci_writel(host
, TMOUT
, 0xFFFFFFFF);
3306 mci_writel(host
, RINTSTS
, 0xFFFFFFFF);
3307 mci_writel(host
, INTMASK
, SDMMC_INT_CMD_DONE
| SDMMC_INT_DATA_OVER
|
3308 SDMMC_INT_TXDR
| SDMMC_INT_RXDR
|
3309 DW_MCI_ERROR_FLAGS
);
3310 mci_writel(host
, CTRL
, SDMMC_CTRL_INT_ENABLE
);
3313 if (host
->slot
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
)
3314 dw_mci_set_ios(host
->slot
->mmc
, &host
->slot
->mmc
->ios
);
3316 /* Force setup bus to guarantee available clock output */
3317 dw_mci_setup_bus(host
->slot
, true);
3319 /* Now that slots are all setup, we can enable card detect */
3320 dw_mci_enable_cd(host
);
3326 (mmc_can_gpio_cd(host
->slot
->mmc
) ||
3327 !mmc_card_is_removable(host
->slot
->mmc
)))
3328 clk_disable_unprepare(host
->biu_clk
);
3332 EXPORT_SYMBOL(dw_mci_runtime_resume
);
3333 #endif /* CONFIG_PM */
3335 static int __init
dw_mci_init(void)
3337 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3341 static void __exit
dw_mci_exit(void)
3345 module_init(dw_mci_init
);
3346 module_exit(dw_mci_exit
);
3348 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3349 MODULE_AUTHOR("NXP Semiconductor VietNam");
3350 MODULE_AUTHOR("Imagination Technologies Ltd");
3351 MODULE_LICENSE("GPL v2");