]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/mmc/host/omap.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mmc: omap: Fix DMA configuration to not rely on device id
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / omap.c
1 /*
2 * linux/drivers/mmc/host/omap.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/timer.h>
25 #include <linux/omap-dma.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/card.h>
28 #include <linux/clk.h>
29 #include <linux/scatterlist.h>
30 #include <linux/slab.h>
31 #include <linux/platform_data/mmc-omap.h>
32
33
34 #define OMAP_MMC_REG_CMD 0x00
35 #define OMAP_MMC_REG_ARGL 0x01
36 #define OMAP_MMC_REG_ARGH 0x02
37 #define OMAP_MMC_REG_CON 0x03
38 #define OMAP_MMC_REG_STAT 0x04
39 #define OMAP_MMC_REG_IE 0x05
40 #define OMAP_MMC_REG_CTO 0x06
41 #define OMAP_MMC_REG_DTO 0x07
42 #define OMAP_MMC_REG_DATA 0x08
43 #define OMAP_MMC_REG_BLEN 0x09
44 #define OMAP_MMC_REG_NBLK 0x0a
45 #define OMAP_MMC_REG_BUF 0x0b
46 #define OMAP_MMC_REG_SDIO 0x0d
47 #define OMAP_MMC_REG_REV 0x0f
48 #define OMAP_MMC_REG_RSP0 0x10
49 #define OMAP_MMC_REG_RSP1 0x11
50 #define OMAP_MMC_REG_RSP2 0x12
51 #define OMAP_MMC_REG_RSP3 0x13
52 #define OMAP_MMC_REG_RSP4 0x14
53 #define OMAP_MMC_REG_RSP5 0x15
54 #define OMAP_MMC_REG_RSP6 0x16
55 #define OMAP_MMC_REG_RSP7 0x17
56 #define OMAP_MMC_REG_IOSR 0x18
57 #define OMAP_MMC_REG_SYSC 0x19
58 #define OMAP_MMC_REG_SYSS 0x1a
59
60 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
61 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
62 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
63 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
64 #define OMAP_MMC_STAT_A_FULL (1 << 10)
65 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
66 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
67 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
68 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
69 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
70 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
71 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
72 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
73
74 #define mmc_omap7xx() (host->features & MMC_OMAP7XX)
75 #define mmc_omap15xx() (host->features & MMC_OMAP15XX)
76 #define mmc_omap16xx() (host->features & MMC_OMAP16XX)
77 #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
78 #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
79 #define mmc_omap2() (!mmc_omap1())
80
81 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
82 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
83 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
84
85 /*
86 * Command types
87 */
88 #define OMAP_MMC_CMDTYPE_BC 0
89 #define OMAP_MMC_CMDTYPE_BCR 1
90 #define OMAP_MMC_CMDTYPE_AC 2
91 #define OMAP_MMC_CMDTYPE_ADTC 3
92
93 #define DRIVER_NAME "mmci-omap"
94
95 /* Specifies how often in millisecs to poll for card status changes
96 * when the cover switch is open */
97 #define OMAP_MMC_COVER_POLL_DELAY 500
98
99 struct mmc_omap_host;
100
101 struct mmc_omap_slot {
102 int id;
103 unsigned int vdd;
104 u16 saved_con;
105 u16 bus_mode;
106 unsigned int fclk_freq;
107
108 struct tasklet_struct cover_tasklet;
109 struct timer_list cover_timer;
110 unsigned cover_open;
111
112 struct mmc_request *mrq;
113 struct mmc_omap_host *host;
114 struct mmc_host *mmc;
115 struct omap_mmc_slot_data *pdata;
116 };
117
118 struct mmc_omap_host {
119 int initialized;
120 struct mmc_request * mrq;
121 struct mmc_command * cmd;
122 struct mmc_data * data;
123 struct mmc_host * mmc;
124 struct device * dev;
125 unsigned char id; /* 16xx chips have 2 MMC blocks */
126 struct clk * iclk;
127 struct clk * fclk;
128 struct dma_chan *dma_rx;
129 u32 dma_rx_burst;
130 struct dma_chan *dma_tx;
131 u32 dma_tx_burst;
132 struct resource *mem_res;
133 void __iomem *virt_base;
134 unsigned int phys_base;
135 int irq;
136 unsigned char bus_mode;
137 unsigned int reg_shift;
138
139 struct work_struct cmd_abort_work;
140 unsigned abort:1;
141 struct timer_list cmd_abort_timer;
142
143 struct work_struct slot_release_work;
144 struct mmc_omap_slot *next_slot;
145 struct work_struct send_stop_work;
146 struct mmc_data *stop_data;
147
148 unsigned int sg_len;
149 int sg_idx;
150 u16 * buffer;
151 u32 buffer_bytes_left;
152 u32 total_bytes_left;
153
154 unsigned features;
155 unsigned use_dma:1;
156 unsigned brs_received:1, dma_done:1;
157 unsigned dma_in_use:1;
158 spinlock_t dma_lock;
159
160 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
161 struct mmc_omap_slot *current_slot;
162 spinlock_t slot_lock;
163 wait_queue_head_t slot_wq;
164 int nr_slots;
165
166 struct timer_list clk_timer;
167 spinlock_t clk_lock; /* for changing enabled state */
168 unsigned int fclk_enabled:1;
169 struct workqueue_struct *mmc_omap_wq;
170
171 struct omap_mmc_platform_data *pdata;
172 };
173
174
175 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot)
176 {
177 unsigned long tick_ns;
178
179 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) {
180 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq;
181 ndelay(8 * tick_ns);
182 }
183 }
184
185 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable)
186 {
187 unsigned long flags;
188
189 spin_lock_irqsave(&host->clk_lock, flags);
190 if (host->fclk_enabled != enable) {
191 host->fclk_enabled = enable;
192 if (enable)
193 clk_enable(host->fclk);
194 else
195 clk_disable(host->fclk);
196 }
197 spin_unlock_irqrestore(&host->clk_lock, flags);
198 }
199
200 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
201 {
202 struct mmc_omap_host *host = slot->host;
203 unsigned long flags;
204
205 if (claimed)
206 goto no_claim;
207 spin_lock_irqsave(&host->slot_lock, flags);
208 while (host->mmc != NULL) {
209 spin_unlock_irqrestore(&host->slot_lock, flags);
210 wait_event(host->slot_wq, host->mmc == NULL);
211 spin_lock_irqsave(&host->slot_lock, flags);
212 }
213 host->mmc = slot->mmc;
214 spin_unlock_irqrestore(&host->slot_lock, flags);
215 no_claim:
216 del_timer(&host->clk_timer);
217 if (host->current_slot != slot || !claimed)
218 mmc_omap_fclk_offdelay(host->current_slot);
219
220 if (host->current_slot != slot) {
221 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00);
222 if (host->pdata->switch_slot != NULL)
223 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
224 host->current_slot = slot;
225 }
226
227 if (claimed) {
228 mmc_omap_fclk_enable(host, 1);
229
230 /* Doing the dummy read here seems to work around some bug
231 * at least in OMAP24xx silicon where the command would not
232 * start after writing the CMD register. Sigh. */
233 OMAP_MMC_READ(host, CON);
234
235 OMAP_MMC_WRITE(host, CON, slot->saved_con);
236 } else
237 mmc_omap_fclk_enable(host, 0);
238 }
239
240 static void mmc_omap_start_request(struct mmc_omap_host *host,
241 struct mmc_request *req);
242
243 static void mmc_omap_slot_release_work(struct work_struct *work)
244 {
245 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
246 slot_release_work);
247 struct mmc_omap_slot *next_slot = host->next_slot;
248 struct mmc_request *rq;
249
250 host->next_slot = NULL;
251 mmc_omap_select_slot(next_slot, 1);
252
253 rq = next_slot->mrq;
254 next_slot->mrq = NULL;
255 mmc_omap_start_request(host, rq);
256 }
257
258 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled)
259 {
260 struct mmc_omap_host *host = slot->host;
261 unsigned long flags;
262 int i;
263
264 BUG_ON(slot == NULL || host->mmc == NULL);
265
266 if (clk_enabled)
267 /* Keeps clock running for at least 8 cycles on valid freq */
268 mod_timer(&host->clk_timer, jiffies + HZ/10);
269 else {
270 del_timer(&host->clk_timer);
271 mmc_omap_fclk_offdelay(slot);
272 mmc_omap_fclk_enable(host, 0);
273 }
274
275 spin_lock_irqsave(&host->slot_lock, flags);
276 /* Check for any pending requests */
277 for (i = 0; i < host->nr_slots; i++) {
278 struct mmc_omap_slot *new_slot;
279
280 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
281 continue;
282
283 BUG_ON(host->next_slot != NULL);
284 new_slot = host->slots[i];
285 /* The current slot should not have a request in queue */
286 BUG_ON(new_slot == host->current_slot);
287
288 host->next_slot = new_slot;
289 host->mmc = new_slot->mmc;
290 spin_unlock_irqrestore(&host->slot_lock, flags);
291 queue_work(host->mmc_omap_wq, &host->slot_release_work);
292 return;
293 }
294
295 host->mmc = NULL;
296 wake_up(&host->slot_wq);
297 spin_unlock_irqrestore(&host->slot_lock, flags);
298 }
299
300 static inline
301 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
302 {
303 if (slot->pdata->get_cover_state)
304 return slot->pdata->get_cover_state(mmc_dev(slot->mmc),
305 slot->id);
306 return 0;
307 }
308
309 static ssize_t
310 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
311 char *buf)
312 {
313 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
314 struct mmc_omap_slot *slot = mmc_priv(mmc);
315
316 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
317 "closed");
318 }
319
320 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
321
322 static ssize_t
323 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
324 char *buf)
325 {
326 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
327 struct mmc_omap_slot *slot = mmc_priv(mmc);
328
329 return sprintf(buf, "%s\n", slot->pdata->name);
330 }
331
332 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
333
334 static void
335 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
336 {
337 u32 cmdreg;
338 u32 resptype;
339 u32 cmdtype;
340
341 host->cmd = cmd;
342
343 resptype = 0;
344 cmdtype = 0;
345
346 /* Our hardware needs to know exact type */
347 switch (mmc_resp_type(cmd)) {
348 case MMC_RSP_NONE:
349 break;
350 case MMC_RSP_R1:
351 case MMC_RSP_R1B:
352 /* resp 1, 1b, 6, 7 */
353 resptype = 1;
354 break;
355 case MMC_RSP_R2:
356 resptype = 2;
357 break;
358 case MMC_RSP_R3:
359 resptype = 3;
360 break;
361 default:
362 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
363 break;
364 }
365
366 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
367 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
368 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
369 cmdtype = OMAP_MMC_CMDTYPE_BC;
370 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
371 cmdtype = OMAP_MMC_CMDTYPE_BCR;
372 } else {
373 cmdtype = OMAP_MMC_CMDTYPE_AC;
374 }
375
376 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
377
378 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
379 cmdreg |= 1 << 6;
380
381 if (cmd->flags & MMC_RSP_BUSY)
382 cmdreg |= 1 << 11;
383
384 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
385 cmdreg |= 1 << 15;
386
387 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2);
388
389 OMAP_MMC_WRITE(host, CTO, 200);
390 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
391 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
392 OMAP_MMC_WRITE(host, IE,
393 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
394 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
395 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
396 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
397 OMAP_MMC_STAT_END_OF_DATA);
398 OMAP_MMC_WRITE(host, CMD, cmdreg);
399 }
400
401 static void
402 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
403 int abort)
404 {
405 enum dma_data_direction dma_data_dir;
406 struct device *dev = mmc_dev(host->mmc);
407 struct dma_chan *c;
408
409 if (data->flags & MMC_DATA_WRITE) {
410 dma_data_dir = DMA_TO_DEVICE;
411 c = host->dma_tx;
412 } else {
413 dma_data_dir = DMA_FROM_DEVICE;
414 c = host->dma_rx;
415 }
416 if (c) {
417 if (data->error) {
418 dmaengine_terminate_all(c);
419 /* Claim nothing transferred on error... */
420 data->bytes_xfered = 0;
421 }
422 dev = c->device->dev;
423 }
424 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir);
425 }
426
427 static void mmc_omap_send_stop_work(struct work_struct *work)
428 {
429 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
430 send_stop_work);
431 struct mmc_omap_slot *slot = host->current_slot;
432 struct mmc_data *data = host->stop_data;
433 unsigned long tick_ns;
434
435 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq;
436 ndelay(8*tick_ns);
437
438 mmc_omap_start_command(host, data->stop);
439 }
440
441 static void
442 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
443 {
444 if (host->dma_in_use)
445 mmc_omap_release_dma(host, data, data->error);
446
447 host->data = NULL;
448 host->sg_len = 0;
449
450 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
451 * dozens of requests until the card finishes writing data.
452 * It'd be cheaper to just wait till an EOFB interrupt arrives...
453 */
454
455 if (!data->stop) {
456 struct mmc_host *mmc;
457
458 host->mrq = NULL;
459 mmc = host->mmc;
460 mmc_omap_release_slot(host->current_slot, 1);
461 mmc_request_done(mmc, data->mrq);
462 return;
463 }
464
465 host->stop_data = data;
466 queue_work(host->mmc_omap_wq, &host->send_stop_work);
467 }
468
469 static void
470 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops)
471 {
472 struct mmc_omap_slot *slot = host->current_slot;
473 unsigned int restarts, passes, timeout;
474 u16 stat = 0;
475
476 /* Sending abort takes 80 clocks. Have some extra and round up */
477 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
478 restarts = 0;
479 while (restarts < maxloops) {
480 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
481 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
482
483 passes = 0;
484 while (passes < timeout) {
485 stat = OMAP_MMC_READ(host, STAT);
486 if (stat & OMAP_MMC_STAT_END_OF_CMD)
487 goto out;
488 udelay(1);
489 passes++;
490 }
491
492 restarts++;
493 }
494 out:
495 OMAP_MMC_WRITE(host, STAT, stat);
496 }
497
498 static void
499 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
500 {
501 if (host->dma_in_use)
502 mmc_omap_release_dma(host, data, 1);
503
504 host->data = NULL;
505 host->sg_len = 0;
506
507 mmc_omap_send_abort(host, 10000);
508 }
509
510 static void
511 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
512 {
513 unsigned long flags;
514 int done;
515
516 if (!host->dma_in_use) {
517 mmc_omap_xfer_done(host, data);
518 return;
519 }
520 done = 0;
521 spin_lock_irqsave(&host->dma_lock, flags);
522 if (host->dma_done)
523 done = 1;
524 else
525 host->brs_received = 1;
526 spin_unlock_irqrestore(&host->dma_lock, flags);
527 if (done)
528 mmc_omap_xfer_done(host, data);
529 }
530
531 static void
532 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
533 {
534 unsigned long flags;
535 int done;
536
537 done = 0;
538 spin_lock_irqsave(&host->dma_lock, flags);
539 if (host->brs_received)
540 done = 1;
541 else
542 host->dma_done = 1;
543 spin_unlock_irqrestore(&host->dma_lock, flags);
544 if (done)
545 mmc_omap_xfer_done(host, data);
546 }
547
548 static void
549 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
550 {
551 host->cmd = NULL;
552
553 del_timer(&host->cmd_abort_timer);
554
555 if (cmd->flags & MMC_RSP_PRESENT) {
556 if (cmd->flags & MMC_RSP_136) {
557 /* response type 2 */
558 cmd->resp[3] =
559 OMAP_MMC_READ(host, RSP0) |
560 (OMAP_MMC_READ(host, RSP1) << 16);
561 cmd->resp[2] =
562 OMAP_MMC_READ(host, RSP2) |
563 (OMAP_MMC_READ(host, RSP3) << 16);
564 cmd->resp[1] =
565 OMAP_MMC_READ(host, RSP4) |
566 (OMAP_MMC_READ(host, RSP5) << 16);
567 cmd->resp[0] =
568 OMAP_MMC_READ(host, RSP6) |
569 (OMAP_MMC_READ(host, RSP7) << 16);
570 } else {
571 /* response types 1, 1b, 3, 4, 5, 6 */
572 cmd->resp[0] =
573 OMAP_MMC_READ(host, RSP6) |
574 (OMAP_MMC_READ(host, RSP7) << 16);
575 }
576 }
577
578 if (host->data == NULL || cmd->error) {
579 struct mmc_host *mmc;
580
581 if (host->data != NULL)
582 mmc_omap_abort_xfer(host, host->data);
583 host->mrq = NULL;
584 mmc = host->mmc;
585 mmc_omap_release_slot(host->current_slot, 1);
586 mmc_request_done(mmc, cmd->mrq);
587 }
588 }
589
590 /*
591 * Abort stuck command. Can occur when card is removed while it is being
592 * read.
593 */
594 static void mmc_omap_abort_command(struct work_struct *work)
595 {
596 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
597 cmd_abort_work);
598 BUG_ON(!host->cmd);
599
600 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
601 host->cmd->opcode);
602
603 if (host->cmd->error == 0)
604 host->cmd->error = -ETIMEDOUT;
605
606 if (host->data == NULL) {
607 struct mmc_command *cmd;
608 struct mmc_host *mmc;
609
610 cmd = host->cmd;
611 host->cmd = NULL;
612 mmc_omap_send_abort(host, 10000);
613
614 host->mrq = NULL;
615 mmc = host->mmc;
616 mmc_omap_release_slot(host->current_slot, 1);
617 mmc_request_done(mmc, cmd->mrq);
618 } else
619 mmc_omap_cmd_done(host, host->cmd);
620
621 host->abort = 0;
622 enable_irq(host->irq);
623 }
624
625 static void
626 mmc_omap_cmd_timer(unsigned long data)
627 {
628 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
629 unsigned long flags;
630
631 spin_lock_irqsave(&host->slot_lock, flags);
632 if (host->cmd != NULL && !host->abort) {
633 OMAP_MMC_WRITE(host, IE, 0);
634 disable_irq(host->irq);
635 host->abort = 1;
636 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
637 }
638 spin_unlock_irqrestore(&host->slot_lock, flags);
639 }
640
641 /* PIO only */
642 static void
643 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
644 {
645 struct scatterlist *sg;
646
647 sg = host->data->sg + host->sg_idx;
648 host->buffer_bytes_left = sg->length;
649 host->buffer = sg_virt(sg);
650 if (host->buffer_bytes_left > host->total_bytes_left)
651 host->buffer_bytes_left = host->total_bytes_left;
652 }
653
654 static void
655 mmc_omap_clk_timer(unsigned long data)
656 {
657 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
658
659 mmc_omap_fclk_enable(host, 0);
660 }
661
662 /* PIO only */
663 static void
664 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
665 {
666 int n, nwords;
667
668 if (host->buffer_bytes_left == 0) {
669 host->sg_idx++;
670 BUG_ON(host->sg_idx == host->sg_len);
671 mmc_omap_sg_to_buf(host);
672 }
673 n = 64;
674 if (n > host->buffer_bytes_left)
675 n = host->buffer_bytes_left;
676
677 nwords = n / 2;
678 nwords += n & 1; /* handle odd number of bytes to transfer */
679
680 host->buffer_bytes_left -= n;
681 host->total_bytes_left -= n;
682 host->data->bytes_xfered += n;
683
684 if (write) {
685 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA),
686 host->buffer, nwords);
687 } else {
688 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA),
689 host->buffer, nwords);
690 }
691
692 host->buffer += nwords;
693 }
694
695 #ifdef CONFIG_MMC_DEBUG
696 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
697 {
698 static const char *mmc_omap_status_bits[] = {
699 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
700 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
701 };
702 int i;
703 char res[64], *buf = res;
704
705 buf += sprintf(buf, "MMC IRQ 0x%x:", status);
706
707 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
708 if (status & (1 << i))
709 buf += sprintf(buf, " %s", mmc_omap_status_bits[i]);
710 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
711 }
712 #else
713 static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status)
714 {
715 }
716 #endif
717
718
719 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
720 {
721 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
722 u16 status;
723 int end_command;
724 int end_transfer;
725 int transfer_error, cmd_error;
726
727 if (host->cmd == NULL && host->data == NULL) {
728 status = OMAP_MMC_READ(host, STAT);
729 dev_info(mmc_dev(host->slots[0]->mmc),
730 "Spurious IRQ 0x%04x\n", status);
731 if (status != 0) {
732 OMAP_MMC_WRITE(host, STAT, status);
733 OMAP_MMC_WRITE(host, IE, 0);
734 }
735 return IRQ_HANDLED;
736 }
737
738 end_command = 0;
739 end_transfer = 0;
740 transfer_error = 0;
741 cmd_error = 0;
742
743 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
744 int cmd;
745
746 OMAP_MMC_WRITE(host, STAT, status);
747 if (host->cmd != NULL)
748 cmd = host->cmd->opcode;
749 else
750 cmd = -1;
751 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
752 status, cmd);
753 mmc_omap_report_irq(host, status);
754
755 if (host->total_bytes_left) {
756 if ((status & OMAP_MMC_STAT_A_FULL) ||
757 (status & OMAP_MMC_STAT_END_OF_DATA))
758 mmc_omap_xfer_data(host, 0);
759 if (status & OMAP_MMC_STAT_A_EMPTY)
760 mmc_omap_xfer_data(host, 1);
761 }
762
763 if (status & OMAP_MMC_STAT_END_OF_DATA)
764 end_transfer = 1;
765
766 if (status & OMAP_MMC_STAT_DATA_TOUT) {
767 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
768 cmd);
769 if (host->data) {
770 host->data->error = -ETIMEDOUT;
771 transfer_error = 1;
772 }
773 }
774
775 if (status & OMAP_MMC_STAT_DATA_CRC) {
776 if (host->data) {
777 host->data->error = -EILSEQ;
778 dev_dbg(mmc_dev(host->mmc),
779 "data CRC error, bytes left %d\n",
780 host->total_bytes_left);
781 transfer_error = 1;
782 } else {
783 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
784 }
785 }
786
787 if (status & OMAP_MMC_STAT_CMD_TOUT) {
788 /* Timeouts are routine with some commands */
789 if (host->cmd) {
790 struct mmc_omap_slot *slot =
791 host->current_slot;
792 if (slot == NULL ||
793 !mmc_omap_cover_is_open(slot))
794 dev_err(mmc_dev(host->mmc),
795 "command timeout (CMD%d)\n",
796 cmd);
797 host->cmd->error = -ETIMEDOUT;
798 end_command = 1;
799 cmd_error = 1;
800 }
801 }
802
803 if (status & OMAP_MMC_STAT_CMD_CRC) {
804 if (host->cmd) {
805 dev_err(mmc_dev(host->mmc),
806 "command CRC error (CMD%d, arg 0x%08x)\n",
807 cmd, host->cmd->arg);
808 host->cmd->error = -EILSEQ;
809 end_command = 1;
810 cmd_error = 1;
811 } else
812 dev_err(mmc_dev(host->mmc),
813 "command CRC error without cmd?\n");
814 }
815
816 if (status & OMAP_MMC_STAT_CARD_ERR) {
817 dev_dbg(mmc_dev(host->mmc),
818 "ignoring card status error (CMD%d)\n",
819 cmd);
820 end_command = 1;
821 }
822
823 /*
824 * NOTE: On 1610 the END_OF_CMD may come too early when
825 * starting a write
826 */
827 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
828 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
829 end_command = 1;
830 }
831 }
832
833 if (cmd_error && host->data) {
834 del_timer(&host->cmd_abort_timer);
835 host->abort = 1;
836 OMAP_MMC_WRITE(host, IE, 0);
837 disable_irq_nosync(host->irq);
838 queue_work(host->mmc_omap_wq, &host->cmd_abort_work);
839 return IRQ_HANDLED;
840 }
841
842 if (end_command && host->cmd)
843 mmc_omap_cmd_done(host, host->cmd);
844 if (host->data != NULL) {
845 if (transfer_error)
846 mmc_omap_xfer_done(host, host->data);
847 else if (end_transfer)
848 mmc_omap_end_of_data(host, host->data);
849 }
850
851 return IRQ_HANDLED;
852 }
853
854 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed)
855 {
856 int cover_open;
857 struct mmc_omap_host *host = dev_get_drvdata(dev);
858 struct mmc_omap_slot *slot = host->slots[num];
859
860 BUG_ON(num >= host->nr_slots);
861
862 /* Other subsystems can call in here before we're initialised. */
863 if (host->nr_slots == 0 || !host->slots[num])
864 return;
865
866 cover_open = mmc_omap_cover_is_open(slot);
867 if (cover_open != slot->cover_open) {
868 slot->cover_open = cover_open;
869 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
870 }
871
872 tasklet_hi_schedule(&slot->cover_tasklet);
873 }
874
875 static void mmc_omap_cover_timer(unsigned long arg)
876 {
877 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
878 tasklet_schedule(&slot->cover_tasklet);
879 }
880
881 static void mmc_omap_cover_handler(unsigned long param)
882 {
883 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param;
884 int cover_open = mmc_omap_cover_is_open(slot);
885
886 mmc_detect_change(slot->mmc, 0);
887 if (!cover_open)
888 return;
889
890 /*
891 * If no card is inserted, we postpone polling until
892 * the cover has been closed.
893 */
894 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card))
895 return;
896
897 mod_timer(&slot->cover_timer,
898 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY));
899 }
900
901 static void mmc_omap_dma_callback(void *priv)
902 {
903 struct mmc_omap_host *host = priv;
904 struct mmc_data *data = host->data;
905
906 /* If we got to the end of DMA, assume everything went well */
907 data->bytes_xfered += data->blocks * data->blksz;
908
909 mmc_omap_dma_done(host, data);
910 }
911
912 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
913 {
914 u16 reg;
915
916 reg = OMAP_MMC_READ(host, SDIO);
917 reg &= ~(1 << 5);
918 OMAP_MMC_WRITE(host, SDIO, reg);
919 /* Set maximum timeout */
920 OMAP_MMC_WRITE(host, CTO, 0xff);
921 }
922
923 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
924 {
925 unsigned int timeout, cycle_ns;
926 u16 reg;
927
928 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
929 timeout = req->data->timeout_ns / cycle_ns;
930 timeout += req->data->timeout_clks;
931
932 /* Check if we need to use timeout multiplier register */
933 reg = OMAP_MMC_READ(host, SDIO);
934 if (timeout > 0xffff) {
935 reg |= (1 << 5);
936 timeout /= 1024;
937 } else
938 reg &= ~(1 << 5);
939 OMAP_MMC_WRITE(host, SDIO, reg);
940 OMAP_MMC_WRITE(host, DTO, timeout);
941 }
942
943 static void
944 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
945 {
946 struct mmc_data *data = req->data;
947 int i, use_dma, block_size;
948 unsigned sg_len;
949
950 host->data = data;
951 if (data == NULL) {
952 OMAP_MMC_WRITE(host, BLEN, 0);
953 OMAP_MMC_WRITE(host, NBLK, 0);
954 OMAP_MMC_WRITE(host, BUF, 0);
955 host->dma_in_use = 0;
956 set_cmd_timeout(host, req);
957 return;
958 }
959
960 block_size = data->blksz;
961
962 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
963 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
964 set_data_timeout(host, req);
965
966 /* cope with calling layer confusion; it issues "single
967 * block" writes using multi-block scatterlists.
968 */
969 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
970
971 /* Only do DMA for entire blocks */
972 use_dma = host->use_dma;
973 if (use_dma) {
974 for (i = 0; i < sg_len; i++) {
975 if ((data->sg[i].length % block_size) != 0) {
976 use_dma = 0;
977 break;
978 }
979 }
980 }
981
982 host->sg_idx = 0;
983 if (use_dma) {
984 enum dma_data_direction dma_data_dir;
985 struct dma_async_tx_descriptor *tx;
986 struct dma_chan *c;
987 u32 burst, *bp;
988 u16 buf;
989
990 /*
991 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
992 * and 24xx. Use 16 or 32 word frames when the
993 * blocksize is at least that large. Blocksize is
994 * usually 512 bytes; but not for some SD reads.
995 */
996 burst = mmc_omap15xx() ? 32 : 64;
997 if (burst > data->blksz)
998 burst = data->blksz;
999
1000 burst >>= 1;
1001
1002 if (data->flags & MMC_DATA_WRITE) {
1003 c = host->dma_tx;
1004 bp = &host->dma_tx_burst;
1005 buf = 0x0f80 | (burst - 1) << 0;
1006 dma_data_dir = DMA_TO_DEVICE;
1007 } else {
1008 c = host->dma_rx;
1009 bp = &host->dma_rx_burst;
1010 buf = 0x800f | (burst - 1) << 8;
1011 dma_data_dir = DMA_FROM_DEVICE;
1012 }
1013
1014 if (!c)
1015 goto use_pio;
1016
1017 /* Only reconfigure if we have a different burst size */
1018 if (*bp != burst) {
1019 struct dma_slave_config cfg;
1020
1021 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1022 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA);
1023 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1024 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1025 cfg.src_maxburst = burst;
1026 cfg.dst_maxburst = burst;
1027
1028 if (dmaengine_slave_config(c, &cfg))
1029 goto use_pio;
1030
1031 *bp = burst;
1032 }
1033
1034 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len,
1035 dma_data_dir);
1036 if (host->sg_len == 0)
1037 goto use_pio;
1038
1039 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len,
1040 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1042 if (!tx)
1043 goto use_pio;
1044
1045 OMAP_MMC_WRITE(host, BUF, buf);
1046
1047 tx->callback = mmc_omap_dma_callback;
1048 tx->callback_param = host;
1049 dmaengine_submit(tx);
1050 host->brs_received = 0;
1051 host->dma_done = 0;
1052 host->dma_in_use = 1;
1053 return;
1054 }
1055 use_pio:
1056
1057 /* Revert to PIO? */
1058 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1059 host->total_bytes_left = data->blocks * block_size;
1060 host->sg_len = sg_len;
1061 mmc_omap_sg_to_buf(host);
1062 host->dma_in_use = 0;
1063 }
1064
1065 static void mmc_omap_start_request(struct mmc_omap_host *host,
1066 struct mmc_request *req)
1067 {
1068 BUG_ON(host->mrq != NULL);
1069
1070 host->mrq = req;
1071
1072 /* only touch fifo AFTER the controller readies it */
1073 mmc_omap_prepare_data(host, req);
1074 mmc_omap_start_command(host, req->cmd);
1075 if (host->dma_in_use) {
1076 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ?
1077 host->dma_tx : host->dma_rx;
1078
1079 dma_async_issue_pending(c);
1080 }
1081 }
1082
1083 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1084 {
1085 struct mmc_omap_slot *slot = mmc_priv(mmc);
1086 struct mmc_omap_host *host = slot->host;
1087 unsigned long flags;
1088
1089 spin_lock_irqsave(&host->slot_lock, flags);
1090 if (host->mmc != NULL) {
1091 BUG_ON(slot->mrq != NULL);
1092 slot->mrq = req;
1093 spin_unlock_irqrestore(&host->slot_lock, flags);
1094 return;
1095 } else
1096 host->mmc = mmc;
1097 spin_unlock_irqrestore(&host->slot_lock, flags);
1098 mmc_omap_select_slot(slot, 1);
1099 mmc_omap_start_request(host, req);
1100 }
1101
1102 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1103 int vdd)
1104 {
1105 struct mmc_omap_host *host;
1106
1107 host = slot->host;
1108
1109 if (slot->pdata->set_power != NULL)
1110 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1111 vdd);
1112 if (mmc_omap2()) {
1113 u16 w;
1114
1115 if (power_on) {
1116 w = OMAP_MMC_READ(host, CON);
1117 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1118 } else {
1119 w = OMAP_MMC_READ(host, CON);
1120 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1121 }
1122 }
1123 }
1124
1125 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1126 {
1127 struct mmc_omap_slot *slot = mmc_priv(mmc);
1128 struct mmc_omap_host *host = slot->host;
1129 int func_clk_rate = clk_get_rate(host->fclk);
1130 int dsor;
1131
1132 if (ios->clock == 0)
1133 return 0;
1134
1135 dsor = func_clk_rate / ios->clock;
1136 if (dsor < 1)
1137 dsor = 1;
1138
1139 if (func_clk_rate / dsor > ios->clock)
1140 dsor++;
1141
1142 if (dsor > 250)
1143 dsor = 250;
1144
1145 slot->fclk_freq = func_clk_rate / dsor;
1146
1147 if (ios->bus_width == MMC_BUS_WIDTH_4)
1148 dsor |= 1 << 15;
1149
1150 return dsor;
1151 }
1152
1153 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1154 {
1155 struct mmc_omap_slot *slot = mmc_priv(mmc);
1156 struct mmc_omap_host *host = slot->host;
1157 int i, dsor;
1158 int clk_enabled;
1159
1160 mmc_omap_select_slot(slot, 0);
1161
1162 dsor = mmc_omap_calc_divisor(mmc, ios);
1163
1164 if (ios->vdd != slot->vdd)
1165 slot->vdd = ios->vdd;
1166
1167 clk_enabled = 0;
1168 switch (ios->power_mode) {
1169 case MMC_POWER_OFF:
1170 mmc_omap_set_power(slot, 0, ios->vdd);
1171 break;
1172 case MMC_POWER_UP:
1173 /* Cannot touch dsor yet, just power up MMC */
1174 mmc_omap_set_power(slot, 1, ios->vdd);
1175 goto exit;
1176 case MMC_POWER_ON:
1177 mmc_omap_fclk_enable(host, 1);
1178 clk_enabled = 1;
1179 dsor |= 1 << 11;
1180 break;
1181 }
1182
1183 if (slot->bus_mode != ios->bus_mode) {
1184 if (slot->pdata->set_bus_mode != NULL)
1185 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1186 ios->bus_mode);
1187 slot->bus_mode = ios->bus_mode;
1188 }
1189
1190 /* On insanely high arm_per frequencies something sometimes
1191 * goes somehow out of sync, and the POW bit is not being set,
1192 * which results in the while loop below getting stuck.
1193 * Writing to the CON register twice seems to do the trick. */
1194 for (i = 0; i < 2; i++)
1195 OMAP_MMC_WRITE(host, CON, dsor);
1196 slot->saved_con = dsor;
1197 if (ios->power_mode == MMC_POWER_ON) {
1198 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1199 int usecs = 250;
1200
1201 /* Send clock cycles, poll completion */
1202 OMAP_MMC_WRITE(host, IE, 0);
1203 OMAP_MMC_WRITE(host, STAT, 0xffff);
1204 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1205 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
1206 udelay(1);
1207 usecs--;
1208 }
1209 OMAP_MMC_WRITE(host, STAT, 1);
1210 }
1211
1212 exit:
1213 mmc_omap_release_slot(slot, clk_enabled);
1214 }
1215
1216 static const struct mmc_host_ops mmc_omap_ops = {
1217 .request = mmc_omap_request,
1218 .set_ios = mmc_omap_set_ios,
1219 };
1220
1221 static int mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1222 {
1223 struct mmc_omap_slot *slot = NULL;
1224 struct mmc_host *mmc;
1225 int r;
1226
1227 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1228 if (mmc == NULL)
1229 return -ENOMEM;
1230
1231 slot = mmc_priv(mmc);
1232 slot->host = host;
1233 slot->mmc = mmc;
1234 slot->id = id;
1235 slot->pdata = &host->pdata->slots[id];
1236
1237 host->slots[id] = slot;
1238
1239 mmc->caps = 0;
1240 if (host->pdata->slots[id].wires >= 4)
1241 mmc->caps |= MMC_CAP_4_BIT_DATA;
1242
1243 mmc->ops = &mmc_omap_ops;
1244 mmc->f_min = 400000;
1245
1246 if (mmc_omap2())
1247 mmc->f_max = 48000000;
1248 else
1249 mmc->f_max = 24000000;
1250 if (host->pdata->max_freq)
1251 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1252 mmc->ocr_avail = slot->pdata->ocr_mask;
1253
1254 /* Use scatterlist DMA to reduce per-transfer costs.
1255 * NOTE max_seg_size assumption that small blocks aren't
1256 * normally used (except e.g. for reading SD registers).
1257 */
1258 mmc->max_segs = 32;
1259 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1260 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1261 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1262 mmc->max_seg_size = mmc->max_req_size;
1263
1264 r = mmc_add_host(mmc);
1265 if (r < 0)
1266 goto err_remove_host;
1267
1268 if (slot->pdata->name != NULL) {
1269 r = device_create_file(&mmc->class_dev,
1270 &dev_attr_slot_name);
1271 if (r < 0)
1272 goto err_remove_host;
1273 }
1274
1275 if (slot->pdata->get_cover_state != NULL) {
1276 r = device_create_file(&mmc->class_dev,
1277 &dev_attr_cover_switch);
1278 if (r < 0)
1279 goto err_remove_slot_name;
1280
1281 setup_timer(&slot->cover_timer, mmc_omap_cover_timer,
1282 (unsigned long)slot);
1283 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler,
1284 (unsigned long)slot);
1285 tasklet_schedule(&slot->cover_tasklet);
1286 }
1287
1288 return 0;
1289
1290 err_remove_slot_name:
1291 if (slot->pdata->name != NULL)
1292 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1293 err_remove_host:
1294 mmc_remove_host(mmc);
1295 mmc_free_host(mmc);
1296 return r;
1297 }
1298
1299 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1300 {
1301 struct mmc_host *mmc = slot->mmc;
1302
1303 if (slot->pdata->name != NULL)
1304 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1305 if (slot->pdata->get_cover_state != NULL)
1306 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1307
1308 tasklet_kill(&slot->cover_tasklet);
1309 del_timer_sync(&slot->cover_timer);
1310 flush_workqueue(slot->host->mmc_omap_wq);
1311
1312 mmc_remove_host(mmc);
1313 mmc_free_host(mmc);
1314 }
1315
1316 static int mmc_omap_probe(struct platform_device *pdev)
1317 {
1318 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1319 struct mmc_omap_host *host = NULL;
1320 struct resource *res;
1321 dma_cap_mask_t mask;
1322 unsigned sig = 0;
1323 int i, ret = 0;
1324 int irq;
1325
1326 if (pdata == NULL) {
1327 dev_err(&pdev->dev, "platform data missing\n");
1328 return -ENXIO;
1329 }
1330 if (pdata->nr_slots == 0) {
1331 dev_err(&pdev->dev, "no slots\n");
1332 return -ENXIO;
1333 }
1334
1335 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1336 irq = platform_get_irq(pdev, 0);
1337 if (res == NULL || irq < 0)
1338 return -ENXIO;
1339
1340 res = request_mem_region(res->start, resource_size(res),
1341 pdev->name);
1342 if (res == NULL)
1343 return -EBUSY;
1344
1345 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1346 if (host == NULL) {
1347 ret = -ENOMEM;
1348 goto err_free_mem_region;
1349 }
1350
1351 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work);
1352 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work);
1353
1354 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command);
1355 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer,
1356 (unsigned long) host);
1357
1358 spin_lock_init(&host->clk_lock);
1359 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host);
1360
1361 spin_lock_init(&host->dma_lock);
1362 spin_lock_init(&host->slot_lock);
1363 init_waitqueue_head(&host->slot_wq);
1364
1365 host->pdata = pdata;
1366 host->features = host->pdata->slots[0].features;
1367 host->dev = &pdev->dev;
1368 platform_set_drvdata(pdev, host);
1369
1370 host->id = pdev->id;
1371 host->mem_res = res;
1372 host->irq = irq;
1373 host->use_dma = 1;
1374 host->irq = irq;
1375 host->phys_base = host->mem_res->start;
1376 host->virt_base = ioremap(res->start, resource_size(res));
1377 if (!host->virt_base)
1378 goto err_ioremap;
1379
1380 host->iclk = clk_get(&pdev->dev, "ick");
1381 if (IS_ERR(host->iclk)) {
1382 ret = PTR_ERR(host->iclk);
1383 goto err_free_mmc_host;
1384 }
1385 clk_enable(host->iclk);
1386
1387 host->fclk = clk_get(&pdev->dev, "fck");
1388 if (IS_ERR(host->fclk)) {
1389 ret = PTR_ERR(host->fclk);
1390 goto err_free_iclk;
1391 }
1392
1393 dma_cap_zero(mask);
1394 dma_cap_set(DMA_SLAVE, mask);
1395
1396 host->dma_tx_burst = -1;
1397 host->dma_rx_burst = -1;
1398
1399 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1400 if (res)
1401 sig = res->start;
1402 host->dma_tx = dma_request_slave_channel_compat(mask,
1403 omap_dma_filter_fn, &sig, &pdev->dev, "tx");
1404 if (!host->dma_tx)
1405 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n",
1406 sig);
1407
1408 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1409 if (res)
1410 sig = res->start;
1411 host->dma_rx = dma_request_slave_channel_compat(mask,
1412 omap_dma_filter_fn, &sig, &pdev->dev, "rx");
1413 if (!host->dma_rx)
1414 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n",
1415 sig);
1416
1417 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1418 if (ret)
1419 goto err_free_dma;
1420
1421 if (pdata->init != NULL) {
1422 ret = pdata->init(&pdev->dev);
1423 if (ret < 0)
1424 goto err_free_irq;
1425 }
1426
1427 host->nr_slots = pdata->nr_slots;
1428 host->reg_shift = (mmc_omap7xx() ? 1 : 2);
1429
1430 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0);
1431 if (!host->mmc_omap_wq)
1432 goto err_plat_cleanup;
1433
1434 for (i = 0; i < pdata->nr_slots; i++) {
1435 ret = mmc_omap_new_slot(host, i);
1436 if (ret < 0) {
1437 while (--i >= 0)
1438 mmc_omap_remove_slot(host->slots[i]);
1439
1440 goto err_destroy_wq;
1441 }
1442 }
1443
1444 return 0;
1445
1446 err_destroy_wq:
1447 destroy_workqueue(host->mmc_omap_wq);
1448 err_plat_cleanup:
1449 if (pdata->cleanup)
1450 pdata->cleanup(&pdev->dev);
1451 err_free_irq:
1452 free_irq(host->irq, host);
1453 err_free_dma:
1454 if (host->dma_tx)
1455 dma_release_channel(host->dma_tx);
1456 if (host->dma_rx)
1457 dma_release_channel(host->dma_rx);
1458 clk_put(host->fclk);
1459 err_free_iclk:
1460 clk_disable(host->iclk);
1461 clk_put(host->iclk);
1462 err_free_mmc_host:
1463 iounmap(host->virt_base);
1464 err_ioremap:
1465 kfree(host);
1466 err_free_mem_region:
1467 release_mem_region(res->start, resource_size(res));
1468 return ret;
1469 }
1470
1471 static int mmc_omap_remove(struct platform_device *pdev)
1472 {
1473 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1474 int i;
1475
1476 BUG_ON(host == NULL);
1477
1478 for (i = 0; i < host->nr_slots; i++)
1479 mmc_omap_remove_slot(host->slots[i]);
1480
1481 if (host->pdata->cleanup)
1482 host->pdata->cleanup(&pdev->dev);
1483
1484 mmc_omap_fclk_enable(host, 0);
1485 free_irq(host->irq, host);
1486 clk_put(host->fclk);
1487 clk_disable(host->iclk);
1488 clk_put(host->iclk);
1489
1490 if (host->dma_tx)
1491 dma_release_channel(host->dma_tx);
1492 if (host->dma_rx)
1493 dma_release_channel(host->dma_rx);
1494
1495 iounmap(host->virt_base);
1496 release_mem_region(pdev->resource[0].start,
1497 pdev->resource[0].end - pdev->resource[0].start + 1);
1498 destroy_workqueue(host->mmc_omap_wq);
1499
1500 kfree(host);
1501
1502 return 0;
1503 }
1504
1505 static struct platform_driver mmc_omap_driver = {
1506 .probe = mmc_omap_probe,
1507 .remove = mmc_omap_remove,
1508 .driver = {
1509 .name = DRIVER_NAME,
1510 .owner = THIS_MODULE,
1511 },
1512 };
1513
1514 module_platform_driver(mmc_omap_driver);
1515 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1516 MODULE_LICENSE("GPL");
1517 MODULE_ALIAS("platform:" DRIVER_NAME);
1518 MODULE_AUTHOR("Juha Yrjölä");
Ubuntu Artful kernel mirror