2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dmaengine.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/delay.h>
23 #include <linux/spinlock.h>
24 #include <linux/timer.h>
25 #include <linux/omap-dma.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/card.h>
28 #include <linux/clk.h>
29 #include <linux/scatterlist.h>
30 #include <linux/slab.h>
31 #include <linux/platform_data/mmc-omap.h>
34 #define OMAP_MMC_REG_CMD 0x00
35 #define OMAP_MMC_REG_ARGL 0x01
36 #define OMAP_MMC_REG_ARGH 0x02
37 #define OMAP_MMC_REG_CON 0x03
38 #define OMAP_MMC_REG_STAT 0x04
39 #define OMAP_MMC_REG_IE 0x05
40 #define OMAP_MMC_REG_CTO 0x06
41 #define OMAP_MMC_REG_DTO 0x07
42 #define OMAP_MMC_REG_DATA 0x08
43 #define OMAP_MMC_REG_BLEN 0x09
44 #define OMAP_MMC_REG_NBLK 0x0a
45 #define OMAP_MMC_REG_BUF 0x0b
46 #define OMAP_MMC_REG_SDIO 0x0d
47 #define OMAP_MMC_REG_REV 0x0f
48 #define OMAP_MMC_REG_RSP0 0x10
49 #define OMAP_MMC_REG_RSP1 0x11
50 #define OMAP_MMC_REG_RSP2 0x12
51 #define OMAP_MMC_REG_RSP3 0x13
52 #define OMAP_MMC_REG_RSP4 0x14
53 #define OMAP_MMC_REG_RSP5 0x15
54 #define OMAP_MMC_REG_RSP6 0x16
55 #define OMAP_MMC_REG_RSP7 0x17
56 #define OMAP_MMC_REG_IOSR 0x18
57 #define OMAP_MMC_REG_SYSC 0x19
58 #define OMAP_MMC_REG_SYSS 0x1a
60 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
61 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
62 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
63 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
64 #define OMAP_MMC_STAT_A_FULL (1 << 10)
65 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
66 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
67 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
68 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
69 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
70 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
71 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
72 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
74 #define mmc_omap7xx() (host->features & MMC_OMAP7XX)
75 #define mmc_omap15xx() (host->features & MMC_OMAP15XX)
76 #define mmc_omap16xx() (host->features & MMC_OMAP16XX)
77 #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX)
78 #define mmc_omap1() (host->features & MMC_OMAP1_MASK)
79 #define mmc_omap2() (!mmc_omap1())
81 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift)
82 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg))
83 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg))
88 #define OMAP_MMC_CMDTYPE_BC 0
89 #define OMAP_MMC_CMDTYPE_BCR 1
90 #define OMAP_MMC_CMDTYPE_AC 2
91 #define OMAP_MMC_CMDTYPE_ADTC 3
93 #define OMAP_DMA_MMC_TX 21
94 #define OMAP_DMA_MMC_RX 22
95 #define OMAP_DMA_MMC2_TX 54
96 #define OMAP_DMA_MMC2_RX 55
98 #define OMAP24XX_DMA_MMC2_TX 47
99 #define OMAP24XX_DMA_MMC2_RX 48
100 #define OMAP24XX_DMA_MMC1_TX 61
101 #define OMAP24XX_DMA_MMC1_RX 62
104 #define DRIVER_NAME "mmci-omap"
106 /* Specifies how often in millisecs to poll for card status changes
107 * when the cover switch is open */
108 #define OMAP_MMC_COVER_POLL_DELAY 500
110 struct mmc_omap_host
;
112 struct mmc_omap_slot
{
117 unsigned int fclk_freq
;
119 struct tasklet_struct cover_tasklet
;
120 struct timer_list cover_timer
;
123 struct mmc_request
*mrq
;
124 struct mmc_omap_host
*host
;
125 struct mmc_host
*mmc
;
126 struct omap_mmc_slot_data
*pdata
;
129 struct mmc_omap_host
{
131 struct mmc_request
* mrq
;
132 struct mmc_command
* cmd
;
133 struct mmc_data
* data
;
134 struct mmc_host
* mmc
;
136 unsigned char id
; /* 16xx chips have 2 MMC blocks */
139 struct dma_chan
*dma_rx
;
141 struct dma_chan
*dma_tx
;
143 struct resource
*mem_res
;
144 void __iomem
*virt_base
;
145 unsigned int phys_base
;
147 unsigned char bus_mode
;
148 unsigned int reg_shift
;
150 struct work_struct cmd_abort_work
;
152 struct timer_list cmd_abort_timer
;
154 struct work_struct slot_release_work
;
155 struct mmc_omap_slot
*next_slot
;
156 struct work_struct send_stop_work
;
157 struct mmc_data
*stop_data
;
162 u32 buffer_bytes_left
;
163 u32 total_bytes_left
;
167 unsigned brs_received
:1, dma_done
:1;
168 unsigned dma_in_use
:1;
171 struct mmc_omap_slot
*slots
[OMAP_MMC_MAX_SLOTS
];
172 struct mmc_omap_slot
*current_slot
;
173 spinlock_t slot_lock
;
174 wait_queue_head_t slot_wq
;
177 struct timer_list clk_timer
;
178 spinlock_t clk_lock
; /* for changing enabled state */
179 unsigned int fclk_enabled
:1;
180 struct workqueue_struct
*mmc_omap_wq
;
182 struct omap_mmc_platform_data
*pdata
;
186 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot
*slot
)
188 unsigned long tick_ns
;
190 if (slot
!= NULL
&& slot
->host
->fclk_enabled
&& slot
->fclk_freq
> 0) {
191 tick_ns
= (1000000000 + slot
->fclk_freq
- 1) / slot
->fclk_freq
;
196 static void mmc_omap_fclk_enable(struct mmc_omap_host
*host
, unsigned int enable
)
200 spin_lock_irqsave(&host
->clk_lock
, flags
);
201 if (host
->fclk_enabled
!= enable
) {
202 host
->fclk_enabled
= enable
;
204 clk_enable(host
->fclk
);
206 clk_disable(host
->fclk
);
208 spin_unlock_irqrestore(&host
->clk_lock
, flags
);
211 static void mmc_omap_select_slot(struct mmc_omap_slot
*slot
, int claimed
)
213 struct mmc_omap_host
*host
= slot
->host
;
218 spin_lock_irqsave(&host
->slot_lock
, flags
);
219 while (host
->mmc
!= NULL
) {
220 spin_unlock_irqrestore(&host
->slot_lock
, flags
);
221 wait_event(host
->slot_wq
, host
->mmc
== NULL
);
222 spin_lock_irqsave(&host
->slot_lock
, flags
);
224 host
->mmc
= slot
->mmc
;
225 spin_unlock_irqrestore(&host
->slot_lock
, flags
);
227 del_timer(&host
->clk_timer
);
228 if (host
->current_slot
!= slot
|| !claimed
)
229 mmc_omap_fclk_offdelay(host
->current_slot
);
231 if (host
->current_slot
!= slot
) {
232 OMAP_MMC_WRITE(host
, CON
, slot
->saved_con
& 0xFC00);
233 if (host
->pdata
->switch_slot
!= NULL
)
234 host
->pdata
->switch_slot(mmc_dev(slot
->mmc
), slot
->id
);
235 host
->current_slot
= slot
;
239 mmc_omap_fclk_enable(host
, 1);
241 /* Doing the dummy read here seems to work around some bug
242 * at least in OMAP24xx silicon where the command would not
243 * start after writing the CMD register. Sigh. */
244 OMAP_MMC_READ(host
, CON
);
246 OMAP_MMC_WRITE(host
, CON
, slot
->saved_con
);
248 mmc_omap_fclk_enable(host
, 0);
251 static void mmc_omap_start_request(struct mmc_omap_host
*host
,
252 struct mmc_request
*req
);
254 static void mmc_omap_slot_release_work(struct work_struct
*work
)
256 struct mmc_omap_host
*host
= container_of(work
, struct mmc_omap_host
,
258 struct mmc_omap_slot
*next_slot
= host
->next_slot
;
259 struct mmc_request
*rq
;
261 host
->next_slot
= NULL
;
262 mmc_omap_select_slot(next_slot
, 1);
265 next_slot
->mrq
= NULL
;
266 mmc_omap_start_request(host
, rq
);
269 static void mmc_omap_release_slot(struct mmc_omap_slot
*slot
, int clk_enabled
)
271 struct mmc_omap_host
*host
= slot
->host
;
275 BUG_ON(slot
== NULL
|| host
->mmc
== NULL
);
278 /* Keeps clock running for at least 8 cycles on valid freq */
279 mod_timer(&host
->clk_timer
, jiffies
+ HZ
/10);
281 del_timer(&host
->clk_timer
);
282 mmc_omap_fclk_offdelay(slot
);
283 mmc_omap_fclk_enable(host
, 0);
286 spin_lock_irqsave(&host
->slot_lock
, flags
);
287 /* Check for any pending requests */
288 for (i
= 0; i
< host
->nr_slots
; i
++) {
289 struct mmc_omap_slot
*new_slot
;
291 if (host
->slots
[i
] == NULL
|| host
->slots
[i
]->mrq
== NULL
)
294 BUG_ON(host
->next_slot
!= NULL
);
295 new_slot
= host
->slots
[i
];
296 /* The current slot should not have a request in queue */
297 BUG_ON(new_slot
== host
->current_slot
);
299 host
->next_slot
= new_slot
;
300 host
->mmc
= new_slot
->mmc
;
301 spin_unlock_irqrestore(&host
->slot_lock
, flags
);
302 queue_work(host
->mmc_omap_wq
, &host
->slot_release_work
);
307 wake_up(&host
->slot_wq
);
308 spin_unlock_irqrestore(&host
->slot_lock
, flags
);
312 int mmc_omap_cover_is_open(struct mmc_omap_slot
*slot
)
314 if (slot
->pdata
->get_cover_state
)
315 return slot
->pdata
->get_cover_state(mmc_dev(slot
->mmc
),
321 mmc_omap_show_cover_switch(struct device
*dev
, struct device_attribute
*attr
,
324 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
325 struct mmc_omap_slot
*slot
= mmc_priv(mmc
);
327 return sprintf(buf
, "%s\n", mmc_omap_cover_is_open(slot
) ? "open" :
331 static DEVICE_ATTR(cover_switch
, S_IRUGO
, mmc_omap_show_cover_switch
, NULL
);
334 mmc_omap_show_slot_name(struct device
*dev
, struct device_attribute
*attr
,
337 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
338 struct mmc_omap_slot
*slot
= mmc_priv(mmc
);
340 return sprintf(buf
, "%s\n", slot
->pdata
->name
);
343 static DEVICE_ATTR(slot_name
, S_IRUGO
, mmc_omap_show_slot_name
, NULL
);
346 mmc_omap_start_command(struct mmc_omap_host
*host
, struct mmc_command
*cmd
)
357 /* Our hardware needs to know exact type */
358 switch (mmc_resp_type(cmd
)) {
363 /* resp 1, 1b, 6, 7 */
373 dev_err(mmc_dev(host
->mmc
), "Invalid response type: %04x\n", mmc_resp_type(cmd
));
377 if (mmc_cmd_type(cmd
) == MMC_CMD_ADTC
) {
378 cmdtype
= OMAP_MMC_CMDTYPE_ADTC
;
379 } else if (mmc_cmd_type(cmd
) == MMC_CMD_BC
) {
380 cmdtype
= OMAP_MMC_CMDTYPE_BC
;
381 } else if (mmc_cmd_type(cmd
) == MMC_CMD_BCR
) {
382 cmdtype
= OMAP_MMC_CMDTYPE_BCR
;
384 cmdtype
= OMAP_MMC_CMDTYPE_AC
;
387 cmdreg
= cmd
->opcode
| (resptype
<< 8) | (cmdtype
<< 12);
389 if (host
->current_slot
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
392 if (cmd
->flags
& MMC_RSP_BUSY
)
395 if (host
->data
&& !(host
->data
->flags
& MMC_DATA_WRITE
))
398 mod_timer(&host
->cmd_abort_timer
, jiffies
+ HZ
/2);
400 OMAP_MMC_WRITE(host
, CTO
, 200);
401 OMAP_MMC_WRITE(host
, ARGL
, cmd
->arg
& 0xffff);
402 OMAP_MMC_WRITE(host
, ARGH
, cmd
->arg
>> 16);
403 OMAP_MMC_WRITE(host
, IE
,
404 OMAP_MMC_STAT_A_EMPTY
| OMAP_MMC_STAT_A_FULL
|
405 OMAP_MMC_STAT_CMD_CRC
| OMAP_MMC_STAT_CMD_TOUT
|
406 OMAP_MMC_STAT_DATA_CRC
| OMAP_MMC_STAT_DATA_TOUT
|
407 OMAP_MMC_STAT_END_OF_CMD
| OMAP_MMC_STAT_CARD_ERR
|
408 OMAP_MMC_STAT_END_OF_DATA
);
409 OMAP_MMC_WRITE(host
, CMD
, cmdreg
);
413 mmc_omap_release_dma(struct mmc_omap_host
*host
, struct mmc_data
*data
,
416 enum dma_data_direction dma_data_dir
;
417 struct device
*dev
= mmc_dev(host
->mmc
);
420 if (data
->flags
& MMC_DATA_WRITE
) {
421 dma_data_dir
= DMA_TO_DEVICE
;
424 dma_data_dir
= DMA_FROM_DEVICE
;
429 dmaengine_terminate_all(c
);
430 /* Claim nothing transferred on error... */
431 data
->bytes_xfered
= 0;
433 dev
= c
->device
->dev
;
435 dma_unmap_sg(dev
, data
->sg
, host
->sg_len
, dma_data_dir
);
438 static void mmc_omap_send_stop_work(struct work_struct
*work
)
440 struct mmc_omap_host
*host
= container_of(work
, struct mmc_omap_host
,
442 struct mmc_omap_slot
*slot
= host
->current_slot
;
443 struct mmc_data
*data
= host
->stop_data
;
444 unsigned long tick_ns
;
446 tick_ns
= (1000000000 + slot
->fclk_freq
- 1)/slot
->fclk_freq
;
449 mmc_omap_start_command(host
, data
->stop
);
453 mmc_omap_xfer_done(struct mmc_omap_host
*host
, struct mmc_data
*data
)
455 if (host
->dma_in_use
)
456 mmc_omap_release_dma(host
, data
, data
->error
);
461 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
462 * dozens of requests until the card finishes writing data.
463 * It'd be cheaper to just wait till an EOFB interrupt arrives...
467 struct mmc_host
*mmc
;
471 mmc_omap_release_slot(host
->current_slot
, 1);
472 mmc_request_done(mmc
, data
->mrq
);
476 host
->stop_data
= data
;
477 queue_work(host
->mmc_omap_wq
, &host
->send_stop_work
);
481 mmc_omap_send_abort(struct mmc_omap_host
*host
, int maxloops
)
483 struct mmc_omap_slot
*slot
= host
->current_slot
;
484 unsigned int restarts
, passes
, timeout
;
487 /* Sending abort takes 80 clocks. Have some extra and round up */
488 timeout
= (120*1000000 + slot
->fclk_freq
- 1)/slot
->fclk_freq
;
490 while (restarts
< maxloops
) {
491 OMAP_MMC_WRITE(host
, STAT
, 0xFFFF);
492 OMAP_MMC_WRITE(host
, CMD
, (3 << 12) | (1 << 7));
495 while (passes
< timeout
) {
496 stat
= OMAP_MMC_READ(host
, STAT
);
497 if (stat
& OMAP_MMC_STAT_END_OF_CMD
)
506 OMAP_MMC_WRITE(host
, STAT
, stat
);
510 mmc_omap_abort_xfer(struct mmc_omap_host
*host
, struct mmc_data
*data
)
512 if (host
->dma_in_use
)
513 mmc_omap_release_dma(host
, data
, 1);
518 mmc_omap_send_abort(host
, 10000);
522 mmc_omap_end_of_data(struct mmc_omap_host
*host
, struct mmc_data
*data
)
527 if (!host
->dma_in_use
) {
528 mmc_omap_xfer_done(host
, data
);
532 spin_lock_irqsave(&host
->dma_lock
, flags
);
536 host
->brs_received
= 1;
537 spin_unlock_irqrestore(&host
->dma_lock
, flags
);
539 mmc_omap_xfer_done(host
, data
);
543 mmc_omap_dma_done(struct mmc_omap_host
*host
, struct mmc_data
*data
)
549 spin_lock_irqsave(&host
->dma_lock
, flags
);
550 if (host
->brs_received
)
554 spin_unlock_irqrestore(&host
->dma_lock
, flags
);
556 mmc_omap_xfer_done(host
, data
);
560 mmc_omap_cmd_done(struct mmc_omap_host
*host
, struct mmc_command
*cmd
)
564 del_timer(&host
->cmd_abort_timer
);
566 if (cmd
->flags
& MMC_RSP_PRESENT
) {
567 if (cmd
->flags
& MMC_RSP_136
) {
568 /* response type 2 */
570 OMAP_MMC_READ(host
, RSP0
) |
571 (OMAP_MMC_READ(host
, RSP1
) << 16);
573 OMAP_MMC_READ(host
, RSP2
) |
574 (OMAP_MMC_READ(host
, RSP3
) << 16);
576 OMAP_MMC_READ(host
, RSP4
) |
577 (OMAP_MMC_READ(host
, RSP5
) << 16);
579 OMAP_MMC_READ(host
, RSP6
) |
580 (OMAP_MMC_READ(host
, RSP7
) << 16);
582 /* response types 1, 1b, 3, 4, 5, 6 */
584 OMAP_MMC_READ(host
, RSP6
) |
585 (OMAP_MMC_READ(host
, RSP7
) << 16);
589 if (host
->data
== NULL
|| cmd
->error
) {
590 struct mmc_host
*mmc
;
592 if (host
->data
!= NULL
)
593 mmc_omap_abort_xfer(host
, host
->data
);
596 mmc_omap_release_slot(host
->current_slot
, 1);
597 mmc_request_done(mmc
, cmd
->mrq
);
602 * Abort stuck command. Can occur when card is removed while it is being
605 static void mmc_omap_abort_command(struct work_struct
*work
)
607 struct mmc_omap_host
*host
= container_of(work
, struct mmc_omap_host
,
611 dev_dbg(mmc_dev(host
->mmc
), "Aborting stuck command CMD%d\n",
614 if (host
->cmd
->error
== 0)
615 host
->cmd
->error
= -ETIMEDOUT
;
617 if (host
->data
== NULL
) {
618 struct mmc_command
*cmd
;
619 struct mmc_host
*mmc
;
623 mmc_omap_send_abort(host
, 10000);
627 mmc_omap_release_slot(host
->current_slot
, 1);
628 mmc_request_done(mmc
, cmd
->mrq
);
630 mmc_omap_cmd_done(host
, host
->cmd
);
633 enable_irq(host
->irq
);
637 mmc_omap_cmd_timer(unsigned long data
)
639 struct mmc_omap_host
*host
= (struct mmc_omap_host
*) data
;
642 spin_lock_irqsave(&host
->slot_lock
, flags
);
643 if (host
->cmd
!= NULL
&& !host
->abort
) {
644 OMAP_MMC_WRITE(host
, IE
, 0);
645 disable_irq(host
->irq
);
647 queue_work(host
->mmc_omap_wq
, &host
->cmd_abort_work
);
649 spin_unlock_irqrestore(&host
->slot_lock
, flags
);
654 mmc_omap_sg_to_buf(struct mmc_omap_host
*host
)
656 struct scatterlist
*sg
;
658 sg
= host
->data
->sg
+ host
->sg_idx
;
659 host
->buffer_bytes_left
= sg
->length
;
660 host
->buffer
= sg_virt(sg
);
661 if (host
->buffer_bytes_left
> host
->total_bytes_left
)
662 host
->buffer_bytes_left
= host
->total_bytes_left
;
666 mmc_omap_clk_timer(unsigned long data
)
668 struct mmc_omap_host
*host
= (struct mmc_omap_host
*) data
;
670 mmc_omap_fclk_enable(host
, 0);
675 mmc_omap_xfer_data(struct mmc_omap_host
*host
, int write
)
679 if (host
->buffer_bytes_left
== 0) {
681 BUG_ON(host
->sg_idx
== host
->sg_len
);
682 mmc_omap_sg_to_buf(host
);
685 if (n
> host
->buffer_bytes_left
)
686 n
= host
->buffer_bytes_left
;
689 nwords
+= n
& 1; /* handle odd number of bytes to transfer */
691 host
->buffer_bytes_left
-= n
;
692 host
->total_bytes_left
-= n
;
693 host
->data
->bytes_xfered
+= n
;
696 __raw_writesw(host
->virt_base
+ OMAP_MMC_REG(host
, DATA
),
697 host
->buffer
, nwords
);
699 __raw_readsw(host
->virt_base
+ OMAP_MMC_REG(host
, DATA
),
700 host
->buffer
, nwords
);
703 host
->buffer
+= nwords
;
706 #ifdef CONFIG_MMC_DEBUG
707 static void mmc_omap_report_irq(struct mmc_omap_host
*host
, u16 status
)
709 static const char *mmc_omap_status_bits
[] = {
710 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
711 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
714 char res
[64], *buf
= res
;
716 buf
+= sprintf(buf
, "MMC IRQ 0x%x:", status
);
718 for (i
= 0; i
< ARRAY_SIZE(mmc_omap_status_bits
); i
++)
719 if (status
& (1 << i
))
720 buf
+= sprintf(buf
, " %s", mmc_omap_status_bits
[i
]);
721 dev_vdbg(mmc_dev(host
->mmc
), "%s\n", res
);
724 static void mmc_omap_report_irq(struct mmc_omap_host
*host
, u16 status
)
730 static irqreturn_t
mmc_omap_irq(int irq
, void *dev_id
)
732 struct mmc_omap_host
* host
= (struct mmc_omap_host
*)dev_id
;
736 int transfer_error
, cmd_error
;
738 if (host
->cmd
== NULL
&& host
->data
== NULL
) {
739 status
= OMAP_MMC_READ(host
, STAT
);
740 dev_info(mmc_dev(host
->slots
[0]->mmc
),
741 "Spurious IRQ 0x%04x\n", status
);
743 OMAP_MMC_WRITE(host
, STAT
, status
);
744 OMAP_MMC_WRITE(host
, IE
, 0);
754 while ((status
= OMAP_MMC_READ(host
, STAT
)) != 0) {
757 OMAP_MMC_WRITE(host
, STAT
, status
);
758 if (host
->cmd
!= NULL
)
759 cmd
= host
->cmd
->opcode
;
762 dev_dbg(mmc_dev(host
->mmc
), "MMC IRQ %04x (CMD %d): ",
764 mmc_omap_report_irq(host
, status
);
766 if (host
->total_bytes_left
) {
767 if ((status
& OMAP_MMC_STAT_A_FULL
) ||
768 (status
& OMAP_MMC_STAT_END_OF_DATA
))
769 mmc_omap_xfer_data(host
, 0);
770 if (status
& OMAP_MMC_STAT_A_EMPTY
)
771 mmc_omap_xfer_data(host
, 1);
774 if (status
& OMAP_MMC_STAT_END_OF_DATA
)
777 if (status
& OMAP_MMC_STAT_DATA_TOUT
) {
778 dev_dbg(mmc_dev(host
->mmc
), "data timeout (CMD%d)\n",
781 host
->data
->error
= -ETIMEDOUT
;
786 if (status
& OMAP_MMC_STAT_DATA_CRC
) {
788 host
->data
->error
= -EILSEQ
;
789 dev_dbg(mmc_dev(host
->mmc
),
790 "data CRC error, bytes left %d\n",
791 host
->total_bytes_left
);
794 dev_dbg(mmc_dev(host
->mmc
), "data CRC error\n");
798 if (status
& OMAP_MMC_STAT_CMD_TOUT
) {
799 /* Timeouts are routine with some commands */
801 struct mmc_omap_slot
*slot
=
804 !mmc_omap_cover_is_open(slot
))
805 dev_err(mmc_dev(host
->mmc
),
806 "command timeout (CMD%d)\n",
808 host
->cmd
->error
= -ETIMEDOUT
;
814 if (status
& OMAP_MMC_STAT_CMD_CRC
) {
816 dev_err(mmc_dev(host
->mmc
),
817 "command CRC error (CMD%d, arg 0x%08x)\n",
818 cmd
, host
->cmd
->arg
);
819 host
->cmd
->error
= -EILSEQ
;
823 dev_err(mmc_dev(host
->mmc
),
824 "command CRC error without cmd?\n");
827 if (status
& OMAP_MMC_STAT_CARD_ERR
) {
828 dev_dbg(mmc_dev(host
->mmc
),
829 "ignoring card status error (CMD%d)\n",
835 * NOTE: On 1610 the END_OF_CMD may come too early when
838 if ((status
& OMAP_MMC_STAT_END_OF_CMD
) &&
839 (!(status
& OMAP_MMC_STAT_A_EMPTY
))) {
844 if (cmd_error
&& host
->data
) {
845 del_timer(&host
->cmd_abort_timer
);
847 OMAP_MMC_WRITE(host
, IE
, 0);
848 disable_irq_nosync(host
->irq
);
849 queue_work(host
->mmc_omap_wq
, &host
->cmd_abort_work
);
853 if (end_command
&& host
->cmd
)
854 mmc_omap_cmd_done(host
, host
->cmd
);
855 if (host
->data
!= NULL
) {
857 mmc_omap_xfer_done(host
, host
->data
);
858 else if (end_transfer
)
859 mmc_omap_end_of_data(host
, host
->data
);
865 void omap_mmc_notify_cover_event(struct device
*dev
, int num
, int is_closed
)
868 struct mmc_omap_host
*host
= dev_get_drvdata(dev
);
869 struct mmc_omap_slot
*slot
= host
->slots
[num
];
871 BUG_ON(num
>= host
->nr_slots
);
873 /* Other subsystems can call in here before we're initialised. */
874 if (host
->nr_slots
== 0 || !host
->slots
[num
])
877 cover_open
= mmc_omap_cover_is_open(slot
);
878 if (cover_open
!= slot
->cover_open
) {
879 slot
->cover_open
= cover_open
;
880 sysfs_notify(&slot
->mmc
->class_dev
.kobj
, NULL
, "cover_switch");
883 tasklet_hi_schedule(&slot
->cover_tasklet
);
886 static void mmc_omap_cover_timer(unsigned long arg
)
888 struct mmc_omap_slot
*slot
= (struct mmc_omap_slot
*) arg
;
889 tasklet_schedule(&slot
->cover_tasklet
);
892 static void mmc_omap_cover_handler(unsigned long param
)
894 struct mmc_omap_slot
*slot
= (struct mmc_omap_slot
*)param
;
895 int cover_open
= mmc_omap_cover_is_open(slot
);
897 mmc_detect_change(slot
->mmc
, 0);
902 * If no card is inserted, we postpone polling until
903 * the cover has been closed.
905 if (slot
->mmc
->card
== NULL
|| !mmc_card_present(slot
->mmc
->card
))
908 mod_timer(&slot
->cover_timer
,
909 jiffies
+ msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY
));
912 static void mmc_omap_dma_callback(void *priv
)
914 struct mmc_omap_host
*host
= priv
;
915 struct mmc_data
*data
= host
->data
;
917 /* If we got to the end of DMA, assume everything went well */
918 data
->bytes_xfered
+= data
->blocks
* data
->blksz
;
920 mmc_omap_dma_done(host
, data
);
923 static inline void set_cmd_timeout(struct mmc_omap_host
*host
, struct mmc_request
*req
)
927 reg
= OMAP_MMC_READ(host
, SDIO
);
929 OMAP_MMC_WRITE(host
, SDIO
, reg
);
930 /* Set maximum timeout */
931 OMAP_MMC_WRITE(host
, CTO
, 0xff);
934 static inline void set_data_timeout(struct mmc_omap_host
*host
, struct mmc_request
*req
)
936 unsigned int timeout
, cycle_ns
;
939 cycle_ns
= 1000000000 / host
->current_slot
->fclk_freq
;
940 timeout
= req
->data
->timeout_ns
/ cycle_ns
;
941 timeout
+= req
->data
->timeout_clks
;
943 /* Check if we need to use timeout multiplier register */
944 reg
= OMAP_MMC_READ(host
, SDIO
);
945 if (timeout
> 0xffff) {
950 OMAP_MMC_WRITE(host
, SDIO
, reg
);
951 OMAP_MMC_WRITE(host
, DTO
, timeout
);
955 mmc_omap_prepare_data(struct mmc_omap_host
*host
, struct mmc_request
*req
)
957 struct mmc_data
*data
= req
->data
;
958 int i
, use_dma
, block_size
;
963 OMAP_MMC_WRITE(host
, BLEN
, 0);
964 OMAP_MMC_WRITE(host
, NBLK
, 0);
965 OMAP_MMC_WRITE(host
, BUF
, 0);
966 host
->dma_in_use
= 0;
967 set_cmd_timeout(host
, req
);
971 block_size
= data
->blksz
;
973 OMAP_MMC_WRITE(host
, NBLK
, data
->blocks
- 1);
974 OMAP_MMC_WRITE(host
, BLEN
, block_size
- 1);
975 set_data_timeout(host
, req
);
977 /* cope with calling layer confusion; it issues "single
978 * block" writes using multi-block scatterlists.
980 sg_len
= (data
->blocks
== 1) ? 1 : data
->sg_len
;
982 /* Only do DMA for entire blocks */
983 use_dma
= host
->use_dma
;
985 for (i
= 0; i
< sg_len
; i
++) {
986 if ((data
->sg
[i
].length
% block_size
) != 0) {
995 enum dma_data_direction dma_data_dir
;
996 struct dma_async_tx_descriptor
*tx
;
1002 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx
1003 * and 24xx. Use 16 or 32 word frames when the
1004 * blocksize is at least that large. Blocksize is
1005 * usually 512 bytes; but not for some SD reads.
1007 burst
= mmc_omap15xx() ? 32 : 64;
1008 if (burst
> data
->blksz
)
1009 burst
= data
->blksz
;
1013 if (data
->flags
& MMC_DATA_WRITE
) {
1015 bp
= &host
->dma_tx_burst
;
1016 buf
= 0x0f80 | (burst
- 1) << 0;
1017 dma_data_dir
= DMA_TO_DEVICE
;
1020 bp
= &host
->dma_rx_burst
;
1021 buf
= 0x800f | (burst
- 1) << 8;
1022 dma_data_dir
= DMA_FROM_DEVICE
;
1028 /* Only reconfigure if we have a different burst size */
1030 struct dma_slave_config cfg
;
1032 cfg
.src_addr
= host
->phys_base
+ OMAP_MMC_REG(host
, DATA
);
1033 cfg
.dst_addr
= host
->phys_base
+ OMAP_MMC_REG(host
, DATA
);
1034 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
1035 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
1036 cfg
.src_maxburst
= burst
;
1037 cfg
.dst_maxburst
= burst
;
1039 if (dmaengine_slave_config(c
, &cfg
))
1045 host
->sg_len
= dma_map_sg(c
->device
->dev
, data
->sg
, sg_len
,
1047 if (host
->sg_len
== 0)
1050 tx
= dmaengine_prep_slave_sg(c
, data
->sg
, host
->sg_len
,
1051 data
->flags
& MMC_DATA_WRITE
? DMA_MEM_TO_DEV
: DMA_DEV_TO_MEM
,
1052 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1056 OMAP_MMC_WRITE(host
, BUF
, buf
);
1058 tx
->callback
= mmc_omap_dma_callback
;
1059 tx
->callback_param
= host
;
1060 dmaengine_submit(tx
);
1061 host
->brs_received
= 0;
1063 host
->dma_in_use
= 1;
1068 /* Revert to PIO? */
1069 OMAP_MMC_WRITE(host
, BUF
, 0x1f1f);
1070 host
->total_bytes_left
= data
->blocks
* block_size
;
1071 host
->sg_len
= sg_len
;
1072 mmc_omap_sg_to_buf(host
);
1073 host
->dma_in_use
= 0;
1076 static void mmc_omap_start_request(struct mmc_omap_host
*host
,
1077 struct mmc_request
*req
)
1079 BUG_ON(host
->mrq
!= NULL
);
1083 /* only touch fifo AFTER the controller readies it */
1084 mmc_omap_prepare_data(host
, req
);
1085 mmc_omap_start_command(host
, req
->cmd
);
1086 if (host
->dma_in_use
) {
1087 struct dma_chan
*c
= host
->data
->flags
& MMC_DATA_WRITE
?
1088 host
->dma_tx
: host
->dma_rx
;
1090 dma_async_issue_pending(c
);
1094 static void mmc_omap_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
1096 struct mmc_omap_slot
*slot
= mmc_priv(mmc
);
1097 struct mmc_omap_host
*host
= slot
->host
;
1098 unsigned long flags
;
1100 spin_lock_irqsave(&host
->slot_lock
, flags
);
1101 if (host
->mmc
!= NULL
) {
1102 BUG_ON(slot
->mrq
!= NULL
);
1104 spin_unlock_irqrestore(&host
->slot_lock
, flags
);
1108 spin_unlock_irqrestore(&host
->slot_lock
, flags
);
1109 mmc_omap_select_slot(slot
, 1);
1110 mmc_omap_start_request(host
, req
);
1113 static void mmc_omap_set_power(struct mmc_omap_slot
*slot
, int power_on
,
1116 struct mmc_omap_host
*host
;
1120 if (slot
->pdata
->set_power
!= NULL
)
1121 slot
->pdata
->set_power(mmc_dev(slot
->mmc
), slot
->id
, power_on
,
1127 w
= OMAP_MMC_READ(host
, CON
);
1128 OMAP_MMC_WRITE(host
, CON
, w
| (1 << 11));
1130 w
= OMAP_MMC_READ(host
, CON
);
1131 OMAP_MMC_WRITE(host
, CON
, w
& ~(1 << 11));
1136 static int mmc_omap_calc_divisor(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1138 struct mmc_omap_slot
*slot
= mmc_priv(mmc
);
1139 struct mmc_omap_host
*host
= slot
->host
;
1140 int func_clk_rate
= clk_get_rate(host
->fclk
);
1143 if (ios
->clock
== 0)
1146 dsor
= func_clk_rate
/ ios
->clock
;
1150 if (func_clk_rate
/ dsor
> ios
->clock
)
1156 slot
->fclk_freq
= func_clk_rate
/ dsor
;
1158 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
1164 static void mmc_omap_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1166 struct mmc_omap_slot
*slot
= mmc_priv(mmc
);
1167 struct mmc_omap_host
*host
= slot
->host
;
1171 mmc_omap_select_slot(slot
, 0);
1173 dsor
= mmc_omap_calc_divisor(mmc
, ios
);
1175 if (ios
->vdd
!= slot
->vdd
)
1176 slot
->vdd
= ios
->vdd
;
1179 switch (ios
->power_mode
) {
1181 mmc_omap_set_power(slot
, 0, ios
->vdd
);
1184 /* Cannot touch dsor yet, just power up MMC */
1185 mmc_omap_set_power(slot
, 1, ios
->vdd
);
1188 mmc_omap_fclk_enable(host
, 1);
1194 if (slot
->bus_mode
!= ios
->bus_mode
) {
1195 if (slot
->pdata
->set_bus_mode
!= NULL
)
1196 slot
->pdata
->set_bus_mode(mmc_dev(mmc
), slot
->id
,
1198 slot
->bus_mode
= ios
->bus_mode
;
1201 /* On insanely high arm_per frequencies something sometimes
1202 * goes somehow out of sync, and the POW bit is not being set,
1203 * which results in the while loop below getting stuck.
1204 * Writing to the CON register twice seems to do the trick. */
1205 for (i
= 0; i
< 2; i
++)
1206 OMAP_MMC_WRITE(host
, CON
, dsor
);
1207 slot
->saved_con
= dsor
;
1208 if (ios
->power_mode
== MMC_POWER_ON
) {
1209 /* worst case at 400kHz, 80 cycles makes 200 microsecs */
1212 /* Send clock cycles, poll completion */
1213 OMAP_MMC_WRITE(host
, IE
, 0);
1214 OMAP_MMC_WRITE(host
, STAT
, 0xffff);
1215 OMAP_MMC_WRITE(host
, CMD
, 1 << 7);
1216 while (usecs
> 0 && (OMAP_MMC_READ(host
, STAT
) & 1) == 0) {
1220 OMAP_MMC_WRITE(host
, STAT
, 1);
1224 mmc_omap_release_slot(slot
, clk_enabled
);
1227 static const struct mmc_host_ops mmc_omap_ops
= {
1228 .request
= mmc_omap_request
,
1229 .set_ios
= mmc_omap_set_ios
,
1232 static int mmc_omap_new_slot(struct mmc_omap_host
*host
, int id
)
1234 struct mmc_omap_slot
*slot
= NULL
;
1235 struct mmc_host
*mmc
;
1238 mmc
= mmc_alloc_host(sizeof(struct mmc_omap_slot
), host
->dev
);
1242 slot
= mmc_priv(mmc
);
1246 slot
->pdata
= &host
->pdata
->slots
[id
];
1248 host
->slots
[id
] = slot
;
1251 if (host
->pdata
->slots
[id
].wires
>= 4)
1252 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
1254 mmc
->ops
= &mmc_omap_ops
;
1255 mmc
->f_min
= 400000;
1258 mmc
->f_max
= 48000000;
1260 mmc
->f_max
= 24000000;
1261 if (host
->pdata
->max_freq
)
1262 mmc
->f_max
= min(host
->pdata
->max_freq
, mmc
->f_max
);
1263 mmc
->ocr_avail
= slot
->pdata
->ocr_mask
;
1265 /* Use scatterlist DMA to reduce per-transfer costs.
1266 * NOTE max_seg_size assumption that small blocks aren't
1267 * normally used (except e.g. for reading SD registers).
1270 mmc
->max_blk_size
= 2048; /* BLEN is 11 bits (+1) */
1271 mmc
->max_blk_count
= 2048; /* NBLK is 11 bits (+1) */
1272 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
1273 mmc
->max_seg_size
= mmc
->max_req_size
;
1275 r
= mmc_add_host(mmc
);
1277 goto err_remove_host
;
1279 if (slot
->pdata
->name
!= NULL
) {
1280 r
= device_create_file(&mmc
->class_dev
,
1281 &dev_attr_slot_name
);
1283 goto err_remove_host
;
1286 if (slot
->pdata
->get_cover_state
!= NULL
) {
1287 r
= device_create_file(&mmc
->class_dev
,
1288 &dev_attr_cover_switch
);
1290 goto err_remove_slot_name
;
1292 setup_timer(&slot
->cover_timer
, mmc_omap_cover_timer
,
1293 (unsigned long)slot
);
1294 tasklet_init(&slot
->cover_tasklet
, mmc_omap_cover_handler
,
1295 (unsigned long)slot
);
1296 tasklet_schedule(&slot
->cover_tasklet
);
1301 err_remove_slot_name
:
1302 if (slot
->pdata
->name
!= NULL
)
1303 device_remove_file(&mmc
->class_dev
, &dev_attr_slot_name
);
1305 mmc_remove_host(mmc
);
1310 static void mmc_omap_remove_slot(struct mmc_omap_slot
*slot
)
1312 struct mmc_host
*mmc
= slot
->mmc
;
1314 if (slot
->pdata
->name
!= NULL
)
1315 device_remove_file(&mmc
->class_dev
, &dev_attr_slot_name
);
1316 if (slot
->pdata
->get_cover_state
!= NULL
)
1317 device_remove_file(&mmc
->class_dev
, &dev_attr_cover_switch
);
1319 tasklet_kill(&slot
->cover_tasklet
);
1320 del_timer_sync(&slot
->cover_timer
);
1321 flush_workqueue(slot
->host
->mmc_omap_wq
);
1323 mmc_remove_host(mmc
);
1327 static int mmc_omap_probe(struct platform_device
*pdev
)
1329 struct omap_mmc_platform_data
*pdata
= pdev
->dev
.platform_data
;
1330 struct mmc_omap_host
*host
= NULL
;
1331 struct resource
*res
;
1332 dma_cap_mask_t mask
;
1337 if (pdata
== NULL
) {
1338 dev_err(&pdev
->dev
, "platform data missing\n");
1341 if (pdata
->nr_slots
== 0) {
1342 dev_err(&pdev
->dev
, "no slots\n");
1346 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1347 irq
= platform_get_irq(pdev
, 0);
1348 if (res
== NULL
|| irq
< 0)
1351 res
= request_mem_region(res
->start
, resource_size(res
),
1356 host
= kzalloc(sizeof(struct mmc_omap_host
), GFP_KERNEL
);
1359 goto err_free_mem_region
;
1362 INIT_WORK(&host
->slot_release_work
, mmc_omap_slot_release_work
);
1363 INIT_WORK(&host
->send_stop_work
, mmc_omap_send_stop_work
);
1365 INIT_WORK(&host
->cmd_abort_work
, mmc_omap_abort_command
);
1366 setup_timer(&host
->cmd_abort_timer
, mmc_omap_cmd_timer
,
1367 (unsigned long) host
);
1369 spin_lock_init(&host
->clk_lock
);
1370 setup_timer(&host
->clk_timer
, mmc_omap_clk_timer
, (unsigned long) host
);
1372 spin_lock_init(&host
->dma_lock
);
1373 spin_lock_init(&host
->slot_lock
);
1374 init_waitqueue_head(&host
->slot_wq
);
1376 host
->pdata
= pdata
;
1377 host
->features
= host
->pdata
->slots
[0].features
;
1378 host
->dev
= &pdev
->dev
;
1379 platform_set_drvdata(pdev
, host
);
1381 host
->id
= pdev
->id
;
1382 host
->mem_res
= res
;
1386 host
->phys_base
= host
->mem_res
->start
;
1387 host
->virt_base
= ioremap(res
->start
, resource_size(res
));
1388 if (!host
->virt_base
)
1391 host
->iclk
= clk_get(&pdev
->dev
, "ick");
1392 if (IS_ERR(host
->iclk
)) {
1393 ret
= PTR_ERR(host
->iclk
);
1394 goto err_free_mmc_host
;
1396 clk_enable(host
->iclk
);
1398 host
->fclk
= clk_get(&pdev
->dev
, "fck");
1399 if (IS_ERR(host
->fclk
)) {
1400 ret
= PTR_ERR(host
->fclk
);
1405 dma_cap_set(DMA_SLAVE
, mask
);
1407 host
->dma_tx_burst
= -1;
1408 host
->dma_rx_burst
= -1;
1411 sig
= host
->id
== 0 ? OMAP24XX_DMA_MMC1_TX
: OMAP24XX_DMA_MMC2_TX
;
1413 sig
= host
->id
== 0 ? OMAP_DMA_MMC_TX
: OMAP_DMA_MMC2_TX
;
1414 host
->dma_tx
= dma_request_channel(mask
, omap_dma_filter_fn
, &sig
);
1416 dev_warn(host
->dev
, "unable to obtain TX DMA engine channel %u\n",
1419 sig
= host
->id
== 0 ? OMAP24XX_DMA_MMC1_RX
: OMAP24XX_DMA_MMC2_RX
;
1421 sig
= host
->id
== 0 ? OMAP_DMA_MMC_RX
: OMAP_DMA_MMC2_RX
;
1422 host
->dma_rx
= dma_request_channel(mask
, omap_dma_filter_fn
, &sig
);
1424 dev_warn(host
->dev
, "unable to obtain RX DMA engine channel %u\n",
1427 ret
= request_irq(host
->irq
, mmc_omap_irq
, 0, DRIVER_NAME
, host
);
1431 if (pdata
->init
!= NULL
) {
1432 ret
= pdata
->init(&pdev
->dev
);
1437 host
->nr_slots
= pdata
->nr_slots
;
1438 host
->reg_shift
= (mmc_omap7xx() ? 1 : 2);
1440 host
->mmc_omap_wq
= alloc_workqueue("mmc_omap", 0, 0);
1441 if (!host
->mmc_omap_wq
)
1442 goto err_plat_cleanup
;
1444 for (i
= 0; i
< pdata
->nr_slots
; i
++) {
1445 ret
= mmc_omap_new_slot(host
, i
);
1448 mmc_omap_remove_slot(host
->slots
[i
]);
1450 goto err_destroy_wq
;
1457 destroy_workqueue(host
->mmc_omap_wq
);
1460 pdata
->cleanup(&pdev
->dev
);
1462 free_irq(host
->irq
, host
);
1465 dma_release_channel(host
->dma_tx
);
1467 dma_release_channel(host
->dma_rx
);
1468 clk_put(host
->fclk
);
1470 clk_disable(host
->iclk
);
1471 clk_put(host
->iclk
);
1473 iounmap(host
->virt_base
);
1476 err_free_mem_region
:
1477 release_mem_region(res
->start
, resource_size(res
));
1481 static int mmc_omap_remove(struct platform_device
*pdev
)
1483 struct mmc_omap_host
*host
= platform_get_drvdata(pdev
);
1486 BUG_ON(host
== NULL
);
1488 for (i
= 0; i
< host
->nr_slots
; i
++)
1489 mmc_omap_remove_slot(host
->slots
[i
]);
1491 if (host
->pdata
->cleanup
)
1492 host
->pdata
->cleanup(&pdev
->dev
);
1494 mmc_omap_fclk_enable(host
, 0);
1495 free_irq(host
->irq
, host
);
1496 clk_put(host
->fclk
);
1497 clk_disable(host
->iclk
);
1498 clk_put(host
->iclk
);
1501 dma_release_channel(host
->dma_tx
);
1503 dma_release_channel(host
->dma_rx
);
1505 iounmap(host
->virt_base
);
1506 release_mem_region(pdev
->resource
[0].start
,
1507 pdev
->resource
[0].end
- pdev
->resource
[0].start
+ 1);
1508 destroy_workqueue(host
->mmc_omap_wq
);
1515 static struct platform_driver mmc_omap_driver
= {
1516 .probe
= mmc_omap_probe
,
1517 .remove
= mmc_omap_remove
,
1519 .name
= DRIVER_NAME
,
1520 .owner
= THIS_MODULE
,
1524 module_platform_driver(mmc_omap_driver
);
1525 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1526 MODULE_LICENSE("GPL");
1527 MODULE_ALIAS("platform:" DRIVER_NAME
);
1528 MODULE_AUTHOR("Juha Yrjölä");