2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/sizes.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/platform_device.h>
29 #include <linux/timer.h>
30 #include <linux/clk.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_gpio.h>
34 #include <linux/of_device.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/core.h>
37 #include <linux/mmc/mmc.h>
38 #include <linux/mmc/slot-gpio.h>
40 #include <linux/irq.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/pinctrl/consumer.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/pm_wakeirq.h>
46 #include <linux/platform_data/hsmmc-omap.h>
48 /* OMAP HSMMC Host Controller Registers */
49 #define OMAP_HSMMC_SYSSTATUS 0x0014
50 #define OMAP_HSMMC_CON 0x002C
51 #define OMAP_HSMMC_SDMASA 0x0100
52 #define OMAP_HSMMC_BLK 0x0104
53 #define OMAP_HSMMC_ARG 0x0108
54 #define OMAP_HSMMC_CMD 0x010C
55 #define OMAP_HSMMC_RSP10 0x0110
56 #define OMAP_HSMMC_RSP32 0x0114
57 #define OMAP_HSMMC_RSP54 0x0118
58 #define OMAP_HSMMC_RSP76 0x011C
59 #define OMAP_HSMMC_DATA 0x0120
60 #define OMAP_HSMMC_PSTATE 0x0124
61 #define OMAP_HSMMC_HCTL 0x0128
62 #define OMAP_HSMMC_SYSCTL 0x012C
63 #define OMAP_HSMMC_STAT 0x0130
64 #define OMAP_HSMMC_IE 0x0134
65 #define OMAP_HSMMC_ISE 0x0138
66 #define OMAP_HSMMC_AC12 0x013C
67 #define OMAP_HSMMC_CAPA 0x0140
69 #define VS18 (1 << 26)
70 #define VS30 (1 << 25)
72 #define SDVS18 (0x5 << 9)
73 #define SDVS30 (0x6 << 9)
74 #define SDVS33 (0x7 << 9)
75 #define SDVS_MASK 0x00000E00
76 #define SDVSCLR 0xFFFFF1FF
77 #define SDVSDET 0x00000400
84 #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
85 #define CLKD_MASK 0x0000FFC0
87 #define DTO_MASK 0x000F0000
89 #define INIT_STREAM (1 << 1)
90 #define ACEN_ACMD23 (2 << 2)
91 #define DP_SELECT (1 << 21)
96 #define FOUR_BIT (1 << 1)
100 #define CLKEXTFREE (1 << 16)
101 #define CTPL (1 << 11)
104 #define STAT_CLEAR 0xFFFFFFFF
105 #define INIT_STREAM_CMD 0x00000000
106 #define DUAL_VOLT_OCR_BIT 7
107 #define SRC (1 << 25)
108 #define SRD (1 << 26)
109 #define SOFTRESET (1 << 1)
112 #define DLEV_DAT(x) (1 << (20 + (x)))
114 /* Interrupt masks for IE and ISE register */
115 #define CC_EN (1 << 0)
116 #define TC_EN (1 << 1)
117 #define BWR_EN (1 << 4)
118 #define BRR_EN (1 << 5)
119 #define CIRQ_EN (1 << 8)
120 #define ERR_EN (1 << 15)
121 #define CTO_EN (1 << 16)
122 #define CCRC_EN (1 << 17)
123 #define CEB_EN (1 << 18)
124 #define CIE_EN (1 << 19)
125 #define DTO_EN (1 << 20)
126 #define DCRC_EN (1 << 21)
127 #define DEB_EN (1 << 22)
128 #define ACE_EN (1 << 24)
129 #define CERR_EN (1 << 28)
130 #define BADA_EN (1 << 29)
132 #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
133 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
134 BRR_EN | BWR_EN | TC_EN | CC_EN)
137 #define ACIE (1 << 4)
138 #define ACEB (1 << 3)
139 #define ACCE (1 << 2)
140 #define ACTO (1 << 1)
141 #define ACNE (1 << 0)
143 #define MMC_AUTOSUSPEND_DELAY 100
144 #define MMC_TIMEOUT_MS 20 /* 20 mSec */
145 #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
146 #define OMAP_MMC_MIN_CLOCK 400000
147 #define OMAP_MMC_MAX_CLOCK 52000000
148 #define DRIVER_NAME "omap_hsmmc"
150 #define VDD_1V8 1800000 /* 180000 uV */
151 #define VDD_3V0 3000000 /* 300000 uV */
152 #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
155 * One controller can have multiple slots, like on some omap boards using
156 * omap.c controller driver. Luckily this is not currently done on any known
157 * omap_hsmmc.c device.
159 #define mmc_pdata(host) host->pdata
162 * MMC Host controller read/write API's
164 #define OMAP_HSMMC_READ(base, reg) \
165 __raw_readl((base) + OMAP_HSMMC_##reg)
167 #define OMAP_HSMMC_WRITE(base, reg, val) \
168 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
170 struct omap_hsmmc_next
{
171 unsigned int dma_len
;
175 struct omap_hsmmc_host
{
177 struct mmc_host
*mmc
;
178 struct mmc_request
*mrq
;
179 struct mmc_command
*cmd
;
180 struct mmc_data
*data
;
183 struct regulator
*pbias
;
187 resource_size_t mapbase
;
188 spinlock_t irq_lock
; /* Prevent races with irq handler */
189 unsigned int dma_len
;
190 unsigned int dma_sg_idx
;
191 unsigned char bus_mode
;
192 unsigned char power_mode
;
201 struct dma_chan
*tx_chan
;
202 struct dma_chan
*rx_chan
;
208 unsigned long clk_rate
;
210 #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
211 #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
212 struct omap_hsmmc_next next_data
;
213 struct omap_hsmmc_platform_data
*pdata
;
215 /* return MMC cover switch state, can be NULL if not supported.
217 * possible return values:
221 int (*get_cover_state
)(struct device
*dev
);
223 int (*card_detect
)(struct device
*dev
);
226 struct omap_mmc_of_data
{
231 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host
*host
);
233 static int omap_hsmmc_card_detect(struct device
*dev
)
235 struct omap_hsmmc_host
*host
= dev_get_drvdata(dev
);
237 return mmc_gpio_get_cd(host
->mmc
);
240 static int omap_hsmmc_get_cover_state(struct device
*dev
)
242 struct omap_hsmmc_host
*host
= dev_get_drvdata(dev
);
244 return mmc_gpio_get_cd(host
->mmc
);
247 static int omap_hsmmc_enable_supply(struct mmc_host
*mmc
)
250 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
251 struct mmc_ios
*ios
= &mmc
->ios
;
253 if (!IS_ERR(mmc
->supply
.vmmc
)) {
254 ret
= mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, ios
->vdd
);
259 /* Enable interface voltage rail, if needed */
260 if (!IS_ERR(mmc
->supply
.vqmmc
) && !host
->vqmmc_enabled
) {
261 ret
= regulator_enable(mmc
->supply
.vqmmc
);
263 dev_err(mmc_dev(mmc
), "vmmc_aux reg enable failed\n");
266 host
->vqmmc_enabled
= 1;
272 if (!IS_ERR(mmc
->supply
.vmmc
))
273 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
278 static int omap_hsmmc_disable_supply(struct mmc_host
*mmc
)
282 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
284 if (!IS_ERR(mmc
->supply
.vqmmc
) && host
->vqmmc_enabled
) {
285 ret
= regulator_disable(mmc
->supply
.vqmmc
);
287 dev_err(mmc_dev(mmc
), "vmmc_aux reg disable failed\n");
290 host
->vqmmc_enabled
= 0;
293 if (!IS_ERR(mmc
->supply
.vmmc
)) {
294 ret
= mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
302 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
303 status
= regulator_enable(mmc
->supply
.vqmmc
);
305 dev_err(mmc_dev(mmc
), "vmmc_aux re-enable failed\n");
311 static int omap_hsmmc_set_pbias(struct omap_hsmmc_host
*host
, bool power_on
,
316 if (IS_ERR(host
->pbias
))
320 if (vdd
<= VDD_165_195
)
321 ret
= regulator_set_voltage(host
->pbias
, VDD_1V8
,
324 ret
= regulator_set_voltage(host
->pbias
, VDD_3V0
,
327 dev_err(host
->dev
, "pbias set voltage fail\n");
331 if (host
->pbias_enabled
== 0) {
332 ret
= regulator_enable(host
->pbias
);
334 dev_err(host
->dev
, "pbias reg enable fail\n");
337 host
->pbias_enabled
= 1;
340 if (host
->pbias_enabled
== 1) {
341 ret
= regulator_disable(host
->pbias
);
343 dev_err(host
->dev
, "pbias reg disable fail\n");
346 host
->pbias_enabled
= 0;
353 static int omap_hsmmc_set_power(struct omap_hsmmc_host
*host
, int power_on
,
356 struct mmc_host
*mmc
= host
->mmc
;
359 if (mmc_pdata(host
)->set_power
)
360 return mmc_pdata(host
)->set_power(host
->dev
, power_on
, vdd
);
363 * If we don't see a Vcc regulator, assume it's a fixed
364 * voltage always-on regulator.
366 if (IS_ERR(mmc
->supply
.vmmc
))
369 if (mmc_pdata(host
)->before_set_reg
)
370 mmc_pdata(host
)->before_set_reg(host
->dev
, power_on
, vdd
);
372 ret
= omap_hsmmc_set_pbias(host
, false, 0);
377 * Assume Vcc regulator is used only to power the card ... OMAP
378 * VDDS is used to power the pins, optionally with a transceiver to
379 * support cards using voltages other than VDDS (1.8V nominal). When a
380 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
382 * In some cases this regulator won't support enable/disable;
383 * e.g. it's a fixed rail for a WLAN chip.
385 * In other cases vcc_aux switches interface power. Example, for
386 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
387 * chips/cards need an interface voltage rail too.
390 ret
= omap_hsmmc_enable_supply(mmc
);
394 ret
= omap_hsmmc_set_pbias(host
, true, vdd
);
396 goto err_set_voltage
;
398 ret
= omap_hsmmc_disable_supply(mmc
);
403 if (mmc_pdata(host
)->after_set_reg
)
404 mmc_pdata(host
)->after_set_reg(host
->dev
, power_on
, vdd
);
409 omap_hsmmc_disable_supply(mmc
);
414 static int omap_hsmmc_disable_boot_regulator(struct regulator
*reg
)
421 if (regulator_is_enabled(reg
)) {
422 ret
= regulator_enable(reg
);
426 ret
= regulator_disable(reg
);
434 static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host
*host
)
436 struct mmc_host
*mmc
= host
->mmc
;
440 * disable regulators enabled during boot and get the usecount
441 * right so that regulators can be enabled/disabled by checking
442 * the return value of regulator_is_enabled
444 ret
= omap_hsmmc_disable_boot_regulator(mmc
->supply
.vmmc
);
446 dev_err(host
->dev
, "fail to disable boot enabled vmmc reg\n");
450 ret
= omap_hsmmc_disable_boot_regulator(mmc
->supply
.vqmmc
);
453 "fail to disable boot enabled vmmc_aux reg\n");
457 ret
= omap_hsmmc_disable_boot_regulator(host
->pbias
);
460 "failed to disable boot enabled pbias reg\n");
467 static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host
)
470 struct mmc_host
*mmc
= host
->mmc
;
472 if (mmc_pdata(host
)->set_power
)
475 ret
= mmc_regulator_get_supply(mmc
);
476 if (ret
== -EPROBE_DEFER
)
479 /* Allow an aux regulator */
480 if (IS_ERR(mmc
->supply
.vqmmc
)) {
481 mmc
->supply
.vqmmc
= devm_regulator_get_optional(host
->dev
,
483 if (IS_ERR(mmc
->supply
.vqmmc
)) {
484 ret
= PTR_ERR(mmc
->supply
.vqmmc
);
485 if ((ret
!= -ENODEV
) && host
->dev
->of_node
)
487 dev_dbg(host
->dev
, "unable to get vmmc_aux regulator %ld\n",
488 PTR_ERR(mmc
->supply
.vqmmc
));
492 host
->pbias
= devm_regulator_get_optional(host
->dev
, "pbias");
493 if (IS_ERR(host
->pbias
)) {
494 ret
= PTR_ERR(host
->pbias
);
495 if ((ret
!= -ENODEV
) && host
->dev
->of_node
) {
497 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
500 dev_dbg(host
->dev
, "unable to get pbias regulator %ld\n",
501 PTR_ERR(host
->pbias
));
504 /* For eMMC do not power off when not in sleep state */
505 if (mmc_pdata(host
)->no_regulator_off_init
)
508 ret
= omap_hsmmc_disable_boot_regulators(host
);
515 static irqreturn_t
omap_hsmmc_cover_irq(int irq
, void *dev_id
);
517 static int omap_hsmmc_gpio_init(struct mmc_host
*mmc
,
518 struct omap_hsmmc_host
*host
,
519 struct omap_hsmmc_platform_data
*pdata
)
523 if (gpio_is_valid(pdata
->gpio_cod
)) {
524 ret
= mmc_gpio_request_cd(mmc
, pdata
->gpio_cod
, 0);
528 host
->get_cover_state
= omap_hsmmc_get_cover_state
;
529 mmc_gpio_set_cd_isr(mmc
, omap_hsmmc_cover_irq
);
530 } else if (gpio_is_valid(pdata
->gpio_cd
)) {
531 ret
= mmc_gpio_request_cd(mmc
, pdata
->gpio_cd
, 0);
535 host
->card_detect
= omap_hsmmc_card_detect
;
538 if (gpio_is_valid(pdata
->gpio_wp
)) {
539 ret
= mmc_gpio_request_ro(mmc
, pdata
->gpio_wp
);
548 * Start clock to the card
550 static void omap_hsmmc_start_clock(struct omap_hsmmc_host
*host
)
552 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
553 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | CEN
);
557 * Stop clock to the card
559 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host
*host
)
561 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
562 OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ~CEN
);
563 if ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & CEN
) != 0x0)
564 dev_dbg(mmc_dev(host
->mmc
), "MMC Clock is not stopped\n");
567 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host
*host
,
568 struct mmc_command
*cmd
)
570 u32 irq_mask
= INT_EN_MASK
;
574 irq_mask
&= ~(BRR_EN
| BWR_EN
);
576 /* Disable timeout for erases */
577 if (cmd
->opcode
== MMC_ERASE
)
580 spin_lock_irqsave(&host
->irq_lock
, flags
);
581 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
582 OMAP_HSMMC_WRITE(host
->base
, ISE
, irq_mask
);
584 /* latch pending CIRQ, but don't signal MMC core */
585 if (host
->flags
& HSMMC_SDIO_IRQ_ENABLED
)
587 OMAP_HSMMC_WRITE(host
->base
, IE
, irq_mask
);
588 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
591 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host
*host
)
596 spin_lock_irqsave(&host
->irq_lock
, flags
);
597 /* no transfer running but need to keep cirq if enabled */
598 if (host
->flags
& HSMMC_SDIO_IRQ_ENABLED
)
600 OMAP_HSMMC_WRITE(host
->base
, ISE
, irq_mask
);
601 OMAP_HSMMC_WRITE(host
->base
, IE
, irq_mask
);
602 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
603 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
606 /* Calculate divisor for the given clock frequency */
607 static u16
calc_divisor(struct omap_hsmmc_host
*host
, struct mmc_ios
*ios
)
612 dsor
= DIV_ROUND_UP(clk_get_rate(host
->fclk
), ios
->clock
);
620 static void omap_hsmmc_set_clock(struct omap_hsmmc_host
*host
)
622 struct mmc_ios
*ios
= &host
->mmc
->ios
;
623 unsigned long regval
;
624 unsigned long timeout
;
625 unsigned long clkdiv
;
627 dev_vdbg(mmc_dev(host
->mmc
), "Set clock to %uHz\n", ios
->clock
);
629 omap_hsmmc_stop_clock(host
);
631 regval
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
632 regval
= regval
& ~(CLKD_MASK
| DTO_MASK
);
633 clkdiv
= calc_divisor(host
, ios
);
634 regval
= regval
| (clkdiv
<< 6) | (DTO
<< 16);
635 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, regval
);
636 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
637 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | ICE
);
639 /* Wait till the ICS bit is set */
640 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
641 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ICS
) != ICS
642 && time_before(jiffies
, timeout
))
646 * Enable High-Speed Support
648 * - Controller should support High-Speed-Enable Bit
649 * - Controller should not be using DDR Mode
650 * - Controller should advertise that it supports High Speed
651 * in capabilities register
652 * - MMC/SD clock coming out of controller > 25MHz
654 if ((mmc_pdata(host
)->features
& HSMMC_HAS_HSPE_SUPPORT
) &&
655 (ios
->timing
!= MMC_TIMING_MMC_DDR52
) &&
656 (ios
->timing
!= MMC_TIMING_UHS_DDR50
) &&
657 ((OMAP_HSMMC_READ(host
->base
, CAPA
) & HSS
) == HSS
)) {
658 regval
= OMAP_HSMMC_READ(host
->base
, HCTL
);
659 if (clkdiv
&& (clk_get_rate(host
->fclk
)/clkdiv
) > 25000000)
664 OMAP_HSMMC_WRITE(host
->base
, HCTL
, regval
);
667 omap_hsmmc_start_clock(host
);
670 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host
*host
)
672 struct mmc_ios
*ios
= &host
->mmc
->ios
;
675 con
= OMAP_HSMMC_READ(host
->base
, CON
);
676 if (ios
->timing
== MMC_TIMING_MMC_DDR52
||
677 ios
->timing
== MMC_TIMING_UHS_DDR50
)
678 con
|= DDR
; /* configure in DDR mode */
681 switch (ios
->bus_width
) {
682 case MMC_BUS_WIDTH_8
:
683 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| DW8
);
685 case MMC_BUS_WIDTH_4
:
686 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
687 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
688 OMAP_HSMMC_READ(host
->base
, HCTL
) | FOUR_BIT
);
690 case MMC_BUS_WIDTH_1
:
691 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
692 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
693 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~FOUR_BIT
);
698 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host
*host
)
700 struct mmc_ios
*ios
= &host
->mmc
->ios
;
703 con
= OMAP_HSMMC_READ(host
->base
, CON
);
704 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
705 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| OD
);
707 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~OD
);
713 * Restore the MMC host context, if it was lost as result of a
714 * power state change.
716 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
718 struct mmc_ios
*ios
= &host
->mmc
->ios
;
720 unsigned long timeout
;
722 if (host
->con
== OMAP_HSMMC_READ(host
->base
, CON
) &&
723 host
->hctl
== OMAP_HSMMC_READ(host
->base
, HCTL
) &&
724 host
->sysctl
== OMAP_HSMMC_READ(host
->base
, SYSCTL
) &&
725 host
->capa
== OMAP_HSMMC_READ(host
->base
, CAPA
))
728 host
->context_loss
++;
730 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
731 if (host
->power_mode
!= MMC_POWER_OFF
&&
732 (1 << ios
->vdd
) <= MMC_VDD_23_24
)
742 if (host
->mmc
->caps
& MMC_CAP_SDIO_IRQ
)
745 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
746 OMAP_HSMMC_READ(host
->base
, HCTL
) | hctl
);
748 OMAP_HSMMC_WRITE(host
->base
, CAPA
,
749 OMAP_HSMMC_READ(host
->base
, CAPA
) | capa
);
751 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
752 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
754 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
755 while ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
) != SDBP
756 && time_before(jiffies
, timeout
))
759 OMAP_HSMMC_WRITE(host
->base
, ISE
, 0);
760 OMAP_HSMMC_WRITE(host
->base
, IE
, 0);
761 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
763 /* Do not initialize card-specific things if the power is off */
764 if (host
->power_mode
== MMC_POWER_OFF
)
767 omap_hsmmc_set_bus_width(host
);
769 omap_hsmmc_set_clock(host
);
771 omap_hsmmc_set_bus_mode(host
);
774 dev_dbg(mmc_dev(host
->mmc
), "context is restored: restore count %d\n",
780 * Save the MMC host context (store the number of power state changes so far).
782 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
784 host
->con
= OMAP_HSMMC_READ(host
->base
, CON
);
785 host
->hctl
= OMAP_HSMMC_READ(host
->base
, HCTL
);
786 host
->sysctl
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
787 host
->capa
= OMAP_HSMMC_READ(host
->base
, CAPA
);
792 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
797 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
804 * Send init stream sequence to card
805 * before sending IDLE command
807 static void send_init_stream(struct omap_hsmmc_host
*host
)
810 unsigned long timeout
;
812 if (host
->protect_card
)
815 disable_irq(host
->irq
);
817 OMAP_HSMMC_WRITE(host
->base
, IE
, INT_EN_MASK
);
818 OMAP_HSMMC_WRITE(host
->base
, CON
,
819 OMAP_HSMMC_READ(host
->base
, CON
) | INIT_STREAM
);
820 OMAP_HSMMC_WRITE(host
->base
, CMD
, INIT_STREAM_CMD
);
822 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
823 while ((reg
!= CC_EN
) && time_before(jiffies
, timeout
))
824 reg
= OMAP_HSMMC_READ(host
->base
, STAT
) & CC_EN
;
826 OMAP_HSMMC_WRITE(host
->base
, CON
,
827 OMAP_HSMMC_READ(host
->base
, CON
) & ~INIT_STREAM
);
829 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
830 OMAP_HSMMC_READ(host
->base
, STAT
);
832 enable_irq(host
->irq
);
836 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host
*host
)
840 if (host
->get_cover_state
)
841 r
= host
->get_cover_state(host
->dev
);
846 omap_hsmmc_show_cover_switch(struct device
*dev
, struct device_attribute
*attr
,
849 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
850 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
852 return sprintf(buf
, "%s\n",
853 omap_hsmmc_cover_is_closed(host
) ? "closed" : "open");
856 static DEVICE_ATTR(cover_switch
, S_IRUGO
, omap_hsmmc_show_cover_switch
, NULL
);
859 omap_hsmmc_show_slot_name(struct device
*dev
, struct device_attribute
*attr
,
862 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
863 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
865 return sprintf(buf
, "%s\n", mmc_pdata(host
)->name
);
868 static DEVICE_ATTR(slot_name
, S_IRUGO
, omap_hsmmc_show_slot_name
, NULL
);
871 * Configure the response type and send the cmd.
874 omap_hsmmc_start_command(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
,
875 struct mmc_data
*data
)
877 int cmdreg
= 0, resptype
= 0, cmdtype
= 0;
879 dev_vdbg(mmc_dev(host
->mmc
), "%s: CMD%d, argument 0x%08x\n",
880 mmc_hostname(host
->mmc
), cmd
->opcode
, cmd
->arg
);
883 omap_hsmmc_enable_irq(host
, cmd
);
885 host
->response_busy
= 0;
886 if (cmd
->flags
& MMC_RSP_PRESENT
) {
887 if (cmd
->flags
& MMC_RSP_136
)
889 else if (cmd
->flags
& MMC_RSP_BUSY
) {
891 host
->response_busy
= 1;
897 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
898 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
899 * a val of 0x3, rest 0x0.
901 if (cmd
== host
->mrq
->stop
)
904 cmdreg
= (cmd
->opcode
<< 24) | (resptype
<< 16) | (cmdtype
<< 22);
906 if ((host
->flags
& AUTO_CMD23
) && mmc_op_multi(cmd
->opcode
) &&
908 cmdreg
|= ACEN_ACMD23
;
909 OMAP_HSMMC_WRITE(host
->base
, SDMASA
, host
->mrq
->sbc
->arg
);
912 cmdreg
|= DP_SELECT
| MSBS
| BCE
;
913 if (data
->flags
& MMC_DATA_READ
)
922 host
->req_in_progress
= 1;
924 OMAP_HSMMC_WRITE(host
->base
, ARG
, cmd
->arg
);
925 OMAP_HSMMC_WRITE(host
->base
, CMD
, cmdreg
);
928 static struct dma_chan
*omap_hsmmc_get_dma_chan(struct omap_hsmmc_host
*host
,
929 struct mmc_data
*data
)
931 return data
->flags
& MMC_DATA_WRITE
? host
->tx_chan
: host
->rx_chan
;
934 static void omap_hsmmc_request_done(struct omap_hsmmc_host
*host
, struct mmc_request
*mrq
)
939 spin_lock_irqsave(&host
->irq_lock
, flags
);
940 host
->req_in_progress
= 0;
941 dma_ch
= host
->dma_ch
;
942 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
944 omap_hsmmc_disable_irq(host
);
945 /* Do not complete the request if DMA is still in progress */
946 if (mrq
->data
&& host
->use_dma
&& dma_ch
!= -1)
949 mmc_request_done(host
->mmc
, mrq
);
953 * Notify the transfer complete to MMC core
956 omap_hsmmc_xfer_done(struct omap_hsmmc_host
*host
, struct mmc_data
*data
)
959 struct mmc_request
*mrq
= host
->mrq
;
961 /* TC before CC from CMD6 - don't know why, but it happens */
962 if (host
->cmd
&& host
->cmd
->opcode
== 6 &&
963 host
->response_busy
) {
964 host
->response_busy
= 0;
968 omap_hsmmc_request_done(host
, mrq
);
975 data
->bytes_xfered
+= data
->blocks
* (data
->blksz
);
977 data
->bytes_xfered
= 0;
979 if (data
->stop
&& (data
->error
|| !host
->mrq
->sbc
))
980 omap_hsmmc_start_command(host
, data
->stop
, NULL
);
982 omap_hsmmc_request_done(host
, data
->mrq
);
986 * Notify the core about command completion
989 omap_hsmmc_cmd_done(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
)
991 if (host
->mrq
->sbc
&& (host
->cmd
== host
->mrq
->sbc
) &&
992 !host
->mrq
->sbc
->error
&& !(host
->flags
& AUTO_CMD23
)) {
994 omap_hsmmc_start_dma_transfer(host
);
995 omap_hsmmc_start_command(host
, host
->mrq
->cmd
,
1002 if (cmd
->flags
& MMC_RSP_PRESENT
) {
1003 if (cmd
->flags
& MMC_RSP_136
) {
1004 /* response type 2 */
1005 cmd
->resp
[3] = OMAP_HSMMC_READ(host
->base
, RSP10
);
1006 cmd
->resp
[2] = OMAP_HSMMC_READ(host
->base
, RSP32
);
1007 cmd
->resp
[1] = OMAP_HSMMC_READ(host
->base
, RSP54
);
1008 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP76
);
1010 /* response types 1, 1b, 3, 4, 5, 6 */
1011 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP10
);
1014 if ((host
->data
== NULL
&& !host
->response_busy
) || cmd
->error
)
1015 omap_hsmmc_request_done(host
, host
->mrq
);
1019 * DMA clean up for command errors
1021 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host
*host
, int errno
)
1024 unsigned long flags
;
1026 host
->data
->error
= errno
;
1028 spin_lock_irqsave(&host
->irq_lock
, flags
);
1029 dma_ch
= host
->dma_ch
;
1031 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
1033 if (host
->use_dma
&& dma_ch
!= -1) {
1034 struct dma_chan
*chan
= omap_hsmmc_get_dma_chan(host
, host
->data
);
1036 dmaengine_terminate_all(chan
);
1037 dma_unmap_sg(chan
->device
->dev
,
1038 host
->data
->sg
, host
->data
->sg_len
,
1039 mmc_get_dma_dir(host
->data
));
1041 host
->data
->host_cookie
= 0;
1047 * Readable error output
1049 #ifdef CONFIG_MMC_DEBUG
1050 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host
*host
, u32 status
)
1052 /* --- means reserved bit without definition at documentation */
1053 static const char *omap_hsmmc_status_bits
[] = {
1054 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1055 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1056 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1057 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1063 len
= sprintf(buf
, "MMC IRQ 0x%x :", status
);
1066 for (i
= 0; i
< ARRAY_SIZE(omap_hsmmc_status_bits
); i
++)
1067 if (status
& (1 << i
)) {
1068 len
= sprintf(buf
, " %s", omap_hsmmc_status_bits
[i
]);
1072 dev_vdbg(mmc_dev(host
->mmc
), "%s\n", res
);
1075 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host
*host
,
1079 #endif /* CONFIG_MMC_DEBUG */
1082 * MMC controller internal state machines reset
1084 * Used to reset command or data internal state machines, using respectively
1085 * SRC or SRD bit of SYSCTL register
1086 * Can be called from interrupt context
1088 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host
*host
,
1091 unsigned long i
= 0;
1092 unsigned long limit
= MMC_TIMEOUT_US
;
1094 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
1095 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | bit
);
1098 * OMAP4 ES2 and greater has an updated reset logic.
1099 * Monitor a 0->1 transition first
1101 if (mmc_pdata(host
)->features
& HSMMC_HAS_UPDATED_RESET
) {
1102 while ((!(OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
))
1108 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
) &&
1112 if (OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
)
1113 dev_err(mmc_dev(host
->mmc
),
1114 "Timeout waiting on controller reset in %s\n",
1118 static void hsmmc_command_incomplete(struct omap_hsmmc_host
*host
,
1119 int err
, int end_cmd
)
1122 omap_hsmmc_reset_controller_fsm(host
, SRC
);
1124 host
->cmd
->error
= err
;
1128 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1129 omap_hsmmc_dma_cleanup(host
, err
);
1130 } else if (host
->mrq
&& host
->mrq
->cmd
)
1131 host
->mrq
->cmd
->error
= err
;
1134 static void omap_hsmmc_do_irq(struct omap_hsmmc_host
*host
, int status
)
1136 struct mmc_data
*data
;
1137 int end_cmd
= 0, end_trans
= 0;
1141 dev_vdbg(mmc_dev(host
->mmc
), "IRQ Status is %x\n", status
);
1143 if (status
& ERR_EN
) {
1144 omap_hsmmc_dbg_report_irq(host
, status
);
1146 if (status
& (CTO_EN
| CCRC_EN
| CEB_EN
))
1148 if (host
->data
|| host
->response_busy
) {
1149 end_trans
= !end_cmd
;
1150 host
->response_busy
= 0;
1152 if (status
& (CTO_EN
| DTO_EN
))
1153 hsmmc_command_incomplete(host
, -ETIMEDOUT
, end_cmd
);
1154 else if (status
& (CCRC_EN
| DCRC_EN
| DEB_EN
| CEB_EN
|
1156 hsmmc_command_incomplete(host
, -EILSEQ
, end_cmd
);
1158 if (status
& ACE_EN
) {
1160 ac12
= OMAP_HSMMC_READ(host
->base
, AC12
);
1161 if (!(ac12
& ACNE
) && host
->mrq
->sbc
) {
1165 else if (ac12
& (ACCE
| ACEB
| ACIE
))
1167 host
->mrq
->sbc
->error
= error
;
1168 hsmmc_command_incomplete(host
, error
, end_cmd
);
1170 dev_dbg(mmc_dev(host
->mmc
), "AC12 err: 0x%x\n", ac12
);
1174 OMAP_HSMMC_WRITE(host
->base
, STAT
, status
);
1175 if (end_cmd
|| ((status
& CC_EN
) && host
->cmd
))
1176 omap_hsmmc_cmd_done(host
, host
->cmd
);
1177 if ((end_trans
|| (status
& TC_EN
)) && host
->mrq
)
1178 omap_hsmmc_xfer_done(host
, data
);
1182 * MMC controller IRQ handler
1184 static irqreturn_t
omap_hsmmc_irq(int irq
, void *dev_id
)
1186 struct omap_hsmmc_host
*host
= dev_id
;
1189 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
1190 while (status
& (INT_EN_MASK
| CIRQ_EN
)) {
1191 if (host
->req_in_progress
)
1192 omap_hsmmc_do_irq(host
, status
);
1194 if (status
& CIRQ_EN
)
1195 mmc_signal_sdio_irq(host
->mmc
);
1197 /* Flush posted write */
1198 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
1204 static void set_sd_bus_power(struct omap_hsmmc_host
*host
)
1208 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1209 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
1210 for (i
= 0; i
< loops_per_jiffy
; i
++) {
1211 if (OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
)
1218 * Switch MMC interface voltage ... only relevant for MMC1.
1220 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1221 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1222 * Some chips, like eMMC ones, use internal transceivers.
1224 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host
*host
, int vdd
)
1229 /* Disable the clocks */
1231 clk_disable_unprepare(host
->dbclk
);
1233 /* Turn the power off */
1234 ret
= omap_hsmmc_set_power(host
, 0, 0);
1236 /* Turn the power ON with given VDD 1.8 or 3.0v */
1238 ret
= omap_hsmmc_set_power(host
, 1, vdd
);
1240 clk_prepare_enable(host
->dbclk
);
1245 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1246 OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSCLR
);
1247 reg_val
= OMAP_HSMMC_READ(host
->base
, HCTL
);
1250 * If a MMC dual voltage card is detected, the set_ios fn calls
1251 * this fn with VDD bit set for 1.8V. Upon card removal from the
1252 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1254 * Cope with a bit of slop in the range ... per data sheets:
1255 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1256 * but recommended values are 1.71V to 1.89V
1257 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1258 * but recommended values are 2.7V to 3.3V
1260 * Board setup code shouldn't permit anything very out-of-range.
1261 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1262 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1264 if ((1 << vdd
) <= MMC_VDD_23_24
)
1269 OMAP_HSMMC_WRITE(host
->base
, HCTL
, reg_val
);
1270 set_sd_bus_power(host
);
1274 dev_err(mmc_dev(host
->mmc
), "Unable to switch operating voltage\n");
1278 /* Protect the card while the cover is open */
1279 static void omap_hsmmc_protect_card(struct omap_hsmmc_host
*host
)
1281 if (!host
->get_cover_state
)
1284 host
->reqs_blocked
= 0;
1285 if (host
->get_cover_state(host
->dev
)) {
1286 if (host
->protect_card
) {
1287 dev_info(host
->dev
, "%s: cover is closed, "
1288 "card is now accessible\n",
1289 mmc_hostname(host
->mmc
));
1290 host
->protect_card
= 0;
1293 if (!host
->protect_card
) {
1294 dev_info(host
->dev
, "%s: cover is open, "
1295 "card is now inaccessible\n",
1296 mmc_hostname(host
->mmc
));
1297 host
->protect_card
= 1;
1303 * irq handler when (cell-phone) cover is mounted/removed
1305 static irqreturn_t
omap_hsmmc_cover_irq(int irq
, void *dev_id
)
1307 struct omap_hsmmc_host
*host
= dev_id
;
1309 sysfs_notify(&host
->mmc
->class_dev
.kobj
, NULL
, "cover_switch");
1311 omap_hsmmc_protect_card(host
);
1312 mmc_detect_change(host
->mmc
, (HZ
* 200) / 1000);
1316 static void omap_hsmmc_dma_callback(void *param
)
1318 struct omap_hsmmc_host
*host
= param
;
1319 struct dma_chan
*chan
;
1320 struct mmc_data
*data
;
1321 int req_in_progress
;
1323 spin_lock_irq(&host
->irq_lock
);
1324 if (host
->dma_ch
< 0) {
1325 spin_unlock_irq(&host
->irq_lock
);
1329 data
= host
->mrq
->data
;
1330 chan
= omap_hsmmc_get_dma_chan(host
, data
);
1331 if (!data
->host_cookie
)
1332 dma_unmap_sg(chan
->device
->dev
,
1333 data
->sg
, data
->sg_len
,
1334 mmc_get_dma_dir(data
));
1336 req_in_progress
= host
->req_in_progress
;
1338 spin_unlock_irq(&host
->irq_lock
);
1340 /* If DMA has finished after TC, complete the request */
1341 if (!req_in_progress
) {
1342 struct mmc_request
*mrq
= host
->mrq
;
1345 mmc_request_done(host
->mmc
, mrq
);
1349 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host
*host
,
1350 struct mmc_data
*data
,
1351 struct omap_hsmmc_next
*next
,
1352 struct dma_chan
*chan
)
1356 if (!next
&& data
->host_cookie
&&
1357 data
->host_cookie
!= host
->next_data
.cookie
) {
1358 dev_warn(host
->dev
, "[%s] invalid cookie: data->host_cookie %d"
1359 " host->next_data.cookie %d\n",
1360 __func__
, data
->host_cookie
, host
->next_data
.cookie
);
1361 data
->host_cookie
= 0;
1364 /* Check if next job is already prepared */
1365 if (next
|| data
->host_cookie
!= host
->next_data
.cookie
) {
1366 dma_len
= dma_map_sg(chan
->device
->dev
, data
->sg
, data
->sg_len
,
1367 mmc_get_dma_dir(data
));
1370 dma_len
= host
->next_data
.dma_len
;
1371 host
->next_data
.dma_len
= 0;
1379 next
->dma_len
= dma_len
;
1380 data
->host_cookie
= ++next
->cookie
< 0 ? 1 : next
->cookie
;
1382 host
->dma_len
= dma_len
;
1388 * Routine to configure and start DMA for the MMC card
1390 static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host
*host
,
1391 struct mmc_request
*req
)
1393 struct dma_async_tx_descriptor
*tx
;
1395 struct mmc_data
*data
= req
->data
;
1396 struct dma_chan
*chan
;
1397 struct dma_slave_config cfg
= {
1398 .src_addr
= host
->mapbase
+ OMAP_HSMMC_DATA
,
1399 .dst_addr
= host
->mapbase
+ OMAP_HSMMC_DATA
,
1400 .src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
,
1401 .dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
,
1402 .src_maxburst
= data
->blksz
/ 4,
1403 .dst_maxburst
= data
->blksz
/ 4,
1406 /* Sanity check: all the SG entries must be aligned by block size. */
1407 for (i
= 0; i
< data
->sg_len
; i
++) {
1408 struct scatterlist
*sgl
;
1411 if (sgl
->length
% data
->blksz
)
1414 if ((data
->blksz
% 4) != 0)
1415 /* REVISIT: The MMC buffer increments only when MSB is written.
1416 * Return error for blksz which is non multiple of four.
1420 BUG_ON(host
->dma_ch
!= -1);
1422 chan
= omap_hsmmc_get_dma_chan(host
, data
);
1424 ret
= dmaengine_slave_config(chan
, &cfg
);
1428 ret
= omap_hsmmc_pre_dma_transfer(host
, data
, NULL
, chan
);
1432 tx
= dmaengine_prep_slave_sg(chan
, data
->sg
, data
->sg_len
,
1433 data
->flags
& MMC_DATA_WRITE
? DMA_MEM_TO_DEV
: DMA_DEV_TO_MEM
,
1434 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1436 dev_err(mmc_dev(host
->mmc
), "prep_slave_sg() failed\n");
1437 /* FIXME: cleanup */
1441 tx
->callback
= omap_hsmmc_dma_callback
;
1442 tx
->callback_param
= host
;
1445 dmaengine_submit(tx
);
1452 static void set_data_timeout(struct omap_hsmmc_host
*host
,
1453 unsigned long long timeout_ns
,
1454 unsigned int timeout_clks
)
1456 unsigned long long timeout
= timeout_ns
;
1457 unsigned int cycle_ns
;
1458 uint32_t reg
, clkd
, dto
= 0;
1460 reg
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
1461 clkd
= (reg
& CLKD_MASK
) >> CLKD_SHIFT
;
1465 cycle_ns
= 1000000000 / (host
->clk_rate
/ clkd
);
1466 do_div(timeout
, cycle_ns
);
1467 timeout
+= timeout_clks
;
1469 while ((timeout
& 0x80000000) == 0) {
1486 reg
|= dto
<< DTO_SHIFT
;
1487 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, reg
);
1490 static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host
*host
)
1492 struct mmc_request
*req
= host
->mrq
;
1493 struct dma_chan
*chan
;
1497 OMAP_HSMMC_WRITE(host
->base
, BLK
, (req
->data
->blksz
)
1498 | (req
->data
->blocks
<< 16));
1499 set_data_timeout(host
, req
->data
->timeout_ns
,
1500 req
->data
->timeout_clks
);
1501 chan
= omap_hsmmc_get_dma_chan(host
, req
->data
);
1502 dma_async_issue_pending(chan
);
1506 * Configure block length for MMC/SD cards and initiate the transfer.
1509 omap_hsmmc_prepare_data(struct omap_hsmmc_host
*host
, struct mmc_request
*req
)
1512 unsigned long long timeout
;
1514 host
->data
= req
->data
;
1516 if (req
->data
== NULL
) {
1517 OMAP_HSMMC_WRITE(host
->base
, BLK
, 0);
1518 if (req
->cmd
->flags
& MMC_RSP_BUSY
) {
1519 timeout
= req
->cmd
->busy_timeout
* NSEC_PER_MSEC
;
1522 * Set an arbitrary 100ms data timeout for commands with
1523 * busy signal and no indication of busy_timeout.
1526 timeout
= 100000000U;
1528 set_data_timeout(host
, timeout
, 0);
1533 if (host
->use_dma
) {
1534 ret
= omap_hsmmc_setup_dma_transfer(host
, req
);
1536 dev_err(mmc_dev(host
->mmc
), "MMC start dma failure\n");
1543 static void omap_hsmmc_post_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
1546 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1547 struct mmc_data
*data
= mrq
->data
;
1549 if (host
->use_dma
&& data
->host_cookie
) {
1550 struct dma_chan
*c
= omap_hsmmc_get_dma_chan(host
, data
);
1552 dma_unmap_sg(c
->device
->dev
, data
->sg
, data
->sg_len
,
1553 mmc_get_dma_dir(data
));
1554 data
->host_cookie
= 0;
1558 static void omap_hsmmc_pre_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1560 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1562 if (mrq
->data
->host_cookie
) {
1563 mrq
->data
->host_cookie
= 0;
1567 if (host
->use_dma
) {
1568 struct dma_chan
*c
= omap_hsmmc_get_dma_chan(host
, mrq
->data
);
1570 if (omap_hsmmc_pre_dma_transfer(host
, mrq
->data
,
1571 &host
->next_data
, c
))
1572 mrq
->data
->host_cookie
= 0;
1577 * Request function. for read/write operation
1579 static void omap_hsmmc_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
1581 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1584 BUG_ON(host
->req_in_progress
);
1585 BUG_ON(host
->dma_ch
!= -1);
1586 if (host
->protect_card
) {
1587 if (host
->reqs_blocked
< 3) {
1589 * Ensure the controller is left in a consistent
1590 * state by resetting the command and data state
1593 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1594 omap_hsmmc_reset_controller_fsm(host
, SRC
);
1595 host
->reqs_blocked
+= 1;
1597 req
->cmd
->error
= -EBADF
;
1599 req
->data
->error
= -EBADF
;
1600 req
->cmd
->retries
= 0;
1601 mmc_request_done(mmc
, req
);
1603 } else if (host
->reqs_blocked
)
1604 host
->reqs_blocked
= 0;
1605 WARN_ON(host
->mrq
!= NULL
);
1607 host
->clk_rate
= clk_get_rate(host
->fclk
);
1608 err
= omap_hsmmc_prepare_data(host
, req
);
1610 req
->cmd
->error
= err
;
1612 req
->data
->error
= err
;
1614 mmc_request_done(mmc
, req
);
1617 if (req
->sbc
&& !(host
->flags
& AUTO_CMD23
)) {
1618 omap_hsmmc_start_command(host
, req
->sbc
, NULL
);
1622 omap_hsmmc_start_dma_transfer(host
);
1623 omap_hsmmc_start_command(host
, req
->cmd
, req
->data
);
1626 /* Routine to configure clock values. Exposed API to core */
1627 static void omap_hsmmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1629 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1630 int do_send_init_stream
= 0;
1632 if (ios
->power_mode
!= host
->power_mode
) {
1633 switch (ios
->power_mode
) {
1635 omap_hsmmc_set_power(host
, 0, 0);
1638 omap_hsmmc_set_power(host
, 1, ios
->vdd
);
1641 do_send_init_stream
= 1;
1644 host
->power_mode
= ios
->power_mode
;
1647 /* FIXME: set registers based only on changes to ios */
1649 omap_hsmmc_set_bus_width(host
);
1651 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
1652 /* Only MMC1 can interface at 3V without some flavor
1653 * of external transceiver; but they all handle 1.8V.
1655 if ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSDET
) &&
1656 (ios
->vdd
== DUAL_VOLT_OCR_BIT
)) {
1658 * The mmc_select_voltage fn of the core does
1659 * not seem to set the power_mode to
1660 * MMC_POWER_UP upon recalculating the voltage.
1663 if (omap_hsmmc_switch_opcond(host
, ios
->vdd
) != 0)
1664 dev_dbg(mmc_dev(host
->mmc
),
1665 "Switch operation failed\n");
1669 omap_hsmmc_set_clock(host
);
1671 if (do_send_init_stream
)
1672 send_init_stream(host
);
1674 omap_hsmmc_set_bus_mode(host
);
1677 static int omap_hsmmc_get_cd(struct mmc_host
*mmc
)
1679 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1681 if (!host
->card_detect
)
1683 return host
->card_detect(host
->dev
);
1686 static void omap_hsmmc_init_card(struct mmc_host
*mmc
, struct mmc_card
*card
)
1688 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1690 if (mmc_pdata(host
)->init_card
)
1691 mmc_pdata(host
)->init_card(card
);
1694 static void omap_hsmmc_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1696 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1698 unsigned long flags
;
1700 spin_lock_irqsave(&host
->irq_lock
, flags
);
1702 con
= OMAP_HSMMC_READ(host
->base
, CON
);
1703 irq_mask
= OMAP_HSMMC_READ(host
->base
, ISE
);
1705 host
->flags
|= HSMMC_SDIO_IRQ_ENABLED
;
1706 irq_mask
|= CIRQ_EN
;
1707 con
|= CTPL
| CLKEXTFREE
;
1709 host
->flags
&= ~HSMMC_SDIO_IRQ_ENABLED
;
1710 irq_mask
&= ~CIRQ_EN
;
1711 con
&= ~(CTPL
| CLKEXTFREE
);
1713 OMAP_HSMMC_WRITE(host
->base
, CON
, con
);
1714 OMAP_HSMMC_WRITE(host
->base
, IE
, irq_mask
);
1717 * if enable, piggy back detection on current request
1718 * but always disable immediately
1720 if (!host
->req_in_progress
|| !enable
)
1721 OMAP_HSMMC_WRITE(host
->base
, ISE
, irq_mask
);
1723 /* flush posted write */
1724 OMAP_HSMMC_READ(host
->base
, IE
);
1726 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
1729 static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host
*host
)
1734 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1735 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1736 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1737 * with functional clock disabled.
1739 if (!host
->dev
->of_node
|| !host
->wake_irq
)
1742 ret
= dev_pm_set_dedicated_wake_irq(host
->dev
, host
->wake_irq
);
1744 dev_err(mmc_dev(host
->mmc
), "Unable to request wake IRQ\n");
1749 * Some omaps don't have wake-up path from deeper idle states
1750 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1752 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SWAKEUP_MISSING
) {
1753 struct pinctrl
*p
= devm_pinctrl_get(host
->dev
);
1758 if (IS_ERR(pinctrl_lookup_state(p
, PINCTRL_STATE_DEFAULT
))) {
1759 dev_info(host
->dev
, "missing default pinctrl state\n");
1760 devm_pinctrl_put(p
);
1765 if (IS_ERR(pinctrl_lookup_state(p
, PINCTRL_STATE_IDLE
))) {
1766 dev_info(host
->dev
, "missing idle pinctrl state\n");
1767 devm_pinctrl_put(p
);
1771 devm_pinctrl_put(p
);
1774 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1775 OMAP_HSMMC_READ(host
->base
, HCTL
) | IWE
);
1779 dev_pm_clear_wake_irq(host
->dev
);
1781 dev_warn(host
->dev
, "no SDIO IRQ support, falling back to polling\n");
1786 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host
*host
)
1788 u32 hctl
, capa
, value
;
1790 /* Only MMC1 supports 3.0V */
1791 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
1799 value
= OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDVS_MASK
;
1800 OMAP_HSMMC_WRITE(host
->base
, HCTL
, value
| hctl
);
1802 value
= OMAP_HSMMC_READ(host
->base
, CAPA
);
1803 OMAP_HSMMC_WRITE(host
->base
, CAPA
, value
| capa
);
1805 /* Set SD bus power bit */
1806 set_sd_bus_power(host
);
1809 static int omap_hsmmc_multi_io_quirk(struct mmc_card
*card
,
1810 unsigned int direction
, int blk_size
)
1812 /* This controller can't do multiblock reads due to hw bugs */
1813 if (direction
== MMC_DATA_READ
)
1819 static struct mmc_host_ops omap_hsmmc_ops
= {
1820 .post_req
= omap_hsmmc_post_req
,
1821 .pre_req
= omap_hsmmc_pre_req
,
1822 .request
= omap_hsmmc_request
,
1823 .set_ios
= omap_hsmmc_set_ios
,
1824 .get_cd
= omap_hsmmc_get_cd
,
1825 .get_ro
= mmc_gpio_get_ro
,
1826 .init_card
= omap_hsmmc_init_card
,
1827 .enable_sdio_irq
= omap_hsmmc_enable_sdio_irq
,
1830 #ifdef CONFIG_DEBUG_FS
1832 static int omap_hsmmc_regs_show(struct seq_file
*s
, void *data
)
1834 struct mmc_host
*mmc
= s
->private;
1835 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1837 seq_printf(s
, "mmc%d:\n", mmc
->index
);
1838 seq_printf(s
, "sdio irq mode\t%s\n",
1839 (mmc
->caps
& MMC_CAP_SDIO_IRQ
) ? "interrupt" : "polling");
1841 if (mmc
->caps
& MMC_CAP_SDIO_IRQ
) {
1842 seq_printf(s
, "sdio irq \t%s\n",
1843 (host
->flags
& HSMMC_SDIO_IRQ_ENABLED
) ? "enabled"
1846 seq_printf(s
, "ctx_loss:\t%d\n", host
->context_loss
);
1848 pm_runtime_get_sync(host
->dev
);
1849 seq_puts(s
, "\nregs:\n");
1850 seq_printf(s
, "CON:\t\t0x%08x\n",
1851 OMAP_HSMMC_READ(host
->base
, CON
));
1852 seq_printf(s
, "PSTATE:\t\t0x%08x\n",
1853 OMAP_HSMMC_READ(host
->base
, PSTATE
));
1854 seq_printf(s
, "HCTL:\t\t0x%08x\n",
1855 OMAP_HSMMC_READ(host
->base
, HCTL
));
1856 seq_printf(s
, "SYSCTL:\t\t0x%08x\n",
1857 OMAP_HSMMC_READ(host
->base
, SYSCTL
));
1858 seq_printf(s
, "IE:\t\t0x%08x\n",
1859 OMAP_HSMMC_READ(host
->base
, IE
));
1860 seq_printf(s
, "ISE:\t\t0x%08x\n",
1861 OMAP_HSMMC_READ(host
->base
, ISE
));
1862 seq_printf(s
, "CAPA:\t\t0x%08x\n",
1863 OMAP_HSMMC_READ(host
->base
, CAPA
));
1865 pm_runtime_mark_last_busy(host
->dev
);
1866 pm_runtime_put_autosuspend(host
->dev
);
1871 static int omap_hsmmc_regs_open(struct inode
*inode
, struct file
*file
)
1873 return single_open(file
, omap_hsmmc_regs_show
, inode
->i_private
);
1876 static const struct file_operations mmc_regs_fops
= {
1877 .open
= omap_hsmmc_regs_open
,
1879 .llseek
= seq_lseek
,
1880 .release
= single_release
,
1883 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
1885 if (mmc
->debugfs_root
)
1886 debugfs_create_file("regs", S_IRUSR
, mmc
->debugfs_root
,
1887 mmc
, &mmc_regs_fops
);
1892 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
1899 static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data
= {
1900 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1901 .controller_flags
= OMAP_HSMMC_BROKEN_MULTIBLOCK_READ
,
1904 static const struct omap_mmc_of_data omap4_mmc_of_data
= {
1905 .reg_offset
= 0x100,
1907 static const struct omap_mmc_of_data am33xx_mmc_of_data
= {
1908 .reg_offset
= 0x100,
1909 .controller_flags
= OMAP_HSMMC_SWAKEUP_MISSING
,
1912 static const struct of_device_id omap_mmc_of_match
[] = {
1914 .compatible
= "ti,omap2-hsmmc",
1917 .compatible
= "ti,omap3-pre-es3-hsmmc",
1918 .data
= &omap3_pre_es3_mmc_of_data
,
1921 .compatible
= "ti,omap3-hsmmc",
1924 .compatible
= "ti,omap4-hsmmc",
1925 .data
= &omap4_mmc_of_data
,
1928 .compatible
= "ti,am33xx-hsmmc",
1929 .data
= &am33xx_mmc_of_data
,
1933 MODULE_DEVICE_TABLE(of
, omap_mmc_of_match
);
1935 static struct omap_hsmmc_platform_data
*of_get_hsmmc_pdata(struct device
*dev
)
1937 struct omap_hsmmc_platform_data
*pdata
, *legacy
;
1938 struct device_node
*np
= dev
->of_node
;
1940 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
1942 return ERR_PTR(-ENOMEM
); /* out of memory */
1944 legacy
= dev_get_platdata(dev
);
1945 if (legacy
&& legacy
->name
)
1946 pdata
->name
= legacy
->name
;
1948 if (of_find_property(np
, "ti,dual-volt", NULL
))
1949 pdata
->controller_flags
|= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
;
1951 pdata
->gpio_cd
= -EINVAL
;
1952 pdata
->gpio_cod
= -EINVAL
;
1953 pdata
->gpio_wp
= -EINVAL
;
1955 if (of_find_property(np
, "ti,non-removable", NULL
)) {
1956 pdata
->nonremovable
= true;
1957 pdata
->no_regulator_off_init
= true;
1960 if (of_find_property(np
, "ti,needs-special-reset", NULL
))
1961 pdata
->features
|= HSMMC_HAS_UPDATED_RESET
;
1963 if (of_find_property(np
, "ti,needs-special-hs-handling", NULL
))
1964 pdata
->features
|= HSMMC_HAS_HSPE_SUPPORT
;
1969 static inline struct omap_hsmmc_platform_data
1970 *of_get_hsmmc_pdata(struct device
*dev
)
1972 return ERR_PTR(-EINVAL
);
1976 static int omap_hsmmc_probe(struct platform_device
*pdev
)
1978 struct omap_hsmmc_platform_data
*pdata
= pdev
->dev
.platform_data
;
1979 struct mmc_host
*mmc
;
1980 struct omap_hsmmc_host
*host
= NULL
;
1981 struct resource
*res
;
1983 const struct of_device_id
*match
;
1984 const struct omap_mmc_of_data
*data
;
1987 match
= of_match_device(of_match_ptr(omap_mmc_of_match
), &pdev
->dev
);
1989 pdata
= of_get_hsmmc_pdata(&pdev
->dev
);
1992 return PTR_ERR(pdata
);
1996 pdata
->reg_offset
= data
->reg_offset
;
1997 pdata
->controller_flags
|= data
->controller_flags
;
2001 if (pdata
== NULL
) {
2002 dev_err(&pdev
->dev
, "Platform Data is missing\n");
2006 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2007 irq
= platform_get_irq(pdev
, 0);
2008 if (res
== NULL
|| irq
< 0)
2011 base
= devm_ioremap_resource(&pdev
->dev
, res
);
2013 return PTR_ERR(base
);
2015 mmc
= mmc_alloc_host(sizeof(struct omap_hsmmc_host
), &pdev
->dev
);
2021 ret
= mmc_of_parse(mmc
);
2025 host
= mmc_priv(mmc
);
2027 host
->pdata
= pdata
;
2028 host
->dev
= &pdev
->dev
;
2032 host
->mapbase
= res
->start
+ pdata
->reg_offset
;
2033 host
->base
= base
+ pdata
->reg_offset
;
2034 host
->power_mode
= MMC_POWER_OFF
;
2035 host
->next_data
.cookie
= 1;
2036 host
->pbias_enabled
= 0;
2037 host
->vqmmc_enabled
= 0;
2039 ret
= omap_hsmmc_gpio_init(mmc
, host
, pdata
);
2043 platform_set_drvdata(pdev
, host
);
2045 if (pdev
->dev
.of_node
)
2046 host
->wake_irq
= irq_of_parse_and_map(pdev
->dev
.of_node
, 1);
2048 mmc
->ops
= &omap_hsmmc_ops
;
2050 mmc
->f_min
= OMAP_MMC_MIN_CLOCK
;
2052 if (pdata
->max_freq
> 0)
2053 mmc
->f_max
= pdata
->max_freq
;
2054 else if (mmc
->f_max
== 0)
2055 mmc
->f_max
= OMAP_MMC_MAX_CLOCK
;
2057 spin_lock_init(&host
->irq_lock
);
2059 host
->fclk
= devm_clk_get(&pdev
->dev
, "fck");
2060 if (IS_ERR(host
->fclk
)) {
2061 ret
= PTR_ERR(host
->fclk
);
2066 if (host
->pdata
->controller_flags
& OMAP_HSMMC_BROKEN_MULTIBLOCK_READ
) {
2067 dev_info(&pdev
->dev
, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2068 omap_hsmmc_ops
.multi_io_quirk
= omap_hsmmc_multi_io_quirk
;
2071 device_init_wakeup(&pdev
->dev
, true);
2072 pm_runtime_enable(host
->dev
);
2073 pm_runtime_get_sync(host
->dev
);
2074 pm_runtime_set_autosuspend_delay(host
->dev
, MMC_AUTOSUSPEND_DELAY
);
2075 pm_runtime_use_autosuspend(host
->dev
);
2077 omap_hsmmc_context_save(host
);
2079 host
->dbclk
= devm_clk_get(&pdev
->dev
, "mmchsdb_fck");
2081 * MMC can still work without debounce clock.
2083 if (IS_ERR(host
->dbclk
)) {
2085 } else if (clk_prepare_enable(host
->dbclk
) != 0) {
2086 dev_warn(mmc_dev(host
->mmc
), "Failed to enable debounce clk\n");
2090 /* Since we do only SG emulation, we can have as many segs
2092 mmc
->max_segs
= 1024;
2094 mmc
->max_blk_size
= 512; /* Block Length at max can be 1024 */
2095 mmc
->max_blk_count
= 0xFFFF; /* No. of Blocks is 16 bits */
2096 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
2097 mmc
->max_seg_size
= mmc
->max_req_size
;
2099 mmc
->caps
|= MMC_CAP_MMC_HIGHSPEED
| MMC_CAP_SD_HIGHSPEED
|
2100 MMC_CAP_WAIT_WHILE_BUSY
| MMC_CAP_ERASE
;
2102 mmc
->caps
|= mmc_pdata(host
)->caps
;
2103 if (mmc
->caps
& MMC_CAP_8_BIT_DATA
)
2104 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
2106 if (mmc_pdata(host
)->nonremovable
)
2107 mmc
->caps
|= MMC_CAP_NONREMOVABLE
;
2109 mmc
->pm_caps
|= mmc_pdata(host
)->pm_caps
;
2111 omap_hsmmc_conf_bus_power(host
);
2113 host
->rx_chan
= dma_request_chan(&pdev
->dev
, "rx");
2114 if (IS_ERR(host
->rx_chan
)) {
2115 dev_err(mmc_dev(host
->mmc
), "RX DMA channel request failed\n");
2116 ret
= PTR_ERR(host
->rx_chan
);
2120 host
->tx_chan
= dma_request_chan(&pdev
->dev
, "tx");
2121 if (IS_ERR(host
->tx_chan
)) {
2122 dev_err(mmc_dev(host
->mmc
), "TX DMA channel request failed\n");
2123 ret
= PTR_ERR(host
->tx_chan
);
2127 /* Request IRQ for MMC operations */
2128 ret
= devm_request_irq(&pdev
->dev
, host
->irq
, omap_hsmmc_irq
, 0,
2129 mmc_hostname(mmc
), host
);
2131 dev_err(mmc_dev(host
->mmc
), "Unable to grab HSMMC IRQ\n");
2135 ret
= omap_hsmmc_reg_get(host
);
2139 if (!mmc
->ocr_avail
)
2140 mmc
->ocr_avail
= mmc_pdata(host
)->ocr_mask
;
2142 omap_hsmmc_disable_irq(host
);
2145 * For now, only support SDIO interrupt if we have a separate
2146 * wake-up interrupt configured from device tree. This is because
2147 * the wake-up interrupt is needed for idle state and some
2148 * platforms need special quirks. And we don't want to add new
2149 * legacy mux platform init code callbacks any longer as we
2150 * are moving to DT based booting anyways.
2152 ret
= omap_hsmmc_configure_wake_irq(host
);
2154 mmc
->caps
|= MMC_CAP_SDIO_IRQ
;
2156 omap_hsmmc_protect_card(host
);
2160 if (mmc_pdata(host
)->name
!= NULL
) {
2161 ret
= device_create_file(&mmc
->class_dev
, &dev_attr_slot_name
);
2165 if (host
->get_cover_state
) {
2166 ret
= device_create_file(&mmc
->class_dev
,
2167 &dev_attr_cover_switch
);
2172 omap_hsmmc_debugfs(mmc
);
2173 pm_runtime_mark_last_busy(host
->dev
);
2174 pm_runtime_put_autosuspend(host
->dev
);
2179 mmc_remove_host(mmc
);
2181 device_init_wakeup(&pdev
->dev
, false);
2182 if (!IS_ERR_OR_NULL(host
->tx_chan
))
2183 dma_release_channel(host
->tx_chan
);
2184 if (!IS_ERR_OR_NULL(host
->rx_chan
))
2185 dma_release_channel(host
->rx_chan
);
2186 pm_runtime_dont_use_autosuspend(host
->dev
);
2187 pm_runtime_put_sync(host
->dev
);
2188 pm_runtime_disable(host
->dev
);
2190 clk_disable_unprepare(host
->dbclk
);
2198 static int omap_hsmmc_remove(struct platform_device
*pdev
)
2200 struct omap_hsmmc_host
*host
= platform_get_drvdata(pdev
);
2202 pm_runtime_get_sync(host
->dev
);
2203 mmc_remove_host(host
->mmc
);
2205 dma_release_channel(host
->tx_chan
);
2206 dma_release_channel(host
->rx_chan
);
2208 pm_runtime_dont_use_autosuspend(host
->dev
);
2209 pm_runtime_put_sync(host
->dev
);
2210 pm_runtime_disable(host
->dev
);
2211 device_init_wakeup(&pdev
->dev
, false);
2213 clk_disable_unprepare(host
->dbclk
);
2215 mmc_free_host(host
->mmc
);
2220 #ifdef CONFIG_PM_SLEEP
2221 static int omap_hsmmc_suspend(struct device
*dev
)
2223 struct omap_hsmmc_host
*host
= dev_get_drvdata(dev
);
2228 pm_runtime_get_sync(host
->dev
);
2230 if (!(host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
)) {
2231 OMAP_HSMMC_WRITE(host
->base
, ISE
, 0);
2232 OMAP_HSMMC_WRITE(host
->base
, IE
, 0);
2233 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
2234 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
2235 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDBP
);
2239 clk_disable_unprepare(host
->dbclk
);
2241 pm_runtime_put_sync(host
->dev
);
2245 /* Routine to resume the MMC device */
2246 static int omap_hsmmc_resume(struct device
*dev
)
2248 struct omap_hsmmc_host
*host
= dev_get_drvdata(dev
);
2253 pm_runtime_get_sync(host
->dev
);
2256 clk_prepare_enable(host
->dbclk
);
2258 if (!(host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
))
2259 omap_hsmmc_conf_bus_power(host
);
2261 omap_hsmmc_protect_card(host
);
2262 pm_runtime_mark_last_busy(host
->dev
);
2263 pm_runtime_put_autosuspend(host
->dev
);
2268 static int omap_hsmmc_runtime_suspend(struct device
*dev
)
2270 struct omap_hsmmc_host
*host
;
2271 unsigned long flags
;
2274 host
= platform_get_drvdata(to_platform_device(dev
));
2275 omap_hsmmc_context_save(host
);
2276 dev_dbg(dev
, "disabled\n");
2278 spin_lock_irqsave(&host
->irq_lock
, flags
);
2279 if ((host
->mmc
->caps
& MMC_CAP_SDIO_IRQ
) &&
2280 (host
->flags
& HSMMC_SDIO_IRQ_ENABLED
)) {
2281 /* disable sdio irq handling to prevent race */
2282 OMAP_HSMMC_WRITE(host
->base
, ISE
, 0);
2283 OMAP_HSMMC_WRITE(host
->base
, IE
, 0);
2285 if (!(OMAP_HSMMC_READ(host
->base
, PSTATE
) & DLEV_DAT(1))) {
2287 * dat1 line low, pending sdio irq
2288 * race condition: possible irq handler running on
2291 dev_dbg(dev
, "pending sdio irq, abort suspend\n");
2292 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
2293 OMAP_HSMMC_WRITE(host
->base
, ISE
, CIRQ_EN
);
2294 OMAP_HSMMC_WRITE(host
->base
, IE
, CIRQ_EN
);
2295 pm_runtime_mark_last_busy(dev
);
2300 pinctrl_pm_select_idle_state(dev
);
2302 pinctrl_pm_select_idle_state(dev
);
2306 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
2310 static int omap_hsmmc_runtime_resume(struct device
*dev
)
2312 struct omap_hsmmc_host
*host
;
2313 unsigned long flags
;
2315 host
= platform_get_drvdata(to_platform_device(dev
));
2316 omap_hsmmc_context_restore(host
);
2317 dev_dbg(dev
, "enabled\n");
2319 spin_lock_irqsave(&host
->irq_lock
, flags
);
2320 if ((host
->mmc
->caps
& MMC_CAP_SDIO_IRQ
) &&
2321 (host
->flags
& HSMMC_SDIO_IRQ_ENABLED
)) {
2323 pinctrl_pm_select_default_state(host
->dev
);
2325 /* irq lost, if pinmux incorrect */
2326 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
2327 OMAP_HSMMC_WRITE(host
->base
, ISE
, CIRQ_EN
);
2328 OMAP_HSMMC_WRITE(host
->base
, IE
, CIRQ_EN
);
2330 pinctrl_pm_select_default_state(host
->dev
);
2332 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
2336 static struct dev_pm_ops omap_hsmmc_dev_pm_ops
= {
2337 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend
, omap_hsmmc_resume
)
2338 .runtime_suspend
= omap_hsmmc_runtime_suspend
,
2339 .runtime_resume
= omap_hsmmc_runtime_resume
,
2342 static struct platform_driver omap_hsmmc_driver
= {
2343 .probe
= omap_hsmmc_probe
,
2344 .remove
= omap_hsmmc_remove
,
2346 .name
= DRIVER_NAME
,
2347 .pm
= &omap_hsmmc_dev_pm_ops
,
2348 .of_match_table
= of_match_ptr(omap_mmc_of_match
),
2352 module_platform_driver(omap_hsmmc_driver
);
2353 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2354 MODULE_LICENSE("GPL");
2355 MODULE_ALIAS("platform:" DRIVER_NAME
);
2356 MODULE_AUTHOR("Texas Instruments Inc");