]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - drivers/mmc/host/sdhci.c
projects / mirror_ubuntu-artful-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mmc: sdhci: prepare DMA address/size quirk handling consolidation
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
44 #endif
45
46 #define MAX_TUNING_LOOP 40
47
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
50
51 static void sdhci_finish_data(struct sdhci_host *);
52
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_do_get_cd(struct sdhci_host *host);
57
58 #ifdef CONFIG_PM
59 static int sdhci_runtime_pm_get(struct sdhci_host *host);
60 static int sdhci_runtime_pm_put(struct sdhci_host *host);
61 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
62 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
63 #else
64 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
65 {
66 return 0;
67 }
68 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
69 {
70 return 0;
71 }
72 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
73 {
74 }
75 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
76 {
77 }
78 #endif
79
80 static void sdhci_dumpregs(struct sdhci_host *host)
81 {
82 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
83 mmc_hostname(host->mmc));
84
85 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
86 sdhci_readl(host, SDHCI_DMA_ADDRESS),
87 sdhci_readw(host, SDHCI_HOST_VERSION));
88 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
89 sdhci_readw(host, SDHCI_BLOCK_SIZE),
90 sdhci_readw(host, SDHCI_BLOCK_COUNT));
91 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
92 sdhci_readl(host, SDHCI_ARGUMENT),
93 sdhci_readw(host, SDHCI_TRANSFER_MODE));
94 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
95 sdhci_readl(host, SDHCI_PRESENT_STATE),
96 sdhci_readb(host, SDHCI_HOST_CONTROL));
97 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
98 sdhci_readb(host, SDHCI_POWER_CONTROL),
99 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
100 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
101 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
102 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
103 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
104 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
105 sdhci_readl(host, SDHCI_INT_STATUS));
106 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
107 sdhci_readl(host, SDHCI_INT_ENABLE),
108 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
109 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
110 sdhci_readw(host, SDHCI_ACMD12_ERR),
111 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
112 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
113 sdhci_readl(host, SDHCI_CAPABILITIES),
114 sdhci_readl(host, SDHCI_CAPABILITIES_1));
115 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
116 sdhci_readw(host, SDHCI_COMMAND),
117 sdhci_readl(host, SDHCI_MAX_CURRENT));
118 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
119 sdhci_readw(host, SDHCI_HOST_CONTROL2));
120
121 if (host->flags & SDHCI_USE_ADMA) {
122 if (host->flags & SDHCI_USE_64_BIT_DMA)
123 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
124 readl(host->ioaddr + SDHCI_ADMA_ERROR),
125 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
126 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
127 else
128 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
129 readl(host->ioaddr + SDHCI_ADMA_ERROR),
130 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
131 }
132
133 pr_debug(DRIVER_NAME ": ===========================================\n");
134 }
135
136 /*****************************************************************************\
137 * *
138 * Low level functions *
139 * *
140 \*****************************************************************************/
141
142 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
143 {
144 u32 present;
145
146 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
147 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
148 return;
149
150 if (enable) {
151 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
152 SDHCI_CARD_PRESENT;
153
154 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
155 SDHCI_INT_CARD_INSERT;
156 } else {
157 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
158 }
159
160 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
161 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
162 }
163
164 static void sdhci_enable_card_detection(struct sdhci_host *host)
165 {
166 sdhci_set_card_detection(host, true);
167 }
168
169 static void sdhci_disable_card_detection(struct sdhci_host *host)
170 {
171 sdhci_set_card_detection(host, false);
172 }
173
174 void sdhci_reset(struct sdhci_host *host, u8 mask)
175 {
176 unsigned long timeout;
177
178 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
179
180 if (mask & SDHCI_RESET_ALL) {
181 host->clock = 0;
182 /* Reset-all turns off SD Bus Power */
183 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
184 sdhci_runtime_pm_bus_off(host);
185 }
186
187 /* Wait max 100 ms */
188 timeout = 100;
189
190 /* hw clears the bit when it's done */
191 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
192 if (timeout == 0) {
193 pr_err("%s: Reset 0x%x never completed.\n",
194 mmc_hostname(host->mmc), (int)mask);
195 sdhci_dumpregs(host);
196 return;
197 }
198 timeout--;
199 mdelay(1);
200 }
201 }
202 EXPORT_SYMBOL_GPL(sdhci_reset);
203
204 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
205 {
206 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
207 if (!sdhci_do_get_cd(host))
208 return;
209 }
210
211 host->ops->reset(host, mask);
212
213 if (mask & SDHCI_RESET_ALL) {
214 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
215 if (host->ops->enable_dma)
216 host->ops->enable_dma(host);
217 }
218
219 /* Resetting the controller clears many */
220 host->preset_enabled = false;
221 }
222 }
223
224 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
225
226 static void sdhci_init(struct sdhci_host *host, int soft)
227 {
228 if (soft)
229 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
230 else
231 sdhci_do_reset(host, SDHCI_RESET_ALL);
232
233 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
234 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
235 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
236 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
237 SDHCI_INT_RESPONSE;
238
239 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
240 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
241
242 if (soft) {
243 /* force clock reconfiguration */
244 host->clock = 0;
245 sdhci_set_ios(host->mmc, &host->mmc->ios);
246 }
247 }
248
249 static void sdhci_reinit(struct sdhci_host *host)
250 {
251 sdhci_init(host, 0);
252 sdhci_enable_card_detection(host);
253 }
254
255 static void sdhci_activate_led(struct sdhci_host *host)
256 {
257 u8 ctrl;
258
259 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
260 ctrl |= SDHCI_CTRL_LED;
261 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
262 }
263
264 static void sdhci_deactivate_led(struct sdhci_host *host)
265 {
266 u8 ctrl;
267
268 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
269 ctrl &= ~SDHCI_CTRL_LED;
270 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
271 }
272
273 #ifdef SDHCI_USE_LEDS_CLASS
274 static void sdhci_led_control(struct led_classdev *led,
275 enum led_brightness brightness)
276 {
277 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
278 unsigned long flags;
279
280 spin_lock_irqsave(&host->lock, flags);
281
282 if (host->runtime_suspended)
283 goto out;
284
285 if (brightness == LED_OFF)
286 sdhci_deactivate_led(host);
287 else
288 sdhci_activate_led(host);
289 out:
290 spin_unlock_irqrestore(&host->lock, flags);
291 }
292 #endif
293
294 /*****************************************************************************\
295 * *
296 * Core functions *
297 * *
298 \*****************************************************************************/
299
300 static void sdhci_read_block_pio(struct sdhci_host *host)
301 {
302 unsigned long flags;
303 size_t blksize, len, chunk;
304 u32 uninitialized_var(scratch);
305 u8 *buf;
306
307 DBG("PIO reading\n");
308
309 blksize = host->data->blksz;
310 chunk = 0;
311
312 local_irq_save(flags);
313
314 while (blksize) {
315 BUG_ON(!sg_miter_next(&host->sg_miter));
316
317 len = min(host->sg_miter.length, blksize);
318
319 blksize -= len;
320 host->sg_miter.consumed = len;
321
322 buf = host->sg_miter.addr;
323
324 while (len) {
325 if (chunk == 0) {
326 scratch = sdhci_readl(host, SDHCI_BUFFER);
327 chunk = 4;
328 }
329
330 *buf = scratch & 0xFF;
331
332 buf++;
333 scratch >>= 8;
334 chunk--;
335 len--;
336 }
337 }
338
339 sg_miter_stop(&host->sg_miter);
340
341 local_irq_restore(flags);
342 }
343
344 static void sdhci_write_block_pio(struct sdhci_host *host)
345 {
346 unsigned long flags;
347 size_t blksize, len, chunk;
348 u32 scratch;
349 u8 *buf;
350
351 DBG("PIO writing\n");
352
353 blksize = host->data->blksz;
354 chunk = 0;
355 scratch = 0;
356
357 local_irq_save(flags);
358
359 while (blksize) {
360 BUG_ON(!sg_miter_next(&host->sg_miter));
361
362 len = min(host->sg_miter.length, blksize);
363
364 blksize -= len;
365 host->sg_miter.consumed = len;
366
367 buf = host->sg_miter.addr;
368
369 while (len) {
370 scratch |= (u32)*buf << (chunk * 8);
371
372 buf++;
373 chunk++;
374 len--;
375
376 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
377 sdhci_writel(host, scratch, SDHCI_BUFFER);
378 chunk = 0;
379 scratch = 0;
380 }
381 }
382 }
383
384 sg_miter_stop(&host->sg_miter);
385
386 local_irq_restore(flags);
387 }
388
389 static void sdhci_transfer_pio(struct sdhci_host *host)
390 {
391 u32 mask;
392
393 BUG_ON(!host->data);
394
395 if (host->blocks == 0)
396 return;
397
398 if (host->data->flags & MMC_DATA_READ)
399 mask = SDHCI_DATA_AVAILABLE;
400 else
401 mask = SDHCI_SPACE_AVAILABLE;
402
403 /*
404 * Some controllers (JMicron JMB38x) mess up the buffer bits
405 * for transfers < 4 bytes. As long as it is just one block,
406 * we can ignore the bits.
407 */
408 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
409 (host->data->blocks == 1))
410 mask = ~0;
411
412 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
413 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
414 udelay(100);
415
416 if (host->data->flags & MMC_DATA_READ)
417 sdhci_read_block_pio(host);
418 else
419 sdhci_write_block_pio(host);
420
421 host->blocks--;
422 if (host->blocks == 0)
423 break;
424 }
425
426 DBG("PIO transfer complete.\n");
427 }
428
429 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
430 struct mmc_data *data, int cookie)
431 {
432 int sg_count;
433
434 /*
435 * If the data buffers are already mapped, return the previous
436 * dma_map_sg() result.
437 */
438 if (data->host_cookie == COOKIE_PRE_MAPPED)
439 return data->sg_count;
440
441 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
442 data->flags & MMC_DATA_WRITE ?
443 DMA_TO_DEVICE : DMA_FROM_DEVICE);
444
445 if (sg_count == 0)
446 return -ENOSPC;
447
448 data->sg_count = sg_count;
449 data->host_cookie = cookie;
450
451 return sg_count;
452 }
453
454 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
455 {
456 local_irq_save(*flags);
457 return kmap_atomic(sg_page(sg)) + sg->offset;
458 }
459
460 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
461 {
462 kunmap_atomic(buffer);
463 local_irq_restore(*flags);
464 }
465
466 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
467 dma_addr_t addr, int len, unsigned cmd)
468 {
469 struct sdhci_adma2_64_desc *dma_desc = desc;
470
471 /* 32-bit and 64-bit descriptors have these members in same position */
472 dma_desc->cmd = cpu_to_le16(cmd);
473 dma_desc->len = cpu_to_le16(len);
474 dma_desc->addr_lo = cpu_to_le32((u32)addr);
475
476 if (host->flags & SDHCI_USE_64_BIT_DMA)
477 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
478 }
479
480 static void sdhci_adma_mark_end(void *desc)
481 {
482 struct sdhci_adma2_64_desc *dma_desc = desc;
483
484 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
485 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
486 }
487
488 static void sdhci_adma_table_pre(struct sdhci_host *host,
489 struct mmc_data *data, int sg_count)
490 {
491 struct scatterlist *sg;
492 unsigned long flags;
493 dma_addr_t addr, align_addr;
494 void *desc, *align;
495 char *buffer;
496 int len, offset, i;
497
498 /*
499 * The spec does not specify endianness of descriptor table.
500 * We currently guess that it is LE.
501 */
502
503 host->sg_count = sg_count;
504
505 desc = host->adma_table;
506 align = host->align_buffer;
507
508 align_addr = host->align_addr;
509
510 for_each_sg(data->sg, sg, host->sg_count, i) {
511 addr = sg_dma_address(sg);
512 len = sg_dma_len(sg);
513
514 /*
515 * The SDHCI specification states that ADMA addresses must
516 * be 32-bit aligned. If they aren't, then we use a bounce
517 * buffer for the (up to three) bytes that screw up the
518 * alignment.
519 */
520 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
521 SDHCI_ADMA2_MASK;
522 if (offset) {
523 if (data->flags & MMC_DATA_WRITE) {
524 buffer = sdhci_kmap_atomic(sg, &flags);
525 memcpy(align, buffer, offset);
526 sdhci_kunmap_atomic(buffer, &flags);
527 }
528
529 /* tran, valid */
530 sdhci_adma_write_desc(host, desc, align_addr, offset,
531 ADMA2_TRAN_VALID);
532
533 BUG_ON(offset > 65536);
534
535 align += SDHCI_ADMA2_ALIGN;
536 align_addr += SDHCI_ADMA2_ALIGN;
537
538 desc += host->desc_sz;
539
540 addr += offset;
541 len -= offset;
542 }
543
544 BUG_ON(len > 65536);
545
546 if (len) {
547 /* tran, valid */
548 sdhci_adma_write_desc(host, desc, addr, len,
549 ADMA2_TRAN_VALID);
550 desc += host->desc_sz;
551 }
552
553 /*
554 * If this triggers then we have a calculation bug
555 * somewhere. :/
556 */
557 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
558 }
559
560 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
561 /* Mark the last descriptor as the terminating descriptor */
562 if (desc != host->adma_table) {
563 desc -= host->desc_sz;
564 sdhci_adma_mark_end(desc);
565 }
566 } else {
567 /* Add a terminating entry - nop, end, valid */
568 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
569 }
570 }
571
572 static void sdhci_adma_table_post(struct sdhci_host *host,
573 struct mmc_data *data)
574 {
575 struct scatterlist *sg;
576 int i, size;
577 void *align;
578 char *buffer;
579 unsigned long flags;
580
581 if (data->flags & MMC_DATA_READ) {
582 bool has_unaligned = false;
583
584 /* Do a quick scan of the SG list for any unaligned mappings */
585 for_each_sg(data->sg, sg, host->sg_count, i)
586 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
587 has_unaligned = true;
588 break;
589 }
590
591 if (has_unaligned) {
592 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
593 data->sg_len, DMA_FROM_DEVICE);
594
595 align = host->align_buffer;
596
597 for_each_sg(data->sg, sg, host->sg_count, i) {
598 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
599 size = SDHCI_ADMA2_ALIGN -
600 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
601
602 buffer = sdhci_kmap_atomic(sg, &flags);
603 memcpy(buffer, align, size);
604 sdhci_kunmap_atomic(buffer, &flags);
605
606 align += SDHCI_ADMA2_ALIGN;
607 }
608 }
609 }
610 }
611 }
612
613 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
614 {
615 u8 count;
616 struct mmc_data *data = cmd->data;
617 unsigned target_timeout, current_timeout;
618
619 /*
620 * If the host controller provides us with an incorrect timeout
621 * value, just skip the check and use 0xE. The hardware may take
622 * longer to time out, but that's much better than having a too-short
623 * timeout value.
624 */
625 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
626 return 0xE;
627
628 /* Unspecified timeout, assume max */
629 if (!data && !cmd->busy_timeout)
630 return 0xE;
631
632 /* timeout in us */
633 if (!data)
634 target_timeout = cmd->busy_timeout * 1000;
635 else {
636 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
637 if (host->clock && data->timeout_clks) {
638 unsigned long long val;
639
640 /*
641 * data->timeout_clks is in units of clock cycles.
642 * host->clock is in Hz. target_timeout is in us.
643 * Hence, us = 1000000 * cycles / Hz. Round up.
644 */
645 val = 1000000 * data->timeout_clks;
646 if (do_div(val, host->clock))
647 target_timeout++;
648 target_timeout += val;
649 }
650 }
651
652 /*
653 * Figure out needed cycles.
654 * We do this in steps in order to fit inside a 32 bit int.
655 * The first step is the minimum timeout, which will have a
656 * minimum resolution of 6 bits:
657 * (1) 2^13*1000 > 2^22,
658 * (2) host->timeout_clk < 2^16
659 * =>
660 * (1) / (2) > 2^6
661 */
662 count = 0;
663 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
664 while (current_timeout < target_timeout) {
665 count++;
666 current_timeout <<= 1;
667 if (count >= 0xF)
668 break;
669 }
670
671 if (count >= 0xF) {
672 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
673 mmc_hostname(host->mmc), count, cmd->opcode);
674 count = 0xE;
675 }
676
677 return count;
678 }
679
680 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
681 {
682 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
683 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
684
685 if (host->flags & SDHCI_REQ_USE_DMA)
686 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
687 else
688 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
689
690 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
691 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
692 }
693
694 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
695 {
696 u8 count;
697
698 if (host->ops->set_timeout) {
699 host->ops->set_timeout(host, cmd);
700 } else {
701 count = sdhci_calc_timeout(host, cmd);
702 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
703 }
704 }
705
706 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
707 {
708 u8 ctrl;
709 struct mmc_data *data = cmd->data;
710
711 WARN_ON(host->data);
712
713 if (data || (cmd->flags & MMC_RSP_BUSY))
714 sdhci_set_timeout(host, cmd);
715
716 if (!data)
717 return;
718
719 /* Sanity checks */
720 BUG_ON(data->blksz * data->blocks > 524288);
721 BUG_ON(data->blksz > host->mmc->max_blk_size);
722 BUG_ON(data->blocks > 65535);
723
724 host->data = data;
725 host->data_early = 0;
726 host->data->bytes_xfered = 0;
727
728 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
729 host->flags |= SDHCI_REQ_USE_DMA;
730
731 /*
732 * FIXME: This doesn't account for merging when mapping the
733 * scatterlist.
734 */
735 if (host->flags & SDHCI_REQ_USE_DMA) {
736 struct scatterlist *sg;
737 unsigned int length_mask;
738 int i;
739
740 length_mask = 0;
741 if (host->flags & SDHCI_USE_ADMA) {
742 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
743 length_mask = 3;
744 } else {
745 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
746 length_mask = 3;
747 }
748
749 if (unlikely(length_mask)) {
750 for_each_sg(data->sg, sg, data->sg_len, i) {
751 if (sg->length & length_mask) {
752 DBG("Reverting to PIO because of transfer size (%d)\n",
753 sg->length);
754 host->flags &= ~SDHCI_REQ_USE_DMA;
755 break;
756 }
757 }
758 }
759 }
760
761 /*
762 * The assumption here being that alignment is the same after
763 * translation to device address space.
764 */
765 if (host->flags & SDHCI_REQ_USE_DMA) {
766 struct scatterlist *sg;
767 unsigned int offset_mask;
768 int i;
769
770 offset_mask = 0;
771 if (host->flags & SDHCI_USE_ADMA) {
772 /*
773 * As we use 3 byte chunks to work around
774 * alignment problems, we need to check this
775 * quirk.
776 */
777 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
778 offset_mask = 3;
779 } else {
780 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
781 offset_mask = 3;
782 }
783
784 if (unlikely(offset_mask)) {
785 for_each_sg(data->sg, sg, data->sg_len, i) {
786 if (sg->offset & offset_mask) {
787 DBG("Reverting to PIO because of bad alignment\n");
788 host->flags &= ~SDHCI_REQ_USE_DMA;
789 break;
790 }
791 }
792 }
793 }
794
795 if (host->flags & SDHCI_REQ_USE_DMA) {
796 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
797
798 if (sg_cnt <= 0) {
799 /*
800 * This only happens when someone fed
801 * us an invalid request.
802 */
803 WARN_ON(1);
804 host->flags &= ~SDHCI_REQ_USE_DMA;
805 } else if (host->flags & SDHCI_USE_ADMA) {
806 sdhci_adma_table_pre(host, data, sg_cnt);
807
808 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
809 if (host->flags & SDHCI_USE_64_BIT_DMA)
810 sdhci_writel(host,
811 (u64)host->adma_addr >> 32,
812 SDHCI_ADMA_ADDRESS_HI);
813 } else {
814 WARN_ON(sg_cnt != 1);
815 sdhci_writel(host, sg_dma_address(data->sg),
816 SDHCI_DMA_ADDRESS);
817 }
818 }
819
820 /*
821 * Always adjust the DMA selection as some controllers
822 * (e.g. JMicron) can't do PIO properly when the selection
823 * is ADMA.
824 */
825 if (host->version >= SDHCI_SPEC_200) {
826 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
827 ctrl &= ~SDHCI_CTRL_DMA_MASK;
828 if ((host->flags & SDHCI_REQ_USE_DMA) &&
829 (host->flags & SDHCI_USE_ADMA)) {
830 if (host->flags & SDHCI_USE_64_BIT_DMA)
831 ctrl |= SDHCI_CTRL_ADMA64;
832 else
833 ctrl |= SDHCI_CTRL_ADMA32;
834 } else {
835 ctrl |= SDHCI_CTRL_SDMA;
836 }
837 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
838 }
839
840 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
841 int flags;
842
843 flags = SG_MITER_ATOMIC;
844 if (host->data->flags & MMC_DATA_READ)
845 flags |= SG_MITER_TO_SG;
846 else
847 flags |= SG_MITER_FROM_SG;
848 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
849 host->blocks = data->blocks;
850 }
851
852 sdhci_set_transfer_irqs(host);
853
854 /* Set the DMA boundary value and block size */
855 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
856 data->blksz), SDHCI_BLOCK_SIZE);
857 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
858 }
859
860 static void sdhci_set_transfer_mode(struct sdhci_host *host,
861 struct mmc_command *cmd)
862 {
863 u16 mode = 0;
864 struct mmc_data *data = cmd->data;
865
866 if (data == NULL) {
867 if (host->quirks2 &
868 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
869 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
870 } else {
871 /* clear Auto CMD settings for no data CMDs */
872 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
873 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
874 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
875 }
876 return;
877 }
878
879 WARN_ON(!host->data);
880
881 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
882 mode = SDHCI_TRNS_BLK_CNT_EN;
883
884 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
885 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
886 /*
887 * If we are sending CMD23, CMD12 never gets sent
888 * on successful completion (so no Auto-CMD12).
889 */
890 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
891 (cmd->opcode != SD_IO_RW_EXTENDED))
892 mode |= SDHCI_TRNS_AUTO_CMD12;
893 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
894 mode |= SDHCI_TRNS_AUTO_CMD23;
895 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
896 }
897 }
898
899 if (data->flags & MMC_DATA_READ)
900 mode |= SDHCI_TRNS_READ;
901 if (host->flags & SDHCI_REQ_USE_DMA)
902 mode |= SDHCI_TRNS_DMA;
903
904 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
905 }
906
907 static void sdhci_finish_data(struct sdhci_host *host)
908 {
909 struct mmc_data *data;
910
911 BUG_ON(!host->data);
912
913 data = host->data;
914 host->data = NULL;
915
916 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
917 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
918 sdhci_adma_table_post(host, data);
919
920 /*
921 * The specification states that the block count register must
922 * be updated, but it does not specify at what point in the
923 * data flow. That makes the register entirely useless to read
924 * back so we have to assume that nothing made it to the card
925 * in the event of an error.
926 */
927 if (data->error)
928 data->bytes_xfered = 0;
929 else
930 data->bytes_xfered = data->blksz * data->blocks;
931
932 /*
933 * Need to send CMD12 if -
934 * a) open-ended multiblock transfer (no CMD23)
935 * b) error in multiblock transfer
936 */
937 if (data->stop &&
938 (data->error ||
939 !host->mrq->sbc)) {
940
941 /*
942 * The controller needs a reset of internal state machines
943 * upon error conditions.
944 */
945 if (data->error) {
946 sdhci_do_reset(host, SDHCI_RESET_CMD);
947 sdhci_do_reset(host, SDHCI_RESET_DATA);
948 }
949
950 sdhci_send_command(host, data->stop);
951 } else
952 tasklet_schedule(&host->finish_tasklet);
953 }
954
955 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
956 {
957 int flags;
958 u32 mask;
959 unsigned long timeout;
960
961 WARN_ON(host->cmd);
962
963 /* Initially, a command has no error */
964 cmd->error = 0;
965
966 /* Wait max 10 ms */
967 timeout = 10;
968
969 mask = SDHCI_CMD_INHIBIT;
970 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
971 mask |= SDHCI_DATA_INHIBIT;
972
973 /* We shouldn't wait for data inihibit for stop commands, even
974 though they might use busy signaling */
975 if (host->mrq->data && (cmd == host->mrq->data->stop))
976 mask &= ~SDHCI_DATA_INHIBIT;
977
978 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
979 if (timeout == 0) {
980 pr_err("%s: Controller never released inhibit bit(s).\n",
981 mmc_hostname(host->mmc));
982 sdhci_dumpregs(host);
983 cmd->error = -EIO;
984 tasklet_schedule(&host->finish_tasklet);
985 return;
986 }
987 timeout--;
988 mdelay(1);
989 }
990
991 timeout = jiffies;
992 if (!cmd->data && cmd->busy_timeout > 9000)
993 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
994 else
995 timeout += 10 * HZ;
996 mod_timer(&host->timer, timeout);
997
998 host->cmd = cmd;
999 host->busy_handle = 0;
1000
1001 sdhci_prepare_data(host, cmd);
1002
1003 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1004
1005 sdhci_set_transfer_mode(host, cmd);
1006
1007 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1008 pr_err("%s: Unsupported response type!\n",
1009 mmc_hostname(host->mmc));
1010 cmd->error = -EINVAL;
1011 tasklet_schedule(&host->finish_tasklet);
1012 return;
1013 }
1014
1015 if (!(cmd->flags & MMC_RSP_PRESENT))
1016 flags = SDHCI_CMD_RESP_NONE;
1017 else if (cmd->flags & MMC_RSP_136)
1018 flags = SDHCI_CMD_RESP_LONG;
1019 else if (cmd->flags & MMC_RSP_BUSY)
1020 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1021 else
1022 flags = SDHCI_CMD_RESP_SHORT;
1023
1024 if (cmd->flags & MMC_RSP_CRC)
1025 flags |= SDHCI_CMD_CRC;
1026 if (cmd->flags & MMC_RSP_OPCODE)
1027 flags |= SDHCI_CMD_INDEX;
1028
1029 /* CMD19 is special in that the Data Present Select should be set */
1030 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1031 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1032 flags |= SDHCI_CMD_DATA;
1033
1034 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1035 }
1036 EXPORT_SYMBOL_GPL(sdhci_send_command);
1037
1038 static void sdhci_finish_command(struct sdhci_host *host)
1039 {
1040 int i;
1041
1042 BUG_ON(host->cmd == NULL);
1043
1044 if (host->cmd->flags & MMC_RSP_PRESENT) {
1045 if (host->cmd->flags & MMC_RSP_136) {
1046 /* CRC is stripped so we need to do some shifting. */
1047 for (i = 0;i < 4;i++) {
1048 host->cmd->resp[i] = sdhci_readl(host,
1049 SDHCI_RESPONSE + (3-i)*4) << 8;
1050 if (i != 3)
1051 host->cmd->resp[i] |=
1052 sdhci_readb(host,
1053 SDHCI_RESPONSE + (3-i)*4-1);
1054 }
1055 } else {
1056 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1057 }
1058 }
1059
1060 /* Finished CMD23, now send actual command. */
1061 if (host->cmd == host->mrq->sbc) {
1062 host->cmd = NULL;
1063 sdhci_send_command(host, host->mrq->cmd);
1064 } else {
1065
1066 /* Processed actual command. */
1067 if (host->data && host->data_early)
1068 sdhci_finish_data(host);
1069
1070 if (!host->cmd->data)
1071 tasklet_schedule(&host->finish_tasklet);
1072
1073 host->cmd = NULL;
1074 }
1075 }
1076
1077 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1078 {
1079 u16 preset = 0;
1080
1081 switch (host->timing) {
1082 case MMC_TIMING_UHS_SDR12:
1083 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1084 break;
1085 case MMC_TIMING_UHS_SDR25:
1086 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1087 break;
1088 case MMC_TIMING_UHS_SDR50:
1089 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1090 break;
1091 case MMC_TIMING_UHS_SDR104:
1092 case MMC_TIMING_MMC_HS200:
1093 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1094 break;
1095 case MMC_TIMING_UHS_DDR50:
1096 case MMC_TIMING_MMC_DDR52:
1097 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1098 break;
1099 case MMC_TIMING_MMC_HS400:
1100 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1101 break;
1102 default:
1103 pr_warn("%s: Invalid UHS-I mode selected\n",
1104 mmc_hostname(host->mmc));
1105 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1106 break;
1107 }
1108 return preset;
1109 }
1110
1111 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1112 {
1113 int div = 0; /* Initialized for compiler warning */
1114 int real_div = div, clk_mul = 1;
1115 u16 clk = 0;
1116 unsigned long timeout;
1117 bool switch_base_clk = false;
1118
1119 host->mmc->actual_clock = 0;
1120
1121 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1122 if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1123 mdelay(1);
1124
1125 if (clock == 0)
1126 return;
1127
1128 if (host->version >= SDHCI_SPEC_300) {
1129 if (host->preset_enabled) {
1130 u16 pre_val;
1131
1132 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1133 pre_val = sdhci_get_preset_value(host);
1134 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1135 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1136 if (host->clk_mul &&
1137 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1138 clk = SDHCI_PROG_CLOCK_MODE;
1139 real_div = div + 1;
1140 clk_mul = host->clk_mul;
1141 } else {
1142 real_div = max_t(int, 1, div << 1);
1143 }
1144 goto clock_set;
1145 }
1146
1147 /*
1148 * Check if the Host Controller supports Programmable Clock
1149 * Mode.
1150 */
1151 if (host->clk_mul) {
1152 for (div = 1; div <= 1024; div++) {
1153 if ((host->max_clk * host->clk_mul / div)
1154 <= clock)
1155 break;
1156 }
1157 if ((host->max_clk * host->clk_mul / div) <= clock) {
1158 /*
1159 * Set Programmable Clock Mode in the Clock
1160 * Control register.
1161 */
1162 clk = SDHCI_PROG_CLOCK_MODE;
1163 real_div = div;
1164 clk_mul = host->clk_mul;
1165 div--;
1166 } else {
1167 /*
1168 * Divisor can be too small to reach clock
1169 * speed requirement. Then use the base clock.
1170 */
1171 switch_base_clk = true;
1172 }
1173 }
1174
1175 if (!host->clk_mul || switch_base_clk) {
1176 /* Version 3.00 divisors must be a multiple of 2. */
1177 if (host->max_clk <= clock)
1178 div = 1;
1179 else {
1180 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1181 div += 2) {
1182 if ((host->max_clk / div) <= clock)
1183 break;
1184 }
1185 }
1186 real_div = div;
1187 div >>= 1;
1188 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1189 && !div && host->max_clk <= 25000000)
1190 div = 1;
1191 }
1192 } else {
1193 /* Version 2.00 divisors must be a power of 2. */
1194 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1195 if ((host->max_clk / div) <= clock)
1196 break;
1197 }
1198 real_div = div;
1199 div >>= 1;
1200 }
1201
1202 clock_set:
1203 if (real_div)
1204 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1205 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1206 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1207 << SDHCI_DIVIDER_HI_SHIFT;
1208 clk |= SDHCI_CLOCK_INT_EN;
1209 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1210
1211 /* Wait max 20 ms */
1212 timeout = 20;
1213 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1214 & SDHCI_CLOCK_INT_STABLE)) {
1215 if (timeout == 0) {
1216 pr_err("%s: Internal clock never stabilised.\n",
1217 mmc_hostname(host->mmc));
1218 sdhci_dumpregs(host);
1219 return;
1220 }
1221 timeout--;
1222 mdelay(1);
1223 }
1224
1225 clk |= SDHCI_CLOCK_CARD_EN;
1226 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1227 }
1228 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1229
1230 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1231 unsigned short vdd)
1232 {
1233 struct mmc_host *mmc = host->mmc;
1234 u8 pwr = 0;
1235
1236 if (mode != MMC_POWER_OFF) {
1237 switch (1 << vdd) {
1238 case MMC_VDD_165_195:
1239 pwr = SDHCI_POWER_180;
1240 break;
1241 case MMC_VDD_29_30:
1242 case MMC_VDD_30_31:
1243 pwr = SDHCI_POWER_300;
1244 break;
1245 case MMC_VDD_32_33:
1246 case MMC_VDD_33_34:
1247 pwr = SDHCI_POWER_330;
1248 break;
1249 default:
1250 WARN(1, "%s: Invalid vdd %#x\n",
1251 mmc_hostname(host->mmc), vdd);
1252 break;
1253 }
1254 }
1255
1256 if (host->pwr == pwr)
1257 return;
1258
1259 host->pwr = pwr;
1260
1261 if (pwr == 0) {
1262 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1263 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1264 sdhci_runtime_pm_bus_off(host);
1265 vdd = 0;
1266 } else {
1267 /*
1268 * Spec says that we should clear the power reg before setting
1269 * a new value. Some controllers don't seem to like this though.
1270 */
1271 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1272 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1273
1274 /*
1275 * At least the Marvell CaFe chip gets confused if we set the
1276 * voltage and set turn on power at the same time, so set the
1277 * voltage first.
1278 */
1279 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1280 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1281
1282 pwr |= SDHCI_POWER_ON;
1283
1284 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1285
1286 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1287 sdhci_runtime_pm_bus_on(host);
1288
1289 /*
1290 * Some controllers need an extra 10ms delay of 10ms before
1291 * they can apply clock after applying power
1292 */
1293 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1294 mdelay(10);
1295 }
1296
1297 if (!IS_ERR(mmc->supply.vmmc)) {
1298 spin_unlock_irq(&host->lock);
1299 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1300 spin_lock_irq(&host->lock);
1301 }
1302 }
1303
1304 /*****************************************************************************\
1305 * *
1306 * MMC callbacks *
1307 * *
1308 \*****************************************************************************/
1309
1310 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1311 {
1312 struct sdhci_host *host;
1313 int present;
1314 unsigned long flags;
1315
1316 host = mmc_priv(mmc);
1317
1318 sdhci_runtime_pm_get(host);
1319
1320 /* Firstly check card presence */
1321 present = mmc->ops->get_cd(mmc);
1322
1323 spin_lock_irqsave(&host->lock, flags);
1324
1325 WARN_ON(host->mrq != NULL);
1326
1327 #ifndef SDHCI_USE_LEDS_CLASS
1328 sdhci_activate_led(host);
1329 #endif
1330
1331 /*
1332 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1333 * requests if Auto-CMD12 is enabled.
1334 */
1335 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1336 if (mrq->stop) {
1337 mrq->data->stop = NULL;
1338 mrq->stop = NULL;
1339 }
1340 }
1341
1342 host->mrq = mrq;
1343
1344 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1345 host->mrq->cmd->error = -ENOMEDIUM;
1346 tasklet_schedule(&host->finish_tasklet);
1347 } else {
1348 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1349 sdhci_send_command(host, mrq->sbc);
1350 else
1351 sdhci_send_command(host, mrq->cmd);
1352 }
1353
1354 mmiowb();
1355 spin_unlock_irqrestore(&host->lock, flags);
1356 }
1357
1358 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1359 {
1360 u8 ctrl;
1361
1362 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1363 if (width == MMC_BUS_WIDTH_8) {
1364 ctrl &= ~SDHCI_CTRL_4BITBUS;
1365 if (host->version >= SDHCI_SPEC_300)
1366 ctrl |= SDHCI_CTRL_8BITBUS;
1367 } else {
1368 if (host->version >= SDHCI_SPEC_300)
1369 ctrl &= ~SDHCI_CTRL_8BITBUS;
1370 if (width == MMC_BUS_WIDTH_4)
1371 ctrl |= SDHCI_CTRL_4BITBUS;
1372 else
1373 ctrl &= ~SDHCI_CTRL_4BITBUS;
1374 }
1375 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1376 }
1377 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1378
1379 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1380 {
1381 u16 ctrl_2;
1382
1383 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1384 /* Select Bus Speed Mode for host */
1385 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1386 if ((timing == MMC_TIMING_MMC_HS200) ||
1387 (timing == MMC_TIMING_UHS_SDR104))
1388 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1389 else if (timing == MMC_TIMING_UHS_SDR12)
1390 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1391 else if (timing == MMC_TIMING_UHS_SDR25)
1392 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1393 else if (timing == MMC_TIMING_UHS_SDR50)
1394 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1395 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1396 (timing == MMC_TIMING_MMC_DDR52))
1397 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1398 else if (timing == MMC_TIMING_MMC_HS400)
1399 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1400 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1401 }
1402 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1403
1404 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1405 {
1406 unsigned long flags;
1407 u8 ctrl;
1408 struct mmc_host *mmc = host->mmc;
1409
1410 spin_lock_irqsave(&host->lock, flags);
1411
1412 if (host->flags & SDHCI_DEVICE_DEAD) {
1413 spin_unlock_irqrestore(&host->lock, flags);
1414 if (!IS_ERR(mmc->supply.vmmc) &&
1415 ios->power_mode == MMC_POWER_OFF)
1416 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1417 return;
1418 }
1419
1420 /*
1421 * Reset the chip on each power off.
1422 * Should clear out any weird states.
1423 */
1424 if (ios->power_mode == MMC_POWER_OFF) {
1425 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1426 sdhci_reinit(host);
1427 }
1428
1429 if (host->version >= SDHCI_SPEC_300 &&
1430 (ios->power_mode == MMC_POWER_UP) &&
1431 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1432 sdhci_enable_preset_value(host, false);
1433
1434 if (!ios->clock || ios->clock != host->clock) {
1435 host->ops->set_clock(host, ios->clock);
1436 host->clock = ios->clock;
1437
1438 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1439 host->clock) {
1440 host->timeout_clk = host->mmc->actual_clock ?
1441 host->mmc->actual_clock / 1000 :
1442 host->clock / 1000;
1443 host->mmc->max_busy_timeout =
1444 host->ops->get_max_timeout_count ?
1445 host->ops->get_max_timeout_count(host) :
1446 1 << 27;
1447 host->mmc->max_busy_timeout /= host->timeout_clk;
1448 }
1449 }
1450
1451 sdhci_set_power(host, ios->power_mode, ios->vdd);
1452
1453 if (host->ops->platform_send_init_74_clocks)
1454 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1455
1456 host->ops->set_bus_width(host, ios->bus_width);
1457
1458 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1459
1460 if ((ios->timing == MMC_TIMING_SD_HS ||
1461 ios->timing == MMC_TIMING_MMC_HS)
1462 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1463 ctrl |= SDHCI_CTRL_HISPD;
1464 else
1465 ctrl &= ~SDHCI_CTRL_HISPD;
1466
1467 if (host->version >= SDHCI_SPEC_300) {
1468 u16 clk, ctrl_2;
1469
1470 /* In case of UHS-I modes, set High Speed Enable */
1471 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1472 (ios->timing == MMC_TIMING_MMC_HS200) ||
1473 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1474 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1475 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1476 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1477 (ios->timing == MMC_TIMING_UHS_SDR25))
1478 ctrl |= SDHCI_CTRL_HISPD;
1479
1480 if (!host->preset_enabled) {
1481 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1482 /*
1483 * We only need to set Driver Strength if the
1484 * preset value enable is not set.
1485 */
1486 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1487 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1488 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1489 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1490 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1491 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1492 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1493 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1494 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1495 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1496 else {
1497 pr_warn("%s: invalid driver type, default to driver type B\n",
1498 mmc_hostname(mmc));
1499 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1500 }
1501
1502 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1503 } else {
1504 /*
1505 * According to SDHC Spec v3.00, if the Preset Value
1506 * Enable in the Host Control 2 register is set, we
1507 * need to reset SD Clock Enable before changing High
1508 * Speed Enable to avoid generating clock gliches.
1509 */
1510
1511 /* Reset SD Clock Enable */
1512 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1513 clk &= ~SDHCI_CLOCK_CARD_EN;
1514 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1515
1516 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1517
1518 /* Re-enable SD Clock */
1519 host->ops->set_clock(host, host->clock);
1520 }
1521
1522 /* Reset SD Clock Enable */
1523 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1524 clk &= ~SDHCI_CLOCK_CARD_EN;
1525 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1526
1527 host->ops->set_uhs_signaling(host, ios->timing);
1528 host->timing = ios->timing;
1529
1530 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1531 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1532 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1533 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1534 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1535 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1536 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1537 u16 preset;
1538
1539 sdhci_enable_preset_value(host, true);
1540 preset = sdhci_get_preset_value(host);
1541 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1542 >> SDHCI_PRESET_DRV_SHIFT;
1543 }
1544
1545 /* Re-enable SD Clock */
1546 host->ops->set_clock(host, host->clock);
1547 } else
1548 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1549
1550 /*
1551 * Some (ENE) controllers go apeshit on some ios operation,
1552 * signalling timeout and CRC errors even on CMD0. Resetting
1553 * it on each ios seems to solve the problem.
1554 */
1555 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1556 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1557
1558 mmiowb();
1559 spin_unlock_irqrestore(&host->lock, flags);
1560 }
1561
1562 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1563 {
1564 struct sdhci_host *host = mmc_priv(mmc);
1565
1566 sdhci_runtime_pm_get(host);
1567 sdhci_do_set_ios(host, ios);
1568 sdhci_runtime_pm_put(host);
1569 }
1570
1571 static int sdhci_do_get_cd(struct sdhci_host *host)
1572 {
1573 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1574
1575 if (host->flags & SDHCI_DEVICE_DEAD)
1576 return 0;
1577
1578 /* If nonremovable, assume that the card is always present. */
1579 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1580 return 1;
1581
1582 /*
1583 * Try slot gpio detect, if defined it take precedence
1584 * over build in controller functionality
1585 */
1586 if (!IS_ERR_VALUE(gpio_cd))
1587 return !!gpio_cd;
1588
1589 /* If polling, assume that the card is always present. */
1590 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1591 return 1;
1592
1593 /* Host native card detect */
1594 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1595 }
1596
1597 static int sdhci_get_cd(struct mmc_host *mmc)
1598 {
1599 struct sdhci_host *host = mmc_priv(mmc);
1600 int ret;
1601
1602 sdhci_runtime_pm_get(host);
1603 ret = sdhci_do_get_cd(host);
1604 sdhci_runtime_pm_put(host);
1605 return ret;
1606 }
1607
1608 static int sdhci_check_ro(struct sdhci_host *host)
1609 {
1610 unsigned long flags;
1611 int is_readonly;
1612
1613 spin_lock_irqsave(&host->lock, flags);
1614
1615 if (host->flags & SDHCI_DEVICE_DEAD)
1616 is_readonly = 0;
1617 else if (host->ops->get_ro)
1618 is_readonly = host->ops->get_ro(host);
1619 else
1620 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1621 & SDHCI_WRITE_PROTECT);
1622
1623 spin_unlock_irqrestore(&host->lock, flags);
1624
1625 /* This quirk needs to be replaced by a callback-function later */
1626 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1627 !is_readonly : is_readonly;
1628 }
1629
1630 #define SAMPLE_COUNT 5
1631
1632 static int sdhci_do_get_ro(struct sdhci_host *host)
1633 {
1634 int i, ro_count;
1635
1636 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1637 return sdhci_check_ro(host);
1638
1639 ro_count = 0;
1640 for (i = 0; i < SAMPLE_COUNT; i++) {
1641 if (sdhci_check_ro(host)) {
1642 if (++ro_count > SAMPLE_COUNT / 2)
1643 return 1;
1644 }
1645 msleep(30);
1646 }
1647 return 0;
1648 }
1649
1650 static void sdhci_hw_reset(struct mmc_host *mmc)
1651 {
1652 struct sdhci_host *host = mmc_priv(mmc);
1653
1654 if (host->ops && host->ops->hw_reset)
1655 host->ops->hw_reset(host);
1656 }
1657
1658 static int sdhci_get_ro(struct mmc_host *mmc)
1659 {
1660 struct sdhci_host *host = mmc_priv(mmc);
1661 int ret;
1662
1663 sdhci_runtime_pm_get(host);
1664 ret = sdhci_do_get_ro(host);
1665 sdhci_runtime_pm_put(host);
1666 return ret;
1667 }
1668
1669 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1670 {
1671 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1672 if (enable)
1673 host->ier |= SDHCI_INT_CARD_INT;
1674 else
1675 host->ier &= ~SDHCI_INT_CARD_INT;
1676
1677 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1678 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1679 mmiowb();
1680 }
1681 }
1682
1683 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1684 {
1685 struct sdhci_host *host = mmc_priv(mmc);
1686 unsigned long flags;
1687
1688 sdhci_runtime_pm_get(host);
1689
1690 spin_lock_irqsave(&host->lock, flags);
1691 if (enable)
1692 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1693 else
1694 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1695
1696 sdhci_enable_sdio_irq_nolock(host, enable);
1697 spin_unlock_irqrestore(&host->lock, flags);
1698
1699 sdhci_runtime_pm_put(host);
1700 }
1701
1702 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1703 struct mmc_ios *ios)
1704 {
1705 struct mmc_host *mmc = host->mmc;
1706 u16 ctrl;
1707 int ret;
1708
1709 /*
1710 * Signal Voltage Switching is only applicable for Host Controllers
1711 * v3.00 and above.
1712 */
1713 if (host->version < SDHCI_SPEC_300)
1714 return 0;
1715
1716 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1717
1718 switch (ios->signal_voltage) {
1719 case MMC_SIGNAL_VOLTAGE_330:
1720 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1721 ctrl &= ~SDHCI_CTRL_VDD_180;
1722 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1723
1724 if (!IS_ERR(mmc->supply.vqmmc)) {
1725 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1726 3600000);
1727 if (ret) {
1728 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1729 mmc_hostname(mmc));
1730 return -EIO;
1731 }
1732 }
1733 /* Wait for 5ms */
1734 usleep_range(5000, 5500);
1735
1736 /* 3.3V regulator output should be stable within 5 ms */
1737 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1738 if (!(ctrl & SDHCI_CTRL_VDD_180))
1739 return 0;
1740
1741 pr_warn("%s: 3.3V regulator output did not became stable\n",
1742 mmc_hostname(mmc));
1743
1744 return -EAGAIN;
1745 case MMC_SIGNAL_VOLTAGE_180:
1746 if (!IS_ERR(mmc->supply.vqmmc)) {
1747 ret = regulator_set_voltage(mmc->supply.vqmmc,
1748 1700000, 1950000);
1749 if (ret) {
1750 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1751 mmc_hostname(mmc));
1752 return -EIO;
1753 }
1754 }
1755
1756 /*
1757 * Enable 1.8V Signal Enable in the Host Control2
1758 * register
1759 */
1760 ctrl |= SDHCI_CTRL_VDD_180;
1761 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1762
1763 /* Some controller need to do more when switching */
1764 if (host->ops->voltage_switch)
1765 host->ops->voltage_switch(host);
1766
1767 /* 1.8V regulator output should be stable within 5 ms */
1768 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1769 if (ctrl & SDHCI_CTRL_VDD_180)
1770 return 0;
1771
1772 pr_warn("%s: 1.8V regulator output did not became stable\n",
1773 mmc_hostname(mmc));
1774
1775 return -EAGAIN;
1776 case MMC_SIGNAL_VOLTAGE_120:
1777 if (!IS_ERR(mmc->supply.vqmmc)) {
1778 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1779 1300000);
1780 if (ret) {
1781 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1782 mmc_hostname(mmc));
1783 return -EIO;
1784 }
1785 }
1786 return 0;
1787 default:
1788 /* No signal voltage switch required */
1789 return 0;
1790 }
1791 }
1792
1793 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1794 struct mmc_ios *ios)
1795 {
1796 struct sdhci_host *host = mmc_priv(mmc);
1797 int err;
1798
1799 if (host->version < SDHCI_SPEC_300)
1800 return 0;
1801 sdhci_runtime_pm_get(host);
1802 err = sdhci_do_start_signal_voltage_switch(host, ios);
1803 sdhci_runtime_pm_put(host);
1804 return err;
1805 }
1806
1807 static int sdhci_card_busy(struct mmc_host *mmc)
1808 {
1809 struct sdhci_host *host = mmc_priv(mmc);
1810 u32 present_state;
1811
1812 sdhci_runtime_pm_get(host);
1813 /* Check whether DAT[3:0] is 0000 */
1814 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1815 sdhci_runtime_pm_put(host);
1816
1817 return !(present_state & SDHCI_DATA_LVL_MASK);
1818 }
1819
1820 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1821 {
1822 struct sdhci_host *host = mmc_priv(mmc);
1823 unsigned long flags;
1824
1825 spin_lock_irqsave(&host->lock, flags);
1826 host->flags |= SDHCI_HS400_TUNING;
1827 spin_unlock_irqrestore(&host->lock, flags);
1828
1829 return 0;
1830 }
1831
1832 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1833 {
1834 struct sdhci_host *host = mmc_priv(mmc);
1835 u16 ctrl;
1836 int tuning_loop_counter = MAX_TUNING_LOOP;
1837 int err = 0;
1838 unsigned long flags;
1839 unsigned int tuning_count = 0;
1840 bool hs400_tuning;
1841
1842 sdhci_runtime_pm_get(host);
1843 spin_lock_irqsave(&host->lock, flags);
1844
1845 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1846 host->flags &= ~SDHCI_HS400_TUNING;
1847
1848 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1849 tuning_count = host->tuning_count;
1850
1851 /*
1852 * The Host Controller needs tuning in case of SDR104 and DDR50
1853 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1854 * the Capabilities register.
1855 * If the Host Controller supports the HS200 mode then the
1856 * tuning function has to be executed.
1857 */
1858 switch (host->timing) {
1859 /* HS400 tuning is done in HS200 mode */
1860 case MMC_TIMING_MMC_HS400:
1861 err = -EINVAL;
1862 goto out_unlock;
1863
1864 case MMC_TIMING_MMC_HS200:
1865 /*
1866 * Periodic re-tuning for HS400 is not expected to be needed, so
1867 * disable it here.
1868 */
1869 if (hs400_tuning)
1870 tuning_count = 0;
1871 break;
1872
1873 case MMC_TIMING_UHS_SDR104:
1874 case MMC_TIMING_UHS_DDR50:
1875 break;
1876
1877 case MMC_TIMING_UHS_SDR50:
1878 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1879 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1880 break;
1881 /* FALLTHROUGH */
1882
1883 default:
1884 goto out_unlock;
1885 }
1886
1887 if (host->ops->platform_execute_tuning) {
1888 spin_unlock_irqrestore(&host->lock, flags);
1889 err = host->ops->platform_execute_tuning(host, opcode);
1890 sdhci_runtime_pm_put(host);
1891 return err;
1892 }
1893
1894 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1895 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1896 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1897 ctrl |= SDHCI_CTRL_TUNED_CLK;
1898 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1899
1900 /*
1901 * As per the Host Controller spec v3.00, tuning command
1902 * generates Buffer Read Ready interrupt, so enable that.
1903 *
1904 * Note: The spec clearly says that when tuning sequence
1905 * is being performed, the controller does not generate
1906 * interrupts other than Buffer Read Ready interrupt. But
1907 * to make sure we don't hit a controller bug, we _only_
1908 * enable Buffer Read Ready interrupt here.
1909 */
1910 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1911 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1912
1913 /*
1914 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1915 * of loops reaches 40 times or a timeout of 150ms occurs.
1916 */
1917 do {
1918 struct mmc_command cmd = {0};
1919 struct mmc_request mrq = {NULL};
1920
1921 cmd.opcode = opcode;
1922 cmd.arg = 0;
1923 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1924 cmd.retries = 0;
1925 cmd.data = NULL;
1926 cmd.error = 0;
1927
1928 if (tuning_loop_counter-- == 0)
1929 break;
1930
1931 mrq.cmd = &cmd;
1932 host->mrq = &mrq;
1933
1934 /*
1935 * In response to CMD19, the card sends 64 bytes of tuning
1936 * block to the Host Controller. So we set the block size
1937 * to 64 here.
1938 */
1939 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1940 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1941 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1942 SDHCI_BLOCK_SIZE);
1943 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1944 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1945 SDHCI_BLOCK_SIZE);
1946 } else {
1947 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1948 SDHCI_BLOCK_SIZE);
1949 }
1950
1951 /*
1952 * The tuning block is sent by the card to the host controller.
1953 * So we set the TRNS_READ bit in the Transfer Mode register.
1954 * This also takes care of setting DMA Enable and Multi Block
1955 * Select in the same register to 0.
1956 */
1957 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1958
1959 sdhci_send_command(host, &cmd);
1960
1961 host->cmd = NULL;
1962 host->mrq = NULL;
1963
1964 spin_unlock_irqrestore(&host->lock, flags);
1965 /* Wait for Buffer Read Ready interrupt */
1966 wait_event_interruptible_timeout(host->buf_ready_int,
1967 (host->tuning_done == 1),
1968 msecs_to_jiffies(50));
1969 spin_lock_irqsave(&host->lock, flags);
1970
1971 if (!host->tuning_done) {
1972 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
1973 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1974 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1975 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1976 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1977
1978 err = -EIO;
1979 goto out;
1980 }
1981
1982 host->tuning_done = 0;
1983
1984 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1985
1986 /* eMMC spec does not require a delay between tuning cycles */
1987 if (opcode == MMC_SEND_TUNING_BLOCK)
1988 mdelay(1);
1989 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1990
1991 /*
1992 * The Host Driver has exhausted the maximum number of loops allowed,
1993 * so use fixed sampling frequency.
1994 */
1995 if (tuning_loop_counter < 0) {
1996 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1997 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1998 }
1999 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2000 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2001 err = -EIO;
2002 }
2003
2004 out:
2005 if (tuning_count) {
2006 /*
2007 * In case tuning fails, host controllers which support
2008 * re-tuning can try tuning again at a later time, when the
2009 * re-tuning timer expires. So for these controllers, we
2010 * return 0. Since there might be other controllers who do not
2011 * have this capability, we return error for them.
2012 */
2013 err = 0;
2014 }
2015
2016 host->mmc->retune_period = err ? 0 : tuning_count;
2017
2018 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2019 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2020 out_unlock:
2021 spin_unlock_irqrestore(&host->lock, flags);
2022 sdhci_runtime_pm_put(host);
2023
2024 return err;
2025 }
2026
2027 static int sdhci_select_drive_strength(struct mmc_card *card,
2028 unsigned int max_dtr, int host_drv,
2029 int card_drv, int *drv_type)
2030 {
2031 struct sdhci_host *host = mmc_priv(card->host);
2032
2033 if (!host->ops->select_drive_strength)
2034 return 0;
2035
2036 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2037 card_drv, drv_type);
2038 }
2039
2040 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2041 {
2042 /* Host Controller v3.00 defines preset value registers */
2043 if (host->version < SDHCI_SPEC_300)
2044 return;
2045
2046 /*
2047 * We only enable or disable Preset Value if they are not already
2048 * enabled or disabled respectively. Otherwise, we bail out.
2049 */
2050 if (host->preset_enabled != enable) {
2051 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2052
2053 if (enable)
2054 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2055 else
2056 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2057
2058 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2059
2060 if (enable)
2061 host->flags |= SDHCI_PV_ENABLED;
2062 else
2063 host->flags &= ~SDHCI_PV_ENABLED;
2064
2065 host->preset_enabled = enable;
2066 }
2067 }
2068
2069 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2070 int err)
2071 {
2072 struct sdhci_host *host = mmc_priv(mmc);
2073 struct mmc_data *data = mrq->data;
2074
2075 if (data->host_cookie != COOKIE_UNMAPPED)
2076 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2077 data->flags & MMC_DATA_WRITE ?
2078 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2079
2080 data->host_cookie = COOKIE_UNMAPPED;
2081 }
2082
2083 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2084 bool is_first_req)
2085 {
2086 struct sdhci_host *host = mmc_priv(mmc);
2087
2088 mrq->data->host_cookie = COOKIE_UNMAPPED;
2089
2090 if (host->flags & SDHCI_REQ_USE_DMA)
2091 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2092 }
2093
2094 static void sdhci_card_event(struct mmc_host *mmc)
2095 {
2096 struct sdhci_host *host = mmc_priv(mmc);
2097 unsigned long flags;
2098 int present;
2099
2100 /* First check if client has provided their own card event */
2101 if (host->ops->card_event)
2102 host->ops->card_event(host);
2103
2104 present = sdhci_do_get_cd(host);
2105
2106 spin_lock_irqsave(&host->lock, flags);
2107
2108 /* Check host->mrq first in case we are runtime suspended */
2109 if (host->mrq && !present) {
2110 pr_err("%s: Card removed during transfer!\n",
2111 mmc_hostname(host->mmc));
2112 pr_err("%s: Resetting controller.\n",
2113 mmc_hostname(host->mmc));
2114
2115 sdhci_do_reset(host, SDHCI_RESET_CMD);
2116 sdhci_do_reset(host, SDHCI_RESET_DATA);
2117
2118 host->mrq->cmd->error = -ENOMEDIUM;
2119 tasklet_schedule(&host->finish_tasklet);
2120 }
2121
2122 spin_unlock_irqrestore(&host->lock, flags);
2123 }
2124
2125 static const struct mmc_host_ops sdhci_ops = {
2126 .request = sdhci_request,
2127 .post_req = sdhci_post_req,
2128 .pre_req = sdhci_pre_req,
2129 .set_ios = sdhci_set_ios,
2130 .get_cd = sdhci_get_cd,
2131 .get_ro = sdhci_get_ro,
2132 .hw_reset = sdhci_hw_reset,
2133 .enable_sdio_irq = sdhci_enable_sdio_irq,
2134 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2135 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2136 .execute_tuning = sdhci_execute_tuning,
2137 .select_drive_strength = sdhci_select_drive_strength,
2138 .card_event = sdhci_card_event,
2139 .card_busy = sdhci_card_busy,
2140 };
2141
2142 /*****************************************************************************\
2143 * *
2144 * Tasklets *
2145 * *
2146 \*****************************************************************************/
2147
2148 static void sdhci_tasklet_finish(unsigned long param)
2149 {
2150 struct sdhci_host *host;
2151 unsigned long flags;
2152 struct mmc_request *mrq;
2153
2154 host = (struct sdhci_host*)param;
2155
2156 spin_lock_irqsave(&host->lock, flags);
2157
2158 /*
2159 * If this tasklet gets rescheduled while running, it will
2160 * be run again afterwards but without any active request.
2161 */
2162 if (!host->mrq) {
2163 spin_unlock_irqrestore(&host->lock, flags);
2164 return;
2165 }
2166
2167 del_timer(&host->timer);
2168
2169 mrq = host->mrq;
2170
2171 /*
2172 * Always unmap the data buffers if they were mapped by
2173 * sdhci_prepare_data() whenever we finish with a request.
2174 * This avoids leaking DMA mappings on error.
2175 */
2176 if (host->flags & SDHCI_REQ_USE_DMA) {
2177 struct mmc_data *data = mrq->data;
2178
2179 if (data && data->host_cookie == COOKIE_MAPPED) {
2180 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2181 (data->flags & MMC_DATA_READ) ?
2182 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2183 data->host_cookie = COOKIE_UNMAPPED;
2184 }
2185 }
2186
2187 /*
2188 * The controller needs a reset of internal state machines
2189 * upon error conditions.
2190 */
2191 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2192 ((mrq->cmd && mrq->cmd->error) ||
2193 (mrq->sbc && mrq->sbc->error) ||
2194 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2195 (mrq->data->stop && mrq->data->stop->error))) ||
2196 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2197
2198 /* Some controllers need this kick or reset won't work here */
2199 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2200 /* This is to force an update */
2201 host->ops->set_clock(host, host->clock);
2202
2203 /* Spec says we should do both at the same time, but Ricoh
2204 controllers do not like that. */
2205 sdhci_do_reset(host, SDHCI_RESET_CMD);
2206 sdhci_do_reset(host, SDHCI_RESET_DATA);
2207 }
2208
2209 host->mrq = NULL;
2210 host->cmd = NULL;
2211 host->data = NULL;
2212
2213 #ifndef SDHCI_USE_LEDS_CLASS
2214 sdhci_deactivate_led(host);
2215 #endif
2216
2217 mmiowb();
2218 spin_unlock_irqrestore(&host->lock, flags);
2219
2220 mmc_request_done(host->mmc, mrq);
2221 sdhci_runtime_pm_put(host);
2222 }
2223
2224 static void sdhci_timeout_timer(unsigned long data)
2225 {
2226 struct sdhci_host *host;
2227 unsigned long flags;
2228
2229 host = (struct sdhci_host*)data;
2230
2231 spin_lock_irqsave(&host->lock, flags);
2232
2233 if (host->mrq) {
2234 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2235 mmc_hostname(host->mmc));
2236 sdhci_dumpregs(host);
2237
2238 if (host->data) {
2239 host->data->error = -ETIMEDOUT;
2240 sdhci_finish_data(host);
2241 } else {
2242 if (host->cmd)
2243 host->cmd->error = -ETIMEDOUT;
2244 else
2245 host->mrq->cmd->error = -ETIMEDOUT;
2246
2247 tasklet_schedule(&host->finish_tasklet);
2248 }
2249 }
2250
2251 mmiowb();
2252 spin_unlock_irqrestore(&host->lock, flags);
2253 }
2254
2255 /*****************************************************************************\
2256 * *
2257 * Interrupt handling *
2258 * *
2259 \*****************************************************************************/
2260
2261 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2262 {
2263 BUG_ON(intmask == 0);
2264
2265 if (!host->cmd) {
2266 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2267 mmc_hostname(host->mmc), (unsigned)intmask);
2268 sdhci_dumpregs(host);
2269 return;
2270 }
2271
2272 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2273 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2274 if (intmask & SDHCI_INT_TIMEOUT)
2275 host->cmd->error = -ETIMEDOUT;
2276 else
2277 host->cmd->error = -EILSEQ;
2278
2279 /*
2280 * If this command initiates a data phase and a response
2281 * CRC error is signalled, the card can start transferring
2282 * data - the card may have received the command without
2283 * error. We must not terminate the mmc_request early.
2284 *
2285 * If the card did not receive the command or returned an
2286 * error which prevented it sending data, the data phase
2287 * will time out.
2288 */
2289 if (host->cmd->data &&
2290 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2291 SDHCI_INT_CRC) {
2292 host->cmd = NULL;
2293 return;
2294 }
2295
2296 tasklet_schedule(&host->finish_tasklet);
2297 return;
2298 }
2299
2300 /*
2301 * The host can send and interrupt when the busy state has
2302 * ended, allowing us to wait without wasting CPU cycles.
2303 * Unfortunately this is overloaded on the "data complete"
2304 * interrupt, so we need to take some care when handling
2305 * it.
2306 *
2307 * Note: The 1.0 specification is a bit ambiguous about this
2308 * feature so there might be some problems with older
2309 * controllers.
2310 */
2311 if (host->cmd->flags & MMC_RSP_BUSY) {
2312 if (host->cmd->data)
2313 DBG("Cannot wait for busy signal when also doing a data transfer");
2314 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2315 && !host->busy_handle) {
2316 /* Mark that command complete before busy is ended */
2317 host->busy_handle = 1;
2318 return;
2319 }
2320
2321 /* The controller does not support the end-of-busy IRQ,
2322 * fall through and take the SDHCI_INT_RESPONSE */
2323 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2324 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2325 *mask &= ~SDHCI_INT_DATA_END;
2326 }
2327
2328 if (intmask & SDHCI_INT_RESPONSE)
2329 sdhci_finish_command(host);
2330 }
2331
2332 #ifdef CONFIG_MMC_DEBUG
2333 static void sdhci_adma_show_error(struct sdhci_host *host)
2334 {
2335 const char *name = mmc_hostname(host->mmc);
2336 void *desc = host->adma_table;
2337
2338 sdhci_dumpregs(host);
2339
2340 while (true) {
2341 struct sdhci_adma2_64_desc *dma_desc = desc;
2342
2343 if (host->flags & SDHCI_USE_64_BIT_DMA)
2344 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2345 name, desc, le32_to_cpu(dma_desc->addr_hi),
2346 le32_to_cpu(dma_desc->addr_lo),
2347 le16_to_cpu(dma_desc->len),
2348 le16_to_cpu(dma_desc->cmd));
2349 else
2350 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2351 name, desc, le32_to_cpu(dma_desc->addr_lo),
2352 le16_to_cpu(dma_desc->len),
2353 le16_to_cpu(dma_desc->cmd));
2354
2355 desc += host->desc_sz;
2356
2357 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2358 break;
2359 }
2360 }
2361 #else
2362 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2363 #endif
2364
2365 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2366 {
2367 u32 command;
2368 BUG_ON(intmask == 0);
2369
2370 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2371 if (intmask & SDHCI_INT_DATA_AVAIL) {
2372 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2373 if (command == MMC_SEND_TUNING_BLOCK ||
2374 command == MMC_SEND_TUNING_BLOCK_HS200) {
2375 host->tuning_done = 1;
2376 wake_up(&host->buf_ready_int);
2377 return;
2378 }
2379 }
2380
2381 if (!host->data) {
2382 /*
2383 * The "data complete" interrupt is also used to
2384 * indicate that a busy state has ended. See comment
2385 * above in sdhci_cmd_irq().
2386 */
2387 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2388 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2389 host->cmd->error = -ETIMEDOUT;
2390 tasklet_schedule(&host->finish_tasklet);
2391 return;
2392 }
2393 if (intmask & SDHCI_INT_DATA_END) {
2394 /*
2395 * Some cards handle busy-end interrupt
2396 * before the command completed, so make
2397 * sure we do things in the proper order.
2398 */
2399 if (host->busy_handle)
2400 sdhci_finish_command(host);
2401 else
2402 host->busy_handle = 1;
2403 return;
2404 }
2405 }
2406
2407 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2408 mmc_hostname(host->mmc), (unsigned)intmask);
2409 sdhci_dumpregs(host);
2410
2411 return;
2412 }
2413
2414 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2415 host->data->error = -ETIMEDOUT;
2416 else if (intmask & SDHCI_INT_DATA_END_BIT)
2417 host->data->error = -EILSEQ;
2418 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2419 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2420 != MMC_BUS_TEST_R)
2421 host->data->error = -EILSEQ;
2422 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2423 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2424 sdhci_adma_show_error(host);
2425 host->data->error = -EIO;
2426 if (host->ops->adma_workaround)
2427 host->ops->adma_workaround(host, intmask);
2428 }
2429
2430 if (host->data->error)
2431 sdhci_finish_data(host);
2432 else {
2433 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2434 sdhci_transfer_pio(host);
2435
2436 /*
2437 * We currently don't do anything fancy with DMA
2438 * boundaries, but as we can't disable the feature
2439 * we need to at least restart the transfer.
2440 *
2441 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2442 * should return a valid address to continue from, but as
2443 * some controllers are faulty, don't trust them.
2444 */
2445 if (intmask & SDHCI_INT_DMA_END) {
2446 u32 dmastart, dmanow;
2447 dmastart = sg_dma_address(host->data->sg);
2448 dmanow = dmastart + host->data->bytes_xfered;
2449 /*
2450 * Force update to the next DMA block boundary.
2451 */
2452 dmanow = (dmanow &
2453 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2454 SDHCI_DEFAULT_BOUNDARY_SIZE;
2455 host->data->bytes_xfered = dmanow - dmastart;
2456 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2457 " next 0x%08x\n",
2458 mmc_hostname(host->mmc), dmastart,
2459 host->data->bytes_xfered, dmanow);
2460 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2461 }
2462
2463 if (intmask & SDHCI_INT_DATA_END) {
2464 if (host->cmd) {
2465 /*
2466 * Data managed to finish before the
2467 * command completed. Make sure we do
2468 * things in the proper order.
2469 */
2470 host->data_early = 1;
2471 } else {
2472 sdhci_finish_data(host);
2473 }
2474 }
2475 }
2476 }
2477
2478 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2479 {
2480 irqreturn_t result = IRQ_NONE;
2481 struct sdhci_host *host = dev_id;
2482 u32 intmask, mask, unexpected = 0;
2483 int max_loops = 16;
2484
2485 spin_lock(&host->lock);
2486
2487 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2488 spin_unlock(&host->lock);
2489 return IRQ_NONE;
2490 }
2491
2492 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2493 if (!intmask || intmask == 0xffffffff) {
2494 result = IRQ_NONE;
2495 goto out;
2496 }
2497
2498 do {
2499 /* Clear selected interrupts. */
2500 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2501 SDHCI_INT_BUS_POWER);
2502 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2503
2504 DBG("*** %s got interrupt: 0x%08x\n",
2505 mmc_hostname(host->mmc), intmask);
2506
2507 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2508 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2509 SDHCI_CARD_PRESENT;
2510
2511 /*
2512 * There is a observation on i.mx esdhc. INSERT
2513 * bit will be immediately set again when it gets
2514 * cleared, if a card is inserted. We have to mask
2515 * the irq to prevent interrupt storm which will
2516 * freeze the system. And the REMOVE gets the
2517 * same situation.
2518 *
2519 * More testing are needed here to ensure it works
2520 * for other platforms though.
2521 */
2522 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2523 SDHCI_INT_CARD_REMOVE);
2524 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2525 SDHCI_INT_CARD_INSERT;
2526 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2527 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2528
2529 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2530 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2531
2532 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2533 SDHCI_INT_CARD_REMOVE);
2534 result = IRQ_WAKE_THREAD;
2535 }
2536
2537 if (intmask & SDHCI_INT_CMD_MASK)
2538 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2539 &intmask);
2540
2541 if (intmask & SDHCI_INT_DATA_MASK)
2542 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2543
2544 if (intmask & SDHCI_INT_BUS_POWER)
2545 pr_err("%s: Card is consuming too much power!\n",
2546 mmc_hostname(host->mmc));
2547
2548 if (intmask & SDHCI_INT_CARD_INT) {
2549 sdhci_enable_sdio_irq_nolock(host, false);
2550 host->thread_isr |= SDHCI_INT_CARD_INT;
2551 result = IRQ_WAKE_THREAD;
2552 }
2553
2554 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2555 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2556 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2557 SDHCI_INT_CARD_INT);
2558
2559 if (intmask) {
2560 unexpected |= intmask;
2561 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2562 }
2563
2564 if (result == IRQ_NONE)
2565 result = IRQ_HANDLED;
2566
2567 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2568 } while (intmask && --max_loops);
2569 out:
2570 spin_unlock(&host->lock);
2571
2572 if (unexpected) {
2573 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2574 mmc_hostname(host->mmc), unexpected);
2575 sdhci_dumpregs(host);
2576 }
2577
2578 return result;
2579 }
2580
2581 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2582 {
2583 struct sdhci_host *host = dev_id;
2584 unsigned long flags;
2585 u32 isr;
2586
2587 spin_lock_irqsave(&host->lock, flags);
2588 isr = host->thread_isr;
2589 host->thread_isr = 0;
2590 spin_unlock_irqrestore(&host->lock, flags);
2591
2592 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2593 sdhci_card_event(host->mmc);
2594 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2595 }
2596
2597 if (isr & SDHCI_INT_CARD_INT) {
2598 sdio_run_irqs(host->mmc);
2599
2600 spin_lock_irqsave(&host->lock, flags);
2601 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2602 sdhci_enable_sdio_irq_nolock(host, true);
2603 spin_unlock_irqrestore(&host->lock, flags);
2604 }
2605
2606 return isr ? IRQ_HANDLED : IRQ_NONE;
2607 }
2608
2609 /*****************************************************************************\
2610 * *
2611 * Suspend/resume *
2612 * *
2613 \*****************************************************************************/
2614
2615 #ifdef CONFIG_PM
2616 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2617 {
2618 u8 val;
2619 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2620 | SDHCI_WAKE_ON_INT;
2621
2622 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2623 val |= mask ;
2624 /* Avoid fake wake up */
2625 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2626 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2627 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2628 }
2629 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2630
2631 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2632 {
2633 u8 val;
2634 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2635 | SDHCI_WAKE_ON_INT;
2636
2637 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2638 val &= ~mask;
2639 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2640 }
2641
2642 int sdhci_suspend_host(struct sdhci_host *host)
2643 {
2644 sdhci_disable_card_detection(host);
2645
2646 mmc_retune_timer_stop(host->mmc);
2647 mmc_retune_needed(host->mmc);
2648
2649 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2650 host->ier = 0;
2651 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2652 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2653 free_irq(host->irq, host);
2654 } else {
2655 sdhci_enable_irq_wakeups(host);
2656 enable_irq_wake(host->irq);
2657 }
2658 return 0;
2659 }
2660
2661 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2662
2663 int sdhci_resume_host(struct sdhci_host *host)
2664 {
2665 int ret = 0;
2666
2667 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2668 if (host->ops->enable_dma)
2669 host->ops->enable_dma(host);
2670 }
2671
2672 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2673 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2674 /* Card keeps power but host controller does not */
2675 sdhci_init(host, 0);
2676 host->pwr = 0;
2677 host->clock = 0;
2678 sdhci_do_set_ios(host, &host->mmc->ios);
2679 } else {
2680 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2681 mmiowb();
2682 }
2683
2684 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2685 ret = request_threaded_irq(host->irq, sdhci_irq,
2686 sdhci_thread_irq, IRQF_SHARED,
2687 mmc_hostname(host->mmc), host);
2688 if (ret)
2689 return ret;
2690 } else {
2691 sdhci_disable_irq_wakeups(host);
2692 disable_irq_wake(host->irq);
2693 }
2694
2695 sdhci_enable_card_detection(host);
2696
2697 return ret;
2698 }
2699
2700 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2701
2702 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2703 {
2704 return pm_runtime_get_sync(host->mmc->parent);
2705 }
2706
2707 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2708 {
2709 pm_runtime_mark_last_busy(host->mmc->parent);
2710 return pm_runtime_put_autosuspend(host->mmc->parent);
2711 }
2712
2713 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2714 {
2715 if (host->bus_on)
2716 return;
2717 host->bus_on = true;
2718 pm_runtime_get_noresume(host->mmc->parent);
2719 }
2720
2721 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2722 {
2723 if (!host->bus_on)
2724 return;
2725 host->bus_on = false;
2726 pm_runtime_put_noidle(host->mmc->parent);
2727 }
2728
2729 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2730 {
2731 unsigned long flags;
2732
2733 mmc_retune_timer_stop(host->mmc);
2734 mmc_retune_needed(host->mmc);
2735
2736 spin_lock_irqsave(&host->lock, flags);
2737 host->ier &= SDHCI_INT_CARD_INT;
2738 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2739 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2740 spin_unlock_irqrestore(&host->lock, flags);
2741
2742 synchronize_hardirq(host->irq);
2743
2744 spin_lock_irqsave(&host->lock, flags);
2745 host->runtime_suspended = true;
2746 spin_unlock_irqrestore(&host->lock, flags);
2747
2748 return 0;
2749 }
2750 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2751
2752 int sdhci_runtime_resume_host(struct sdhci_host *host)
2753 {
2754 unsigned long flags;
2755 int host_flags = host->flags;
2756
2757 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2758 if (host->ops->enable_dma)
2759 host->ops->enable_dma(host);
2760 }
2761
2762 sdhci_init(host, 0);
2763
2764 /* Force clock and power re-program */
2765 host->pwr = 0;
2766 host->clock = 0;
2767 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2768 sdhci_do_set_ios(host, &host->mmc->ios);
2769
2770 if ((host_flags & SDHCI_PV_ENABLED) &&
2771 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2772 spin_lock_irqsave(&host->lock, flags);
2773 sdhci_enable_preset_value(host, true);
2774 spin_unlock_irqrestore(&host->lock, flags);
2775 }
2776
2777 spin_lock_irqsave(&host->lock, flags);
2778
2779 host->runtime_suspended = false;
2780
2781 /* Enable SDIO IRQ */
2782 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2783 sdhci_enable_sdio_irq_nolock(host, true);
2784
2785 /* Enable Card Detection */
2786 sdhci_enable_card_detection(host);
2787
2788 spin_unlock_irqrestore(&host->lock, flags);
2789
2790 return 0;
2791 }
2792 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2793
2794 #endif /* CONFIG_PM */
2795
2796 /*****************************************************************************\
2797 * *
2798 * Device allocation/registration *
2799 * *
2800 \*****************************************************************************/
2801
2802 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2803 size_t priv_size)
2804 {
2805 struct mmc_host *mmc;
2806 struct sdhci_host *host;
2807
2808 WARN_ON(dev == NULL);
2809
2810 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2811 if (!mmc)
2812 return ERR_PTR(-ENOMEM);
2813
2814 host = mmc_priv(mmc);
2815 host->mmc = mmc;
2816 host->mmc_host_ops = sdhci_ops;
2817 mmc->ops = &host->mmc_host_ops;
2818
2819 return host;
2820 }
2821
2822 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2823
2824 int sdhci_add_host(struct sdhci_host *host)
2825 {
2826 struct mmc_host *mmc;
2827 u32 caps[2] = {0, 0};
2828 u32 max_current_caps;
2829 unsigned int ocr_avail;
2830 unsigned int override_timeout_clk;
2831 u32 max_clk;
2832 int ret;
2833
2834 WARN_ON(host == NULL);
2835 if (host == NULL)
2836 return -EINVAL;
2837
2838 mmc = host->mmc;
2839
2840 if (debug_quirks)
2841 host->quirks = debug_quirks;
2842 if (debug_quirks2)
2843 host->quirks2 = debug_quirks2;
2844
2845 override_timeout_clk = host->timeout_clk;
2846
2847 sdhci_do_reset(host, SDHCI_RESET_ALL);
2848
2849 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2850 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2851 >> SDHCI_SPEC_VER_SHIFT;
2852 if (host->version > SDHCI_SPEC_300) {
2853 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2854 mmc_hostname(mmc), host->version);
2855 }
2856
2857 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2858 sdhci_readl(host, SDHCI_CAPABILITIES);
2859
2860 if (host->version >= SDHCI_SPEC_300)
2861 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2862 host->caps1 :
2863 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2864
2865 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2866 host->flags |= SDHCI_USE_SDMA;
2867 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2868 DBG("Controller doesn't have SDMA capability\n");
2869 else
2870 host->flags |= SDHCI_USE_SDMA;
2871
2872 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2873 (host->flags & SDHCI_USE_SDMA)) {
2874 DBG("Disabling DMA as it is marked broken\n");
2875 host->flags &= ~SDHCI_USE_SDMA;
2876 }
2877
2878 if ((host->version >= SDHCI_SPEC_200) &&
2879 (caps[0] & SDHCI_CAN_DO_ADMA2))
2880 host->flags |= SDHCI_USE_ADMA;
2881
2882 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2883 (host->flags & SDHCI_USE_ADMA)) {
2884 DBG("Disabling ADMA as it is marked broken\n");
2885 host->flags &= ~SDHCI_USE_ADMA;
2886 }
2887
2888 /*
2889 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2890 * and *must* do 64-bit DMA. A driver has the opportunity to change
2891 * that during the first call to ->enable_dma(). Similarly
2892 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2893 * implement.
2894 */
2895 if (caps[0] & SDHCI_CAN_64BIT)
2896 host->flags |= SDHCI_USE_64_BIT_DMA;
2897
2898 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2899 if (host->ops->enable_dma) {
2900 if (host->ops->enable_dma(host)) {
2901 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2902 mmc_hostname(mmc));
2903 host->flags &=
2904 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2905 }
2906 }
2907 }
2908
2909 /* SDMA does not support 64-bit DMA */
2910 if (host->flags & SDHCI_USE_64_BIT_DMA)
2911 host->flags &= ~SDHCI_USE_SDMA;
2912
2913 if (host->flags & SDHCI_USE_ADMA) {
2914 dma_addr_t dma;
2915 void *buf;
2916
2917 /*
2918 * The DMA descriptor table size is calculated as the maximum
2919 * number of segments times 2, to allow for an alignment
2920 * descriptor for each segment, plus 1 for a nop end descriptor,
2921 * all multipled by the descriptor size.
2922 */
2923 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2924 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2925 SDHCI_ADMA2_64_DESC_SZ;
2926 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2927 } else {
2928 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2929 SDHCI_ADMA2_32_DESC_SZ;
2930 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2931 }
2932
2933 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
2934 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2935 host->adma_table_sz, &dma, GFP_KERNEL);
2936 if (!buf) {
2937 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2938 mmc_hostname(mmc));
2939 host->flags &= ~SDHCI_USE_ADMA;
2940 } else if ((dma + host->align_buffer_sz) &
2941 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
2942 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2943 mmc_hostname(mmc));
2944 host->flags &= ~SDHCI_USE_ADMA;
2945 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2946 host->adma_table_sz, buf, dma);
2947 } else {
2948 host->align_buffer = buf;
2949 host->align_addr = dma;
2950
2951 host->adma_table = buf + host->align_buffer_sz;
2952 host->adma_addr = dma + host->align_buffer_sz;
2953 }
2954 }
2955
2956 /*
2957 * If we use DMA, then it's up to the caller to set the DMA
2958 * mask, but PIO does not need the hw shim so we set a new
2959 * mask here in that case.
2960 */
2961 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2962 host->dma_mask = DMA_BIT_MASK(64);
2963 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2964 }
2965
2966 if (host->version >= SDHCI_SPEC_300)
2967 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2968 >> SDHCI_CLOCK_BASE_SHIFT;
2969 else
2970 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2971 >> SDHCI_CLOCK_BASE_SHIFT;
2972
2973 host->max_clk *= 1000000;
2974 if (host->max_clk == 0 || host->quirks &
2975 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2976 if (!host->ops->get_max_clock) {
2977 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
2978 mmc_hostname(mmc));
2979 return -ENODEV;
2980 }
2981 host->max_clk = host->ops->get_max_clock(host);
2982 }
2983
2984 /*
2985 * In case of Host Controller v3.00, find out whether clock
2986 * multiplier is supported.
2987 */
2988 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2989 SDHCI_CLOCK_MUL_SHIFT;
2990
2991 /*
2992 * In case the value in Clock Multiplier is 0, then programmable
2993 * clock mode is not supported, otherwise the actual clock
2994 * multiplier is one more than the value of Clock Multiplier
2995 * in the Capabilities Register.
2996 */
2997 if (host->clk_mul)
2998 host->clk_mul += 1;
2999
3000 /*
3001 * Set host parameters.
3002 */
3003 max_clk = host->max_clk;
3004
3005 if (host->ops->get_min_clock)
3006 mmc->f_min = host->ops->get_min_clock(host);
3007 else if (host->version >= SDHCI_SPEC_300) {
3008 if (host->clk_mul) {
3009 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3010 max_clk = host->max_clk * host->clk_mul;
3011 } else
3012 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3013 } else
3014 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3015
3016 if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3017 mmc->f_max = max_clk;
3018
3019 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3020 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3021 SDHCI_TIMEOUT_CLK_SHIFT;
3022 if (host->timeout_clk == 0) {
3023 if (host->ops->get_timeout_clock) {
3024 host->timeout_clk =
3025 host->ops->get_timeout_clock(host);
3026 } else {
3027 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3028 mmc_hostname(mmc));
3029 return -ENODEV;
3030 }
3031 }
3032
3033 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3034 host->timeout_clk *= 1000;
3035
3036 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3037 host->ops->get_max_timeout_count(host) : 1 << 27;
3038 mmc->max_busy_timeout /= host->timeout_clk;
3039 }
3040
3041 if (override_timeout_clk)
3042 host->timeout_clk = override_timeout_clk;
3043
3044 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3045 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3046
3047 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3048 host->flags |= SDHCI_AUTO_CMD12;
3049
3050 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3051 if ((host->version >= SDHCI_SPEC_300) &&
3052 ((host->flags & SDHCI_USE_ADMA) ||
3053 !(host->flags & SDHCI_USE_SDMA)) &&
3054 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3055 host->flags |= SDHCI_AUTO_CMD23;
3056 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3057 } else {
3058 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3059 }
3060
3061 /*
3062 * A controller may support 8-bit width, but the board itself
3063 * might not have the pins brought out. Boards that support
3064 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3065 * their platform code before calling sdhci_add_host(), and we
3066 * won't assume 8-bit width for hosts without that CAP.
3067 */
3068 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3069 mmc->caps |= MMC_CAP_4_BIT_DATA;
3070
3071 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3072 mmc->caps &= ~MMC_CAP_CMD23;
3073
3074 if (caps[0] & SDHCI_CAN_DO_HISPD)
3075 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3076
3077 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3078 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3079 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3080 mmc->caps |= MMC_CAP_NEEDS_POLL;
3081
3082 /* If there are external regulators, get them */
3083 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3084 return -EPROBE_DEFER;
3085
3086 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3087 if (!IS_ERR(mmc->supply.vqmmc)) {
3088 ret = regulator_enable(mmc->supply.vqmmc);
3089 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3090 1950000))
3091 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3092 SDHCI_SUPPORT_SDR50 |
3093 SDHCI_SUPPORT_DDR50);
3094 if (ret) {
3095 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3096 mmc_hostname(mmc), ret);
3097 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3098 }
3099 }
3100
3101 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3102 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3103 SDHCI_SUPPORT_DDR50);
3104
3105 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3106 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3107 SDHCI_SUPPORT_DDR50))
3108 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3109
3110 /* SDR104 supports also implies SDR50 support */
3111 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3112 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3113 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3114 * field can be promoted to support HS200.
3115 */
3116 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3117 mmc->caps2 |= MMC_CAP2_HS200;
3118 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3119 mmc->caps |= MMC_CAP_UHS_SDR50;
3120
3121 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3122 (caps[1] & SDHCI_SUPPORT_HS400))
3123 mmc->caps2 |= MMC_CAP2_HS400;
3124
3125 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3126 (IS_ERR(mmc->supply.vqmmc) ||
3127 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3128 1300000)))
3129 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3130
3131 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3132 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3133 mmc->caps |= MMC_CAP_UHS_DDR50;
3134
3135 /* Does the host need tuning for SDR50? */
3136 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3137 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3138
3139 /* Does the host need tuning for SDR104 / HS200? */
3140 if (mmc->caps2 & MMC_CAP2_HS200)
3141 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3142
3143 /* Driver Type(s) (A, C, D) supported by the host */
3144 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3145 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3146 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3147 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3148 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3149 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3150
3151 /* Initial value for re-tuning timer count */
3152 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3153 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3154
3155 /*
3156 * In case Re-tuning Timer is not disabled, the actual value of
3157 * re-tuning timer will be 2 ^ (n - 1).
3158 */
3159 if (host->tuning_count)
3160 host->tuning_count = 1 << (host->tuning_count - 1);
3161
3162 /* Re-tuning mode supported by the Host Controller */
3163 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3164 SDHCI_RETUNING_MODE_SHIFT;
3165
3166 ocr_avail = 0;
3167
3168 /*
3169 * According to SD Host Controller spec v3.00, if the Host System
3170 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3171 * the value is meaningful only if Voltage Support in the Capabilities
3172 * register is set. The actual current value is 4 times the register
3173 * value.
3174 */
3175 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3176 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3177 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3178 if (curr > 0) {
3179
3180 /* convert to SDHCI_MAX_CURRENT format */
3181 curr = curr/1000; /* convert to mA */
3182 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3183
3184 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3185 max_current_caps =
3186 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3187 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3188 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3189 }
3190 }
3191
3192 if (caps[0] & SDHCI_CAN_VDD_330) {
3193 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3194
3195 mmc->max_current_330 = ((max_current_caps &
3196 SDHCI_MAX_CURRENT_330_MASK) >>
3197 SDHCI_MAX_CURRENT_330_SHIFT) *
3198 SDHCI_MAX_CURRENT_MULTIPLIER;
3199 }
3200 if (caps[0] & SDHCI_CAN_VDD_300) {
3201 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3202
3203 mmc->max_current_300 = ((max_current_caps &
3204 SDHCI_MAX_CURRENT_300_MASK) >>
3205 SDHCI_MAX_CURRENT_300_SHIFT) *
3206 SDHCI_MAX_CURRENT_MULTIPLIER;
3207 }
3208 if (caps[0] & SDHCI_CAN_VDD_180) {
3209 ocr_avail |= MMC_VDD_165_195;
3210
3211 mmc->max_current_180 = ((max_current_caps &
3212 SDHCI_MAX_CURRENT_180_MASK) >>
3213 SDHCI_MAX_CURRENT_180_SHIFT) *
3214 SDHCI_MAX_CURRENT_MULTIPLIER;
3215 }
3216
3217 /* If OCR set by host, use it instead. */
3218 if (host->ocr_mask)
3219 ocr_avail = host->ocr_mask;
3220
3221 /* If OCR set by external regulators, give it highest prio. */
3222 if (mmc->ocr_avail)
3223 ocr_avail = mmc->ocr_avail;
3224
3225 mmc->ocr_avail = ocr_avail;
3226 mmc->ocr_avail_sdio = ocr_avail;
3227 if (host->ocr_avail_sdio)
3228 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3229 mmc->ocr_avail_sd = ocr_avail;
3230 if (host->ocr_avail_sd)
3231 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3232 else /* normal SD controllers don't support 1.8V */
3233 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3234 mmc->ocr_avail_mmc = ocr_avail;
3235 if (host->ocr_avail_mmc)
3236 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3237
3238 if (mmc->ocr_avail == 0) {
3239 pr_err("%s: Hardware doesn't report any support voltages.\n",
3240 mmc_hostname(mmc));
3241 return -ENODEV;
3242 }
3243
3244 spin_lock_init(&host->lock);
3245
3246 /*
3247 * Maximum number of segments. Depends on if the hardware
3248 * can do scatter/gather or not.
3249 */
3250 if (host->flags & SDHCI_USE_ADMA)
3251 mmc->max_segs = SDHCI_MAX_SEGS;
3252 else if (host->flags & SDHCI_USE_SDMA)
3253 mmc->max_segs = 1;
3254 else /* PIO */
3255 mmc->max_segs = SDHCI_MAX_SEGS;
3256
3257 /*
3258 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3259 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3260 * is less anyway.
3261 */
3262 mmc->max_req_size = 524288;
3263
3264 /*
3265 * Maximum segment size. Could be one segment with the maximum number
3266 * of bytes. When doing hardware scatter/gather, each entry cannot
3267 * be larger than 64 KiB though.
3268 */
3269 if (host->flags & SDHCI_USE_ADMA) {
3270 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3271 mmc->max_seg_size = 65535;
3272 else
3273 mmc->max_seg_size = 65536;
3274 } else {
3275 mmc->max_seg_size = mmc->max_req_size;
3276 }
3277
3278 /*
3279 * Maximum block size. This varies from controller to controller and
3280 * is specified in the capabilities register.
3281 */
3282 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3283 mmc->max_blk_size = 2;
3284 } else {
3285 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3286 SDHCI_MAX_BLOCK_SHIFT;
3287 if (mmc->max_blk_size >= 3) {
3288 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3289 mmc_hostname(mmc));
3290 mmc->max_blk_size = 0;
3291 }
3292 }
3293
3294 mmc->max_blk_size = 512 << mmc->max_blk_size;
3295
3296 /*
3297 * Maximum block count.
3298 */
3299 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3300
3301 /*
3302 * Init tasklets.
3303 */
3304 tasklet_init(&host->finish_tasklet,
3305 sdhci_tasklet_finish, (unsigned long)host);
3306
3307 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3308
3309 init_waitqueue_head(&host->buf_ready_int);
3310
3311 sdhci_init(host, 0);
3312
3313 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3314 IRQF_SHARED, mmc_hostname(mmc), host);
3315 if (ret) {
3316 pr_err("%s: Failed to request IRQ %d: %d\n",
3317 mmc_hostname(mmc), host->irq, ret);
3318 goto untasklet;
3319 }
3320
3321 #ifdef CONFIG_MMC_DEBUG
3322 sdhci_dumpregs(host);
3323 #endif
3324
3325 #ifdef SDHCI_USE_LEDS_CLASS
3326 snprintf(host->led_name, sizeof(host->led_name),
3327 "%s::", mmc_hostname(mmc));
3328 host->led.name = host->led_name;
3329 host->led.brightness = LED_OFF;
3330 host->led.default_trigger = mmc_hostname(mmc);
3331 host->led.brightness_set = sdhci_led_control;
3332
3333 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3334 if (ret) {
3335 pr_err("%s: Failed to register LED device: %d\n",
3336 mmc_hostname(mmc), ret);
3337 goto reset;
3338 }
3339 #endif
3340
3341 mmiowb();
3342
3343 mmc_add_host(mmc);
3344
3345 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3346 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3347 (host->flags & SDHCI_USE_ADMA) ?
3348 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3349 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3350
3351 sdhci_enable_card_detection(host);
3352
3353 return 0;
3354
3355 #ifdef SDHCI_USE_LEDS_CLASS
3356 reset:
3357 sdhci_do_reset(host, SDHCI_RESET_ALL);
3358 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3359 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3360 free_irq(host->irq, host);
3361 #endif
3362 untasklet:
3363 tasklet_kill(&host->finish_tasklet);
3364
3365 return ret;
3366 }
3367
3368 EXPORT_SYMBOL_GPL(sdhci_add_host);
3369
3370 void sdhci_remove_host(struct sdhci_host *host, int dead)
3371 {
3372 struct mmc_host *mmc = host->mmc;
3373 unsigned long flags;
3374
3375 if (dead) {
3376 spin_lock_irqsave(&host->lock, flags);
3377
3378 host->flags |= SDHCI_DEVICE_DEAD;
3379
3380 if (host->mrq) {
3381 pr_err("%s: Controller removed during "
3382 " transfer!\n", mmc_hostname(mmc));
3383
3384 host->mrq->cmd->error = -ENOMEDIUM;
3385 tasklet_schedule(&host->finish_tasklet);
3386 }
3387
3388 spin_unlock_irqrestore(&host->lock, flags);
3389 }
3390
3391 sdhci_disable_card_detection(host);
3392
3393 mmc_remove_host(mmc);
3394
3395 #ifdef SDHCI_USE_LEDS_CLASS
3396 led_classdev_unregister(&host->led);
3397 #endif
3398
3399 if (!dead)
3400 sdhci_do_reset(host, SDHCI_RESET_ALL);
3401
3402 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3403 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3404 free_irq(host->irq, host);
3405
3406 del_timer_sync(&host->timer);
3407
3408 tasklet_kill(&host->finish_tasklet);
3409
3410 if (!IS_ERR(mmc->supply.vqmmc))
3411 regulator_disable(mmc->supply.vqmmc);
3412
3413 if (host->align_buffer)
3414 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3415 host->adma_table_sz, host->align_buffer,
3416 host->align_addr);
3417
3418 host->adma_table = NULL;
3419 host->align_buffer = NULL;
3420 }
3421
3422 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3423
3424 void sdhci_free_host(struct sdhci_host *host)
3425 {
3426 mmc_free_host(host->mmc);
3427 }
3428
3429 EXPORT_SYMBOL_GPL(sdhci_free_host);
3430
3431 /*****************************************************************************\
3432 * *
3433 * Driver init/exit *
3434 * *
3435 \*****************************************************************************/
3436
3437 static int __init sdhci_drv_init(void)
3438 {
3439 pr_info(DRIVER_NAME
3440 ": Secure Digital Host Controller Interface driver\n");
3441 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3442
3443 return 0;
3444 }
3445
3446 static void __exit sdhci_drv_exit(void)
3447 {
3448 }
3449
3450 module_init(sdhci_drv_init);
3451 module_exit(sdhci_drv_exit);
3452
3453 module_param(debug_quirks, uint, 0444);
3454 module_param(debug_quirks2, uint, 0444);
3455
3456 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3457 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3458 MODULE_LICENSE("GPL");
3459
3460 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3461 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Ubuntu Artful kernel mirror