2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
36 #define DRIVER_NAME "sdhci"
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
46 #define MAX_TUNING_LOOP 40
48 static unsigned int debug_quirks
= 0;
49 static unsigned int debug_quirks2
;
51 static void sdhci_finish_data(struct sdhci_host
*);
53 static void sdhci_finish_command(struct sdhci_host
*);
54 static int sdhci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
);
55 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
);
56 static int sdhci_pre_dma_transfer(struct sdhci_host
*host
,
57 struct mmc_data
*data
);
58 static int sdhci_do_get_cd(struct sdhci_host
*host
);
61 static int sdhci_runtime_pm_get(struct sdhci_host
*host
);
62 static int sdhci_runtime_pm_put(struct sdhci_host
*host
);
63 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
);
64 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
);
66 static inline int sdhci_runtime_pm_get(struct sdhci_host
*host
)
70 static inline int sdhci_runtime_pm_put(struct sdhci_host
*host
)
74 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
)
77 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
)
82 static void sdhci_dumpregs(struct sdhci_host
*host
)
84 pr_debug(DRIVER_NAME
": =========== REGISTER DUMP (%s)===========\n",
85 mmc_hostname(host
->mmc
));
87 pr_debug(DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
88 sdhci_readl(host
, SDHCI_DMA_ADDRESS
),
89 sdhci_readw(host
, SDHCI_HOST_VERSION
));
90 pr_debug(DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
91 sdhci_readw(host
, SDHCI_BLOCK_SIZE
),
92 sdhci_readw(host
, SDHCI_BLOCK_COUNT
));
93 pr_debug(DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
94 sdhci_readl(host
, SDHCI_ARGUMENT
),
95 sdhci_readw(host
, SDHCI_TRANSFER_MODE
));
96 pr_debug(DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
97 sdhci_readl(host
, SDHCI_PRESENT_STATE
),
98 sdhci_readb(host
, SDHCI_HOST_CONTROL
));
99 pr_debug(DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
100 sdhci_readb(host
, SDHCI_POWER_CONTROL
),
101 sdhci_readb(host
, SDHCI_BLOCK_GAP_CONTROL
));
102 pr_debug(DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
103 sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
),
104 sdhci_readw(host
, SDHCI_CLOCK_CONTROL
));
105 pr_debug(DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
106 sdhci_readb(host
, SDHCI_TIMEOUT_CONTROL
),
107 sdhci_readl(host
, SDHCI_INT_STATUS
));
108 pr_debug(DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
109 sdhci_readl(host
, SDHCI_INT_ENABLE
),
110 sdhci_readl(host
, SDHCI_SIGNAL_ENABLE
));
111 pr_debug(DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
112 sdhci_readw(host
, SDHCI_ACMD12_ERR
),
113 sdhci_readw(host
, SDHCI_SLOT_INT_STATUS
));
114 pr_debug(DRIVER_NAME
": Caps: 0x%08x | Caps_1: 0x%08x\n",
115 sdhci_readl(host
, SDHCI_CAPABILITIES
),
116 sdhci_readl(host
, SDHCI_CAPABILITIES_1
));
117 pr_debug(DRIVER_NAME
": Cmd: 0x%08x | Max curr: 0x%08x\n",
118 sdhci_readw(host
, SDHCI_COMMAND
),
119 sdhci_readl(host
, SDHCI_MAX_CURRENT
));
120 pr_debug(DRIVER_NAME
": Host ctl2: 0x%08x\n",
121 sdhci_readw(host
, SDHCI_HOST_CONTROL2
));
123 if (host
->flags
& SDHCI_USE_ADMA
) {
124 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
125 pr_debug(DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
126 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
127 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS_HI
),
128 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
130 pr_debug(DRIVER_NAME
": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
131 readl(host
->ioaddr
+ SDHCI_ADMA_ERROR
),
132 readl(host
->ioaddr
+ SDHCI_ADMA_ADDRESS
));
135 pr_debug(DRIVER_NAME
": ===========================================\n");
138 /*****************************************************************************\
140 * Low level functions *
142 \*****************************************************************************/
144 static void sdhci_set_card_detection(struct sdhci_host
*host
, bool enable
)
148 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) ||
149 (host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
))
153 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
156 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
157 SDHCI_INT_CARD_INSERT
;
159 host
->ier
&= ~(SDHCI_INT_CARD_REMOVE
| SDHCI_INT_CARD_INSERT
);
162 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
163 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
166 static void sdhci_enable_card_detection(struct sdhci_host
*host
)
168 sdhci_set_card_detection(host
, true);
171 static void sdhci_disable_card_detection(struct sdhci_host
*host
)
173 sdhci_set_card_detection(host
, false);
176 void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
178 unsigned long timeout
;
180 sdhci_writeb(host
, mask
, SDHCI_SOFTWARE_RESET
);
182 if (mask
& SDHCI_RESET_ALL
) {
184 /* Reset-all turns off SD Bus Power */
185 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
186 sdhci_runtime_pm_bus_off(host
);
189 /* Wait max 100 ms */
192 /* hw clears the bit when it's done */
193 while (sdhci_readb(host
, SDHCI_SOFTWARE_RESET
) & mask
) {
195 pr_err("%s: Reset 0x%x never completed.\n",
196 mmc_hostname(host
->mmc
), (int)mask
);
197 sdhci_dumpregs(host
);
204 EXPORT_SYMBOL_GPL(sdhci_reset
);
206 static void sdhci_do_reset(struct sdhci_host
*host
, u8 mask
)
208 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
209 if (!sdhci_do_get_cd(host
))
213 host
->ops
->reset(host
, mask
);
215 if (mask
& SDHCI_RESET_ALL
) {
216 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
217 if (host
->ops
->enable_dma
)
218 host
->ops
->enable_dma(host
);
221 /* Resetting the controller clears many */
222 host
->preset_enabled
= false;
226 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
);
228 static void sdhci_init(struct sdhci_host
*host
, int soft
)
231 sdhci_do_reset(host
, SDHCI_RESET_CMD
|SDHCI_RESET_DATA
);
233 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
235 host
->ier
= SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
236 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
|
237 SDHCI_INT_INDEX
| SDHCI_INT_END_BIT
| SDHCI_INT_CRC
|
238 SDHCI_INT_TIMEOUT
| SDHCI_INT_DATA_END
|
241 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
242 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
245 /* force clock reconfiguration */
247 sdhci_set_ios(host
->mmc
, &host
->mmc
->ios
);
251 static void sdhci_reinit(struct sdhci_host
*host
)
254 sdhci_enable_card_detection(host
);
257 static void sdhci_activate_led(struct sdhci_host
*host
)
261 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
262 ctrl
|= SDHCI_CTRL_LED
;
263 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
266 static void sdhci_deactivate_led(struct sdhci_host
*host
)
270 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
271 ctrl
&= ~SDHCI_CTRL_LED
;
272 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
275 #ifdef SDHCI_USE_LEDS_CLASS
276 static void sdhci_led_control(struct led_classdev
*led
,
277 enum led_brightness brightness
)
279 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
282 spin_lock_irqsave(&host
->lock
, flags
);
284 if (host
->runtime_suspended
)
287 if (brightness
== LED_OFF
)
288 sdhci_deactivate_led(host
);
290 sdhci_activate_led(host
);
292 spin_unlock_irqrestore(&host
->lock
, flags
);
296 /*****************************************************************************\
300 \*****************************************************************************/
302 static void sdhci_read_block_pio(struct sdhci_host
*host
)
305 size_t blksize
, len
, chunk
;
306 u32
uninitialized_var(scratch
);
309 DBG("PIO reading\n");
311 blksize
= host
->data
->blksz
;
314 local_irq_save(flags
);
317 BUG_ON(!sg_miter_next(&host
->sg_miter
));
319 len
= min(host
->sg_miter
.length
, blksize
);
322 host
->sg_miter
.consumed
= len
;
324 buf
= host
->sg_miter
.addr
;
328 scratch
= sdhci_readl(host
, SDHCI_BUFFER
);
332 *buf
= scratch
& 0xFF;
341 sg_miter_stop(&host
->sg_miter
);
343 local_irq_restore(flags
);
346 static void sdhci_write_block_pio(struct sdhci_host
*host
)
349 size_t blksize
, len
, chunk
;
353 DBG("PIO writing\n");
355 blksize
= host
->data
->blksz
;
359 local_irq_save(flags
);
362 BUG_ON(!sg_miter_next(&host
->sg_miter
));
364 len
= min(host
->sg_miter
.length
, blksize
);
367 host
->sg_miter
.consumed
= len
;
369 buf
= host
->sg_miter
.addr
;
372 scratch
|= (u32
)*buf
<< (chunk
* 8);
378 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
379 sdhci_writel(host
, scratch
, SDHCI_BUFFER
);
386 sg_miter_stop(&host
->sg_miter
);
388 local_irq_restore(flags
);
391 static void sdhci_transfer_pio(struct sdhci_host
*host
)
397 if (host
->blocks
== 0)
400 if (host
->data
->flags
& MMC_DATA_READ
)
401 mask
= SDHCI_DATA_AVAILABLE
;
403 mask
= SDHCI_SPACE_AVAILABLE
;
406 * Some controllers (JMicron JMB38x) mess up the buffer bits
407 * for transfers < 4 bytes. As long as it is just one block,
408 * we can ignore the bits.
410 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_SMALL_PIO
) &&
411 (host
->data
->blocks
== 1))
414 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
415 if (host
->quirks
& SDHCI_QUIRK_PIO_NEEDS_DELAY
)
418 if (host
->data
->flags
& MMC_DATA_READ
)
419 sdhci_read_block_pio(host
);
421 sdhci_write_block_pio(host
);
424 if (host
->blocks
== 0)
428 DBG("PIO transfer complete.\n");
431 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
433 local_irq_save(*flags
);
434 return kmap_atomic(sg_page(sg
)) + sg
->offset
;
437 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
439 kunmap_atomic(buffer
);
440 local_irq_restore(*flags
);
443 static void sdhci_adma_write_desc(struct sdhci_host
*host
, void *desc
,
444 dma_addr_t addr
, int len
, unsigned cmd
)
446 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
448 /* 32-bit and 64-bit descriptors have these members in same position */
449 dma_desc
->cmd
= cpu_to_le16(cmd
);
450 dma_desc
->len
= cpu_to_le16(len
);
451 dma_desc
->addr_lo
= cpu_to_le32((u32
)addr
);
453 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
454 dma_desc
->addr_hi
= cpu_to_le32((u64
)addr
>> 32);
457 static void sdhci_adma_mark_end(void *desc
)
459 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
461 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
462 dma_desc
->cmd
|= cpu_to_le16(ADMA2_END
);
465 static int sdhci_adma_table_pre(struct sdhci_host
*host
,
466 struct mmc_data
*data
)
473 dma_addr_t align_addr
;
476 struct scatterlist
*sg
;
482 * The spec does not specify endianness of descriptor table.
483 * We currently guess that it is LE.
486 if (data
->flags
& MMC_DATA_READ
)
487 direction
= DMA_FROM_DEVICE
;
489 direction
= DMA_TO_DEVICE
;
491 host
->align_addr
= dma_map_single(mmc_dev(host
->mmc
),
492 host
->align_buffer
, host
->align_buffer_sz
, direction
);
493 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->align_addr
))
495 BUG_ON(host
->align_addr
& SDHCI_ADMA2_MASK
);
497 host
->sg_count
= sdhci_pre_dma_transfer(host
, data
);
498 if (host
->sg_count
< 0)
501 desc
= host
->adma_table
;
502 align
= host
->align_buffer
;
504 align_addr
= host
->align_addr
;
506 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
507 addr
= sg_dma_address(sg
);
508 len
= sg_dma_len(sg
);
511 * The SDHCI specification states that ADMA
512 * addresses must be 32-bit aligned. If they
513 * aren't, then we use a bounce buffer for
514 * the (up to three) bytes that screw up the
517 offset
= (SDHCI_ADMA2_ALIGN
- (addr
& SDHCI_ADMA2_MASK
)) &
520 if (data
->flags
& MMC_DATA_WRITE
) {
521 buffer
= sdhci_kmap_atomic(sg
, &flags
);
522 memcpy(align
, buffer
, offset
);
523 sdhci_kunmap_atomic(buffer
, &flags
);
527 sdhci_adma_write_desc(host
, desc
, align_addr
, offset
,
530 BUG_ON(offset
> 65536);
532 align
+= SDHCI_ADMA2_ALIGN
;
533 align_addr
+= SDHCI_ADMA2_ALIGN
;
535 desc
+= host
->desc_sz
;
545 sdhci_adma_write_desc(host
, desc
, addr
, len
,
547 desc
+= host
->desc_sz
;
551 * If this triggers then we have a calculation bug
554 WARN_ON((desc
- host
->adma_table
) >= host
->adma_table_sz
);
557 if (host
->quirks
& SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
) {
559 * Mark the last descriptor as the terminating descriptor
561 if (desc
!= host
->adma_table
) {
562 desc
-= host
->desc_sz
;
563 sdhci_adma_mark_end(desc
);
567 * Add a terminating entry.
570 /* nop, end, valid */
571 sdhci_adma_write_desc(host
, desc
, 0, 0, ADMA2_NOP_END_VALID
);
575 * Resync align buffer as we might have changed it.
577 if (data
->flags
& MMC_DATA_WRITE
) {
578 dma_sync_single_for_device(mmc_dev(host
->mmc
),
579 host
->align_addr
, host
->align_buffer_sz
, direction
);
585 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
586 host
->align_buffer_sz
, direction
);
591 static void sdhci_adma_table_post(struct sdhci_host
*host
,
592 struct mmc_data
*data
)
596 struct scatterlist
*sg
;
603 if (data
->flags
& MMC_DATA_READ
)
604 direction
= DMA_FROM_DEVICE
;
606 direction
= DMA_TO_DEVICE
;
608 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
609 host
->align_buffer_sz
, direction
);
611 /* Do a quick scan of the SG list for any unaligned mappings */
612 has_unaligned
= false;
613 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
)
614 if (sg_dma_address(sg
) & SDHCI_ADMA2_MASK
) {
615 has_unaligned
= true;
619 if (has_unaligned
&& data
->flags
& MMC_DATA_READ
) {
620 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
621 data
->sg_len
, direction
);
623 align
= host
->align_buffer
;
625 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
626 if (sg_dma_address(sg
) & SDHCI_ADMA2_MASK
) {
627 size
= SDHCI_ADMA2_ALIGN
-
628 (sg_dma_address(sg
) & SDHCI_ADMA2_MASK
);
630 buffer
= sdhci_kmap_atomic(sg
, &flags
);
631 memcpy(buffer
, align
, size
);
632 sdhci_kunmap_atomic(buffer
, &flags
);
634 align
+= SDHCI_ADMA2_ALIGN
;
639 if (data
->host_cookie
== COOKIE_MAPPED
) {
640 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
641 data
->sg_len
, direction
);
642 data
->host_cookie
= COOKIE_UNMAPPED
;
646 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
649 struct mmc_data
*data
= cmd
->data
;
650 unsigned target_timeout
, current_timeout
;
653 * If the host controller provides us with an incorrect timeout
654 * value, just skip the check and use 0xE. The hardware may take
655 * longer to time out, but that's much better than having a too-short
658 if (host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
)
661 /* Unspecified timeout, assume max */
662 if (!data
&& !cmd
->busy_timeout
)
667 target_timeout
= cmd
->busy_timeout
* 1000;
669 target_timeout
= data
->timeout_ns
/ 1000;
671 target_timeout
+= data
->timeout_clks
/ host
->clock
;
675 * Figure out needed cycles.
676 * We do this in steps in order to fit inside a 32 bit int.
677 * The first step is the minimum timeout, which will have a
678 * minimum resolution of 6 bits:
679 * (1) 2^13*1000 > 2^22,
680 * (2) host->timeout_clk < 2^16
685 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
686 while (current_timeout
< target_timeout
) {
688 current_timeout
<<= 1;
694 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
695 mmc_hostname(host
->mmc
), count
, cmd
->opcode
);
702 static void sdhci_set_transfer_irqs(struct sdhci_host
*host
)
704 u32 pio_irqs
= SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
;
705 u32 dma_irqs
= SDHCI_INT_DMA_END
| SDHCI_INT_ADMA_ERROR
;
707 if (host
->flags
& SDHCI_REQ_USE_DMA
)
708 host
->ier
= (host
->ier
& ~pio_irqs
) | dma_irqs
;
710 host
->ier
= (host
->ier
& ~dma_irqs
) | pio_irqs
;
712 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
713 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
716 static void sdhci_set_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
720 if (host
->ops
->set_timeout
) {
721 host
->ops
->set_timeout(host
, cmd
);
723 count
= sdhci_calc_timeout(host
, cmd
);
724 sdhci_writeb(host
, count
, SDHCI_TIMEOUT_CONTROL
);
728 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_command
*cmd
)
731 struct mmc_data
*data
= cmd
->data
;
736 if (data
|| (cmd
->flags
& MMC_RSP_BUSY
))
737 sdhci_set_timeout(host
, cmd
);
743 BUG_ON(data
->blksz
* data
->blocks
> 524288);
744 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
745 BUG_ON(data
->blocks
> 65535);
748 host
->data_early
= 0;
749 host
->data
->bytes_xfered
= 0;
751 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))
752 host
->flags
|= SDHCI_REQ_USE_DMA
;
755 * FIXME: This doesn't account for merging when mapping the
758 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
760 struct scatterlist
*sg
;
763 if (host
->flags
& SDHCI_USE_ADMA
) {
764 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
767 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
771 if (unlikely(broken
)) {
772 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
773 if (sg
->length
& 0x3) {
774 DBG("Reverting to PIO because of transfer size (%d)\n",
776 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
784 * The assumption here being that alignment is the same after
785 * translation to device address space.
787 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
789 struct scatterlist
*sg
;
792 if (host
->flags
& SDHCI_USE_ADMA
) {
794 * As we use 3 byte chunks to work around
795 * alignment problems, we need to check this
798 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
801 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
805 if (unlikely(broken
)) {
806 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
807 if (sg
->offset
& 0x3) {
808 DBG("Reverting to PIO because of bad alignment\n");
809 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
816 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
817 if (host
->flags
& SDHCI_USE_ADMA
) {
818 ret
= sdhci_adma_table_pre(host
, data
);
821 * This only happens when someone fed
822 * us an invalid request.
825 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
827 sdhci_writel(host
, host
->adma_addr
,
829 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
831 (u64
)host
->adma_addr
>> 32,
832 SDHCI_ADMA_ADDRESS_HI
);
837 sg_cnt
= sdhci_pre_dma_transfer(host
, data
);
840 * This only happens when someone fed
841 * us an invalid request.
844 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
846 WARN_ON(sg_cnt
!= 1);
847 sdhci_writel(host
, sg_dma_address(data
->sg
),
854 * Always adjust the DMA selection as some controllers
855 * (e.g. JMicron) can't do PIO properly when the selection
858 if (host
->version
>= SDHCI_SPEC_200
) {
859 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
860 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
861 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
862 (host
->flags
& SDHCI_USE_ADMA
)) {
863 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
864 ctrl
|= SDHCI_CTRL_ADMA64
;
866 ctrl
|= SDHCI_CTRL_ADMA32
;
868 ctrl
|= SDHCI_CTRL_SDMA
;
870 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
873 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
876 flags
= SG_MITER_ATOMIC
;
877 if (host
->data
->flags
& MMC_DATA_READ
)
878 flags
|= SG_MITER_TO_SG
;
880 flags
|= SG_MITER_FROM_SG
;
881 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
882 host
->blocks
= data
->blocks
;
885 sdhci_set_transfer_irqs(host
);
887 /* Set the DMA boundary value and block size */
888 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG
,
889 data
->blksz
), SDHCI_BLOCK_SIZE
);
890 sdhci_writew(host
, data
->blocks
, SDHCI_BLOCK_COUNT
);
893 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
894 struct mmc_command
*cmd
)
897 struct mmc_data
*data
= cmd
->data
;
901 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD
) {
902 sdhci_writew(host
, 0x0, SDHCI_TRANSFER_MODE
);
904 /* clear Auto CMD settings for no data CMDs */
905 mode
= sdhci_readw(host
, SDHCI_TRANSFER_MODE
);
906 sdhci_writew(host
, mode
& ~(SDHCI_TRNS_AUTO_CMD12
|
907 SDHCI_TRNS_AUTO_CMD23
), SDHCI_TRANSFER_MODE
);
912 WARN_ON(!host
->data
);
914 if (!(host
->quirks2
& SDHCI_QUIRK2_SUPPORT_SINGLE
))
915 mode
= SDHCI_TRNS_BLK_CNT_EN
;
917 if (mmc_op_multi(cmd
->opcode
) || data
->blocks
> 1) {
918 mode
= SDHCI_TRNS_BLK_CNT_EN
| SDHCI_TRNS_MULTI
;
920 * If we are sending CMD23, CMD12 never gets sent
921 * on successful completion (so no Auto-CMD12).
923 if (!host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
) &&
924 (cmd
->opcode
!= SD_IO_RW_EXTENDED
))
925 mode
|= SDHCI_TRNS_AUTO_CMD12
;
926 else if (host
->mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD23
)) {
927 mode
|= SDHCI_TRNS_AUTO_CMD23
;
928 sdhci_writel(host
, host
->mrq
->sbc
->arg
, SDHCI_ARGUMENT2
);
932 if (data
->flags
& MMC_DATA_READ
)
933 mode
|= SDHCI_TRNS_READ
;
934 if (host
->flags
& SDHCI_REQ_USE_DMA
)
935 mode
|= SDHCI_TRNS_DMA
;
937 sdhci_writew(host
, mode
, SDHCI_TRANSFER_MODE
);
940 static void sdhci_finish_data(struct sdhci_host
*host
)
942 struct mmc_data
*data
;
949 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
950 if (host
->flags
& SDHCI_USE_ADMA
)
951 sdhci_adma_table_post(host
, data
);
953 if (data
->host_cookie
== COOKIE_MAPPED
) {
954 dma_unmap_sg(mmc_dev(host
->mmc
),
955 data
->sg
, data
->sg_len
,
956 (data
->flags
& MMC_DATA_READ
) ?
957 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
958 data
->host_cookie
= COOKIE_UNMAPPED
;
964 * The specification states that the block count register must
965 * be updated, but it does not specify at what point in the
966 * data flow. That makes the register entirely useless to read
967 * back so we have to assume that nothing made it to the card
968 * in the event of an error.
971 data
->bytes_xfered
= 0;
973 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
976 * Need to send CMD12 if -
977 * a) open-ended multiblock transfer (no CMD23)
978 * b) error in multiblock transfer
985 * The controller needs a reset of internal state machines
986 * upon error conditions.
989 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
990 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
993 sdhci_send_command(host
, data
->stop
);
995 tasklet_schedule(&host
->finish_tasklet
);
998 void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
1002 unsigned long timeout
;
1006 /* Wait max 10 ms */
1009 mask
= SDHCI_CMD_INHIBIT
;
1010 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
1011 mask
|= SDHCI_DATA_INHIBIT
;
1013 /* We shouldn't wait for data inihibit for stop commands, even
1014 though they might use busy signaling */
1015 if (host
->mrq
->data
&& (cmd
== host
->mrq
->data
->stop
))
1016 mask
&= ~SDHCI_DATA_INHIBIT
;
1018 while (sdhci_readl(host
, SDHCI_PRESENT_STATE
) & mask
) {
1020 pr_err("%s: Controller never released inhibit bit(s).\n",
1021 mmc_hostname(host
->mmc
));
1022 sdhci_dumpregs(host
);
1024 tasklet_schedule(&host
->finish_tasklet
);
1032 if (!cmd
->data
&& cmd
->busy_timeout
> 9000)
1033 timeout
+= DIV_ROUND_UP(cmd
->busy_timeout
, 1000) * HZ
+ HZ
;
1036 mod_timer(&host
->timer
, timeout
);
1039 host
->busy_handle
= 0;
1041 sdhci_prepare_data(host
, cmd
);
1043 sdhci_writel(host
, cmd
->arg
, SDHCI_ARGUMENT
);
1045 sdhci_set_transfer_mode(host
, cmd
);
1047 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
1048 pr_err("%s: Unsupported response type!\n",
1049 mmc_hostname(host
->mmc
));
1050 cmd
->error
= -EINVAL
;
1051 tasklet_schedule(&host
->finish_tasklet
);
1055 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
1056 flags
= SDHCI_CMD_RESP_NONE
;
1057 else if (cmd
->flags
& MMC_RSP_136
)
1058 flags
= SDHCI_CMD_RESP_LONG
;
1059 else if (cmd
->flags
& MMC_RSP_BUSY
)
1060 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
1062 flags
= SDHCI_CMD_RESP_SHORT
;
1064 if (cmd
->flags
& MMC_RSP_CRC
)
1065 flags
|= SDHCI_CMD_CRC
;
1066 if (cmd
->flags
& MMC_RSP_OPCODE
)
1067 flags
|= SDHCI_CMD_INDEX
;
1069 /* CMD19 is special in that the Data Present Select should be set */
1070 if (cmd
->data
|| cmd
->opcode
== MMC_SEND_TUNING_BLOCK
||
1071 cmd
->opcode
== MMC_SEND_TUNING_BLOCK_HS200
)
1072 flags
|= SDHCI_CMD_DATA
;
1074 sdhci_writew(host
, SDHCI_MAKE_CMD(cmd
->opcode
, flags
), SDHCI_COMMAND
);
1076 EXPORT_SYMBOL_GPL(sdhci_send_command
);
1078 static void sdhci_finish_command(struct sdhci_host
*host
)
1082 BUG_ON(host
->cmd
== NULL
);
1084 if (host
->cmd
->flags
& MMC_RSP_PRESENT
) {
1085 if (host
->cmd
->flags
& MMC_RSP_136
) {
1086 /* CRC is stripped so we need to do some shifting. */
1087 for (i
= 0;i
< 4;i
++) {
1088 host
->cmd
->resp
[i
] = sdhci_readl(host
,
1089 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
1091 host
->cmd
->resp
[i
] |=
1093 SDHCI_RESPONSE
+ (3-i
)*4-1);
1096 host
->cmd
->resp
[0] = sdhci_readl(host
, SDHCI_RESPONSE
);
1100 host
->cmd
->error
= 0;
1102 /* Finished CMD23, now send actual command. */
1103 if (host
->cmd
== host
->mrq
->sbc
) {
1105 sdhci_send_command(host
, host
->mrq
->cmd
);
1108 /* Processed actual command. */
1109 if (host
->data
&& host
->data_early
)
1110 sdhci_finish_data(host
);
1112 if (!host
->cmd
->data
)
1113 tasklet_schedule(&host
->finish_tasklet
);
1119 static u16
sdhci_get_preset_value(struct sdhci_host
*host
)
1123 switch (host
->timing
) {
1124 case MMC_TIMING_UHS_SDR12
:
1125 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1127 case MMC_TIMING_UHS_SDR25
:
1128 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR25
);
1130 case MMC_TIMING_UHS_SDR50
:
1131 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR50
);
1133 case MMC_TIMING_UHS_SDR104
:
1134 case MMC_TIMING_MMC_HS200
:
1135 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR104
);
1137 case MMC_TIMING_UHS_DDR50
:
1138 case MMC_TIMING_MMC_DDR52
:
1139 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_DDR50
);
1141 case MMC_TIMING_MMC_HS400
:
1142 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_HS400
);
1145 pr_warn("%s: Invalid UHS-I mode selected\n",
1146 mmc_hostname(host
->mmc
));
1147 preset
= sdhci_readw(host
, SDHCI_PRESET_FOR_SDR12
);
1153 void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1155 int div
= 0; /* Initialized for compiler warning */
1156 int real_div
= div
, clk_mul
= 1;
1158 unsigned long timeout
;
1159 bool switch_base_clk
= false;
1161 host
->mmc
->actual_clock
= 0;
1163 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1164 if (host
->quirks2
& SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST
)
1170 if (host
->version
>= SDHCI_SPEC_300
) {
1171 if (host
->preset_enabled
) {
1174 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1175 pre_val
= sdhci_get_preset_value(host
);
1176 div
= (pre_val
& SDHCI_PRESET_SDCLK_FREQ_MASK
)
1177 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT
;
1178 if (host
->clk_mul
&&
1179 (pre_val
& SDHCI_PRESET_CLKGEN_SEL_MASK
)) {
1180 clk
= SDHCI_PROG_CLOCK_MODE
;
1182 clk_mul
= host
->clk_mul
;
1184 real_div
= max_t(int, 1, div
<< 1);
1190 * Check if the Host Controller supports Programmable Clock
1193 if (host
->clk_mul
) {
1194 for (div
= 1; div
<= 1024; div
++) {
1195 if ((host
->max_clk
* host
->clk_mul
/ div
)
1199 if ((host
->max_clk
* host
->clk_mul
/ div
) <= clock
) {
1201 * Set Programmable Clock Mode in the Clock
1204 clk
= SDHCI_PROG_CLOCK_MODE
;
1206 clk_mul
= host
->clk_mul
;
1210 * Divisor can be too small to reach clock
1211 * speed requirement. Then use the base clock.
1213 switch_base_clk
= true;
1217 if (!host
->clk_mul
|| switch_base_clk
) {
1218 /* Version 3.00 divisors must be a multiple of 2. */
1219 if (host
->max_clk
<= clock
)
1222 for (div
= 2; div
< SDHCI_MAX_DIV_SPEC_300
;
1224 if ((host
->max_clk
/ div
) <= clock
)
1230 if ((host
->quirks2
& SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN
)
1231 && !div
&& host
->max_clk
<= 25000000)
1235 /* Version 2.00 divisors must be a power of 2. */
1236 for (div
= 1; div
< SDHCI_MAX_DIV_SPEC_200
; div
*= 2) {
1237 if ((host
->max_clk
/ div
) <= clock
)
1246 host
->mmc
->actual_clock
= (host
->max_clk
* clk_mul
) / real_div
;
1247 clk
|= (div
& SDHCI_DIV_MASK
) << SDHCI_DIVIDER_SHIFT
;
1248 clk
|= ((div
& SDHCI_DIV_HI_MASK
) >> SDHCI_DIV_MASK_LEN
)
1249 << SDHCI_DIVIDER_HI_SHIFT
;
1250 clk
|= SDHCI_CLOCK_INT_EN
;
1251 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1253 /* Wait max 20 ms */
1255 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
1256 & SDHCI_CLOCK_INT_STABLE
)) {
1258 pr_err("%s: Internal clock never stabilised.\n",
1259 mmc_hostname(host
->mmc
));
1260 sdhci_dumpregs(host
);
1267 clk
|= SDHCI_CLOCK_CARD_EN
;
1268 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1270 EXPORT_SYMBOL_GPL(sdhci_set_clock
);
1272 static void sdhci_set_power(struct sdhci_host
*host
, unsigned char mode
,
1275 struct mmc_host
*mmc
= host
->mmc
;
1278 if (mode
!= MMC_POWER_OFF
) {
1280 case MMC_VDD_165_195
:
1281 pwr
= SDHCI_POWER_180
;
1285 pwr
= SDHCI_POWER_300
;
1289 pwr
= SDHCI_POWER_330
;
1292 WARN(1, "%s: Invalid vdd %#x\n",
1293 mmc_hostname(host
->mmc
), vdd
);
1298 if (host
->pwr
== pwr
)
1304 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1305 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1306 sdhci_runtime_pm_bus_off(host
);
1310 * Spec says that we should clear the power reg before setting
1311 * a new value. Some controllers don't seem to like this though.
1313 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
1314 sdhci_writeb(host
, 0, SDHCI_POWER_CONTROL
);
1317 * At least the Marvell CaFe chip gets confused if we set the
1318 * voltage and set turn on power at the same time, so set the
1321 if (host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
)
1322 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1324 pwr
|= SDHCI_POWER_ON
;
1326 sdhci_writeb(host
, pwr
, SDHCI_POWER_CONTROL
);
1328 if (host
->quirks2
& SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON
)
1329 sdhci_runtime_pm_bus_on(host
);
1332 * Some controllers need an extra 10ms delay of 10ms before
1333 * they can apply clock after applying power
1335 if (host
->quirks
& SDHCI_QUIRK_DELAY_AFTER_POWER
)
1339 if (!IS_ERR(mmc
->supply
.vmmc
)) {
1340 spin_unlock_irq(&host
->lock
);
1341 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, vdd
);
1342 spin_lock_irq(&host
->lock
);
1346 /*****************************************************************************\
1350 \*****************************************************************************/
1352 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1354 struct sdhci_host
*host
;
1356 unsigned long flags
;
1358 host
= mmc_priv(mmc
);
1360 sdhci_runtime_pm_get(host
);
1362 /* Firstly check card presence */
1363 present
= mmc
->ops
->get_cd(mmc
);
1365 spin_lock_irqsave(&host
->lock
, flags
);
1367 WARN_ON(host
->mrq
!= NULL
);
1369 #ifndef SDHCI_USE_LEDS_CLASS
1370 sdhci_activate_led(host
);
1374 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1375 * requests if Auto-CMD12 is enabled.
1377 if (!mrq
->sbc
&& (host
->flags
& SDHCI_AUTO_CMD12
)) {
1379 mrq
->data
->stop
= NULL
;
1386 if (!present
|| host
->flags
& SDHCI_DEVICE_DEAD
) {
1387 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1388 tasklet_schedule(&host
->finish_tasklet
);
1390 if (mrq
->sbc
&& !(host
->flags
& SDHCI_AUTO_CMD23
))
1391 sdhci_send_command(host
, mrq
->sbc
);
1393 sdhci_send_command(host
, mrq
->cmd
);
1397 spin_unlock_irqrestore(&host
->lock
, flags
);
1400 void sdhci_set_bus_width(struct sdhci_host
*host
, int width
)
1404 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1405 if (width
== MMC_BUS_WIDTH_8
) {
1406 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1407 if (host
->version
>= SDHCI_SPEC_300
)
1408 ctrl
|= SDHCI_CTRL_8BITBUS
;
1410 if (host
->version
>= SDHCI_SPEC_300
)
1411 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
1412 if (width
== MMC_BUS_WIDTH_4
)
1413 ctrl
|= SDHCI_CTRL_4BITBUS
;
1415 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1417 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1419 EXPORT_SYMBOL_GPL(sdhci_set_bus_width
);
1421 void sdhci_set_uhs_signaling(struct sdhci_host
*host
, unsigned timing
)
1425 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1426 /* Select Bus Speed Mode for host */
1427 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1428 if ((timing
== MMC_TIMING_MMC_HS200
) ||
1429 (timing
== MMC_TIMING_UHS_SDR104
))
1430 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1431 else if (timing
== MMC_TIMING_UHS_SDR12
)
1432 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1433 else if (timing
== MMC_TIMING_UHS_SDR25
)
1434 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1435 else if (timing
== MMC_TIMING_UHS_SDR50
)
1436 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1437 else if ((timing
== MMC_TIMING_UHS_DDR50
) ||
1438 (timing
== MMC_TIMING_MMC_DDR52
))
1439 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1440 else if (timing
== MMC_TIMING_MMC_HS400
)
1441 ctrl_2
|= SDHCI_CTRL_HS400
; /* Non-standard */
1442 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1444 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling
);
1446 static void sdhci_do_set_ios(struct sdhci_host
*host
, struct mmc_ios
*ios
)
1448 unsigned long flags
;
1450 struct mmc_host
*mmc
= host
->mmc
;
1452 spin_lock_irqsave(&host
->lock
, flags
);
1454 if (host
->flags
& SDHCI_DEVICE_DEAD
) {
1455 spin_unlock_irqrestore(&host
->lock
, flags
);
1456 if (!IS_ERR(mmc
->supply
.vmmc
) &&
1457 ios
->power_mode
== MMC_POWER_OFF
)
1458 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, 0);
1463 * Reset the chip on each power off.
1464 * Should clear out any weird states.
1466 if (ios
->power_mode
== MMC_POWER_OFF
) {
1467 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
1471 if (host
->version
>= SDHCI_SPEC_300
&&
1472 (ios
->power_mode
== MMC_POWER_UP
) &&
1473 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
))
1474 sdhci_enable_preset_value(host
, false);
1476 if (!ios
->clock
|| ios
->clock
!= host
->clock
) {
1477 host
->ops
->set_clock(host
, ios
->clock
);
1478 host
->clock
= ios
->clock
;
1480 if (host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
&&
1482 host
->timeout_clk
= host
->mmc
->actual_clock
?
1483 host
->mmc
->actual_clock
/ 1000 :
1485 host
->mmc
->max_busy_timeout
=
1486 host
->ops
->get_max_timeout_count
?
1487 host
->ops
->get_max_timeout_count(host
) :
1489 host
->mmc
->max_busy_timeout
/= host
->timeout_clk
;
1493 sdhci_set_power(host
, ios
->power_mode
, ios
->vdd
);
1495 if (host
->ops
->platform_send_init_74_clocks
)
1496 host
->ops
->platform_send_init_74_clocks(host
, ios
->power_mode
);
1498 host
->ops
->set_bus_width(host
, ios
->bus_width
);
1500 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
1502 if ((ios
->timing
== MMC_TIMING_SD_HS
||
1503 ios
->timing
== MMC_TIMING_MMC_HS
)
1504 && !(host
->quirks
& SDHCI_QUIRK_NO_HISPD_BIT
))
1505 ctrl
|= SDHCI_CTRL_HISPD
;
1507 ctrl
&= ~SDHCI_CTRL_HISPD
;
1509 if (host
->version
>= SDHCI_SPEC_300
) {
1512 /* In case of UHS-I modes, set High Speed Enable */
1513 if ((ios
->timing
== MMC_TIMING_MMC_HS400
) ||
1514 (ios
->timing
== MMC_TIMING_MMC_HS200
) ||
1515 (ios
->timing
== MMC_TIMING_MMC_DDR52
) ||
1516 (ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1517 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1518 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1519 (ios
->timing
== MMC_TIMING_UHS_SDR25
))
1520 ctrl
|= SDHCI_CTRL_HISPD
;
1522 if (!host
->preset_enabled
) {
1523 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1525 * We only need to set Driver Strength if the
1526 * preset value enable is not set.
1528 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1529 ctrl_2
&= ~SDHCI_CTRL_DRV_TYPE_MASK
;
1530 if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_A
)
1531 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_A
;
1532 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_B
)
1533 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_B
;
1534 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_C
)
1535 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_C
;
1536 else if (ios
->drv_type
== MMC_SET_DRIVER_TYPE_D
)
1537 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_D
;
1539 pr_warn("%s: invalid driver type, default to driver type B\n",
1541 ctrl_2
|= SDHCI_CTRL_DRV_TYPE_B
;
1544 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1547 * According to SDHC Spec v3.00, if the Preset Value
1548 * Enable in the Host Control 2 register is set, we
1549 * need to reset SD Clock Enable before changing High
1550 * Speed Enable to avoid generating clock gliches.
1553 /* Reset SD Clock Enable */
1554 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1555 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1556 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1558 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1560 /* Re-enable SD Clock */
1561 host
->ops
->set_clock(host
, host
->clock
);
1564 /* Reset SD Clock Enable */
1565 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1566 clk
&= ~SDHCI_CLOCK_CARD_EN
;
1567 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
1569 host
->ops
->set_uhs_signaling(host
, ios
->timing
);
1570 host
->timing
= ios
->timing
;
1572 if (!(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
) &&
1573 ((ios
->timing
== MMC_TIMING_UHS_SDR12
) ||
1574 (ios
->timing
== MMC_TIMING_UHS_SDR25
) ||
1575 (ios
->timing
== MMC_TIMING_UHS_SDR50
) ||
1576 (ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1577 (ios
->timing
== MMC_TIMING_UHS_DDR50
) ||
1578 (ios
->timing
== MMC_TIMING_MMC_DDR52
))) {
1581 sdhci_enable_preset_value(host
, true);
1582 preset
= sdhci_get_preset_value(host
);
1583 ios
->drv_type
= (preset
& SDHCI_PRESET_DRV_MASK
)
1584 >> SDHCI_PRESET_DRV_SHIFT
;
1587 /* Re-enable SD Clock */
1588 host
->ops
->set_clock(host
, host
->clock
);
1590 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
1593 * Some (ENE) controllers go apeshit on some ios operation,
1594 * signalling timeout and CRC errors even on CMD0. Resetting
1595 * it on each ios seems to solve the problem.
1597 if (host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1598 sdhci_do_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1601 spin_unlock_irqrestore(&host
->lock
, flags
);
1604 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1606 struct sdhci_host
*host
= mmc_priv(mmc
);
1608 sdhci_runtime_pm_get(host
);
1609 sdhci_do_set_ios(host
, ios
);
1610 sdhci_runtime_pm_put(host
);
1613 static int sdhci_do_get_cd(struct sdhci_host
*host
)
1615 int gpio_cd
= mmc_gpio_get_cd(host
->mmc
);
1617 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1620 /* If nonremovable, assume that the card is always present. */
1621 if (host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
)
1625 * Try slot gpio detect, if defined it take precedence
1626 * over build in controller functionality
1628 if (!IS_ERR_VALUE(gpio_cd
))
1631 /* If polling, assume that the card is always present. */
1632 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
1635 /* Host native card detect */
1636 return !!(sdhci_readl(host
, SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
);
1639 static int sdhci_get_cd(struct mmc_host
*mmc
)
1641 struct sdhci_host
*host
= mmc_priv(mmc
);
1644 sdhci_runtime_pm_get(host
);
1645 ret
= sdhci_do_get_cd(host
);
1646 sdhci_runtime_pm_put(host
);
1650 static int sdhci_check_ro(struct sdhci_host
*host
)
1652 unsigned long flags
;
1655 spin_lock_irqsave(&host
->lock
, flags
);
1657 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1659 else if (host
->ops
->get_ro
)
1660 is_readonly
= host
->ops
->get_ro(host
);
1662 is_readonly
= !(sdhci_readl(host
, SDHCI_PRESENT_STATE
)
1663 & SDHCI_WRITE_PROTECT
);
1665 spin_unlock_irqrestore(&host
->lock
, flags
);
1667 /* This quirk needs to be replaced by a callback-function later */
1668 return host
->quirks
& SDHCI_QUIRK_INVERTED_WRITE_PROTECT
?
1669 !is_readonly
: is_readonly
;
1672 #define SAMPLE_COUNT 5
1674 static int sdhci_do_get_ro(struct sdhci_host
*host
)
1678 if (!(host
->quirks
& SDHCI_QUIRK_UNSTABLE_RO_DETECT
))
1679 return sdhci_check_ro(host
);
1682 for (i
= 0; i
< SAMPLE_COUNT
; i
++) {
1683 if (sdhci_check_ro(host
)) {
1684 if (++ro_count
> SAMPLE_COUNT
/ 2)
1692 static void sdhci_hw_reset(struct mmc_host
*mmc
)
1694 struct sdhci_host
*host
= mmc_priv(mmc
);
1696 if (host
->ops
&& host
->ops
->hw_reset
)
1697 host
->ops
->hw_reset(host
);
1700 static int sdhci_get_ro(struct mmc_host
*mmc
)
1702 struct sdhci_host
*host
= mmc_priv(mmc
);
1705 sdhci_runtime_pm_get(host
);
1706 ret
= sdhci_do_get_ro(host
);
1707 sdhci_runtime_pm_put(host
);
1711 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host
*host
, int enable
)
1713 if (!(host
->flags
& SDHCI_DEVICE_DEAD
)) {
1715 host
->ier
|= SDHCI_INT_CARD_INT
;
1717 host
->ier
&= ~SDHCI_INT_CARD_INT
;
1719 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
1720 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
1725 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1727 struct sdhci_host
*host
= mmc_priv(mmc
);
1728 unsigned long flags
;
1730 sdhci_runtime_pm_get(host
);
1732 spin_lock_irqsave(&host
->lock
, flags
);
1734 host
->flags
|= SDHCI_SDIO_IRQ_ENABLED
;
1736 host
->flags
&= ~SDHCI_SDIO_IRQ_ENABLED
;
1738 sdhci_enable_sdio_irq_nolock(host
, enable
);
1739 spin_unlock_irqrestore(&host
->lock
, flags
);
1741 sdhci_runtime_pm_put(host
);
1744 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host
*host
,
1745 struct mmc_ios
*ios
)
1747 struct mmc_host
*mmc
= host
->mmc
;
1752 * Signal Voltage Switching is only applicable for Host Controllers
1755 if (host
->version
< SDHCI_SPEC_300
)
1758 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1760 switch (ios
->signal_voltage
) {
1761 case MMC_SIGNAL_VOLTAGE_330
:
1762 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1763 ctrl
&= ~SDHCI_CTRL_VDD_180
;
1764 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1766 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1767 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
, 2700000,
1770 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1776 usleep_range(5000, 5500);
1778 /* 3.3V regulator output should be stable within 5 ms */
1779 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1780 if (!(ctrl
& SDHCI_CTRL_VDD_180
))
1783 pr_warn("%s: 3.3V regulator output did not became stable\n",
1787 case MMC_SIGNAL_VOLTAGE_180
:
1788 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1789 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
,
1792 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1799 * Enable 1.8V Signal Enable in the Host Control2
1802 ctrl
|= SDHCI_CTRL_VDD_180
;
1803 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1805 /* Some controller need to do more when switching */
1806 if (host
->ops
->voltage_switch
)
1807 host
->ops
->voltage_switch(host
);
1809 /* 1.8V regulator output should be stable within 5 ms */
1810 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1811 if (ctrl
& SDHCI_CTRL_VDD_180
)
1814 pr_warn("%s: 1.8V regulator output did not became stable\n",
1818 case MMC_SIGNAL_VOLTAGE_120
:
1819 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
1820 ret
= regulator_set_voltage(mmc
->supply
.vqmmc
, 1100000,
1823 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1830 /* No signal voltage switch required */
1835 static int sdhci_start_signal_voltage_switch(struct mmc_host
*mmc
,
1836 struct mmc_ios
*ios
)
1838 struct sdhci_host
*host
= mmc_priv(mmc
);
1841 if (host
->version
< SDHCI_SPEC_300
)
1843 sdhci_runtime_pm_get(host
);
1844 err
= sdhci_do_start_signal_voltage_switch(host
, ios
);
1845 sdhci_runtime_pm_put(host
);
1849 static int sdhci_card_busy(struct mmc_host
*mmc
)
1851 struct sdhci_host
*host
= mmc_priv(mmc
);
1854 sdhci_runtime_pm_get(host
);
1855 /* Check whether DAT[3:0] is 0000 */
1856 present_state
= sdhci_readl(host
, SDHCI_PRESENT_STATE
);
1857 sdhci_runtime_pm_put(host
);
1859 return !(present_state
& SDHCI_DATA_LVL_MASK
);
1862 static int sdhci_prepare_hs400_tuning(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1864 struct sdhci_host
*host
= mmc_priv(mmc
);
1865 unsigned long flags
;
1867 spin_lock_irqsave(&host
->lock
, flags
);
1868 host
->flags
|= SDHCI_HS400_TUNING
;
1869 spin_unlock_irqrestore(&host
->lock
, flags
);
1874 static int sdhci_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1876 struct sdhci_host
*host
= mmc_priv(mmc
);
1878 int tuning_loop_counter
= MAX_TUNING_LOOP
;
1880 unsigned long flags
;
1881 unsigned int tuning_count
= 0;
1884 sdhci_runtime_pm_get(host
);
1885 spin_lock_irqsave(&host
->lock
, flags
);
1887 hs400_tuning
= host
->flags
& SDHCI_HS400_TUNING
;
1888 host
->flags
&= ~SDHCI_HS400_TUNING
;
1890 if (host
->tuning_mode
== SDHCI_TUNING_MODE_1
)
1891 tuning_count
= host
->tuning_count
;
1894 * The Host Controller needs tuning in case of SDR104 and DDR50
1895 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1896 * the Capabilities register.
1897 * If the Host Controller supports the HS200 mode then the
1898 * tuning function has to be executed.
1900 switch (host
->timing
) {
1901 /* HS400 tuning is done in HS200 mode */
1902 case MMC_TIMING_MMC_HS400
:
1906 case MMC_TIMING_MMC_HS200
:
1908 * Periodic re-tuning for HS400 is not expected to be needed, so
1915 case MMC_TIMING_UHS_SDR104
:
1916 case MMC_TIMING_UHS_DDR50
:
1919 case MMC_TIMING_UHS_SDR50
:
1920 if (host
->flags
& SDHCI_SDR50_NEEDS_TUNING
||
1921 host
->flags
& SDHCI_SDR104_NEEDS_TUNING
)
1929 if (host
->ops
->platform_execute_tuning
) {
1930 spin_unlock_irqrestore(&host
->lock
, flags
);
1931 err
= host
->ops
->platform_execute_tuning(host
, opcode
);
1932 sdhci_runtime_pm_put(host
);
1936 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1937 ctrl
|= SDHCI_CTRL_EXEC_TUNING
;
1938 if (host
->quirks2
& SDHCI_QUIRK2_TUNING_WORK_AROUND
)
1939 ctrl
|= SDHCI_CTRL_TUNED_CLK
;
1940 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
1943 * As per the Host Controller spec v3.00, tuning command
1944 * generates Buffer Read Ready interrupt, so enable that.
1946 * Note: The spec clearly says that when tuning sequence
1947 * is being performed, the controller does not generate
1948 * interrupts other than Buffer Read Ready interrupt. But
1949 * to make sure we don't hit a controller bug, we _only_
1950 * enable Buffer Read Ready interrupt here.
1952 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_INT_ENABLE
);
1953 sdhci_writel(host
, SDHCI_INT_DATA_AVAIL
, SDHCI_SIGNAL_ENABLE
);
1956 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1957 * of loops reaches 40 times or a timeout of 150ms occurs.
1960 struct mmc_command cmd
= {0};
1961 struct mmc_request mrq
= {NULL
};
1963 cmd
.opcode
= opcode
;
1965 cmd
.flags
= MMC_RSP_R1
| MMC_CMD_ADTC
;
1970 if (tuning_loop_counter
-- == 0)
1977 * In response to CMD19, the card sends 64 bytes of tuning
1978 * block to the Host Controller. So we set the block size
1981 if (cmd
.opcode
== MMC_SEND_TUNING_BLOCK_HS200
) {
1982 if (mmc
->ios
.bus_width
== MMC_BUS_WIDTH_8
)
1983 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 128),
1985 else if (mmc
->ios
.bus_width
== MMC_BUS_WIDTH_4
)
1986 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64),
1989 sdhci_writew(host
, SDHCI_MAKE_BLKSZ(7, 64),
1994 * The tuning block is sent by the card to the host controller.
1995 * So we set the TRNS_READ bit in the Transfer Mode register.
1996 * This also takes care of setting DMA Enable and Multi Block
1997 * Select in the same register to 0.
1999 sdhci_writew(host
, SDHCI_TRNS_READ
, SDHCI_TRANSFER_MODE
);
2001 sdhci_send_command(host
, &cmd
);
2006 spin_unlock_irqrestore(&host
->lock
, flags
);
2007 /* Wait for Buffer Read Ready interrupt */
2008 wait_event_interruptible_timeout(host
->buf_ready_int
,
2009 (host
->tuning_done
== 1),
2010 msecs_to_jiffies(50));
2011 spin_lock_irqsave(&host
->lock
, flags
);
2013 if (!host
->tuning_done
) {
2014 pr_info(DRIVER_NAME
": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
2015 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2016 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
2017 ctrl
&= ~SDHCI_CTRL_EXEC_TUNING
;
2018 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2024 host
->tuning_done
= 0;
2026 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2028 /* eMMC spec does not require a delay between tuning cycles */
2029 if (opcode
== MMC_SEND_TUNING_BLOCK
)
2031 } while (ctrl
& SDHCI_CTRL_EXEC_TUNING
);
2034 * The Host Driver has exhausted the maximum number of loops allowed,
2035 * so use fixed sampling frequency.
2037 if (tuning_loop_counter
< 0) {
2038 ctrl
&= ~SDHCI_CTRL_TUNED_CLK
;
2039 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2041 if (!(ctrl
& SDHCI_CTRL_TUNED_CLK
)) {
2042 pr_info(DRIVER_NAME
": Tuning procedure failed, falling back to fixed sampling clock\n");
2049 * In case tuning fails, host controllers which support
2050 * re-tuning can try tuning again at a later time, when the
2051 * re-tuning timer expires. So for these controllers, we
2052 * return 0. Since there might be other controllers who do not
2053 * have this capability, we return error for them.
2058 host
->mmc
->retune_period
= err
? 0 : tuning_count
;
2060 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2061 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2063 spin_unlock_irqrestore(&host
->lock
, flags
);
2064 sdhci_runtime_pm_put(host
);
2069 static int sdhci_select_drive_strength(struct mmc_card
*card
,
2070 unsigned int max_dtr
, int host_drv
,
2071 int card_drv
, int *drv_type
)
2073 struct sdhci_host
*host
= mmc_priv(card
->host
);
2075 if (!host
->ops
->select_drive_strength
)
2078 return host
->ops
->select_drive_strength(host
, card
, max_dtr
, host_drv
,
2079 card_drv
, drv_type
);
2082 static void sdhci_enable_preset_value(struct sdhci_host
*host
, bool enable
)
2084 /* Host Controller v3.00 defines preset value registers */
2085 if (host
->version
< SDHCI_SPEC_300
)
2089 * We only enable or disable Preset Value if they are not already
2090 * enabled or disabled respectively. Otherwise, we bail out.
2092 if (host
->preset_enabled
!= enable
) {
2093 u16 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2096 ctrl
|= SDHCI_CTRL_PRESET_VAL_ENABLE
;
2098 ctrl
&= ~SDHCI_CTRL_PRESET_VAL_ENABLE
;
2100 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2103 host
->flags
|= SDHCI_PV_ENABLED
;
2105 host
->flags
&= ~SDHCI_PV_ENABLED
;
2107 host
->preset_enabled
= enable
;
2111 static void sdhci_post_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
2114 struct sdhci_host
*host
= mmc_priv(mmc
);
2115 struct mmc_data
*data
= mrq
->data
;
2117 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
2118 if (data
->host_cookie
== COOKIE_GIVEN
||
2119 data
->host_cookie
== COOKIE_MAPPED
)
2120 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
2121 data
->flags
& MMC_DATA_WRITE
?
2122 DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
2123 data
->host_cookie
= COOKIE_UNMAPPED
;
2127 static int sdhci_pre_dma_transfer(struct sdhci_host
*host
,
2128 struct mmc_data
*data
)
2132 if (data
->host_cookie
== COOKIE_MAPPED
) {
2133 data
->host_cookie
= COOKIE_GIVEN
;
2134 return data
->sg_count
;
2137 WARN_ON(data
->host_cookie
== COOKIE_GIVEN
);
2139 sg_count
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
, data
->sg_len
,
2140 data
->flags
& MMC_DATA_WRITE
?
2141 DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
2146 data
->sg_count
= sg_count
;
2147 data
->host_cookie
= COOKIE_MAPPED
;
2152 static void sdhci_pre_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
2155 struct sdhci_host
*host
= mmc_priv(mmc
);
2157 mrq
->data
->host_cookie
= COOKIE_UNMAPPED
;
2159 if (host
->flags
& SDHCI_REQ_USE_DMA
)
2160 sdhci_pre_dma_transfer(host
, mrq
->data
);
2163 static void sdhci_card_event(struct mmc_host
*mmc
)
2165 struct sdhci_host
*host
= mmc_priv(mmc
);
2166 unsigned long flags
;
2169 /* First check if client has provided their own card event */
2170 if (host
->ops
->card_event
)
2171 host
->ops
->card_event(host
);
2173 present
= sdhci_do_get_cd(host
);
2175 spin_lock_irqsave(&host
->lock
, flags
);
2177 /* Check host->mrq first in case we are runtime suspended */
2178 if (host
->mrq
&& !present
) {
2179 pr_err("%s: Card removed during transfer!\n",
2180 mmc_hostname(host
->mmc
));
2181 pr_err("%s: Resetting controller.\n",
2182 mmc_hostname(host
->mmc
));
2184 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2185 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2187 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
2188 tasklet_schedule(&host
->finish_tasklet
);
2191 spin_unlock_irqrestore(&host
->lock
, flags
);
2194 static const struct mmc_host_ops sdhci_ops
= {
2195 .request
= sdhci_request
,
2196 .post_req
= sdhci_post_req
,
2197 .pre_req
= sdhci_pre_req
,
2198 .set_ios
= sdhci_set_ios
,
2199 .get_cd
= sdhci_get_cd
,
2200 .get_ro
= sdhci_get_ro
,
2201 .hw_reset
= sdhci_hw_reset
,
2202 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
2203 .start_signal_voltage_switch
= sdhci_start_signal_voltage_switch
,
2204 .prepare_hs400_tuning
= sdhci_prepare_hs400_tuning
,
2205 .execute_tuning
= sdhci_execute_tuning
,
2206 .select_drive_strength
= sdhci_select_drive_strength
,
2207 .card_event
= sdhci_card_event
,
2208 .card_busy
= sdhci_card_busy
,
2211 /*****************************************************************************\
2215 \*****************************************************************************/
2217 static void sdhci_tasklet_finish(unsigned long param
)
2219 struct sdhci_host
*host
;
2220 unsigned long flags
;
2221 struct mmc_request
*mrq
;
2223 host
= (struct sdhci_host
*)param
;
2225 spin_lock_irqsave(&host
->lock
, flags
);
2228 * If this tasklet gets rescheduled while running, it will
2229 * be run again afterwards but without any active request.
2232 spin_unlock_irqrestore(&host
->lock
, flags
);
2236 del_timer(&host
->timer
);
2241 * The controller needs a reset of internal state machines
2242 * upon error conditions.
2244 if (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
2245 ((mrq
->cmd
&& mrq
->cmd
->error
) ||
2246 (mrq
->sbc
&& mrq
->sbc
->error
) ||
2247 (mrq
->data
&& ((mrq
->data
->error
&& !mrq
->data
->stop
) ||
2248 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
2249 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
))) {
2251 /* Some controllers need this kick or reset won't work here */
2252 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
)
2253 /* This is to force an update */
2254 host
->ops
->set_clock(host
, host
->clock
);
2256 /* Spec says we should do both at the same time, but Ricoh
2257 controllers do not like that. */
2258 sdhci_do_reset(host
, SDHCI_RESET_CMD
);
2259 sdhci_do_reset(host
, SDHCI_RESET_DATA
);
2266 #ifndef SDHCI_USE_LEDS_CLASS
2267 sdhci_deactivate_led(host
);
2271 spin_unlock_irqrestore(&host
->lock
, flags
);
2273 mmc_request_done(host
->mmc
, mrq
);
2274 sdhci_runtime_pm_put(host
);
2277 static void sdhci_timeout_timer(unsigned long data
)
2279 struct sdhci_host
*host
;
2280 unsigned long flags
;
2282 host
= (struct sdhci_host
*)data
;
2284 spin_lock_irqsave(&host
->lock
, flags
);
2287 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2288 mmc_hostname(host
->mmc
));
2289 sdhci_dumpregs(host
);
2292 host
->data
->error
= -ETIMEDOUT
;
2293 sdhci_finish_data(host
);
2296 host
->cmd
->error
= -ETIMEDOUT
;
2298 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
2300 tasklet_schedule(&host
->finish_tasklet
);
2305 spin_unlock_irqrestore(&host
->lock
, flags
);
2308 /*****************************************************************************\
2310 * Interrupt handling *
2312 \*****************************************************************************/
2314 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
, u32
*mask
)
2316 BUG_ON(intmask
== 0);
2319 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2320 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2321 sdhci_dumpregs(host
);
2325 if (intmask
& SDHCI_INT_TIMEOUT
)
2326 host
->cmd
->error
= -ETIMEDOUT
;
2327 else if (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_END_BIT
|
2329 host
->cmd
->error
= -EILSEQ
;
2331 if (host
->cmd
->error
) {
2332 tasklet_schedule(&host
->finish_tasklet
);
2337 * The host can send and interrupt when the busy state has
2338 * ended, allowing us to wait without wasting CPU cycles.
2339 * Unfortunately this is overloaded on the "data complete"
2340 * interrupt, so we need to take some care when handling
2343 * Note: The 1.0 specification is a bit ambiguous about this
2344 * feature so there might be some problems with older
2347 if (host
->cmd
->flags
& MMC_RSP_BUSY
) {
2348 if (host
->cmd
->data
)
2349 DBG("Cannot wait for busy signal when also doing a data transfer");
2350 else if (!(host
->quirks
& SDHCI_QUIRK_NO_BUSY_IRQ
)
2351 && !host
->busy_handle
) {
2352 /* Mark that command complete before busy is ended */
2353 host
->busy_handle
= 1;
2357 /* The controller does not support the end-of-busy IRQ,
2358 * fall through and take the SDHCI_INT_RESPONSE */
2359 } else if ((host
->quirks2
& SDHCI_QUIRK2_STOP_WITH_TC
) &&
2360 host
->cmd
->opcode
== MMC_STOP_TRANSMISSION
&& !host
->data
) {
2361 *mask
&= ~SDHCI_INT_DATA_END
;
2364 if (intmask
& SDHCI_INT_RESPONSE
)
2365 sdhci_finish_command(host
);
2368 #ifdef CONFIG_MMC_DEBUG
2369 static void sdhci_adma_show_error(struct sdhci_host
*host
)
2371 const char *name
= mmc_hostname(host
->mmc
);
2372 void *desc
= host
->adma_table
;
2374 sdhci_dumpregs(host
);
2377 struct sdhci_adma2_64_desc
*dma_desc
= desc
;
2379 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
2380 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2381 name
, desc
, le32_to_cpu(dma_desc
->addr_hi
),
2382 le32_to_cpu(dma_desc
->addr_lo
),
2383 le16_to_cpu(dma_desc
->len
),
2384 le16_to_cpu(dma_desc
->cmd
));
2386 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2387 name
, desc
, le32_to_cpu(dma_desc
->addr_lo
),
2388 le16_to_cpu(dma_desc
->len
),
2389 le16_to_cpu(dma_desc
->cmd
));
2391 desc
+= host
->desc_sz
;
2393 if (dma_desc
->cmd
& cpu_to_le16(ADMA2_END
))
2398 static void sdhci_adma_show_error(struct sdhci_host
*host
) { }
2401 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
2404 BUG_ON(intmask
== 0);
2406 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2407 if (intmask
& SDHCI_INT_DATA_AVAIL
) {
2408 command
= SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
));
2409 if (command
== MMC_SEND_TUNING_BLOCK
||
2410 command
== MMC_SEND_TUNING_BLOCK_HS200
) {
2411 host
->tuning_done
= 1;
2412 wake_up(&host
->buf_ready_int
);
2419 * The "data complete" interrupt is also used to
2420 * indicate that a busy state has ended. See comment
2421 * above in sdhci_cmd_irq().
2423 if (host
->cmd
&& (host
->cmd
->flags
& MMC_RSP_BUSY
)) {
2424 if (intmask
& SDHCI_INT_DATA_TIMEOUT
) {
2425 host
->cmd
->error
= -ETIMEDOUT
;
2426 tasklet_schedule(&host
->finish_tasklet
);
2429 if (intmask
& SDHCI_INT_DATA_END
) {
2431 * Some cards handle busy-end interrupt
2432 * before the command completed, so make
2433 * sure we do things in the proper order.
2435 if (host
->busy_handle
)
2436 sdhci_finish_command(host
);
2438 host
->busy_handle
= 1;
2443 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2444 mmc_hostname(host
->mmc
), (unsigned)intmask
);
2445 sdhci_dumpregs(host
);
2450 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
2451 host
->data
->error
= -ETIMEDOUT
;
2452 else if (intmask
& SDHCI_INT_DATA_END_BIT
)
2453 host
->data
->error
= -EILSEQ
;
2454 else if ((intmask
& SDHCI_INT_DATA_CRC
) &&
2455 SDHCI_GET_CMD(sdhci_readw(host
, SDHCI_COMMAND
))
2457 host
->data
->error
= -EILSEQ
;
2458 else if (intmask
& SDHCI_INT_ADMA_ERROR
) {
2459 pr_err("%s: ADMA error\n", mmc_hostname(host
->mmc
));
2460 sdhci_adma_show_error(host
);
2461 host
->data
->error
= -EIO
;
2462 if (host
->ops
->adma_workaround
)
2463 host
->ops
->adma_workaround(host
, intmask
);
2466 if (host
->data
->error
)
2467 sdhci_finish_data(host
);
2469 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
2470 sdhci_transfer_pio(host
);
2473 * We currently don't do anything fancy with DMA
2474 * boundaries, but as we can't disable the feature
2475 * we need to at least restart the transfer.
2477 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2478 * should return a valid address to continue from, but as
2479 * some controllers are faulty, don't trust them.
2481 if (intmask
& SDHCI_INT_DMA_END
) {
2482 u32 dmastart
, dmanow
;
2483 dmastart
= sg_dma_address(host
->data
->sg
);
2484 dmanow
= dmastart
+ host
->data
->bytes_xfered
;
2486 * Force update to the next DMA block boundary.
2489 ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1)) +
2490 SDHCI_DEFAULT_BOUNDARY_SIZE
;
2491 host
->data
->bytes_xfered
= dmanow
- dmastart
;
2492 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2494 mmc_hostname(host
->mmc
), dmastart
,
2495 host
->data
->bytes_xfered
, dmanow
);
2496 sdhci_writel(host
, dmanow
, SDHCI_DMA_ADDRESS
);
2499 if (intmask
& SDHCI_INT_DATA_END
) {
2502 * Data managed to finish before the
2503 * command completed. Make sure we do
2504 * things in the proper order.
2506 host
->data_early
= 1;
2508 sdhci_finish_data(host
);
2514 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
2516 irqreturn_t result
= IRQ_NONE
;
2517 struct sdhci_host
*host
= dev_id
;
2518 u32 intmask
, mask
, unexpected
= 0;
2521 spin_lock(&host
->lock
);
2523 if (host
->runtime_suspended
&& !sdhci_sdio_irq_enabled(host
)) {
2524 spin_unlock(&host
->lock
);
2528 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2529 if (!intmask
|| intmask
== 0xffffffff) {
2535 /* Clear selected interrupts. */
2536 mask
= intmask
& (SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2537 SDHCI_INT_BUS_POWER
);
2538 sdhci_writel(host
, mask
, SDHCI_INT_STATUS
);
2540 DBG("*** %s got interrupt: 0x%08x\n",
2541 mmc_hostname(host
->mmc
), intmask
);
2543 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2544 u32 present
= sdhci_readl(host
, SDHCI_PRESENT_STATE
) &
2548 * There is a observation on i.mx esdhc. INSERT
2549 * bit will be immediately set again when it gets
2550 * cleared, if a card is inserted. We have to mask
2551 * the irq to prevent interrupt storm which will
2552 * freeze the system. And the REMOVE gets the
2555 * More testing are needed here to ensure it works
2556 * for other platforms though.
2558 host
->ier
&= ~(SDHCI_INT_CARD_INSERT
|
2559 SDHCI_INT_CARD_REMOVE
);
2560 host
->ier
|= present
? SDHCI_INT_CARD_REMOVE
:
2561 SDHCI_INT_CARD_INSERT
;
2562 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2563 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2565 sdhci_writel(host
, intmask
& (SDHCI_INT_CARD_INSERT
|
2566 SDHCI_INT_CARD_REMOVE
), SDHCI_INT_STATUS
);
2568 host
->thread_isr
|= intmask
& (SDHCI_INT_CARD_INSERT
|
2569 SDHCI_INT_CARD_REMOVE
);
2570 result
= IRQ_WAKE_THREAD
;
2573 if (intmask
& SDHCI_INT_CMD_MASK
)
2574 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
,
2577 if (intmask
& SDHCI_INT_DATA_MASK
)
2578 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
2580 if (intmask
& SDHCI_INT_BUS_POWER
)
2581 pr_err("%s: Card is consuming too much power!\n",
2582 mmc_hostname(host
->mmc
));
2584 if (intmask
& SDHCI_INT_CARD_INT
) {
2585 sdhci_enable_sdio_irq_nolock(host
, false);
2586 host
->thread_isr
|= SDHCI_INT_CARD_INT
;
2587 result
= IRQ_WAKE_THREAD
;
2590 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
|
2591 SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
|
2592 SDHCI_INT_ERROR
| SDHCI_INT_BUS_POWER
|
2593 SDHCI_INT_CARD_INT
);
2596 unexpected
|= intmask
;
2597 sdhci_writel(host
, intmask
, SDHCI_INT_STATUS
);
2600 if (result
== IRQ_NONE
)
2601 result
= IRQ_HANDLED
;
2603 intmask
= sdhci_readl(host
, SDHCI_INT_STATUS
);
2604 } while (intmask
&& --max_loops
);
2606 spin_unlock(&host
->lock
);
2609 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2610 mmc_hostname(host
->mmc
), unexpected
);
2611 sdhci_dumpregs(host
);
2617 static irqreturn_t
sdhci_thread_irq(int irq
, void *dev_id
)
2619 struct sdhci_host
*host
= dev_id
;
2620 unsigned long flags
;
2623 spin_lock_irqsave(&host
->lock
, flags
);
2624 isr
= host
->thread_isr
;
2625 host
->thread_isr
= 0;
2626 spin_unlock_irqrestore(&host
->lock
, flags
);
2628 if (isr
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
2629 sdhci_card_event(host
->mmc
);
2630 mmc_detect_change(host
->mmc
, msecs_to_jiffies(200));
2633 if (isr
& SDHCI_INT_CARD_INT
) {
2634 sdio_run_irqs(host
->mmc
);
2636 spin_lock_irqsave(&host
->lock
, flags
);
2637 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2638 sdhci_enable_sdio_irq_nolock(host
, true);
2639 spin_unlock_irqrestore(&host
->lock
, flags
);
2642 return isr
? IRQ_HANDLED
: IRQ_NONE
;
2645 /*****************************************************************************\
2649 \*****************************************************************************/
2652 void sdhci_enable_irq_wakeups(struct sdhci_host
*host
)
2655 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2656 | SDHCI_WAKE_ON_INT
;
2658 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2660 /* Avoid fake wake up */
2661 if (host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
)
2662 val
&= ~(SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
);
2663 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2665 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups
);
2667 static void sdhci_disable_irq_wakeups(struct sdhci_host
*host
)
2670 u8 mask
= SDHCI_WAKE_ON_INSERT
| SDHCI_WAKE_ON_REMOVE
2671 | SDHCI_WAKE_ON_INT
;
2673 val
= sdhci_readb(host
, SDHCI_WAKE_UP_CONTROL
);
2675 sdhci_writeb(host
, val
, SDHCI_WAKE_UP_CONTROL
);
2678 int sdhci_suspend_host(struct sdhci_host
*host
)
2680 sdhci_disable_card_detection(host
);
2682 mmc_retune_timer_stop(host
->mmc
);
2683 mmc_retune_needed(host
->mmc
);
2685 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2687 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
2688 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
2689 free_irq(host
->irq
, host
);
2691 sdhci_enable_irq_wakeups(host
);
2692 enable_irq_wake(host
->irq
);
2697 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
2699 int sdhci_resume_host(struct sdhci_host
*host
)
2703 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2704 if (host
->ops
->enable_dma
)
2705 host
->ops
->enable_dma(host
);
2708 if ((host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
) &&
2709 (host
->quirks2
& SDHCI_QUIRK2_HOST_OFF_CARD_ON
)) {
2710 /* Card keeps power but host controller does not */
2711 sdhci_init(host
, 0);
2714 sdhci_do_set_ios(host
, &host
->mmc
->ios
);
2716 sdhci_init(host
, (host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
));
2720 if (!device_may_wakeup(mmc_dev(host
->mmc
))) {
2721 ret
= request_threaded_irq(host
->irq
, sdhci_irq
,
2722 sdhci_thread_irq
, IRQF_SHARED
,
2723 mmc_hostname(host
->mmc
), host
);
2727 sdhci_disable_irq_wakeups(host
);
2728 disable_irq_wake(host
->irq
);
2731 sdhci_enable_card_detection(host
);
2736 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
2738 static int sdhci_runtime_pm_get(struct sdhci_host
*host
)
2740 return pm_runtime_get_sync(host
->mmc
->parent
);
2743 static int sdhci_runtime_pm_put(struct sdhci_host
*host
)
2745 pm_runtime_mark_last_busy(host
->mmc
->parent
);
2746 return pm_runtime_put_autosuspend(host
->mmc
->parent
);
2749 static void sdhci_runtime_pm_bus_on(struct sdhci_host
*host
)
2753 host
->bus_on
= true;
2754 pm_runtime_get_noresume(host
->mmc
->parent
);
2757 static void sdhci_runtime_pm_bus_off(struct sdhci_host
*host
)
2761 host
->bus_on
= false;
2762 pm_runtime_put_noidle(host
->mmc
->parent
);
2765 int sdhci_runtime_suspend_host(struct sdhci_host
*host
)
2767 unsigned long flags
;
2769 mmc_retune_timer_stop(host
->mmc
);
2770 mmc_retune_needed(host
->mmc
);
2772 spin_lock_irqsave(&host
->lock
, flags
);
2773 host
->ier
&= SDHCI_INT_CARD_INT
;
2774 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
2775 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
2776 spin_unlock_irqrestore(&host
->lock
, flags
);
2778 synchronize_hardirq(host
->irq
);
2780 spin_lock_irqsave(&host
->lock
, flags
);
2781 host
->runtime_suspended
= true;
2782 spin_unlock_irqrestore(&host
->lock
, flags
);
2786 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host
);
2788 int sdhci_runtime_resume_host(struct sdhci_host
*host
)
2790 unsigned long flags
;
2791 int host_flags
= host
->flags
;
2793 if (host_flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2794 if (host
->ops
->enable_dma
)
2795 host
->ops
->enable_dma(host
);
2798 sdhci_init(host
, 0);
2800 /* Force clock and power re-program */
2803 sdhci_do_start_signal_voltage_switch(host
, &host
->mmc
->ios
);
2804 sdhci_do_set_ios(host
, &host
->mmc
->ios
);
2806 if ((host_flags
& SDHCI_PV_ENABLED
) &&
2807 !(host
->quirks2
& SDHCI_QUIRK2_PRESET_VALUE_BROKEN
)) {
2808 spin_lock_irqsave(&host
->lock
, flags
);
2809 sdhci_enable_preset_value(host
, true);
2810 spin_unlock_irqrestore(&host
->lock
, flags
);
2813 spin_lock_irqsave(&host
->lock
, flags
);
2815 host
->runtime_suspended
= false;
2817 /* Enable SDIO IRQ */
2818 if (host
->flags
& SDHCI_SDIO_IRQ_ENABLED
)
2819 sdhci_enable_sdio_irq_nolock(host
, true);
2821 /* Enable Card Detection */
2822 sdhci_enable_card_detection(host
);
2824 spin_unlock_irqrestore(&host
->lock
, flags
);
2828 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host
);
2830 #endif /* CONFIG_PM */
2832 /*****************************************************************************\
2834 * Device allocation/registration *
2836 \*****************************************************************************/
2838 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
2841 struct mmc_host
*mmc
;
2842 struct sdhci_host
*host
;
2844 WARN_ON(dev
== NULL
);
2846 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
2848 return ERR_PTR(-ENOMEM
);
2850 host
= mmc_priv(mmc
);
2852 host
->mmc_host_ops
= sdhci_ops
;
2853 mmc
->ops
= &host
->mmc_host_ops
;
2858 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
2860 int sdhci_add_host(struct sdhci_host
*host
)
2862 struct mmc_host
*mmc
;
2863 u32 caps
[2] = {0, 0};
2864 u32 max_current_caps
;
2865 unsigned int ocr_avail
;
2866 unsigned int override_timeout_clk
;
2870 WARN_ON(host
== NULL
);
2877 host
->quirks
= debug_quirks
;
2879 host
->quirks2
= debug_quirks2
;
2881 override_timeout_clk
= host
->timeout_clk
;
2883 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
2885 host
->version
= sdhci_readw(host
, SDHCI_HOST_VERSION
);
2886 host
->version
= (host
->version
& SDHCI_SPEC_VER_MASK
)
2887 >> SDHCI_SPEC_VER_SHIFT
;
2888 if (host
->version
> SDHCI_SPEC_300
) {
2889 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2890 mmc_hostname(mmc
), host
->version
);
2893 caps
[0] = (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
) ? host
->caps
:
2894 sdhci_readl(host
, SDHCI_CAPABILITIES
);
2896 if (host
->version
>= SDHCI_SPEC_300
)
2897 caps
[1] = (host
->quirks
& SDHCI_QUIRK_MISSING_CAPS
) ?
2899 sdhci_readl(host
, SDHCI_CAPABILITIES_1
);
2901 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
2902 host
->flags
|= SDHCI_USE_SDMA
;
2903 else if (!(caps
[0] & SDHCI_CAN_DO_SDMA
))
2904 DBG("Controller doesn't have SDMA capability\n");
2906 host
->flags
|= SDHCI_USE_SDMA
;
2908 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
2909 (host
->flags
& SDHCI_USE_SDMA
)) {
2910 DBG("Disabling DMA as it is marked broken\n");
2911 host
->flags
&= ~SDHCI_USE_SDMA
;
2914 if ((host
->version
>= SDHCI_SPEC_200
) &&
2915 (caps
[0] & SDHCI_CAN_DO_ADMA2
))
2916 host
->flags
|= SDHCI_USE_ADMA
;
2918 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
2919 (host
->flags
& SDHCI_USE_ADMA
)) {
2920 DBG("Disabling ADMA as it is marked broken\n");
2921 host
->flags
&= ~SDHCI_USE_ADMA
;
2925 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2926 * and *must* do 64-bit DMA. A driver has the opportunity to change
2927 * that during the first call to ->enable_dma(). Similarly
2928 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2931 if (sdhci_readl(host
, SDHCI_CAPABILITIES
) & SDHCI_CAN_64BIT
)
2932 host
->flags
|= SDHCI_USE_64_BIT_DMA
;
2934 if (host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
)) {
2935 if (host
->ops
->enable_dma
) {
2936 if (host
->ops
->enable_dma(host
)) {
2937 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2940 ~(SDHCI_USE_SDMA
| SDHCI_USE_ADMA
);
2945 /* SDMA does not support 64-bit DMA */
2946 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
2947 host
->flags
&= ~SDHCI_USE_SDMA
;
2949 if (host
->flags
& SDHCI_USE_ADMA
) {
2951 * The DMA descriptor table size is calculated as the maximum
2952 * number of segments times 2, to allow for an alignment
2953 * descriptor for each segment, plus 1 for a nop end descriptor,
2954 * all multipled by the descriptor size.
2956 if (host
->flags
& SDHCI_USE_64_BIT_DMA
) {
2957 host
->adma_table_sz
= (SDHCI_MAX_SEGS
* 2 + 1) *
2958 SDHCI_ADMA2_64_DESC_SZ
;
2959 host
->desc_sz
= SDHCI_ADMA2_64_DESC_SZ
;
2961 host
->adma_table_sz
= (SDHCI_MAX_SEGS
* 2 + 1) *
2962 SDHCI_ADMA2_32_DESC_SZ
;
2963 host
->desc_sz
= SDHCI_ADMA2_32_DESC_SZ
;
2965 host
->adma_table
= dma_alloc_coherent(mmc_dev(mmc
),
2966 host
->adma_table_sz
,
2969 host
->align_buffer_sz
= SDHCI_MAX_SEGS
* SDHCI_ADMA2_ALIGN
;
2970 host
->align_buffer
= kmalloc(host
->align_buffer_sz
, GFP_KERNEL
);
2971 if (!host
->adma_table
|| !host
->align_buffer
) {
2972 if (host
->adma_table
)
2973 dma_free_coherent(mmc_dev(mmc
),
2974 host
->adma_table_sz
,
2977 kfree(host
->align_buffer
);
2978 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2980 host
->flags
&= ~SDHCI_USE_ADMA
;
2981 host
->adma_table
= NULL
;
2982 host
->align_buffer
= NULL
;
2983 } else if (host
->adma_addr
& (SDHCI_ADMA2_DESC_ALIGN
- 1)) {
2984 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2986 host
->flags
&= ~SDHCI_USE_ADMA
;
2987 dma_free_coherent(mmc_dev(mmc
), host
->adma_table_sz
,
2988 host
->adma_table
, host
->adma_addr
);
2989 kfree(host
->align_buffer
);
2990 host
->adma_table
= NULL
;
2991 host
->align_buffer
= NULL
;
2996 * If we use DMA, then it's up to the caller to set the DMA
2997 * mask, but PIO does not need the hw shim so we set a new
2998 * mask here in that case.
3000 if (!(host
->flags
& (SDHCI_USE_SDMA
| SDHCI_USE_ADMA
))) {
3001 host
->dma_mask
= DMA_BIT_MASK(64);
3002 mmc_dev(mmc
)->dma_mask
= &host
->dma_mask
;
3005 if (host
->version
>= SDHCI_SPEC_300
)
3006 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_V3_BASE_MASK
)
3007 >> SDHCI_CLOCK_BASE_SHIFT
;
3009 host
->max_clk
= (caps
[0] & SDHCI_CLOCK_BASE_MASK
)
3010 >> SDHCI_CLOCK_BASE_SHIFT
;
3012 host
->max_clk
*= 1000000;
3013 if (host
->max_clk
== 0 || host
->quirks
&
3014 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
) {
3015 if (!host
->ops
->get_max_clock
) {
3016 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3020 host
->max_clk
= host
->ops
->get_max_clock(host
);
3024 * In case of Host Controller v3.00, find out whether clock
3025 * multiplier is supported.
3027 host
->clk_mul
= (caps
[1] & SDHCI_CLOCK_MUL_MASK
) >>
3028 SDHCI_CLOCK_MUL_SHIFT
;
3031 * In case the value in Clock Multiplier is 0, then programmable
3032 * clock mode is not supported, otherwise the actual clock
3033 * multiplier is one more than the value of Clock Multiplier
3034 * in the Capabilities Register.
3040 * Set host parameters.
3042 max_clk
= host
->max_clk
;
3044 if (host
->ops
->get_min_clock
)
3045 mmc
->f_min
= host
->ops
->get_min_clock(host
);
3046 else if (host
->version
>= SDHCI_SPEC_300
) {
3047 if (host
->clk_mul
) {
3048 mmc
->f_min
= (host
->max_clk
* host
->clk_mul
) / 1024;
3049 max_clk
= host
->max_clk
* host
->clk_mul
;
3051 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_300
;
3053 mmc
->f_min
= host
->max_clk
/ SDHCI_MAX_DIV_SPEC_200
;
3055 if (!mmc
->f_max
|| (mmc
->f_max
&& (mmc
->f_max
> max_clk
)))
3056 mmc
->f_max
= max_clk
;
3058 if (!(host
->quirks
& SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
)) {
3059 host
->timeout_clk
= (caps
[0] & SDHCI_TIMEOUT_CLK_MASK
) >>
3060 SDHCI_TIMEOUT_CLK_SHIFT
;
3061 if (host
->timeout_clk
== 0) {
3062 if (host
->ops
->get_timeout_clock
) {
3064 host
->ops
->get_timeout_clock(host
);
3066 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3072 if (caps
[0] & SDHCI_TIMEOUT_CLK_UNIT
)
3073 host
->timeout_clk
*= 1000;
3075 mmc
->max_busy_timeout
= host
->ops
->get_max_timeout_count
?
3076 host
->ops
->get_max_timeout_count(host
) : 1 << 27;
3077 mmc
->max_busy_timeout
/= host
->timeout_clk
;
3080 if (override_timeout_clk
)
3081 host
->timeout_clk
= override_timeout_clk
;
3083 mmc
->caps
|= MMC_CAP_SDIO_IRQ
| MMC_CAP_ERASE
| MMC_CAP_CMD23
;
3084 mmc
->caps2
|= MMC_CAP2_SDIO_IRQ_NOTHREAD
;
3086 if (host
->quirks
& SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
)
3087 host
->flags
|= SDHCI_AUTO_CMD12
;
3089 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3090 if ((host
->version
>= SDHCI_SPEC_300
) &&
3091 ((host
->flags
& SDHCI_USE_ADMA
) ||
3092 !(host
->flags
& SDHCI_USE_SDMA
)) &&
3093 !(host
->quirks2
& SDHCI_QUIRK2_ACMD23_BROKEN
)) {
3094 host
->flags
|= SDHCI_AUTO_CMD23
;
3095 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc
));
3097 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc
));
3101 * A controller may support 8-bit width, but the board itself
3102 * might not have the pins brought out. Boards that support
3103 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3104 * their platform code before calling sdhci_add_host(), and we
3105 * won't assume 8-bit width for hosts without that CAP.
3107 if (!(host
->quirks
& SDHCI_QUIRK_FORCE_1_BIT_DATA
))
3108 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
3110 if (host
->quirks2
& SDHCI_QUIRK2_HOST_NO_CMD23
)
3111 mmc
->caps
&= ~MMC_CAP_CMD23
;
3113 if (caps
[0] & SDHCI_CAN_DO_HISPD
)
3114 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
;
3116 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_CARD_DETECTION
) &&
3117 !(mmc
->caps
& MMC_CAP_NONREMOVABLE
) &&
3118 IS_ERR_VALUE(mmc_gpio_get_cd(host
->mmc
)))
3119 mmc
->caps
|= MMC_CAP_NEEDS_POLL
;
3121 /* If there are external regulators, get them */
3122 if (mmc_regulator_get_supply(mmc
) == -EPROBE_DEFER
)
3123 return -EPROBE_DEFER
;
3125 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3126 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
3127 ret
= regulator_enable(mmc
->supply
.vqmmc
);
3128 if (!regulator_is_supported_voltage(mmc
->supply
.vqmmc
, 1700000,
3130 caps
[1] &= ~(SDHCI_SUPPORT_SDR104
|
3131 SDHCI_SUPPORT_SDR50
|
3132 SDHCI_SUPPORT_DDR50
);
3134 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3135 mmc_hostname(mmc
), ret
);
3136 mmc
->supply
.vqmmc
= ERR_PTR(-EINVAL
);
3140 if (host
->quirks2
& SDHCI_QUIRK2_NO_1_8_V
)
3141 caps
[1] &= ~(SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3142 SDHCI_SUPPORT_DDR50
);
3144 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3145 if (caps
[1] & (SDHCI_SUPPORT_SDR104
| SDHCI_SUPPORT_SDR50
|
3146 SDHCI_SUPPORT_DDR50
))
3147 mmc
->caps
|= MMC_CAP_UHS_SDR12
| MMC_CAP_UHS_SDR25
;
3149 /* SDR104 supports also implies SDR50 support */
3150 if (caps
[1] & SDHCI_SUPPORT_SDR104
) {
3151 mmc
->caps
|= MMC_CAP_UHS_SDR104
| MMC_CAP_UHS_SDR50
;
3152 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3153 * field can be promoted to support HS200.
3155 if (!(host
->quirks2
& SDHCI_QUIRK2_BROKEN_HS200
))
3156 mmc
->caps2
|= MMC_CAP2_HS200
;
3157 } else if (caps
[1] & SDHCI_SUPPORT_SDR50
)
3158 mmc
->caps
|= MMC_CAP_UHS_SDR50
;
3160 if (host
->quirks2
& SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400
&&
3161 (caps
[1] & SDHCI_SUPPORT_HS400
))
3162 mmc
->caps2
|= MMC_CAP2_HS400
;
3164 if ((mmc
->caps2
& MMC_CAP2_HSX00_1_2V
) &&
3165 (IS_ERR(mmc
->supply
.vqmmc
) ||
3166 !regulator_is_supported_voltage(mmc
->supply
.vqmmc
, 1100000,
3168 mmc
->caps2
&= ~MMC_CAP2_HSX00_1_2V
;
3170 if ((caps
[1] & SDHCI_SUPPORT_DDR50
) &&
3171 !(host
->quirks2
& SDHCI_QUIRK2_BROKEN_DDR50
))
3172 mmc
->caps
|= MMC_CAP_UHS_DDR50
;
3174 /* Does the host need tuning for SDR50? */
3175 if (caps
[1] & SDHCI_USE_SDR50_TUNING
)
3176 host
->flags
|= SDHCI_SDR50_NEEDS_TUNING
;
3178 /* Does the host need tuning for SDR104 / HS200? */
3179 if (mmc
->caps2
& MMC_CAP2_HS200
)
3180 host
->flags
|= SDHCI_SDR104_NEEDS_TUNING
;
3182 /* Driver Type(s) (A, C, D) supported by the host */
3183 if (caps
[1] & SDHCI_DRIVER_TYPE_A
)
3184 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_A
;
3185 if (caps
[1] & SDHCI_DRIVER_TYPE_C
)
3186 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_C
;
3187 if (caps
[1] & SDHCI_DRIVER_TYPE_D
)
3188 mmc
->caps
|= MMC_CAP_DRIVER_TYPE_D
;
3190 /* Initial value for re-tuning timer count */
3191 host
->tuning_count
= (caps
[1] & SDHCI_RETUNING_TIMER_COUNT_MASK
) >>
3192 SDHCI_RETUNING_TIMER_COUNT_SHIFT
;
3195 * In case Re-tuning Timer is not disabled, the actual value of
3196 * re-tuning timer will be 2 ^ (n - 1).
3198 if (host
->tuning_count
)
3199 host
->tuning_count
= 1 << (host
->tuning_count
- 1);
3201 /* Re-tuning mode supported by the Host Controller */
3202 host
->tuning_mode
= (caps
[1] & SDHCI_RETUNING_MODE_MASK
) >>
3203 SDHCI_RETUNING_MODE_SHIFT
;
3208 * According to SD Host Controller spec v3.00, if the Host System
3209 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3210 * the value is meaningful only if Voltage Support in the Capabilities
3211 * register is set. The actual current value is 4 times the register
3214 max_current_caps
= sdhci_readl(host
, SDHCI_MAX_CURRENT
);
3215 if (!max_current_caps
&& !IS_ERR(mmc
->supply
.vmmc
)) {
3216 int curr
= regulator_get_current_limit(mmc
->supply
.vmmc
);
3219 /* convert to SDHCI_MAX_CURRENT format */
3220 curr
= curr
/1000; /* convert to mA */
3221 curr
= curr
/SDHCI_MAX_CURRENT_MULTIPLIER
;
3223 curr
= min_t(u32
, curr
, SDHCI_MAX_CURRENT_LIMIT
);
3225 (curr
<< SDHCI_MAX_CURRENT_330_SHIFT
) |
3226 (curr
<< SDHCI_MAX_CURRENT_300_SHIFT
) |
3227 (curr
<< SDHCI_MAX_CURRENT_180_SHIFT
);
3231 if (caps
[0] & SDHCI_CAN_VDD_330
) {
3232 ocr_avail
|= MMC_VDD_32_33
| MMC_VDD_33_34
;
3234 mmc
->max_current_330
= ((max_current_caps
&
3235 SDHCI_MAX_CURRENT_330_MASK
) >>
3236 SDHCI_MAX_CURRENT_330_SHIFT
) *
3237 SDHCI_MAX_CURRENT_MULTIPLIER
;
3239 if (caps
[0] & SDHCI_CAN_VDD_300
) {
3240 ocr_avail
|= MMC_VDD_29_30
| MMC_VDD_30_31
;
3242 mmc
->max_current_300
= ((max_current_caps
&
3243 SDHCI_MAX_CURRENT_300_MASK
) >>
3244 SDHCI_MAX_CURRENT_300_SHIFT
) *
3245 SDHCI_MAX_CURRENT_MULTIPLIER
;
3247 if (caps
[0] & SDHCI_CAN_VDD_180
) {
3248 ocr_avail
|= MMC_VDD_165_195
;
3250 mmc
->max_current_180
= ((max_current_caps
&
3251 SDHCI_MAX_CURRENT_180_MASK
) >>
3252 SDHCI_MAX_CURRENT_180_SHIFT
) *
3253 SDHCI_MAX_CURRENT_MULTIPLIER
;
3256 /* If OCR set by host, use it instead. */
3258 ocr_avail
= host
->ocr_mask
;
3260 /* If OCR set by external regulators, give it highest prio. */
3262 ocr_avail
= mmc
->ocr_avail
;
3264 mmc
->ocr_avail
= ocr_avail
;
3265 mmc
->ocr_avail_sdio
= ocr_avail
;
3266 if (host
->ocr_avail_sdio
)
3267 mmc
->ocr_avail_sdio
&= host
->ocr_avail_sdio
;
3268 mmc
->ocr_avail_sd
= ocr_avail
;
3269 if (host
->ocr_avail_sd
)
3270 mmc
->ocr_avail_sd
&= host
->ocr_avail_sd
;
3271 else /* normal SD controllers don't support 1.8V */
3272 mmc
->ocr_avail_sd
&= ~MMC_VDD_165_195
;
3273 mmc
->ocr_avail_mmc
= ocr_avail
;
3274 if (host
->ocr_avail_mmc
)
3275 mmc
->ocr_avail_mmc
&= host
->ocr_avail_mmc
;
3277 if (mmc
->ocr_avail
== 0) {
3278 pr_err("%s: Hardware doesn't report any support voltages.\n",
3283 spin_lock_init(&host
->lock
);
3286 * Maximum number of segments. Depends on if the hardware
3287 * can do scatter/gather or not.
3289 if (host
->flags
& SDHCI_USE_ADMA
)
3290 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3291 else if (host
->flags
& SDHCI_USE_SDMA
)
3294 mmc
->max_segs
= SDHCI_MAX_SEGS
;
3297 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3298 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3301 mmc
->max_req_size
= 524288;
3304 * Maximum segment size. Could be one segment with the maximum number
3305 * of bytes. When doing hardware scatter/gather, each entry cannot
3306 * be larger than 64 KiB though.
3308 if (host
->flags
& SDHCI_USE_ADMA
) {
3309 if (host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
)
3310 mmc
->max_seg_size
= 65535;
3312 mmc
->max_seg_size
= 65536;
3314 mmc
->max_seg_size
= mmc
->max_req_size
;
3318 * Maximum block size. This varies from controller to controller and
3319 * is specified in the capabilities register.
3321 if (host
->quirks
& SDHCI_QUIRK_FORCE_BLK_SZ_2048
) {
3322 mmc
->max_blk_size
= 2;
3324 mmc
->max_blk_size
= (caps
[0] & SDHCI_MAX_BLOCK_MASK
) >>
3325 SDHCI_MAX_BLOCK_SHIFT
;
3326 if (mmc
->max_blk_size
>= 3) {
3327 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3329 mmc
->max_blk_size
= 0;
3333 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
3336 * Maximum block count.
3338 mmc
->max_blk_count
= (host
->quirks
& SDHCI_QUIRK_NO_MULTIBLOCK
) ? 1 : 65535;
3343 tasklet_init(&host
->finish_tasklet
,
3344 sdhci_tasklet_finish
, (unsigned long)host
);
3346 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
3348 init_waitqueue_head(&host
->buf_ready_int
);
3350 sdhci_init(host
, 0);
3352 ret
= request_threaded_irq(host
->irq
, sdhci_irq
, sdhci_thread_irq
,
3353 IRQF_SHARED
, mmc_hostname(mmc
), host
);
3355 pr_err("%s: Failed to request IRQ %d: %d\n",
3356 mmc_hostname(mmc
), host
->irq
, ret
);
3360 #ifdef CONFIG_MMC_DEBUG
3361 sdhci_dumpregs(host
);
3364 #ifdef SDHCI_USE_LEDS_CLASS
3365 snprintf(host
->led_name
, sizeof(host
->led_name
),
3366 "%s::", mmc_hostname(mmc
));
3367 host
->led
.name
= host
->led_name
;
3368 host
->led
.brightness
= LED_OFF
;
3369 host
->led
.default_trigger
= mmc_hostname(mmc
);
3370 host
->led
.brightness_set
= sdhci_led_control
;
3372 ret
= led_classdev_register(mmc_dev(mmc
), &host
->led
);
3374 pr_err("%s: Failed to register LED device: %d\n",
3375 mmc_hostname(mmc
), ret
);
3384 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3385 mmc_hostname(mmc
), host
->hw_name
, dev_name(mmc_dev(mmc
)),
3386 (host
->flags
& SDHCI_USE_ADMA
) ?
3387 (host
->flags
& SDHCI_USE_64_BIT_DMA
) ? "ADMA 64-bit" : "ADMA" :
3388 (host
->flags
& SDHCI_USE_SDMA
) ? "DMA" : "PIO");
3390 sdhci_enable_card_detection(host
);
3394 #ifdef SDHCI_USE_LEDS_CLASS
3396 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3397 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3398 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3399 free_irq(host
->irq
, host
);
3402 tasklet_kill(&host
->finish_tasklet
);
3407 EXPORT_SYMBOL_GPL(sdhci_add_host
);
3409 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
3411 struct mmc_host
*mmc
= host
->mmc
;
3412 unsigned long flags
;
3415 spin_lock_irqsave(&host
->lock
, flags
);
3417 host
->flags
|= SDHCI_DEVICE_DEAD
;
3420 pr_err("%s: Controller removed during "
3421 " transfer!\n", mmc_hostname(mmc
));
3423 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
3424 tasklet_schedule(&host
->finish_tasklet
);
3427 spin_unlock_irqrestore(&host
->lock
, flags
);
3430 sdhci_disable_card_detection(host
);
3432 mmc_remove_host(mmc
);
3434 #ifdef SDHCI_USE_LEDS_CLASS
3435 led_classdev_unregister(&host
->led
);
3439 sdhci_do_reset(host
, SDHCI_RESET_ALL
);
3441 sdhci_writel(host
, 0, SDHCI_INT_ENABLE
);
3442 sdhci_writel(host
, 0, SDHCI_SIGNAL_ENABLE
);
3443 free_irq(host
->irq
, host
);
3445 del_timer_sync(&host
->timer
);
3447 tasklet_kill(&host
->finish_tasklet
);
3449 if (!IS_ERR(mmc
->supply
.vqmmc
))
3450 regulator_disable(mmc
->supply
.vqmmc
);
3452 if (host
->adma_table
)
3453 dma_free_coherent(mmc_dev(mmc
), host
->adma_table_sz
,
3454 host
->adma_table
, host
->adma_addr
);
3455 kfree(host
->align_buffer
);
3457 host
->adma_table
= NULL
;
3458 host
->align_buffer
= NULL
;
3461 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
3463 void sdhci_free_host(struct sdhci_host
*host
)
3465 mmc_free_host(host
->mmc
);
3468 EXPORT_SYMBOL_GPL(sdhci_free_host
);
3470 /*****************************************************************************\
3472 * Driver init/exit *
3474 \*****************************************************************************/
3476 static int __init
sdhci_drv_init(void)
3479 ": Secure Digital Host Controller Interface driver\n");
3480 pr_info(DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
3485 static void __exit
sdhci_drv_exit(void)
3489 module_init(sdhci_drv_init
);
3490 module_exit(sdhci_drv_exit
);
3492 module_param(debug_quirks
, uint
, 0444);
3493 module_param(debug_quirks2
, uint
, 0444);
3495 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3496 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3497 MODULE_LICENSE("GPL");
3499 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");
3500 MODULE_PARM_DESC(debug_quirks2
, "Force certain other quirks.");