2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/interrupt.h>
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/wait.h>
23 #include <linux/mutex.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/module.h>
26 #include <linux/slab.h>
30 MODULE_LICENSE("GPL");
32 #define DENALI_NAND_NAME "denali-nand"
34 /* Host Data/Command Interface */
35 #define DENALI_HOST_ADDR 0x00
36 #define DENALI_HOST_DATA 0x10
38 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
39 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
40 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
41 #define DENALI_MAP11 (3 << 26) /* direct controller access */
43 /* MAP11 access cycle type */
44 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
45 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
46 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
49 #define DENALI_ERASE 0x01
51 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
53 #define DENALI_INVALID_BANK -1
54 #define DENALI_NR_BANKS 4
57 * The bus interface clock, clk_x, is phase aligned with the core clock. The
58 * clk_x is an integral multiple N of the core clk. The value N is configured
59 * at IP delivery time, and its available value is 4, 5, or 6. We need to align
60 * to the largest value to make it work with any possible configuration.
62 #define DENALI_CLK_X_MULT 6
65 * this macro allows us to convert from an MTD structure to our own
66 * device context (denali) structure.
68 static inline struct denali_nand_info
*mtd_to_denali(struct mtd_info
*mtd
)
70 return container_of(mtd_to_nand(mtd
), struct denali_nand_info
, nand
);
73 static void denali_host_write(struct denali_nand_info
*denali
,
74 uint32_t addr
, uint32_t data
)
76 iowrite32(addr
, denali
->host
+ DENALI_HOST_ADDR
);
77 iowrite32(data
, denali
->host
+ DENALI_HOST_DATA
);
81 * Use the configuration feature register to determine the maximum number of
82 * banks that the hardware supports.
84 static void detect_max_banks(struct denali_nand_info
*denali
)
86 uint32_t features
= ioread32(denali
->reg
+ FEATURES
);
88 denali
->max_banks
= 1 << (features
& FEATURES__N_BANKS
);
90 /* the encoding changed from rev 5.0 to 5.1 */
91 if (denali
->revision
< 0x0501)
92 denali
->max_banks
<<= 1;
95 static void denali_enable_irq(struct denali_nand_info
*denali
)
99 for (i
= 0; i
< DENALI_NR_BANKS
; i
++)
100 iowrite32(U32_MAX
, denali
->reg
+ INTR_EN(i
));
101 iowrite32(GLOBAL_INT_EN_FLAG
, denali
->reg
+ GLOBAL_INT_ENABLE
);
104 static void denali_disable_irq(struct denali_nand_info
*denali
)
108 for (i
= 0; i
< DENALI_NR_BANKS
; i
++)
109 iowrite32(0, denali
->reg
+ INTR_EN(i
));
110 iowrite32(0, denali
->reg
+ GLOBAL_INT_ENABLE
);
113 static void denali_clear_irq(struct denali_nand_info
*denali
,
114 int bank
, uint32_t irq_status
)
116 /* write one to clear bits */
117 iowrite32(irq_status
, denali
->reg
+ INTR_STATUS(bank
));
120 static void denali_clear_irq_all(struct denali_nand_info
*denali
)
124 for (i
= 0; i
< DENALI_NR_BANKS
; i
++)
125 denali_clear_irq(denali
, i
, U32_MAX
);
128 static irqreturn_t
denali_isr(int irq
, void *dev_id
)
130 struct denali_nand_info
*denali
= dev_id
;
131 irqreturn_t ret
= IRQ_NONE
;
135 spin_lock(&denali
->irq_lock
);
137 for (i
= 0; i
< DENALI_NR_BANKS
; i
++) {
138 irq_status
= ioread32(denali
->reg
+ INTR_STATUS(i
));
142 denali_clear_irq(denali
, i
, irq_status
);
144 if (i
!= denali
->active_bank
)
147 denali
->irq_status
|= irq_status
;
149 if (denali
->irq_status
& denali
->irq_mask
)
150 complete(&denali
->complete
);
153 spin_unlock(&denali
->irq_lock
);
158 static void denali_reset_irq(struct denali_nand_info
*denali
)
162 spin_lock_irqsave(&denali
->irq_lock
, flags
);
163 denali
->irq_status
= 0;
164 denali
->irq_mask
= 0;
165 spin_unlock_irqrestore(&denali
->irq_lock
, flags
);
168 static uint32_t denali_wait_for_irq(struct denali_nand_info
*denali
,
171 unsigned long time_left
, flags
;
174 spin_lock_irqsave(&denali
->irq_lock
, flags
);
176 irq_status
= denali
->irq_status
;
178 if (irq_mask
& irq_status
) {
179 /* return immediately if the IRQ has already happened. */
180 spin_unlock_irqrestore(&denali
->irq_lock
, flags
);
184 denali
->irq_mask
= irq_mask
;
185 reinit_completion(&denali
->complete
);
186 spin_unlock_irqrestore(&denali
->irq_lock
, flags
);
188 time_left
= wait_for_completion_timeout(&denali
->complete
,
189 msecs_to_jiffies(1000));
191 dev_err(denali
->dev
, "timeout while waiting for irq 0x%x\n",
196 return denali
->irq_status
;
199 static uint32_t denali_check_irq(struct denali_nand_info
*denali
)
204 spin_lock_irqsave(&denali
->irq_lock
, flags
);
205 irq_status
= denali
->irq_status
;
206 spin_unlock_irqrestore(&denali
->irq_lock
, flags
);
212 * This helper function setups the registers for ECC and whether or not
213 * the spare area will be transferred.
215 static void setup_ecc_for_xfer(struct denali_nand_info
*denali
, bool ecc_en
,
218 int ecc_en_flag
, transfer_spare_flag
;
220 /* set ECC, transfer spare bits if needed */
221 ecc_en_flag
= ecc_en
? ECC_ENABLE__FLAG
: 0;
222 transfer_spare_flag
= transfer_spare
? TRANSFER_SPARE_REG__FLAG
: 0;
224 /* Enable spare area/ECC per user's request. */
225 iowrite32(ecc_en_flag
, denali
->reg
+ ECC_ENABLE
);
226 iowrite32(transfer_spare_flag
, denali
->reg
+ TRANSFER_SPARE_REG
);
229 static void denali_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
231 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
234 iowrite32(DENALI_MAP11_DATA
| DENALI_BANK(denali
),
235 denali
->host
+ DENALI_HOST_ADDR
);
237 for (i
= 0; i
< len
; i
++)
238 buf
[i
] = ioread32(denali
->host
+ DENALI_HOST_DATA
);
241 static void denali_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
243 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
246 iowrite32(DENALI_MAP11_DATA
| DENALI_BANK(denali
),
247 denali
->host
+ DENALI_HOST_ADDR
);
249 for (i
= 0; i
< len
; i
++)
250 iowrite32(buf
[i
], denali
->host
+ DENALI_HOST_DATA
);
253 static void denali_read_buf16(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
255 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
256 uint16_t *buf16
= (uint16_t *)buf
;
259 iowrite32(DENALI_MAP11_DATA
| DENALI_BANK(denali
),
260 denali
->host
+ DENALI_HOST_ADDR
);
262 for (i
= 0; i
< len
/ 2; i
++)
263 buf16
[i
] = ioread32(denali
->host
+ DENALI_HOST_DATA
);
266 static void denali_write_buf16(struct mtd_info
*mtd
, const uint8_t *buf
,
269 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
270 const uint16_t *buf16
= (const uint16_t *)buf
;
273 iowrite32(DENALI_MAP11_DATA
| DENALI_BANK(denali
),
274 denali
->host
+ DENALI_HOST_ADDR
);
276 for (i
= 0; i
< len
/ 2; i
++)
277 iowrite32(buf16
[i
], denali
->host
+ DENALI_HOST_DATA
);
280 static uint8_t denali_read_byte(struct mtd_info
*mtd
)
284 denali_read_buf(mtd
, &byte
, 1);
289 static void denali_write_byte(struct mtd_info
*mtd
, uint8_t byte
)
291 denali_write_buf(mtd
, &byte
, 1);
294 static uint16_t denali_read_word(struct mtd_info
*mtd
)
298 denali_read_buf16(mtd
, (uint8_t *)&word
, 2);
303 static void denali_cmd_ctrl(struct mtd_info
*mtd
, int dat
, unsigned int ctrl
)
305 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
309 type
= DENALI_MAP11_CMD
;
310 else if (ctrl
& NAND_ALE
)
311 type
= DENALI_MAP11_ADDR
;
316 * Some commands are followed by chip->dev_ready or chip->waitfunc.
317 * irq_status must be cleared here to catch the R/B# interrupt later.
319 if (ctrl
& NAND_CTRL_CHANGE
)
320 denali_reset_irq(denali
);
322 denali_host_write(denali
, DENALI_BANK(denali
) | type
, dat
);
325 static int denali_dev_ready(struct mtd_info
*mtd
)
327 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
329 return !!(denali_check_irq(denali
) & INTR__INT_ACT
);
332 static int denali_check_erased_page(struct mtd_info
*mtd
,
333 struct nand_chip
*chip
, uint8_t *buf
,
334 unsigned long uncor_ecc_flags
,
335 unsigned int max_bitflips
)
337 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
338 int ecc_steps
= chip
->ecc
.steps
;
339 int ecc_size
= chip
->ecc
.size
;
340 int ecc_bytes
= chip
->ecc
.bytes
;
343 ret
= mtd_ooblayout_get_eccbytes(mtd
, ecc_code
, chip
->oob_poi
, 0,
348 for (i
= 0; i
< ecc_steps
; i
++) {
349 if (!(uncor_ecc_flags
& BIT(i
)))
352 stat
= nand_check_erased_ecc_chunk(buf
, ecc_size
,
357 mtd
->ecc_stats
.failed
++;
359 mtd
->ecc_stats
.corrected
+= stat
;
360 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
364 ecc_code
+= ecc_bytes
;
370 static int denali_hw_ecc_fixup(struct mtd_info
*mtd
,
371 struct denali_nand_info
*denali
,
372 unsigned long *uncor_ecc_flags
)
374 struct nand_chip
*chip
= mtd_to_nand(mtd
);
375 int bank
= denali
->active_bank
;
377 unsigned int max_bitflips
;
379 ecc_cor
= ioread32(denali
->reg
+ ECC_COR_INFO(bank
));
380 ecc_cor
>>= ECC_COR_INFO__SHIFT(bank
);
382 if (ecc_cor
& ECC_COR_INFO__UNCOR_ERR
) {
384 * This flag is set when uncorrectable error occurs at least in
385 * one ECC sector. We can not know "how many sectors", or
386 * "which sector(s)". We need erase-page check for all sectors.
388 *uncor_ecc_flags
= GENMASK(chip
->ecc
.steps
- 1, 0);
392 max_bitflips
= ecc_cor
& ECC_COR_INFO__MAX_ERRORS
;
395 * The register holds the maximum of per-sector corrected bitflips.
396 * This is suitable for the return value of the ->read_page() callback.
397 * Unfortunately, we can not know the total number of corrected bits in
398 * the page. Increase the stats by max_bitflips. (compromised solution)
400 mtd
->ecc_stats
.corrected
+= max_bitflips
;
405 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
406 #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
407 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
408 #define ECC_ERROR_UNCORRECTABLE(x) ((x) & ERR_CORRECTION_INFO__ERROR_TYPE)
409 #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
410 #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
412 static int denali_sw_ecc_fixup(struct mtd_info
*mtd
,
413 struct denali_nand_info
*denali
,
414 unsigned long *uncor_ecc_flags
, uint8_t *buf
)
416 unsigned int ecc_size
= denali
->nand
.ecc
.size
;
417 unsigned int bitflips
= 0;
418 unsigned int max_bitflips
= 0;
419 uint32_t err_addr
, err_cor_info
;
420 unsigned int err_byte
, err_sector
, err_device
;
421 uint8_t err_cor_value
;
422 unsigned int prev_sector
= 0;
425 denali_reset_irq(denali
);
428 err_addr
= ioread32(denali
->reg
+ ECC_ERROR_ADDRESS
);
429 err_sector
= ECC_SECTOR(err_addr
);
430 err_byte
= ECC_BYTE(err_addr
);
432 err_cor_info
= ioread32(denali
->reg
+ ERR_CORRECTION_INFO
);
433 err_cor_value
= ECC_CORRECTION_VALUE(err_cor_info
);
434 err_device
= ECC_ERR_DEVICE(err_cor_info
);
436 /* reset the bitflip counter when crossing ECC sector */
437 if (err_sector
!= prev_sector
)
440 if (ECC_ERROR_UNCORRECTABLE(err_cor_info
)) {
442 * Check later if this is a real ECC error, or
445 *uncor_ecc_flags
|= BIT(err_sector
);
446 } else if (err_byte
< ecc_size
) {
448 * If err_byte is larger than ecc_size, means error
449 * happened in OOB, so we ignore it. It's no need for
450 * us to correct it err_device is represented the NAND
451 * error bits are happened in if there are more than
452 * one NAND connected.
455 unsigned int flips_in_byte
;
457 offset
= (err_sector
* ecc_size
+ err_byte
) *
458 denali
->devs_per_cs
+ err_device
;
460 /* correct the ECC error */
461 flips_in_byte
= hweight8(buf
[offset
] ^ err_cor_value
);
462 buf
[offset
] ^= err_cor_value
;
463 mtd
->ecc_stats
.corrected
+= flips_in_byte
;
464 bitflips
+= flips_in_byte
;
466 max_bitflips
= max(max_bitflips
, bitflips
);
469 prev_sector
= err_sector
;
470 } while (!ECC_LAST_ERR(err_cor_info
));
473 * Once handle all ecc errors, controller will trigger a
474 * ECC_TRANSACTION_DONE interrupt, so here just wait for
475 * a while for this interrupt
477 irq_status
= denali_wait_for_irq(denali
, INTR__ECC_TRANSACTION_DONE
);
478 if (!(irq_status
& INTR__ECC_TRANSACTION_DONE
))
484 /* programs the controller to either enable/disable DMA transfers */
485 static void denali_enable_dma(struct denali_nand_info
*denali
, bool en
)
487 iowrite32(en
? DMA_ENABLE__FLAG
: 0, denali
->reg
+ DMA_ENABLE
);
488 ioread32(denali
->reg
+ DMA_ENABLE
);
491 static void denali_setup_dma64(struct denali_nand_info
*denali
,
492 dma_addr_t dma_addr
, int page
, int write
)
495 const int page_count
= 1;
497 mode
= DENALI_MAP10
| DENALI_BANK(denali
) | page
;
499 /* DMA is a three step process */
502 * 1. setup transfer type, interrupt when complete,
503 * burst len = 64 bytes, the number of pages
505 denali_host_write(denali
, mode
,
506 0x01002000 | (64 << 16) | (write
<< 8) | page_count
);
508 /* 2. set memory low address */
509 denali_host_write(denali
, mode
, dma_addr
);
511 /* 3. set memory high address */
512 denali_host_write(denali
, mode
, (uint64_t)dma_addr
>> 32);
515 static void denali_setup_dma32(struct denali_nand_info
*denali
,
516 dma_addr_t dma_addr
, int page
, int write
)
519 const int page_count
= 1;
521 mode
= DENALI_MAP10
| DENALI_BANK(denali
);
523 /* DMA is a four step process */
525 /* 1. setup transfer type and # of pages */
526 denali_host_write(denali
, mode
| page
,
527 0x2000 | (write
<< 8) | page_count
);
529 /* 2. set memory high address bits 23:8 */
530 denali_host_write(denali
, mode
| ((dma_addr
>> 16) << 8), 0x2200);
532 /* 3. set memory low address bits 23:8 */
533 denali_host_write(denali
, mode
| ((dma_addr
& 0xffff) << 8), 0x2300);
535 /* 4. interrupt when complete, burst len = 64 bytes */
536 denali_host_write(denali
, mode
| 0x14000, 0x2400);
539 static void denali_setup_dma(struct denali_nand_info
*denali
,
540 dma_addr_t dma_addr
, int page
, int write
)
542 if (denali
->caps
& DENALI_CAP_DMA_64BIT
)
543 denali_setup_dma64(denali
, dma_addr
, page
, write
);
545 denali_setup_dma32(denali
, dma_addr
, page
, write
);
548 static int denali_pio_read(struct denali_nand_info
*denali
, void *buf
,
549 size_t size
, int page
, int raw
)
551 uint32_t addr
= DENALI_BANK(denali
) | page
;
552 uint32_t *buf32
= (uint32_t *)buf
;
553 uint32_t irq_status
, ecc_err_mask
;
556 if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
)
557 ecc_err_mask
= INTR__ECC_UNCOR_ERR
;
559 ecc_err_mask
= INTR__ECC_ERR
;
561 denali_reset_irq(denali
);
563 iowrite32(DENALI_MAP01
| addr
, denali
->host
+ DENALI_HOST_ADDR
);
564 for (i
= 0; i
< size
/ 4; i
++)
565 *buf32
++ = ioread32(denali
->host
+ DENALI_HOST_DATA
);
567 irq_status
= denali_wait_for_irq(denali
, INTR__PAGE_XFER_INC
);
568 if (!(irq_status
& INTR__PAGE_XFER_INC
))
571 if (irq_status
& INTR__ERASED_PAGE
)
572 memset(buf
, 0xff, size
);
574 return irq_status
& ecc_err_mask
? -EBADMSG
: 0;
577 static int denali_pio_write(struct denali_nand_info
*denali
,
578 const void *buf
, size_t size
, int page
, int raw
)
580 uint32_t addr
= DENALI_BANK(denali
) | page
;
581 const uint32_t *buf32
= (uint32_t *)buf
;
585 denali_reset_irq(denali
);
587 iowrite32(DENALI_MAP01
| addr
, denali
->host
+ DENALI_HOST_ADDR
);
588 for (i
= 0; i
< size
/ 4; i
++)
589 iowrite32(*buf32
++, denali
->host
+ DENALI_HOST_DATA
);
591 irq_status
= denali_wait_for_irq(denali
,
592 INTR__PROGRAM_COMP
| INTR__PROGRAM_FAIL
);
593 if (!(irq_status
& INTR__PROGRAM_COMP
))
599 static int denali_pio_xfer(struct denali_nand_info
*denali
, void *buf
,
600 size_t size
, int page
, int raw
, int write
)
603 return denali_pio_write(denali
, buf
, size
, page
, raw
);
605 return denali_pio_read(denali
, buf
, size
, page
, raw
);
608 static int denali_dma_xfer(struct denali_nand_info
*denali
, void *buf
,
609 size_t size
, int page
, int raw
, int write
)
612 uint32_t irq_mask
, irq_status
, ecc_err_mask
;
613 enum dma_data_direction dir
= write
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
616 dma_addr
= dma_map_single(denali
->dev
, buf
, size
, dir
);
617 if (dma_mapping_error(denali
->dev
, dma_addr
)) {
618 dev_dbg(denali
->dev
, "Failed to DMA-map buffer. Trying PIO.\n");
619 return denali_pio_xfer(denali
, buf
, size
, page
, raw
, write
);
624 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
625 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
626 * when the page program is completed.
628 irq_mask
= INTR__DMA_CMD_COMP
| INTR__PROGRAM_FAIL
;
630 } else if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
) {
631 irq_mask
= INTR__DMA_CMD_COMP
;
632 ecc_err_mask
= INTR__ECC_UNCOR_ERR
;
634 irq_mask
= INTR__DMA_CMD_COMP
;
635 ecc_err_mask
= INTR__ECC_ERR
;
638 denali_enable_dma(denali
, true);
640 denali_reset_irq(denali
);
641 denali_setup_dma(denali
, dma_addr
, page
, write
);
643 /* wait for operation to complete */
644 irq_status
= denali_wait_for_irq(denali
, irq_mask
);
645 if (!(irq_status
& INTR__DMA_CMD_COMP
))
647 else if (irq_status
& ecc_err_mask
)
650 denali_enable_dma(denali
, false);
651 dma_unmap_single(denali
->dev
, dma_addr
, size
, dir
);
653 if (irq_status
& INTR__ERASED_PAGE
)
654 memset(buf
, 0xff, size
);
659 static int denali_data_xfer(struct denali_nand_info
*denali
, void *buf
,
660 size_t size
, int page
, int raw
, int write
)
662 setup_ecc_for_xfer(denali
, !raw
, raw
);
664 if (denali
->dma_avail
)
665 return denali_dma_xfer(denali
, buf
, size
, page
, raw
, write
);
667 return denali_pio_xfer(denali
, buf
, size
, page
, raw
, write
);
670 static void denali_oob_xfer(struct mtd_info
*mtd
, struct nand_chip
*chip
,
673 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
674 unsigned int start_cmd
= write
? NAND_CMD_SEQIN
: NAND_CMD_READ0
;
675 unsigned int rnd_cmd
= write
? NAND_CMD_RNDIN
: NAND_CMD_RNDOUT
;
676 int writesize
= mtd
->writesize
;
677 int oobsize
= mtd
->oobsize
;
678 uint8_t *bufpoi
= chip
->oob_poi
;
679 int ecc_steps
= chip
->ecc
.steps
;
680 int ecc_size
= chip
->ecc
.size
;
681 int ecc_bytes
= chip
->ecc
.bytes
;
682 int oob_skip
= denali
->oob_skip_bytes
;
683 size_t size
= writesize
+ oobsize
;
686 /* BBM at the beginning of the OOB area */
687 chip
->cmdfunc(mtd
, start_cmd
, writesize
, page
);
689 chip
->write_buf(mtd
, bufpoi
, oob_skip
);
691 chip
->read_buf(mtd
, bufpoi
, oob_skip
);
695 for (i
= 0; i
< ecc_steps
; i
++) {
696 pos
= ecc_size
+ i
* (ecc_size
+ ecc_bytes
);
699 if (pos
>= writesize
)
701 else if (pos
+ len
> writesize
)
702 len
= writesize
- pos
;
704 chip
->cmdfunc(mtd
, rnd_cmd
, pos
, -1);
706 chip
->write_buf(mtd
, bufpoi
, len
);
708 chip
->read_buf(mtd
, bufpoi
, len
);
710 if (len
< ecc_bytes
) {
711 len
= ecc_bytes
- len
;
712 chip
->cmdfunc(mtd
, rnd_cmd
, writesize
+ oob_skip
, -1);
714 chip
->write_buf(mtd
, bufpoi
, len
);
716 chip
->read_buf(mtd
, bufpoi
, len
);
722 len
= oobsize
- (bufpoi
- chip
->oob_poi
);
723 chip
->cmdfunc(mtd
, rnd_cmd
, size
- len
, -1);
725 chip
->write_buf(mtd
, bufpoi
, len
);
727 chip
->read_buf(mtd
, bufpoi
, len
);
730 static int denali_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
731 uint8_t *buf
, int oob_required
, int page
)
733 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
734 int writesize
= mtd
->writesize
;
735 int oobsize
= mtd
->oobsize
;
736 int ecc_steps
= chip
->ecc
.steps
;
737 int ecc_size
= chip
->ecc
.size
;
738 int ecc_bytes
= chip
->ecc
.bytes
;
739 void *dma_buf
= denali
->buf
;
740 int oob_skip
= denali
->oob_skip_bytes
;
741 size_t size
= writesize
+ oobsize
;
742 int ret
, i
, pos
, len
;
744 ret
= denali_data_xfer(denali
, dma_buf
, size
, page
, 1, 0);
748 /* Arrange the buffer for syndrome payload/ecc layout */
750 for (i
= 0; i
< ecc_steps
; i
++) {
751 pos
= i
* (ecc_size
+ ecc_bytes
);
754 if (pos
>= writesize
)
756 else if (pos
+ len
> writesize
)
757 len
= writesize
- pos
;
759 memcpy(buf
, dma_buf
+ pos
, len
);
761 if (len
< ecc_size
) {
762 len
= ecc_size
- len
;
763 memcpy(buf
, dma_buf
+ writesize
+ oob_skip
,
771 uint8_t *oob
= chip
->oob_poi
;
773 /* BBM at the beginning of the OOB area */
774 memcpy(oob
, dma_buf
+ writesize
, oob_skip
);
778 for (i
= 0; i
< ecc_steps
; i
++) {
779 pos
= ecc_size
+ i
* (ecc_size
+ ecc_bytes
);
782 if (pos
>= writesize
)
784 else if (pos
+ len
> writesize
)
785 len
= writesize
- pos
;
787 memcpy(oob
, dma_buf
+ pos
, len
);
789 if (len
< ecc_bytes
) {
790 len
= ecc_bytes
- len
;
791 memcpy(oob
, dma_buf
+ writesize
+ oob_skip
,
798 len
= oobsize
- (oob
- chip
->oob_poi
);
799 memcpy(oob
, dma_buf
+ size
- len
, len
);
805 static int denali_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
808 denali_oob_xfer(mtd
, chip
, page
, 0);
813 static int denali_write_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
816 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
819 denali_reset_irq(denali
);
821 denali_oob_xfer(mtd
, chip
, page
, 1);
823 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
824 status
= chip
->waitfunc(mtd
, chip
);
826 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
829 static int denali_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
830 uint8_t *buf
, int oob_required
, int page
)
832 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
833 unsigned long uncor_ecc_flags
= 0;
837 ret
= denali_data_xfer(denali
, buf
, mtd
->writesize
, page
, 0, 0);
838 if (ret
&& ret
!= -EBADMSG
)
841 if (denali
->caps
& DENALI_CAP_HW_ECC_FIXUP
)
842 stat
= denali_hw_ecc_fixup(mtd
, denali
, &uncor_ecc_flags
);
843 else if (ret
== -EBADMSG
)
844 stat
= denali_sw_ecc_fixup(mtd
, denali
, &uncor_ecc_flags
, buf
);
849 if (uncor_ecc_flags
) {
850 ret
= denali_read_oob(mtd
, chip
, page
);
854 stat
= denali_check_erased_page(mtd
, chip
, buf
,
855 uncor_ecc_flags
, stat
);
861 static int denali_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
862 const uint8_t *buf
, int oob_required
, int page
)
864 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
865 int writesize
= mtd
->writesize
;
866 int oobsize
= mtd
->oobsize
;
867 int ecc_steps
= chip
->ecc
.steps
;
868 int ecc_size
= chip
->ecc
.size
;
869 int ecc_bytes
= chip
->ecc
.bytes
;
870 void *dma_buf
= denali
->buf
;
871 int oob_skip
= denali
->oob_skip_bytes
;
872 size_t size
= writesize
+ oobsize
;
876 * Fill the buffer with 0xff first except the full page transfer.
877 * This simplifies the logic.
879 if (!buf
|| !oob_required
)
880 memset(dma_buf
, 0xff, size
);
882 /* Arrange the buffer for syndrome payload/ecc layout */
884 for (i
= 0; i
< ecc_steps
; i
++) {
885 pos
= i
* (ecc_size
+ ecc_bytes
);
888 if (pos
>= writesize
)
890 else if (pos
+ len
> writesize
)
891 len
= writesize
- pos
;
893 memcpy(dma_buf
+ pos
, buf
, len
);
895 if (len
< ecc_size
) {
896 len
= ecc_size
- len
;
897 memcpy(dma_buf
+ writesize
+ oob_skip
, buf
,
905 const uint8_t *oob
= chip
->oob_poi
;
907 /* BBM at the beginning of the OOB area */
908 memcpy(dma_buf
+ writesize
, oob
, oob_skip
);
912 for (i
= 0; i
< ecc_steps
; i
++) {
913 pos
= ecc_size
+ i
* (ecc_size
+ ecc_bytes
);
916 if (pos
>= writesize
)
918 else if (pos
+ len
> writesize
)
919 len
= writesize
- pos
;
921 memcpy(dma_buf
+ pos
, oob
, len
);
923 if (len
< ecc_bytes
) {
924 len
= ecc_bytes
- len
;
925 memcpy(dma_buf
+ writesize
+ oob_skip
, oob
,
932 len
= oobsize
- (oob
- chip
->oob_poi
);
933 memcpy(dma_buf
+ size
- len
, oob
, len
);
936 return denali_data_xfer(denali
, dma_buf
, size
, page
, 1, 1);
939 static int denali_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
940 const uint8_t *buf
, int oob_required
, int page
)
942 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
944 return denali_data_xfer(denali
, (void *)buf
, mtd
->writesize
,
948 static void denali_select_chip(struct mtd_info
*mtd
, int chip
)
950 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
952 denali
->active_bank
= chip
;
955 static int denali_waitfunc(struct mtd_info
*mtd
, struct nand_chip
*chip
)
957 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
960 /* R/B# pin transitioned from low to high? */
961 irq_status
= denali_wait_for_irq(denali
, INTR__INT_ACT
);
963 return irq_status
& INTR__INT_ACT
? 0 : NAND_STATUS_FAIL
;
966 static int denali_erase(struct mtd_info
*mtd
, int page
)
968 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
971 denali_reset_irq(denali
);
973 denali_host_write(denali
, DENALI_MAP10
| DENALI_BANK(denali
) | page
,
976 /* wait for erase to complete or failure to occur */
977 irq_status
= denali_wait_for_irq(denali
,
978 INTR__ERASE_COMP
| INTR__ERASE_FAIL
);
980 return irq_status
& INTR__ERASE_COMP
? 0 : NAND_STATUS_FAIL
;
983 static int denali_setup_data_interface(struct mtd_info
*mtd
, int chipnr
,
984 const struct nand_data_interface
*conf
)
986 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
987 const struct nand_sdr_timings
*timings
;
989 int acc_clks
, re_2_we
, re_2_re
, we_2_re
, addr_2_data
;
990 int rdwr_en_lo
, rdwr_en_hi
, rdwr_en_lo_hi
, cs_setup
;
991 int addr_2_data_mask
;
994 timings
= nand_get_sdr_timings(conf
);
996 return PTR_ERR(timings
);
998 /* clk_x period in picoseconds */
999 t_clk
= DIV_ROUND_DOWN_ULL(1000000000000ULL, denali
->clk_x_rate
);
1003 if (chipnr
== NAND_DATA_IFACE_CHECK_ONLY
)
1006 /* tREA -> ACC_CLKS */
1007 acc_clks
= DIV_ROUND_UP(timings
->tREA_max
, t_clk
);
1008 acc_clks
= min_t(int, acc_clks
, ACC_CLKS__VALUE
);
1010 tmp
= ioread32(denali
->reg
+ ACC_CLKS
);
1011 tmp
&= ~ACC_CLKS__VALUE
;
1013 iowrite32(tmp
, denali
->reg
+ ACC_CLKS
);
1015 /* tRWH -> RE_2_WE */
1016 re_2_we
= DIV_ROUND_UP(timings
->tRHW_min
, t_clk
);
1017 re_2_we
= min_t(int, re_2_we
, RE_2_WE__VALUE
);
1019 tmp
= ioread32(denali
->reg
+ RE_2_WE
);
1020 tmp
&= ~RE_2_WE__VALUE
;
1022 iowrite32(tmp
, denali
->reg
+ RE_2_WE
);
1024 /* tRHZ -> RE_2_RE */
1025 re_2_re
= DIV_ROUND_UP(timings
->tRHZ_max
, t_clk
);
1026 re_2_re
= min_t(int, re_2_re
, RE_2_RE__VALUE
);
1028 tmp
= ioread32(denali
->reg
+ RE_2_RE
);
1029 tmp
&= ~RE_2_RE__VALUE
;
1031 iowrite32(tmp
, denali
->reg
+ RE_2_RE
);
1033 /* tWHR -> WE_2_RE */
1034 we_2_re
= DIV_ROUND_UP(timings
->tWHR_min
, t_clk
);
1035 we_2_re
= min_t(int, we_2_re
, TWHR2_AND_WE_2_RE__WE_2_RE
);
1037 tmp
= ioread32(denali
->reg
+ TWHR2_AND_WE_2_RE
);
1038 tmp
&= ~TWHR2_AND_WE_2_RE__WE_2_RE
;
1040 iowrite32(tmp
, denali
->reg
+ TWHR2_AND_WE_2_RE
);
1042 /* tADL -> ADDR_2_DATA */
1044 /* for older versions, ADDR_2_DATA is only 6 bit wide */
1045 addr_2_data_mask
= TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA
;
1046 if (denali
->revision
< 0x0501)
1047 addr_2_data_mask
>>= 1;
1049 addr_2_data
= DIV_ROUND_UP(timings
->tADL_min
, t_clk
);
1050 addr_2_data
= min_t(int, addr_2_data
, addr_2_data_mask
);
1052 tmp
= ioread32(denali
->reg
+ TCWAW_AND_ADDR_2_DATA
);
1053 tmp
&= ~addr_2_data_mask
;
1055 iowrite32(tmp
, denali
->reg
+ TCWAW_AND_ADDR_2_DATA
);
1057 /* tREH, tWH -> RDWR_EN_HI_CNT */
1058 rdwr_en_hi
= DIV_ROUND_UP(max(timings
->tREH_min
, timings
->tWH_min
),
1060 rdwr_en_hi
= min_t(int, rdwr_en_hi
, RDWR_EN_HI_CNT__VALUE
);
1062 tmp
= ioread32(denali
->reg
+ RDWR_EN_HI_CNT
);
1063 tmp
&= ~RDWR_EN_HI_CNT__VALUE
;
1065 iowrite32(tmp
, denali
->reg
+ RDWR_EN_HI_CNT
);
1067 /* tRP, tWP -> RDWR_EN_LO_CNT */
1068 rdwr_en_lo
= DIV_ROUND_UP(max(timings
->tRP_min
, timings
->tWP_min
),
1070 rdwr_en_lo_hi
= DIV_ROUND_UP(max(timings
->tRC_min
, timings
->tWC_min
),
1072 rdwr_en_lo_hi
= max(rdwr_en_lo_hi
, DENALI_CLK_X_MULT
);
1073 rdwr_en_lo
= max(rdwr_en_lo
, rdwr_en_lo_hi
- rdwr_en_hi
);
1074 rdwr_en_lo
= min_t(int, rdwr_en_lo
, RDWR_EN_LO_CNT__VALUE
);
1076 tmp
= ioread32(denali
->reg
+ RDWR_EN_LO_CNT
);
1077 tmp
&= ~RDWR_EN_LO_CNT__VALUE
;
1079 iowrite32(tmp
, denali
->reg
+ RDWR_EN_LO_CNT
);
1081 /* tCS, tCEA -> CS_SETUP_CNT */
1082 cs_setup
= max3((int)DIV_ROUND_UP(timings
->tCS_min
, t_clk
) - rdwr_en_lo
,
1083 (int)DIV_ROUND_UP(timings
->tCEA_max
, t_clk
) - acc_clks
,
1085 cs_setup
= min_t(int, cs_setup
, CS_SETUP_CNT__VALUE
);
1087 tmp
= ioread32(denali
->reg
+ CS_SETUP_CNT
);
1088 tmp
&= ~CS_SETUP_CNT__VALUE
;
1090 iowrite32(tmp
, denali
->reg
+ CS_SETUP_CNT
);
1095 static void denali_reset_banks(struct denali_nand_info
*denali
)
1100 for (i
= 0; i
< denali
->max_banks
; i
++) {
1101 denali
->active_bank
= i
;
1103 denali_reset_irq(denali
);
1105 iowrite32(DEVICE_RESET__BANK(i
),
1106 denali
->reg
+ DEVICE_RESET
);
1108 irq_status
= denali_wait_for_irq(denali
,
1109 INTR__RST_COMP
| INTR__INT_ACT
| INTR__TIME_OUT
);
1110 if (!(irq_status
& INTR__INT_ACT
))
1114 dev_dbg(denali
->dev
, "%d chips connected\n", i
);
1115 denali
->max_banks
= i
;
1118 static void denali_hw_init(struct denali_nand_info
*denali
)
1121 * The REVISION register may not be reliable. Platforms are allowed to
1124 if (!denali
->revision
)
1125 denali
->revision
= swab16(ioread32(denali
->reg
+ REVISION
));
1128 * tell driver how many bit controller will skip before
1129 * writing ECC code in OOB, this register may be already
1130 * set by firmware. So we read this value out.
1131 * if this value is 0, just let it be.
1133 denali
->oob_skip_bytes
= ioread32(denali
->reg
+ SPARE_AREA_SKIP_BYTES
);
1134 detect_max_banks(denali
);
1135 iowrite32(0x0F, denali
->reg
+ RB_PIN_ENABLED
);
1136 iowrite32(CHIP_EN_DONT_CARE__FLAG
, denali
->reg
+ CHIP_ENABLE_DONT_CARE
);
1138 iowrite32(0xffff, denali
->reg
+ SPARE_AREA_MARKER
);
1140 /* Should set value for these registers when init */
1141 iowrite32(0, denali
->reg
+ TWO_ROW_ADDR_CYCLES
);
1142 iowrite32(1, denali
->reg
+ ECC_ENABLE
);
1145 int denali_calc_ecc_bytes(int step_size
, int strength
)
1147 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
1148 return DIV_ROUND_UP(strength
* fls(step_size
* 8), 16) * 2;
1150 EXPORT_SYMBOL(denali_calc_ecc_bytes
);
1152 static int denali_ecc_setup(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1153 struct denali_nand_info
*denali
)
1155 int oobavail
= mtd
->oobsize
- denali
->oob_skip_bytes
;
1159 * If .size and .strength are already set (usually by DT),
1160 * check if they are supported by this controller.
1162 if (chip
->ecc
.size
&& chip
->ecc
.strength
)
1163 return nand_check_ecc_caps(chip
, denali
->ecc_caps
, oobavail
);
1166 * We want .size and .strength closest to the chip's requirement
1167 * unless NAND_ECC_MAXIMIZE is requested.
1169 if (!(chip
->ecc
.options
& NAND_ECC_MAXIMIZE
)) {
1170 ret
= nand_match_ecc_req(chip
, denali
->ecc_caps
, oobavail
);
1175 /* Max ECC strength is the last thing we can do */
1176 return nand_maximize_ecc(chip
, denali
->ecc_caps
, oobavail
);
1179 static int denali_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
1180 struct mtd_oob_region
*oobregion
)
1182 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1183 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1188 oobregion
->offset
= denali
->oob_skip_bytes
;
1189 oobregion
->length
= chip
->ecc
.total
;
1194 static int denali_ooblayout_free(struct mtd_info
*mtd
, int section
,
1195 struct mtd_oob_region
*oobregion
)
1197 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1198 struct nand_chip
*chip
= mtd_to_nand(mtd
);
1203 oobregion
->offset
= chip
->ecc
.total
+ denali
->oob_skip_bytes
;
1204 oobregion
->length
= mtd
->oobsize
- oobregion
->offset
;
1209 static const struct mtd_ooblayout_ops denali_ooblayout_ops
= {
1210 .ecc
= denali_ooblayout_ecc
,
1211 .free
= denali_ooblayout_free
,
1214 /* initialize driver data structures */
1215 static void denali_drv_init(struct denali_nand_info
*denali
)
1218 * the completion object will be used to notify
1219 * the callee that the interrupt is done
1221 init_completion(&denali
->complete
);
1224 * the spinlock will be used to synchronize the ISR with any
1225 * element that might be access shared data (interrupt status)
1227 spin_lock_init(&denali
->irq_lock
);
1230 static int denali_multidev_fixup(struct denali_nand_info
*denali
)
1232 struct nand_chip
*chip
= &denali
->nand
;
1233 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1236 * Support for multi device:
1237 * When the IP configuration is x16 capable and two x8 chips are
1238 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1239 * In this case, the core framework knows nothing about this fact,
1240 * so we should tell it the _logical_ pagesize and anything necessary.
1242 denali
->devs_per_cs
= ioread32(denali
->reg
+ DEVICES_CONNECTED
);
1245 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1246 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1248 if (denali
->devs_per_cs
== 0) {
1249 denali
->devs_per_cs
= 1;
1250 iowrite32(1, denali
->reg
+ DEVICES_CONNECTED
);
1253 if (denali
->devs_per_cs
== 1)
1256 if (denali
->devs_per_cs
!= 2) {
1257 dev_err(denali
->dev
, "unsupported number of devices %d\n",
1258 denali
->devs_per_cs
);
1262 /* 2 chips in parallel */
1264 mtd
->erasesize
<<= 1;
1265 mtd
->writesize
<<= 1;
1267 chip
->chipsize
<<= 1;
1268 chip
->page_shift
+= 1;
1269 chip
->phys_erase_shift
+= 1;
1270 chip
->bbt_erase_shift
+= 1;
1271 chip
->chip_shift
+= 1;
1272 chip
->pagemask
<<= 1;
1273 chip
->ecc
.size
<<= 1;
1274 chip
->ecc
.bytes
<<= 1;
1275 chip
->ecc
.strength
<<= 1;
1276 denali
->oob_skip_bytes
<<= 1;
1281 int denali_init(struct denali_nand_info
*denali
)
1283 struct nand_chip
*chip
= &denali
->nand
;
1284 struct mtd_info
*mtd
= nand_to_mtd(chip
);
1287 mtd
->dev
.parent
= denali
->dev
;
1288 denali_hw_init(denali
);
1289 denali_drv_init(denali
);
1291 denali_clear_irq_all(denali
);
1293 /* Request IRQ after all the hardware initialization is finished */
1294 ret
= devm_request_irq(denali
->dev
, denali
->irq
, denali_isr
,
1295 IRQF_SHARED
, DENALI_NAND_NAME
, denali
);
1297 dev_err(denali
->dev
, "Unable to request IRQ\n");
1301 denali_enable_irq(denali
);
1302 denali_reset_banks(denali
);
1304 denali
->active_bank
= DENALI_INVALID_BANK
;
1306 nand_set_flash_node(chip
, denali
->dev
->of_node
);
1307 /* Fallback to the default name if DT did not give "label" property */
1309 mtd
->name
= "denali-nand";
1311 /* register the driver with the NAND core subsystem */
1312 chip
->select_chip
= denali_select_chip
;
1313 chip
->read_byte
= denali_read_byte
;
1314 chip
->write_byte
= denali_write_byte
;
1315 chip
->read_word
= denali_read_word
;
1316 chip
->cmd_ctrl
= denali_cmd_ctrl
;
1317 chip
->dev_ready
= denali_dev_ready
;
1318 chip
->waitfunc
= denali_waitfunc
;
1320 /* clk rate info is needed for setup_data_interface */
1321 if (denali
->clk_x_rate
)
1322 chip
->setup_data_interface
= denali_setup_data_interface
;
1325 * scan for NAND devices attached to the controller
1326 * this is the first stage in a two step process to register
1327 * with the nand subsystem
1329 ret
= nand_scan_ident(mtd
, denali
->max_banks
, NULL
);
1333 if (ioread32(denali
->reg
+ FEATURES
) & FEATURES__DMA
)
1334 denali
->dma_avail
= 1;
1336 if (denali
->dma_avail
) {
1337 int dma_bit
= denali
->caps
& DENALI_CAP_DMA_64BIT
? 64 : 32;
1339 ret
= dma_set_mask(denali
->dev
, DMA_BIT_MASK(dma_bit
));
1341 dev_info(denali
->dev
,
1342 "Failed to set DMA mask. Disabling DMA.\n");
1343 denali
->dma_avail
= 0;
1347 if (denali
->dma_avail
) {
1348 chip
->options
|= NAND_USE_BOUNCE_BUFFER
;
1349 chip
->buf_align
= 16;
1353 * second stage of the NAND scan
1354 * this stage requires information regarding ECC and
1355 * bad block management.
1358 chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
1359 chip
->bbt_options
|= NAND_BBT_NO_OOB
;
1361 chip
->ecc
.mode
= NAND_ECC_HW_SYNDROME
;
1363 /* no subpage writes on denali */
1364 chip
->options
|= NAND_NO_SUBPAGE_WRITE
;
1366 ret
= denali_ecc_setup(mtd
, chip
, denali
);
1368 dev_err(denali
->dev
, "Failed to setup ECC settings.\n");
1372 dev_dbg(denali
->dev
,
1373 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1374 chip
->ecc
.size
, chip
->ecc
.strength
, chip
->ecc
.bytes
);
1376 iowrite32(MAKE_ECC_CORRECTION(chip
->ecc
.strength
, 1),
1377 denali
->reg
+ ECC_CORRECTION
);
1378 iowrite32(mtd
->erasesize
/ mtd
->writesize
,
1379 denali
->reg
+ PAGES_PER_BLOCK
);
1380 iowrite32(chip
->options
& NAND_BUSWIDTH_16
? 1 : 0,
1381 denali
->reg
+ DEVICE_WIDTH
);
1382 iowrite32(mtd
->writesize
, denali
->reg
+ DEVICE_MAIN_AREA_SIZE
);
1383 iowrite32(mtd
->oobsize
, denali
->reg
+ DEVICE_SPARE_AREA_SIZE
);
1385 iowrite32(chip
->ecc
.size
, denali
->reg
+ CFG_DATA_BLOCK_SIZE
);
1386 iowrite32(chip
->ecc
.size
, denali
->reg
+ CFG_LAST_DATA_BLOCK_SIZE
);
1387 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1388 iowrite32(mtd
->writesize
/ chip
->ecc
.size
,
1389 denali
->reg
+ CFG_NUM_DATA_BLOCKS
);
1391 mtd_set_ooblayout(mtd
, &denali_ooblayout_ops
);
1393 if (chip
->options
& NAND_BUSWIDTH_16
) {
1394 chip
->read_buf
= denali_read_buf16
;
1395 chip
->write_buf
= denali_write_buf16
;
1397 chip
->read_buf
= denali_read_buf
;
1398 chip
->write_buf
= denali_write_buf
;
1400 chip
->ecc
.options
|= NAND_ECC_CUSTOM_PAGE_ACCESS
;
1401 chip
->ecc
.read_page
= denali_read_page
;
1402 chip
->ecc
.read_page_raw
= denali_read_page_raw
;
1403 chip
->ecc
.write_page
= denali_write_page
;
1404 chip
->ecc
.write_page_raw
= denali_write_page_raw
;
1405 chip
->ecc
.read_oob
= denali_read_oob
;
1406 chip
->ecc
.write_oob
= denali_write_oob
;
1407 chip
->erase
= denali_erase
;
1409 ret
= denali_multidev_fixup(denali
);
1414 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
1415 * use devm_kmalloc() because the memory allocated by devm_ does not
1416 * guarantee DMA-safe alignment.
1418 denali
->buf
= kmalloc(mtd
->writesize
+ mtd
->oobsize
, GFP_KERNEL
);
1424 ret
= nand_scan_tail(mtd
);
1428 ret
= mtd_device_register(mtd
, NULL
, 0);
1430 dev_err(denali
->dev
, "Failed to register MTD: %d\n", ret
);
1438 denali_disable_irq(denali
);
1442 EXPORT_SYMBOL(denali_init
);
1444 /* driver exit point */
1445 void denali_remove(struct denali_nand_info
*denali
)
1447 struct mtd_info
*mtd
= nand_to_mtd(&denali
->nand
);
1451 denali_disable_irq(denali
);
1453 EXPORT_SYMBOL(denali_remove
);