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[mirror_ubuntu-artful-kernel.git] / drivers / net / dsa / mv88e6xxx / chip.c
1 /*
2 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/netdevice.h>
32 #include <linux/gpio/consumer.h>
33 #include <linux/phy.h>
34 #include <net/dsa.h>
35 #include <net/switchdev.h>
36
37 #include "mv88e6xxx.h"
38 #include "global1.h"
39 #include "global2.h"
40 #include "port.h"
41
42 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
43 {
44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
45 dev_err(chip->dev, "Switch registers lock not held!\n");
46 dump_stack();
47 }
48 }
49
50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
52 *
53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
54 * is the only device connected to the SMI master. In this mode it responds to
55 * all 32 possible SMI addresses, and thus maps directly the internal devices.
56 *
57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
58 * multiple devices to share the SMI interface. In this mode it responds to only
59 * 2 registers, used to indirectly access the internal SMI devices.
60 */
61
62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
63 int addr, int reg, u16 *val)
64 {
65 if (!chip->smi_ops)
66 return -EOPNOTSUPP;
67
68 return chip->smi_ops->read(chip, addr, reg, val);
69 }
70
71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
72 int addr, int reg, u16 val)
73 {
74 if (!chip->smi_ops)
75 return -EOPNOTSUPP;
76
77 return chip->smi_ops->write(chip, addr, reg, val);
78 }
79
80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
81 int addr, int reg, u16 *val)
82 {
83 int ret;
84
85 ret = mdiobus_read_nested(chip->bus, addr, reg);
86 if (ret < 0)
87 return ret;
88
89 *val = ret & 0xffff;
90
91 return 0;
92 }
93
94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
95 int addr, int reg, u16 val)
96 {
97 int ret;
98
99 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
100 if (ret < 0)
101 return ret;
102
103 return 0;
104 }
105
106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
107 .read = mv88e6xxx_smi_single_chip_read,
108 .write = mv88e6xxx_smi_single_chip_write,
109 };
110
111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
112 {
113 int ret;
114 int i;
115
116 for (i = 0; i < 16; i++) {
117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
118 if (ret < 0)
119 return ret;
120
121 if ((ret & SMI_CMD_BUSY) == 0)
122 return 0;
123 }
124
125 return -ETIMEDOUT;
126 }
127
128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
129 int addr, int reg, u16 *val)
130 {
131 int ret;
132
133 /* Wait for the bus to become free. */
134 ret = mv88e6xxx_smi_multi_chip_wait(chip);
135 if (ret < 0)
136 return ret;
137
138 /* Transmit the read command. */
139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
140 SMI_CMD_OP_22_READ | (addr << 5) | reg);
141 if (ret < 0)
142 return ret;
143
144 /* Wait for the read command to complete. */
145 ret = mv88e6xxx_smi_multi_chip_wait(chip);
146 if (ret < 0)
147 return ret;
148
149 /* Read the data. */
150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
151 if (ret < 0)
152 return ret;
153
154 *val = ret & 0xffff;
155
156 return 0;
157 }
158
159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
160 int addr, int reg, u16 val)
161 {
162 int ret;
163
164 /* Wait for the bus to become free. */
165 ret = mv88e6xxx_smi_multi_chip_wait(chip);
166 if (ret < 0)
167 return ret;
168
169 /* Transmit the data to write. */
170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
171 if (ret < 0)
172 return ret;
173
174 /* Transmit the write command. */
175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
177 if (ret < 0)
178 return ret;
179
180 /* Wait for the write command to complete. */
181 ret = mv88e6xxx_smi_multi_chip_wait(chip);
182 if (ret < 0)
183 return ret;
184
185 return 0;
186 }
187
188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
189 .read = mv88e6xxx_smi_multi_chip_read,
190 .write = mv88e6xxx_smi_multi_chip_write,
191 };
192
193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
194 {
195 int err;
196
197 assert_reg_lock(chip);
198
199 err = mv88e6xxx_smi_read(chip, addr, reg, val);
200 if (err)
201 return err;
202
203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
204 addr, reg, *val);
205
206 return 0;
207 }
208
209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
210 {
211 int err;
212
213 assert_reg_lock(chip);
214
215 err = mv88e6xxx_smi_write(chip, addr, reg, val);
216 if (err)
217 return err;
218
219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
220 addr, reg, val);
221
222 return 0;
223 }
224
225 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
226 int reg, u16 *val)
227 {
228 int addr = phy; /* PHY devices addresses start at 0x0 */
229
230 if (!chip->info->ops->phy_read)
231 return -EOPNOTSUPP;
232
233 return chip->info->ops->phy_read(chip, addr, reg, val);
234 }
235
236 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
237 int reg, u16 val)
238 {
239 int addr = phy; /* PHY devices addresses start at 0x0 */
240
241 if (!chip->info->ops->phy_write)
242 return -EOPNOTSUPP;
243
244 return chip->info->ops->phy_write(chip, addr, reg, val);
245 }
246
247 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
248 {
249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
250 return -EOPNOTSUPP;
251
252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
253 }
254
255 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
256 {
257 int err;
258
259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
261 if (unlikely(err)) {
262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
263 phy, err);
264 }
265 }
266
267 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
268 u8 page, int reg, u16 *val)
269 {
270 int err;
271
272 /* There is no paging for registers 22 */
273 if (reg == PHY_PAGE)
274 return -EINVAL;
275
276 err = mv88e6xxx_phy_page_get(chip, phy, page);
277 if (!err) {
278 err = mv88e6xxx_phy_read(chip, phy, reg, val);
279 mv88e6xxx_phy_page_put(chip, phy);
280 }
281
282 return err;
283 }
284
285 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
286 u8 page, int reg, u16 val)
287 {
288 int err;
289
290 /* There is no paging for registers 22 */
291 if (reg == PHY_PAGE)
292 return -EINVAL;
293
294 err = mv88e6xxx_phy_page_get(chip, phy, page);
295 if (!err) {
296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
297 mv88e6xxx_phy_page_put(chip, phy);
298 }
299
300 return err;
301 }
302
303 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
304 {
305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
306 reg, val);
307 }
308
309 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
310 {
311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
312 reg, val);
313 }
314
315 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
316 {
317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
318 unsigned int n = d->hwirq;
319
320 chip->g1_irq.masked |= (1 << n);
321 }
322
323 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
324 {
325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
326 unsigned int n = d->hwirq;
327
328 chip->g1_irq.masked &= ~(1 << n);
329 }
330
331 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
332 {
333 struct mv88e6xxx_chip *chip = dev_id;
334 unsigned int nhandled = 0;
335 unsigned int sub_irq;
336 unsigned int n;
337 u16 reg;
338 int err;
339
340 mutex_lock(&chip->reg_lock);
341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
342 mutex_unlock(&chip->reg_lock);
343
344 if (err)
345 goto out;
346
347 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
348 if (reg & (1 << n)) {
349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
350 handle_nested_irq(sub_irq);
351 ++nhandled;
352 }
353 }
354 out:
355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
356 }
357
358 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
359 {
360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
361
362 mutex_lock(&chip->reg_lock);
363 }
364
365 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
366 {
367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
369 u16 reg;
370 int err;
371
372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &reg);
373 if (err)
374 goto out;
375
376 reg &= ~mask;
377 reg |= (~chip->g1_irq.masked & mask);
378
379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
380 if (err)
381 goto out;
382
383 out:
384 mutex_unlock(&chip->reg_lock);
385 }
386
387 static struct irq_chip mv88e6xxx_g1_irq_chip = {
388 .name = "mv88e6xxx-g1",
389 .irq_mask = mv88e6xxx_g1_irq_mask,
390 .irq_unmask = mv88e6xxx_g1_irq_unmask,
391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
393 };
394
395 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
396 unsigned int irq,
397 irq_hw_number_t hwirq)
398 {
399 struct mv88e6xxx_chip *chip = d->host_data;
400
401 irq_set_chip_data(irq, d->host_data);
402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
403 irq_set_noprobe(irq);
404
405 return 0;
406 }
407
408 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
409 .map = mv88e6xxx_g1_irq_domain_map,
410 .xlate = irq_domain_xlate_twocell,
411 };
412
413 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
414 {
415 int irq, virq;
416 u16 mask;
417
418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
419 mask |= GENMASK(chip->g1_irq.nirqs, 0);
420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
421
422 free_irq(chip->irq, chip);
423
424 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
425 virq = irq_find_mapping(chip->g1_irq.domain, irq);
426 irq_dispose_mapping(virq);
427 }
428
429 irq_domain_remove(chip->g1_irq.domain);
430 }
431
432 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
433 {
434 int err, irq, virq;
435 u16 reg, mask;
436
437 chip->g1_irq.nirqs = chip->info->g1_irqs;
438 chip->g1_irq.domain = irq_domain_add_simple(
439 NULL, chip->g1_irq.nirqs, 0,
440 &mv88e6xxx_g1_irq_domain_ops, chip);
441 if (!chip->g1_irq.domain)
442 return -ENOMEM;
443
444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
445 irq_create_mapping(chip->g1_irq.domain, irq);
446
447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
448 chip->g1_irq.masked = ~0;
449
450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask);
451 if (err)
452 goto out_mapping;
453
454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
455
456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
457 if (err)
458 goto out_disable;
459
460 /* Reading the interrupt status clears (most of) them */
461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &reg);
462 if (err)
463 goto out_disable;
464
465 err = request_threaded_irq(chip->irq, NULL,
466 mv88e6xxx_g1_irq_thread_fn,
467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
468 dev_name(chip->dev), chip);
469 if (err)
470 goto out_disable;
471
472 return 0;
473
474 out_disable:
475 mask |= GENMASK(chip->g1_irq.nirqs, 0);
476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask);
477
478 out_mapping:
479 for (irq = 0; irq < 16; irq++) {
480 virq = irq_find_mapping(chip->g1_irq.domain, irq);
481 irq_dispose_mapping(virq);
482 }
483
484 irq_domain_remove(chip->g1_irq.domain);
485
486 return err;
487 }
488
489 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
490 {
491 int i;
492
493 for (i = 0; i < 16; i++) {
494 u16 val;
495 int err;
496
497 err = mv88e6xxx_read(chip, addr, reg, &val);
498 if (err)
499 return err;
500
501 if (!(val & mask))
502 return 0;
503
504 usleep_range(1000, 2000);
505 }
506
507 dev_err(chip->dev, "Timeout while waiting for switch\n");
508 return -ETIMEDOUT;
509 }
510
511 /* Indirect write to single pointer-data register with an Update bit */
512 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
513 {
514 u16 val;
515 int err;
516
517 /* Wait until the previous operation is completed */
518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
519 if (err)
520 return err;
521
522 /* Set the Update bit to trigger a write operation */
523 val = BIT(15) | update;
524
525 return mv88e6xxx_write(chip, addr, reg, val);
526 }
527
528 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
529 {
530 if (!chip->info->ops->ppu_disable)
531 return 0;
532
533 return chip->info->ops->ppu_disable(chip);
534 }
535
536 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
537 {
538 if (!chip->info->ops->ppu_enable)
539 return 0;
540
541 return chip->info->ops->ppu_enable(chip);
542 }
543
544 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
545 {
546 struct mv88e6xxx_chip *chip;
547
548 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
549
550 mutex_lock(&chip->reg_lock);
551
552 if (mutex_trylock(&chip->ppu_mutex)) {
553 if (mv88e6xxx_ppu_enable(chip) == 0)
554 chip->ppu_disabled = 0;
555 mutex_unlock(&chip->ppu_mutex);
556 }
557
558 mutex_unlock(&chip->reg_lock);
559 }
560
561 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
562 {
563 struct mv88e6xxx_chip *chip = (void *)_ps;
564
565 schedule_work(&chip->ppu_work);
566 }
567
568 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
569 {
570 int ret;
571
572 mutex_lock(&chip->ppu_mutex);
573
574 /* If the PHY polling unit is enabled, disable it so that
575 * we can access the PHY registers. If it was already
576 * disabled, cancel the timer that is going to re-enable
577 * it.
578 */
579 if (!chip->ppu_disabled) {
580 ret = mv88e6xxx_ppu_disable(chip);
581 if (ret < 0) {
582 mutex_unlock(&chip->ppu_mutex);
583 return ret;
584 }
585 chip->ppu_disabled = 1;
586 } else {
587 del_timer(&chip->ppu_timer);
588 ret = 0;
589 }
590
591 return ret;
592 }
593
594 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
595 {
596 /* Schedule a timer to re-enable the PHY polling unit. */
597 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
598 mutex_unlock(&chip->ppu_mutex);
599 }
600
601 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
602 {
603 mutex_init(&chip->ppu_mutex);
604 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
605 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer,
606 (unsigned long)chip);
607 }
608
609 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
610 {
611 del_timer_sync(&chip->ppu_timer);
612 }
613
614 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
615 int reg, u16 *val)
616 {
617 int err;
618
619 err = mv88e6xxx_ppu_access_get(chip);
620 if (!err) {
621 err = mv88e6xxx_read(chip, addr, reg, val);
622 mv88e6xxx_ppu_access_put(chip);
623 }
624
625 return err;
626 }
627
628 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
629 int reg, u16 val)
630 {
631 int err;
632
633 err = mv88e6xxx_ppu_access_get(chip);
634 if (!err) {
635 err = mv88e6xxx_write(chip, addr, reg, val);
636 mv88e6xxx_ppu_access_put(chip);
637 }
638
639 return err;
640 }
641
642 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
643 {
644 return chip->info->family == MV88E6XXX_FAMILY_6095;
645 }
646
647 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
648 {
649 return chip->info->family == MV88E6XXX_FAMILY_6097;
650 }
651
652 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
653 {
654 return chip->info->family == MV88E6XXX_FAMILY_6165;
655 }
656
657 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
658 {
659 return chip->info->family == MV88E6XXX_FAMILY_6185;
660 }
661
662 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
663 {
664 return chip->info->family == MV88E6XXX_FAMILY_6320;
665 }
666
667 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
668 {
669 return chip->info->family == MV88E6XXX_FAMILY_6351;
670 }
671
672 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
673 {
674 return chip->info->family == MV88E6XXX_FAMILY_6352;
675 }
676
677 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
678 int link, int speed, int duplex,
679 phy_interface_t mode)
680 {
681 int err;
682
683 if (!chip->info->ops->port_set_link)
684 return 0;
685
686 /* Port's MAC control must not be changed unless the link is down */
687 err = chip->info->ops->port_set_link(chip, port, 0);
688 if (err)
689 return err;
690
691 if (chip->info->ops->port_set_speed) {
692 err = chip->info->ops->port_set_speed(chip, port, speed);
693 if (err && err != -EOPNOTSUPP)
694 goto restore_link;
695 }
696
697 if (chip->info->ops->port_set_duplex) {
698 err = chip->info->ops->port_set_duplex(chip, port, duplex);
699 if (err && err != -EOPNOTSUPP)
700 goto restore_link;
701 }
702
703 if (chip->info->ops->port_set_rgmii_delay) {
704 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
705 if (err && err != -EOPNOTSUPP)
706 goto restore_link;
707 }
708
709 err = 0;
710 restore_link:
711 if (chip->info->ops->port_set_link(chip, port, link))
712 netdev_err(chip->ds->ports[port].netdev,
713 "failed to restore MAC's link\n");
714
715 return err;
716 }
717
718 /* We expect the switch to perform auto negotiation if there is a real
719 * phy. However, in the case of a fixed link phy, we force the port
720 * settings from the fixed link settings.
721 */
722 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
723 struct phy_device *phydev)
724 {
725 struct mv88e6xxx_chip *chip = ds->priv;
726 int err;
727
728 if (!phy_is_pseudo_fixed_link(phydev))
729 return;
730
731 mutex_lock(&chip->reg_lock);
732 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
733 phydev->duplex, phydev->interface);
734 mutex_unlock(&chip->reg_lock);
735
736 if (err && err != -EOPNOTSUPP)
737 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n");
738 }
739
740 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
741 {
742 if (!chip->info->ops->stats_snapshot)
743 return -EOPNOTSUPP;
744
745 return chip->info->ops->stats_snapshot(chip, port);
746 }
747
748 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
749 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
750 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
751 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
752 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
753 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
754 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
755 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
756 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
757 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
758 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
759 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
760 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
761 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
762 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
763 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
764 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
765 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
766 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
767 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
768 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
769 { "single", 4, 0x14, STATS_TYPE_BANK0, },
770 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
771 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
772 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
773 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
774 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
775 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
776 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
777 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
778 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
779 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
780 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
781 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
782 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
783 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
784 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
785 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
786 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
787 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
788 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
789 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
790 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
791 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
792 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
793 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
794 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
795 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
796 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
797 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
798 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
799 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
800 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
801 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
802 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
803 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
804 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
805 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
806 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
807 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
808 };
809
810 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
811 struct mv88e6xxx_hw_stat *s,
812 int port, u16 bank1_select,
813 u16 histogram)
814 {
815 u32 low;
816 u32 high = 0;
817 u16 reg = 0;
818 int err;
819 u64 value;
820
821 switch (s->type) {
822 case STATS_TYPE_PORT:
823 err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
824 if (err)
825 return UINT64_MAX;
826
827 low = reg;
828 if (s->sizeof_stat == 4) {
829 err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
830 if (err)
831 return UINT64_MAX;
832 high = reg;
833 }
834 break;
835 case STATS_TYPE_BANK1:
836 reg = bank1_select;
837 /* fall through */
838 case STATS_TYPE_BANK0:
839 reg |= s->reg | histogram;
840 mv88e6xxx_g1_stats_read(chip, reg, &low);
841 if (s->sizeof_stat == 8)
842 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
843 }
844 value = (((u64)high) << 16) | low;
845 return value;
846 }
847
848 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
849 uint8_t *data, int types)
850 {
851 struct mv88e6xxx_hw_stat *stat;
852 int i, j;
853
854 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
855 stat = &mv88e6xxx_hw_stats[i];
856 if (stat->type & types) {
857 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
858 ETH_GSTRING_LEN);
859 j++;
860 }
861 }
862 }
863
864 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
865 uint8_t *data)
866 {
867 mv88e6xxx_stats_get_strings(chip, data,
868 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
869 }
870
871 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
872 uint8_t *data)
873 {
874 mv88e6xxx_stats_get_strings(chip, data,
875 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
876 }
877
878 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
879 uint8_t *data)
880 {
881 struct mv88e6xxx_chip *chip = ds->priv;
882
883 if (chip->info->ops->stats_get_strings)
884 chip->info->ops->stats_get_strings(chip, data);
885 }
886
887 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
888 int types)
889 {
890 struct mv88e6xxx_hw_stat *stat;
891 int i, j;
892
893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
894 stat = &mv88e6xxx_hw_stats[i];
895 if (stat->type & types)
896 j++;
897 }
898 return j;
899 }
900
901 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
902 {
903 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
904 STATS_TYPE_PORT);
905 }
906
907 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
908 {
909 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
910 STATS_TYPE_BANK1);
911 }
912
913 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
914 {
915 struct mv88e6xxx_chip *chip = ds->priv;
916
917 if (chip->info->ops->stats_get_sset_count)
918 return chip->info->ops->stats_get_sset_count(chip);
919
920 return 0;
921 }
922
923 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
924 uint64_t *data, int types,
925 u16 bank1_select, u16 histogram)
926 {
927 struct mv88e6xxx_hw_stat *stat;
928 int i, j;
929
930 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
931 stat = &mv88e6xxx_hw_stats[i];
932 if (stat->type & types) {
933 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
934 bank1_select,
935 histogram);
936 j++;
937 }
938 }
939 }
940
941 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
942 uint64_t *data)
943 {
944 return mv88e6xxx_stats_get_stats(chip, port, data,
945 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
946 0, GLOBAL_STATS_OP_HIST_RX_TX);
947 }
948
949 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
950 uint64_t *data)
951 {
952 return mv88e6xxx_stats_get_stats(chip, port, data,
953 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
954 GLOBAL_STATS_OP_BANK_1_BIT_9,
955 GLOBAL_STATS_OP_HIST_RX_TX);
956 }
957
958 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
959 uint64_t *data)
960 {
961 return mv88e6xxx_stats_get_stats(chip, port, data,
962 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
963 GLOBAL_STATS_OP_BANK_1_BIT_10, 0);
964 }
965
966 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
967 uint64_t *data)
968 {
969 if (chip->info->ops->stats_get_stats)
970 chip->info->ops->stats_get_stats(chip, port, data);
971 }
972
973 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
974 uint64_t *data)
975 {
976 struct mv88e6xxx_chip *chip = ds->priv;
977 int ret;
978
979 mutex_lock(&chip->reg_lock);
980
981 ret = mv88e6xxx_stats_snapshot(chip, port);
982 if (ret < 0) {
983 mutex_unlock(&chip->reg_lock);
984 return;
985 }
986
987 mv88e6xxx_get_stats(chip, port, data);
988
989 mutex_unlock(&chip->reg_lock);
990 }
991
992 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip)
993 {
994 if (chip->info->ops->stats_set_histogram)
995 return chip->info->ops->stats_set_histogram(chip);
996
997 return 0;
998 }
999
1000 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1001 {
1002 return 32 * sizeof(u16);
1003 }
1004
1005 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1006 struct ethtool_regs *regs, void *_p)
1007 {
1008 struct mv88e6xxx_chip *chip = ds->priv;
1009 int err;
1010 u16 reg;
1011 u16 *p = _p;
1012 int i;
1013
1014 regs->version = 0;
1015
1016 memset(p, 0xff, 32 * sizeof(u16));
1017
1018 mutex_lock(&chip->reg_lock);
1019
1020 for (i = 0; i < 32; i++) {
1021
1022 err = mv88e6xxx_port_read(chip, port, i, &reg);
1023 if (!err)
1024 p[i] = reg;
1025 }
1026
1027 mutex_unlock(&chip->reg_lock);
1028 }
1029
1030 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
1031 {
1032 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY);
1033 }
1034
1035 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1036 struct ethtool_eee *e)
1037 {
1038 struct mv88e6xxx_chip *chip = ds->priv;
1039 u16 reg;
1040 int err;
1041
1042 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1043 return -EOPNOTSUPP;
1044
1045 mutex_lock(&chip->reg_lock);
1046
1047 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1048 if (err)
1049 goto out;
1050
1051 e->eee_enabled = !!(reg & 0x0200);
1052 e->tx_lpi_enabled = !!(reg & 0x0100);
1053
1054 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
1055 if (err)
1056 goto out;
1057
1058 e->eee_active = !!(reg & PORT_STATUS_EEE);
1059 out:
1060 mutex_unlock(&chip->reg_lock);
1061
1062 return err;
1063 }
1064
1065 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1066 struct phy_device *phydev, struct ethtool_eee *e)
1067 {
1068 struct mv88e6xxx_chip *chip = ds->priv;
1069 u16 reg;
1070 int err;
1071
1072 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1073 return -EOPNOTSUPP;
1074
1075 mutex_lock(&chip->reg_lock);
1076
1077 err = mv88e6xxx_phy_read(chip, port, 16, &reg);
1078 if (err)
1079 goto out;
1080
1081 reg &= ~0x0300;
1082 if (e->eee_enabled)
1083 reg |= 0x0200;
1084 if (e->tx_lpi_enabled)
1085 reg |= 0x0100;
1086
1087 err = mv88e6xxx_phy_write(chip, port, 16, reg);
1088 out:
1089 mutex_unlock(&chip->reg_lock);
1090
1091 return err;
1092 }
1093
1094 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
1095 {
1096 u16 val;
1097 int err;
1098
1099 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) {
1100 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid);
1101 if (err)
1102 return err;
1103 } else if (mv88e6xxx_num_databases(chip) == 256) {
1104 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1105 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
1106 if (err)
1107 return err;
1108
1109 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
1110 (val & 0xfff) | ((fid << 8) & 0xf000));
1111 if (err)
1112 return err;
1113
1114 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1115 cmd |= fid & 0xf;
1116 }
1117
1118 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd);
1119 if (err)
1120 return err;
1121
1122 return _mv88e6xxx_atu_wait(chip);
1123 }
1124
1125 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1126 struct mv88e6xxx_atu_entry *entry)
1127 {
1128 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1129
1130 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1131 unsigned int mask, shift;
1132
1133 if (entry->trunk) {
1134 data |= GLOBAL_ATU_DATA_TRUNK;
1135 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1136 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1137 } else {
1138 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1139 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1140 }
1141
1142 data |= (entry->portv_trunkid << shift) & mask;
1143 }
1144
1145 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data);
1146 }
1147
1148 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1149 struct mv88e6xxx_atu_entry *entry,
1150 bool static_too)
1151 {
1152 int op;
1153 int err;
1154
1155 err = _mv88e6xxx_atu_wait(chip);
1156 if (err)
1157 return err;
1158
1159 err = _mv88e6xxx_atu_data_write(chip, entry);
1160 if (err)
1161 return err;
1162
1163 if (entry->fid) {
1164 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1165 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1166 } else {
1167 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1168 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1169 }
1170
1171 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1172 }
1173
1174 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1175 u16 fid, bool static_too)
1176 {
1177 struct mv88e6xxx_atu_entry entry = {
1178 .fid = fid,
1179 .state = 0, /* EntryState bits must be 0 */
1180 };
1181
1182 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1183 }
1184
1185 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1186 int from_port, int to_port, bool static_too)
1187 {
1188 struct mv88e6xxx_atu_entry entry = {
1189 .trunk = false,
1190 .fid = fid,
1191 };
1192
1193 /* EntryState bits must be 0xF */
1194 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1195
1196 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1197 entry.portv_trunkid = (to_port & 0x0f) << 4;
1198 entry.portv_trunkid |= from_port & 0x0f;
1199
1200 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1201 }
1202
1203 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1204 int port, bool static_too)
1205 {
1206 /* Destination port 0xF means remove the entries */
1207 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1208 }
1209
1210 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1211 {
1212 struct net_device *bridge = chip->ports[port].bridge_dev;
1213 struct dsa_switch *ds = chip->ds;
1214 u16 output_ports = 0;
1215 int i;
1216
1217 /* allow CPU port or DSA link(s) to send frames to every port */
1218 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1219 output_ports = ~0;
1220 } else {
1221 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1222 /* allow sending frames to every group member */
1223 if (bridge && chip->ports[i].bridge_dev == bridge)
1224 output_ports |= BIT(i);
1225
1226 /* allow sending frames to CPU port and DSA link(s) */
1227 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1228 output_ports |= BIT(i);
1229 }
1230 }
1231
1232 /* prevent frames from going back out of the port they came in on */
1233 output_ports &= ~BIT(port);
1234
1235 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1236 }
1237
1238 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1239 u8 state)
1240 {
1241 struct mv88e6xxx_chip *chip = ds->priv;
1242 int stp_state;
1243 int err;
1244
1245 switch (state) {
1246 case BR_STATE_DISABLED:
1247 stp_state = PORT_CONTROL_STATE_DISABLED;
1248 break;
1249 case BR_STATE_BLOCKING:
1250 case BR_STATE_LISTENING:
1251 stp_state = PORT_CONTROL_STATE_BLOCKING;
1252 break;
1253 case BR_STATE_LEARNING:
1254 stp_state = PORT_CONTROL_STATE_LEARNING;
1255 break;
1256 case BR_STATE_FORWARDING:
1257 default:
1258 stp_state = PORT_CONTROL_STATE_FORWARDING;
1259 break;
1260 }
1261
1262 mutex_lock(&chip->reg_lock);
1263 err = mv88e6xxx_port_set_state(chip, port, stp_state);
1264 mutex_unlock(&chip->reg_lock);
1265
1266 if (err)
1267 netdev_err(ds->ports[port].netdev, "failed to update state\n");
1268 }
1269
1270 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1271 {
1272 struct mv88e6xxx_chip *chip = ds->priv;
1273 int err;
1274
1275 mutex_lock(&chip->reg_lock);
1276 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1277 mutex_unlock(&chip->reg_lock);
1278
1279 if (err)
1280 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1281 }
1282
1283 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1284 {
1285 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
1286 }
1287
1288 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1289 {
1290 int err;
1291
1292 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
1293 if (err)
1294 return err;
1295
1296 return _mv88e6xxx_vtu_wait(chip);
1297 }
1298
1299 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1300 {
1301 int ret;
1302
1303 ret = _mv88e6xxx_vtu_wait(chip);
1304 if (ret < 0)
1305 return ret;
1306
1307 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1308 }
1309
1310 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1311 struct mv88e6xxx_vtu_entry *entry,
1312 unsigned int nibble_offset)
1313 {
1314 u16 regs[3];
1315 int i, err;
1316
1317 for (i = 0; i < 3; ++i) {
1318 u16 *reg = &regs[i];
1319
1320 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1321 if (err)
1322 return err;
1323 }
1324
1325 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1326 unsigned int shift = (i % 4) * 4 + nibble_offset;
1327 u16 reg = regs[i / 4];
1328
1329 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1330 }
1331
1332 return 0;
1333 }
1334
1335 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1336 struct mv88e6xxx_vtu_entry *entry)
1337 {
1338 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1339 }
1340
1341 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1342 struct mv88e6xxx_vtu_entry *entry)
1343 {
1344 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1345 }
1346
1347 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1348 struct mv88e6xxx_vtu_entry *entry,
1349 unsigned int nibble_offset)
1350 {
1351 u16 regs[3] = { 0 };
1352 int i, err;
1353
1354 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1355 unsigned int shift = (i % 4) * 4 + nibble_offset;
1356 u8 data = entry->data[i];
1357
1358 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1359 }
1360
1361 for (i = 0; i < 3; ++i) {
1362 u16 reg = regs[i];
1363
1364 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
1365 if (err)
1366 return err;
1367 }
1368
1369 return 0;
1370 }
1371
1372 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1373 struct mv88e6xxx_vtu_entry *entry)
1374 {
1375 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1376 }
1377
1378 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1379 struct mv88e6xxx_vtu_entry *entry)
1380 {
1381 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1382 }
1383
1384 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1385 {
1386 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID,
1387 vid & GLOBAL_VTU_VID_MASK);
1388 }
1389
1390 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1391 struct mv88e6xxx_vtu_entry *entry)
1392 {
1393 struct mv88e6xxx_vtu_entry next = { 0 };
1394 u16 val;
1395 int err;
1396
1397 err = _mv88e6xxx_vtu_wait(chip);
1398 if (err)
1399 return err;
1400
1401 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1402 if (err)
1403 return err;
1404
1405 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1406 if (err)
1407 return err;
1408
1409 next.vid = val & GLOBAL_VTU_VID_MASK;
1410 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1411
1412 if (next.valid) {
1413 err = mv88e6xxx_vtu_data_read(chip, &next);
1414 if (err)
1415 return err;
1416
1417 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1418 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
1419 if (err)
1420 return err;
1421
1422 next.fid = val & GLOBAL_VTU_FID_MASK;
1423 } else if (mv88e6xxx_num_databases(chip) == 256) {
1424 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1425 * VTU DBNum[3:0] are located in VTU Operation 3:0
1426 */
1427 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
1428 if (err)
1429 return err;
1430
1431 next.fid = (val & 0xf00) >> 4;
1432 next.fid |= val & 0xf;
1433 }
1434
1435 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1436 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1437 if (err)
1438 return err;
1439
1440 next.sid = val & GLOBAL_VTU_SID_MASK;
1441 }
1442 }
1443
1444 *entry = next;
1445 return 0;
1446 }
1447
1448 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1449 struct switchdev_obj_port_vlan *vlan,
1450 int (*cb)(struct switchdev_obj *obj))
1451 {
1452 struct mv88e6xxx_chip *chip = ds->priv;
1453 struct mv88e6xxx_vtu_entry next;
1454 u16 pvid;
1455 int err;
1456
1457 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1458 return -EOPNOTSUPP;
1459
1460 mutex_lock(&chip->reg_lock);
1461
1462 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1463 if (err)
1464 goto unlock;
1465
1466 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1467 if (err)
1468 goto unlock;
1469
1470 do {
1471 err = _mv88e6xxx_vtu_getnext(chip, &next);
1472 if (err)
1473 break;
1474
1475 if (!next.valid)
1476 break;
1477
1478 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1479 continue;
1480
1481 /* reinit and dump this VLAN obj */
1482 vlan->vid_begin = next.vid;
1483 vlan->vid_end = next.vid;
1484 vlan->flags = 0;
1485
1486 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1487 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1488
1489 if (next.vid == pvid)
1490 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1491
1492 err = cb(&vlan->obj);
1493 if (err)
1494 break;
1495 } while (next.vid < GLOBAL_VTU_VID_MASK);
1496
1497 unlock:
1498 mutex_unlock(&chip->reg_lock);
1499
1500 return err;
1501 }
1502
1503 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1504 struct mv88e6xxx_vtu_entry *entry)
1505 {
1506 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1507 u16 reg = 0;
1508 int err;
1509
1510 err = _mv88e6xxx_vtu_wait(chip);
1511 if (err)
1512 return err;
1513
1514 if (!entry->valid)
1515 goto loadpurge;
1516
1517 /* Write port member tags */
1518 err = mv88e6xxx_vtu_data_write(chip, entry);
1519 if (err)
1520 return err;
1521
1522 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1523 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1524 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1525 if (err)
1526 return err;
1527 }
1528
1529 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) {
1530 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1531 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg);
1532 if (err)
1533 return err;
1534 } else if (mv88e6xxx_num_databases(chip) == 256) {
1535 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1536 * VTU DBNum[3:0] are located in VTU Operation 3:0
1537 */
1538 op |= (entry->fid & 0xf0) << 8;
1539 op |= entry->fid & 0xf;
1540 }
1541
1542 reg = GLOBAL_VTU_VID_VALID;
1543 loadpurge:
1544 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1545 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1546 if (err)
1547 return err;
1548
1549 return _mv88e6xxx_vtu_cmd(chip, op);
1550 }
1551
1552 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1553 struct mv88e6xxx_vtu_entry *entry)
1554 {
1555 struct mv88e6xxx_vtu_entry next = { 0 };
1556 u16 val;
1557 int err;
1558
1559 err = _mv88e6xxx_vtu_wait(chip);
1560 if (err)
1561 return err;
1562
1563 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID,
1564 sid & GLOBAL_VTU_SID_MASK);
1565 if (err)
1566 return err;
1567
1568 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1569 if (err)
1570 return err;
1571
1572 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
1573 if (err)
1574 return err;
1575
1576 next.sid = val & GLOBAL_VTU_SID_MASK;
1577
1578 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
1579 if (err)
1580 return err;
1581
1582 next.valid = !!(val & GLOBAL_VTU_VID_VALID);
1583
1584 if (next.valid) {
1585 err = mv88e6xxx_stu_data_read(chip, &next);
1586 if (err)
1587 return err;
1588 }
1589
1590 *entry = next;
1591 return 0;
1592 }
1593
1594 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1595 struct mv88e6xxx_vtu_entry *entry)
1596 {
1597 u16 reg = 0;
1598 int err;
1599
1600 err = _mv88e6xxx_vtu_wait(chip);
1601 if (err)
1602 return err;
1603
1604 if (!entry->valid)
1605 goto loadpurge;
1606
1607 /* Write port states */
1608 err = mv88e6xxx_stu_data_write(chip, entry);
1609 if (err)
1610 return err;
1611
1612 reg = GLOBAL_VTU_VID_VALID;
1613 loadpurge:
1614 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg);
1615 if (err)
1616 return err;
1617
1618 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1619 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg);
1620 if (err)
1621 return err;
1622
1623 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1624 }
1625
1626 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1627 {
1628 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1629 struct mv88e6xxx_vtu_entry vlan;
1630 int i, err;
1631
1632 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1633
1634 /* Set every FID bit used by the (un)bridged ports */
1635 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1636 err = mv88e6xxx_port_get_fid(chip, i, fid);
1637 if (err)
1638 return err;
1639
1640 set_bit(*fid, fid_bitmap);
1641 }
1642
1643 /* Set every FID bit used by the VLAN entries */
1644 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1645 if (err)
1646 return err;
1647
1648 do {
1649 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1650 if (err)
1651 return err;
1652
1653 if (!vlan.valid)
1654 break;
1655
1656 set_bit(vlan.fid, fid_bitmap);
1657 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1658
1659 /* The reset value 0x000 is used to indicate that multiple address
1660 * databases are not needed. Return the next positive available.
1661 */
1662 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1663 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1664 return -ENOSPC;
1665
1666 /* Clear the database */
1667 return _mv88e6xxx_atu_flush(chip, *fid, true);
1668 }
1669
1670 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1671 struct mv88e6xxx_vtu_entry *entry)
1672 {
1673 struct dsa_switch *ds = chip->ds;
1674 struct mv88e6xxx_vtu_entry vlan = {
1675 .valid = true,
1676 .vid = vid,
1677 };
1678 int i, err;
1679
1680 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1681 if (err)
1682 return err;
1683
1684 /* exclude all ports except the CPU and DSA ports */
1685 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1686 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1687 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1688 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1689
1690 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1691 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1692 struct mv88e6xxx_vtu_entry vstp;
1693
1694 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1695 * implemented, only one STU entry is needed to cover all VTU
1696 * entries. Thus, validate the SID 0.
1697 */
1698 vlan.sid = 0;
1699 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1700 if (err)
1701 return err;
1702
1703 if (vstp.sid != vlan.sid || !vstp.valid) {
1704 memset(&vstp, 0, sizeof(vstp));
1705 vstp.valid = true;
1706 vstp.sid = vlan.sid;
1707
1708 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1709 if (err)
1710 return err;
1711 }
1712 }
1713
1714 *entry = vlan;
1715 return 0;
1716 }
1717
1718 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1719 struct mv88e6xxx_vtu_entry *entry, bool creat)
1720 {
1721 int err;
1722
1723 if (!vid)
1724 return -EINVAL;
1725
1726 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1727 if (err)
1728 return err;
1729
1730 err = _mv88e6xxx_vtu_getnext(chip, entry);
1731 if (err)
1732 return err;
1733
1734 if (entry->vid != vid || !entry->valid) {
1735 if (!creat)
1736 return -EOPNOTSUPP;
1737 /* -ENOENT would've been more appropriate, but switchdev expects
1738 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1739 */
1740
1741 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1742 }
1743
1744 return err;
1745 }
1746
1747 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1748 u16 vid_begin, u16 vid_end)
1749 {
1750 struct mv88e6xxx_chip *chip = ds->priv;
1751 struct mv88e6xxx_vtu_entry vlan;
1752 int i, err;
1753
1754 if (!vid_begin)
1755 return -EOPNOTSUPP;
1756
1757 mutex_lock(&chip->reg_lock);
1758
1759 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1760 if (err)
1761 goto unlock;
1762
1763 do {
1764 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1765 if (err)
1766 goto unlock;
1767
1768 if (!vlan.valid)
1769 break;
1770
1771 if (vlan.vid > vid_end)
1772 break;
1773
1774 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1775 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1776 continue;
1777
1778 if (!ds->ports[port].netdev)
1779 continue;
1780
1781 if (vlan.data[i] ==
1782 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1783 continue;
1784
1785 if (chip->ports[i].bridge_dev ==
1786 chip->ports[port].bridge_dev)
1787 break; /* same bridge, check next VLAN */
1788
1789 if (!chip->ports[i].bridge_dev)
1790 continue;
1791
1792 netdev_warn(ds->ports[port].netdev,
1793 "hardware VLAN %d already used by %s\n",
1794 vlan.vid,
1795 netdev_name(chip->ports[i].bridge_dev));
1796 err = -EOPNOTSUPP;
1797 goto unlock;
1798 }
1799 } while (vlan.vid < vid_end);
1800
1801 unlock:
1802 mutex_unlock(&chip->reg_lock);
1803
1804 return err;
1805 }
1806
1807 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1808 bool vlan_filtering)
1809 {
1810 struct mv88e6xxx_chip *chip = ds->priv;
1811 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1812 PORT_CONTROL_2_8021Q_DISABLED;
1813 int err;
1814
1815 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1816 return -EOPNOTSUPP;
1817
1818 mutex_lock(&chip->reg_lock);
1819 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1820 mutex_unlock(&chip->reg_lock);
1821
1822 return err;
1823 }
1824
1825 static int
1826 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1827 const struct switchdev_obj_port_vlan *vlan,
1828 struct switchdev_trans *trans)
1829 {
1830 struct mv88e6xxx_chip *chip = ds->priv;
1831 int err;
1832
1833 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1834 return -EOPNOTSUPP;
1835
1836 /* If the requested port doesn't belong to the same bridge as the VLAN
1837 * members, do not support it (yet) and fallback to software VLAN.
1838 */
1839 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1840 vlan->vid_end);
1841 if (err)
1842 return err;
1843
1844 /* We don't need any dynamic resource from the kernel (yet),
1845 * so skip the prepare phase.
1846 */
1847 return 0;
1848 }
1849
1850 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1851 u16 vid, bool untagged)
1852 {
1853 struct mv88e6xxx_vtu_entry vlan;
1854 int err;
1855
1856 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1857 if (err)
1858 return err;
1859
1860 vlan.data[port] = untagged ?
1861 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1862 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1863
1864 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1865 }
1866
1867 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1868 const struct switchdev_obj_port_vlan *vlan,
1869 struct switchdev_trans *trans)
1870 {
1871 struct mv88e6xxx_chip *chip = ds->priv;
1872 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1873 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1874 u16 vid;
1875
1876 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1877 return;
1878
1879 mutex_lock(&chip->reg_lock);
1880
1881 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1882 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1883 netdev_err(ds->ports[port].netdev,
1884 "failed to add VLAN %d%c\n",
1885 vid, untagged ? 'u' : 't');
1886
1887 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1888 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1889 vlan->vid_end);
1890
1891 mutex_unlock(&chip->reg_lock);
1892 }
1893
1894 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1895 int port, u16 vid)
1896 {
1897 struct dsa_switch *ds = chip->ds;
1898 struct mv88e6xxx_vtu_entry vlan;
1899 int i, err;
1900
1901 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1902 if (err)
1903 return err;
1904
1905 /* Tell switchdev if this VLAN is handled in software */
1906 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1907 return -EOPNOTSUPP;
1908
1909 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1910
1911 /* keep the VLAN unless all ports are excluded */
1912 vlan.valid = false;
1913 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1914 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1915 continue;
1916
1917 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1918 vlan.valid = true;
1919 break;
1920 }
1921 }
1922
1923 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1924 if (err)
1925 return err;
1926
1927 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1928 }
1929
1930 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1931 const struct switchdev_obj_port_vlan *vlan)
1932 {
1933 struct mv88e6xxx_chip *chip = ds->priv;
1934 u16 pvid, vid;
1935 int err = 0;
1936
1937 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1938 return -EOPNOTSUPP;
1939
1940 mutex_lock(&chip->reg_lock);
1941
1942 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1943 if (err)
1944 goto unlock;
1945
1946 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1947 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1948 if (err)
1949 goto unlock;
1950
1951 if (vid == pvid) {
1952 err = mv88e6xxx_port_set_pvid(chip, port, 0);
1953 if (err)
1954 goto unlock;
1955 }
1956 }
1957
1958 unlock:
1959 mutex_unlock(&chip->reg_lock);
1960
1961 return err;
1962 }
1963
1964 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
1965 const unsigned char *addr)
1966 {
1967 int i, err;
1968
1969 for (i = 0; i < 3; i++) {
1970 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i,
1971 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1972 if (err)
1973 return err;
1974 }
1975
1976 return 0;
1977 }
1978
1979 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
1980 unsigned char *addr)
1981 {
1982 u16 val;
1983 int i, err;
1984
1985 for (i = 0; i < 3; i++) {
1986 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val);
1987 if (err)
1988 return err;
1989
1990 addr[i * 2] = val >> 8;
1991 addr[i * 2 + 1] = val & 0xff;
1992 }
1993
1994 return 0;
1995 }
1996
1997 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
1998 struct mv88e6xxx_atu_entry *entry)
1999 {
2000 int ret;
2001
2002 ret = _mv88e6xxx_atu_wait(chip);
2003 if (ret < 0)
2004 return ret;
2005
2006 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2007 if (ret < 0)
2008 return ret;
2009
2010 ret = _mv88e6xxx_atu_data_write(chip, entry);
2011 if (ret < 0)
2012 return ret;
2013
2014 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2015 }
2016
2017 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2018 struct mv88e6xxx_atu_entry *entry);
2019
2020 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2021 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2022 {
2023 struct mv88e6xxx_atu_entry next;
2024 int err;
2025
2026 memcpy(next.mac, addr, ETH_ALEN);
2027 eth_addr_dec(next.mac);
2028
2029 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2030 if (err)
2031 return err;
2032
2033 do {
2034 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2035 if (err)
2036 return err;
2037
2038 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2039 break;
2040
2041 if (ether_addr_equal(next.mac, addr)) {
2042 *entry = next;
2043 return 0;
2044 }
2045 } while (ether_addr_greater(addr, next.mac));
2046
2047 memset(entry, 0, sizeof(*entry));
2048 entry->fid = fid;
2049 ether_addr_copy(entry->mac, addr);
2050
2051 return 0;
2052 }
2053
2054 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2055 const unsigned char *addr, u16 vid,
2056 u8 state)
2057 {
2058 struct mv88e6xxx_vtu_entry vlan;
2059 struct mv88e6xxx_atu_entry entry;
2060 int err;
2061
2062 /* Null VLAN ID corresponds to the port private database */
2063 if (vid == 0)
2064 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
2065 else
2066 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2067 if (err)
2068 return err;
2069
2070 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2071 if (err)
2072 return err;
2073
2074 /* Purge the ATU entry only if no port is using it anymore */
2075 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2076 entry.portv_trunkid &= ~BIT(port);
2077 if (!entry.portv_trunkid)
2078 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2079 } else {
2080 entry.portv_trunkid |= BIT(port);
2081 entry.state = state;
2082 }
2083
2084 return _mv88e6xxx_atu_load(chip, &entry);
2085 }
2086
2087 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2088 const struct switchdev_obj_port_fdb *fdb,
2089 struct switchdev_trans *trans)
2090 {
2091 /* We don't need any dynamic resource from the kernel (yet),
2092 * so skip the prepare phase.
2093 */
2094 return 0;
2095 }
2096
2097 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2098 const struct switchdev_obj_port_fdb *fdb,
2099 struct switchdev_trans *trans)
2100 {
2101 struct mv88e6xxx_chip *chip = ds->priv;
2102
2103 mutex_lock(&chip->reg_lock);
2104 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2105 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2106 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2107 mutex_unlock(&chip->reg_lock);
2108 }
2109
2110 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2111 const struct switchdev_obj_port_fdb *fdb)
2112 {
2113 struct mv88e6xxx_chip *chip = ds->priv;
2114 int err;
2115
2116 mutex_lock(&chip->reg_lock);
2117 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2118 GLOBAL_ATU_DATA_STATE_UNUSED);
2119 mutex_unlock(&chip->reg_lock);
2120
2121 return err;
2122 }
2123
2124 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2125 struct mv88e6xxx_atu_entry *entry)
2126 {
2127 struct mv88e6xxx_atu_entry next = { 0 };
2128 u16 val;
2129 int err;
2130
2131 next.fid = fid;
2132
2133 err = _mv88e6xxx_atu_wait(chip);
2134 if (err)
2135 return err;
2136
2137 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2138 if (err)
2139 return err;
2140
2141 err = _mv88e6xxx_atu_mac_read(chip, next.mac);
2142 if (err)
2143 return err;
2144
2145 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val);
2146 if (err)
2147 return err;
2148
2149 next.state = val & GLOBAL_ATU_DATA_STATE_MASK;
2150 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2151 unsigned int mask, shift;
2152
2153 if (val & GLOBAL_ATU_DATA_TRUNK) {
2154 next.trunk = true;
2155 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2156 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2157 } else {
2158 next.trunk = false;
2159 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2160 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2161 }
2162
2163 next.portv_trunkid = (val & mask) >> shift;
2164 }
2165
2166 *entry = next;
2167 return 0;
2168 }
2169
2170 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2171 u16 fid, u16 vid, int port,
2172 struct switchdev_obj *obj,
2173 int (*cb)(struct switchdev_obj *obj))
2174 {
2175 struct mv88e6xxx_atu_entry addr = {
2176 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2177 };
2178 int err;
2179
2180 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2181 if (err)
2182 return err;
2183
2184 do {
2185 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2186 if (err)
2187 return err;
2188
2189 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2190 break;
2191
2192 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2193 continue;
2194
2195 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2196 struct switchdev_obj_port_fdb *fdb;
2197
2198 if (!is_unicast_ether_addr(addr.mac))
2199 continue;
2200
2201 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2202 fdb->vid = vid;
2203 ether_addr_copy(fdb->addr, addr.mac);
2204 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2205 fdb->ndm_state = NUD_NOARP;
2206 else
2207 fdb->ndm_state = NUD_REACHABLE;
2208 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2209 struct switchdev_obj_port_mdb *mdb;
2210
2211 if (!is_multicast_ether_addr(addr.mac))
2212 continue;
2213
2214 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2215 mdb->vid = vid;
2216 ether_addr_copy(mdb->addr, addr.mac);
2217 } else {
2218 return -EOPNOTSUPP;
2219 }
2220
2221 err = cb(obj);
2222 if (err)
2223 return err;
2224 } while (!is_broadcast_ether_addr(addr.mac));
2225
2226 return err;
2227 }
2228
2229 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2230 struct switchdev_obj *obj,
2231 int (*cb)(struct switchdev_obj *obj))
2232 {
2233 struct mv88e6xxx_vtu_entry vlan = {
2234 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2235 };
2236 u16 fid;
2237 int err;
2238
2239 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2240 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2241 if (err)
2242 return err;
2243
2244 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2245 if (err)
2246 return err;
2247
2248 /* Dump VLANs' Filtering Information Databases */
2249 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2250 if (err)
2251 return err;
2252
2253 do {
2254 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2255 if (err)
2256 return err;
2257
2258 if (!vlan.valid)
2259 break;
2260
2261 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2262 obj, cb);
2263 if (err)
2264 return err;
2265 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2266
2267 return err;
2268 }
2269
2270 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2271 struct switchdev_obj_port_fdb *fdb,
2272 int (*cb)(struct switchdev_obj *obj))
2273 {
2274 struct mv88e6xxx_chip *chip = ds->priv;
2275 int err;
2276
2277 mutex_lock(&chip->reg_lock);
2278 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2279 mutex_unlock(&chip->reg_lock);
2280
2281 return err;
2282 }
2283
2284 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2285 struct net_device *bridge)
2286 {
2287 struct mv88e6xxx_chip *chip = ds->priv;
2288 int i, err = 0;
2289
2290 mutex_lock(&chip->reg_lock);
2291
2292 /* Assign the bridge and remap each port's VLANTable */
2293 chip->ports[port].bridge_dev = bridge;
2294
2295 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2296 if (chip->ports[i].bridge_dev == bridge) {
2297 err = _mv88e6xxx_port_based_vlan_map(chip, i);
2298 if (err)
2299 break;
2300 }
2301 }
2302
2303 mutex_unlock(&chip->reg_lock);
2304
2305 return err;
2306 }
2307
2308 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2309 {
2310 struct mv88e6xxx_chip *chip = ds->priv;
2311 struct net_device *bridge = chip->ports[port].bridge_dev;
2312 int i;
2313
2314 mutex_lock(&chip->reg_lock);
2315
2316 /* Unassign the bridge and remap each port's VLANTable */
2317 chip->ports[port].bridge_dev = NULL;
2318
2319 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2320 if (i == port || chip->ports[i].bridge_dev == bridge)
2321 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2322 netdev_warn(ds->ports[i].netdev,
2323 "failed to remap\n");
2324
2325 mutex_unlock(&chip->reg_lock);
2326 }
2327
2328 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2329 {
2330 if (chip->info->ops->reset)
2331 return chip->info->ops->reset(chip);
2332
2333 return 0;
2334 }
2335
2336 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2337 {
2338 struct gpio_desc *gpiod = chip->reset;
2339
2340 /* If there is a GPIO connected to the reset pin, toggle it */
2341 if (gpiod) {
2342 gpiod_set_value_cansleep(gpiod, 1);
2343 usleep_range(10000, 20000);
2344 gpiod_set_value_cansleep(gpiod, 0);
2345 usleep_range(10000, 20000);
2346 }
2347 }
2348
2349 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2350 {
2351 int i, err;
2352
2353 /* Set all ports to the Disabled state */
2354 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2355 err = mv88e6xxx_port_set_state(chip, i,
2356 PORT_CONTROL_STATE_DISABLED);
2357 if (err)
2358 return err;
2359 }
2360
2361 /* Wait for transmit queues to drain,
2362 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2363 */
2364 usleep_range(2000, 4000);
2365
2366 return 0;
2367 }
2368
2369 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2370 {
2371 int err;
2372
2373 err = mv88e6xxx_disable_ports(chip);
2374 if (err)
2375 return err;
2376
2377 mv88e6xxx_hardware_reset(chip);
2378
2379 return mv88e6xxx_software_reset(chip);
2380 }
2381
2382 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2383 {
2384 u16 val;
2385 int err;
2386
2387 /* Clear Power Down bit */
2388 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2389 if (err)
2390 return err;
2391
2392 if (val & BMCR_PDOWN) {
2393 val &= ~BMCR_PDOWN;
2394 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2395 }
2396
2397 return err;
2398 }
2399
2400 static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port,
2401 int upstream_port)
2402 {
2403 int err;
2404
2405 err = chip->info->ops->port_set_frame_mode(
2406 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2407 if (err)
2408 return err;
2409
2410 return chip->info->ops->port_set_egress_unknowns(
2411 chip, port, port == upstream_port);
2412 }
2413
2414 static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port)
2415 {
2416 int err;
2417
2418 switch (chip->info->tag_protocol) {
2419 case DSA_TAG_PROTO_EDSA:
2420 err = chip->info->ops->port_set_frame_mode(
2421 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE);
2422 if (err)
2423 return err;
2424
2425 err = mv88e6xxx_port_set_egress_mode(
2426 chip, port, PORT_CONTROL_EGRESS_ADD_TAG);
2427 if (err)
2428 return err;
2429
2430 if (chip->info->ops->port_set_ether_type)
2431 err = chip->info->ops->port_set_ether_type(
2432 chip, port, ETH_P_EDSA);
2433 break;
2434
2435 case DSA_TAG_PROTO_DSA:
2436 err = chip->info->ops->port_set_frame_mode(
2437 chip, port, MV88E6XXX_FRAME_MODE_DSA);
2438 if (err)
2439 return err;
2440
2441 err = mv88e6xxx_port_set_egress_mode(
2442 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED);
2443 break;
2444 default:
2445 err = -EINVAL;
2446 }
2447
2448 if (err)
2449 return err;
2450
2451 return chip->info->ops->port_set_egress_unknowns(chip, port, true);
2452 }
2453
2454 static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port)
2455 {
2456 int err;
2457
2458 err = chip->info->ops->port_set_frame_mode(
2459 chip, port, MV88E6XXX_FRAME_MODE_NORMAL);
2460 if (err)
2461 return err;
2462
2463 return chip->info->ops->port_set_egress_unknowns(chip, port, false);
2464 }
2465
2466 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2467 {
2468 struct dsa_switch *ds = chip->ds;
2469 int err;
2470 u16 reg;
2471
2472 /* MAC Forcing register: don't force link, speed, duplex or flow control
2473 * state to any particular values on physical ports, but force the CPU
2474 * port and all DSA ports to their maximum bandwidth and full duplex.
2475 */
2476 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2477 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2478 SPEED_MAX, DUPLEX_FULL,
2479 PHY_INTERFACE_MODE_NA);
2480 else
2481 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2482 SPEED_UNFORCED, DUPLEX_UNFORCED,
2483 PHY_INTERFACE_MODE_NA);
2484 if (err)
2485 return err;
2486
2487 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2488 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2489 * tunneling, determine priority by looking at 802.1p and IP
2490 * priority fields (IP prio has precedence), and set STP state
2491 * to Forwarding.
2492 *
2493 * If this is the CPU link, use DSA or EDSA tagging depending
2494 * on which tagging mode was configured.
2495 *
2496 * If this is a link to another switch, use DSA tagging mode.
2497 *
2498 * If this is the upstream port for this switch, enable
2499 * forwarding of unknown unicasts and multicasts.
2500 */
2501 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2502 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2503 PORT_CONTROL_STATE_FORWARDING;
2504 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2505 if (err)
2506 return err;
2507
2508 if (dsa_is_cpu_port(ds, port)) {
2509 err = mv88e6xxx_setup_port_cpu(chip, port);
2510 } else if (dsa_is_dsa_port(ds, port)) {
2511 err = mv88e6xxx_setup_port_dsa(chip, port,
2512 dsa_upstream_port(ds));
2513 } else {
2514 err = mv88e6xxx_setup_port_normal(chip, port);
2515 }
2516 if (err)
2517 return err;
2518
2519 /* If this port is connected to a SerDes, make sure the SerDes is not
2520 * powered down.
2521 */
2522 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2523 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, &reg);
2524 if (err)
2525 return err;
2526 reg &= PORT_STATUS_CMODE_MASK;
2527 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2528 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2529 (reg == PORT_STATUS_CMODE_SGMII)) {
2530 err = mv88e6xxx_serdes_power_on(chip);
2531 if (err < 0)
2532 return err;
2533 }
2534 }
2535
2536 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2537 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2538 * untagged frames on this port, do a destination address lookup on all
2539 * received packets as usual, disable ARP mirroring and don't send a
2540 * copy of all transmitted/received frames on this port to the CPU.
2541 */
2542 reg = 0;
2543 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2544 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2545 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2546 mv88e6xxx_6185_family(chip))
2547 reg = PORT_CONTROL_2_MAP_DA;
2548
2549 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2550 /* Set the upstream port this port should use */
2551 reg |= dsa_upstream_port(ds);
2552 /* enable forwarding of unknown multicast addresses to
2553 * the upstream port
2554 */
2555 if (port == dsa_upstream_port(ds))
2556 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2557 }
2558
2559 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2560
2561 if (reg) {
2562 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2563 if (err)
2564 return err;
2565 }
2566
2567 if (chip->info->ops->port_jumbo_config) {
2568 err = chip->info->ops->port_jumbo_config(chip, port);
2569 if (err)
2570 return err;
2571 }
2572
2573 /* Port Association Vector: when learning source addresses
2574 * of packets, add the address to the address database using
2575 * a port bitmap that has only the bit for this port set and
2576 * the other bits clear.
2577 */
2578 reg = 1 << port;
2579 /* Disable learning for CPU port */
2580 if (dsa_is_cpu_port(ds, port))
2581 reg = 0;
2582
2583 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2584 if (err)
2585 return err;
2586
2587 /* Egress rate control 2: disable egress rate control. */
2588 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2589 if (err)
2590 return err;
2591
2592 if (chip->info->ops->port_pause_config) {
2593 err = chip->info->ops->port_pause_config(chip, port);
2594 if (err)
2595 return err;
2596 }
2597
2598 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2599 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2600 mv88e6xxx_6320_family(chip)) {
2601 /* Port ATU control: disable limiting the number of
2602 * address database entries that this port is allowed
2603 * to use.
2604 */
2605 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2606 0x0000);
2607 /* Priority Override: disable DA, SA and VTU priority
2608 * override.
2609 */
2610 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2611 0x0000);
2612 if (err)
2613 return err;
2614 }
2615
2616 if (chip->info->ops->port_tag_remap) {
2617 err = chip->info->ops->port_tag_remap(chip, port);
2618 if (err)
2619 return err;
2620 }
2621
2622 if (chip->info->ops->port_egress_rate_limiting) {
2623 err = chip->info->ops->port_egress_rate_limiting(chip, port);
2624 if (err)
2625 return err;
2626 }
2627
2628 /* Port Control 1: disable trunking, disable sending
2629 * learning messages to this port.
2630 */
2631 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2632 if (err)
2633 return err;
2634
2635 /* Port based VLAN map: give each port the same default address
2636 * database, and allow bidirectional communication between the
2637 * CPU and DSA port(s), and the other ports.
2638 */
2639 err = mv88e6xxx_port_set_fid(chip, port, 0);
2640 if (err)
2641 return err;
2642
2643 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2644 if (err)
2645 return err;
2646
2647 /* Default VLAN ID and priority: don't set a default VLAN
2648 * ID, and set the default packet priority to zero.
2649 */
2650 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2651 }
2652
2653 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2654 {
2655 int err;
2656
2657 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
2658 if (err)
2659 return err;
2660
2661 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
2662 if (err)
2663 return err;
2664
2665 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
2666 if (err)
2667 return err;
2668
2669 return 0;
2670 }
2671
2672 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2673 unsigned int msecs)
2674 {
2675 const unsigned int coeff = chip->info->age_time_coeff;
2676 const unsigned int min = 0x01 * coeff;
2677 const unsigned int max = 0xff * coeff;
2678 u8 age_time;
2679 u16 val;
2680 int err;
2681
2682 if (msecs < min || msecs > max)
2683 return -ERANGE;
2684
2685 /* Round to nearest multiple of coeff */
2686 age_time = (msecs + coeff / 2) / coeff;
2687
2688 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val);
2689 if (err)
2690 return err;
2691
2692 /* AgeTime is 11:4 bits */
2693 val &= ~0xff0;
2694 val |= age_time << 4;
2695
2696 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val);
2697 }
2698
2699 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2700 unsigned int ageing_time)
2701 {
2702 struct mv88e6xxx_chip *chip = ds->priv;
2703 int err;
2704
2705 mutex_lock(&chip->reg_lock);
2706 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2707 mutex_unlock(&chip->reg_lock);
2708
2709 return err;
2710 }
2711
2712 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2713 {
2714 struct dsa_switch *ds = chip->ds;
2715 u32 upstream_port = dsa_upstream_port(ds);
2716 int err;
2717
2718 /* Enable the PHY Polling Unit if present, don't discard any packets,
2719 * and mask all interrupt sources.
2720 */
2721 err = mv88e6xxx_ppu_enable(chip);
2722 if (err)
2723 return err;
2724
2725 if (chip->info->ops->g1_set_cpu_port) {
2726 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port);
2727 if (err)
2728 return err;
2729 }
2730
2731 if (chip->info->ops->g1_set_egress_port) {
2732 err = chip->info->ops->g1_set_egress_port(chip, upstream_port);
2733 if (err)
2734 return err;
2735 }
2736
2737 /* Disable remote management, and set the switch's DSA device number. */
2738 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2,
2739 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2740 (ds->index & 0x1f));
2741 if (err)
2742 return err;
2743
2744 /* Clear all the VTU and STU entries */
2745 err = _mv88e6xxx_vtu_stu_flush(chip);
2746 if (err < 0)
2747 return err;
2748
2749 /* Set the default address aging time to 5 minutes, and
2750 * enable address learn messages to be sent to all message
2751 * ports.
2752 */
2753 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL,
2754 GLOBAL_ATU_CONTROL_LEARN2ALL);
2755 if (err)
2756 return err;
2757
2758 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2759 if (err)
2760 return err;
2761
2762 /* Clear all ATU entries */
2763 err = _mv88e6xxx_atu_flush(chip, 0, true);
2764 if (err)
2765 return err;
2766
2767 /* Configure the IP ToS mapping registers. */
2768 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000);
2769 if (err)
2770 return err;
2771 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000);
2772 if (err)
2773 return err;
2774 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555);
2775 if (err)
2776 return err;
2777 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555);
2778 if (err)
2779 return err;
2780 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa);
2781 if (err)
2782 return err;
2783 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa);
2784 if (err)
2785 return err;
2786 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff);
2787 if (err)
2788 return err;
2789 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff);
2790 if (err)
2791 return err;
2792
2793 /* Configure the IEEE 802.1p priority mapping register. */
2794 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41);
2795 if (err)
2796 return err;
2797
2798 /* Initialize the statistics unit */
2799 err = mv88e6xxx_stats_set_histogram(chip);
2800 if (err)
2801 return err;
2802
2803 /* Clear the statistics counters for all ports */
2804 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP,
2805 GLOBAL_STATS_OP_FLUSH_ALL);
2806 if (err)
2807 return err;
2808
2809 /* Wait for the flush to complete. */
2810 err = mv88e6xxx_g1_stats_wait(chip);
2811 if (err)
2812 return err;
2813
2814 return 0;
2815 }
2816
2817 static int mv88e6xxx_setup(struct dsa_switch *ds)
2818 {
2819 struct mv88e6xxx_chip *chip = ds->priv;
2820 int err;
2821 int i;
2822
2823 chip->ds = ds;
2824 ds->slave_mii_bus = chip->mdio_bus;
2825
2826 mutex_lock(&chip->reg_lock);
2827
2828 /* Setup Switch Port Registers */
2829 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2830 err = mv88e6xxx_setup_port(chip, i);
2831 if (err)
2832 goto unlock;
2833 }
2834
2835 /* Setup Switch Global 1 Registers */
2836 err = mv88e6xxx_g1_setup(chip);
2837 if (err)
2838 goto unlock;
2839
2840 /* Setup Switch Global 2 Registers */
2841 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2842 err = mv88e6xxx_g2_setup(chip);
2843 if (err)
2844 goto unlock;
2845 }
2846
2847 /* Some generations have the configuration of sending reserved
2848 * management frames to the CPU in global2, others in
2849 * global1. Hence it does not fit the two setup functions
2850 * above.
2851 */
2852 if (chip->info->ops->mgmt_rsvd2cpu) {
2853 err = chip->info->ops->mgmt_rsvd2cpu(chip);
2854 if (err)
2855 goto unlock;
2856 }
2857
2858 unlock:
2859 mutex_unlock(&chip->reg_lock);
2860
2861 return err;
2862 }
2863
2864 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2865 {
2866 struct mv88e6xxx_chip *chip = ds->priv;
2867 int err;
2868
2869 if (!chip->info->ops->set_switch_mac)
2870 return -EOPNOTSUPP;
2871
2872 mutex_lock(&chip->reg_lock);
2873 err = chip->info->ops->set_switch_mac(chip, addr);
2874 mutex_unlock(&chip->reg_lock);
2875
2876 return err;
2877 }
2878
2879 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2880 {
2881 struct mv88e6xxx_chip *chip = bus->priv;
2882 u16 val;
2883 int err;
2884
2885 if (phy >= mv88e6xxx_num_ports(chip))
2886 return 0xffff;
2887
2888 mutex_lock(&chip->reg_lock);
2889 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
2890 mutex_unlock(&chip->reg_lock);
2891
2892 return err ? err : val;
2893 }
2894
2895 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2896 {
2897 struct mv88e6xxx_chip *chip = bus->priv;
2898 int err;
2899
2900 if (phy >= mv88e6xxx_num_ports(chip))
2901 return 0xffff;
2902
2903 mutex_lock(&chip->reg_lock);
2904 err = mv88e6xxx_phy_write(chip, phy, reg, val);
2905 mutex_unlock(&chip->reg_lock);
2906
2907 return err;
2908 }
2909
2910 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2911 struct device_node *np)
2912 {
2913 static int index;
2914 struct mii_bus *bus;
2915 int err;
2916
2917 if (np)
2918 chip->mdio_np = of_get_child_by_name(np, "mdio");
2919
2920 bus = devm_mdiobus_alloc(chip->dev);
2921 if (!bus)
2922 return -ENOMEM;
2923
2924 bus->priv = (void *)chip;
2925 if (np) {
2926 bus->name = np->full_name;
2927 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
2928 } else {
2929 bus->name = "mv88e6xxx SMI";
2930 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2931 }
2932
2933 bus->read = mv88e6xxx_mdio_read;
2934 bus->write = mv88e6xxx_mdio_write;
2935 bus->parent = chip->dev;
2936
2937 if (chip->mdio_np)
2938 err = of_mdiobus_register(bus, chip->mdio_np);
2939 else
2940 err = mdiobus_register(bus);
2941 if (err) {
2942 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2943 goto out;
2944 }
2945 chip->mdio_bus = bus;
2946
2947 return 0;
2948
2949 out:
2950 if (chip->mdio_np)
2951 of_node_put(chip->mdio_np);
2952
2953 return err;
2954 }
2955
2956 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
2957
2958 {
2959 struct mii_bus *bus = chip->mdio_bus;
2960
2961 mdiobus_unregister(bus);
2962
2963 if (chip->mdio_np)
2964 of_node_put(chip->mdio_np);
2965 }
2966
2967 #ifdef CONFIG_NET_DSA_HWMON
2968
2969 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2970 {
2971 struct mv88e6xxx_chip *chip = ds->priv;
2972 u16 val;
2973 int ret;
2974
2975 *temp = 0;
2976
2977 mutex_lock(&chip->reg_lock);
2978
2979 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
2980 if (ret < 0)
2981 goto error;
2982
2983 /* Enable temperature sensor */
2984 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
2985 if (ret < 0)
2986 goto error;
2987
2988 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
2989 if (ret < 0)
2990 goto error;
2991
2992 /* Wait for temperature to stabilize */
2993 usleep_range(10000, 12000);
2994
2995 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
2996 if (ret < 0)
2997 goto error;
2998
2999 /* Disable temperature sensor */
3000 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3001 if (ret < 0)
3002 goto error;
3003
3004 *temp = ((val & 0x1f) - 5) * 5;
3005
3006 error:
3007 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3008 mutex_unlock(&chip->reg_lock);
3009 return ret;
3010 }
3011
3012 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3013 {
3014 struct mv88e6xxx_chip *chip = ds->priv;
3015 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3016 u16 val;
3017 int ret;
3018
3019 *temp = 0;
3020
3021 mutex_lock(&chip->reg_lock);
3022 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3023 mutex_unlock(&chip->reg_lock);
3024 if (ret < 0)
3025 return ret;
3026
3027 *temp = (val & 0xff) - 25;
3028
3029 return 0;
3030 }
3031
3032 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3033 {
3034 struct mv88e6xxx_chip *chip = ds->priv;
3035
3036 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3037 return -EOPNOTSUPP;
3038
3039 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3040 return mv88e63xx_get_temp(ds, temp);
3041
3042 return mv88e61xx_get_temp(ds, temp);
3043 }
3044
3045 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3046 {
3047 struct mv88e6xxx_chip *chip = ds->priv;
3048 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3049 u16 val;
3050 int ret;
3051
3052 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3053 return -EOPNOTSUPP;
3054
3055 *temp = 0;
3056
3057 mutex_lock(&chip->reg_lock);
3058 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3059 mutex_unlock(&chip->reg_lock);
3060 if (ret < 0)
3061 return ret;
3062
3063 *temp = (((val >> 8) & 0x1f) * 5) - 25;
3064
3065 return 0;
3066 }
3067
3068 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3069 {
3070 struct mv88e6xxx_chip *chip = ds->priv;
3071 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3072 u16 val;
3073 int err;
3074
3075 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3076 return -EOPNOTSUPP;
3077
3078 mutex_lock(&chip->reg_lock);
3079 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3080 if (err)
3081 goto unlock;
3082 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3083 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3084 (val & 0xe0ff) | (temp << 8));
3085 unlock:
3086 mutex_unlock(&chip->reg_lock);
3087
3088 return err;
3089 }
3090
3091 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3092 {
3093 struct mv88e6xxx_chip *chip = ds->priv;
3094 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3095 u16 val;
3096 int ret;
3097
3098 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3099 return -EOPNOTSUPP;
3100
3101 *alarm = false;
3102
3103 mutex_lock(&chip->reg_lock);
3104 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3105 mutex_unlock(&chip->reg_lock);
3106 if (ret < 0)
3107 return ret;
3108
3109 *alarm = !!(val & 0x40);
3110
3111 return 0;
3112 }
3113 #endif /* CONFIG_NET_DSA_HWMON */
3114
3115 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3116 {
3117 struct mv88e6xxx_chip *chip = ds->priv;
3118
3119 return chip->eeprom_len;
3120 }
3121
3122 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3123 struct ethtool_eeprom *eeprom, u8 *data)
3124 {
3125 struct mv88e6xxx_chip *chip = ds->priv;
3126 int err;
3127
3128 if (!chip->info->ops->get_eeprom)
3129 return -EOPNOTSUPP;
3130
3131 mutex_lock(&chip->reg_lock);
3132 err = chip->info->ops->get_eeprom(chip, eeprom, data);
3133 mutex_unlock(&chip->reg_lock);
3134
3135 if (err)
3136 return err;
3137
3138 eeprom->magic = 0xc3ec4951;
3139
3140 return 0;
3141 }
3142
3143 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3144 struct ethtool_eeprom *eeprom, u8 *data)
3145 {
3146 struct mv88e6xxx_chip *chip = ds->priv;
3147 int err;
3148
3149 if (!chip->info->ops->set_eeprom)
3150 return -EOPNOTSUPP;
3151
3152 if (eeprom->magic != 0xc3ec4951)
3153 return -EINVAL;
3154
3155 mutex_lock(&chip->reg_lock);
3156 err = chip->info->ops->set_eeprom(chip, eeprom, data);
3157 mutex_unlock(&chip->reg_lock);
3158
3159 return err;
3160 }
3161
3162 static const struct mv88e6xxx_ops mv88e6085_ops = {
3163 /* MV88E6XXX_FAMILY_6097 */
3164 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3165 .phy_read = mv88e6xxx_phy_ppu_read,
3166 .phy_write = mv88e6xxx_phy_ppu_write,
3167 .port_set_link = mv88e6xxx_port_set_link,
3168 .port_set_duplex = mv88e6xxx_port_set_duplex,
3169 .port_set_speed = mv88e6185_port_set_speed,
3170 .port_tag_remap = mv88e6095_port_tag_remap,
3171 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3172 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3173 .port_set_ether_type = mv88e6351_port_set_ether_type,
3174 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3175 .port_pause_config = mv88e6097_port_pause_config,
3176 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3177 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3178 .stats_get_strings = mv88e6095_stats_get_strings,
3179 .stats_get_stats = mv88e6095_stats_get_stats,
3180 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3181 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3182 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3183 .ppu_enable = mv88e6185_g1_ppu_enable,
3184 .ppu_disable = mv88e6185_g1_ppu_disable,
3185 .reset = mv88e6185_g1_reset,
3186 };
3187
3188 static const struct mv88e6xxx_ops mv88e6095_ops = {
3189 /* MV88E6XXX_FAMILY_6095 */
3190 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3191 .phy_read = mv88e6xxx_phy_ppu_read,
3192 .phy_write = mv88e6xxx_phy_ppu_write,
3193 .port_set_link = mv88e6xxx_port_set_link,
3194 .port_set_duplex = mv88e6xxx_port_set_duplex,
3195 .port_set_speed = mv88e6185_port_set_speed,
3196 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3197 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
3198 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3199 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3200 .stats_get_strings = mv88e6095_stats_get_strings,
3201 .stats_get_stats = mv88e6095_stats_get_stats,
3202 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3203 .ppu_enable = mv88e6185_g1_ppu_enable,
3204 .ppu_disable = mv88e6185_g1_ppu_disable,
3205 .reset = mv88e6185_g1_reset,
3206 };
3207
3208 static const struct mv88e6xxx_ops mv88e6097_ops = {
3209 /* MV88E6XXX_FAMILY_6097 */
3210 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3211 .phy_read = mv88e6xxx_g2_smi_phy_read,
3212 .phy_write = mv88e6xxx_g2_smi_phy_write,
3213 .port_set_link = mv88e6xxx_port_set_link,
3214 .port_set_duplex = mv88e6xxx_port_set_duplex,
3215 .port_set_speed = mv88e6185_port_set_speed,
3216 .port_tag_remap = mv88e6095_port_tag_remap,
3217 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3218 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3219 .port_set_ether_type = mv88e6351_port_set_ether_type,
3220 .port_jumbo_config = mv88e6165_port_jumbo_config,
3221 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3222 .port_pause_config = mv88e6097_port_pause_config,
3223 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3224 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3225 .stats_get_strings = mv88e6095_stats_get_strings,
3226 .stats_get_stats = mv88e6095_stats_get_stats,
3227 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3228 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3229 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3230 .reset = mv88e6352_g1_reset,
3231 };
3232
3233 static const struct mv88e6xxx_ops mv88e6123_ops = {
3234 /* MV88E6XXX_FAMILY_6165 */
3235 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3236 .phy_read = mv88e6xxx_read,
3237 .phy_write = mv88e6xxx_write,
3238 .port_set_link = mv88e6xxx_port_set_link,
3239 .port_set_duplex = mv88e6xxx_port_set_duplex,
3240 .port_set_speed = mv88e6185_port_set_speed,
3241 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3242 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
3243 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3244 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3245 .stats_get_strings = mv88e6095_stats_get_strings,
3246 .stats_get_stats = mv88e6095_stats_get_stats,
3247 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3248 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3249 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3250 .reset = mv88e6352_g1_reset,
3251 };
3252
3253 static const struct mv88e6xxx_ops mv88e6131_ops = {
3254 /* MV88E6XXX_FAMILY_6185 */
3255 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3256 .phy_read = mv88e6xxx_phy_ppu_read,
3257 .phy_write = mv88e6xxx_phy_ppu_write,
3258 .port_set_link = mv88e6xxx_port_set_link,
3259 .port_set_duplex = mv88e6xxx_port_set_duplex,
3260 .port_set_speed = mv88e6185_port_set_speed,
3261 .port_tag_remap = mv88e6095_port_tag_remap,
3262 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3263 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3264 .port_set_ether_type = mv88e6351_port_set_ether_type,
3265 .port_jumbo_config = mv88e6165_port_jumbo_config,
3266 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3267 .port_pause_config = mv88e6097_port_pause_config,
3268 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3269 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3270 .stats_get_strings = mv88e6095_stats_get_strings,
3271 .stats_get_stats = mv88e6095_stats_get_stats,
3272 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3273 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3274 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3275 .ppu_enable = mv88e6185_g1_ppu_enable,
3276 .ppu_disable = mv88e6185_g1_ppu_disable,
3277 .reset = mv88e6185_g1_reset,
3278 };
3279
3280 static const struct mv88e6xxx_ops mv88e6161_ops = {
3281 /* MV88E6XXX_FAMILY_6165 */
3282 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3283 .phy_read = mv88e6xxx_read,
3284 .phy_write = mv88e6xxx_write,
3285 .port_set_link = mv88e6xxx_port_set_link,
3286 .port_set_duplex = mv88e6xxx_port_set_duplex,
3287 .port_set_speed = mv88e6185_port_set_speed,
3288 .port_tag_remap = mv88e6095_port_tag_remap,
3289 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3290 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3291 .port_set_ether_type = mv88e6351_port_set_ether_type,
3292 .port_jumbo_config = mv88e6165_port_jumbo_config,
3293 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3294 .port_pause_config = mv88e6097_port_pause_config,
3295 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3296 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3297 .stats_get_strings = mv88e6095_stats_get_strings,
3298 .stats_get_stats = mv88e6095_stats_get_stats,
3299 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3300 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3301 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3302 .reset = mv88e6352_g1_reset,
3303 };
3304
3305 static const struct mv88e6xxx_ops mv88e6165_ops = {
3306 /* MV88E6XXX_FAMILY_6165 */
3307 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3308 .phy_read = mv88e6xxx_read,
3309 .phy_write = mv88e6xxx_write,
3310 .port_set_link = mv88e6xxx_port_set_link,
3311 .port_set_duplex = mv88e6xxx_port_set_duplex,
3312 .port_set_speed = mv88e6185_port_set_speed,
3313 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3314 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3315 .stats_get_strings = mv88e6095_stats_get_strings,
3316 .stats_get_stats = mv88e6095_stats_get_stats,
3317 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3318 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3319 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3320 .reset = mv88e6352_g1_reset,
3321 };
3322
3323 static const struct mv88e6xxx_ops mv88e6171_ops = {
3324 /* MV88E6XXX_FAMILY_6351 */
3325 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3326 .phy_read = mv88e6xxx_g2_smi_phy_read,
3327 .phy_write = mv88e6xxx_g2_smi_phy_write,
3328 .port_set_link = mv88e6xxx_port_set_link,
3329 .port_set_duplex = mv88e6xxx_port_set_duplex,
3330 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3331 .port_set_speed = mv88e6185_port_set_speed,
3332 .port_tag_remap = mv88e6095_port_tag_remap,
3333 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3334 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3335 .port_set_ether_type = mv88e6351_port_set_ether_type,
3336 .port_jumbo_config = mv88e6165_port_jumbo_config,
3337 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3338 .port_pause_config = mv88e6097_port_pause_config,
3339 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3340 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3341 .stats_get_strings = mv88e6095_stats_get_strings,
3342 .stats_get_stats = mv88e6095_stats_get_stats,
3343 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3344 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3345 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3346 .reset = mv88e6352_g1_reset,
3347 };
3348
3349 static const struct mv88e6xxx_ops mv88e6172_ops = {
3350 /* MV88E6XXX_FAMILY_6352 */
3351 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3352 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3353 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3354 .phy_read = mv88e6xxx_g2_smi_phy_read,
3355 .phy_write = mv88e6xxx_g2_smi_phy_write,
3356 .port_set_link = mv88e6xxx_port_set_link,
3357 .port_set_duplex = mv88e6xxx_port_set_duplex,
3358 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3359 .port_set_speed = mv88e6352_port_set_speed,
3360 .port_tag_remap = mv88e6095_port_tag_remap,
3361 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3362 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3363 .port_set_ether_type = mv88e6351_port_set_ether_type,
3364 .port_jumbo_config = mv88e6165_port_jumbo_config,
3365 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3366 .port_pause_config = mv88e6097_port_pause_config,
3367 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3368 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3369 .stats_get_strings = mv88e6095_stats_get_strings,
3370 .stats_get_stats = mv88e6095_stats_get_stats,
3371 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3372 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3373 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3374 .reset = mv88e6352_g1_reset,
3375 };
3376
3377 static const struct mv88e6xxx_ops mv88e6175_ops = {
3378 /* MV88E6XXX_FAMILY_6351 */
3379 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3380 .phy_read = mv88e6xxx_g2_smi_phy_read,
3381 .phy_write = mv88e6xxx_g2_smi_phy_write,
3382 .port_set_link = mv88e6xxx_port_set_link,
3383 .port_set_duplex = mv88e6xxx_port_set_duplex,
3384 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3385 .port_set_speed = mv88e6185_port_set_speed,
3386 .port_tag_remap = mv88e6095_port_tag_remap,
3387 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3388 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3389 .port_set_ether_type = mv88e6351_port_set_ether_type,
3390 .port_jumbo_config = mv88e6165_port_jumbo_config,
3391 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3392 .port_pause_config = mv88e6097_port_pause_config,
3393 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3394 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3395 .stats_get_strings = mv88e6095_stats_get_strings,
3396 .stats_get_stats = mv88e6095_stats_get_stats,
3397 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3398 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3399 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3400 .reset = mv88e6352_g1_reset,
3401 };
3402
3403 static const struct mv88e6xxx_ops mv88e6176_ops = {
3404 /* MV88E6XXX_FAMILY_6352 */
3405 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3406 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3407 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3408 .phy_read = mv88e6xxx_g2_smi_phy_read,
3409 .phy_write = mv88e6xxx_g2_smi_phy_write,
3410 .port_set_link = mv88e6xxx_port_set_link,
3411 .port_set_duplex = mv88e6xxx_port_set_duplex,
3412 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3413 .port_set_speed = mv88e6352_port_set_speed,
3414 .port_tag_remap = mv88e6095_port_tag_remap,
3415 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3416 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3417 .port_set_ether_type = mv88e6351_port_set_ether_type,
3418 .port_jumbo_config = mv88e6165_port_jumbo_config,
3419 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3420 .port_pause_config = mv88e6097_port_pause_config,
3421 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3422 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3423 .stats_get_strings = mv88e6095_stats_get_strings,
3424 .stats_get_stats = mv88e6095_stats_get_stats,
3425 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3426 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3427 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3428 .reset = mv88e6352_g1_reset,
3429 };
3430
3431 static const struct mv88e6xxx_ops mv88e6185_ops = {
3432 /* MV88E6XXX_FAMILY_6185 */
3433 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3434 .phy_read = mv88e6xxx_phy_ppu_read,
3435 .phy_write = mv88e6xxx_phy_ppu_write,
3436 .port_set_link = mv88e6xxx_port_set_link,
3437 .port_set_duplex = mv88e6xxx_port_set_duplex,
3438 .port_set_speed = mv88e6185_port_set_speed,
3439 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
3440 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns,
3441 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3442 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3443 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3444 .stats_get_strings = mv88e6095_stats_get_strings,
3445 .stats_get_stats = mv88e6095_stats_get_stats,
3446 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3447 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3448 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3449 .ppu_enable = mv88e6185_g1_ppu_enable,
3450 .ppu_disable = mv88e6185_g1_ppu_disable,
3451 .reset = mv88e6185_g1_reset,
3452 };
3453
3454 static const struct mv88e6xxx_ops mv88e6190_ops = {
3455 /* MV88E6XXX_FAMILY_6390 */
3456 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3457 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3458 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3459 .phy_read = mv88e6xxx_g2_smi_phy_read,
3460 .phy_write = mv88e6xxx_g2_smi_phy_write,
3461 .port_set_link = mv88e6xxx_port_set_link,
3462 .port_set_duplex = mv88e6xxx_port_set_duplex,
3463 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3464 .port_set_speed = mv88e6390_port_set_speed,
3465 .port_tag_remap = mv88e6390_port_tag_remap,
3466 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3467 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3468 .port_set_ether_type = mv88e6351_port_set_ether_type,
3469 .port_pause_config = mv88e6390_port_pause_config,
3470 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3471 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3472 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3473 .stats_get_strings = mv88e6320_stats_get_strings,
3474 .stats_get_stats = mv88e6390_stats_get_stats,
3475 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3476 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3477 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3478 .reset = mv88e6352_g1_reset,
3479 };
3480
3481 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3482 /* MV88E6XXX_FAMILY_6390 */
3483 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3484 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3485 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3486 .phy_read = mv88e6xxx_g2_smi_phy_read,
3487 .phy_write = mv88e6xxx_g2_smi_phy_write,
3488 .port_set_link = mv88e6xxx_port_set_link,
3489 .port_set_duplex = mv88e6xxx_port_set_duplex,
3490 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3491 .port_set_speed = mv88e6390x_port_set_speed,
3492 .port_tag_remap = mv88e6390_port_tag_remap,
3493 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3494 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3495 .port_set_ether_type = mv88e6351_port_set_ether_type,
3496 .port_pause_config = mv88e6390_port_pause_config,
3497 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3498 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3499 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3500 .stats_get_strings = mv88e6320_stats_get_strings,
3501 .stats_get_stats = mv88e6390_stats_get_stats,
3502 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3503 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3504 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3505 .reset = mv88e6352_g1_reset,
3506 };
3507
3508 static const struct mv88e6xxx_ops mv88e6191_ops = {
3509 /* MV88E6XXX_FAMILY_6390 */
3510 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3511 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3512 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3513 .phy_read = mv88e6xxx_g2_smi_phy_read,
3514 .phy_write = mv88e6xxx_g2_smi_phy_write,
3515 .port_set_link = mv88e6xxx_port_set_link,
3516 .port_set_duplex = mv88e6xxx_port_set_duplex,
3517 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3518 .port_set_speed = mv88e6390_port_set_speed,
3519 .port_tag_remap = mv88e6390_port_tag_remap,
3520 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3521 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3522 .port_set_ether_type = mv88e6351_port_set_ether_type,
3523 .port_pause_config = mv88e6390_port_pause_config,
3524 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3525 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3526 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3527 .stats_get_strings = mv88e6320_stats_get_strings,
3528 .stats_get_stats = mv88e6390_stats_get_stats,
3529 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3530 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3531 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3532 .reset = mv88e6352_g1_reset,
3533 };
3534
3535 static const struct mv88e6xxx_ops mv88e6240_ops = {
3536 /* MV88E6XXX_FAMILY_6352 */
3537 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3538 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3539 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3540 .phy_read = mv88e6xxx_g2_smi_phy_read,
3541 .phy_write = mv88e6xxx_g2_smi_phy_write,
3542 .port_set_link = mv88e6xxx_port_set_link,
3543 .port_set_duplex = mv88e6xxx_port_set_duplex,
3544 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3545 .port_set_speed = mv88e6352_port_set_speed,
3546 .port_tag_remap = mv88e6095_port_tag_remap,
3547 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3548 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3549 .port_set_ether_type = mv88e6351_port_set_ether_type,
3550 .port_jumbo_config = mv88e6165_port_jumbo_config,
3551 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3552 .port_pause_config = mv88e6097_port_pause_config,
3553 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3554 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3555 .stats_get_strings = mv88e6095_stats_get_strings,
3556 .stats_get_stats = mv88e6095_stats_get_stats,
3557 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3558 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3559 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3560 .reset = mv88e6352_g1_reset,
3561 };
3562
3563 static const struct mv88e6xxx_ops mv88e6290_ops = {
3564 /* MV88E6XXX_FAMILY_6390 */
3565 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3566 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3567 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3568 .phy_read = mv88e6xxx_g2_smi_phy_read,
3569 .phy_write = mv88e6xxx_g2_smi_phy_write,
3570 .port_set_link = mv88e6xxx_port_set_link,
3571 .port_set_duplex = mv88e6xxx_port_set_duplex,
3572 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3573 .port_set_speed = mv88e6390_port_set_speed,
3574 .port_tag_remap = mv88e6390_port_tag_remap,
3575 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3576 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3577 .port_set_ether_type = mv88e6351_port_set_ether_type,
3578 .port_pause_config = mv88e6390_port_pause_config,
3579 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3580 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3581 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3582 .stats_get_strings = mv88e6320_stats_get_strings,
3583 .stats_get_stats = mv88e6390_stats_get_stats,
3584 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3585 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3586 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3587 .reset = mv88e6352_g1_reset,
3588 };
3589
3590 static const struct mv88e6xxx_ops mv88e6320_ops = {
3591 /* MV88E6XXX_FAMILY_6320 */
3592 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3593 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3594 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3595 .phy_read = mv88e6xxx_g2_smi_phy_read,
3596 .phy_write = mv88e6xxx_g2_smi_phy_write,
3597 .port_set_link = mv88e6xxx_port_set_link,
3598 .port_set_duplex = mv88e6xxx_port_set_duplex,
3599 .port_set_speed = mv88e6185_port_set_speed,
3600 .port_tag_remap = mv88e6095_port_tag_remap,
3601 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3602 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3603 .port_set_ether_type = mv88e6351_port_set_ether_type,
3604 .port_jumbo_config = mv88e6165_port_jumbo_config,
3605 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3606 .port_pause_config = mv88e6097_port_pause_config,
3607 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3608 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3609 .stats_get_strings = mv88e6320_stats_get_strings,
3610 .stats_get_stats = mv88e6320_stats_get_stats,
3611 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3612 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3613 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3614 .reset = mv88e6352_g1_reset,
3615 };
3616
3617 static const struct mv88e6xxx_ops mv88e6321_ops = {
3618 /* MV88E6XXX_FAMILY_6321 */
3619 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3620 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3621 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3622 .phy_read = mv88e6xxx_g2_smi_phy_read,
3623 .phy_write = mv88e6xxx_g2_smi_phy_write,
3624 .port_set_link = mv88e6xxx_port_set_link,
3625 .port_set_duplex = mv88e6xxx_port_set_duplex,
3626 .port_set_speed = mv88e6185_port_set_speed,
3627 .port_tag_remap = mv88e6095_port_tag_remap,
3628 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3629 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3630 .port_set_ether_type = mv88e6351_port_set_ether_type,
3631 .port_jumbo_config = mv88e6165_port_jumbo_config,
3632 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3633 .port_pause_config = mv88e6097_port_pause_config,
3634 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3635 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3636 .stats_get_strings = mv88e6320_stats_get_strings,
3637 .stats_get_stats = mv88e6320_stats_get_stats,
3638 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3639 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3640 .reset = mv88e6352_g1_reset,
3641 };
3642
3643 static const struct mv88e6xxx_ops mv88e6350_ops = {
3644 /* MV88E6XXX_FAMILY_6351 */
3645 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3646 .phy_read = mv88e6xxx_g2_smi_phy_read,
3647 .phy_write = mv88e6xxx_g2_smi_phy_write,
3648 .port_set_link = mv88e6xxx_port_set_link,
3649 .port_set_duplex = mv88e6xxx_port_set_duplex,
3650 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3651 .port_set_speed = mv88e6185_port_set_speed,
3652 .port_tag_remap = mv88e6095_port_tag_remap,
3653 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3654 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3655 .port_set_ether_type = mv88e6351_port_set_ether_type,
3656 .port_jumbo_config = mv88e6165_port_jumbo_config,
3657 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3658 .port_pause_config = mv88e6097_port_pause_config,
3659 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3660 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3661 .stats_get_strings = mv88e6095_stats_get_strings,
3662 .stats_get_stats = mv88e6095_stats_get_stats,
3663 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3664 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3665 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3666 .reset = mv88e6352_g1_reset,
3667 };
3668
3669 static const struct mv88e6xxx_ops mv88e6351_ops = {
3670 /* MV88E6XXX_FAMILY_6351 */
3671 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3672 .phy_read = mv88e6xxx_g2_smi_phy_read,
3673 .phy_write = mv88e6xxx_g2_smi_phy_write,
3674 .port_set_link = mv88e6xxx_port_set_link,
3675 .port_set_duplex = mv88e6xxx_port_set_duplex,
3676 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3677 .port_set_speed = mv88e6185_port_set_speed,
3678 .port_tag_remap = mv88e6095_port_tag_remap,
3679 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3680 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3681 .port_set_ether_type = mv88e6351_port_set_ether_type,
3682 .port_jumbo_config = mv88e6165_port_jumbo_config,
3683 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3684 .port_pause_config = mv88e6097_port_pause_config,
3685 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3686 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3687 .stats_get_strings = mv88e6095_stats_get_strings,
3688 .stats_get_stats = mv88e6095_stats_get_stats,
3689 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3690 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3691 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3692 .reset = mv88e6352_g1_reset,
3693 };
3694
3695 static const struct mv88e6xxx_ops mv88e6352_ops = {
3696 /* MV88E6XXX_FAMILY_6352 */
3697 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
3698 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
3699 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3700 .phy_read = mv88e6xxx_g2_smi_phy_read,
3701 .phy_write = mv88e6xxx_g2_smi_phy_write,
3702 .port_set_link = mv88e6xxx_port_set_link,
3703 .port_set_duplex = mv88e6xxx_port_set_duplex,
3704 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3705 .port_set_speed = mv88e6352_port_set_speed,
3706 .port_tag_remap = mv88e6095_port_tag_remap,
3707 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3708 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3709 .port_set_ether_type = mv88e6351_port_set_ether_type,
3710 .port_jumbo_config = mv88e6165_port_jumbo_config,
3711 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3712 .port_pause_config = mv88e6097_port_pause_config,
3713 .stats_snapshot = mv88e6320_g1_stats_snapshot,
3714 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
3715 .stats_get_strings = mv88e6095_stats_get_strings,
3716 .stats_get_stats = mv88e6095_stats_get_stats,
3717 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
3718 .g1_set_egress_port = mv88e6095_g1_set_egress_port,
3719 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
3720 .reset = mv88e6352_g1_reset,
3721 };
3722
3723 static const struct mv88e6xxx_ops mv88e6390_ops = {
3724 /* MV88E6XXX_FAMILY_6390 */
3725 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3726 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3727 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3728 .phy_read = mv88e6xxx_g2_smi_phy_read,
3729 .phy_write = mv88e6xxx_g2_smi_phy_write,
3730 .port_set_link = mv88e6xxx_port_set_link,
3731 .port_set_duplex = mv88e6xxx_port_set_duplex,
3732 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3733 .port_set_speed = mv88e6390_port_set_speed,
3734 .port_tag_remap = mv88e6390_port_tag_remap,
3735 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3736 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3737 .port_set_ether_type = mv88e6351_port_set_ether_type,
3738 .port_jumbo_config = mv88e6165_port_jumbo_config,
3739 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3740 .port_pause_config = mv88e6390_port_pause_config,
3741 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3742 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3743 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3744 .stats_get_strings = mv88e6320_stats_get_strings,
3745 .stats_get_stats = mv88e6390_stats_get_stats,
3746 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3747 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3748 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3749 .reset = mv88e6352_g1_reset,
3750 };
3751
3752 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3753 /* MV88E6XXX_FAMILY_6390 */
3754 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3755 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3756 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3757 .phy_read = mv88e6xxx_g2_smi_phy_read,
3758 .phy_write = mv88e6xxx_g2_smi_phy_write,
3759 .port_set_link = mv88e6xxx_port_set_link,
3760 .port_set_duplex = mv88e6xxx_port_set_duplex,
3761 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3762 .port_set_speed = mv88e6390x_port_set_speed,
3763 .port_tag_remap = mv88e6390_port_tag_remap,
3764 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3765 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3766 .port_set_ether_type = mv88e6351_port_set_ether_type,
3767 .port_jumbo_config = mv88e6165_port_jumbo_config,
3768 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3769 .port_pause_config = mv88e6390_port_pause_config,
3770 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3771 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3772 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3773 .stats_get_strings = mv88e6320_stats_get_strings,
3774 .stats_get_stats = mv88e6390_stats_get_stats,
3775 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3776 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3777 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3778 .reset = mv88e6352_g1_reset,
3779 };
3780
3781 static const struct mv88e6xxx_ops mv88e6391_ops = {
3782 /* MV88E6XXX_FAMILY_6390 */
3783 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
3784 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
3785 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3786 .phy_read = mv88e6xxx_g2_smi_phy_read,
3787 .phy_write = mv88e6xxx_g2_smi_phy_write,
3788 .port_set_link = mv88e6xxx_port_set_link,
3789 .port_set_duplex = mv88e6xxx_port_set_duplex,
3790 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3791 .port_set_speed = mv88e6390_port_set_speed,
3792 .port_tag_remap = mv88e6390_port_tag_remap,
3793 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
3794 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
3795 .port_set_ether_type = mv88e6351_port_set_ether_type,
3796 .port_pause_config = mv88e6390_port_pause_config,
3797 .stats_snapshot = mv88e6390_g1_stats_snapshot,
3798 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3799 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
3800 .stats_get_strings = mv88e6320_stats_get_strings,
3801 .stats_get_stats = mv88e6390_stats_get_stats,
3802 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
3803 .g1_set_egress_port = mv88e6390_g1_set_egress_port,
3804 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3805 .reset = mv88e6352_g1_reset,
3806 };
3807
3808 static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip,
3809 const struct mv88e6xxx_ops *ops)
3810 {
3811 if (!ops->port_set_frame_mode) {
3812 dev_err(chip->dev, "Missing port_set_frame_mode");
3813 return -EINVAL;
3814 }
3815
3816 if (!ops->port_set_egress_unknowns) {
3817 dev_err(chip->dev, "Missing port_set_egress_mode");
3818 return -EINVAL;
3819 }
3820
3821 return 0;
3822 }
3823
3824 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3825 [MV88E6085] = {
3826 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3827 .family = MV88E6XXX_FAMILY_6097,
3828 .name = "Marvell 88E6085",
3829 .num_databases = 4096,
3830 .num_ports = 10,
3831 .port_base_addr = 0x10,
3832 .global1_addr = 0x1b,
3833 .age_time_coeff = 15000,
3834 .g1_irqs = 8,
3835 .tag_protocol = DSA_TAG_PROTO_DSA,
3836 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3837 .ops = &mv88e6085_ops,
3838 },
3839
3840 [MV88E6095] = {
3841 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3842 .family = MV88E6XXX_FAMILY_6095,
3843 .name = "Marvell 88E6095/88E6095F",
3844 .num_databases = 256,
3845 .num_ports = 11,
3846 .port_base_addr = 0x10,
3847 .global1_addr = 0x1b,
3848 .age_time_coeff = 15000,
3849 .g1_irqs = 8,
3850 .tag_protocol = DSA_TAG_PROTO_DSA,
3851 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3852 .ops = &mv88e6095_ops,
3853 },
3854
3855 [MV88E6097] = {
3856 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097,
3857 .family = MV88E6XXX_FAMILY_6097,
3858 .name = "Marvell 88E6097/88E6097F",
3859 .num_databases = 4096,
3860 .num_ports = 11,
3861 .port_base_addr = 0x10,
3862 .global1_addr = 0x1b,
3863 .age_time_coeff = 15000,
3864 .g1_irqs = 8,
3865 .tag_protocol = DSA_TAG_PROTO_EDSA,
3866 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3867 .ops = &mv88e6097_ops,
3868 },
3869
3870 [MV88E6123] = {
3871 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3872 .family = MV88E6XXX_FAMILY_6165,
3873 .name = "Marvell 88E6123",
3874 .num_databases = 4096,
3875 .num_ports = 3,
3876 .port_base_addr = 0x10,
3877 .global1_addr = 0x1b,
3878 .age_time_coeff = 15000,
3879 .g1_irqs = 9,
3880 .tag_protocol = DSA_TAG_PROTO_DSA,
3881 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3882 .ops = &mv88e6123_ops,
3883 },
3884
3885 [MV88E6131] = {
3886 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3887 .family = MV88E6XXX_FAMILY_6185,
3888 .name = "Marvell 88E6131",
3889 .num_databases = 256,
3890 .num_ports = 8,
3891 .port_base_addr = 0x10,
3892 .global1_addr = 0x1b,
3893 .age_time_coeff = 15000,
3894 .g1_irqs = 9,
3895 .tag_protocol = DSA_TAG_PROTO_DSA,
3896 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3897 .ops = &mv88e6131_ops,
3898 },
3899
3900 [MV88E6161] = {
3901 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3902 .family = MV88E6XXX_FAMILY_6165,
3903 .name = "Marvell 88E6161",
3904 .num_databases = 4096,
3905 .num_ports = 6,
3906 .port_base_addr = 0x10,
3907 .global1_addr = 0x1b,
3908 .age_time_coeff = 15000,
3909 .g1_irqs = 9,
3910 .tag_protocol = DSA_TAG_PROTO_DSA,
3911 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3912 .ops = &mv88e6161_ops,
3913 },
3914
3915 [MV88E6165] = {
3916 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3917 .family = MV88E6XXX_FAMILY_6165,
3918 .name = "Marvell 88E6165",
3919 .num_databases = 4096,
3920 .num_ports = 6,
3921 .port_base_addr = 0x10,
3922 .global1_addr = 0x1b,
3923 .age_time_coeff = 15000,
3924 .g1_irqs = 9,
3925 .tag_protocol = DSA_TAG_PROTO_DSA,
3926 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3927 .ops = &mv88e6165_ops,
3928 },
3929
3930 [MV88E6171] = {
3931 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3932 .family = MV88E6XXX_FAMILY_6351,
3933 .name = "Marvell 88E6171",
3934 .num_databases = 4096,
3935 .num_ports = 7,
3936 .port_base_addr = 0x10,
3937 .global1_addr = 0x1b,
3938 .age_time_coeff = 15000,
3939 .g1_irqs = 9,
3940 .tag_protocol = DSA_TAG_PROTO_EDSA,
3941 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3942 .ops = &mv88e6171_ops,
3943 },
3944
3945 [MV88E6172] = {
3946 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3947 .family = MV88E6XXX_FAMILY_6352,
3948 .name = "Marvell 88E6172",
3949 .num_databases = 4096,
3950 .num_ports = 7,
3951 .port_base_addr = 0x10,
3952 .global1_addr = 0x1b,
3953 .age_time_coeff = 15000,
3954 .g1_irqs = 9,
3955 .tag_protocol = DSA_TAG_PROTO_EDSA,
3956 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3957 .ops = &mv88e6172_ops,
3958 },
3959
3960 [MV88E6175] = {
3961 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3962 .family = MV88E6XXX_FAMILY_6351,
3963 .name = "Marvell 88E6175",
3964 .num_databases = 4096,
3965 .num_ports = 7,
3966 .port_base_addr = 0x10,
3967 .global1_addr = 0x1b,
3968 .age_time_coeff = 15000,
3969 .g1_irqs = 9,
3970 .tag_protocol = DSA_TAG_PROTO_EDSA,
3971 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3972 .ops = &mv88e6175_ops,
3973 },
3974
3975 [MV88E6176] = {
3976 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3977 .family = MV88E6XXX_FAMILY_6352,
3978 .name = "Marvell 88E6176",
3979 .num_databases = 4096,
3980 .num_ports = 7,
3981 .port_base_addr = 0x10,
3982 .global1_addr = 0x1b,
3983 .age_time_coeff = 15000,
3984 .g1_irqs = 9,
3985 .tag_protocol = DSA_TAG_PROTO_EDSA,
3986 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3987 .ops = &mv88e6176_ops,
3988 },
3989
3990 [MV88E6185] = {
3991 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3992 .family = MV88E6XXX_FAMILY_6185,
3993 .name = "Marvell 88E6185",
3994 .num_databases = 256,
3995 .num_ports = 10,
3996 .port_base_addr = 0x10,
3997 .global1_addr = 0x1b,
3998 .age_time_coeff = 15000,
3999 .g1_irqs = 8,
4000 .tag_protocol = DSA_TAG_PROTO_EDSA,
4001 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
4002 .ops = &mv88e6185_ops,
4003 },
4004
4005 [MV88E6190] = {
4006 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190,
4007 .family = MV88E6XXX_FAMILY_6390,
4008 .name = "Marvell 88E6190",
4009 .num_databases = 4096,
4010 .num_ports = 11, /* 10 + Z80 */
4011 .port_base_addr = 0x0,
4012 .global1_addr = 0x1b,
4013 .tag_protocol = DSA_TAG_PROTO_DSA,
4014 .age_time_coeff = 15000,
4015 .g1_irqs = 9,
4016 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4017 .ops = &mv88e6190_ops,
4018 },
4019
4020 [MV88E6190X] = {
4021 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X,
4022 .family = MV88E6XXX_FAMILY_6390,
4023 .name = "Marvell 88E6190X",
4024 .num_databases = 4096,
4025 .num_ports = 11, /* 10 + Z80 */
4026 .port_base_addr = 0x0,
4027 .global1_addr = 0x1b,
4028 .age_time_coeff = 15000,
4029 .g1_irqs = 9,
4030 .tag_protocol = DSA_TAG_PROTO_DSA,
4031 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4032 .ops = &mv88e6190x_ops,
4033 },
4034
4035 [MV88E6191] = {
4036 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191,
4037 .family = MV88E6XXX_FAMILY_6390,
4038 .name = "Marvell 88E6191",
4039 .num_databases = 4096,
4040 .num_ports = 11, /* 10 + Z80 */
4041 .port_base_addr = 0x0,
4042 .global1_addr = 0x1b,
4043 .age_time_coeff = 15000,
4044 .g1_irqs = 9,
4045 .tag_protocol = DSA_TAG_PROTO_DSA,
4046 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4047 .ops = &mv88e6391_ops,
4048 },
4049
4050 [MV88E6240] = {
4051 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
4052 .family = MV88E6XXX_FAMILY_6352,
4053 .name = "Marvell 88E6240",
4054 .num_databases = 4096,
4055 .num_ports = 7,
4056 .port_base_addr = 0x10,
4057 .global1_addr = 0x1b,
4058 .age_time_coeff = 15000,
4059 .g1_irqs = 9,
4060 .tag_protocol = DSA_TAG_PROTO_EDSA,
4061 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
4062 .ops = &mv88e6240_ops,
4063 },
4064
4065 [MV88E6290] = {
4066 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290,
4067 .family = MV88E6XXX_FAMILY_6390,
4068 .name = "Marvell 88E6290",
4069 .num_databases = 4096,
4070 .num_ports = 11, /* 10 + Z80 */
4071 .port_base_addr = 0x0,
4072 .global1_addr = 0x1b,
4073 .age_time_coeff = 15000,
4074 .g1_irqs = 9,
4075 .tag_protocol = DSA_TAG_PROTO_DSA,
4076 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4077 .ops = &mv88e6290_ops,
4078 },
4079
4080 [MV88E6320] = {
4081 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
4082 .family = MV88E6XXX_FAMILY_6320,
4083 .name = "Marvell 88E6320",
4084 .num_databases = 4096,
4085 .num_ports = 7,
4086 .port_base_addr = 0x10,
4087 .global1_addr = 0x1b,
4088 .age_time_coeff = 15000,
4089 .g1_irqs = 8,
4090 .tag_protocol = DSA_TAG_PROTO_EDSA,
4091 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
4092 .ops = &mv88e6320_ops,
4093 },
4094
4095 [MV88E6321] = {
4096 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
4097 .family = MV88E6XXX_FAMILY_6320,
4098 .name = "Marvell 88E6321",
4099 .num_databases = 4096,
4100 .num_ports = 7,
4101 .port_base_addr = 0x10,
4102 .global1_addr = 0x1b,
4103 .age_time_coeff = 15000,
4104 .g1_irqs = 8,
4105 .tag_protocol = DSA_TAG_PROTO_EDSA,
4106 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
4107 .ops = &mv88e6321_ops,
4108 },
4109
4110 [MV88E6350] = {
4111 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
4112 .family = MV88E6XXX_FAMILY_6351,
4113 .name = "Marvell 88E6350",
4114 .num_databases = 4096,
4115 .num_ports = 7,
4116 .port_base_addr = 0x10,
4117 .global1_addr = 0x1b,
4118 .age_time_coeff = 15000,
4119 .g1_irqs = 9,
4120 .tag_protocol = DSA_TAG_PROTO_EDSA,
4121 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
4122 .ops = &mv88e6350_ops,
4123 },
4124
4125 [MV88E6351] = {
4126 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
4127 .family = MV88E6XXX_FAMILY_6351,
4128 .name = "Marvell 88E6351",
4129 .num_databases = 4096,
4130 .num_ports = 7,
4131 .port_base_addr = 0x10,
4132 .global1_addr = 0x1b,
4133 .age_time_coeff = 15000,
4134 .g1_irqs = 9,
4135 .tag_protocol = DSA_TAG_PROTO_EDSA,
4136 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
4137 .ops = &mv88e6351_ops,
4138 },
4139
4140 [MV88E6352] = {
4141 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
4142 .family = MV88E6XXX_FAMILY_6352,
4143 .name = "Marvell 88E6352",
4144 .num_databases = 4096,
4145 .num_ports = 7,
4146 .port_base_addr = 0x10,
4147 .global1_addr = 0x1b,
4148 .age_time_coeff = 15000,
4149 .g1_irqs = 9,
4150 .tag_protocol = DSA_TAG_PROTO_EDSA,
4151 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
4152 .ops = &mv88e6352_ops,
4153 },
4154 [MV88E6390] = {
4155 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390,
4156 .family = MV88E6XXX_FAMILY_6390,
4157 .name = "Marvell 88E6390",
4158 .num_databases = 4096,
4159 .num_ports = 11, /* 10 + Z80 */
4160 .port_base_addr = 0x0,
4161 .global1_addr = 0x1b,
4162 .age_time_coeff = 15000,
4163 .g1_irqs = 9,
4164 .tag_protocol = DSA_TAG_PROTO_DSA,
4165 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4166 .ops = &mv88e6390_ops,
4167 },
4168 [MV88E6390X] = {
4169 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X,
4170 .family = MV88E6XXX_FAMILY_6390,
4171 .name = "Marvell 88E6390X",
4172 .num_databases = 4096,
4173 .num_ports = 11, /* 10 + Z80 */
4174 .port_base_addr = 0x0,
4175 .global1_addr = 0x1b,
4176 .age_time_coeff = 15000,
4177 .g1_irqs = 9,
4178 .tag_protocol = DSA_TAG_PROTO_DSA,
4179 .flags = MV88E6XXX_FLAGS_FAMILY_6390,
4180 .ops = &mv88e6390x_ops,
4181 },
4182 };
4183
4184 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4185 {
4186 int i;
4187
4188 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4189 if (mv88e6xxx_table[i].prod_num == prod_num)
4190 return &mv88e6xxx_table[i];
4191
4192 return NULL;
4193 }
4194
4195 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4196 {
4197 const struct mv88e6xxx_info *info;
4198 unsigned int prod_num, rev;
4199 u16 id;
4200 int err;
4201
4202 mutex_lock(&chip->reg_lock);
4203 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
4204 mutex_unlock(&chip->reg_lock);
4205 if (err)
4206 return err;
4207
4208 prod_num = (id & 0xfff0) >> 4;
4209 rev = id & 0x000f;
4210
4211 info = mv88e6xxx_lookup_info(prod_num);
4212 if (!info)
4213 return -ENODEV;
4214
4215 /* Update the compatible info with the probed one */
4216 chip->info = info;
4217
4218 err = mv88e6xxx_g2_require(chip);
4219 if (err)
4220 return err;
4221
4222 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4223 chip->info->prod_num, chip->info->name, rev);
4224
4225 return 0;
4226 }
4227
4228 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4229 {
4230 struct mv88e6xxx_chip *chip;
4231
4232 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4233 if (!chip)
4234 return NULL;
4235
4236 chip->dev = dev;
4237
4238 mutex_init(&chip->reg_lock);
4239
4240 return chip;
4241 }
4242
4243 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
4244 {
4245 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
4246 mv88e6xxx_ppu_state_init(chip);
4247 }
4248
4249 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
4250 {
4251 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
4252 mv88e6xxx_ppu_state_destroy(chip);
4253 }
4254
4255 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4256 struct mii_bus *bus, int sw_addr)
4257 {
4258 if (sw_addr == 0)
4259 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4260 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
4261 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4262 else
4263 return -EINVAL;
4264
4265 chip->bus = bus;
4266 chip->sw_addr = sw_addr;
4267
4268 return 0;
4269 }
4270
4271 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
4272 {
4273 struct mv88e6xxx_chip *chip = ds->priv;
4274
4275 return chip->info->tag_protocol;
4276 }
4277
4278 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4279 struct device *host_dev, int sw_addr,
4280 void **priv)
4281 {
4282 struct mv88e6xxx_chip *chip;
4283 struct mii_bus *bus;
4284 int err;
4285
4286 bus = dsa_host_dev_to_mii_bus(host_dev);
4287 if (!bus)
4288 return NULL;
4289
4290 chip = mv88e6xxx_alloc_chip(dsa_dev);
4291 if (!chip)
4292 return NULL;
4293
4294 /* Legacy SMI probing will only support chips similar to 88E6085 */
4295 chip->info = &mv88e6xxx_table[MV88E6085];
4296
4297 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4298 if (err)
4299 goto free;
4300
4301 err = mv88e6xxx_detect(chip);
4302 if (err)
4303 goto free;
4304
4305 mutex_lock(&chip->reg_lock);
4306 err = mv88e6xxx_switch_reset(chip);
4307 mutex_unlock(&chip->reg_lock);
4308 if (err)
4309 goto free;
4310
4311 mv88e6xxx_phy_init(chip);
4312
4313 err = mv88e6xxx_mdio_register(chip, NULL);
4314 if (err)
4315 goto free;
4316
4317 *priv = chip;
4318
4319 return chip->info->name;
4320 free:
4321 devm_kfree(dsa_dev, chip);
4322
4323 return NULL;
4324 }
4325
4326 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4327 const struct switchdev_obj_port_mdb *mdb,
4328 struct switchdev_trans *trans)
4329 {
4330 /* We don't need any dynamic resource from the kernel (yet),
4331 * so skip the prepare phase.
4332 */
4333
4334 return 0;
4335 }
4336
4337 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4338 const struct switchdev_obj_port_mdb *mdb,
4339 struct switchdev_trans *trans)
4340 {
4341 struct mv88e6xxx_chip *chip = ds->priv;
4342
4343 mutex_lock(&chip->reg_lock);
4344 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4345 GLOBAL_ATU_DATA_STATE_MC_STATIC))
4346 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
4347 mutex_unlock(&chip->reg_lock);
4348 }
4349
4350 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4351 const struct switchdev_obj_port_mdb *mdb)
4352 {
4353 struct mv88e6xxx_chip *chip = ds->priv;
4354 int err;
4355
4356 mutex_lock(&chip->reg_lock);
4357 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4358 GLOBAL_ATU_DATA_STATE_UNUSED);
4359 mutex_unlock(&chip->reg_lock);
4360
4361 return err;
4362 }
4363
4364 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
4365 struct switchdev_obj_port_mdb *mdb,
4366 int (*cb)(struct switchdev_obj *obj))
4367 {
4368 struct mv88e6xxx_chip *chip = ds->priv;
4369 int err;
4370
4371 mutex_lock(&chip->reg_lock);
4372 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
4373 mutex_unlock(&chip->reg_lock);
4374
4375 return err;
4376 }
4377
4378 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4379 .probe = mv88e6xxx_drv_probe,
4380 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
4381 .setup = mv88e6xxx_setup,
4382 .set_addr = mv88e6xxx_set_addr,
4383 .adjust_link = mv88e6xxx_adjust_link,
4384 .get_strings = mv88e6xxx_get_strings,
4385 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
4386 .get_sset_count = mv88e6xxx_get_sset_count,
4387 .set_eee = mv88e6xxx_set_eee,
4388 .get_eee = mv88e6xxx_get_eee,
4389 #ifdef CONFIG_NET_DSA_HWMON
4390 .get_temp = mv88e6xxx_get_temp,
4391 .get_temp_limit = mv88e6xxx_get_temp_limit,
4392 .set_temp_limit = mv88e6xxx_set_temp_limit,
4393 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
4394 #endif
4395 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
4396 .get_eeprom = mv88e6xxx_get_eeprom,
4397 .set_eeprom = mv88e6xxx_set_eeprom,
4398 .get_regs_len = mv88e6xxx_get_regs_len,
4399 .get_regs = mv88e6xxx_get_regs,
4400 .set_ageing_time = mv88e6xxx_set_ageing_time,
4401 .port_bridge_join = mv88e6xxx_port_bridge_join,
4402 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
4403 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
4404 .port_fast_age = mv88e6xxx_port_fast_age,
4405 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
4406 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
4407 .port_vlan_add = mv88e6xxx_port_vlan_add,
4408 .port_vlan_del = mv88e6xxx_port_vlan_del,
4409 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4410 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4411 .port_fdb_add = mv88e6xxx_port_fdb_add,
4412 .port_fdb_del = mv88e6xxx_port_fdb_del,
4413 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4414 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
4415 .port_mdb_add = mv88e6xxx_port_mdb_add,
4416 .port_mdb_del = mv88e6xxx_port_mdb_del,
4417 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
4418 };
4419
4420 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4421 .ops = &mv88e6xxx_switch_ops,
4422 };
4423
4424 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4425 struct device_node *np)
4426 {
4427 struct device *dev = chip->dev;
4428 struct dsa_switch *ds;
4429
4430 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4431 if (!ds)
4432 return -ENOMEM;
4433
4434 ds->dev = dev;
4435 ds->priv = chip;
4436 ds->ops = &mv88e6xxx_switch_ops;
4437
4438 dev_set_drvdata(dev, ds);
4439
4440 return dsa_register_switch(ds, np);
4441 }
4442
4443 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4444 {
4445 dsa_unregister_switch(chip->ds);
4446 }
4447
4448 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4449 {
4450 struct device *dev = &mdiodev->dev;
4451 struct device_node *np = dev->of_node;
4452 const struct mv88e6xxx_info *compat_info;
4453 struct mv88e6xxx_chip *chip;
4454 u32 eeprom_len;
4455 int err;
4456
4457 compat_info = of_device_get_match_data(dev);
4458 if (!compat_info)
4459 return -EINVAL;
4460
4461 chip = mv88e6xxx_alloc_chip(dev);
4462 if (!chip)
4463 return -ENOMEM;
4464
4465 chip->info = compat_info;
4466
4467 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops);
4468 if (err)
4469 return err;
4470
4471 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4472 if (err)
4473 return err;
4474
4475 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4476 if (IS_ERR(chip->reset))
4477 return PTR_ERR(chip->reset);
4478
4479 err = mv88e6xxx_detect(chip);
4480 if (err)
4481 return err;
4482
4483 mv88e6xxx_phy_init(chip);
4484
4485 if (chip->info->ops->get_eeprom &&
4486 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4487 chip->eeprom_len = eeprom_len;
4488
4489 mutex_lock(&chip->reg_lock);
4490 err = mv88e6xxx_switch_reset(chip);
4491 mutex_unlock(&chip->reg_lock);
4492 if (err)
4493 goto out;
4494
4495 chip->irq = of_irq_get(np, 0);
4496 if (chip->irq == -EPROBE_DEFER) {
4497 err = chip->irq;
4498 goto out;
4499 }
4500
4501 if (chip->irq > 0) {
4502 /* Has to be performed before the MDIO bus is created,
4503 * because the PHYs will link there interrupts to these
4504 * interrupt controllers
4505 */
4506 mutex_lock(&chip->reg_lock);
4507 err = mv88e6xxx_g1_irq_setup(chip);
4508 mutex_unlock(&chip->reg_lock);
4509
4510 if (err)
4511 goto out;
4512
4513 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) {
4514 err = mv88e6xxx_g2_irq_setup(chip);
4515 if (err)
4516 goto out_g1_irq;
4517 }
4518 }
4519
4520 err = mv88e6xxx_mdio_register(chip, np);
4521 if (err)
4522 goto out_g2_irq;
4523
4524 err = mv88e6xxx_register_switch(chip, np);
4525 if (err)
4526 goto out_mdio;
4527
4528 return 0;
4529
4530 out_mdio:
4531 mv88e6xxx_mdio_unregister(chip);
4532 out_g2_irq:
4533 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0)
4534 mv88e6xxx_g2_irq_free(chip);
4535 out_g1_irq:
4536 if (chip->irq > 0) {
4537 mutex_lock(&chip->reg_lock);
4538 mv88e6xxx_g1_irq_free(chip);
4539 mutex_unlock(&chip->reg_lock);
4540 }
4541 out:
4542 return err;
4543 }
4544
4545 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4546 {
4547 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4548 struct mv88e6xxx_chip *chip = ds->priv;
4549
4550 mv88e6xxx_phy_destroy(chip);
4551 mv88e6xxx_unregister_switch(chip);
4552 mv88e6xxx_mdio_unregister(chip);
4553
4554 if (chip->irq > 0) {
4555 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT))
4556 mv88e6xxx_g2_irq_free(chip);
4557 mv88e6xxx_g1_irq_free(chip);
4558 }
4559 }
4560
4561 static const struct of_device_id mv88e6xxx_of_match[] = {
4562 {
4563 .compatible = "marvell,mv88e6085",
4564 .data = &mv88e6xxx_table[MV88E6085],
4565 },
4566 {
4567 .compatible = "marvell,mv88e6190",
4568 .data = &mv88e6xxx_table[MV88E6190],
4569 },
4570 { /* sentinel */ },
4571 };
4572
4573 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4574
4575 static struct mdio_driver mv88e6xxx_driver = {
4576 .probe = mv88e6xxx_probe,
4577 .remove = mv88e6xxx_remove,
4578 .mdiodrv.driver = {
4579 .name = "mv88e6085",
4580 .of_match_table = mv88e6xxx_of_match,
4581 },
4582 };
4583
4584 static int __init mv88e6xxx_init(void)
4585 {
4586 register_switch_driver(&mv88e6xxx_switch_drv);
4587 return mdio_driver_register(&mv88e6xxx_driver);
4588 }
4589 module_init(mv88e6xxx_init);
4590
4591 static void __exit mv88e6xxx_cleanup(void)
4592 {
4593 mdio_driver_unregister(&mv88e6xxx_driver);
4594 unregister_switch_driver(&mv88e6xxx_switch_drv);
4595 }
4596 module_exit(mv88e6xxx_cleanup);
4597
4598 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4599 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4600 MODULE_LICENSE("GPL");
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