2 * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
14 #include <linux/if_vlan.h>
15 #include <linux/gpio/consumer.h>
18 #define UINT64_MAX (u64)(~((u64)0))
22 #define SMI_CMD_BUSY BIT(15)
23 #define SMI_CMD_CLAUSE_22 BIT(12)
24 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
25 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
26 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
27 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
28 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
29 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
32 /* Fiber/SERDES Registers are located at SMI address F, page 1 */
33 #define REG_FIBER_SERDES 0x0f
34 #define PAGE_FIBER_SERDES 0x01
36 #define REG_PORT(p) (0x10 + (p))
37 #define PORT_STATUS 0x00
38 #define PORT_STATUS_PAUSE_EN BIT(15)
39 #define PORT_STATUS_MY_PAUSE BIT(14)
40 #define PORT_STATUS_HD_FLOW BIT(13)
41 #define PORT_STATUS_PHY_DETECT BIT(12)
42 #define PORT_STATUS_LINK BIT(11)
43 #define PORT_STATUS_DUPLEX BIT(10)
44 #define PORT_STATUS_SPEED_MASK 0x0300
45 #define PORT_STATUS_SPEED_10 0x0000
46 #define PORT_STATUS_SPEED_100 0x0100
47 #define PORT_STATUS_SPEED_1000 0x0200
48 #define PORT_STATUS_EEE BIT(6) /* 6352 */
49 #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
50 #define PORT_STATUS_MGMII BIT(6) /* 6185 */
51 #define PORT_STATUS_TX_PAUSED BIT(5)
52 #define PORT_STATUS_FLOW_CTRL BIT(4)
53 #define PORT_STATUS_CMODE_MASK 0x0f
54 #define PORT_STATUS_CMODE_100BASE_X 0x8
55 #define PORT_STATUS_CMODE_1000BASE_X 0x9
56 #define PORT_STATUS_CMODE_SGMII 0xa
57 #define PORT_PCS_CTRL 0x01
58 #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
59 #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
60 #define PORT_PCS_CTRL_FC BIT(7)
61 #define PORT_PCS_CTRL_FORCE_FC BIT(6)
62 #define PORT_PCS_CTRL_LINK_UP BIT(5)
63 #define PORT_PCS_CTRL_FORCE_LINK BIT(4)
64 #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3)
65 #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2)
66 #define PORT_PCS_CTRL_10 0x00
67 #define PORT_PCS_CTRL_100 0x01
68 #define PORT_PCS_CTRL_1000 0x02
69 #define PORT_PCS_CTRL_UNFORCED 0x03
70 #define PORT_PAUSE_CTRL 0x02
71 #define PORT_SWITCH_ID 0x03
72 #define PORT_SWITCH_ID_PROD_NUM_6085 0x04a
73 #define PORT_SWITCH_ID_PROD_NUM_6095 0x095
74 #define PORT_SWITCH_ID_PROD_NUM_6131 0x106
75 #define PORT_SWITCH_ID_PROD_NUM_6320 0x115
76 #define PORT_SWITCH_ID_PROD_NUM_6123 0x121
77 #define PORT_SWITCH_ID_PROD_NUM_6161 0x161
78 #define PORT_SWITCH_ID_PROD_NUM_6165 0x165
79 #define PORT_SWITCH_ID_PROD_NUM_6171 0x171
80 #define PORT_SWITCH_ID_PROD_NUM_6172 0x172
81 #define PORT_SWITCH_ID_PROD_NUM_6175 0x175
82 #define PORT_SWITCH_ID_PROD_NUM_6176 0x176
83 #define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7
84 #define PORT_SWITCH_ID_PROD_NUM_6240 0x240
85 #define PORT_SWITCH_ID_PROD_NUM_6321 0x310
86 #define PORT_SWITCH_ID_PROD_NUM_6352 0x352
87 #define PORT_SWITCH_ID_PROD_NUM_6350 0x371
88 #define PORT_SWITCH_ID_PROD_NUM_6351 0x375
89 #define PORT_CONTROL 0x04
90 #define PORT_CONTROL_USE_CORE_TAG BIT(15)
91 #define PORT_CONTROL_DROP_ON_LOCK BIT(14)
92 #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12)
93 #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12)
94 #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12)
95 #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12)
96 #define PORT_CONTROL_HEADER BIT(11)
97 #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10)
98 #define PORT_CONTROL_DOUBLE_TAG BIT(9)
99 #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8)
100 #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8)
101 #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8)
102 #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8)
103 #define PORT_CONTROL_DSA_TAG BIT(8)
104 #define PORT_CONTROL_VLAN_TUNNEL BIT(7)
105 #define PORT_CONTROL_TAG_IF_BOTH BIT(6)
106 #define PORT_CONTROL_USE_IP BIT(5)
107 #define PORT_CONTROL_USE_TAG BIT(4)
108 #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
109 #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2)
110 #define PORT_CONTROL_STATE_MASK 0x03
111 #define PORT_CONTROL_STATE_DISABLED 0x00
112 #define PORT_CONTROL_STATE_BLOCKING 0x01
113 #define PORT_CONTROL_STATE_LEARNING 0x02
114 #define PORT_CONTROL_STATE_FORWARDING 0x03
115 #define PORT_CONTROL_1 0x05
116 #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0)
117 #define PORT_BASE_VLAN 0x06
118 #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12)
119 #define PORT_DEFAULT_VLAN 0x07
120 #define PORT_DEFAULT_VLAN_MASK 0xfff
121 #define PORT_CONTROL_2 0x08
122 #define PORT_CONTROL_2_IGNORE_FCS BIT(15)
123 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
124 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
125 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
126 #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
127 #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
128 #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
129 #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10)
130 #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10)
131 #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10)
132 #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10)
133 #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10)
134 #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9)
135 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
136 #define PORT_CONTROL_2_MAP_DA BIT(7)
137 #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6)
138 #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6)
139 #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5)
140 #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4)
141 #define PORT_RATE_CONTROL 0x09
142 #define PORT_RATE_CONTROL_2 0x0a
143 #define PORT_ASSOC_VECTOR 0x0b
144 #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15)
145 #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14)
146 #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13)
147 #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12)
148 #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11)
149 #define PORT_ATU_CONTROL 0x0c
150 #define PORT_PRI_OVERRIDE 0x0d
151 #define PORT_ETH_TYPE 0x0f
152 #define PORT_IN_DISCARD_LO 0x10
153 #define PORT_IN_DISCARD_HI 0x11
154 #define PORT_IN_FILTERED 0x12
155 #define PORT_OUT_FILTERED 0x13
156 #define PORT_TAG_REGMAP_0123 0x18
157 #define PORT_TAG_REGMAP_4567 0x19
159 #define REG_GLOBAL 0x1b
160 #define GLOBAL_STATUS 0x00
161 #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
162 /* Two bits for 6165, 6185 etc */
163 #define GLOBAL_STATUS_PPU_MASK (0x3 << 14)
164 #define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14)
165 #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
166 #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
167 #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
168 #define GLOBAL_MAC_01 0x01
169 #define GLOBAL_MAC_23 0x02
170 #define GLOBAL_MAC_45 0x03
171 #define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */
172 #define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */
173 #define GLOBAL_VTU_FID_MASK 0xfff
174 #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */
175 #define GLOBAL_VTU_SID_MASK 0x3f
176 #define GLOBAL_CONTROL 0x04
177 #define GLOBAL_CONTROL_SW_RESET BIT(15)
178 #define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
179 #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
180 #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
181 #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
182 #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
183 #define GLOBAL_CONTROL_DEVICE_EN BIT(7)
184 #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
185 #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
186 #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
187 #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
188 #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
189 #define GLOBAL_CONTROL_TCAM_EN BIT(1)
190 #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
191 #define GLOBAL_VTU_OP 0x05
192 #define GLOBAL_VTU_OP_BUSY BIT(15)
193 #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY)
194 #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY)
195 #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY)
196 #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY)
197 #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY)
198 #define GLOBAL_VTU_VID 0x06
199 #define GLOBAL_VTU_VID_MASK 0xfff
200 #define GLOBAL_VTU_VID_VALID BIT(12)
201 #define GLOBAL_VTU_DATA_0_3 0x07
202 #define GLOBAL_VTU_DATA_4_7 0x08
203 #define GLOBAL_VTU_DATA_8_11 0x09
204 #define GLOBAL_VTU_STU_DATA_MASK 0x03
205 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00
206 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01
207 #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02
208 #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03
209 #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00
210 #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01
211 #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02
212 #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03
213 #define GLOBAL_ATU_CONTROL 0x0a
214 #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3)
215 #define GLOBAL_ATU_OP 0x0b
216 #define GLOBAL_ATU_OP_BUSY BIT(15)
217 #define GLOBAL_ATU_OP_NOP (0 << 12)
218 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
219 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY)
220 #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
221 #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
222 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
223 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
224 #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY)
225 #define GLOBAL_ATU_DATA 0x0c
226 #define GLOBAL_ATU_DATA_TRUNK BIT(15)
227 #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0
228 #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4
229 #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
230 #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
231 #define GLOBAL_ATU_DATA_STATE_MASK 0x0f
232 #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
233 #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
234 #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
235 #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
236 #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
237 #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
238 #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
239 #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
240 #define GLOBAL_ATU_MAC_01 0x0d
241 #define GLOBAL_ATU_MAC_23 0x0e
242 #define GLOBAL_ATU_MAC_45 0x0f
243 #define GLOBAL_IP_PRI_0 0x10
244 #define GLOBAL_IP_PRI_1 0x11
245 #define GLOBAL_IP_PRI_2 0x12
246 #define GLOBAL_IP_PRI_3 0x13
247 #define GLOBAL_IP_PRI_4 0x14
248 #define GLOBAL_IP_PRI_5 0x15
249 #define GLOBAL_IP_PRI_6 0x16
250 #define GLOBAL_IP_PRI_7 0x17
251 #define GLOBAL_IEEE_PRI 0x18
252 #define GLOBAL_CORE_TAG_TYPE 0x19
253 #define GLOBAL_MONITOR_CONTROL 0x1a
254 #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
255 #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
256 #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
257 #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
258 #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
259 #define GLOBAL_CONTROL_2 0x1c
260 #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000
261 #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000
263 #define GLOBAL_STATS_OP 0x1d
264 #define GLOBAL_STATS_OP_BUSY BIT(15)
265 #define GLOBAL_STATS_OP_NOP (0 << 12)
266 #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY)
267 #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY)
268 #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY)
269 #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY)
270 #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY)
271 #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY)
272 #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY)
273 #define GLOBAL_STATS_OP_BANK_1 BIT(9)
274 #define GLOBAL_STATS_COUNTER_32 0x1e
275 #define GLOBAL_STATS_COUNTER_01 0x1f
277 #define REG_GLOBAL2 0x1c
278 #define GLOBAL2_INT_SOURCE 0x00
279 #define GLOBAL2_INT_MASK 0x01
280 #define GLOBAL2_MGMT_EN_2X 0x02
281 #define GLOBAL2_MGMT_EN_0X 0x03
282 #define GLOBAL2_FLOW_CONTROL 0x04
283 #define GLOBAL2_SWITCH_MGMT 0x05
284 #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
285 #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
286 #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
287 #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
288 #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
289 #define GLOBAL2_DEVICE_MAPPING 0x06
290 #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15)
291 #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8
292 #define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f
293 #define GLOBAL2_TRUNK_MASK 0x07
294 #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15)
295 #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12
296 #define GLOBAL2_TRUNK_MAPPING 0x08
297 #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
298 #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
299 #define GLOBAL2_INGRESS_OP 0x09
300 #define GLOBAL2_INGRESS_DATA 0x0a
301 #define GLOBAL2_PVT_ADDR 0x0b
302 #define GLOBAL2_PVT_DATA 0x0c
303 #define GLOBAL2_SWITCH_MAC 0x0d
304 #define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
305 #define GLOBAL2_ATU_STATS 0x0e
306 #define GLOBAL2_PRIO_OVERRIDE 0x0f
307 #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
308 #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
309 #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
310 #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
311 #define GLOBAL2_EEPROM_OP 0x14
312 #define GLOBAL2_EEPROM_OP_BUSY BIT(15)
313 #define GLOBAL2_EEPROM_OP_WRITE ((3 << 12) | GLOBAL2_EEPROM_OP_BUSY)
314 #define GLOBAL2_EEPROM_OP_READ ((4 << 12) | GLOBAL2_EEPROM_OP_BUSY)
315 #define GLOBAL2_EEPROM_OP_LOAD BIT(11)
316 #define GLOBAL2_EEPROM_OP_WRITE_EN BIT(10)
317 #define GLOBAL2_EEPROM_OP_ADDR_MASK 0xff
318 #define GLOBAL2_EEPROM_DATA 0x15
319 #define GLOBAL2_PTP_AVB_OP 0x16
320 #define GLOBAL2_PTP_AVB_DATA 0x17
321 #define GLOBAL2_SMI_OP 0x18
322 #define GLOBAL2_SMI_OP_BUSY BIT(15)
323 #define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12)
324 #define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \
325 GLOBAL2_SMI_OP_CLAUSE_22)
326 #define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \
327 GLOBAL2_SMI_OP_CLAUSE_22)
328 #define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY)
329 #define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY)
330 #define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY)
331 #define GLOBAL2_SMI_DATA 0x19
332 #define GLOBAL2_SCRATCH_MISC 0x1a
333 #define GLOBAL2_SCRATCH_BUSY BIT(15)
334 #define GLOBAL2_SCRATCH_REGISTER_SHIFT 8
335 #define GLOBAL2_SCRATCH_VALUE_MASK 0xff
336 #define GLOBAL2_WDOG_CONTROL 0x1b
337 #define GLOBAL2_QOS_WEIGHT 0x1c
338 #define GLOBAL2_MISC 0x1d
340 #define MV88E6XXX_N_FID 4096
342 /* List of supported models */
343 enum mv88e6xxx_model
{
363 enum mv88e6xxx_family
{
364 MV88E6XXX_FAMILY_NONE
,
365 MV88E6XXX_FAMILY_6065
, /* 6031 6035 6061 6065 */
366 MV88E6XXX_FAMILY_6095
, /* 6092 6095 */
367 MV88E6XXX_FAMILY_6097
, /* 6046 6085 6096 6097 */
368 MV88E6XXX_FAMILY_6165
, /* 6123 6161 6165 */
369 MV88E6XXX_FAMILY_6185
, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
370 MV88E6XXX_FAMILY_6320
, /* 6320 6321 */
371 MV88E6XXX_FAMILY_6351
, /* 6171 6175 6350 6351 */
372 MV88E6XXX_FAMILY_6352
, /* 6172 6176 6240 6352 */
376 /* Address Translation Unit.
377 * The ATU is used to lookup and learn MAC addresses. See GLOBAL_ATU_OP.
381 /* Energy Efficient Ethernet.
385 /* EEPROM Command and Data registers.
386 * See GLOBAL2_EEPROM_OP and GLOBAL2_EEPROM_DATA.
388 MV88E6XXX_CAP_EEPROM
,
390 /* Multi-chip Addressing Mode.
391 * Some chips require an indirect SMI access when their SMI device
392 * address is not zero. See SMI_CMD and SMI_DATA.
394 MV88E6XXX_CAP_MULTI_CHIP
,
396 /* Port State Filtering for 802.1D Spanning Tree.
397 * See PORT_CONTROL_STATE_* values in the PORT_CONTROL register.
399 MV88E6XXX_CAP_PORTSTATE
,
402 * See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING.
405 MV88E6XXX_CAP_PPU_ACTIVE
,
407 /* SMI PHY Command and Data registers.
408 * This requires an indirect access to PHY registers through
409 * GLOBAL2_SMI_OP, otherwise direct access to PHY registers is done.
411 MV88E6XXX_CAP_SMI_PHY
,
413 /* Per VLAN Spanning Tree Unit (STU).
414 * The Port State database, if present, is accessed through VTU
415 * operations and dedicated SID registers. See GLOBAL_VTU_SID.
419 /* Switch MAC/WoL/WoF register.
420 * This requires an indirect access to set the switch MAC address
421 * through GLOBAL2_SWITCH_MAC, otherwise GLOBAL_MAC_01, GLOBAL_MAC_23,
422 * and GLOBAL_MAC_45 are used with a direct access.
424 MV88E6XXX_CAP_SWITCH_MAC_WOL_WOF
,
426 /* Internal temperature sensor.
427 * Available from any enabled port's PHY register 26, page 6.
430 MV88E6XXX_CAP_TEMP_LIMIT
,
432 /* In-chip Port Based VLANs.
433 * Each port VLANTable register (see PORT_BASE_VLAN) is used to restrict
434 * the output (or egress) ports to which it is allowed to send frames.
436 MV88E6XXX_CAP_VLANTABLE
,
439 * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP.
444 /* Bitmask of capabilities */
445 #define MV88E6XXX_FLAG_ATU BIT(MV88E6XXX_CAP_ATU)
446 #define MV88E6XXX_FLAG_EEE BIT(MV88E6XXX_CAP_EEE)
447 #define MV88E6XXX_FLAG_EEPROM BIT(MV88E6XXX_CAP_EEPROM)
448 #define MV88E6XXX_FLAG_MULTI_CHIP BIT(MV88E6XXX_CAP_MULTI_CHIP)
449 #define MV88E6XXX_FLAG_PORTSTATE BIT(MV88E6XXX_CAP_PORTSTATE)
450 #define MV88E6XXX_FLAG_PPU BIT(MV88E6XXX_CAP_PPU)
451 #define MV88E6XXX_FLAG_PPU_ACTIVE BIT(MV88E6XXX_CAP_PPU_ACTIVE)
452 #define MV88E6XXX_FLAG_SMI_PHY BIT(MV88E6XXX_CAP_SMI_PHY)
453 #define MV88E6XXX_FLAG_STU BIT(MV88E6XXX_CAP_STU)
454 #define MV88E6XXX_FLAG_SWITCH_MAC BIT(MV88E6XXX_CAP_SWITCH_MAC_WOL_WOF)
455 #define MV88E6XXX_FLAG_TEMP BIT(MV88E6XXX_CAP_TEMP)
456 #define MV88E6XXX_FLAG_TEMP_LIMIT BIT(MV88E6XXX_CAP_TEMP_LIMIT)
457 #define MV88E6XXX_FLAG_VLANTABLE BIT(MV88E6XXX_CAP_VLANTABLE)
458 #define MV88E6XXX_FLAG_VTU BIT(MV88E6XXX_CAP_VTU)
460 #define MV88E6XXX_FLAGS_FAMILY_6095 \
461 (MV88E6XXX_FLAG_ATU | \
462 MV88E6XXX_FLAG_MULTI_CHIP | \
463 MV88E6XXX_FLAG_PPU | \
464 MV88E6XXX_FLAG_VLANTABLE | \
467 #define MV88E6XXX_FLAGS_FAMILY_6097 \
468 (MV88E6XXX_FLAG_ATU | \
469 MV88E6XXX_FLAG_MULTI_CHIP | \
470 MV88E6XXX_FLAG_PPU | \
471 MV88E6XXX_FLAG_STU | \
472 MV88E6XXX_FLAG_VLANTABLE | \
475 #define MV88E6XXX_FLAGS_FAMILY_6165 \
476 (MV88E6XXX_FLAG_MULTI_CHIP | \
477 MV88E6XXX_FLAG_STU | \
478 MV88E6XXX_FLAG_SWITCH_MAC | \
479 MV88E6XXX_FLAG_TEMP | \
482 #define MV88E6XXX_FLAGS_FAMILY_6185 \
483 (MV88E6XXX_FLAG_ATU | \
484 MV88E6XXX_FLAG_MULTI_CHIP | \
485 MV88E6XXX_FLAG_PPU | \
486 MV88E6XXX_FLAG_VLANTABLE | \
489 #define MV88E6XXX_FLAGS_FAMILY_6320 \
490 (MV88E6XXX_FLAG_ATU | \
491 MV88E6XXX_FLAG_EEE | \
492 MV88E6XXX_FLAG_EEPROM | \
493 MV88E6XXX_FLAG_MULTI_CHIP | \
494 MV88E6XXX_FLAG_PORTSTATE | \
495 MV88E6XXX_FLAG_PPU_ACTIVE | \
496 MV88E6XXX_FLAG_SMI_PHY | \
497 MV88E6XXX_FLAG_SWITCH_MAC | \
498 MV88E6XXX_FLAG_TEMP | \
499 MV88E6XXX_FLAG_TEMP_LIMIT | \
500 MV88E6XXX_FLAG_VLANTABLE | \
503 #define MV88E6XXX_FLAGS_FAMILY_6351 \
504 (MV88E6XXX_FLAG_ATU | \
505 MV88E6XXX_FLAG_MULTI_CHIP | \
506 MV88E6XXX_FLAG_PORTSTATE | \
507 MV88E6XXX_FLAG_PPU_ACTIVE | \
508 MV88E6XXX_FLAG_SMI_PHY | \
509 MV88E6XXX_FLAG_STU | \
510 MV88E6XXX_FLAG_SWITCH_MAC | \
511 MV88E6XXX_FLAG_TEMP | \
512 MV88E6XXX_FLAG_VLANTABLE | \
515 #define MV88E6XXX_FLAGS_FAMILY_6352 \
516 (MV88E6XXX_FLAG_ATU | \
517 MV88E6XXX_FLAG_EEE | \
518 MV88E6XXX_FLAG_EEPROM | \
519 MV88E6XXX_FLAG_MULTI_CHIP | \
520 MV88E6XXX_FLAG_PORTSTATE | \
521 MV88E6XXX_FLAG_PPU_ACTIVE | \
522 MV88E6XXX_FLAG_SMI_PHY | \
523 MV88E6XXX_FLAG_STU | \
524 MV88E6XXX_FLAG_SWITCH_MAC | \
525 MV88E6XXX_FLAG_TEMP | \
526 MV88E6XXX_FLAG_TEMP_LIMIT | \
527 MV88E6XXX_FLAG_VLANTABLE | \
530 struct mv88e6xxx_info
{
531 enum mv88e6xxx_family family
;
534 unsigned int num_databases
;
535 unsigned int num_ports
;
536 unsigned int port_base_addr
;
540 struct mv88e6xxx_atu_entry
{
548 struct mv88e6xxx_vtu_stu_entry
{
556 u8 data
[DSA_MAX_PORTS
];
559 struct mv88e6xxx_ops
;
561 struct mv88e6xxx_priv_port
{
562 struct net_device
*bridge_dev
;
565 struct mv88e6xxx_priv_state
{
566 const struct mv88e6xxx_info
*info
;
568 /* The dsa_switch this private structure is related to */
569 struct dsa_switch
*ds
;
571 /* The device this structure is associated to */
574 /* This mutex protects the access to the switch registers */
575 struct mutex reg_lock
;
577 /* The MII bus and the address on the bus that is used to
578 * communication with the switch
580 const struct mv88e6xxx_ops
*smi_ops
;
584 /* Handles automatic disabling and re-enabling of the PHY
587 struct mutex ppu_mutex
;
589 struct work_struct ppu_work
;
590 struct timer_list ppu_timer
;
592 /* This mutex serialises access to the statistics unit.
593 * Hold this mutex over snapshot + dump sequences.
595 struct mutex stats_mutex
;
597 /* This mutex serializes phy access for chips with
598 * indirect phy addressing. It is unused for chips
599 * with direct phy access.
601 struct mutex phy_mutex
;
603 /* This mutex serializes eeprom access for chips with
606 struct mutex eeprom_mutex
;
608 struct mv88e6xxx_priv_port ports
[DSA_MAX_PORTS
];
610 /* A switch may have a GPIO line tied to its reset pin. Parse
611 * this from the device tree, and use it before performing
614 struct gpio_desc
*reset
;
616 /* set to size of eeprom if supported by the switch */
619 /* Device node for the MDIO bus */
620 struct device_node
*mdio_np
;
622 /* And the MDIO bus itself */
623 struct mii_bus
*mdio_bus
;
626 struct mv88e6xxx_ops
{
627 int (*read
)(struct mv88e6xxx_priv_state
*ps
,
628 int addr
, int reg
, u16
*val
);
629 int (*write
)(struct mv88e6xxx_priv_state
*ps
,
630 int addr
, int reg
, u16 val
);
639 struct mv88e6xxx_hw_stat
{
640 char string
[ETH_GSTRING_LEN
];
646 static inline bool mv88e6xxx_has(struct mv88e6xxx_priv_state
*ps
,
649 return (ps
->info
->flags
& flags
) == flags
;