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Merge remote-tracking branches 'asoc/topic/atmel', 'asoc/topic/bcm2835' and 'asoc...
[mirror_ubuntu-zesty-kernel.git] / drivers / net / ethernet / apm / xgene / xgene_enet_main.c
1 /* Applied Micro X-Gene SoC Ethernet Driver
2 *
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "xgene_enet_main.h"
23 #include "xgene_enet_hw.h"
24 #include "xgene_enet_sgmac.h"
25 #include "xgene_enet_xgmac.h"
26
27 #define RES_ENET_CSR 0
28 #define RES_RING_CSR 1
29 #define RES_RING_CMD 2
30
31 static const struct of_device_id xgene_enet_of_match[];
32 static const struct acpi_device_id xgene_enet_acpi_match[];
33
34 static void xgene_enet_init_bufpool(struct xgene_enet_desc_ring *buf_pool)
35 {
36 struct xgene_enet_raw_desc16 *raw_desc;
37 int i;
38
39 for (i = 0; i < buf_pool->slots; i++) {
40 raw_desc = &buf_pool->raw_desc16[i];
41
42 /* Hardware expects descriptor in little endian format */
43 raw_desc->m0 = cpu_to_le64(i |
44 SET_VAL(FPQNUM, buf_pool->dst_ring_num) |
45 SET_VAL(STASH, 3));
46 }
47 }
48
49 static int xgene_enet_refill_bufpool(struct xgene_enet_desc_ring *buf_pool,
50 u32 nbuf)
51 {
52 struct sk_buff *skb;
53 struct xgene_enet_raw_desc16 *raw_desc;
54 struct xgene_enet_pdata *pdata;
55 struct net_device *ndev;
56 struct device *dev;
57 dma_addr_t dma_addr;
58 u32 tail = buf_pool->tail;
59 u32 slots = buf_pool->slots - 1;
60 u16 bufdatalen, len;
61 int i;
62
63 ndev = buf_pool->ndev;
64 dev = ndev_to_dev(buf_pool->ndev);
65 pdata = netdev_priv(ndev);
66 bufdatalen = BUF_LEN_CODE_2K | (SKB_BUFFER_SIZE & GENMASK(11, 0));
67 len = XGENE_ENET_MAX_MTU;
68
69 for (i = 0; i < nbuf; i++) {
70 raw_desc = &buf_pool->raw_desc16[tail];
71
72 skb = netdev_alloc_skb_ip_align(ndev, len);
73 if (unlikely(!skb))
74 return -ENOMEM;
75 buf_pool->rx_skb[tail] = skb;
76
77 dma_addr = dma_map_single(dev, skb->data, len, DMA_FROM_DEVICE);
78 if (dma_mapping_error(dev, dma_addr)) {
79 netdev_err(ndev, "DMA mapping error\n");
80 dev_kfree_skb_any(skb);
81 return -EINVAL;
82 }
83
84 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
85 SET_VAL(BUFDATALEN, bufdatalen) |
86 SET_BIT(COHERENT));
87 tail = (tail + 1) & slots;
88 }
89
90 pdata->ring_ops->wr_cmd(buf_pool, nbuf);
91 buf_pool->tail = tail;
92
93 return 0;
94 }
95
96 static u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
97 {
98 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
99
100 return ((u16)pdata->rm << 10) | ring->num;
101 }
102
103 static u8 xgene_enet_hdr_len(const void *data)
104 {
105 const struct ethhdr *eth = data;
106
107 return (eth->h_proto == htons(ETH_P_8021Q)) ? VLAN_ETH_HLEN : ETH_HLEN;
108 }
109
110 static void xgene_enet_delete_bufpool(struct xgene_enet_desc_ring *buf_pool)
111 {
112 struct xgene_enet_pdata *pdata = netdev_priv(buf_pool->ndev);
113 struct xgene_enet_raw_desc16 *raw_desc;
114 u32 slots = buf_pool->slots - 1;
115 u32 tail = buf_pool->tail;
116 u32 userinfo;
117 int i, len;
118
119 len = pdata->ring_ops->len(buf_pool);
120 for (i = 0; i < len; i++) {
121 tail = (tail - 1) & slots;
122 raw_desc = &buf_pool->raw_desc16[tail];
123
124 /* Hardware stores descriptor in little endian format */
125 userinfo = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
126 dev_kfree_skb_any(buf_pool->rx_skb[userinfo]);
127 }
128
129 pdata->ring_ops->wr_cmd(buf_pool, -len);
130 buf_pool->tail = tail;
131 }
132
133 static irqreturn_t xgene_enet_rx_irq(const int irq, void *data)
134 {
135 struct xgene_enet_desc_ring *rx_ring = data;
136
137 if (napi_schedule_prep(&rx_ring->napi)) {
138 disable_irq_nosync(irq);
139 __napi_schedule(&rx_ring->napi);
140 }
141
142 return IRQ_HANDLED;
143 }
144
145 static int xgene_enet_tx_completion(struct xgene_enet_desc_ring *cp_ring,
146 struct xgene_enet_raw_desc *raw_desc)
147 {
148 struct sk_buff *skb;
149 struct device *dev;
150 skb_frag_t *frag;
151 dma_addr_t *frag_dma_addr;
152 u16 skb_index;
153 u8 status;
154 int i, ret = 0;
155
156 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
157 skb = cp_ring->cp_skb[skb_index];
158 frag_dma_addr = &cp_ring->frag_dma_addr[skb_index * MAX_SKB_FRAGS];
159
160 dev = ndev_to_dev(cp_ring->ndev);
161 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
162 skb_headlen(skb),
163 DMA_TO_DEVICE);
164
165 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
166 frag = &skb_shinfo(skb)->frags[i];
167 dma_unmap_page(dev, frag_dma_addr[i], skb_frag_size(frag),
168 DMA_TO_DEVICE);
169 }
170
171 /* Checking for error */
172 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
173 if (unlikely(status > 2)) {
174 xgene_enet_parse_error(cp_ring, netdev_priv(cp_ring->ndev),
175 status);
176 ret = -EIO;
177 }
178
179 if (likely(skb)) {
180 dev_kfree_skb_any(skb);
181 } else {
182 netdev_err(cp_ring->ndev, "completion skb is NULL\n");
183 ret = -EIO;
184 }
185
186 return ret;
187 }
188
189 static u64 xgene_enet_work_msg(struct sk_buff *skb)
190 {
191 struct net_device *ndev = skb->dev;
192 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
193 struct iphdr *iph;
194 u8 l3hlen = 0, l4hlen = 0;
195 u8 ethhdr, proto = 0, csum_enable = 0;
196 u64 hopinfo = 0;
197 u32 hdr_len, mss = 0;
198 u32 i, len, nr_frags;
199
200 ethhdr = xgene_enet_hdr_len(skb->data);
201
202 if (unlikely(skb->protocol != htons(ETH_P_IP)) &&
203 unlikely(skb->protocol != htons(ETH_P_8021Q)))
204 goto out;
205
206 if (unlikely(!(skb->dev->features & NETIF_F_IP_CSUM)))
207 goto out;
208
209 iph = ip_hdr(skb);
210 if (unlikely(ip_is_fragment(iph)))
211 goto out;
212
213 if (likely(iph->protocol == IPPROTO_TCP)) {
214 l4hlen = tcp_hdrlen(skb) >> 2;
215 csum_enable = 1;
216 proto = TSO_IPPROTO_TCP;
217 if (ndev->features & NETIF_F_TSO) {
218 hdr_len = ethhdr + ip_hdrlen(skb) + tcp_hdrlen(skb);
219 mss = skb_shinfo(skb)->gso_size;
220
221 if (skb_is_nonlinear(skb)) {
222 len = skb_headlen(skb);
223 nr_frags = skb_shinfo(skb)->nr_frags;
224
225 for (i = 0; i < 2 && i < nr_frags; i++)
226 len += skb_shinfo(skb)->frags[i].size;
227
228 /* HW requires header must reside in 3 buffer */
229 if (unlikely(hdr_len > len)) {
230 if (skb_linearize(skb))
231 return 0;
232 }
233 }
234
235 if (!mss || ((skb->len - hdr_len) <= mss))
236 goto out;
237
238 if (mss != pdata->mss) {
239 pdata->mss = mss;
240 pdata->mac_ops->set_mss(pdata);
241 }
242 hopinfo |= SET_BIT(ET);
243 }
244 } else if (iph->protocol == IPPROTO_UDP) {
245 l4hlen = UDP_HDR_SIZE;
246 csum_enable = 1;
247 }
248 out:
249 l3hlen = ip_hdrlen(skb) >> 2;
250 hopinfo |= SET_VAL(TCPHDR, l4hlen) |
251 SET_VAL(IPHDR, l3hlen) |
252 SET_VAL(ETHHDR, ethhdr) |
253 SET_VAL(EC, csum_enable) |
254 SET_VAL(IS, proto) |
255 SET_BIT(IC) |
256 SET_BIT(TYPE_ETH_WORK_MESSAGE);
257
258 return hopinfo;
259 }
260
261 static u16 xgene_enet_encode_len(u16 len)
262 {
263 return (len == BUFLEN_16K) ? 0 : len;
264 }
265
266 static void xgene_set_addr_len(__le64 *desc, u32 idx, dma_addr_t addr, u32 len)
267 {
268 desc[idx ^ 1] = cpu_to_le64(SET_VAL(DATAADDR, addr) |
269 SET_VAL(BUFDATALEN, len));
270 }
271
272 static __le64 *xgene_enet_get_exp_bufs(struct xgene_enet_desc_ring *ring)
273 {
274 __le64 *exp_bufs;
275
276 exp_bufs = &ring->exp_bufs[ring->exp_buf_tail * MAX_EXP_BUFFS];
277 memset(exp_bufs, 0, sizeof(__le64) * MAX_EXP_BUFFS);
278 ring->exp_buf_tail = (ring->exp_buf_tail + 1) & ((ring->slots / 2) - 1);
279
280 return exp_bufs;
281 }
282
283 static dma_addr_t *xgene_get_frag_dma_array(struct xgene_enet_desc_ring *ring)
284 {
285 return &ring->cp_ring->frag_dma_addr[ring->tail * MAX_SKB_FRAGS];
286 }
287
288 static int xgene_enet_setup_tx_desc(struct xgene_enet_desc_ring *tx_ring,
289 struct sk_buff *skb)
290 {
291 struct device *dev = ndev_to_dev(tx_ring->ndev);
292 struct xgene_enet_pdata *pdata = netdev_priv(tx_ring->ndev);
293 struct xgene_enet_raw_desc *raw_desc;
294 __le64 *exp_desc = NULL, *exp_bufs = NULL;
295 dma_addr_t dma_addr, pbuf_addr, *frag_dma_addr;
296 skb_frag_t *frag;
297 u16 tail = tx_ring->tail;
298 u64 hopinfo;
299 u32 len, hw_len;
300 u8 ll = 0, nv = 0, idx = 0;
301 bool split = false;
302 u32 size, offset, ell_bytes = 0;
303 u32 i, fidx, nr_frags, count = 1;
304
305 raw_desc = &tx_ring->raw_desc[tail];
306 tail = (tail + 1) & (tx_ring->slots - 1);
307 memset(raw_desc, 0, sizeof(struct xgene_enet_raw_desc));
308
309 hopinfo = xgene_enet_work_msg(skb);
310 if (!hopinfo)
311 return -EINVAL;
312 raw_desc->m3 = cpu_to_le64(SET_VAL(HENQNUM, tx_ring->dst_ring_num) |
313 hopinfo);
314
315 len = skb_headlen(skb);
316 hw_len = xgene_enet_encode_len(len);
317
318 dma_addr = dma_map_single(dev, skb->data, len, DMA_TO_DEVICE);
319 if (dma_mapping_error(dev, dma_addr)) {
320 netdev_err(tx_ring->ndev, "DMA mapping error\n");
321 return -EINVAL;
322 }
323
324 /* Hardware expects descriptor in little endian format */
325 raw_desc->m1 = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
326 SET_VAL(BUFDATALEN, hw_len) |
327 SET_BIT(COHERENT));
328
329 if (!skb_is_nonlinear(skb))
330 goto out;
331
332 /* scatter gather */
333 nv = 1;
334 exp_desc = (void *)&tx_ring->raw_desc[tail];
335 tail = (tail + 1) & (tx_ring->slots - 1);
336 memset(exp_desc, 0, sizeof(struct xgene_enet_raw_desc));
337
338 nr_frags = skb_shinfo(skb)->nr_frags;
339 for (i = nr_frags; i < 4 ; i++)
340 exp_desc[i ^ 1] = cpu_to_le64(LAST_BUFFER);
341
342 frag_dma_addr = xgene_get_frag_dma_array(tx_ring);
343
344 for (i = 0, fidx = 0; split || (fidx < nr_frags); i++) {
345 if (!split) {
346 frag = &skb_shinfo(skb)->frags[fidx];
347 size = skb_frag_size(frag);
348 offset = 0;
349
350 pbuf_addr = skb_frag_dma_map(dev, frag, 0, size,
351 DMA_TO_DEVICE);
352 if (dma_mapping_error(dev, pbuf_addr))
353 return -EINVAL;
354
355 frag_dma_addr[fidx] = pbuf_addr;
356 fidx++;
357
358 if (size > BUFLEN_16K)
359 split = true;
360 }
361
362 if (size > BUFLEN_16K) {
363 len = BUFLEN_16K;
364 size -= BUFLEN_16K;
365 } else {
366 len = size;
367 split = false;
368 }
369
370 dma_addr = pbuf_addr + offset;
371 hw_len = xgene_enet_encode_len(len);
372
373 switch (i) {
374 case 0:
375 case 1:
376 case 2:
377 xgene_set_addr_len(exp_desc, i, dma_addr, hw_len);
378 break;
379 case 3:
380 if (split || (fidx != nr_frags)) {
381 exp_bufs = xgene_enet_get_exp_bufs(tx_ring);
382 xgene_set_addr_len(exp_bufs, idx, dma_addr,
383 hw_len);
384 idx++;
385 ell_bytes += len;
386 } else {
387 xgene_set_addr_len(exp_desc, i, dma_addr,
388 hw_len);
389 }
390 break;
391 default:
392 xgene_set_addr_len(exp_bufs, idx, dma_addr, hw_len);
393 idx++;
394 ell_bytes += len;
395 break;
396 }
397
398 if (split)
399 offset += BUFLEN_16K;
400 }
401 count++;
402
403 if (idx) {
404 ll = 1;
405 dma_addr = dma_map_single(dev, exp_bufs,
406 sizeof(u64) * MAX_EXP_BUFFS,
407 DMA_TO_DEVICE);
408 if (dma_mapping_error(dev, dma_addr)) {
409 dev_kfree_skb_any(skb);
410 return -EINVAL;
411 }
412 i = ell_bytes >> LL_BYTES_LSB_LEN;
413 exp_desc[2] = cpu_to_le64(SET_VAL(DATAADDR, dma_addr) |
414 SET_VAL(LL_BYTES_MSB, i) |
415 SET_VAL(LL_LEN, idx));
416 raw_desc->m2 = cpu_to_le64(SET_VAL(LL_BYTES_LSB, ell_bytes));
417 }
418
419 out:
420 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) |
421 SET_VAL(USERINFO, tx_ring->tail));
422 tx_ring->cp_ring->cp_skb[tx_ring->tail] = skb;
423 pdata->tx_level += count;
424 tx_ring->tail = tail;
425
426 return count;
427 }
428
429 static netdev_tx_t xgene_enet_start_xmit(struct sk_buff *skb,
430 struct net_device *ndev)
431 {
432 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
433 struct xgene_enet_desc_ring *tx_ring = pdata->tx_ring;
434 u32 tx_level = pdata->tx_level;
435 int count;
436
437 if (tx_level < pdata->txc_level)
438 tx_level += ((typeof(pdata->tx_level))~0U);
439
440 if ((tx_level - pdata->txc_level) > pdata->tx_qcnt_hi) {
441 netif_stop_queue(ndev);
442 return NETDEV_TX_BUSY;
443 }
444
445 if (skb_padto(skb, XGENE_MIN_ENET_FRAME_SIZE))
446 return NETDEV_TX_OK;
447
448 count = xgene_enet_setup_tx_desc(tx_ring, skb);
449 if (count <= 0) {
450 dev_kfree_skb_any(skb);
451 return NETDEV_TX_OK;
452 }
453
454 skb_tx_timestamp(skb);
455
456 pdata->stats.tx_packets++;
457 pdata->stats.tx_bytes += skb->len;
458
459 pdata->ring_ops->wr_cmd(tx_ring, count);
460 return NETDEV_TX_OK;
461 }
462
463 static void xgene_enet_skip_csum(struct sk_buff *skb)
464 {
465 struct iphdr *iph = ip_hdr(skb);
466
467 if (!ip_is_fragment(iph) ||
468 (iph->protocol != IPPROTO_TCP && iph->protocol != IPPROTO_UDP)) {
469 skb->ip_summed = CHECKSUM_UNNECESSARY;
470 }
471 }
472
473 static int xgene_enet_rx_frame(struct xgene_enet_desc_ring *rx_ring,
474 struct xgene_enet_raw_desc *raw_desc)
475 {
476 struct net_device *ndev;
477 struct xgene_enet_pdata *pdata;
478 struct device *dev;
479 struct xgene_enet_desc_ring *buf_pool;
480 u32 datalen, skb_index;
481 struct sk_buff *skb;
482 u8 status;
483 int ret = 0;
484
485 ndev = rx_ring->ndev;
486 pdata = netdev_priv(ndev);
487 dev = ndev_to_dev(rx_ring->ndev);
488 buf_pool = rx_ring->buf_pool;
489
490 dma_unmap_single(dev, GET_VAL(DATAADDR, le64_to_cpu(raw_desc->m1)),
491 XGENE_ENET_MAX_MTU, DMA_FROM_DEVICE);
492 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0));
493 skb = buf_pool->rx_skb[skb_index];
494
495 /* checking for error */
496 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0));
497 if (unlikely(status > 2)) {
498 dev_kfree_skb_any(skb);
499 xgene_enet_parse_error(rx_ring, netdev_priv(rx_ring->ndev),
500 status);
501 pdata->stats.rx_dropped++;
502 ret = -EIO;
503 goto out;
504 }
505
506 /* strip off CRC as HW isn't doing this */
507 datalen = GET_VAL(BUFDATALEN, le64_to_cpu(raw_desc->m1));
508 datalen = (datalen & DATALEN_MASK) - 4;
509 prefetch(skb->data - NET_IP_ALIGN);
510 skb_put(skb, datalen);
511
512 skb_checksum_none_assert(skb);
513 skb->protocol = eth_type_trans(skb, ndev);
514 if (likely((ndev->features & NETIF_F_IP_CSUM) &&
515 skb->protocol == htons(ETH_P_IP))) {
516 xgene_enet_skip_csum(skb);
517 }
518
519 pdata->stats.rx_packets++;
520 pdata->stats.rx_bytes += datalen;
521 napi_gro_receive(&rx_ring->napi, skb);
522 out:
523 if (--rx_ring->nbufpool == 0) {
524 ret = xgene_enet_refill_bufpool(buf_pool, NUM_BUFPOOL);
525 rx_ring->nbufpool = NUM_BUFPOOL;
526 }
527
528 return ret;
529 }
530
531 static bool is_rx_desc(struct xgene_enet_raw_desc *raw_desc)
532 {
533 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false;
534 }
535
536 static int xgene_enet_process_ring(struct xgene_enet_desc_ring *ring,
537 int budget)
538 {
539 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
540 struct xgene_enet_raw_desc *raw_desc, *exp_desc;
541 u16 head = ring->head;
542 u16 slots = ring->slots - 1;
543 int ret, desc_count, count = 0, processed = 0;
544 bool is_completion;
545
546 do {
547 raw_desc = &ring->raw_desc[head];
548 desc_count = 0;
549 is_completion = false;
550 exp_desc = NULL;
551 if (unlikely(xgene_enet_is_desc_slot_empty(raw_desc)))
552 break;
553
554 /* read fpqnum field after dataaddr field */
555 dma_rmb();
556 if (GET_BIT(NV, le64_to_cpu(raw_desc->m0))) {
557 head = (head + 1) & slots;
558 exp_desc = &ring->raw_desc[head];
559
560 if (unlikely(xgene_enet_is_desc_slot_empty(exp_desc))) {
561 head = (head - 1) & slots;
562 break;
563 }
564 dma_rmb();
565 count++;
566 desc_count++;
567 }
568 if (is_rx_desc(raw_desc)) {
569 ret = xgene_enet_rx_frame(ring, raw_desc);
570 } else {
571 ret = xgene_enet_tx_completion(ring, raw_desc);
572 is_completion = true;
573 }
574 xgene_enet_mark_desc_slot_empty(raw_desc);
575 if (exp_desc)
576 xgene_enet_mark_desc_slot_empty(exp_desc);
577
578 head = (head + 1) & slots;
579 count++;
580 desc_count++;
581 processed++;
582 if (is_completion)
583 pdata->txc_level += desc_count;
584
585 if (ret)
586 break;
587 } while (--budget);
588
589 if (likely(count)) {
590 pdata->ring_ops->wr_cmd(ring, -count);
591 ring->head = head;
592
593 if (netif_queue_stopped(ring->ndev))
594 netif_start_queue(ring->ndev);
595 }
596
597 return processed;
598 }
599
600 static int xgene_enet_napi(struct napi_struct *napi, const int budget)
601 {
602 struct xgene_enet_desc_ring *ring;
603 int processed;
604
605 ring = container_of(napi, struct xgene_enet_desc_ring, napi);
606 processed = xgene_enet_process_ring(ring, budget);
607
608 if (processed != budget) {
609 napi_complete(napi);
610 enable_irq(ring->irq);
611 }
612
613 return processed;
614 }
615
616 static void xgene_enet_timeout(struct net_device *ndev)
617 {
618 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
619
620 pdata->mac_ops->reset(pdata);
621 }
622
623 static int xgene_enet_register_irq(struct net_device *ndev)
624 {
625 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
626 struct device *dev = ndev_to_dev(ndev);
627 struct xgene_enet_desc_ring *ring;
628 int ret;
629
630 ring = pdata->rx_ring;
631 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
632 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
633 IRQF_SHARED, ring->irq_name, ring);
634 if (ret)
635 netdev_err(ndev, "Failed to request irq %s\n", ring->irq_name);
636
637 if (pdata->cq_cnt) {
638 ring = pdata->tx_ring->cp_ring;
639 irq_set_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
640 ret = devm_request_irq(dev, ring->irq, xgene_enet_rx_irq,
641 IRQF_SHARED, ring->irq_name, ring);
642 if (ret) {
643 netdev_err(ndev, "Failed to request irq %s\n",
644 ring->irq_name);
645 }
646 }
647
648 return ret;
649 }
650
651 static void xgene_enet_free_irq(struct net_device *ndev)
652 {
653 struct xgene_enet_pdata *pdata;
654 struct xgene_enet_desc_ring *ring;
655 struct device *dev;
656
657 pdata = netdev_priv(ndev);
658 dev = ndev_to_dev(ndev);
659 ring = pdata->rx_ring;
660 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
661 devm_free_irq(dev, ring->irq, ring);
662
663 if (pdata->cq_cnt) {
664 ring = pdata->tx_ring->cp_ring;
665 irq_clear_status_flags(ring->irq, IRQ_DISABLE_UNLAZY);
666 devm_free_irq(dev, ring->irq, ring);
667 }
668 }
669
670 static void xgene_enet_napi_enable(struct xgene_enet_pdata *pdata)
671 {
672 struct napi_struct *napi;
673
674 napi = &pdata->rx_ring->napi;
675 napi_enable(napi);
676
677 if (pdata->cq_cnt) {
678 napi = &pdata->tx_ring->cp_ring->napi;
679 napi_enable(napi);
680 }
681 }
682
683 static void xgene_enet_napi_disable(struct xgene_enet_pdata *pdata)
684 {
685 struct napi_struct *napi;
686
687 napi = &pdata->rx_ring->napi;
688 napi_disable(napi);
689
690 if (pdata->cq_cnt) {
691 napi = &pdata->tx_ring->cp_ring->napi;
692 napi_disable(napi);
693 }
694 }
695
696 static int xgene_enet_open(struct net_device *ndev)
697 {
698 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
699 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
700 int ret;
701
702 mac_ops->tx_enable(pdata);
703 mac_ops->rx_enable(pdata);
704
705 xgene_enet_napi_enable(pdata);
706 ret = xgene_enet_register_irq(ndev);
707 if (ret)
708 return ret;
709
710 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
711 phy_start(pdata->phy_dev);
712 else
713 schedule_delayed_work(&pdata->link_work, PHY_POLL_LINK_OFF);
714
715 netif_start_queue(ndev);
716
717 return ret;
718 }
719
720 static int xgene_enet_close(struct net_device *ndev)
721 {
722 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
723 const struct xgene_mac_ops *mac_ops = pdata->mac_ops;
724
725 netif_stop_queue(ndev);
726
727 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
728 phy_stop(pdata->phy_dev);
729 else
730 cancel_delayed_work_sync(&pdata->link_work);
731
732 mac_ops->tx_disable(pdata);
733 mac_ops->rx_disable(pdata);
734
735 xgene_enet_free_irq(ndev);
736 xgene_enet_napi_disable(pdata);
737 xgene_enet_process_ring(pdata->rx_ring, -1);
738
739 return 0;
740 }
741
742 static void xgene_enet_delete_ring(struct xgene_enet_desc_ring *ring)
743 {
744 struct xgene_enet_pdata *pdata;
745 struct device *dev;
746
747 pdata = netdev_priv(ring->ndev);
748 dev = ndev_to_dev(ring->ndev);
749
750 pdata->ring_ops->clear(ring);
751 dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
752 }
753
754 static void xgene_enet_delete_desc_rings(struct xgene_enet_pdata *pdata)
755 {
756 struct xgene_enet_desc_ring *buf_pool;
757
758 if (pdata->tx_ring) {
759 xgene_enet_delete_ring(pdata->tx_ring);
760 pdata->tx_ring = NULL;
761 }
762
763 if (pdata->rx_ring) {
764 buf_pool = pdata->rx_ring->buf_pool;
765 xgene_enet_delete_bufpool(buf_pool);
766 xgene_enet_delete_ring(buf_pool);
767 xgene_enet_delete_ring(pdata->rx_ring);
768 pdata->rx_ring = NULL;
769 }
770 }
771
772 static int xgene_enet_get_ring_size(struct device *dev,
773 enum xgene_enet_ring_cfgsize cfgsize)
774 {
775 int size = -EINVAL;
776
777 switch (cfgsize) {
778 case RING_CFGSIZE_512B:
779 size = 0x200;
780 break;
781 case RING_CFGSIZE_2KB:
782 size = 0x800;
783 break;
784 case RING_CFGSIZE_16KB:
785 size = 0x4000;
786 break;
787 case RING_CFGSIZE_64KB:
788 size = 0x10000;
789 break;
790 case RING_CFGSIZE_512KB:
791 size = 0x80000;
792 break;
793 default:
794 dev_err(dev, "Unsupported cfg ring size %d\n", cfgsize);
795 break;
796 }
797
798 return size;
799 }
800
801 static void xgene_enet_free_desc_ring(struct xgene_enet_desc_ring *ring)
802 {
803 struct xgene_enet_pdata *pdata;
804 struct device *dev;
805
806 if (!ring)
807 return;
808
809 dev = ndev_to_dev(ring->ndev);
810 pdata = netdev_priv(ring->ndev);
811
812 if (ring->desc_addr) {
813 pdata->ring_ops->clear(ring);
814 dma_free_coherent(dev, ring->size, ring->desc_addr, ring->dma);
815 }
816 devm_kfree(dev, ring);
817 }
818
819 static void xgene_enet_free_desc_rings(struct xgene_enet_pdata *pdata)
820 {
821 struct device *dev = &pdata->pdev->dev;
822 struct xgene_enet_desc_ring *ring;
823
824 ring = pdata->tx_ring;
825 if (ring) {
826 if (ring->cp_ring && ring->cp_ring->cp_skb)
827 devm_kfree(dev, ring->cp_ring->cp_skb);
828 if (ring->cp_ring && pdata->cq_cnt)
829 xgene_enet_free_desc_ring(ring->cp_ring);
830 xgene_enet_free_desc_ring(ring);
831 }
832
833 ring = pdata->rx_ring;
834 if (ring) {
835 if (ring->buf_pool) {
836 if (ring->buf_pool->rx_skb)
837 devm_kfree(dev, ring->buf_pool->rx_skb);
838 xgene_enet_free_desc_ring(ring->buf_pool);
839 }
840 xgene_enet_free_desc_ring(ring);
841 }
842 }
843
844 static bool is_irq_mbox_required(struct xgene_enet_pdata *pdata,
845 struct xgene_enet_desc_ring *ring)
846 {
847 if ((pdata->enet_id == XGENE_ENET2) &&
848 (xgene_enet_ring_owner(ring->id) == RING_OWNER_CPU)) {
849 return true;
850 }
851
852 return false;
853 }
854
855 static void __iomem *xgene_enet_ring_cmd_base(struct xgene_enet_pdata *pdata,
856 struct xgene_enet_desc_ring *ring)
857 {
858 u8 num_ring_id_shift = pdata->ring_ops->num_ring_id_shift;
859
860 return pdata->ring_cmd_addr + (ring->num << num_ring_id_shift);
861 }
862
863 static struct xgene_enet_desc_ring *xgene_enet_create_desc_ring(
864 struct net_device *ndev, u32 ring_num,
865 enum xgene_enet_ring_cfgsize cfgsize, u32 ring_id)
866 {
867 struct xgene_enet_desc_ring *ring;
868 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
869 struct device *dev = ndev_to_dev(ndev);
870 int size;
871
872 size = xgene_enet_get_ring_size(dev, cfgsize);
873 if (size < 0)
874 return NULL;
875
876 ring = devm_kzalloc(dev, sizeof(struct xgene_enet_desc_ring),
877 GFP_KERNEL);
878 if (!ring)
879 return NULL;
880
881 ring->ndev = ndev;
882 ring->num = ring_num;
883 ring->cfgsize = cfgsize;
884 ring->id = ring_id;
885
886 ring->desc_addr = dma_zalloc_coherent(dev, size, &ring->dma,
887 GFP_KERNEL);
888 if (!ring->desc_addr) {
889 devm_kfree(dev, ring);
890 return NULL;
891 }
892 ring->size = size;
893
894 if (is_irq_mbox_required(pdata, ring)) {
895 ring->irq_mbox_addr = dma_zalloc_coherent(dev, INTR_MBOX_SIZE,
896 &ring->irq_mbox_dma, GFP_KERNEL);
897 if (!ring->irq_mbox_addr) {
898 dma_free_coherent(dev, size, ring->desc_addr,
899 ring->dma);
900 devm_kfree(dev, ring);
901 return NULL;
902 }
903 }
904
905 ring->cmd_base = xgene_enet_ring_cmd_base(pdata, ring);
906 ring->cmd = ring->cmd_base + INC_DEC_CMD_ADDR;
907 ring = pdata->ring_ops->setup(ring);
908 netdev_dbg(ndev, "ring info: num=%d size=%d id=%d slots=%d\n",
909 ring->num, ring->size, ring->id, ring->slots);
910
911 return ring;
912 }
913
914 static u16 xgene_enet_get_ring_id(enum xgene_ring_owner owner, u8 bufnum)
915 {
916 return (owner << 6) | (bufnum & GENMASK(5, 0));
917 }
918
919 static enum xgene_ring_owner xgene_derive_ring_owner(struct xgene_enet_pdata *p)
920 {
921 enum xgene_ring_owner owner;
922
923 if (p->enet_id == XGENE_ENET1) {
924 switch (p->phy_mode) {
925 case PHY_INTERFACE_MODE_SGMII:
926 owner = RING_OWNER_ETH0;
927 break;
928 default:
929 owner = (!p->port_id) ? RING_OWNER_ETH0 :
930 RING_OWNER_ETH1;
931 break;
932 }
933 } else {
934 owner = (!p->port_id) ? RING_OWNER_ETH0 : RING_OWNER_ETH1;
935 }
936
937 return owner;
938 }
939
940 static int xgene_enet_create_desc_rings(struct net_device *ndev)
941 {
942 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
943 struct device *dev = ndev_to_dev(ndev);
944 struct xgene_enet_desc_ring *rx_ring, *tx_ring, *cp_ring;
945 struct xgene_enet_desc_ring *buf_pool = NULL;
946 enum xgene_ring_owner owner;
947 dma_addr_t dma_exp_bufs;
948 u8 cpu_bufnum = pdata->cpu_bufnum;
949 u8 eth_bufnum = pdata->eth_bufnum;
950 u8 bp_bufnum = pdata->bp_bufnum;
951 u16 ring_num = pdata->ring_num;
952 u16 ring_id;
953 int ret, size;
954
955 /* allocate rx descriptor ring */
956 owner = xgene_derive_ring_owner(pdata);
957 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
958 rx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
959 RING_CFGSIZE_16KB, ring_id);
960 if (!rx_ring) {
961 ret = -ENOMEM;
962 goto err;
963 }
964
965 /* allocate buffer pool for receiving packets */
966 owner = xgene_derive_ring_owner(pdata);
967 ring_id = xgene_enet_get_ring_id(owner, bp_bufnum++);
968 buf_pool = xgene_enet_create_desc_ring(ndev, ring_num++,
969 RING_CFGSIZE_2KB, ring_id);
970 if (!buf_pool) {
971 ret = -ENOMEM;
972 goto err;
973 }
974
975 rx_ring->nbufpool = NUM_BUFPOOL;
976 rx_ring->buf_pool = buf_pool;
977 rx_ring->irq = pdata->rx_irq;
978 if (!pdata->cq_cnt) {
979 snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx-txc",
980 ndev->name);
981 } else {
982 snprintf(rx_ring->irq_name, IRQ_ID_SIZE, "%s-rx", ndev->name);
983 }
984 buf_pool->rx_skb = devm_kcalloc(dev, buf_pool->slots,
985 sizeof(struct sk_buff *), GFP_KERNEL);
986 if (!buf_pool->rx_skb) {
987 ret = -ENOMEM;
988 goto err;
989 }
990
991 buf_pool->dst_ring_num = xgene_enet_dst_ring_num(buf_pool);
992 rx_ring->buf_pool = buf_pool;
993 pdata->rx_ring = rx_ring;
994
995 /* allocate tx descriptor ring */
996 owner = xgene_derive_ring_owner(pdata);
997 ring_id = xgene_enet_get_ring_id(owner, eth_bufnum++);
998 tx_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
999 RING_CFGSIZE_16KB, ring_id);
1000 if (!tx_ring) {
1001 ret = -ENOMEM;
1002 goto err;
1003 }
1004
1005 size = (tx_ring->slots / 2) * sizeof(__le64) * MAX_EXP_BUFFS;
1006 tx_ring->exp_bufs = dma_zalloc_coherent(dev, size, &dma_exp_bufs,
1007 GFP_KERNEL);
1008 if (!tx_ring->exp_bufs) {
1009 ret = -ENOMEM;
1010 goto err;
1011 }
1012
1013 pdata->tx_ring = tx_ring;
1014
1015 if (!pdata->cq_cnt) {
1016 cp_ring = pdata->rx_ring;
1017 } else {
1018 /* allocate tx completion descriptor ring */
1019 ring_id = xgene_enet_get_ring_id(RING_OWNER_CPU, cpu_bufnum++);
1020 cp_ring = xgene_enet_create_desc_ring(ndev, ring_num++,
1021 RING_CFGSIZE_16KB,
1022 ring_id);
1023 if (!cp_ring) {
1024 ret = -ENOMEM;
1025 goto err;
1026 }
1027 cp_ring->irq = pdata->txc_irq;
1028 snprintf(cp_ring->irq_name, IRQ_ID_SIZE, "%s-txc", ndev->name);
1029 }
1030
1031 cp_ring->cp_skb = devm_kcalloc(dev, tx_ring->slots,
1032 sizeof(struct sk_buff *), GFP_KERNEL);
1033 if (!cp_ring->cp_skb) {
1034 ret = -ENOMEM;
1035 goto err;
1036 }
1037
1038 size = sizeof(dma_addr_t) * MAX_SKB_FRAGS;
1039 cp_ring->frag_dma_addr = devm_kcalloc(dev, tx_ring->slots,
1040 size, GFP_KERNEL);
1041 if (!cp_ring->frag_dma_addr) {
1042 devm_kfree(dev, cp_ring->cp_skb);
1043 ret = -ENOMEM;
1044 goto err;
1045 }
1046
1047 pdata->tx_ring->cp_ring = cp_ring;
1048 pdata->tx_ring->dst_ring_num = xgene_enet_dst_ring_num(cp_ring);
1049
1050 pdata->tx_qcnt_hi = pdata->tx_ring->slots - 128;
1051
1052 return 0;
1053
1054 err:
1055 xgene_enet_free_desc_rings(pdata);
1056 return ret;
1057 }
1058
1059 static struct rtnl_link_stats64 *xgene_enet_get_stats64(
1060 struct net_device *ndev,
1061 struct rtnl_link_stats64 *storage)
1062 {
1063 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1064 struct rtnl_link_stats64 *stats = &pdata->stats;
1065
1066 stats->rx_errors += stats->rx_length_errors +
1067 stats->rx_crc_errors +
1068 stats->rx_frame_errors +
1069 stats->rx_fifo_errors;
1070 memcpy(storage, &pdata->stats, sizeof(struct rtnl_link_stats64));
1071
1072 return storage;
1073 }
1074
1075 static int xgene_enet_set_mac_address(struct net_device *ndev, void *addr)
1076 {
1077 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
1078 int ret;
1079
1080 ret = eth_mac_addr(ndev, addr);
1081 if (ret)
1082 return ret;
1083 pdata->mac_ops->set_mac_addr(pdata);
1084
1085 return ret;
1086 }
1087
1088 static const struct net_device_ops xgene_ndev_ops = {
1089 .ndo_open = xgene_enet_open,
1090 .ndo_stop = xgene_enet_close,
1091 .ndo_start_xmit = xgene_enet_start_xmit,
1092 .ndo_tx_timeout = xgene_enet_timeout,
1093 .ndo_get_stats64 = xgene_enet_get_stats64,
1094 .ndo_change_mtu = eth_change_mtu,
1095 .ndo_set_mac_address = xgene_enet_set_mac_address,
1096 };
1097
1098 #ifdef CONFIG_ACPI
1099 static void xgene_get_port_id_acpi(struct device *dev,
1100 struct xgene_enet_pdata *pdata)
1101 {
1102 acpi_status status;
1103 u64 temp;
1104
1105 status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_SUN", NULL, &temp);
1106 if (ACPI_FAILURE(status)) {
1107 pdata->port_id = 0;
1108 } else {
1109 pdata->port_id = temp;
1110 }
1111
1112 return;
1113 }
1114 #endif
1115
1116 static void xgene_get_port_id_dt(struct device *dev, struct xgene_enet_pdata *pdata)
1117 {
1118 u32 id = 0;
1119
1120 of_property_read_u32(dev->of_node, "port-id", &id);
1121
1122 pdata->port_id = id & BIT(0);
1123
1124 return;
1125 }
1126
1127 static int xgene_get_tx_delay(struct xgene_enet_pdata *pdata)
1128 {
1129 struct device *dev = &pdata->pdev->dev;
1130 int delay, ret;
1131
1132 ret = of_property_read_u32(dev->of_node, "tx-delay", &delay);
1133 if (ret) {
1134 pdata->tx_delay = 4;
1135 return 0;
1136 }
1137
1138 if (delay < 0 || delay > 7) {
1139 dev_err(dev, "Invalid tx-delay specified\n");
1140 return -EINVAL;
1141 }
1142
1143 pdata->tx_delay = delay;
1144
1145 return 0;
1146 }
1147
1148 static int xgene_get_rx_delay(struct xgene_enet_pdata *pdata)
1149 {
1150 struct device *dev = &pdata->pdev->dev;
1151 int delay, ret;
1152
1153 ret = of_property_read_u32(dev->of_node, "rx-delay", &delay);
1154 if (ret) {
1155 pdata->rx_delay = 2;
1156 return 0;
1157 }
1158
1159 if (delay < 0 || delay > 7) {
1160 dev_err(dev, "Invalid rx-delay specified\n");
1161 return -EINVAL;
1162 }
1163
1164 pdata->rx_delay = delay;
1165
1166 return 0;
1167 }
1168
1169 static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
1170 {
1171 struct platform_device *pdev;
1172 struct net_device *ndev;
1173 struct device *dev;
1174 struct resource *res;
1175 void __iomem *base_addr;
1176 u32 offset;
1177 int ret = 0;
1178
1179 pdev = pdata->pdev;
1180 dev = &pdev->dev;
1181 ndev = pdata->ndev;
1182
1183 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_ENET_CSR);
1184 if (!res) {
1185 dev_err(dev, "Resource enet_csr not defined\n");
1186 return -ENODEV;
1187 }
1188 pdata->base_addr = devm_ioremap(dev, res->start, resource_size(res));
1189 if (!pdata->base_addr) {
1190 dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
1191 return -ENOMEM;
1192 }
1193
1194 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CSR);
1195 if (!res) {
1196 dev_err(dev, "Resource ring_csr not defined\n");
1197 return -ENODEV;
1198 }
1199 pdata->ring_csr_addr = devm_ioremap(dev, res->start,
1200 resource_size(res));
1201 if (!pdata->ring_csr_addr) {
1202 dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
1203 return -ENOMEM;
1204 }
1205
1206 res = platform_get_resource(pdev, IORESOURCE_MEM, RES_RING_CMD);
1207 if (!res) {
1208 dev_err(dev, "Resource ring_cmd not defined\n");
1209 return -ENODEV;
1210 }
1211 pdata->ring_cmd_addr = devm_ioremap(dev, res->start,
1212 resource_size(res));
1213 if (!pdata->ring_cmd_addr) {
1214 dev_err(dev, "Unable to retrieve ENET Ring command region\n");
1215 return -ENOMEM;
1216 }
1217
1218 if (dev->of_node)
1219 xgene_get_port_id_dt(dev, pdata);
1220 #ifdef CONFIG_ACPI
1221 else
1222 xgene_get_port_id_acpi(dev, pdata);
1223 #endif
1224
1225 if (!device_get_mac_address(dev, ndev->dev_addr, ETH_ALEN))
1226 eth_hw_addr_random(ndev);
1227
1228 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
1229
1230 pdata->phy_mode = device_get_phy_mode(dev);
1231 if (pdata->phy_mode < 0) {
1232 dev_err(dev, "Unable to get phy-connection-type\n");
1233 return pdata->phy_mode;
1234 }
1235 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII &&
1236 pdata->phy_mode != PHY_INTERFACE_MODE_SGMII &&
1237 pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
1238 dev_err(dev, "Incorrect phy-connection-type specified\n");
1239 return -ENODEV;
1240 }
1241
1242 ret = xgene_get_tx_delay(pdata);
1243 if (ret)
1244 return ret;
1245
1246 ret = xgene_get_rx_delay(pdata);
1247 if (ret)
1248 return ret;
1249
1250 ret = platform_get_irq(pdev, 0);
1251 if (ret <= 0) {
1252 dev_err(dev, "Unable to get ENET Rx IRQ\n");
1253 ret = ret ? : -ENXIO;
1254 return ret;
1255 }
1256 pdata->rx_irq = ret;
1257
1258 if (pdata->phy_mode != PHY_INTERFACE_MODE_RGMII) {
1259 ret = platform_get_irq(pdev, 1);
1260 if (ret <= 0) {
1261 pdata->cq_cnt = 0;
1262 dev_info(dev, "Unable to get Tx completion IRQ,"
1263 "using Rx IRQ instead\n");
1264 } else {
1265 pdata->cq_cnt = XGENE_MAX_TXC_RINGS;
1266 pdata->txc_irq = ret;
1267 }
1268 }
1269
1270 pdata->clk = devm_clk_get(&pdev->dev, NULL);
1271 if (IS_ERR(pdata->clk)) {
1272 /* Firmware may have set up the clock already. */
1273 dev_info(dev, "clocks have been setup already\n");
1274 }
1275
1276 if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII)
1277 base_addr = pdata->base_addr - (pdata->port_id * MAC_OFFSET);
1278 else
1279 base_addr = pdata->base_addr;
1280 pdata->eth_csr_addr = base_addr + BLOCK_ETH_CSR_OFFSET;
1281 pdata->eth_ring_if_addr = base_addr + BLOCK_ETH_RING_IF_OFFSET;
1282 pdata->eth_diag_csr_addr = base_addr + BLOCK_ETH_DIAG_CSR_OFFSET;
1283 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII ||
1284 pdata->phy_mode == PHY_INTERFACE_MODE_SGMII) {
1285 pdata->mcx_mac_addr = pdata->base_addr + BLOCK_ETH_MAC_OFFSET;
1286 offset = (pdata->enet_id == XGENE_ENET1) ?
1287 BLOCK_ETH_MAC_CSR_OFFSET :
1288 X2_BLOCK_ETH_MAC_CSR_OFFSET;
1289 pdata->mcx_mac_csr_addr = base_addr + offset;
1290 } else {
1291 pdata->mcx_mac_addr = base_addr + BLOCK_AXG_MAC_OFFSET;
1292 pdata->mcx_mac_csr_addr = base_addr + BLOCK_AXG_MAC_CSR_OFFSET;
1293 }
1294 pdata->rx_buff_cnt = NUM_PKT_BUF;
1295
1296 return 0;
1297 }
1298
1299 static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
1300 {
1301 struct net_device *ndev = pdata->ndev;
1302 struct xgene_enet_desc_ring *buf_pool;
1303 u16 dst_ring_num;
1304 int ret;
1305
1306 ret = pdata->port_ops->reset(pdata);
1307 if (ret)
1308 return ret;
1309
1310 ret = xgene_enet_create_desc_rings(ndev);
1311 if (ret) {
1312 netdev_err(ndev, "Error in ring configuration\n");
1313 return ret;
1314 }
1315
1316 /* setup buffer pool */
1317 buf_pool = pdata->rx_ring->buf_pool;
1318 xgene_enet_init_bufpool(buf_pool);
1319 ret = xgene_enet_refill_bufpool(buf_pool, pdata->rx_buff_cnt);
1320 if (ret) {
1321 xgene_enet_delete_desc_rings(pdata);
1322 return ret;
1323 }
1324
1325 dst_ring_num = xgene_enet_dst_ring_num(pdata->rx_ring);
1326 pdata->port_ops->cle_bypass(pdata, dst_ring_num, buf_pool->id);
1327 pdata->mac_ops->init(pdata);
1328
1329 return ret;
1330 }
1331
1332 static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
1333 {
1334 switch (pdata->phy_mode) {
1335 case PHY_INTERFACE_MODE_RGMII:
1336 pdata->mac_ops = &xgene_gmac_ops;
1337 pdata->port_ops = &xgene_gport_ops;
1338 pdata->rm = RM3;
1339 break;
1340 case PHY_INTERFACE_MODE_SGMII:
1341 pdata->mac_ops = &xgene_sgmac_ops;
1342 pdata->port_ops = &xgene_sgport_ops;
1343 pdata->rm = RM1;
1344 break;
1345 default:
1346 pdata->mac_ops = &xgene_xgmac_ops;
1347 pdata->port_ops = &xgene_xgport_ops;
1348 pdata->rm = RM0;
1349 break;
1350 }
1351
1352 if (pdata->enet_id == XGENE_ENET1) {
1353 switch (pdata->port_id) {
1354 case 0:
1355 pdata->cpu_bufnum = START_CPU_BUFNUM_0;
1356 pdata->eth_bufnum = START_ETH_BUFNUM_0;
1357 pdata->bp_bufnum = START_BP_BUFNUM_0;
1358 pdata->ring_num = START_RING_NUM_0;
1359 break;
1360 case 1:
1361 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1362 pdata->cpu_bufnum = XG_START_CPU_BUFNUM_1;
1363 pdata->eth_bufnum = XG_START_ETH_BUFNUM_1;
1364 pdata->bp_bufnum = XG_START_BP_BUFNUM_1;
1365 pdata->ring_num = XG_START_RING_NUM_1;
1366 } else {
1367 pdata->cpu_bufnum = START_CPU_BUFNUM_1;
1368 pdata->eth_bufnum = START_ETH_BUFNUM_1;
1369 pdata->bp_bufnum = START_BP_BUFNUM_1;
1370 pdata->ring_num = START_RING_NUM_1;
1371 }
1372 break;
1373 default:
1374 break;
1375 }
1376 pdata->ring_ops = &xgene_ring1_ops;
1377 } else {
1378 switch (pdata->port_id) {
1379 case 0:
1380 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_0;
1381 pdata->eth_bufnum = X2_START_ETH_BUFNUM_0;
1382 pdata->bp_bufnum = X2_START_BP_BUFNUM_0;
1383 pdata->ring_num = X2_START_RING_NUM_0;
1384 break;
1385 case 1:
1386 pdata->cpu_bufnum = X2_START_CPU_BUFNUM_1;
1387 pdata->eth_bufnum = X2_START_ETH_BUFNUM_1;
1388 pdata->bp_bufnum = X2_START_BP_BUFNUM_1;
1389 pdata->ring_num = X2_START_RING_NUM_1;
1390 break;
1391 default:
1392 break;
1393 }
1394 pdata->rm = RM0;
1395 pdata->ring_ops = &xgene_ring2_ops;
1396 }
1397 }
1398
1399 static void xgene_enet_napi_add(struct xgene_enet_pdata *pdata)
1400 {
1401 struct napi_struct *napi;
1402
1403 napi = &pdata->rx_ring->napi;
1404 netif_napi_add(pdata->ndev, napi, xgene_enet_napi, NAPI_POLL_WEIGHT);
1405
1406 if (pdata->cq_cnt) {
1407 napi = &pdata->tx_ring->cp_ring->napi;
1408 netif_napi_add(pdata->ndev, napi, xgene_enet_napi,
1409 NAPI_POLL_WEIGHT);
1410 }
1411 }
1412
1413 static void xgene_enet_napi_del(struct xgene_enet_pdata *pdata)
1414 {
1415 struct napi_struct *napi;
1416
1417 napi = &pdata->rx_ring->napi;
1418 netif_napi_del(napi);
1419
1420 if (pdata->cq_cnt) {
1421 napi = &pdata->tx_ring->cp_ring->napi;
1422 netif_napi_del(napi);
1423 }
1424 }
1425
1426 static int xgene_enet_probe(struct platform_device *pdev)
1427 {
1428 struct net_device *ndev;
1429 struct xgene_enet_pdata *pdata;
1430 struct device *dev = &pdev->dev;
1431 const struct xgene_mac_ops *mac_ops;
1432 const struct of_device_id *of_id;
1433 int ret;
1434
1435 ndev = alloc_etherdev(sizeof(struct xgene_enet_pdata));
1436 if (!ndev)
1437 return -ENOMEM;
1438
1439 pdata = netdev_priv(ndev);
1440
1441 pdata->pdev = pdev;
1442 pdata->ndev = ndev;
1443 SET_NETDEV_DEV(ndev, dev);
1444 platform_set_drvdata(pdev, pdata);
1445 ndev->netdev_ops = &xgene_ndev_ops;
1446 xgene_enet_set_ethtool_ops(ndev);
1447 ndev->features |= NETIF_F_IP_CSUM |
1448 NETIF_F_GSO |
1449 NETIF_F_GRO |
1450 NETIF_F_SG;
1451
1452 of_id = of_match_device(xgene_enet_of_match, &pdev->dev);
1453 if (of_id) {
1454 pdata->enet_id = (enum xgene_enet_id)of_id->data;
1455 }
1456 #ifdef CONFIG_ACPI
1457 else {
1458 const struct acpi_device_id *acpi_id;
1459
1460 acpi_id = acpi_match_device(xgene_enet_acpi_match, &pdev->dev);
1461 if (acpi_id)
1462 pdata->enet_id = (enum xgene_enet_id) acpi_id->driver_data;
1463 }
1464 #endif
1465 if (!pdata->enet_id) {
1466 free_netdev(ndev);
1467 return -ENODEV;
1468 }
1469
1470 ret = xgene_enet_get_resources(pdata);
1471 if (ret)
1472 goto err;
1473
1474 xgene_enet_setup_ops(pdata);
1475
1476 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
1477 ndev->features |= NETIF_F_TSO;
1478 pdata->mss = XGENE_ENET_MSS;
1479 }
1480 ndev->hw_features = ndev->features;
1481
1482 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
1483 if (ret) {
1484 netdev_err(ndev, "No usable DMA configuration\n");
1485 goto err;
1486 }
1487
1488 ret = register_netdev(ndev);
1489 if (ret) {
1490 netdev_err(ndev, "Failed to register netdev\n");
1491 goto err;
1492 }
1493
1494 ret = xgene_enet_init_hw(pdata);
1495 if (ret)
1496 goto err;
1497
1498 mac_ops = pdata->mac_ops;
1499 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII) {
1500 ret = xgene_enet_mdio_config(pdata);
1501 if (ret)
1502 goto err;
1503 } else {
1504 INIT_DELAYED_WORK(&pdata->link_work, mac_ops->link_state);
1505 }
1506
1507 xgene_enet_napi_add(pdata);
1508 return 0;
1509 err:
1510 unregister_netdev(ndev);
1511 free_netdev(ndev);
1512 return ret;
1513 }
1514
1515 static int xgene_enet_remove(struct platform_device *pdev)
1516 {
1517 struct xgene_enet_pdata *pdata;
1518 const struct xgene_mac_ops *mac_ops;
1519 struct net_device *ndev;
1520
1521 pdata = platform_get_drvdata(pdev);
1522 mac_ops = pdata->mac_ops;
1523 ndev = pdata->ndev;
1524
1525 mac_ops->rx_disable(pdata);
1526 mac_ops->tx_disable(pdata);
1527
1528 xgene_enet_napi_del(pdata);
1529 if (pdata->phy_mode == PHY_INTERFACE_MODE_RGMII)
1530 xgene_enet_mdio_remove(pdata);
1531 unregister_netdev(ndev);
1532 xgene_enet_delete_desc_rings(pdata);
1533 pdata->port_ops->shutdown(pdata);
1534 free_netdev(ndev);
1535
1536 return 0;
1537 }
1538
1539 #ifdef CONFIG_ACPI
1540 static const struct acpi_device_id xgene_enet_acpi_match[] = {
1541 { "APMC0D05", XGENE_ENET1},
1542 { "APMC0D30", XGENE_ENET1},
1543 { "APMC0D31", XGENE_ENET1},
1544 { "APMC0D3F", XGENE_ENET1},
1545 { "APMC0D26", XGENE_ENET2},
1546 { "APMC0D25", XGENE_ENET2},
1547 { }
1548 };
1549 MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
1550 #endif
1551
1552 #ifdef CONFIG_OF
1553 static const struct of_device_id xgene_enet_of_match[] = {
1554 {.compatible = "apm,xgene-enet", .data = (void *)XGENE_ENET1},
1555 {.compatible = "apm,xgene1-sgenet", .data = (void *)XGENE_ENET1},
1556 {.compatible = "apm,xgene1-xgenet", .data = (void *)XGENE_ENET1},
1557 {.compatible = "apm,xgene2-sgenet", .data = (void *)XGENE_ENET2},
1558 {.compatible = "apm,xgene2-xgenet", .data = (void *)XGENE_ENET2},
1559 {},
1560 };
1561
1562 MODULE_DEVICE_TABLE(of, xgene_enet_of_match);
1563 #endif
1564
1565 static struct platform_driver xgene_enet_driver = {
1566 .driver = {
1567 .name = "xgene-enet",
1568 .of_match_table = of_match_ptr(xgene_enet_of_match),
1569 .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match),
1570 },
1571 .probe = xgene_enet_probe,
1572 .remove = xgene_enet_remove,
1573 };
1574
1575 module_platform_driver(xgene_enet_driver);
1576
1577 MODULE_DESCRIPTION("APM X-Gene SoC Ethernet driver");
1578 MODULE_VERSION(XGENE_DRV_VERSION);
1579 MODULE_AUTHOR("Iyappan Subramanian <isubramanian@apm.com>");
1580 MODULE_AUTHOR("Keyur Chudgar <kchudgar@apm.com>");
1581 MODULE_LICENSE("GPL");
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