1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __XGENE_ENET_MAIN_H__
23 #define __XGENE_ENET_MAIN_H__
25 #include <linux/acpi.h>
26 #include <linux/clk.h>
27 #include <linux/efi.h>
28 #include <linux/irq.h>
30 #include <linux/of_platform.h>
31 #include <linux/of_net.h>
32 #include <linux/of_mdio.h>
33 #include <linux/module.h>
35 #include <linux/prefetch.h>
36 #include <linux/if_vlan.h>
37 #include <linux/phy.h>
38 #include "xgene_enet_hw.h"
39 #include "xgene_enet_cle.h"
40 #include "xgene_enet_ring2.h"
41 #include "../../../phy/mdio-xgene.h"
43 #define XGENE_DRV_VERSION "v1.0"
44 #define XGENE_ENET_MAX_MTU 1536
45 #define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
46 #define BUFLEN_16K (16 * 1024)
47 #define NUM_PKT_BUF 64
48 #define NUM_BUFPOOL 32
49 #define MAX_EXP_BUFFS 256
50 #define XGENE_ENET_MSS 1448
51 #define XGENE_MIN_ENET_FRAME_SIZE 60
53 #define XGENE_MAX_ENET_IRQ 16
54 #define XGENE_NUM_RX_RING 8
55 #define XGENE_NUM_TX_RING 8
56 #define XGENE_NUM_TXC_RING 8
58 #define START_CPU_BUFNUM_0 0
59 #define START_ETH_BUFNUM_0 2
60 #define START_BP_BUFNUM_0 0x22
61 #define START_RING_NUM_0 8
62 #define START_CPU_BUFNUM_1 12
63 #define START_ETH_BUFNUM_1 10
64 #define START_BP_BUFNUM_1 0x2A
65 #define START_RING_NUM_1 264
67 #define XG_START_CPU_BUFNUM_1 12
68 #define XG_START_ETH_BUFNUM_1 2
69 #define XG_START_BP_BUFNUM_1 0x22
70 #define XG_START_RING_NUM_1 264
72 #define X2_START_CPU_BUFNUM_0 0
73 #define X2_START_ETH_BUFNUM_0 0
74 #define X2_START_BP_BUFNUM_0 0x20
75 #define X2_START_RING_NUM_0 0
76 #define X2_START_CPU_BUFNUM_1 0xc
77 #define X2_START_ETH_BUFNUM_1 0
78 #define X2_START_BP_BUFNUM_1 0x20
79 #define X2_START_RING_NUM_1 256
81 #define IRQ_ID_SIZE 16
83 #define PHY_POLL_LINK_ON (10 * HZ)
84 #define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
91 /* software context of a descriptor ring */
92 struct xgene_enet_desc_ring
{
93 struct net_device
*ndev
;
101 char irq_name
[IRQ_ID_SIZE
];
103 u32 state
[X2_NUM_RING_CONFIG
];
104 void __iomem
*cmd_base
;
107 dma_addr_t irq_mbox_dma
;
112 struct sk_buff
*(*rx_skb
);
113 struct sk_buff
*(*cp_skb
);
114 dma_addr_t
*frag_dma_addr
;
115 enum xgene_enet_ring_cfgsize cfgsize
;
116 struct xgene_enet_desc_ring
*cp_ring
;
117 struct xgene_enet_desc_ring
*buf_pool
;
118 struct napi_struct napi
;
121 struct xgene_enet_raw_desc
*raw_desc
;
122 struct xgene_enet_raw_desc16
*raw_desc16
;
131 u64 rx_length_errors
;
137 struct xgene_mac_ops
{
138 void (*init
)(struct xgene_enet_pdata
*pdata
);
139 void (*reset
)(struct xgene_enet_pdata
*pdata
);
140 void (*tx_enable
)(struct xgene_enet_pdata
*pdata
);
141 void (*rx_enable
)(struct xgene_enet_pdata
*pdata
);
142 void (*tx_disable
)(struct xgene_enet_pdata
*pdata
);
143 void (*rx_disable
)(struct xgene_enet_pdata
*pdata
);
144 void (*set_speed
)(struct xgene_enet_pdata
*pdata
);
145 void (*set_mac_addr
)(struct xgene_enet_pdata
*pdata
);
146 void (*set_mss
)(struct xgene_enet_pdata
*pdata
);
147 void (*link_state
)(struct work_struct
*work
);
150 struct xgene_port_ops
{
151 int (*reset
)(struct xgene_enet_pdata
*pdata
);
152 void (*clear
)(struct xgene_enet_pdata
*pdata
,
153 struct xgene_enet_desc_ring
*ring
);
154 void (*cle_bypass
)(struct xgene_enet_pdata
*pdata
,
155 u32 dst_ring_num
, u16 bufpool_id
);
156 void (*shutdown
)(struct xgene_enet_pdata
*pdata
);
159 struct xgene_ring_ops
{
161 u8 num_ring_id_shift
;
162 struct xgene_enet_desc_ring
* (*setup
)(struct xgene_enet_desc_ring
*);
163 void (*clear
)(struct xgene_enet_desc_ring
*);
164 void (*wr_cmd
)(struct xgene_enet_desc_ring
*, int);
165 u32 (*len
)(struct xgene_enet_desc_ring
*);
166 void (*coalesce
)(struct xgene_enet_desc_ring
*);
169 struct xgene_cle_ops
{
170 int (*cle_init
)(struct xgene_enet_pdata
*pdata
);
173 /* ethernet private data */
174 struct xgene_enet_pdata
{
175 struct net_device
*ndev
;
176 struct mii_bus
*mdio_bus
;
177 struct phy_device
*phy_dev
;
180 struct platform_device
*pdev
;
181 enum xgene_enet_id enet_id
;
182 struct xgene_enet_desc_ring
*tx_ring
[XGENE_NUM_TX_RING
];
183 struct xgene_enet_desc_ring
*rx_ring
[XGENE_NUM_RX_RING
];
184 u16 tx_level
[XGENE_NUM_TX_RING
];
185 u16 txc_level
[XGENE_NUM_TX_RING
];
189 u32 irqs
[XGENE_MAX_ENET_IRQ
];
193 void __iomem
*eth_csr_addr
;
194 void __iomem
*eth_ring_if_addr
;
195 void __iomem
*eth_diag_csr_addr
;
196 void __iomem
*mcx_mac_addr
;
197 void __iomem
*mcx_mac_csr_addr
;
198 void __iomem
*base_addr
;
199 void __iomem
*ring_csr_addr
;
200 void __iomem
*ring_cmd_addr
;
202 enum xgene_enet_rm rm
;
203 struct xgene_enet_cle cle
;
204 struct rtnl_link_stats64 stats
;
205 const struct xgene_mac_ops
*mac_ops
;
206 const struct xgene_port_ops
*port_ops
;
207 struct xgene_ring_ops
*ring_ops
;
208 const struct xgene_cle_ops
*cle_ops
;
209 struct delayed_work link_work
;
221 struct xgene_indirect_ctl
{
225 void __iomem
*cmd_done
;
228 static inline struct device
*ndev_to_dev(struct net_device
*ndev
)
230 return ndev
->dev
.parent
;
233 static inline u16
xgene_enet_dst_ring_num(struct xgene_enet_desc_ring
*ring
)
235 struct xgene_enet_pdata
*pdata
= netdev_priv(ring
->ndev
);
237 return ((u16
)pdata
->rm
<< 10) | ring
->num
;
240 void xgene_enet_set_ethtool_ops(struct net_device
*netdev
);
242 #endif /* __XGENE_ENET_MAIN_H__ */