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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.c
1 /* Broadcom NetXtreme-C/E network driver.
2 *
3 * Copyright (c) 2014-2016 Broadcom Corporation
4 * Copyright (c) 2016-2019 Broadcom Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12
13 #include <linux/stringify.h>
14 #include <linux/kernel.h>
15 #include <linux/timer.h>
16 #include <linux/errno.h>
17 #include <linux/ioport.h>
18 #include <linux/slab.h>
19 #include <linux/vmalloc.h>
20 #include <linux/interrupt.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/bitops.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/delay.h>
30 #include <asm/byteorder.h>
31 #include <asm/page.h>
32 #include <linux/time.h>
33 #include <linux/mii.h>
34 #include <linux/mdio.h>
35 #include <linux/if.h>
36 #include <linux/if_vlan.h>
37 #include <linux/if_bridge.h>
38 #include <linux/rtc.h>
39 #include <linux/bpf.h>
40 #include <net/ip.h>
41 #include <net/tcp.h>
42 #include <net/udp.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <net/udp_tunnel.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
53 #include <linux/cpumask.h>
54 #include <net/pkt_cls.h>
55 #include <linux/hwmon.h>
56 #include <linux/hwmon-sysfs.h>
57 #include <net/page_pool.h>
58
59 #include "bnxt_hsi.h"
60 #include "bnxt.h"
61 #include "bnxt_ulp.h"
62 #include "bnxt_sriov.h"
63 #include "bnxt_ethtool.h"
64 #include "bnxt_dcb.h"
65 #include "bnxt_xdp.h"
66 #include "bnxt_vfr.h"
67 #include "bnxt_tc.h"
68 #include "bnxt_devlink.h"
69 #include "bnxt_debugfs.h"
70
71 #define BNXT_TX_TIMEOUT (5 * HZ)
72 #define BNXT_DEF_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_HW)
73
74 MODULE_LICENSE("GPL");
75 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
76
77 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
78 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
79 #define BNXT_RX_COPY_THRESH 256
80
81 #define BNXT_TX_PUSH_THRESH 164
82
83 enum board_idx {
84 BCM57301,
85 BCM57302,
86 BCM57304,
87 BCM57417_NPAR,
88 BCM58700,
89 BCM57311,
90 BCM57312,
91 BCM57402,
92 BCM57404,
93 BCM57406,
94 BCM57402_NPAR,
95 BCM57407,
96 BCM57412,
97 BCM57414,
98 BCM57416,
99 BCM57417,
100 BCM57412_NPAR,
101 BCM57314,
102 BCM57417_SFP,
103 BCM57416_SFP,
104 BCM57404_NPAR,
105 BCM57406_NPAR,
106 BCM57407_SFP,
107 BCM57407_NPAR,
108 BCM57414_NPAR,
109 BCM57416_NPAR,
110 BCM57452,
111 BCM57454,
112 BCM5745x_NPAR,
113 BCM57508,
114 BCM57504,
115 BCM57502,
116 BCM57508_NPAR,
117 BCM57504_NPAR,
118 BCM57502_NPAR,
119 BCM58802,
120 BCM58804,
121 BCM58808,
122 NETXTREME_E_VF,
123 NETXTREME_C_VF,
124 NETXTREME_S_VF,
125 NETXTREME_E_P5_VF,
126 };
127
128 /* indexed by enum above */
129 static const struct {
130 char *name;
131 } board_info[] = {
132 [BCM57301] = { "Broadcom BCM57301 NetXtreme-C 10Gb Ethernet" },
133 [BCM57302] = { "Broadcom BCM57302 NetXtreme-C 10Gb/25Gb Ethernet" },
134 [BCM57304] = { "Broadcom BCM57304 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
135 [BCM57417_NPAR] = { "Broadcom BCM57417 NetXtreme-E Ethernet Partition" },
136 [BCM58700] = { "Broadcom BCM58700 Nitro 1Gb/2.5Gb/10Gb Ethernet" },
137 [BCM57311] = { "Broadcom BCM57311 NetXtreme-C 10Gb Ethernet" },
138 [BCM57312] = { "Broadcom BCM57312 NetXtreme-C 10Gb/25Gb Ethernet" },
139 [BCM57402] = { "Broadcom BCM57402 NetXtreme-E 10Gb Ethernet" },
140 [BCM57404] = { "Broadcom BCM57404 NetXtreme-E 10Gb/25Gb Ethernet" },
141 [BCM57406] = { "Broadcom BCM57406 NetXtreme-E 10GBase-T Ethernet" },
142 [BCM57402_NPAR] = { "Broadcom BCM57402 NetXtreme-E Ethernet Partition" },
143 [BCM57407] = { "Broadcom BCM57407 NetXtreme-E 10GBase-T Ethernet" },
144 [BCM57412] = { "Broadcom BCM57412 NetXtreme-E 10Gb Ethernet" },
145 [BCM57414] = { "Broadcom BCM57414 NetXtreme-E 10Gb/25Gb Ethernet" },
146 [BCM57416] = { "Broadcom BCM57416 NetXtreme-E 10GBase-T Ethernet" },
147 [BCM57417] = { "Broadcom BCM57417 NetXtreme-E 10GBase-T Ethernet" },
148 [BCM57412_NPAR] = { "Broadcom BCM57412 NetXtreme-E Ethernet Partition" },
149 [BCM57314] = { "Broadcom BCM57314 NetXtreme-C 10Gb/25Gb/40Gb/50Gb Ethernet" },
150 [BCM57417_SFP] = { "Broadcom BCM57417 NetXtreme-E 10Gb/25Gb Ethernet" },
151 [BCM57416_SFP] = { "Broadcom BCM57416 NetXtreme-E 10Gb Ethernet" },
152 [BCM57404_NPAR] = { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
153 [BCM57406_NPAR] = { "Broadcom BCM57406 NetXtreme-E Ethernet Partition" },
154 [BCM57407_SFP] = { "Broadcom BCM57407 NetXtreme-E 25Gb Ethernet" },
155 [BCM57407_NPAR] = { "Broadcom BCM57407 NetXtreme-E Ethernet Partition" },
156 [BCM57414_NPAR] = { "Broadcom BCM57414 NetXtreme-E Ethernet Partition" },
157 [BCM57416_NPAR] = { "Broadcom BCM57416 NetXtreme-E Ethernet Partition" },
158 [BCM57452] = { "Broadcom BCM57452 NetXtreme-E 10Gb/25Gb/40Gb/50Gb Ethernet" },
159 [BCM57454] = { "Broadcom BCM57454 NetXtreme-E 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
160 [BCM5745x_NPAR] = { "Broadcom BCM5745x NetXtreme-E Ethernet Partition" },
161 [BCM57508] = { "Broadcom BCM57508 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
162 [BCM57504] = { "Broadcom BCM57504 NetXtreme-E 10Gb/25Gb/50Gb/100Gb/200Gb Ethernet" },
163 [BCM57502] = { "Broadcom BCM57502 NetXtreme-E 10Gb/25Gb/50Gb Ethernet" },
164 [BCM57508_NPAR] = { "Broadcom BCM57508 NetXtreme-E Ethernet Partition" },
165 [BCM57504_NPAR] = { "Broadcom BCM57504 NetXtreme-E Ethernet Partition" },
166 [BCM57502_NPAR] = { "Broadcom BCM57502 NetXtreme-E Ethernet Partition" },
167 [BCM58802] = { "Broadcom BCM58802 NetXtreme-S 10Gb/25Gb/40Gb/50Gb Ethernet" },
168 [BCM58804] = { "Broadcom BCM58804 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
169 [BCM58808] = { "Broadcom BCM58808 NetXtreme-S 10Gb/25Gb/40Gb/50Gb/100Gb Ethernet" },
170 [NETXTREME_E_VF] = { "Broadcom NetXtreme-E Ethernet Virtual Function" },
171 [NETXTREME_C_VF] = { "Broadcom NetXtreme-C Ethernet Virtual Function" },
172 [NETXTREME_S_VF] = { "Broadcom NetXtreme-S Ethernet Virtual Function" },
173 [NETXTREME_E_P5_VF] = { "Broadcom BCM5750X NetXtreme-E Ethernet Virtual Function" },
174 };
175
176 static const struct pci_device_id bnxt_pci_tbl[] = {
177 { PCI_VDEVICE(BROADCOM, 0x1604), .driver_data = BCM5745x_NPAR },
178 { PCI_VDEVICE(BROADCOM, 0x1605), .driver_data = BCM5745x_NPAR },
179 { PCI_VDEVICE(BROADCOM, 0x1614), .driver_data = BCM57454 },
180 { PCI_VDEVICE(BROADCOM, 0x16c0), .driver_data = BCM57417_NPAR },
181 { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
182 { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
183 { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
184 { PCI_VDEVICE(BROADCOM, 0x16cc), .driver_data = BCM57417_NPAR },
185 { PCI_VDEVICE(BROADCOM, 0x16cd), .driver_data = BCM58700 },
186 { PCI_VDEVICE(BROADCOM, 0x16ce), .driver_data = BCM57311 },
187 { PCI_VDEVICE(BROADCOM, 0x16cf), .driver_data = BCM57312 },
188 { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
189 { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
190 { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
191 { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57402_NPAR },
192 { PCI_VDEVICE(BROADCOM, 0x16d5), .driver_data = BCM57407 },
193 { PCI_VDEVICE(BROADCOM, 0x16d6), .driver_data = BCM57412 },
194 { PCI_VDEVICE(BROADCOM, 0x16d7), .driver_data = BCM57414 },
195 { PCI_VDEVICE(BROADCOM, 0x16d8), .driver_data = BCM57416 },
196 { PCI_VDEVICE(BROADCOM, 0x16d9), .driver_data = BCM57417 },
197 { PCI_VDEVICE(BROADCOM, 0x16de), .driver_data = BCM57412_NPAR },
198 { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
199 { PCI_VDEVICE(BROADCOM, 0x16e2), .driver_data = BCM57417_SFP },
200 { PCI_VDEVICE(BROADCOM, 0x16e3), .driver_data = BCM57416_SFP },
201 { PCI_VDEVICE(BROADCOM, 0x16e7), .driver_data = BCM57404_NPAR },
202 { PCI_VDEVICE(BROADCOM, 0x16e8), .driver_data = BCM57406_NPAR },
203 { PCI_VDEVICE(BROADCOM, 0x16e9), .driver_data = BCM57407_SFP },
204 { PCI_VDEVICE(BROADCOM, 0x16ea), .driver_data = BCM57407_NPAR },
205 { PCI_VDEVICE(BROADCOM, 0x16eb), .driver_data = BCM57412_NPAR },
206 { PCI_VDEVICE(BROADCOM, 0x16ec), .driver_data = BCM57414_NPAR },
207 { PCI_VDEVICE(BROADCOM, 0x16ed), .driver_data = BCM57414_NPAR },
208 { PCI_VDEVICE(BROADCOM, 0x16ee), .driver_data = BCM57416_NPAR },
209 { PCI_VDEVICE(BROADCOM, 0x16ef), .driver_data = BCM57416_NPAR },
210 { PCI_VDEVICE(BROADCOM, 0x16f0), .driver_data = BCM58808 },
211 { PCI_VDEVICE(BROADCOM, 0x16f1), .driver_data = BCM57452 },
212 { PCI_VDEVICE(BROADCOM, 0x1750), .driver_data = BCM57508 },
213 { PCI_VDEVICE(BROADCOM, 0x1751), .driver_data = BCM57504 },
214 { PCI_VDEVICE(BROADCOM, 0x1752), .driver_data = BCM57502 },
215 { PCI_VDEVICE(BROADCOM, 0x1800), .driver_data = BCM57508_NPAR },
216 { PCI_VDEVICE(BROADCOM, 0x1801), .driver_data = BCM57504_NPAR },
217 { PCI_VDEVICE(BROADCOM, 0x1802), .driver_data = BCM57502_NPAR },
218 { PCI_VDEVICE(BROADCOM, 0x1803), .driver_data = BCM57508_NPAR },
219 { PCI_VDEVICE(BROADCOM, 0x1804), .driver_data = BCM57504_NPAR },
220 { PCI_VDEVICE(BROADCOM, 0x1805), .driver_data = BCM57502_NPAR },
221 { PCI_VDEVICE(BROADCOM, 0xd802), .driver_data = BCM58802 },
222 { PCI_VDEVICE(BROADCOM, 0xd804), .driver_data = BCM58804 },
223 #ifdef CONFIG_BNXT_SRIOV
224 { PCI_VDEVICE(BROADCOM, 0x1606), .driver_data = NETXTREME_E_VF },
225 { PCI_VDEVICE(BROADCOM, 0x1609), .driver_data = NETXTREME_E_VF },
226 { PCI_VDEVICE(BROADCOM, 0x16c1), .driver_data = NETXTREME_E_VF },
227 { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = NETXTREME_C_VF },
228 { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = NETXTREME_E_VF },
229 { PCI_VDEVICE(BROADCOM, 0x16dc), .driver_data = NETXTREME_E_VF },
230 { PCI_VDEVICE(BROADCOM, 0x16e1), .driver_data = NETXTREME_C_VF },
231 { PCI_VDEVICE(BROADCOM, 0x16e5), .driver_data = NETXTREME_C_VF },
232 { PCI_VDEVICE(BROADCOM, 0x1806), .driver_data = NETXTREME_E_P5_VF },
233 { PCI_VDEVICE(BROADCOM, 0x1807), .driver_data = NETXTREME_E_P5_VF },
234 { PCI_VDEVICE(BROADCOM, 0xd800), .driver_data = NETXTREME_S_VF },
235 #endif
236 { 0 }
237 };
238
239 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
240
241 static const u16 bnxt_vf_req_snif[] = {
242 HWRM_FUNC_CFG,
243 HWRM_FUNC_VF_CFG,
244 HWRM_PORT_PHY_QCFG,
245 HWRM_CFA_L2_FILTER_ALLOC,
246 };
247
248 static const u16 bnxt_async_events_arr[] = {
249 ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
250 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE,
251 ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
252 ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
253 ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
254 ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
255 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE,
256 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY,
257 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY,
258 ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION,
259 ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG,
260 ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST,
261 };
262
263 static struct workqueue_struct *bnxt_pf_wq;
264
265 static bool bnxt_vf_pciid(enum board_idx idx)
266 {
267 return (idx == NETXTREME_C_VF || idx == NETXTREME_E_VF ||
268 idx == NETXTREME_S_VF || idx == NETXTREME_E_P5_VF);
269 }
270
271 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
272 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
273 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
274
275 #define BNXT_CP_DB_IRQ_DIS(db) \
276 writel(DB_CP_IRQ_DIS_FLAGS, db)
277
278 #define BNXT_DB_CQ(db, idx) \
279 writel(DB_CP_FLAGS | RING_CMP(idx), (db)->doorbell)
280
281 #define BNXT_DB_NQ_P5(db, idx) \
282 writeq((db)->db_key64 | DBR_TYPE_NQ | RING_CMP(idx), (db)->doorbell)
283
284 #define BNXT_DB_CQ_ARM(db, idx) \
285 writel(DB_CP_REARM_FLAGS | RING_CMP(idx), (db)->doorbell)
286
287 #define BNXT_DB_NQ_ARM_P5(db, idx) \
288 writeq((db)->db_key64 | DBR_TYPE_NQ_ARM | RING_CMP(idx), (db)->doorbell)
289
290 static void bnxt_db_nq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
291 {
292 if (bp->flags & BNXT_FLAG_CHIP_P5)
293 BNXT_DB_NQ_P5(db, idx);
294 else
295 BNXT_DB_CQ(db, idx);
296 }
297
298 static void bnxt_db_nq_arm(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
299 {
300 if (bp->flags & BNXT_FLAG_CHIP_P5)
301 BNXT_DB_NQ_ARM_P5(db, idx);
302 else
303 BNXT_DB_CQ_ARM(db, idx);
304 }
305
306 static void bnxt_db_cq(struct bnxt *bp, struct bnxt_db_info *db, u32 idx)
307 {
308 if (bp->flags & BNXT_FLAG_CHIP_P5)
309 writeq(db->db_key64 | DBR_TYPE_CQ_ARMALL | RING_CMP(idx),
310 db->doorbell);
311 else
312 BNXT_DB_CQ(db, idx);
313 }
314
315 const u16 bnxt_lhint_arr[] = {
316 TX_BD_FLAGS_LHINT_512_AND_SMALLER,
317 TX_BD_FLAGS_LHINT_512_TO_1023,
318 TX_BD_FLAGS_LHINT_1024_TO_2047,
319 TX_BD_FLAGS_LHINT_1024_TO_2047,
320 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
321 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
322 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
323 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
324 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
325 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
326 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
327 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
328 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
329 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
330 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
331 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
332 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
333 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
334 TX_BD_FLAGS_LHINT_2048_AND_LARGER,
335 };
336
337 static u16 bnxt_xmit_get_cfa_action(struct sk_buff *skb)
338 {
339 struct metadata_dst *md_dst = skb_metadata_dst(skb);
340
341 if (!md_dst || md_dst->type != METADATA_HW_PORT_MUX)
342 return 0;
343
344 return md_dst->u.port_info.port_id;
345 }
346
347 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
348 {
349 struct bnxt *bp = netdev_priv(dev);
350 struct tx_bd *txbd;
351 struct tx_bd_ext *txbd1;
352 struct netdev_queue *txq;
353 int i;
354 dma_addr_t mapping;
355 unsigned int length, pad = 0;
356 u32 len, free_size, vlan_tag_flags, cfa_action, flags;
357 u16 prod, last_frag;
358 struct pci_dev *pdev = bp->pdev;
359 struct bnxt_tx_ring_info *txr;
360 struct bnxt_sw_tx_bd *tx_buf;
361
362 i = skb_get_queue_mapping(skb);
363 if (unlikely(i >= bp->tx_nr_rings)) {
364 dev_kfree_skb_any(skb);
365 return NETDEV_TX_OK;
366 }
367
368 txq = netdev_get_tx_queue(dev, i);
369 txr = &bp->tx_ring[bp->tx_ring_map[i]];
370 prod = txr->tx_prod;
371
372 free_size = bnxt_tx_avail(bp, txr);
373 if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
374 netif_tx_stop_queue(txq);
375 return NETDEV_TX_BUSY;
376 }
377
378 length = skb->len;
379 len = skb_headlen(skb);
380 last_frag = skb_shinfo(skb)->nr_frags;
381
382 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
383
384 txbd->tx_bd_opaque = prod;
385
386 tx_buf = &txr->tx_buf_ring[prod];
387 tx_buf->skb = skb;
388 tx_buf->nr_frags = last_frag;
389
390 vlan_tag_flags = 0;
391 cfa_action = bnxt_xmit_get_cfa_action(skb);
392 if (skb_vlan_tag_present(skb)) {
393 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
394 skb_vlan_tag_get(skb);
395 /* Currently supports 8021Q, 8021AD vlan offloads
396 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
397 */
398 if (skb->vlan_proto == htons(ETH_P_8021Q))
399 vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
400 }
401
402 if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
403 struct tx_push_buffer *tx_push_buf = txr->tx_push;
404 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
405 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
406 void __iomem *db = txr->tx_db.doorbell;
407 void *pdata = tx_push_buf->data;
408 u64 *end;
409 int j, push_len;
410
411 /* Set COAL_NOW to be ready quickly for the next push */
412 tx_push->tx_bd_len_flags_type =
413 cpu_to_le32((length << TX_BD_LEN_SHIFT) |
414 TX_BD_TYPE_LONG_TX_BD |
415 TX_BD_FLAGS_LHINT_512_AND_SMALLER |
416 TX_BD_FLAGS_COAL_NOW |
417 TX_BD_FLAGS_PACKET_END |
418 (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
419
420 if (skb->ip_summed == CHECKSUM_PARTIAL)
421 tx_push1->tx_bd_hsize_lflags =
422 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
423 else
424 tx_push1->tx_bd_hsize_lflags = 0;
425
426 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
427 tx_push1->tx_bd_cfa_action =
428 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
429
430 end = pdata + length;
431 end = PTR_ALIGN(end, 8) - 1;
432 *end = 0;
433
434 skb_copy_from_linear_data(skb, pdata, len);
435 pdata += len;
436 for (j = 0; j < last_frag; j++) {
437 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
438 void *fptr;
439
440 fptr = skb_frag_address_safe(frag);
441 if (!fptr)
442 goto normal_tx;
443
444 memcpy(pdata, fptr, skb_frag_size(frag));
445 pdata += skb_frag_size(frag);
446 }
447
448 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
449 txbd->tx_bd_haddr = txr->data_mapping;
450 prod = NEXT_TX(prod);
451 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
452 memcpy(txbd, tx_push1, sizeof(*txbd));
453 prod = NEXT_TX(prod);
454 tx_push->doorbell =
455 cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
456 txr->tx_prod = prod;
457
458 tx_buf->is_push = 1;
459 netdev_tx_sent_queue(txq, skb->len);
460 wmb(); /* Sync is_push and byte queue before pushing data */
461
462 push_len = (length + sizeof(*tx_push) + 7) / 8;
463 if (push_len > 16) {
464 __iowrite64_copy(db, tx_push_buf, 16);
465 __iowrite32_copy(db + 4, tx_push_buf + 1,
466 (push_len - 16) << 1);
467 } else {
468 __iowrite64_copy(db, tx_push_buf, push_len);
469 }
470
471 goto tx_done;
472 }
473
474 normal_tx:
475 if (length < BNXT_MIN_PKT_SIZE) {
476 pad = BNXT_MIN_PKT_SIZE - length;
477 if (skb_pad(skb, pad)) {
478 /* SKB already freed. */
479 tx_buf->skb = NULL;
480 return NETDEV_TX_OK;
481 }
482 length = BNXT_MIN_PKT_SIZE;
483 }
484
485 mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
486
487 if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
488 dev_kfree_skb_any(skb);
489 tx_buf->skb = NULL;
490 return NETDEV_TX_OK;
491 }
492
493 dma_unmap_addr_set(tx_buf, mapping, mapping);
494 flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
495 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
496
497 txbd->tx_bd_haddr = cpu_to_le64(mapping);
498
499 prod = NEXT_TX(prod);
500 txbd1 = (struct tx_bd_ext *)
501 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
502
503 txbd1->tx_bd_hsize_lflags = 0;
504 if (skb_is_gso(skb)) {
505 u32 hdr_len;
506
507 if (skb->encapsulation)
508 hdr_len = skb_inner_network_offset(skb) +
509 skb_inner_network_header_len(skb) +
510 inner_tcp_hdrlen(skb);
511 else
512 hdr_len = skb_transport_offset(skb) +
513 tcp_hdrlen(skb);
514
515 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
516 TX_BD_FLAGS_T_IPID |
517 (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
518 length = skb_shinfo(skb)->gso_size;
519 txbd1->tx_bd_mss = cpu_to_le32(length);
520 length += hdr_len;
521 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
522 txbd1->tx_bd_hsize_lflags =
523 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
524 txbd1->tx_bd_mss = 0;
525 }
526
527 length >>= 9;
528 if (unlikely(length >= ARRAY_SIZE(bnxt_lhint_arr))) {
529 dev_warn_ratelimited(&pdev->dev, "Dropped oversize %d bytes TX packet.\n",
530 skb->len);
531 i = 0;
532 goto tx_dma_error;
533 }
534 flags |= bnxt_lhint_arr[length];
535 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
536
537 txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
538 txbd1->tx_bd_cfa_action =
539 cpu_to_le32(cfa_action << TX_BD_CFA_ACTION_SHIFT);
540 for (i = 0; i < last_frag; i++) {
541 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
542
543 prod = NEXT_TX(prod);
544 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
545
546 len = skb_frag_size(frag);
547 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
548 DMA_TO_DEVICE);
549
550 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
551 goto tx_dma_error;
552
553 tx_buf = &txr->tx_buf_ring[prod];
554 dma_unmap_addr_set(tx_buf, mapping, mapping);
555
556 txbd->tx_bd_haddr = cpu_to_le64(mapping);
557
558 flags = len << TX_BD_LEN_SHIFT;
559 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
560 }
561
562 flags &= ~TX_BD_LEN;
563 txbd->tx_bd_len_flags_type =
564 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
565 TX_BD_FLAGS_PACKET_END);
566
567 netdev_tx_sent_queue(txq, skb->len);
568
569 /* Sync BD data before updating doorbell */
570 wmb();
571
572 prod = NEXT_TX(prod);
573 txr->tx_prod = prod;
574
575 if (!netdev_xmit_more() || netif_xmit_stopped(txq))
576 bnxt_db_write(bp, &txr->tx_db, prod);
577
578 tx_done:
579
580 if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
581 if (netdev_xmit_more() && !tx_buf->is_push)
582 bnxt_db_write(bp, &txr->tx_db, prod);
583
584 netif_tx_stop_queue(txq);
585
586 /* netif_tx_stop_queue() must be done before checking
587 * tx index in bnxt_tx_avail() below, because in
588 * bnxt_tx_int(), we update tx index before checking for
589 * netif_tx_queue_stopped().
590 */
591 smp_mb();
592 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
593 netif_tx_wake_queue(txq);
594 }
595 return NETDEV_TX_OK;
596
597 tx_dma_error:
598 last_frag = i;
599
600 /* start back at beginning and unmap skb */
601 prod = txr->tx_prod;
602 tx_buf = &txr->tx_buf_ring[prod];
603 tx_buf->skb = NULL;
604 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
605 skb_headlen(skb), PCI_DMA_TODEVICE);
606 prod = NEXT_TX(prod);
607
608 /* unmap remaining mapped pages */
609 for (i = 0; i < last_frag; i++) {
610 prod = NEXT_TX(prod);
611 tx_buf = &txr->tx_buf_ring[prod];
612 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
613 skb_frag_size(&skb_shinfo(skb)->frags[i]),
614 PCI_DMA_TODEVICE);
615 }
616
617 dev_kfree_skb_any(skb);
618 return NETDEV_TX_OK;
619 }
620
621 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
622 {
623 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
624 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, txr->txq_index);
625 u16 cons = txr->tx_cons;
626 struct pci_dev *pdev = bp->pdev;
627 int i;
628 unsigned int tx_bytes = 0;
629
630 for (i = 0; i < nr_pkts; i++) {
631 struct bnxt_sw_tx_bd *tx_buf;
632 struct sk_buff *skb;
633 int j, last;
634
635 tx_buf = &txr->tx_buf_ring[cons];
636 cons = NEXT_TX(cons);
637 skb = tx_buf->skb;
638 tx_buf->skb = NULL;
639
640 if (tx_buf->is_push) {
641 tx_buf->is_push = 0;
642 goto next_tx_int;
643 }
644
645 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
646 skb_headlen(skb), PCI_DMA_TODEVICE);
647 last = tx_buf->nr_frags;
648
649 for (j = 0; j < last; j++) {
650 cons = NEXT_TX(cons);
651 tx_buf = &txr->tx_buf_ring[cons];
652 dma_unmap_page(
653 &pdev->dev,
654 dma_unmap_addr(tx_buf, mapping),
655 skb_frag_size(&skb_shinfo(skb)->frags[j]),
656 PCI_DMA_TODEVICE);
657 }
658
659 next_tx_int:
660 cons = NEXT_TX(cons);
661
662 tx_bytes += skb->len;
663 dev_kfree_skb_any(skb);
664 }
665
666 netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
667 txr->tx_cons = cons;
668
669 /* Need to make the tx_cons update visible to bnxt_start_xmit()
670 * before checking for netif_tx_queue_stopped(). Without the
671 * memory barrier, there is a small possibility that bnxt_start_xmit()
672 * will miss it and cause the queue to be stopped forever.
673 */
674 smp_mb();
675
676 if (unlikely(netif_tx_queue_stopped(txq)) &&
677 (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
678 __netif_tx_lock(txq, smp_processor_id());
679 if (netif_tx_queue_stopped(txq) &&
680 bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
681 txr->dev_state != BNXT_DEV_STATE_CLOSING)
682 netif_tx_wake_queue(txq);
683 __netif_tx_unlock(txq);
684 }
685 }
686
687 static struct page *__bnxt_alloc_rx_page(struct bnxt *bp, dma_addr_t *mapping,
688 struct bnxt_rx_ring_info *rxr,
689 gfp_t gfp)
690 {
691 struct device *dev = &bp->pdev->dev;
692 struct page *page;
693
694 page = page_pool_dev_alloc_pages(rxr->page_pool);
695 if (!page)
696 return NULL;
697
698 *mapping = dma_map_page_attrs(dev, page, 0, PAGE_SIZE, bp->rx_dir,
699 DMA_ATTR_WEAK_ORDERING);
700 if (dma_mapping_error(dev, *mapping)) {
701 page_pool_recycle_direct(rxr->page_pool, page);
702 return NULL;
703 }
704 *mapping += bp->rx_dma_offset;
705 return page;
706 }
707
708 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
709 gfp_t gfp)
710 {
711 u8 *data;
712 struct pci_dev *pdev = bp->pdev;
713
714 data = kmalloc(bp->rx_buf_size, gfp);
715 if (!data)
716 return NULL;
717
718 *mapping = dma_map_single_attrs(&pdev->dev, data + bp->rx_dma_offset,
719 bp->rx_buf_use_size, bp->rx_dir,
720 DMA_ATTR_WEAK_ORDERING);
721
722 if (dma_mapping_error(&pdev->dev, *mapping)) {
723 kfree(data);
724 data = NULL;
725 }
726 return data;
727 }
728
729 int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
730 u16 prod, gfp_t gfp)
731 {
732 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
733 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
734 dma_addr_t mapping;
735
736 if (BNXT_RX_PAGE_MODE(bp)) {
737 struct page *page =
738 __bnxt_alloc_rx_page(bp, &mapping, rxr, gfp);
739
740 if (!page)
741 return -ENOMEM;
742
743 rx_buf->data = page;
744 rx_buf->data_ptr = page_address(page) + bp->rx_offset;
745 } else {
746 u8 *data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
747
748 if (!data)
749 return -ENOMEM;
750
751 rx_buf->data = data;
752 rx_buf->data_ptr = data + bp->rx_offset;
753 }
754 rx_buf->mapping = mapping;
755
756 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
757 return 0;
758 }
759
760 void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data)
761 {
762 u16 prod = rxr->rx_prod;
763 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
764 struct rx_bd *cons_bd, *prod_bd;
765
766 prod_rx_buf = &rxr->rx_buf_ring[prod];
767 cons_rx_buf = &rxr->rx_buf_ring[cons];
768
769 prod_rx_buf->data = data;
770 prod_rx_buf->data_ptr = cons_rx_buf->data_ptr;
771
772 prod_rx_buf->mapping = cons_rx_buf->mapping;
773
774 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
775 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
776
777 prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
778 }
779
780 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
781 {
782 u16 next, max = rxr->rx_agg_bmap_size;
783
784 next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
785 if (next >= max)
786 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
787 return next;
788 }
789
790 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
791 struct bnxt_rx_ring_info *rxr,
792 u16 prod, gfp_t gfp)
793 {
794 struct rx_bd *rxbd =
795 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
796 struct bnxt_sw_rx_agg_bd *rx_agg_buf;
797 struct pci_dev *pdev = bp->pdev;
798 struct page *page;
799 dma_addr_t mapping;
800 u16 sw_prod = rxr->rx_sw_agg_prod;
801 unsigned int offset = 0;
802
803 if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
804 page = rxr->rx_page;
805 if (!page) {
806 page = alloc_page(gfp);
807 if (!page)
808 return -ENOMEM;
809 rxr->rx_page = page;
810 rxr->rx_page_offset = 0;
811 }
812 offset = rxr->rx_page_offset;
813 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
814 if (rxr->rx_page_offset == PAGE_SIZE)
815 rxr->rx_page = NULL;
816 else
817 get_page(page);
818 } else {
819 page = alloc_page(gfp);
820 if (!page)
821 return -ENOMEM;
822 }
823
824 mapping = dma_map_page_attrs(&pdev->dev, page, offset,
825 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
826 DMA_ATTR_WEAK_ORDERING);
827 if (dma_mapping_error(&pdev->dev, mapping)) {
828 __free_page(page);
829 return -EIO;
830 }
831
832 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
833 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
834
835 __set_bit(sw_prod, rxr->rx_agg_bmap);
836 rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
837 rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
838
839 rx_agg_buf->page = page;
840 rx_agg_buf->offset = offset;
841 rx_agg_buf->mapping = mapping;
842 rxbd->rx_bd_haddr = cpu_to_le64(mapping);
843 rxbd->rx_bd_opaque = sw_prod;
844 return 0;
845 }
846
847 static struct rx_agg_cmp *bnxt_get_agg(struct bnxt *bp,
848 struct bnxt_cp_ring_info *cpr,
849 u16 cp_cons, u16 curr)
850 {
851 struct rx_agg_cmp *agg;
852
853 cp_cons = RING_CMP(ADV_RAW_CMP(cp_cons, curr));
854 agg = (struct rx_agg_cmp *)
855 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
856 return agg;
857 }
858
859 static struct rx_agg_cmp *bnxt_get_tpa_agg_p5(struct bnxt *bp,
860 struct bnxt_rx_ring_info *rxr,
861 u16 agg_id, u16 curr)
862 {
863 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[agg_id];
864
865 return &tpa_info->agg_arr[curr];
866 }
867
868 static void bnxt_reuse_rx_agg_bufs(struct bnxt_cp_ring_info *cpr, u16 idx,
869 u16 start, u32 agg_bufs, bool tpa)
870 {
871 struct bnxt_napi *bnapi = cpr->bnapi;
872 struct bnxt *bp = bnapi->bp;
873 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
874 u16 prod = rxr->rx_agg_prod;
875 u16 sw_prod = rxr->rx_sw_agg_prod;
876 bool p5_tpa = false;
877 u32 i;
878
879 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
880 p5_tpa = true;
881
882 for (i = 0; i < agg_bufs; i++) {
883 u16 cons;
884 struct rx_agg_cmp *agg;
885 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
886 struct rx_bd *prod_bd;
887 struct page *page;
888
889 if (p5_tpa)
890 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, start + i);
891 else
892 agg = bnxt_get_agg(bp, cpr, idx, start + i);
893 cons = agg->rx_agg_cmp_opaque;
894 __clear_bit(cons, rxr->rx_agg_bmap);
895
896 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
897 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
898
899 __set_bit(sw_prod, rxr->rx_agg_bmap);
900 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
901 cons_rx_buf = &rxr->rx_agg_ring[cons];
902
903 /* It is possible for sw_prod to be equal to cons, so
904 * set cons_rx_buf->page to NULL first.
905 */
906 page = cons_rx_buf->page;
907 cons_rx_buf->page = NULL;
908 prod_rx_buf->page = page;
909 prod_rx_buf->offset = cons_rx_buf->offset;
910
911 prod_rx_buf->mapping = cons_rx_buf->mapping;
912
913 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
914
915 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
916 prod_bd->rx_bd_opaque = sw_prod;
917
918 prod = NEXT_RX_AGG(prod);
919 sw_prod = NEXT_RX_AGG(sw_prod);
920 }
921 rxr->rx_agg_prod = prod;
922 rxr->rx_sw_agg_prod = sw_prod;
923 }
924
925 static struct sk_buff *bnxt_rx_page_skb(struct bnxt *bp,
926 struct bnxt_rx_ring_info *rxr,
927 u16 cons, void *data, u8 *data_ptr,
928 dma_addr_t dma_addr,
929 unsigned int offset_and_len)
930 {
931 unsigned int payload = offset_and_len >> 16;
932 unsigned int len = offset_and_len & 0xffff;
933 skb_frag_t *frag;
934 struct page *page = data;
935 u16 prod = rxr->rx_prod;
936 struct sk_buff *skb;
937 int off, err;
938
939 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
940 if (unlikely(err)) {
941 bnxt_reuse_rx_data(rxr, cons, data);
942 return NULL;
943 }
944 dma_addr -= bp->rx_dma_offset;
945 dma_unmap_page_attrs(&bp->pdev->dev, dma_addr, PAGE_SIZE, bp->rx_dir,
946 DMA_ATTR_WEAK_ORDERING);
947 page_pool_release_page(rxr->page_pool, page);
948
949 if (unlikely(!payload))
950 payload = eth_get_headlen(bp->dev, data_ptr, len);
951
952 skb = napi_alloc_skb(&rxr->bnapi->napi, payload);
953 if (!skb) {
954 __free_page(page);
955 return NULL;
956 }
957
958 off = (void *)data_ptr - page_address(page);
959 skb_add_rx_frag(skb, 0, page, off, len, PAGE_SIZE);
960 memcpy(skb->data - NET_IP_ALIGN, data_ptr - NET_IP_ALIGN,
961 payload + NET_IP_ALIGN);
962
963 frag = &skb_shinfo(skb)->frags[0];
964 skb_frag_size_sub(frag, payload);
965 skb_frag_off_add(frag, payload);
966 skb->data_len -= payload;
967 skb->tail += payload;
968
969 return skb;
970 }
971
972 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
973 struct bnxt_rx_ring_info *rxr, u16 cons,
974 void *data, u8 *data_ptr,
975 dma_addr_t dma_addr,
976 unsigned int offset_and_len)
977 {
978 u16 prod = rxr->rx_prod;
979 struct sk_buff *skb;
980 int err;
981
982 err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
983 if (unlikely(err)) {
984 bnxt_reuse_rx_data(rxr, cons, data);
985 return NULL;
986 }
987
988 skb = build_skb(data, 0);
989 dma_unmap_single_attrs(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
990 bp->rx_dir, DMA_ATTR_WEAK_ORDERING);
991 if (!skb) {
992 kfree(data);
993 return NULL;
994 }
995
996 skb_reserve(skb, bp->rx_offset);
997 skb_put(skb, offset_and_len & 0xffff);
998 return skb;
999 }
1000
1001 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp,
1002 struct bnxt_cp_ring_info *cpr,
1003 struct sk_buff *skb, u16 idx,
1004 u32 agg_bufs, bool tpa)
1005 {
1006 struct bnxt_napi *bnapi = cpr->bnapi;
1007 struct pci_dev *pdev = bp->pdev;
1008 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1009 u16 prod = rxr->rx_agg_prod;
1010 bool p5_tpa = false;
1011 u32 i;
1012
1013 if ((bp->flags & BNXT_FLAG_CHIP_P5) && tpa)
1014 p5_tpa = true;
1015
1016 for (i = 0; i < agg_bufs; i++) {
1017 u16 cons, frag_len;
1018 struct rx_agg_cmp *agg;
1019 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
1020 struct page *page;
1021 dma_addr_t mapping;
1022
1023 if (p5_tpa)
1024 agg = bnxt_get_tpa_agg_p5(bp, rxr, idx, i);
1025 else
1026 agg = bnxt_get_agg(bp, cpr, idx, i);
1027 cons = agg->rx_agg_cmp_opaque;
1028 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
1029 RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
1030
1031 cons_rx_buf = &rxr->rx_agg_ring[cons];
1032 skb_fill_page_desc(skb, i, cons_rx_buf->page,
1033 cons_rx_buf->offset, frag_len);
1034 __clear_bit(cons, rxr->rx_agg_bmap);
1035
1036 /* It is possible for bnxt_alloc_rx_page() to allocate
1037 * a sw_prod index that equals the cons index, so we
1038 * need to clear the cons entry now.
1039 */
1040 mapping = cons_rx_buf->mapping;
1041 page = cons_rx_buf->page;
1042 cons_rx_buf->page = NULL;
1043
1044 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
1045 struct skb_shared_info *shinfo;
1046 unsigned int nr_frags;
1047
1048 shinfo = skb_shinfo(skb);
1049 nr_frags = --shinfo->nr_frags;
1050 __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
1051
1052 dev_kfree_skb(skb);
1053
1054 cons_rx_buf->page = page;
1055
1056 /* Update prod since possibly some pages have been
1057 * allocated already.
1058 */
1059 rxr->rx_agg_prod = prod;
1060 bnxt_reuse_rx_agg_bufs(cpr, idx, i, agg_bufs - i, tpa);
1061 return NULL;
1062 }
1063
1064 dma_unmap_page_attrs(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
1065 PCI_DMA_FROMDEVICE,
1066 DMA_ATTR_WEAK_ORDERING);
1067
1068 skb->data_len += frag_len;
1069 skb->len += frag_len;
1070 skb->truesize += PAGE_SIZE;
1071
1072 prod = NEXT_RX_AGG(prod);
1073 }
1074 rxr->rx_agg_prod = prod;
1075 return skb;
1076 }
1077
1078 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1079 u8 agg_bufs, u32 *raw_cons)
1080 {
1081 u16 last;
1082 struct rx_agg_cmp *agg;
1083
1084 *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
1085 last = RING_CMP(*raw_cons);
1086 agg = (struct rx_agg_cmp *)
1087 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
1088 return RX_AGG_CMP_VALID(agg, *raw_cons);
1089 }
1090
1091 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
1092 unsigned int len,
1093 dma_addr_t mapping)
1094 {
1095 struct bnxt *bp = bnapi->bp;
1096 struct pci_dev *pdev = bp->pdev;
1097 struct sk_buff *skb;
1098
1099 skb = napi_alloc_skb(&bnapi->napi, len);
1100 if (!skb)
1101 return NULL;
1102
1103 dma_sync_single_for_cpu(&pdev->dev, mapping, bp->rx_copy_thresh,
1104 bp->rx_dir);
1105
1106 memcpy(skb->data - NET_IP_ALIGN, data - NET_IP_ALIGN,
1107 len + NET_IP_ALIGN);
1108
1109 dma_sync_single_for_device(&pdev->dev, mapping, bp->rx_copy_thresh,
1110 bp->rx_dir);
1111
1112 skb_put(skb, len);
1113 return skb;
1114 }
1115
1116 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1117 u32 *raw_cons, void *cmp)
1118 {
1119 struct rx_cmp *rxcmp = cmp;
1120 u32 tmp_raw_cons = *raw_cons;
1121 u8 cmp_type, agg_bufs = 0;
1122
1123 cmp_type = RX_CMP_TYPE(rxcmp);
1124
1125 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1126 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
1127 RX_CMP_AGG_BUFS) >>
1128 RX_CMP_AGG_BUFS_SHIFT;
1129 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1130 struct rx_tpa_end_cmp *tpa_end = cmp;
1131
1132 if (bp->flags & BNXT_FLAG_CHIP_P5)
1133 return 0;
1134
1135 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1136 }
1137
1138 if (agg_bufs) {
1139 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1140 return -EBUSY;
1141 }
1142 *raw_cons = tmp_raw_cons;
1143 return 0;
1144 }
1145
1146 static void bnxt_queue_fw_reset_work(struct bnxt *bp, unsigned long delay)
1147 {
1148 if (!(test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)))
1149 return;
1150
1151 if (BNXT_PF(bp))
1152 queue_delayed_work(bnxt_pf_wq, &bp->fw_reset_task, delay);
1153 else
1154 schedule_delayed_work(&bp->fw_reset_task, delay);
1155 }
1156
1157 static void bnxt_queue_sp_work(struct bnxt *bp)
1158 {
1159 if (BNXT_PF(bp))
1160 queue_work(bnxt_pf_wq, &bp->sp_task);
1161 else
1162 schedule_work(&bp->sp_task);
1163 }
1164
1165 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
1166 {
1167 if (!rxr->bnapi->in_reset) {
1168 rxr->bnapi->in_reset = true;
1169 if (bp->flags & BNXT_FLAG_CHIP_P5)
1170 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
1171 else
1172 set_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event);
1173 bnxt_queue_sp_work(bp);
1174 }
1175 rxr->rx_next_cons = 0xffff;
1176 }
1177
1178 static u16 bnxt_alloc_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1179 {
1180 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1181 u16 idx = agg_id & MAX_TPA_P5_MASK;
1182
1183 if (test_bit(idx, map->agg_idx_bmap))
1184 idx = find_first_zero_bit(map->agg_idx_bmap,
1185 BNXT_AGG_IDX_BMAP_SIZE);
1186 __set_bit(idx, map->agg_idx_bmap);
1187 map->agg_id_tbl[agg_id] = idx;
1188 return idx;
1189 }
1190
1191 static void bnxt_free_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
1192 {
1193 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1194
1195 __clear_bit(idx, map->agg_idx_bmap);
1196 }
1197
1198 static u16 bnxt_lookup_agg_idx(struct bnxt_rx_ring_info *rxr, u16 agg_id)
1199 {
1200 struct bnxt_tpa_idx_map *map = rxr->rx_tpa_idx_map;
1201
1202 return map->agg_id_tbl[agg_id];
1203 }
1204
1205 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1206 struct rx_tpa_start_cmp *tpa_start,
1207 struct rx_tpa_start_cmp_ext *tpa_start1)
1208 {
1209 struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
1210 struct bnxt_tpa_info *tpa_info;
1211 u16 cons, prod, agg_id;
1212 struct rx_bd *prod_bd;
1213 dma_addr_t mapping;
1214
1215 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1216 agg_id = TPA_START_AGG_ID_P5(tpa_start);
1217 agg_id = bnxt_alloc_agg_idx(rxr, agg_id);
1218 } else {
1219 agg_id = TPA_START_AGG_ID(tpa_start);
1220 }
1221 cons = tpa_start->rx_tpa_start_cmp_opaque;
1222 prod = rxr->rx_prod;
1223 cons_rx_buf = &rxr->rx_buf_ring[cons];
1224 prod_rx_buf = &rxr->rx_buf_ring[prod];
1225 tpa_info = &rxr->rx_tpa[agg_id];
1226
1227 if (unlikely(cons != rxr->rx_next_cons ||
1228 TPA_START_ERROR(tpa_start))) {
1229 netdev_warn(bp->dev, "TPA cons %x, expected cons %x, error code %x\n",
1230 cons, rxr->rx_next_cons,
1231 TPA_START_ERROR_CODE(tpa_start1));
1232 bnxt_sched_reset(bp, rxr);
1233 return;
1234 }
1235 /* Store cfa_code in tpa_info to use in tpa_end
1236 * completion processing.
1237 */
1238 tpa_info->cfa_code = TPA_START_CFA_CODE(tpa_start1);
1239 prod_rx_buf->data = tpa_info->data;
1240 prod_rx_buf->data_ptr = tpa_info->data_ptr;
1241
1242 mapping = tpa_info->mapping;
1243 prod_rx_buf->mapping = mapping;
1244
1245 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1246
1247 prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
1248
1249 tpa_info->data = cons_rx_buf->data;
1250 tpa_info->data_ptr = cons_rx_buf->data_ptr;
1251 cons_rx_buf->data = NULL;
1252 tpa_info->mapping = cons_rx_buf->mapping;
1253
1254 tpa_info->len =
1255 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
1256 RX_TPA_START_CMP_LEN_SHIFT;
1257 if (likely(TPA_START_HASH_VALID(tpa_start))) {
1258 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
1259
1260 tpa_info->hash_type = PKT_HASH_TYPE_L4;
1261 tpa_info->gso_type = SKB_GSO_TCPV4;
1262 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1263 if (hash_type == 3 || TPA_START_IS_IPV6(tpa_start1))
1264 tpa_info->gso_type = SKB_GSO_TCPV6;
1265 tpa_info->rss_hash =
1266 le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
1267 } else {
1268 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
1269 tpa_info->gso_type = 0;
1270 netif_warn(bp, rx_err, bp->dev, "TPA packet without valid hash\n");
1271 }
1272 tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
1273 tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
1274 tpa_info->hdr_info = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_hdr_info);
1275 tpa_info->agg_count = 0;
1276
1277 rxr->rx_prod = NEXT_RX(prod);
1278 cons = NEXT_RX(cons);
1279 rxr->rx_next_cons = NEXT_RX(cons);
1280 cons_rx_buf = &rxr->rx_buf_ring[cons];
1281
1282 bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
1283 rxr->rx_prod = NEXT_RX(rxr->rx_prod);
1284 cons_rx_buf->data = NULL;
1285 }
1286
1287 static void bnxt_abort_tpa(struct bnxt_cp_ring_info *cpr, u16 idx, u32 agg_bufs)
1288 {
1289 if (agg_bufs)
1290 bnxt_reuse_rx_agg_bufs(cpr, idx, 0, agg_bufs, true);
1291 }
1292
1293 #ifdef CONFIG_INET
1294 static void bnxt_gro_tunnel(struct sk_buff *skb, __be16 ip_proto)
1295 {
1296 struct udphdr *uh = NULL;
1297
1298 if (ip_proto == htons(ETH_P_IP)) {
1299 struct iphdr *iph = (struct iphdr *)skb->data;
1300
1301 if (iph->protocol == IPPROTO_UDP)
1302 uh = (struct udphdr *)(iph + 1);
1303 } else {
1304 struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1305
1306 if (iph->nexthdr == IPPROTO_UDP)
1307 uh = (struct udphdr *)(iph + 1);
1308 }
1309 if (uh) {
1310 if (uh->check)
1311 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL_CSUM;
1312 else
1313 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1314 }
1315 }
1316 #endif
1317
1318 static struct sk_buff *bnxt_gro_func_5731x(struct bnxt_tpa_info *tpa_info,
1319 int payload_off, int tcp_ts,
1320 struct sk_buff *skb)
1321 {
1322 #ifdef CONFIG_INET
1323 struct tcphdr *th;
1324 int len, nw_off;
1325 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1326 u32 hdr_info = tpa_info->hdr_info;
1327 bool loopback = false;
1328
1329 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1330 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1331 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1332
1333 /* If the packet is an internal loopback packet, the offsets will
1334 * have an extra 4 bytes.
1335 */
1336 if (inner_mac_off == 4) {
1337 loopback = true;
1338 } else if (inner_mac_off > 4) {
1339 __be16 proto = *((__be16 *)(skb->data + inner_ip_off -
1340 ETH_HLEN - 2));
1341
1342 /* We only support inner iPv4/ipv6. If we don't see the
1343 * correct protocol ID, it must be a loopback packet where
1344 * the offsets are off by 4.
1345 */
1346 if (proto != htons(ETH_P_IP) && proto != htons(ETH_P_IPV6))
1347 loopback = true;
1348 }
1349 if (loopback) {
1350 /* internal loopback packet, subtract all offsets by 4 */
1351 inner_ip_off -= 4;
1352 inner_mac_off -= 4;
1353 outer_ip_off -= 4;
1354 }
1355
1356 nw_off = inner_ip_off - ETH_HLEN;
1357 skb_set_network_header(skb, nw_off);
1358 if (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) {
1359 struct ipv6hdr *iph = ipv6_hdr(skb);
1360
1361 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1362 len = skb->len - skb_transport_offset(skb);
1363 th = tcp_hdr(skb);
1364 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1365 } else {
1366 struct iphdr *iph = ip_hdr(skb);
1367
1368 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1369 len = skb->len - skb_transport_offset(skb);
1370 th = tcp_hdr(skb);
1371 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1372 }
1373
1374 if (inner_mac_off) { /* tunnel */
1375 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1376 ETH_HLEN - 2));
1377
1378 bnxt_gro_tunnel(skb, proto);
1379 }
1380 #endif
1381 return skb;
1382 }
1383
1384 static struct sk_buff *bnxt_gro_func_5750x(struct bnxt_tpa_info *tpa_info,
1385 int payload_off, int tcp_ts,
1386 struct sk_buff *skb)
1387 {
1388 #ifdef CONFIG_INET
1389 u16 outer_ip_off, inner_ip_off, inner_mac_off;
1390 u32 hdr_info = tpa_info->hdr_info;
1391 int iphdr_len, nw_off;
1392
1393 inner_ip_off = BNXT_TPA_INNER_L3_OFF(hdr_info);
1394 inner_mac_off = BNXT_TPA_INNER_L2_OFF(hdr_info);
1395 outer_ip_off = BNXT_TPA_OUTER_L3_OFF(hdr_info);
1396
1397 nw_off = inner_ip_off - ETH_HLEN;
1398 skb_set_network_header(skb, nw_off);
1399 iphdr_len = (tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_IP_TYPE) ?
1400 sizeof(struct ipv6hdr) : sizeof(struct iphdr);
1401 skb_set_transport_header(skb, nw_off + iphdr_len);
1402
1403 if (inner_mac_off) { /* tunnel */
1404 __be16 proto = *((__be16 *)(skb->data + outer_ip_off -
1405 ETH_HLEN - 2));
1406
1407 bnxt_gro_tunnel(skb, proto);
1408 }
1409 #endif
1410 return skb;
1411 }
1412
1413 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
1414 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
1415
1416 static struct sk_buff *bnxt_gro_func_5730x(struct bnxt_tpa_info *tpa_info,
1417 int payload_off, int tcp_ts,
1418 struct sk_buff *skb)
1419 {
1420 #ifdef CONFIG_INET
1421 struct tcphdr *th;
1422 int len, nw_off, tcp_opt_len = 0;
1423
1424 if (tcp_ts)
1425 tcp_opt_len = 12;
1426
1427 if (tpa_info->gso_type == SKB_GSO_TCPV4) {
1428 struct iphdr *iph;
1429
1430 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
1431 ETH_HLEN;
1432 skb_set_network_header(skb, nw_off);
1433 iph = ip_hdr(skb);
1434 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
1435 len = skb->len - skb_transport_offset(skb);
1436 th = tcp_hdr(skb);
1437 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
1438 } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
1439 struct ipv6hdr *iph;
1440
1441 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
1442 ETH_HLEN;
1443 skb_set_network_header(skb, nw_off);
1444 iph = ipv6_hdr(skb);
1445 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
1446 len = skb->len - skb_transport_offset(skb);
1447 th = tcp_hdr(skb);
1448 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
1449 } else {
1450 dev_kfree_skb_any(skb);
1451 return NULL;
1452 }
1453
1454 if (nw_off) /* tunnel */
1455 bnxt_gro_tunnel(skb, skb->protocol);
1456 #endif
1457 return skb;
1458 }
1459
1460 static inline struct sk_buff *bnxt_gro_skb(struct bnxt *bp,
1461 struct bnxt_tpa_info *tpa_info,
1462 struct rx_tpa_end_cmp *tpa_end,
1463 struct rx_tpa_end_cmp_ext *tpa_end1,
1464 struct sk_buff *skb)
1465 {
1466 #ifdef CONFIG_INET
1467 int payload_off;
1468 u16 segs;
1469
1470 segs = TPA_END_TPA_SEGS(tpa_end);
1471 if (segs == 1)
1472 return skb;
1473
1474 NAPI_GRO_CB(skb)->count = segs;
1475 skb_shinfo(skb)->gso_size =
1476 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
1477 skb_shinfo(skb)->gso_type = tpa_info->gso_type;
1478 if (bp->flags & BNXT_FLAG_CHIP_P5)
1479 payload_off = TPA_END_PAYLOAD_OFF_P5(tpa_end1);
1480 else
1481 payload_off = TPA_END_PAYLOAD_OFF(tpa_end);
1482 skb = bp->gro_func(tpa_info, payload_off, TPA_END_GRO_TS(tpa_end), skb);
1483 if (likely(skb))
1484 tcp_gro_complete(skb);
1485 #endif
1486 return skb;
1487 }
1488
1489 /* Given the cfa_code of a received packet determine which
1490 * netdev (vf-rep or PF) the packet is destined to.
1491 */
1492 static struct net_device *bnxt_get_pkt_dev(struct bnxt *bp, u16 cfa_code)
1493 {
1494 struct net_device *dev = bnxt_get_vf_rep(bp, cfa_code);
1495
1496 /* if vf-rep dev is NULL, the must belongs to the PF */
1497 return dev ? dev : bp->dev;
1498 }
1499
1500 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1501 struct bnxt_cp_ring_info *cpr,
1502 u32 *raw_cons,
1503 struct rx_tpa_end_cmp *tpa_end,
1504 struct rx_tpa_end_cmp_ext *tpa_end1,
1505 u8 *event)
1506 {
1507 struct bnxt_napi *bnapi = cpr->bnapi;
1508 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1509 u8 *data_ptr, agg_bufs;
1510 unsigned int len;
1511 struct bnxt_tpa_info *tpa_info;
1512 dma_addr_t mapping;
1513 struct sk_buff *skb;
1514 u16 idx = 0, agg_id;
1515 void *data;
1516 bool gro;
1517
1518 if (unlikely(bnapi->in_reset)) {
1519 int rc = bnxt_discard_rx(bp, cpr, raw_cons, tpa_end);
1520
1521 if (rc < 0)
1522 return ERR_PTR(-EBUSY);
1523 return NULL;
1524 }
1525
1526 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1527 agg_id = TPA_END_AGG_ID_P5(tpa_end);
1528 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1529 agg_bufs = TPA_END_AGG_BUFS_P5(tpa_end1);
1530 tpa_info = &rxr->rx_tpa[agg_id];
1531 if (unlikely(agg_bufs != tpa_info->agg_count)) {
1532 netdev_warn(bp->dev, "TPA end agg_buf %d != expected agg_bufs %d\n",
1533 agg_bufs, tpa_info->agg_count);
1534 agg_bufs = tpa_info->agg_count;
1535 }
1536 tpa_info->agg_count = 0;
1537 *event |= BNXT_AGG_EVENT;
1538 bnxt_free_agg_idx(rxr, agg_id);
1539 idx = agg_id;
1540 gro = !!(bp->flags & BNXT_FLAG_GRO);
1541 } else {
1542 agg_id = TPA_END_AGG_ID(tpa_end);
1543 agg_bufs = TPA_END_AGG_BUFS(tpa_end);
1544 tpa_info = &rxr->rx_tpa[agg_id];
1545 idx = RING_CMP(*raw_cons);
1546 if (agg_bufs) {
1547 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1548 return ERR_PTR(-EBUSY);
1549
1550 *event |= BNXT_AGG_EVENT;
1551 idx = NEXT_CMP(idx);
1552 }
1553 gro = !!TPA_END_GRO(tpa_end);
1554 }
1555 data = tpa_info->data;
1556 data_ptr = tpa_info->data_ptr;
1557 prefetch(data_ptr);
1558 len = tpa_info->len;
1559 mapping = tpa_info->mapping;
1560
1561 if (unlikely(agg_bufs > MAX_SKB_FRAGS || TPA_END_ERRORS(tpa_end1))) {
1562 bnxt_abort_tpa(cpr, idx, agg_bufs);
1563 if (agg_bufs > MAX_SKB_FRAGS)
1564 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1565 agg_bufs, (int)MAX_SKB_FRAGS);
1566 return NULL;
1567 }
1568
1569 if (len <= bp->rx_copy_thresh) {
1570 skb = bnxt_copy_skb(bnapi, data_ptr, len, mapping);
1571 if (!skb) {
1572 bnxt_abort_tpa(cpr, idx, agg_bufs);
1573 return NULL;
1574 }
1575 } else {
1576 u8 *new_data;
1577 dma_addr_t new_mapping;
1578
1579 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1580 if (!new_data) {
1581 bnxt_abort_tpa(cpr, idx, agg_bufs);
1582 return NULL;
1583 }
1584
1585 tpa_info->data = new_data;
1586 tpa_info->data_ptr = new_data + bp->rx_offset;
1587 tpa_info->mapping = new_mapping;
1588
1589 skb = build_skb(data, 0);
1590 dma_unmap_single_attrs(&bp->pdev->dev, mapping,
1591 bp->rx_buf_use_size, bp->rx_dir,
1592 DMA_ATTR_WEAK_ORDERING);
1593
1594 if (!skb) {
1595 kfree(data);
1596 bnxt_abort_tpa(cpr, idx, agg_bufs);
1597 return NULL;
1598 }
1599 skb_reserve(skb, bp->rx_offset);
1600 skb_put(skb, len);
1601 }
1602
1603 if (agg_bufs) {
1604 skb = bnxt_rx_pages(bp, cpr, skb, idx, agg_bufs, true);
1605 if (!skb) {
1606 /* Page reuse already handled by bnxt_rx_pages(). */
1607 return NULL;
1608 }
1609 }
1610
1611 skb->protocol =
1612 eth_type_trans(skb, bnxt_get_pkt_dev(bp, tpa_info->cfa_code));
1613
1614 if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1615 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1616
1617 if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1618 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1619 u16 vlan_proto = tpa_info->metadata >>
1620 RX_CMP_FLAGS2_METADATA_TPID_SFT;
1621 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1622
1623 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1624 }
1625
1626 skb_checksum_none_assert(skb);
1627 if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1628 skb->ip_summed = CHECKSUM_UNNECESSARY;
1629 skb->csum_level =
1630 (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1631 }
1632
1633 if (gro)
1634 skb = bnxt_gro_skb(bp, tpa_info, tpa_end, tpa_end1, skb);
1635
1636 return skb;
1637 }
1638
1639 static void bnxt_tpa_agg(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1640 struct rx_agg_cmp *rx_agg)
1641 {
1642 u16 agg_id = TPA_AGG_AGG_ID(rx_agg);
1643 struct bnxt_tpa_info *tpa_info;
1644
1645 agg_id = bnxt_lookup_agg_idx(rxr, agg_id);
1646 tpa_info = &rxr->rx_tpa[agg_id];
1647 BUG_ON(tpa_info->agg_count >= MAX_SKB_FRAGS);
1648 tpa_info->agg_arr[tpa_info->agg_count++] = *rx_agg;
1649 }
1650
1651 static void bnxt_deliver_skb(struct bnxt *bp, struct bnxt_napi *bnapi,
1652 struct sk_buff *skb)
1653 {
1654 if (skb->dev != bp->dev) {
1655 /* this packet belongs to a vf-rep */
1656 bnxt_vf_rep_rx(bp, skb);
1657 return;
1658 }
1659 skb_record_rx_queue(skb, bnapi->index);
1660 napi_gro_receive(&bnapi->napi, skb);
1661 }
1662
1663 /* returns the following:
1664 * 1 - 1 packet successfully received
1665 * 0 - successful TPA_START, packet not completed yet
1666 * -EBUSY - completion ring does not have all the agg buffers yet
1667 * -ENOMEM - packet aborted due to out of memory
1668 * -EIO - packet aborted due to hw error indicated in BD
1669 */
1670 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
1671 u32 *raw_cons, u8 *event)
1672 {
1673 struct bnxt_napi *bnapi = cpr->bnapi;
1674 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1675 struct net_device *dev = bp->dev;
1676 struct rx_cmp *rxcmp;
1677 struct rx_cmp_ext *rxcmp1;
1678 u32 tmp_raw_cons = *raw_cons;
1679 u16 cfa_code, cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1680 struct bnxt_sw_rx_bd *rx_buf;
1681 unsigned int len;
1682 u8 *data_ptr, agg_bufs, cmp_type;
1683 dma_addr_t dma_addr;
1684 struct sk_buff *skb;
1685 void *data;
1686 int rc = 0;
1687 u32 misc;
1688
1689 rxcmp = (struct rx_cmp *)
1690 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1691
1692 cmp_type = RX_CMP_TYPE(rxcmp);
1693
1694 if (cmp_type == CMP_TYPE_RX_TPA_AGG_CMP) {
1695 bnxt_tpa_agg(bp, rxr, (struct rx_agg_cmp *)rxcmp);
1696 goto next_rx_no_prod_no_len;
1697 }
1698
1699 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1700 cp_cons = RING_CMP(tmp_raw_cons);
1701 rxcmp1 = (struct rx_cmp_ext *)
1702 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1703
1704 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1705 return -EBUSY;
1706
1707 prod = rxr->rx_prod;
1708
1709 if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1710 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1711 (struct rx_tpa_start_cmp_ext *)rxcmp1);
1712
1713 *event |= BNXT_RX_EVENT;
1714 goto next_rx_no_prod_no_len;
1715
1716 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1717 skb = bnxt_tpa_end(bp, cpr, &tmp_raw_cons,
1718 (struct rx_tpa_end_cmp *)rxcmp,
1719 (struct rx_tpa_end_cmp_ext *)rxcmp1, event);
1720
1721 if (IS_ERR(skb))
1722 return -EBUSY;
1723
1724 rc = -ENOMEM;
1725 if (likely(skb)) {
1726 bnxt_deliver_skb(bp, bnapi, skb);
1727 rc = 1;
1728 }
1729 *event |= BNXT_RX_EVENT;
1730 goto next_rx_no_prod_no_len;
1731 }
1732
1733 cons = rxcmp->rx_cmp_opaque;
1734 if (unlikely(cons != rxr->rx_next_cons)) {
1735 int rc1 = bnxt_discard_rx(bp, cpr, raw_cons, rxcmp);
1736
1737 /* 0xffff is forced error, don't print it */
1738 if (rxr->rx_next_cons != 0xffff)
1739 netdev_warn(bp->dev, "RX cons %x != expected cons %x\n",
1740 cons, rxr->rx_next_cons);
1741 bnxt_sched_reset(bp, rxr);
1742 return rc1;
1743 }
1744 rx_buf = &rxr->rx_buf_ring[cons];
1745 data = rx_buf->data;
1746 data_ptr = rx_buf->data_ptr;
1747 prefetch(data_ptr);
1748
1749 misc = le32_to_cpu(rxcmp->rx_cmp_misc_v1);
1750 agg_bufs = (misc & RX_CMP_AGG_BUFS) >> RX_CMP_AGG_BUFS_SHIFT;
1751
1752 if (agg_bufs) {
1753 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1754 return -EBUSY;
1755
1756 cp_cons = NEXT_CMP(cp_cons);
1757 *event |= BNXT_AGG_EVENT;
1758 }
1759 *event |= BNXT_RX_EVENT;
1760
1761 rx_buf->data = NULL;
1762 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1763 u32 rx_err = le32_to_cpu(rxcmp1->rx_cmp_cfa_code_errors_v2);
1764
1765 bnxt_reuse_rx_data(rxr, cons, data);
1766 if (agg_bufs)
1767 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0, agg_bufs,
1768 false);
1769
1770 rc = -EIO;
1771 if (rx_err & RX_CMPL_ERRORS_BUFFER_ERROR_MASK) {
1772 bnapi->cp_ring.sw_stats.rx.rx_buf_errors++;
1773 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
1774 !(bp->fw_cap & BNXT_FW_CAP_RING_MONITOR)) {
1775 netdev_warn_once(bp->dev, "RX buffer error %x\n",
1776 rx_err);
1777 bnxt_sched_reset(bp, rxr);
1778 }
1779 }
1780 goto next_rx_no_len;
1781 }
1782
1783 len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1784 dma_addr = rx_buf->mapping;
1785
1786 if (bnxt_rx_xdp(bp, rxr, cons, data, &data_ptr, &len, event)) {
1787 rc = 1;
1788 goto next_rx;
1789 }
1790
1791 if (len <= bp->rx_copy_thresh) {
1792 skb = bnxt_copy_skb(bnapi, data_ptr, len, dma_addr);
1793 bnxt_reuse_rx_data(rxr, cons, data);
1794 if (!skb) {
1795 if (agg_bufs)
1796 bnxt_reuse_rx_agg_bufs(cpr, cp_cons, 0,
1797 agg_bufs, false);
1798 rc = -ENOMEM;
1799 goto next_rx;
1800 }
1801 } else {
1802 u32 payload;
1803
1804 if (rx_buf->data_ptr == data_ptr)
1805 payload = misc & RX_CMP_PAYLOAD_OFFSET;
1806 else
1807 payload = 0;
1808 skb = bp->rx_skb_func(bp, rxr, cons, data, data_ptr, dma_addr,
1809 payload | len);
1810 if (!skb) {
1811 rc = -ENOMEM;
1812 goto next_rx;
1813 }
1814 }
1815
1816 if (agg_bufs) {
1817 skb = bnxt_rx_pages(bp, cpr, skb, cp_cons, agg_bufs, false);
1818 if (!skb) {
1819 rc = -ENOMEM;
1820 goto next_rx;
1821 }
1822 }
1823
1824 if (RX_CMP_HASH_VALID(rxcmp)) {
1825 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1826 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1827
1828 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1829 if (hash_type != 1 && hash_type != 3)
1830 type = PKT_HASH_TYPE_L3;
1831 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1832 }
1833
1834 cfa_code = RX_CMP_CFA_CODE(rxcmp1);
1835 skb->protocol = eth_type_trans(skb, bnxt_get_pkt_dev(bp, cfa_code));
1836
1837 if ((rxcmp1->rx_cmp_flags2 &
1838 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1839 (skb->dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)) {
1840 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1841 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_TCI_MASK;
1842 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1843
1844 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1845 }
1846
1847 skb_checksum_none_assert(skb);
1848 if (RX_CMP_L4_CS_OK(rxcmp1)) {
1849 if (dev->features & NETIF_F_RXCSUM) {
1850 skb->ip_summed = CHECKSUM_UNNECESSARY;
1851 skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1852 }
1853 } else {
1854 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1855 if (dev->features & NETIF_F_RXCSUM)
1856 bnapi->cp_ring.sw_stats.rx.rx_l4_csum_errors++;
1857 }
1858 }
1859
1860 bnxt_deliver_skb(bp, bnapi, skb);
1861 rc = 1;
1862
1863 next_rx:
1864 cpr->rx_packets += 1;
1865 cpr->rx_bytes += len;
1866
1867 next_rx_no_len:
1868 rxr->rx_prod = NEXT_RX(prod);
1869 rxr->rx_next_cons = NEXT_RX(cons);
1870
1871 next_rx_no_prod_no_len:
1872 *raw_cons = tmp_raw_cons;
1873
1874 return rc;
1875 }
1876
1877 /* In netpoll mode, if we are using a combined completion ring, we need to
1878 * discard the rx packets and recycle the buffers.
1879 */
1880 static int bnxt_force_rx_discard(struct bnxt *bp,
1881 struct bnxt_cp_ring_info *cpr,
1882 u32 *raw_cons, u8 *event)
1883 {
1884 u32 tmp_raw_cons = *raw_cons;
1885 struct rx_cmp_ext *rxcmp1;
1886 struct rx_cmp *rxcmp;
1887 u16 cp_cons;
1888 u8 cmp_type;
1889
1890 cp_cons = RING_CMP(tmp_raw_cons);
1891 rxcmp = (struct rx_cmp *)
1892 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1893
1894 tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1895 cp_cons = RING_CMP(tmp_raw_cons);
1896 rxcmp1 = (struct rx_cmp_ext *)
1897 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1898
1899 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1900 return -EBUSY;
1901
1902 cmp_type = RX_CMP_TYPE(rxcmp);
1903 if (cmp_type == CMP_TYPE_RX_L2_CMP) {
1904 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
1905 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
1906 } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1907 struct rx_tpa_end_cmp_ext *tpa_end1;
1908
1909 tpa_end1 = (struct rx_tpa_end_cmp_ext *)rxcmp1;
1910 tpa_end1->rx_tpa_end_cmp_errors_v2 |=
1911 cpu_to_le32(RX_TPA_END_CMP_ERRORS);
1912 }
1913 return bnxt_rx_pkt(bp, cpr, raw_cons, event);
1914 }
1915
1916 u32 bnxt_fw_health_readl(struct bnxt *bp, int reg_idx)
1917 {
1918 struct bnxt_fw_health *fw_health = bp->fw_health;
1919 u32 reg = fw_health->regs[reg_idx];
1920 u32 reg_type, reg_off, val = 0;
1921
1922 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
1923 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
1924 switch (reg_type) {
1925 case BNXT_FW_HEALTH_REG_TYPE_CFG:
1926 pci_read_config_dword(bp->pdev, reg_off, &val);
1927 break;
1928 case BNXT_FW_HEALTH_REG_TYPE_GRC:
1929 reg_off = fw_health->mapped_regs[reg_idx];
1930 fallthrough;
1931 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
1932 val = readl(bp->bar0 + reg_off);
1933 break;
1934 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
1935 val = readl(bp->bar1 + reg_off);
1936 break;
1937 }
1938 if (reg_idx == BNXT_FW_RESET_INPROG_REG)
1939 val &= fw_health->fw_reset_inprog_reg_mask;
1940 return val;
1941 }
1942
1943 static u16 bnxt_agg_ring_id_to_grp_idx(struct bnxt *bp, u16 ring_id)
1944 {
1945 int i;
1946
1947 for (i = 0; i < bp->rx_nr_rings; i++) {
1948 u16 grp_idx = bp->rx_ring[i].bnapi->index;
1949 struct bnxt_ring_grp_info *grp_info;
1950
1951 grp_info = &bp->grp_info[grp_idx];
1952 if (grp_info->agg_fw_ring_id == ring_id)
1953 return grp_idx;
1954 }
1955 return INVALID_HW_RING_ID;
1956 }
1957
1958 #define BNXT_GET_EVENT_PORT(data) \
1959 ((data) & \
1960 ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1961
1962 #define BNXT_EVENT_RING_TYPE(data2) \
1963 ((data2) & \
1964 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_MASK)
1965
1966 #define BNXT_EVENT_RING_TYPE_RX(data2) \
1967 (BNXT_EVENT_RING_TYPE(data2) == \
1968 ASYNC_EVENT_CMPL_RING_MONITOR_MSG_EVENT_DATA2_DISABLE_RING_TYPE_RX)
1969
1970 static int bnxt_async_event_process(struct bnxt *bp,
1971 struct hwrm_async_event_cmpl *cmpl)
1972 {
1973 u16 event_id = le16_to_cpu(cmpl->event_id);
1974 u32 data1 = le32_to_cpu(cmpl->event_data1);
1975 u32 data2 = le32_to_cpu(cmpl->event_data2);
1976
1977 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1978 switch (event_id) {
1979 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1980 struct bnxt_link_info *link_info = &bp->link_info;
1981
1982 if (BNXT_VF(bp))
1983 goto async_event_process_exit;
1984
1985 /* print unsupported speed warning in forced speed mode only */
1986 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED) &&
1987 (data1 & 0x20000)) {
1988 u16 fw_speed = link_info->force_link_speed;
1989 u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1990
1991 if (speed != SPEED_UNKNOWN)
1992 netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1993 speed);
1994 }
1995 set_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT, &bp->sp_event);
1996 }
1997 fallthrough;
1998 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE:
1999 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE:
2000 set_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT, &bp->sp_event);
2001 fallthrough;
2002 case ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
2003 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
2004 break;
2005 case ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
2006 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
2007 break;
2008 case ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
2009 u16 port_id = BNXT_GET_EVENT_PORT(data1);
2010
2011 if (BNXT_VF(bp))
2012 break;
2013
2014 if (bp->pf.port_id != port_id)
2015 break;
2016
2017 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
2018 break;
2019 }
2020 case ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
2021 if (BNXT_PF(bp))
2022 goto async_event_process_exit;
2023 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
2024 break;
2025 case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: {
2026 char *fatal_str = "non-fatal";
2027
2028 if (!bp->fw_health)
2029 goto async_event_process_exit;
2030
2031 bp->fw_reset_timestamp = jiffies;
2032 bp->fw_reset_min_dsecs = cmpl->timestamp_lo;
2033 if (!bp->fw_reset_min_dsecs)
2034 bp->fw_reset_min_dsecs = BNXT_DFLT_FW_RST_MIN_DSECS;
2035 bp->fw_reset_max_dsecs = le16_to_cpu(cmpl->timestamp_hi);
2036 if (!bp->fw_reset_max_dsecs)
2037 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS;
2038 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) {
2039 fatal_str = "fatal";
2040 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
2041 }
2042 netif_warn(bp, hw, bp->dev,
2043 "Firmware %s reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n",
2044 fatal_str, data1, data2,
2045 bp->fw_reset_min_dsecs * 100,
2046 bp->fw_reset_max_dsecs * 100);
2047 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event);
2048 break;
2049 }
2050 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: {
2051 struct bnxt_fw_health *fw_health = bp->fw_health;
2052
2053 if (!fw_health)
2054 goto async_event_process_exit;
2055
2056 fw_health->enabled = EVENT_DATA1_RECOVERY_ENABLED(data1);
2057 fw_health->master = EVENT_DATA1_RECOVERY_MASTER_FUNC(data1);
2058 if (!fw_health->enabled) {
2059 netif_info(bp, drv, bp->dev,
2060 "Error recovery info: error recovery[0]\n");
2061 break;
2062 }
2063 fw_health->tmr_multiplier =
2064 DIV_ROUND_UP(fw_health->polling_dsecs * HZ,
2065 bp->current_interval * 10);
2066 fw_health->tmr_counter = fw_health->tmr_multiplier;
2067 fw_health->last_fw_heartbeat =
2068 bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
2069 fw_health->last_fw_reset_cnt =
2070 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
2071 netif_info(bp, drv, bp->dev,
2072 "Error recovery info: error recovery[1], master[%d], reset count[%u], health status: 0x%x\n",
2073 fw_health->master, fw_health->last_fw_reset_cnt,
2074 bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG));
2075 goto async_event_process_exit;
2076 }
2077 case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION:
2078 netif_notice(bp, hw, bp->dev,
2079 "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n",
2080 data1, data2);
2081 goto async_event_process_exit;
2082 case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: {
2083 struct bnxt_rx_ring_info *rxr;
2084 u16 grp_idx;
2085
2086 if (bp->flags & BNXT_FLAG_CHIP_P5)
2087 goto async_event_process_exit;
2088
2089 netdev_warn(bp->dev, "Ring monitor event, ring type %lu id 0x%x\n",
2090 BNXT_EVENT_RING_TYPE(data2), data1);
2091 if (!BNXT_EVENT_RING_TYPE_RX(data2))
2092 goto async_event_process_exit;
2093
2094 grp_idx = bnxt_agg_ring_id_to_grp_idx(bp, data1);
2095 if (grp_idx == INVALID_HW_RING_ID) {
2096 netdev_warn(bp->dev, "Unknown RX agg ring id 0x%x\n",
2097 data1);
2098 goto async_event_process_exit;
2099 }
2100 rxr = bp->bnapi[grp_idx]->rx_ring;
2101 bnxt_sched_reset(bp, rxr);
2102 goto async_event_process_exit;
2103 }
2104 case ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST: {
2105 struct bnxt_fw_health *fw_health = bp->fw_health;
2106
2107 netif_notice(bp, hw, bp->dev,
2108 "Received firmware echo request, data1: 0x%x, data2: 0x%x\n",
2109 data1, data2);
2110 if (fw_health) {
2111 fw_health->echo_req_data1 = data1;
2112 fw_health->echo_req_data2 = data2;
2113 set_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event);
2114 break;
2115 }
2116 goto async_event_process_exit;
2117 }
2118 default:
2119 goto async_event_process_exit;
2120 }
2121 bnxt_queue_sp_work(bp);
2122 async_event_process_exit:
2123 bnxt_ulp_async_events(bp, cmpl);
2124 return 0;
2125 }
2126
2127 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
2128 {
2129 u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
2130 struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
2131 struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
2132 (struct hwrm_fwd_req_cmpl *)txcmp;
2133
2134 switch (cmpl_type) {
2135 case CMPL_BASE_TYPE_HWRM_DONE:
2136 seq_id = le16_to_cpu(h_cmpl->sequence_id);
2137 if (seq_id == bp->hwrm_intr_seq_id)
2138 bp->hwrm_intr_seq_id = (u16)~bp->hwrm_intr_seq_id;
2139 else
2140 netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
2141 break;
2142
2143 case CMPL_BASE_TYPE_HWRM_FWD_REQ:
2144 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
2145
2146 if ((vf_id < bp->pf.first_vf_id) ||
2147 (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
2148 netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
2149 vf_id);
2150 return -EINVAL;
2151 }
2152
2153 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
2154 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
2155 bnxt_queue_sp_work(bp);
2156 break;
2157
2158 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
2159 bnxt_async_event_process(bp,
2160 (struct hwrm_async_event_cmpl *)txcmp);
2161
2162 default:
2163 break;
2164 }
2165
2166 return 0;
2167 }
2168
2169 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
2170 {
2171 struct bnxt_napi *bnapi = dev_instance;
2172 struct bnxt *bp = bnapi->bp;
2173 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2174 u32 cons = RING_CMP(cpr->cp_raw_cons);
2175
2176 cpr->event_ctr++;
2177 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2178 napi_schedule(&bnapi->napi);
2179 return IRQ_HANDLED;
2180 }
2181
2182 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
2183 {
2184 u32 raw_cons = cpr->cp_raw_cons;
2185 u16 cons = RING_CMP(raw_cons);
2186 struct tx_cmp *txcmp;
2187
2188 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2189
2190 return TX_CMP_VALID(txcmp, raw_cons);
2191 }
2192
2193 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
2194 {
2195 struct bnxt_napi *bnapi = dev_instance;
2196 struct bnxt *bp = bnapi->bp;
2197 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2198 u32 cons = RING_CMP(cpr->cp_raw_cons);
2199 u32 int_status;
2200
2201 prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
2202
2203 if (!bnxt_has_work(bp, cpr)) {
2204 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
2205 /* return if erroneous interrupt */
2206 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
2207 return IRQ_NONE;
2208 }
2209
2210 /* disable ring IRQ */
2211 BNXT_CP_DB_IRQ_DIS(cpr->cp_db.doorbell);
2212
2213 /* Return here if interrupt is shared and is disabled. */
2214 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2215 return IRQ_HANDLED;
2216
2217 napi_schedule(&bnapi->napi);
2218 return IRQ_HANDLED;
2219 }
2220
2221 static int __bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2222 int budget)
2223 {
2224 struct bnxt_napi *bnapi = cpr->bnapi;
2225 u32 raw_cons = cpr->cp_raw_cons;
2226 u32 cons;
2227 int tx_pkts = 0;
2228 int rx_pkts = 0;
2229 u8 event = 0;
2230 struct tx_cmp *txcmp;
2231
2232 cpr->has_more_work = 0;
2233 cpr->had_work_done = 1;
2234 while (1) {
2235 int rc;
2236
2237 cons = RING_CMP(raw_cons);
2238 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2239
2240 if (!TX_CMP_VALID(txcmp, raw_cons))
2241 break;
2242
2243 /* The valid test of the entry must be done first before
2244 * reading any further.
2245 */
2246 dma_rmb();
2247 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
2248 tx_pkts++;
2249 /* return full budget so NAPI will complete. */
2250 if (unlikely(tx_pkts > bp->tx_wake_thresh)) {
2251 rx_pkts = budget;
2252 raw_cons = NEXT_RAW_CMP(raw_cons);
2253 if (budget)
2254 cpr->has_more_work = 1;
2255 break;
2256 }
2257 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2258 if (likely(budget))
2259 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2260 else
2261 rc = bnxt_force_rx_discard(bp, cpr, &raw_cons,
2262 &event);
2263 if (likely(rc >= 0))
2264 rx_pkts += rc;
2265 /* Increment rx_pkts when rc is -ENOMEM to count towards
2266 * the NAPI budget. Otherwise, we may potentially loop
2267 * here forever if we consistently cannot allocate
2268 * buffers.
2269 */
2270 else if (rc == -ENOMEM && budget)
2271 rx_pkts++;
2272 else if (rc == -EBUSY) /* partial completion */
2273 break;
2274 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
2275 CMPL_BASE_TYPE_HWRM_DONE) ||
2276 (TX_CMP_TYPE(txcmp) ==
2277 CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
2278 (TX_CMP_TYPE(txcmp) ==
2279 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
2280 bnxt_hwrm_handler(bp, txcmp);
2281 }
2282 raw_cons = NEXT_RAW_CMP(raw_cons);
2283
2284 if (rx_pkts && rx_pkts == budget) {
2285 cpr->has_more_work = 1;
2286 break;
2287 }
2288 }
2289
2290 if (event & BNXT_REDIRECT_EVENT)
2291 xdp_do_flush_map();
2292
2293 if (event & BNXT_TX_EVENT) {
2294 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
2295 u16 prod = txr->tx_prod;
2296
2297 /* Sync BD data before updating doorbell */
2298 wmb();
2299
2300 bnxt_db_write_relaxed(bp, &txr->tx_db, prod);
2301 }
2302
2303 cpr->cp_raw_cons = raw_cons;
2304 bnapi->tx_pkts += tx_pkts;
2305 bnapi->events |= event;
2306 return rx_pkts;
2307 }
2308
2309 static void __bnxt_poll_work_done(struct bnxt *bp, struct bnxt_napi *bnapi)
2310 {
2311 if (bnapi->tx_pkts) {
2312 bnapi->tx_int(bp, bnapi, bnapi->tx_pkts);
2313 bnapi->tx_pkts = 0;
2314 }
2315
2316 if ((bnapi->events & BNXT_RX_EVENT) && !(bnapi->in_reset)) {
2317 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2318
2319 if (bnapi->events & BNXT_AGG_EVENT)
2320 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2321 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2322 }
2323 bnapi->events = 0;
2324 }
2325
2326 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
2327 int budget)
2328 {
2329 struct bnxt_napi *bnapi = cpr->bnapi;
2330 int rx_pkts;
2331
2332 rx_pkts = __bnxt_poll_work(bp, cpr, budget);
2333
2334 /* ACK completion ring before freeing tx ring and producing new
2335 * buffers in rx/agg rings to prevent overflowing the completion
2336 * ring.
2337 */
2338 bnxt_db_cq(bp, &cpr->cp_db, cpr->cp_raw_cons);
2339
2340 __bnxt_poll_work_done(bp, bnapi);
2341 return rx_pkts;
2342 }
2343
2344 static int bnxt_poll_nitroa0(struct napi_struct *napi, int budget)
2345 {
2346 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2347 struct bnxt *bp = bnapi->bp;
2348 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2349 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
2350 struct tx_cmp *txcmp;
2351 struct rx_cmp_ext *rxcmp1;
2352 u32 cp_cons, tmp_raw_cons;
2353 u32 raw_cons = cpr->cp_raw_cons;
2354 u32 rx_pkts = 0;
2355 u8 event = 0;
2356
2357 while (1) {
2358 int rc;
2359
2360 cp_cons = RING_CMP(raw_cons);
2361 txcmp = &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2362
2363 if (!TX_CMP_VALID(txcmp, raw_cons))
2364 break;
2365
2366 if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
2367 tmp_raw_cons = NEXT_RAW_CMP(raw_cons);
2368 cp_cons = RING_CMP(tmp_raw_cons);
2369 rxcmp1 = (struct rx_cmp_ext *)
2370 &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
2371
2372 if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
2373 break;
2374
2375 /* force an error to recycle the buffer */
2376 rxcmp1->rx_cmp_cfa_code_errors_v2 |=
2377 cpu_to_le32(RX_CMPL_ERRORS_CRC_ERROR);
2378
2379 rc = bnxt_rx_pkt(bp, cpr, &raw_cons, &event);
2380 if (likely(rc == -EIO) && budget)
2381 rx_pkts++;
2382 else if (rc == -EBUSY) /* partial completion */
2383 break;
2384 } else if (unlikely(TX_CMP_TYPE(txcmp) ==
2385 CMPL_BASE_TYPE_HWRM_DONE)) {
2386 bnxt_hwrm_handler(bp, txcmp);
2387 } else {
2388 netdev_err(bp->dev,
2389 "Invalid completion received on special ring\n");
2390 }
2391 raw_cons = NEXT_RAW_CMP(raw_cons);
2392
2393 if (rx_pkts == budget)
2394 break;
2395 }
2396
2397 cpr->cp_raw_cons = raw_cons;
2398 BNXT_DB_CQ(&cpr->cp_db, cpr->cp_raw_cons);
2399 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
2400
2401 if (event & BNXT_AGG_EVENT)
2402 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
2403
2404 if (!bnxt_has_work(bp, cpr) && rx_pkts < budget) {
2405 napi_complete_done(napi, rx_pkts);
2406 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2407 }
2408 return rx_pkts;
2409 }
2410
2411 static int bnxt_poll(struct napi_struct *napi, int budget)
2412 {
2413 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2414 struct bnxt *bp = bnapi->bp;
2415 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2416 int work_done = 0;
2417
2418 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2419 napi_complete(napi);
2420 return 0;
2421 }
2422 while (1) {
2423 work_done += bnxt_poll_work(bp, cpr, budget - work_done);
2424
2425 if (work_done >= budget) {
2426 if (!budget)
2427 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2428 break;
2429 }
2430
2431 if (!bnxt_has_work(bp, cpr)) {
2432 if (napi_complete_done(napi, work_done))
2433 BNXT_DB_CQ_ARM(&cpr->cp_db, cpr->cp_raw_cons);
2434 break;
2435 }
2436 }
2437 if (bp->flags & BNXT_FLAG_DIM) {
2438 struct dim_sample dim_sample = {};
2439
2440 dim_update_sample(cpr->event_ctr,
2441 cpr->rx_packets,
2442 cpr->rx_bytes,
2443 &dim_sample);
2444 net_dim(&cpr->dim, dim_sample);
2445 }
2446 return work_done;
2447 }
2448
2449 static int __bnxt_poll_cqs(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
2450 {
2451 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2452 int i, work_done = 0;
2453
2454 for (i = 0; i < 2; i++) {
2455 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2456
2457 if (cpr2) {
2458 work_done += __bnxt_poll_work(bp, cpr2,
2459 budget - work_done);
2460 cpr->has_more_work |= cpr2->has_more_work;
2461 }
2462 }
2463 return work_done;
2464 }
2465
2466 static void __bnxt_poll_cqs_done(struct bnxt *bp, struct bnxt_napi *bnapi,
2467 u64 dbr_type)
2468 {
2469 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2470 int i;
2471
2472 for (i = 0; i < 2; i++) {
2473 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[i];
2474 struct bnxt_db_info *db;
2475
2476 if (cpr2 && cpr2->had_work_done) {
2477 db = &cpr2->cp_db;
2478 writeq(db->db_key64 | dbr_type |
2479 RING_CMP(cpr2->cp_raw_cons), db->doorbell);
2480 cpr2->had_work_done = 0;
2481 }
2482 }
2483 __bnxt_poll_work_done(bp, bnapi);
2484 }
2485
2486 static int bnxt_poll_p5(struct napi_struct *napi, int budget)
2487 {
2488 struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
2489 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2490 u32 raw_cons = cpr->cp_raw_cons;
2491 struct bnxt *bp = bnapi->bp;
2492 struct nqe_cn *nqcmp;
2493 int work_done = 0;
2494 u32 cons;
2495
2496 if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) {
2497 napi_complete(napi);
2498 return 0;
2499 }
2500 if (cpr->has_more_work) {
2501 cpr->has_more_work = 0;
2502 work_done = __bnxt_poll_cqs(bp, bnapi, budget);
2503 }
2504 while (1) {
2505 cons = RING_CMP(raw_cons);
2506 nqcmp = &cpr->nq_desc_ring[CP_RING(cons)][CP_IDX(cons)];
2507
2508 if (!NQ_CMP_VALID(nqcmp, raw_cons)) {
2509 if (cpr->has_more_work)
2510 break;
2511
2512 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ_ARMALL);
2513 cpr->cp_raw_cons = raw_cons;
2514 if (napi_complete_done(napi, work_done))
2515 BNXT_DB_NQ_ARM_P5(&cpr->cp_db,
2516 cpr->cp_raw_cons);
2517 return work_done;
2518 }
2519
2520 /* The valid test of the entry must be done first before
2521 * reading any further.
2522 */
2523 dma_rmb();
2524
2525 if (nqcmp->type == cpu_to_le16(NQ_CN_TYPE_CQ_NOTIFICATION)) {
2526 u32 idx = le32_to_cpu(nqcmp->cq_handle_low);
2527 struct bnxt_cp_ring_info *cpr2;
2528
2529 cpr2 = cpr->cp_ring_arr[idx];
2530 work_done += __bnxt_poll_work(bp, cpr2,
2531 budget - work_done);
2532 cpr->has_more_work |= cpr2->has_more_work;
2533 } else {
2534 bnxt_hwrm_handler(bp, (struct tx_cmp *)nqcmp);
2535 }
2536 raw_cons = NEXT_RAW_CMP(raw_cons);
2537 }
2538 __bnxt_poll_cqs_done(bp, bnapi, DBR_TYPE_CQ);
2539 if (raw_cons != cpr->cp_raw_cons) {
2540 cpr->cp_raw_cons = raw_cons;
2541 BNXT_DB_NQ_P5(&cpr->cp_db, raw_cons);
2542 }
2543 return work_done;
2544 }
2545
2546 static void bnxt_free_tx_skbs(struct bnxt *bp)
2547 {
2548 int i, max_idx;
2549 struct pci_dev *pdev = bp->pdev;
2550
2551 if (!bp->tx_ring)
2552 return;
2553
2554 max_idx = bp->tx_nr_pages * TX_DESC_CNT;
2555 for (i = 0; i < bp->tx_nr_rings; i++) {
2556 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2557 int j;
2558
2559 for (j = 0; j < max_idx;) {
2560 struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
2561 struct sk_buff *skb;
2562 int k, last;
2563
2564 if (i < bp->tx_nr_rings_xdp &&
2565 tx_buf->action == XDP_REDIRECT) {
2566 dma_unmap_single(&pdev->dev,
2567 dma_unmap_addr(tx_buf, mapping),
2568 dma_unmap_len(tx_buf, len),
2569 PCI_DMA_TODEVICE);
2570 xdp_return_frame(tx_buf->xdpf);
2571 tx_buf->action = 0;
2572 tx_buf->xdpf = NULL;
2573 j++;
2574 continue;
2575 }
2576
2577 skb = tx_buf->skb;
2578 if (!skb) {
2579 j++;
2580 continue;
2581 }
2582
2583 tx_buf->skb = NULL;
2584
2585 if (tx_buf->is_push) {
2586 dev_kfree_skb(skb);
2587 j += 2;
2588 continue;
2589 }
2590
2591 dma_unmap_single(&pdev->dev,
2592 dma_unmap_addr(tx_buf, mapping),
2593 skb_headlen(skb),
2594 PCI_DMA_TODEVICE);
2595
2596 last = tx_buf->nr_frags;
2597 j += 2;
2598 for (k = 0; k < last; k++, j++) {
2599 int ring_idx = j & bp->tx_ring_mask;
2600 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
2601
2602 tx_buf = &txr->tx_buf_ring[ring_idx];
2603 dma_unmap_page(
2604 &pdev->dev,
2605 dma_unmap_addr(tx_buf, mapping),
2606 skb_frag_size(frag), PCI_DMA_TODEVICE);
2607 }
2608 dev_kfree_skb(skb);
2609 }
2610 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
2611 }
2612 }
2613
2614 static void bnxt_free_one_rx_ring_skbs(struct bnxt *bp, int ring_nr)
2615 {
2616 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
2617 struct pci_dev *pdev = bp->pdev;
2618 struct bnxt_tpa_idx_map *map;
2619 int i, max_idx, max_agg_idx;
2620
2621 max_idx = bp->rx_nr_pages * RX_DESC_CNT;
2622 max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
2623 if (!rxr->rx_tpa)
2624 goto skip_rx_tpa_free;
2625
2626 for (i = 0; i < bp->max_tpa; i++) {
2627 struct bnxt_tpa_info *tpa_info = &rxr->rx_tpa[i];
2628 u8 *data = tpa_info->data;
2629
2630 if (!data)
2631 continue;
2632
2633 dma_unmap_single_attrs(&pdev->dev, tpa_info->mapping,
2634 bp->rx_buf_use_size, bp->rx_dir,
2635 DMA_ATTR_WEAK_ORDERING);
2636
2637 tpa_info->data = NULL;
2638
2639 kfree(data);
2640 }
2641
2642 skip_rx_tpa_free:
2643 for (i = 0; i < max_idx; i++) {
2644 struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[i];
2645 dma_addr_t mapping = rx_buf->mapping;
2646 void *data = rx_buf->data;
2647
2648 if (!data)
2649 continue;
2650
2651 rx_buf->data = NULL;
2652 if (BNXT_RX_PAGE_MODE(bp)) {
2653 mapping -= bp->rx_dma_offset;
2654 dma_unmap_page_attrs(&pdev->dev, mapping, PAGE_SIZE,
2655 bp->rx_dir,
2656 DMA_ATTR_WEAK_ORDERING);
2657 page_pool_recycle_direct(rxr->page_pool, data);
2658 } else {
2659 dma_unmap_single_attrs(&pdev->dev, mapping,
2660 bp->rx_buf_use_size, bp->rx_dir,
2661 DMA_ATTR_WEAK_ORDERING);
2662 kfree(data);
2663 }
2664 }
2665 for (i = 0; i < max_agg_idx; i++) {
2666 struct bnxt_sw_rx_agg_bd *rx_agg_buf = &rxr->rx_agg_ring[i];
2667 struct page *page = rx_agg_buf->page;
2668
2669 if (!page)
2670 continue;
2671
2672 dma_unmap_page_attrs(&pdev->dev, rx_agg_buf->mapping,
2673 BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE,
2674 DMA_ATTR_WEAK_ORDERING);
2675
2676 rx_agg_buf->page = NULL;
2677 __clear_bit(i, rxr->rx_agg_bmap);
2678
2679 __free_page(page);
2680 }
2681 if (rxr->rx_page) {
2682 __free_page(rxr->rx_page);
2683 rxr->rx_page = NULL;
2684 }
2685 map = rxr->rx_tpa_idx_map;
2686 if (map)
2687 memset(map->agg_idx_bmap, 0, sizeof(map->agg_idx_bmap));
2688 }
2689
2690 static void bnxt_free_rx_skbs(struct bnxt *bp)
2691 {
2692 int i;
2693
2694 if (!bp->rx_ring)
2695 return;
2696
2697 for (i = 0; i < bp->rx_nr_rings; i++)
2698 bnxt_free_one_rx_ring_skbs(bp, i);
2699 }
2700
2701 static void bnxt_free_skbs(struct bnxt *bp)
2702 {
2703 bnxt_free_tx_skbs(bp);
2704 bnxt_free_rx_skbs(bp);
2705 }
2706
2707 static void bnxt_init_ctx_mem(struct bnxt_mem_init *mem_init, void *p, int len)
2708 {
2709 u8 init_val = mem_init->init_val;
2710 u16 offset = mem_init->offset;
2711 u8 *p2 = p;
2712 int i;
2713
2714 if (!init_val)
2715 return;
2716 if (offset == BNXT_MEM_INVALID_OFFSET) {
2717 memset(p, init_val, len);
2718 return;
2719 }
2720 for (i = 0; i < len; i += mem_init->size)
2721 *(p2 + i + offset) = init_val;
2722 }
2723
2724 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2725 {
2726 struct pci_dev *pdev = bp->pdev;
2727 int i;
2728
2729 for (i = 0; i < rmem->nr_pages; i++) {
2730 if (!rmem->pg_arr[i])
2731 continue;
2732
2733 dma_free_coherent(&pdev->dev, rmem->page_size,
2734 rmem->pg_arr[i], rmem->dma_arr[i]);
2735
2736 rmem->pg_arr[i] = NULL;
2737 }
2738 if (rmem->pg_tbl) {
2739 size_t pg_tbl_size = rmem->nr_pages * 8;
2740
2741 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2742 pg_tbl_size = rmem->page_size;
2743 dma_free_coherent(&pdev->dev, pg_tbl_size,
2744 rmem->pg_tbl, rmem->pg_tbl_map);
2745 rmem->pg_tbl = NULL;
2746 }
2747 if (rmem->vmem_size && *rmem->vmem) {
2748 vfree(*rmem->vmem);
2749 *rmem->vmem = NULL;
2750 }
2751 }
2752
2753 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_mem_info *rmem)
2754 {
2755 struct pci_dev *pdev = bp->pdev;
2756 u64 valid_bit = 0;
2757 int i;
2758
2759 if (rmem->flags & (BNXT_RMEM_VALID_PTE_FLAG | BNXT_RMEM_RING_PTE_FLAG))
2760 valid_bit = PTU_PTE_VALID;
2761 if ((rmem->nr_pages > 1 || rmem->depth > 0) && !rmem->pg_tbl) {
2762 size_t pg_tbl_size = rmem->nr_pages * 8;
2763
2764 if (rmem->flags & BNXT_RMEM_USE_FULL_PAGE_FLAG)
2765 pg_tbl_size = rmem->page_size;
2766 rmem->pg_tbl = dma_alloc_coherent(&pdev->dev, pg_tbl_size,
2767 &rmem->pg_tbl_map,
2768 GFP_KERNEL);
2769 if (!rmem->pg_tbl)
2770 return -ENOMEM;
2771 }
2772
2773 for (i = 0; i < rmem->nr_pages; i++) {
2774 u64 extra_bits = valid_bit;
2775
2776 rmem->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
2777 rmem->page_size,
2778 &rmem->dma_arr[i],
2779 GFP_KERNEL);
2780 if (!rmem->pg_arr[i])
2781 return -ENOMEM;
2782
2783 if (rmem->mem_init)
2784 bnxt_init_ctx_mem(rmem->mem_init, rmem->pg_arr[i],
2785 rmem->page_size);
2786 if (rmem->nr_pages > 1 || rmem->depth > 0) {
2787 if (i == rmem->nr_pages - 2 &&
2788 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2789 extra_bits |= PTU_PTE_NEXT_TO_LAST;
2790 else if (i == rmem->nr_pages - 1 &&
2791 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG))
2792 extra_bits |= PTU_PTE_LAST;
2793 rmem->pg_tbl[i] =
2794 cpu_to_le64(rmem->dma_arr[i] | extra_bits);
2795 }
2796 }
2797
2798 if (rmem->vmem_size) {
2799 *rmem->vmem = vzalloc(rmem->vmem_size);
2800 if (!(*rmem->vmem))
2801 return -ENOMEM;
2802 }
2803 return 0;
2804 }
2805
2806 static void bnxt_free_tpa_info(struct bnxt *bp)
2807 {
2808 int i;
2809
2810 for (i = 0; i < bp->rx_nr_rings; i++) {
2811 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2812
2813 kfree(rxr->rx_tpa_idx_map);
2814 rxr->rx_tpa_idx_map = NULL;
2815 if (rxr->rx_tpa) {
2816 kfree(rxr->rx_tpa[0].agg_arr);
2817 rxr->rx_tpa[0].agg_arr = NULL;
2818 }
2819 kfree(rxr->rx_tpa);
2820 rxr->rx_tpa = NULL;
2821 }
2822 }
2823
2824 static int bnxt_alloc_tpa_info(struct bnxt *bp)
2825 {
2826 int i, j, total_aggs = 0;
2827
2828 bp->max_tpa = MAX_TPA;
2829 if (bp->flags & BNXT_FLAG_CHIP_P5) {
2830 if (!bp->max_tpa_v2)
2831 return 0;
2832 bp->max_tpa = max_t(u16, bp->max_tpa_v2, MAX_TPA_P5);
2833 total_aggs = bp->max_tpa * MAX_SKB_FRAGS;
2834 }
2835
2836 for (i = 0; i < bp->rx_nr_rings; i++) {
2837 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2838 struct rx_agg_cmp *agg;
2839
2840 rxr->rx_tpa = kcalloc(bp->max_tpa, sizeof(struct bnxt_tpa_info),
2841 GFP_KERNEL);
2842 if (!rxr->rx_tpa)
2843 return -ENOMEM;
2844
2845 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
2846 continue;
2847 agg = kcalloc(total_aggs, sizeof(*agg), GFP_KERNEL);
2848 rxr->rx_tpa[0].agg_arr = agg;
2849 if (!agg)
2850 return -ENOMEM;
2851 for (j = 1; j < bp->max_tpa; j++)
2852 rxr->rx_tpa[j].agg_arr = agg + j * MAX_SKB_FRAGS;
2853 rxr->rx_tpa_idx_map = kzalloc(sizeof(*rxr->rx_tpa_idx_map),
2854 GFP_KERNEL);
2855 if (!rxr->rx_tpa_idx_map)
2856 return -ENOMEM;
2857 }
2858 return 0;
2859 }
2860
2861 static void bnxt_free_rx_rings(struct bnxt *bp)
2862 {
2863 int i;
2864
2865 if (!bp->rx_ring)
2866 return;
2867
2868 bnxt_free_tpa_info(bp);
2869 for (i = 0; i < bp->rx_nr_rings; i++) {
2870 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2871 struct bnxt_ring_struct *ring;
2872
2873 if (rxr->xdp_prog)
2874 bpf_prog_put(rxr->xdp_prog);
2875
2876 if (xdp_rxq_info_is_reg(&rxr->xdp_rxq))
2877 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2878
2879 page_pool_destroy(rxr->page_pool);
2880 rxr->page_pool = NULL;
2881
2882 kfree(rxr->rx_agg_bmap);
2883 rxr->rx_agg_bmap = NULL;
2884
2885 ring = &rxr->rx_ring_struct;
2886 bnxt_free_ring(bp, &ring->ring_mem);
2887
2888 ring = &rxr->rx_agg_ring_struct;
2889 bnxt_free_ring(bp, &ring->ring_mem);
2890 }
2891 }
2892
2893 static int bnxt_alloc_rx_page_pool(struct bnxt *bp,
2894 struct bnxt_rx_ring_info *rxr)
2895 {
2896 struct page_pool_params pp = { 0 };
2897
2898 pp.pool_size = bp->rx_ring_size;
2899 pp.nid = dev_to_node(&bp->pdev->dev);
2900 pp.dev = &bp->pdev->dev;
2901 pp.dma_dir = DMA_BIDIRECTIONAL;
2902
2903 rxr->page_pool = page_pool_create(&pp);
2904 if (IS_ERR(rxr->page_pool)) {
2905 int err = PTR_ERR(rxr->page_pool);
2906
2907 rxr->page_pool = NULL;
2908 return err;
2909 }
2910 return 0;
2911 }
2912
2913 static int bnxt_alloc_rx_rings(struct bnxt *bp)
2914 {
2915 int i, rc = 0, agg_rings = 0;
2916
2917 if (!bp->rx_ring)
2918 return -ENOMEM;
2919
2920 if (bp->flags & BNXT_FLAG_AGG_RINGS)
2921 agg_rings = 1;
2922
2923 for (i = 0; i < bp->rx_nr_rings; i++) {
2924 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
2925 struct bnxt_ring_struct *ring;
2926
2927 ring = &rxr->rx_ring_struct;
2928
2929 rc = bnxt_alloc_rx_page_pool(bp, rxr);
2930 if (rc)
2931 return rc;
2932
2933 rc = xdp_rxq_info_reg(&rxr->xdp_rxq, bp->dev, i, 0);
2934 if (rc < 0)
2935 return rc;
2936
2937 rc = xdp_rxq_info_reg_mem_model(&rxr->xdp_rxq,
2938 MEM_TYPE_PAGE_POOL,
2939 rxr->page_pool);
2940 if (rc) {
2941 xdp_rxq_info_unreg(&rxr->xdp_rxq);
2942 return rc;
2943 }
2944
2945 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2946 if (rc)
2947 return rc;
2948
2949 ring->grp_idx = i;
2950 if (agg_rings) {
2951 u16 mem_size;
2952
2953 ring = &rxr->rx_agg_ring_struct;
2954 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
2955 if (rc)
2956 return rc;
2957
2958 ring->grp_idx = i;
2959 rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
2960 mem_size = rxr->rx_agg_bmap_size / 8;
2961 rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
2962 if (!rxr->rx_agg_bmap)
2963 return -ENOMEM;
2964 }
2965 }
2966 if (bp->flags & BNXT_FLAG_TPA)
2967 rc = bnxt_alloc_tpa_info(bp);
2968 return rc;
2969 }
2970
2971 static void bnxt_free_tx_rings(struct bnxt *bp)
2972 {
2973 int i;
2974 struct pci_dev *pdev = bp->pdev;
2975
2976 if (!bp->tx_ring)
2977 return;
2978
2979 for (i = 0; i < bp->tx_nr_rings; i++) {
2980 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2981 struct bnxt_ring_struct *ring;
2982
2983 if (txr->tx_push) {
2984 dma_free_coherent(&pdev->dev, bp->tx_push_size,
2985 txr->tx_push, txr->tx_push_mapping);
2986 txr->tx_push = NULL;
2987 }
2988
2989 ring = &txr->tx_ring_struct;
2990
2991 bnxt_free_ring(bp, &ring->ring_mem);
2992 }
2993 }
2994
2995 static int bnxt_alloc_tx_rings(struct bnxt *bp)
2996 {
2997 int i, j, rc;
2998 struct pci_dev *pdev = bp->pdev;
2999
3000 bp->tx_push_size = 0;
3001 if (bp->tx_push_thresh) {
3002 int push_size;
3003
3004 push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
3005 bp->tx_push_thresh);
3006
3007 if (push_size > 256) {
3008 push_size = 0;
3009 bp->tx_push_thresh = 0;
3010 }
3011
3012 bp->tx_push_size = push_size;
3013 }
3014
3015 for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
3016 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3017 struct bnxt_ring_struct *ring;
3018 u8 qidx;
3019
3020 ring = &txr->tx_ring_struct;
3021
3022 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3023 if (rc)
3024 return rc;
3025
3026 ring->grp_idx = txr->bnapi->index;
3027 if (bp->tx_push_size) {
3028 dma_addr_t mapping;
3029
3030 /* One pre-allocated DMA buffer to backup
3031 * TX push operation
3032 */
3033 txr->tx_push = dma_alloc_coherent(&pdev->dev,
3034 bp->tx_push_size,
3035 &txr->tx_push_mapping,
3036 GFP_KERNEL);
3037
3038 if (!txr->tx_push)
3039 return -ENOMEM;
3040
3041 mapping = txr->tx_push_mapping +
3042 sizeof(struct tx_push_bd);
3043 txr->data_mapping = cpu_to_le64(mapping);
3044 }
3045 qidx = bp->tc_to_qidx[j];
3046 ring->queue_id = bp->q_info[qidx].queue_id;
3047 if (i < bp->tx_nr_rings_xdp)
3048 continue;
3049 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
3050 j++;
3051 }
3052 return 0;
3053 }
3054
3055 static void bnxt_free_cp_rings(struct bnxt *bp)
3056 {
3057 int i;
3058
3059 if (!bp->bnapi)
3060 return;
3061
3062 for (i = 0; i < bp->cp_nr_rings; i++) {
3063 struct bnxt_napi *bnapi = bp->bnapi[i];
3064 struct bnxt_cp_ring_info *cpr;
3065 struct bnxt_ring_struct *ring;
3066 int j;
3067
3068 if (!bnapi)
3069 continue;
3070
3071 cpr = &bnapi->cp_ring;
3072 ring = &cpr->cp_ring_struct;
3073
3074 bnxt_free_ring(bp, &ring->ring_mem);
3075
3076 for (j = 0; j < 2; j++) {
3077 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3078
3079 if (cpr2) {
3080 ring = &cpr2->cp_ring_struct;
3081 bnxt_free_ring(bp, &ring->ring_mem);
3082 kfree(cpr2);
3083 cpr->cp_ring_arr[j] = NULL;
3084 }
3085 }
3086 }
3087 }
3088
3089 static struct bnxt_cp_ring_info *bnxt_alloc_cp_sub_ring(struct bnxt *bp)
3090 {
3091 struct bnxt_ring_mem_info *rmem;
3092 struct bnxt_ring_struct *ring;
3093 struct bnxt_cp_ring_info *cpr;
3094 int rc;
3095
3096 cpr = kzalloc(sizeof(*cpr), GFP_KERNEL);
3097 if (!cpr)
3098 return NULL;
3099
3100 ring = &cpr->cp_ring_struct;
3101 rmem = &ring->ring_mem;
3102 rmem->nr_pages = bp->cp_nr_pages;
3103 rmem->page_size = HW_CMPD_RING_SIZE;
3104 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3105 rmem->dma_arr = cpr->cp_desc_mapping;
3106 rmem->flags = BNXT_RMEM_RING_PTE_FLAG;
3107 rc = bnxt_alloc_ring(bp, rmem);
3108 if (rc) {
3109 bnxt_free_ring(bp, rmem);
3110 kfree(cpr);
3111 cpr = NULL;
3112 }
3113 return cpr;
3114 }
3115
3116 static int bnxt_alloc_cp_rings(struct bnxt *bp)
3117 {
3118 bool sh = !!(bp->flags & BNXT_FLAG_SHARED_RINGS);
3119 int i, rc, ulp_base_vec, ulp_msix;
3120
3121 ulp_msix = bnxt_get_ulp_msix_num(bp);
3122 ulp_base_vec = bnxt_get_ulp_msix_base(bp);
3123 for (i = 0; i < bp->cp_nr_rings; i++) {
3124 struct bnxt_napi *bnapi = bp->bnapi[i];
3125 struct bnxt_cp_ring_info *cpr;
3126 struct bnxt_ring_struct *ring;
3127
3128 if (!bnapi)
3129 continue;
3130
3131 cpr = &bnapi->cp_ring;
3132 cpr->bnapi = bnapi;
3133 ring = &cpr->cp_ring_struct;
3134
3135 rc = bnxt_alloc_ring(bp, &ring->ring_mem);
3136 if (rc)
3137 return rc;
3138
3139 if (ulp_msix && i >= ulp_base_vec)
3140 ring->map_idx = i + ulp_msix;
3141 else
3142 ring->map_idx = i;
3143
3144 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
3145 continue;
3146
3147 if (i < bp->rx_nr_rings) {
3148 struct bnxt_cp_ring_info *cpr2 =
3149 bnxt_alloc_cp_sub_ring(bp);
3150
3151 cpr->cp_ring_arr[BNXT_RX_HDL] = cpr2;
3152 if (!cpr2)
3153 return -ENOMEM;
3154 cpr2->bnapi = bnapi;
3155 }
3156 if ((sh && i < bp->tx_nr_rings) ||
3157 (!sh && i >= bp->rx_nr_rings)) {
3158 struct bnxt_cp_ring_info *cpr2 =
3159 bnxt_alloc_cp_sub_ring(bp);
3160
3161 cpr->cp_ring_arr[BNXT_TX_HDL] = cpr2;
3162 if (!cpr2)
3163 return -ENOMEM;
3164 cpr2->bnapi = bnapi;
3165 }
3166 }
3167 return 0;
3168 }
3169
3170 static void bnxt_init_ring_struct(struct bnxt *bp)
3171 {
3172 int i;
3173
3174 for (i = 0; i < bp->cp_nr_rings; i++) {
3175 struct bnxt_napi *bnapi = bp->bnapi[i];
3176 struct bnxt_ring_mem_info *rmem;
3177 struct bnxt_cp_ring_info *cpr;
3178 struct bnxt_rx_ring_info *rxr;
3179 struct bnxt_tx_ring_info *txr;
3180 struct bnxt_ring_struct *ring;
3181
3182 if (!bnapi)
3183 continue;
3184
3185 cpr = &bnapi->cp_ring;
3186 ring = &cpr->cp_ring_struct;
3187 rmem = &ring->ring_mem;
3188 rmem->nr_pages = bp->cp_nr_pages;
3189 rmem->page_size = HW_CMPD_RING_SIZE;
3190 rmem->pg_arr = (void **)cpr->cp_desc_ring;
3191 rmem->dma_arr = cpr->cp_desc_mapping;
3192 rmem->vmem_size = 0;
3193
3194 rxr = bnapi->rx_ring;
3195 if (!rxr)
3196 goto skip_rx;
3197
3198 ring = &rxr->rx_ring_struct;
3199 rmem = &ring->ring_mem;
3200 rmem->nr_pages = bp->rx_nr_pages;
3201 rmem->page_size = HW_RXBD_RING_SIZE;
3202 rmem->pg_arr = (void **)rxr->rx_desc_ring;
3203 rmem->dma_arr = rxr->rx_desc_mapping;
3204 rmem->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
3205 rmem->vmem = (void **)&rxr->rx_buf_ring;
3206
3207 ring = &rxr->rx_agg_ring_struct;
3208 rmem = &ring->ring_mem;
3209 rmem->nr_pages = bp->rx_agg_nr_pages;
3210 rmem->page_size = HW_RXBD_RING_SIZE;
3211 rmem->pg_arr = (void **)rxr->rx_agg_desc_ring;
3212 rmem->dma_arr = rxr->rx_agg_desc_mapping;
3213 rmem->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
3214 rmem->vmem = (void **)&rxr->rx_agg_ring;
3215
3216 skip_rx:
3217 txr = bnapi->tx_ring;
3218 if (!txr)
3219 continue;
3220
3221 ring = &txr->tx_ring_struct;
3222 rmem = &ring->ring_mem;
3223 rmem->nr_pages = bp->tx_nr_pages;
3224 rmem->page_size = HW_RXBD_RING_SIZE;
3225 rmem->pg_arr = (void **)txr->tx_desc_ring;
3226 rmem->dma_arr = txr->tx_desc_mapping;
3227 rmem->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
3228 rmem->vmem = (void **)&txr->tx_buf_ring;
3229 }
3230 }
3231
3232 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
3233 {
3234 int i;
3235 u32 prod;
3236 struct rx_bd **rx_buf_ring;
3237
3238 rx_buf_ring = (struct rx_bd **)ring->ring_mem.pg_arr;
3239 for (i = 0, prod = 0; i < ring->ring_mem.nr_pages; i++) {
3240 int j;
3241 struct rx_bd *rxbd;
3242
3243 rxbd = rx_buf_ring[i];
3244 if (!rxbd)
3245 continue;
3246
3247 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
3248 rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
3249 rxbd->rx_bd_opaque = prod;
3250 }
3251 }
3252 }
3253
3254 static int bnxt_alloc_one_rx_ring(struct bnxt *bp, int ring_nr)
3255 {
3256 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
3257 struct net_device *dev = bp->dev;
3258 u32 prod;
3259 int i;
3260
3261 prod = rxr->rx_prod;
3262 for (i = 0; i < bp->rx_ring_size; i++) {
3263 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL)) {
3264 netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
3265 ring_nr, i, bp->rx_ring_size);
3266 break;
3267 }
3268 prod = NEXT_RX(prod);
3269 }
3270 rxr->rx_prod = prod;
3271
3272 if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
3273 return 0;
3274
3275 prod = rxr->rx_agg_prod;
3276 for (i = 0; i < bp->rx_agg_ring_size; i++) {
3277 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL)) {
3278 netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
3279 ring_nr, i, bp->rx_ring_size);
3280 break;
3281 }
3282 prod = NEXT_RX_AGG(prod);
3283 }
3284 rxr->rx_agg_prod = prod;
3285
3286 if (rxr->rx_tpa) {
3287 dma_addr_t mapping;
3288 u8 *data;
3289
3290 for (i = 0; i < bp->max_tpa; i++) {
3291 data = __bnxt_alloc_rx_data(bp, &mapping, GFP_KERNEL);
3292 if (!data)
3293 return -ENOMEM;
3294
3295 rxr->rx_tpa[i].data = data;
3296 rxr->rx_tpa[i].data_ptr = data + bp->rx_offset;
3297 rxr->rx_tpa[i].mapping = mapping;
3298 }
3299 }
3300 return 0;
3301 }
3302
3303 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
3304 {
3305 struct bnxt_rx_ring_info *rxr;
3306 struct bnxt_ring_struct *ring;
3307 u32 type;
3308
3309 type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
3310 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
3311
3312 if (NET_IP_ALIGN == 2)
3313 type |= RX_BD_FLAGS_SOP;
3314
3315 rxr = &bp->rx_ring[ring_nr];
3316 ring = &rxr->rx_ring_struct;
3317 bnxt_init_rxbd_pages(ring, type);
3318
3319 if (BNXT_RX_PAGE_MODE(bp) && bp->xdp_prog) {
3320 bpf_prog_add(bp->xdp_prog, 1);
3321 rxr->xdp_prog = bp->xdp_prog;
3322 }
3323 ring->fw_ring_id = INVALID_HW_RING_ID;
3324
3325 ring = &rxr->rx_agg_ring_struct;
3326 ring->fw_ring_id = INVALID_HW_RING_ID;
3327
3328 if ((bp->flags & BNXT_FLAG_AGG_RINGS)) {
3329 type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
3330 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
3331
3332 bnxt_init_rxbd_pages(ring, type);
3333 }
3334
3335 return bnxt_alloc_one_rx_ring(bp, ring_nr);
3336 }
3337
3338 static void bnxt_init_cp_rings(struct bnxt *bp)
3339 {
3340 int i, j;
3341
3342 for (i = 0; i < bp->cp_nr_rings; i++) {
3343 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
3344 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3345
3346 ring->fw_ring_id = INVALID_HW_RING_ID;
3347 cpr->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3348 cpr->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3349 for (j = 0; j < 2; j++) {
3350 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
3351
3352 if (!cpr2)
3353 continue;
3354
3355 ring = &cpr2->cp_ring_struct;
3356 ring->fw_ring_id = INVALID_HW_RING_ID;
3357 cpr2->rx_ring_coal.coal_ticks = bp->rx_coal.coal_ticks;
3358 cpr2->rx_ring_coal.coal_bufs = bp->rx_coal.coal_bufs;
3359 }
3360 }
3361 }
3362
3363 static int bnxt_init_rx_rings(struct bnxt *bp)
3364 {
3365 int i, rc = 0;
3366
3367 if (BNXT_RX_PAGE_MODE(bp)) {
3368 bp->rx_offset = NET_IP_ALIGN + XDP_PACKET_HEADROOM;
3369 bp->rx_dma_offset = XDP_PACKET_HEADROOM;
3370 } else {
3371 bp->rx_offset = BNXT_RX_OFFSET;
3372 bp->rx_dma_offset = BNXT_RX_DMA_OFFSET;
3373 }
3374
3375 for (i = 0; i < bp->rx_nr_rings; i++) {
3376 rc = bnxt_init_one_rx_ring(bp, i);
3377 if (rc)
3378 break;
3379 }
3380
3381 return rc;
3382 }
3383
3384 static int bnxt_init_tx_rings(struct bnxt *bp)
3385 {
3386 u16 i;
3387
3388 bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
3389 MAX_SKB_FRAGS + 1);
3390
3391 for (i = 0; i < bp->tx_nr_rings; i++) {
3392 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3393 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3394
3395 ring->fw_ring_id = INVALID_HW_RING_ID;
3396 }
3397
3398 return 0;
3399 }
3400
3401 static void bnxt_free_ring_grps(struct bnxt *bp)
3402 {
3403 kfree(bp->grp_info);
3404 bp->grp_info = NULL;
3405 }
3406
3407 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
3408 {
3409 int i;
3410
3411 if (irq_re_init) {
3412 bp->grp_info = kcalloc(bp->cp_nr_rings,
3413 sizeof(struct bnxt_ring_grp_info),
3414 GFP_KERNEL);
3415 if (!bp->grp_info)
3416 return -ENOMEM;
3417 }
3418 for (i = 0; i < bp->cp_nr_rings; i++) {
3419 if (irq_re_init)
3420 bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
3421 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3422 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
3423 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
3424 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3425 }
3426 return 0;
3427 }
3428
3429 static void bnxt_free_vnics(struct bnxt *bp)
3430 {
3431 kfree(bp->vnic_info);
3432 bp->vnic_info = NULL;
3433 bp->nr_vnics = 0;
3434 }
3435
3436 static int bnxt_alloc_vnics(struct bnxt *bp)
3437 {
3438 int num_vnics = 1;
3439
3440 #ifdef CONFIG_RFS_ACCEL
3441 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
3442 num_vnics += bp->rx_nr_rings;
3443 #endif
3444
3445 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
3446 num_vnics++;
3447
3448 bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
3449 GFP_KERNEL);
3450 if (!bp->vnic_info)
3451 return -ENOMEM;
3452
3453 bp->nr_vnics = num_vnics;
3454 return 0;
3455 }
3456
3457 static void bnxt_init_vnics(struct bnxt *bp)
3458 {
3459 int i;
3460
3461 for (i = 0; i < bp->nr_vnics; i++) {
3462 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3463 int j;
3464
3465 vnic->fw_vnic_id = INVALID_HW_RING_ID;
3466 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++)
3467 vnic->fw_rss_cos_lb_ctx[j] = INVALID_HW_RING_ID;
3468
3469 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
3470
3471 if (bp->vnic_info[i].rss_hash_key) {
3472 if (i == 0)
3473 prandom_bytes(vnic->rss_hash_key,
3474 HW_HASH_KEY_SIZE);
3475 else
3476 memcpy(vnic->rss_hash_key,
3477 bp->vnic_info[0].rss_hash_key,
3478 HW_HASH_KEY_SIZE);
3479 }
3480 }
3481 }
3482
3483 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
3484 {
3485 int pages;
3486
3487 pages = ring_size / desc_per_pg;
3488
3489 if (!pages)
3490 return 1;
3491
3492 pages++;
3493
3494 while (pages & (pages - 1))
3495 pages++;
3496
3497 return pages;
3498 }
3499
3500 void bnxt_set_tpa_flags(struct bnxt *bp)
3501 {
3502 bp->flags &= ~BNXT_FLAG_TPA;
3503 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
3504 return;
3505 if (bp->dev->features & NETIF_F_LRO)
3506 bp->flags |= BNXT_FLAG_LRO;
3507 else if (bp->dev->features & NETIF_F_GRO_HW)
3508 bp->flags |= BNXT_FLAG_GRO;
3509 }
3510
3511 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
3512 * be set on entry.
3513 */
3514 void bnxt_set_ring_params(struct bnxt *bp)
3515 {
3516 u32 ring_size, rx_size, rx_space, max_rx_cmpl;
3517 u32 agg_factor = 0, agg_ring_size = 0;
3518
3519 /* 8 for CRC and VLAN */
3520 rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
3521
3522 rx_space = rx_size + NET_SKB_PAD +
3523 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3524
3525 bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
3526 ring_size = bp->rx_ring_size;
3527 bp->rx_agg_ring_size = 0;
3528 bp->rx_agg_nr_pages = 0;
3529
3530 if (bp->flags & BNXT_FLAG_TPA)
3531 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
3532
3533 bp->flags &= ~BNXT_FLAG_JUMBO;
3534 if (rx_space > PAGE_SIZE && !(bp->flags & BNXT_FLAG_NO_AGG_RINGS)) {
3535 u32 jumbo_factor;
3536
3537 bp->flags |= BNXT_FLAG_JUMBO;
3538 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
3539 if (jumbo_factor > agg_factor)
3540 agg_factor = jumbo_factor;
3541 }
3542 agg_ring_size = ring_size * agg_factor;
3543
3544 if (agg_ring_size) {
3545 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
3546 RX_DESC_CNT);
3547 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
3548 u32 tmp = agg_ring_size;
3549
3550 bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
3551 agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
3552 netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
3553 tmp, agg_ring_size);
3554 }
3555 bp->rx_agg_ring_size = agg_ring_size;
3556 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
3557 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
3558 rx_space = rx_size + NET_SKB_PAD +
3559 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3560 }
3561
3562 bp->rx_buf_use_size = rx_size;
3563 bp->rx_buf_size = rx_space;
3564
3565 bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
3566 bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
3567
3568 ring_size = bp->tx_ring_size;
3569 bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
3570 bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
3571
3572 max_rx_cmpl = bp->rx_ring_size;
3573 /* MAX TPA needs to be added because TPA_START completions are
3574 * immediately recycled, so the TPA completions are not bound by
3575 * the RX ring size.
3576 */
3577 if (bp->flags & BNXT_FLAG_TPA)
3578 max_rx_cmpl += bp->max_tpa;
3579 /* RX and TPA completions are 32-byte, all others are 16-byte */
3580 ring_size = max_rx_cmpl * 2 + agg_ring_size + bp->tx_ring_size;
3581 bp->cp_ring_size = ring_size;
3582
3583 bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
3584 if (bp->cp_nr_pages > MAX_CP_PAGES) {
3585 bp->cp_nr_pages = MAX_CP_PAGES;
3586 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
3587 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
3588 ring_size, bp->cp_ring_size);
3589 }
3590 bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
3591 bp->cp_ring_mask = bp->cp_bit - 1;
3592 }
3593
3594 /* Changing allocation mode of RX rings.
3595 * TODO: Update when extending xdp_rxq_info to support allocation modes.
3596 */
3597 int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode)
3598 {
3599 if (page_mode) {
3600 if (bp->dev->mtu > BNXT_MAX_PAGE_MODE_MTU)
3601 return -EOPNOTSUPP;
3602 bp->dev->max_mtu =
3603 min_t(u16, bp->max_mtu, BNXT_MAX_PAGE_MODE_MTU);
3604 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
3605 bp->flags |= BNXT_FLAG_NO_AGG_RINGS | BNXT_FLAG_RX_PAGE_MODE;
3606 bp->rx_dir = DMA_BIDIRECTIONAL;
3607 bp->rx_skb_func = bnxt_rx_page_skb;
3608 /* Disable LRO or GRO_HW */
3609 netdev_update_features(bp->dev);
3610 } else {
3611 bp->dev->max_mtu = bp->max_mtu;
3612 bp->flags &= ~BNXT_FLAG_RX_PAGE_MODE;
3613 bp->rx_dir = DMA_FROM_DEVICE;
3614 bp->rx_skb_func = bnxt_rx_skb;
3615 }
3616 return 0;
3617 }
3618
3619 static void bnxt_free_vnic_attributes(struct bnxt *bp)
3620 {
3621 int i;
3622 struct bnxt_vnic_info *vnic;
3623 struct pci_dev *pdev = bp->pdev;
3624
3625 if (!bp->vnic_info)
3626 return;
3627
3628 for (i = 0; i < bp->nr_vnics; i++) {
3629 vnic = &bp->vnic_info[i];
3630
3631 kfree(vnic->fw_grp_ids);
3632 vnic->fw_grp_ids = NULL;
3633
3634 kfree(vnic->uc_list);
3635 vnic->uc_list = NULL;
3636
3637 if (vnic->mc_list) {
3638 dma_free_coherent(&pdev->dev, vnic->mc_list_size,
3639 vnic->mc_list, vnic->mc_list_mapping);
3640 vnic->mc_list = NULL;
3641 }
3642
3643 if (vnic->rss_table) {
3644 dma_free_coherent(&pdev->dev, vnic->rss_table_size,
3645 vnic->rss_table,
3646 vnic->rss_table_dma_addr);
3647 vnic->rss_table = NULL;
3648 }
3649
3650 vnic->rss_hash_key = NULL;
3651 vnic->flags = 0;
3652 }
3653 }
3654
3655 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
3656 {
3657 int i, rc = 0, size;
3658 struct bnxt_vnic_info *vnic;
3659 struct pci_dev *pdev = bp->pdev;
3660 int max_rings;
3661
3662 for (i = 0; i < bp->nr_vnics; i++) {
3663 vnic = &bp->vnic_info[i];
3664
3665 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
3666 int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
3667
3668 if (mem_size > 0) {
3669 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
3670 if (!vnic->uc_list) {
3671 rc = -ENOMEM;
3672 goto out;
3673 }
3674 }
3675 }
3676
3677 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
3678 vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
3679 vnic->mc_list =
3680 dma_alloc_coherent(&pdev->dev,
3681 vnic->mc_list_size,
3682 &vnic->mc_list_mapping,
3683 GFP_KERNEL);
3684 if (!vnic->mc_list) {
3685 rc = -ENOMEM;
3686 goto out;
3687 }
3688 }
3689
3690 if (bp->flags & BNXT_FLAG_CHIP_P5)
3691 goto vnic_skip_grps;
3692
3693 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3694 max_rings = bp->rx_nr_rings;
3695 else
3696 max_rings = 1;
3697
3698 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
3699 if (!vnic->fw_grp_ids) {
3700 rc = -ENOMEM;
3701 goto out;
3702 }
3703 vnic_skip_grps:
3704 if ((bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
3705 !(vnic->flags & BNXT_VNIC_RSS_FLAG))
3706 continue;
3707
3708 /* Allocate rss table and hash key */
3709 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
3710 if (bp->flags & BNXT_FLAG_CHIP_P5)
3711 size = L1_CACHE_ALIGN(BNXT_MAX_RSS_TABLE_SIZE_P5);
3712
3713 vnic->rss_table_size = size + HW_HASH_KEY_SIZE;
3714 vnic->rss_table = dma_alloc_coherent(&pdev->dev,
3715 vnic->rss_table_size,
3716 &vnic->rss_table_dma_addr,
3717 GFP_KERNEL);
3718 if (!vnic->rss_table) {
3719 rc = -ENOMEM;
3720 goto out;
3721 }
3722
3723 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
3724 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
3725 }
3726 return 0;
3727
3728 out:
3729 return rc;
3730 }
3731
3732 static void bnxt_free_hwrm_resources(struct bnxt *bp)
3733 {
3734 struct pci_dev *pdev = bp->pdev;
3735
3736 if (bp->hwrm_cmd_resp_addr) {
3737 dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
3738 bp->hwrm_cmd_resp_dma_addr);
3739 bp->hwrm_cmd_resp_addr = NULL;
3740 }
3741
3742 if (bp->hwrm_cmd_kong_resp_addr) {
3743 dma_free_coherent(&pdev->dev, PAGE_SIZE,
3744 bp->hwrm_cmd_kong_resp_addr,
3745 bp->hwrm_cmd_kong_resp_dma_addr);
3746 bp->hwrm_cmd_kong_resp_addr = NULL;
3747 }
3748 }
3749
3750 static int bnxt_alloc_kong_hwrm_resources(struct bnxt *bp)
3751 {
3752 struct pci_dev *pdev = bp->pdev;
3753
3754 if (bp->hwrm_cmd_kong_resp_addr)
3755 return 0;
3756
3757 bp->hwrm_cmd_kong_resp_addr =
3758 dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3759 &bp->hwrm_cmd_kong_resp_dma_addr,
3760 GFP_KERNEL);
3761 if (!bp->hwrm_cmd_kong_resp_addr)
3762 return -ENOMEM;
3763
3764 return 0;
3765 }
3766
3767 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
3768 {
3769 struct pci_dev *pdev = bp->pdev;
3770
3771 bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
3772 &bp->hwrm_cmd_resp_dma_addr,
3773 GFP_KERNEL);
3774 if (!bp->hwrm_cmd_resp_addr)
3775 return -ENOMEM;
3776
3777 return 0;
3778 }
3779
3780 static void bnxt_free_hwrm_short_cmd_req(struct bnxt *bp)
3781 {
3782 if (bp->hwrm_short_cmd_req_addr) {
3783 struct pci_dev *pdev = bp->pdev;
3784
3785 dma_free_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3786 bp->hwrm_short_cmd_req_addr,
3787 bp->hwrm_short_cmd_req_dma_addr);
3788 bp->hwrm_short_cmd_req_addr = NULL;
3789 }
3790 }
3791
3792 static int bnxt_alloc_hwrm_short_cmd_req(struct bnxt *bp)
3793 {
3794 struct pci_dev *pdev = bp->pdev;
3795
3796 if (bp->hwrm_short_cmd_req_addr)
3797 return 0;
3798
3799 bp->hwrm_short_cmd_req_addr =
3800 dma_alloc_coherent(&pdev->dev, bp->hwrm_max_ext_req_len,
3801 &bp->hwrm_short_cmd_req_dma_addr,
3802 GFP_KERNEL);
3803 if (!bp->hwrm_short_cmd_req_addr)
3804 return -ENOMEM;
3805
3806 return 0;
3807 }
3808
3809 static void bnxt_free_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats)
3810 {
3811 kfree(stats->hw_masks);
3812 stats->hw_masks = NULL;
3813 kfree(stats->sw_stats);
3814 stats->sw_stats = NULL;
3815 if (stats->hw_stats) {
3816 dma_free_coherent(&bp->pdev->dev, stats->len, stats->hw_stats,
3817 stats->hw_stats_map);
3818 stats->hw_stats = NULL;
3819 }
3820 }
3821
3822 static int bnxt_alloc_stats_mem(struct bnxt *bp, struct bnxt_stats_mem *stats,
3823 bool alloc_masks)
3824 {
3825 stats->hw_stats = dma_alloc_coherent(&bp->pdev->dev, stats->len,
3826 &stats->hw_stats_map, GFP_KERNEL);
3827 if (!stats->hw_stats)
3828 return -ENOMEM;
3829
3830 stats->sw_stats = kzalloc(stats->len, GFP_KERNEL);
3831 if (!stats->sw_stats)
3832 goto stats_mem_err;
3833
3834 if (alloc_masks) {
3835 stats->hw_masks = kzalloc(stats->len, GFP_KERNEL);
3836 if (!stats->hw_masks)
3837 goto stats_mem_err;
3838 }
3839 return 0;
3840
3841 stats_mem_err:
3842 bnxt_free_stats_mem(bp, stats);
3843 return -ENOMEM;
3844 }
3845
3846 static void bnxt_fill_masks(u64 *mask_arr, u64 mask, int count)
3847 {
3848 int i;
3849
3850 for (i = 0; i < count; i++)
3851 mask_arr[i] = mask;
3852 }
3853
3854 static void bnxt_copy_hw_masks(u64 *mask_arr, __le64 *hw_mask_arr, int count)
3855 {
3856 int i;
3857
3858 for (i = 0; i < count; i++)
3859 mask_arr[i] = le64_to_cpu(hw_mask_arr[i]);
3860 }
3861
3862 static int bnxt_hwrm_func_qstat_ext(struct bnxt *bp,
3863 struct bnxt_stats_mem *stats)
3864 {
3865 struct hwrm_func_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
3866 struct hwrm_func_qstats_ext_input req = {0};
3867 __le64 *hw_masks;
3868 int rc;
3869
3870 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED) ||
3871 !(bp->flags & BNXT_FLAG_CHIP_P5))
3872 return -EOPNOTSUPP;
3873
3874 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QSTATS_EXT, -1, -1);
3875 req.fid = cpu_to_le16(0xffff);
3876 req.flags = FUNC_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
3877 mutex_lock(&bp->hwrm_cmd_lock);
3878 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3879 if (rc)
3880 goto qstat_exit;
3881
3882 hw_masks = &resp->rx_ucast_pkts;
3883 bnxt_copy_hw_masks(stats->hw_masks, hw_masks, stats->len / 8);
3884
3885 qstat_exit:
3886 mutex_unlock(&bp->hwrm_cmd_lock);
3887 return rc;
3888 }
3889
3890 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags);
3891 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags);
3892
3893 static void bnxt_init_stats(struct bnxt *bp)
3894 {
3895 struct bnxt_napi *bnapi = bp->bnapi[0];
3896 struct bnxt_cp_ring_info *cpr;
3897 struct bnxt_stats_mem *stats;
3898 __le64 *rx_stats, *tx_stats;
3899 int rc, rx_count, tx_count;
3900 u64 *rx_masks, *tx_masks;
3901 u64 mask;
3902 u8 flags;
3903
3904 cpr = &bnapi->cp_ring;
3905 stats = &cpr->stats;
3906 rc = bnxt_hwrm_func_qstat_ext(bp, stats);
3907 if (rc) {
3908 if (bp->flags & BNXT_FLAG_CHIP_P5)
3909 mask = (1ULL << 48) - 1;
3910 else
3911 mask = -1ULL;
3912 bnxt_fill_masks(stats->hw_masks, mask, stats->len / 8);
3913 }
3914 if (bp->flags & BNXT_FLAG_PORT_STATS) {
3915 stats = &bp->port_stats;
3916 rx_stats = stats->hw_stats;
3917 rx_masks = stats->hw_masks;
3918 rx_count = sizeof(struct rx_port_stats) / 8;
3919 tx_stats = rx_stats + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3920 tx_masks = rx_masks + BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
3921 tx_count = sizeof(struct tx_port_stats) / 8;
3922
3923 flags = PORT_QSTATS_REQ_FLAGS_COUNTER_MASK;
3924 rc = bnxt_hwrm_port_qstats(bp, flags);
3925 if (rc) {
3926 mask = (1ULL << 40) - 1;
3927
3928 bnxt_fill_masks(rx_masks, mask, rx_count);
3929 bnxt_fill_masks(tx_masks, mask, tx_count);
3930 } else {
3931 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
3932 bnxt_copy_hw_masks(tx_masks, tx_stats, tx_count);
3933 bnxt_hwrm_port_qstats(bp, 0);
3934 }
3935 }
3936 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
3937 stats = &bp->rx_port_stats_ext;
3938 rx_stats = stats->hw_stats;
3939 rx_masks = stats->hw_masks;
3940 rx_count = sizeof(struct rx_port_stats_ext) / 8;
3941 stats = &bp->tx_port_stats_ext;
3942 tx_stats = stats->hw_stats;
3943 tx_masks = stats->hw_masks;
3944 tx_count = sizeof(struct tx_port_stats_ext) / 8;
3945
3946 flags = PORT_QSTATS_EXT_REQ_FLAGS_COUNTER_MASK;
3947 rc = bnxt_hwrm_port_qstats_ext(bp, flags);
3948 if (rc) {
3949 mask = (1ULL << 40) - 1;
3950
3951 bnxt_fill_masks(rx_masks, mask, rx_count);
3952 if (tx_stats)
3953 bnxt_fill_masks(tx_masks, mask, tx_count);
3954 } else {
3955 bnxt_copy_hw_masks(rx_masks, rx_stats, rx_count);
3956 if (tx_stats)
3957 bnxt_copy_hw_masks(tx_masks, tx_stats,
3958 tx_count);
3959 bnxt_hwrm_port_qstats_ext(bp, 0);
3960 }
3961 }
3962 }
3963
3964 static void bnxt_free_port_stats(struct bnxt *bp)
3965 {
3966 bp->flags &= ~BNXT_FLAG_PORT_STATS;
3967 bp->flags &= ~BNXT_FLAG_PORT_STATS_EXT;
3968
3969 bnxt_free_stats_mem(bp, &bp->port_stats);
3970 bnxt_free_stats_mem(bp, &bp->rx_port_stats_ext);
3971 bnxt_free_stats_mem(bp, &bp->tx_port_stats_ext);
3972 }
3973
3974 static void bnxt_free_ring_stats(struct bnxt *bp)
3975 {
3976 int i;
3977
3978 if (!bp->bnapi)
3979 return;
3980
3981 for (i = 0; i < bp->cp_nr_rings; i++) {
3982 struct bnxt_napi *bnapi = bp->bnapi[i];
3983 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3984
3985 bnxt_free_stats_mem(bp, &cpr->stats);
3986 }
3987 }
3988
3989 static int bnxt_alloc_stats(struct bnxt *bp)
3990 {
3991 u32 size, i;
3992 int rc;
3993
3994 size = bp->hw_ring_stats_size;
3995
3996 for (i = 0; i < bp->cp_nr_rings; i++) {
3997 struct bnxt_napi *bnapi = bp->bnapi[i];
3998 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3999
4000 cpr->stats.len = size;
4001 rc = bnxt_alloc_stats_mem(bp, &cpr->stats, !i);
4002 if (rc)
4003 return rc;
4004
4005 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
4006 }
4007
4008 if (BNXT_VF(bp) || bp->chip_num == CHIP_NUM_58700)
4009 return 0;
4010
4011 if (bp->port_stats.hw_stats)
4012 goto alloc_ext_stats;
4013
4014 bp->port_stats.len = BNXT_PORT_STATS_SIZE;
4015 rc = bnxt_alloc_stats_mem(bp, &bp->port_stats, true);
4016 if (rc)
4017 return rc;
4018
4019 bp->flags |= BNXT_FLAG_PORT_STATS;
4020
4021 alloc_ext_stats:
4022 /* Display extended statistics only if FW supports it */
4023 if (bp->hwrm_spec_code < 0x10804 || bp->hwrm_spec_code == 0x10900)
4024 if (!(bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED))
4025 return 0;
4026
4027 if (bp->rx_port_stats_ext.hw_stats)
4028 goto alloc_tx_ext_stats;
4029
4030 bp->rx_port_stats_ext.len = sizeof(struct rx_port_stats_ext);
4031 rc = bnxt_alloc_stats_mem(bp, &bp->rx_port_stats_ext, true);
4032 /* Extended stats are optional */
4033 if (rc)
4034 return 0;
4035
4036 alloc_tx_ext_stats:
4037 if (bp->tx_port_stats_ext.hw_stats)
4038 return 0;
4039
4040 if (bp->hwrm_spec_code >= 0x10902 ||
4041 (bp->fw_cap & BNXT_FW_CAP_EXT_STATS_SUPPORTED)) {
4042 bp->tx_port_stats_ext.len = sizeof(struct tx_port_stats_ext);
4043 rc = bnxt_alloc_stats_mem(bp, &bp->tx_port_stats_ext, true);
4044 /* Extended stats are optional */
4045 if (rc)
4046 return 0;
4047 }
4048 bp->flags |= BNXT_FLAG_PORT_STATS_EXT;
4049 return 0;
4050 }
4051
4052 static void bnxt_clear_ring_indices(struct bnxt *bp)
4053 {
4054 int i;
4055
4056 if (!bp->bnapi)
4057 return;
4058
4059 for (i = 0; i < bp->cp_nr_rings; i++) {
4060 struct bnxt_napi *bnapi = bp->bnapi[i];
4061 struct bnxt_cp_ring_info *cpr;
4062 struct bnxt_rx_ring_info *rxr;
4063 struct bnxt_tx_ring_info *txr;
4064
4065 if (!bnapi)
4066 continue;
4067
4068 cpr = &bnapi->cp_ring;
4069 cpr->cp_raw_cons = 0;
4070
4071 txr = bnapi->tx_ring;
4072 if (txr) {
4073 txr->tx_prod = 0;
4074 txr->tx_cons = 0;
4075 }
4076
4077 rxr = bnapi->rx_ring;
4078 if (rxr) {
4079 rxr->rx_prod = 0;
4080 rxr->rx_agg_prod = 0;
4081 rxr->rx_sw_agg_prod = 0;
4082 rxr->rx_next_cons = 0;
4083 }
4084 }
4085 }
4086
4087 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
4088 {
4089 #ifdef CONFIG_RFS_ACCEL
4090 int i;
4091
4092 /* Under rtnl_lock and all our NAPIs have been disabled. It's
4093 * safe to delete the hash table.
4094 */
4095 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
4096 struct hlist_head *head;
4097 struct hlist_node *tmp;
4098 struct bnxt_ntuple_filter *fltr;
4099
4100 head = &bp->ntp_fltr_hash_tbl[i];
4101 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
4102 hlist_del(&fltr->hash);
4103 kfree(fltr);
4104 }
4105 }
4106 if (irq_reinit) {
4107 kfree(bp->ntp_fltr_bmap);
4108 bp->ntp_fltr_bmap = NULL;
4109 }
4110 bp->ntp_fltr_count = 0;
4111 #endif
4112 }
4113
4114 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
4115 {
4116 #ifdef CONFIG_RFS_ACCEL
4117 int i, rc = 0;
4118
4119 if (!(bp->flags & BNXT_FLAG_RFS))
4120 return 0;
4121
4122 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
4123 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
4124
4125 bp->ntp_fltr_count = 0;
4126 bp->ntp_fltr_bmap = kcalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
4127 sizeof(long),
4128 GFP_KERNEL);
4129
4130 if (!bp->ntp_fltr_bmap)
4131 rc = -ENOMEM;
4132
4133 return rc;
4134 #else
4135 return 0;
4136 #endif
4137 }
4138
4139 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
4140 {
4141 bnxt_free_vnic_attributes(bp);
4142 bnxt_free_tx_rings(bp);
4143 bnxt_free_rx_rings(bp);
4144 bnxt_free_cp_rings(bp);
4145 bnxt_free_ntp_fltrs(bp, irq_re_init);
4146 if (irq_re_init) {
4147 bnxt_free_ring_stats(bp);
4148 if (!(bp->fw_cap & BNXT_FW_CAP_PORT_STATS_NO_RESET) ||
4149 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
4150 bnxt_free_port_stats(bp);
4151 bnxt_free_ring_grps(bp);
4152 bnxt_free_vnics(bp);
4153 kfree(bp->tx_ring_map);
4154 bp->tx_ring_map = NULL;
4155 kfree(bp->tx_ring);
4156 bp->tx_ring = NULL;
4157 kfree(bp->rx_ring);
4158 bp->rx_ring = NULL;
4159 kfree(bp->bnapi);
4160 bp->bnapi = NULL;
4161 } else {
4162 bnxt_clear_ring_indices(bp);
4163 }
4164 }
4165
4166 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
4167 {
4168 int i, j, rc, size, arr_size;
4169 void *bnapi;
4170
4171 if (irq_re_init) {
4172 /* Allocate bnapi mem pointer array and mem block for
4173 * all queues
4174 */
4175 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
4176 bp->cp_nr_rings);
4177 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
4178 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
4179 if (!bnapi)
4180 return -ENOMEM;
4181
4182 bp->bnapi = bnapi;
4183 bnapi += arr_size;
4184 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
4185 bp->bnapi[i] = bnapi;
4186 bp->bnapi[i]->index = i;
4187 bp->bnapi[i]->bp = bp;
4188 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4189 struct bnxt_cp_ring_info *cpr =
4190 &bp->bnapi[i]->cp_ring;
4191
4192 cpr->cp_ring_struct.ring_mem.flags =
4193 BNXT_RMEM_RING_PTE_FLAG;
4194 }
4195 }
4196
4197 bp->rx_ring = kcalloc(bp->rx_nr_rings,
4198 sizeof(struct bnxt_rx_ring_info),
4199 GFP_KERNEL);
4200 if (!bp->rx_ring)
4201 return -ENOMEM;
4202
4203 for (i = 0; i < bp->rx_nr_rings; i++) {
4204 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
4205
4206 if (bp->flags & BNXT_FLAG_CHIP_P5) {
4207 rxr->rx_ring_struct.ring_mem.flags =
4208 BNXT_RMEM_RING_PTE_FLAG;
4209 rxr->rx_agg_ring_struct.ring_mem.flags =
4210 BNXT_RMEM_RING_PTE_FLAG;
4211 }
4212 rxr->bnapi = bp->bnapi[i];
4213 bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
4214 }
4215
4216 bp->tx_ring = kcalloc(bp->tx_nr_rings,
4217 sizeof(struct bnxt_tx_ring_info),
4218 GFP_KERNEL);
4219 if (!bp->tx_ring)
4220 return -ENOMEM;
4221
4222 bp->tx_ring_map = kcalloc(bp->tx_nr_rings, sizeof(u16),
4223 GFP_KERNEL);
4224
4225 if (!bp->tx_ring_map)
4226 return -ENOMEM;
4227
4228 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4229 j = 0;
4230 else
4231 j = bp->rx_nr_rings;
4232
4233 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
4234 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
4235
4236 if (bp->flags & BNXT_FLAG_CHIP_P5)
4237 txr->tx_ring_struct.ring_mem.flags =
4238 BNXT_RMEM_RING_PTE_FLAG;
4239 txr->bnapi = bp->bnapi[j];
4240 bp->bnapi[j]->tx_ring = txr;
4241 bp->tx_ring_map[i] = bp->tx_nr_rings_xdp + i;
4242 if (i >= bp->tx_nr_rings_xdp) {
4243 txr->txq_index = i - bp->tx_nr_rings_xdp;
4244 bp->bnapi[j]->tx_int = bnxt_tx_int;
4245 } else {
4246 bp->bnapi[j]->flags |= BNXT_NAPI_FLAG_XDP;
4247 bp->bnapi[j]->tx_int = bnxt_tx_int_xdp;
4248 }
4249 }
4250
4251 rc = bnxt_alloc_stats(bp);
4252 if (rc)
4253 goto alloc_mem_err;
4254 bnxt_init_stats(bp);
4255
4256 rc = bnxt_alloc_ntp_fltrs(bp);
4257 if (rc)
4258 goto alloc_mem_err;
4259
4260 rc = bnxt_alloc_vnics(bp);
4261 if (rc)
4262 goto alloc_mem_err;
4263 }
4264
4265 bnxt_init_ring_struct(bp);
4266
4267 rc = bnxt_alloc_rx_rings(bp);
4268 if (rc)
4269 goto alloc_mem_err;
4270
4271 rc = bnxt_alloc_tx_rings(bp);
4272 if (rc)
4273 goto alloc_mem_err;
4274
4275 rc = bnxt_alloc_cp_rings(bp);
4276 if (rc)
4277 goto alloc_mem_err;
4278
4279 bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
4280 BNXT_VNIC_UCAST_FLAG;
4281 rc = bnxt_alloc_vnic_attributes(bp);
4282 if (rc)
4283 goto alloc_mem_err;
4284 return 0;
4285
4286 alloc_mem_err:
4287 bnxt_free_mem(bp, true);
4288 return rc;
4289 }
4290
4291 static void bnxt_disable_int(struct bnxt *bp)
4292 {
4293 int i;
4294
4295 if (!bp->bnapi)
4296 return;
4297
4298 for (i = 0; i < bp->cp_nr_rings; i++) {
4299 struct bnxt_napi *bnapi = bp->bnapi[i];
4300 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4301 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
4302
4303 if (ring->fw_ring_id != INVALID_HW_RING_ID)
4304 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
4305 }
4306 }
4307
4308 static int bnxt_cp_num_to_irq_num(struct bnxt *bp, int n)
4309 {
4310 struct bnxt_napi *bnapi = bp->bnapi[n];
4311 struct bnxt_cp_ring_info *cpr;
4312
4313 cpr = &bnapi->cp_ring;
4314 return cpr->cp_ring_struct.map_idx;
4315 }
4316
4317 static void bnxt_disable_int_sync(struct bnxt *bp)
4318 {
4319 int i;
4320
4321 if (!bp->irq_tbl)
4322 return;
4323
4324 atomic_inc(&bp->intr_sem);
4325
4326 bnxt_disable_int(bp);
4327 for (i = 0; i < bp->cp_nr_rings; i++) {
4328 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
4329
4330 synchronize_irq(bp->irq_tbl[map_idx].vector);
4331 }
4332 }
4333
4334 static void bnxt_enable_int(struct bnxt *bp)
4335 {
4336 int i;
4337
4338 atomic_set(&bp->intr_sem, 0);
4339 for (i = 0; i < bp->cp_nr_rings; i++) {
4340 struct bnxt_napi *bnapi = bp->bnapi[i];
4341 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4342
4343 bnxt_db_nq_arm(bp, &cpr->cp_db, cpr->cp_raw_cons);
4344 }
4345 }
4346
4347 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
4348 u16 cmpl_ring, u16 target_id)
4349 {
4350 struct input *req = request;
4351
4352 req->req_type = cpu_to_le16(req_type);
4353 req->cmpl_ring = cpu_to_le16(cmpl_ring);
4354 req->target_id = cpu_to_le16(target_id);
4355 if (bnxt_kong_hwrm_message(bp, req))
4356 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
4357 else
4358 req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
4359 }
4360
4361 static int bnxt_hwrm_to_stderr(u32 hwrm_err)
4362 {
4363 switch (hwrm_err) {
4364 case HWRM_ERR_CODE_SUCCESS:
4365 return 0;
4366 case HWRM_ERR_CODE_RESOURCE_LOCKED:
4367 return -EROFS;
4368 case HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED:
4369 return -EACCES;
4370 case HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR:
4371 return -ENOSPC;
4372 case HWRM_ERR_CODE_INVALID_PARAMS:
4373 case HWRM_ERR_CODE_INVALID_FLAGS:
4374 case HWRM_ERR_CODE_INVALID_ENABLES:
4375 case HWRM_ERR_CODE_UNSUPPORTED_TLV:
4376 case HWRM_ERR_CODE_UNSUPPORTED_OPTION_ERR:
4377 return -EINVAL;
4378 case HWRM_ERR_CODE_NO_BUFFER:
4379 return -ENOMEM;
4380 case HWRM_ERR_CODE_HOT_RESET_PROGRESS:
4381 case HWRM_ERR_CODE_BUSY:
4382 return -EAGAIN;
4383 case HWRM_ERR_CODE_CMD_NOT_SUPPORTED:
4384 return -EOPNOTSUPP;
4385 default:
4386 return -EIO;
4387 }
4388 }
4389
4390 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
4391 int timeout, bool silent)
4392 {
4393 int i, intr_process, rc, tmo_count;
4394 struct input *req = msg;
4395 u32 *data = msg;
4396 u8 *valid;
4397 u16 cp_ring_id, len = 0;
4398 struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
4399 u16 max_req_len = BNXT_HWRM_MAX_REQ_LEN;
4400 struct hwrm_short_input short_input = {0};
4401 u32 doorbell_offset = BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER;
4402 u32 bar_offset = BNXT_GRCPF_REG_CHIMP_COMM;
4403 u16 dst = BNXT_HWRM_CHNL_CHIMP;
4404
4405 if (BNXT_NO_FW_ACCESS(bp) &&
4406 le16_to_cpu(req->req_type) != HWRM_FUNC_RESET)
4407 return -EBUSY;
4408
4409 if (msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4410 if (msg_len > bp->hwrm_max_ext_req_len ||
4411 !bp->hwrm_short_cmd_req_addr)
4412 return -EINVAL;
4413 }
4414
4415 if (bnxt_hwrm_kong_chnl(bp, req)) {
4416 dst = BNXT_HWRM_CHNL_KONG;
4417 bar_offset = BNXT_GRCPF_REG_KONG_COMM;
4418 doorbell_offset = BNXT_GRCPF_REG_KONG_COMM_TRIGGER;
4419 resp = bp->hwrm_cmd_kong_resp_addr;
4420 }
4421
4422 memset(resp, 0, PAGE_SIZE);
4423 cp_ring_id = le16_to_cpu(req->cmpl_ring);
4424 intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
4425
4426 req->seq_id = cpu_to_le16(bnxt_get_hwrm_seq_id(bp, dst));
4427 /* currently supports only one outstanding message */
4428 if (intr_process)
4429 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
4430
4431 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
4432 msg_len > BNXT_HWRM_MAX_REQ_LEN) {
4433 void *short_cmd_req = bp->hwrm_short_cmd_req_addr;
4434 u16 max_msg_len;
4435
4436 /* Set boundary for maximum extended request length for short
4437 * cmd format. If passed up from device use the max supported
4438 * internal req length.
4439 */
4440 max_msg_len = bp->hwrm_max_ext_req_len;
4441
4442 memcpy(short_cmd_req, req, msg_len);
4443 if (msg_len < max_msg_len)
4444 memset(short_cmd_req + msg_len, 0,
4445 max_msg_len - msg_len);
4446
4447 short_input.req_type = req->req_type;
4448 short_input.signature =
4449 cpu_to_le16(SHORT_REQ_SIGNATURE_SHORT_CMD);
4450 short_input.size = cpu_to_le16(msg_len);
4451 short_input.req_addr =
4452 cpu_to_le64(bp->hwrm_short_cmd_req_dma_addr);
4453
4454 data = (u32 *)&short_input;
4455 msg_len = sizeof(short_input);
4456
4457 /* Sync memory write before updating doorbell */
4458 wmb();
4459
4460 max_req_len = BNXT_HWRM_SHORT_REQ_LEN;
4461 }
4462
4463 /* Write request msg to hwrm channel */
4464 __iowrite32_copy(bp->bar0 + bar_offset, data, msg_len / 4);
4465
4466 for (i = msg_len; i < max_req_len; i += 4)
4467 writel(0, bp->bar0 + bar_offset + i);
4468
4469 /* Ring channel doorbell */
4470 writel(1, bp->bar0 + doorbell_offset);
4471
4472 if (!pci_is_enabled(bp->pdev))
4473 return -ENODEV;
4474
4475 if (!timeout)
4476 timeout = DFLT_HWRM_CMD_TIMEOUT;
4477 /* Limit timeout to an upper limit */
4478 timeout = min(timeout, HWRM_CMD_MAX_TIMEOUT);
4479 /* convert timeout to usec */
4480 timeout *= 1000;
4481
4482 i = 0;
4483 /* Short timeout for the first few iterations:
4484 * number of loops = number of loops for short timeout +
4485 * number of loops for standard timeout.
4486 */
4487 tmo_count = HWRM_SHORT_TIMEOUT_COUNTER;
4488 timeout = timeout - HWRM_SHORT_MIN_TIMEOUT * HWRM_SHORT_TIMEOUT_COUNTER;
4489 tmo_count += DIV_ROUND_UP(timeout, HWRM_MIN_TIMEOUT);
4490
4491 if (intr_process) {
4492 u16 seq_id = bp->hwrm_intr_seq_id;
4493
4494 /* Wait until hwrm response cmpl interrupt is processed */
4495 while (bp->hwrm_intr_seq_id != (u16)~seq_id &&
4496 i++ < tmo_count) {
4497 /* Abort the wait for completion if the FW health
4498 * check has failed.
4499 */
4500 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
4501 return -EBUSY;
4502 /* on first few passes, just barely sleep */
4503 if (i < HWRM_SHORT_TIMEOUT_COUNTER) {
4504 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4505 HWRM_SHORT_MAX_TIMEOUT);
4506 } else {
4507 if (HWRM_WAIT_MUST_ABORT(bp, req))
4508 break;
4509 usleep_range(HWRM_MIN_TIMEOUT,
4510 HWRM_MAX_TIMEOUT);
4511 }
4512 }
4513
4514 if (bp->hwrm_intr_seq_id != (u16)~seq_id) {
4515 if (!silent)
4516 netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
4517 le16_to_cpu(req->req_type));
4518 return -EBUSY;
4519 }
4520 len = le16_to_cpu(resp->resp_len);
4521 valid = ((u8 *)resp) + len - 1;
4522 } else {
4523 int j;
4524
4525 /* Check if response len is updated */
4526 for (i = 0; i < tmo_count; i++) {
4527 /* Abort the wait for completion if the FW health
4528 * check has failed.
4529 */
4530 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
4531 return -EBUSY;
4532 len = le16_to_cpu(resp->resp_len);
4533 if (len)
4534 break;
4535 /* on first few passes, just barely sleep */
4536 if (i < HWRM_SHORT_TIMEOUT_COUNTER) {
4537 usleep_range(HWRM_SHORT_MIN_TIMEOUT,
4538 HWRM_SHORT_MAX_TIMEOUT);
4539 } else {
4540 if (HWRM_WAIT_MUST_ABORT(bp, req))
4541 goto timeout_abort;
4542 usleep_range(HWRM_MIN_TIMEOUT,
4543 HWRM_MAX_TIMEOUT);
4544 }
4545 }
4546
4547 if (i >= tmo_count) {
4548 timeout_abort:
4549 if (!silent)
4550 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
4551 HWRM_TOTAL_TIMEOUT(i),
4552 le16_to_cpu(req->req_type),
4553 le16_to_cpu(req->seq_id), len);
4554 return -EBUSY;
4555 }
4556
4557 /* Last byte of resp contains valid bit */
4558 valid = ((u8 *)resp) + len - 1;
4559 for (j = 0; j < HWRM_VALID_BIT_DELAY_USEC; j++) {
4560 /* make sure we read from updated DMA memory */
4561 dma_rmb();
4562 if (*valid)
4563 break;
4564 usleep_range(1, 5);
4565 }
4566
4567 if (j >= HWRM_VALID_BIT_DELAY_USEC) {
4568 if (!silent)
4569 netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
4570 HWRM_TOTAL_TIMEOUT(i),
4571 le16_to_cpu(req->req_type),
4572 le16_to_cpu(req->seq_id), len,
4573 *valid);
4574 return -EBUSY;
4575 }
4576 }
4577
4578 /* Zero valid bit for compatibility. Valid bit in an older spec
4579 * may become a new field in a newer spec. We must make sure that
4580 * a new field not implemented by old spec will read zero.
4581 */
4582 *valid = 0;
4583 rc = le16_to_cpu(resp->error_code);
4584 if (rc && !silent)
4585 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
4586 le16_to_cpu(resp->req_type),
4587 le16_to_cpu(resp->seq_id), rc);
4588 return bnxt_hwrm_to_stderr(rc);
4589 }
4590
4591 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4592 {
4593 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
4594 }
4595
4596 int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4597 int timeout)
4598 {
4599 return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4600 }
4601
4602 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
4603 {
4604 int rc;
4605
4606 mutex_lock(&bp->hwrm_cmd_lock);
4607 rc = _hwrm_send_message(bp, msg, msg_len, timeout);
4608 mutex_unlock(&bp->hwrm_cmd_lock);
4609 return rc;
4610 }
4611
4612 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
4613 int timeout)
4614 {
4615 int rc;
4616
4617 mutex_lock(&bp->hwrm_cmd_lock);
4618 rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
4619 mutex_unlock(&bp->hwrm_cmd_lock);
4620 return rc;
4621 }
4622
4623 int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp, unsigned long *bmap, int bmap_size,
4624 bool async_only)
4625 {
4626 struct hwrm_func_drv_rgtr_output *resp = bp->hwrm_cmd_resp_addr;
4627 struct hwrm_func_drv_rgtr_input req = {0};
4628 DECLARE_BITMAP(async_events_bmap, 256);
4629 u32 *events = (u32 *)async_events_bmap;
4630 u32 flags;
4631 int rc, i;
4632
4633 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
4634
4635 req.enables =
4636 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
4637 FUNC_DRV_RGTR_REQ_ENABLES_VER |
4638 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4639
4640 req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
4641 flags = FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE;
4642 if (bp->fw_cap & BNXT_FW_CAP_HOT_RESET)
4643 flags |= FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT;
4644 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
4645 flags |= FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT |
4646 FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT;
4647 req.flags = cpu_to_le32(flags);
4648 req.ver_maj_8b = DRV_VER_MAJ;
4649 req.ver_min_8b = DRV_VER_MIN;
4650 req.ver_upd_8b = DRV_VER_UPD;
4651 req.ver_maj = cpu_to_le16(DRV_VER_MAJ);
4652 req.ver_min = cpu_to_le16(DRV_VER_MIN);
4653 req.ver_upd = cpu_to_le16(DRV_VER_UPD);
4654
4655 if (BNXT_PF(bp)) {
4656 u32 data[8];
4657 int i;
4658
4659 memset(data, 0, sizeof(data));
4660 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) {
4661 u16 cmd = bnxt_vf_req_snif[i];
4662 unsigned int bit, idx;
4663
4664 idx = cmd / 32;
4665 bit = cmd % 32;
4666 data[idx] |= 1 << bit;
4667 }
4668
4669 for (i = 0; i < 8; i++)
4670 req.vf_req_fwd[i] = cpu_to_le32(data[i]);
4671
4672 req.enables |=
4673 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
4674 }
4675
4676 if (bp->fw_cap & BNXT_FW_CAP_OVS_64BIT_HANDLE)
4677 req.flags |= cpu_to_le32(
4678 FUNC_DRV_RGTR_REQ_FLAGS_FLOW_HANDLE_64BIT_MODE);
4679
4680 memset(async_events_bmap, 0, sizeof(async_events_bmap));
4681 for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++) {
4682 u16 event_id = bnxt_async_events_arr[i];
4683
4684 if (event_id == ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY &&
4685 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
4686 continue;
4687 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
4688 }
4689 if (bmap && bmap_size) {
4690 for (i = 0; i < bmap_size; i++) {
4691 if (test_bit(i, bmap))
4692 __set_bit(i, async_events_bmap);
4693 }
4694 }
4695 for (i = 0; i < 8; i++)
4696 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
4697
4698 if (async_only)
4699 req.enables =
4700 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
4701
4702 mutex_lock(&bp->hwrm_cmd_lock);
4703 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4704 if (!rc) {
4705 set_bit(BNXT_STATE_DRV_REGISTERED, &bp->state);
4706 if (resp->flags &
4707 cpu_to_le32(FUNC_DRV_RGTR_RESP_FLAGS_IF_CHANGE_SUPPORTED))
4708 bp->fw_cap |= BNXT_FW_CAP_IF_CHANGE;
4709 }
4710 mutex_unlock(&bp->hwrm_cmd_lock);
4711 return rc;
4712 }
4713
4714 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
4715 {
4716 struct hwrm_func_drv_unrgtr_input req = {0};
4717
4718 if (!test_and_clear_bit(BNXT_STATE_DRV_REGISTERED, &bp->state))
4719 return 0;
4720
4721 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
4722 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4723 }
4724
4725 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
4726 {
4727 u32 rc = 0;
4728 struct hwrm_tunnel_dst_port_free_input req = {0};
4729
4730 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
4731 req.tunnel_type = tunnel_type;
4732
4733 switch (tunnel_type) {
4734 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
4735 req.tunnel_dst_port_id = cpu_to_le16(bp->vxlan_fw_dst_port_id);
4736 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
4737 break;
4738 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
4739 req.tunnel_dst_port_id = cpu_to_le16(bp->nge_fw_dst_port_id);
4740 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
4741 break;
4742 default:
4743 break;
4744 }
4745
4746 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4747 if (rc)
4748 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
4749 rc);
4750 return rc;
4751 }
4752
4753 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
4754 u8 tunnel_type)
4755 {
4756 u32 rc = 0;
4757 struct hwrm_tunnel_dst_port_alloc_input req = {0};
4758 struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4759
4760 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
4761
4762 req.tunnel_type = tunnel_type;
4763 req.tunnel_dst_port_val = port;
4764
4765 mutex_lock(&bp->hwrm_cmd_lock);
4766 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4767 if (rc) {
4768 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
4769 rc);
4770 goto err_out;
4771 }
4772
4773 switch (tunnel_type) {
4774 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN:
4775 bp->vxlan_fw_dst_port_id =
4776 le16_to_cpu(resp->tunnel_dst_port_id);
4777 break;
4778 case TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE:
4779 bp->nge_fw_dst_port_id = le16_to_cpu(resp->tunnel_dst_port_id);
4780 break;
4781 default:
4782 break;
4783 }
4784
4785 err_out:
4786 mutex_unlock(&bp->hwrm_cmd_lock);
4787 return rc;
4788 }
4789
4790 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
4791 {
4792 struct hwrm_cfa_l2_set_rx_mask_input req = {0};
4793 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4794
4795 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
4796 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
4797
4798 req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
4799 req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
4800 req.mask = cpu_to_le32(vnic->rx_mask);
4801 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4802 }
4803
4804 #ifdef CONFIG_RFS_ACCEL
4805 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
4806 struct bnxt_ntuple_filter *fltr)
4807 {
4808 struct hwrm_cfa_ntuple_filter_free_input req = {0};
4809
4810 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
4811 req.ntuple_filter_id = fltr->filter_id;
4812 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4813 }
4814
4815 #define BNXT_NTP_FLTR_FLAGS \
4816 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
4817 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
4818 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
4819 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
4820 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
4821 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
4822 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
4823 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
4824 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
4825 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
4826 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
4827 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
4828 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
4829 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
4830
4831 #define BNXT_NTP_TUNNEL_FLTR_FLAG \
4832 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE
4833
4834 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
4835 struct bnxt_ntuple_filter *fltr)
4836 {
4837 struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
4838 struct hwrm_cfa_ntuple_filter_alloc_output *resp;
4839 struct flow_keys *keys = &fltr->fkeys;
4840 struct bnxt_vnic_info *vnic;
4841 u32 flags = 0;
4842 int rc = 0;
4843
4844 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
4845 req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[fltr->l2_fltr_idx];
4846
4847 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2) {
4848 flags = CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DEST_RFS_RING_IDX;
4849 req.dst_id = cpu_to_le16(fltr->rxq);
4850 } else {
4851 vnic = &bp->vnic_info[fltr->rxq + 1];
4852 req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
4853 }
4854 req.flags = cpu_to_le32(flags);
4855 req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
4856
4857 req.ethertype = htons(ETH_P_IP);
4858 memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
4859 req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
4860 req.ip_protocol = keys->basic.ip_proto;
4861
4862 if (keys->basic.n_proto == htons(ETH_P_IPV6)) {
4863 int i;
4864
4865 req.ethertype = htons(ETH_P_IPV6);
4866 req.ip_addr_type =
4867 CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6;
4868 *(struct in6_addr *)&req.src_ipaddr[0] =
4869 keys->addrs.v6addrs.src;
4870 *(struct in6_addr *)&req.dst_ipaddr[0] =
4871 keys->addrs.v6addrs.dst;
4872 for (i = 0; i < 4; i++) {
4873 req.src_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4874 req.dst_ipaddr_mask[i] = cpu_to_be32(0xffffffff);
4875 }
4876 } else {
4877 req.src_ipaddr[0] = keys->addrs.v4addrs.src;
4878 req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4879 req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
4880 req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
4881 }
4882 if (keys->control.flags & FLOW_DIS_ENCAPSULATION) {
4883 req.enables |= cpu_to_le32(BNXT_NTP_TUNNEL_FLTR_FLAG);
4884 req.tunnel_type =
4885 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL;
4886 }
4887
4888 req.src_port = keys->ports.src;
4889 req.src_port_mask = cpu_to_be16(0xffff);
4890 req.dst_port = keys->ports.dst;
4891 req.dst_port_mask = cpu_to_be16(0xffff);
4892
4893 mutex_lock(&bp->hwrm_cmd_lock);
4894 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4895 if (!rc) {
4896 resp = bnxt_get_hwrm_resp_addr(bp, &req);
4897 fltr->filter_id = resp->ntuple_filter_id;
4898 }
4899 mutex_unlock(&bp->hwrm_cmd_lock);
4900 return rc;
4901 }
4902 #endif
4903
4904 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
4905 u8 *mac_addr)
4906 {
4907 u32 rc = 0;
4908 struct hwrm_cfa_l2_filter_alloc_input req = {0};
4909 struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
4910
4911 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
4912 req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX);
4913 if (!BNXT_CHIP_TYPE_NITRO_A0(bp))
4914 req.flags |=
4915 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
4916 req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
4917 req.enables =
4918 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
4919 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
4920 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
4921 memcpy(req.l2_addr, mac_addr, ETH_ALEN);
4922 req.l2_addr_mask[0] = 0xff;
4923 req.l2_addr_mask[1] = 0xff;
4924 req.l2_addr_mask[2] = 0xff;
4925 req.l2_addr_mask[3] = 0xff;
4926 req.l2_addr_mask[4] = 0xff;
4927 req.l2_addr_mask[5] = 0xff;
4928
4929 mutex_lock(&bp->hwrm_cmd_lock);
4930 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4931 if (!rc)
4932 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
4933 resp->l2_filter_id;
4934 mutex_unlock(&bp->hwrm_cmd_lock);
4935 return rc;
4936 }
4937
4938 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
4939 {
4940 u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
4941 int rc = 0;
4942
4943 /* Any associated ntuple filters will also be cleared by firmware. */
4944 mutex_lock(&bp->hwrm_cmd_lock);
4945 for (i = 0; i < num_of_vnics; i++) {
4946 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
4947
4948 for (j = 0; j < vnic->uc_filter_count; j++) {
4949 struct hwrm_cfa_l2_filter_free_input req = {0};
4950
4951 bnxt_hwrm_cmd_hdr_init(bp, &req,
4952 HWRM_CFA_L2_FILTER_FREE, -1, -1);
4953
4954 req.l2_filter_id = vnic->fw_l2_filter_id[j];
4955
4956 rc = _hwrm_send_message(bp, &req, sizeof(req),
4957 HWRM_CMD_TIMEOUT);
4958 }
4959 vnic->uc_filter_count = 0;
4960 }
4961 mutex_unlock(&bp->hwrm_cmd_lock);
4962
4963 return rc;
4964 }
4965
4966 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
4967 {
4968 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
4969 u16 max_aggs = VNIC_TPA_CFG_REQ_MAX_AGGS_MAX;
4970 struct hwrm_vnic_tpa_cfg_input req = {0};
4971
4972 if (vnic->fw_vnic_id == INVALID_HW_RING_ID)
4973 return 0;
4974
4975 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
4976
4977 if (tpa_flags) {
4978 u16 mss = bp->dev->mtu - 40;
4979 u32 nsegs, n, segs = 0, flags;
4980
4981 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
4982 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
4983 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
4984 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
4985 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
4986 if (tpa_flags & BNXT_FLAG_GRO)
4987 flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
4988
4989 req.flags = cpu_to_le32(flags);
4990
4991 req.enables =
4992 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
4993 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
4994 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
4995
4996 /* Number of segs are log2 units, and first packet is not
4997 * included as part of this units.
4998 */
4999 if (mss <= BNXT_RX_PAGE_SIZE) {
5000 n = BNXT_RX_PAGE_SIZE / mss;
5001 nsegs = (MAX_SKB_FRAGS - 1) * n;
5002 } else {
5003 n = mss / BNXT_RX_PAGE_SIZE;
5004 if (mss & (BNXT_RX_PAGE_SIZE - 1))
5005 n++;
5006 nsegs = (MAX_SKB_FRAGS - n) / n;
5007 }
5008
5009 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5010 segs = MAX_TPA_SEGS_P5;
5011 max_aggs = bp->max_tpa;
5012 } else {
5013 segs = ilog2(nsegs);
5014 }
5015 req.max_agg_segs = cpu_to_le16(segs);
5016 req.max_aggs = cpu_to_le16(max_aggs);
5017
5018 req.min_agg_len = cpu_to_le32(512);
5019 }
5020 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5021
5022 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5023 }
5024
5025 static u16 bnxt_cp_ring_from_grp(struct bnxt *bp, struct bnxt_ring_struct *ring)
5026 {
5027 struct bnxt_ring_grp_info *grp_info;
5028
5029 grp_info = &bp->grp_info[ring->grp_idx];
5030 return grp_info->cp_fw_ring_id;
5031 }
5032
5033 static u16 bnxt_cp_ring_for_rx(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
5034 {
5035 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5036 struct bnxt_napi *bnapi = rxr->bnapi;
5037 struct bnxt_cp_ring_info *cpr;
5038
5039 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_RX_HDL];
5040 return cpr->cp_ring_struct.fw_ring_id;
5041 } else {
5042 return bnxt_cp_ring_from_grp(bp, &rxr->rx_ring_struct);
5043 }
5044 }
5045
5046 static u16 bnxt_cp_ring_for_tx(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
5047 {
5048 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5049 struct bnxt_napi *bnapi = txr->bnapi;
5050 struct bnxt_cp_ring_info *cpr;
5051
5052 cpr = bnapi->cp_ring.cp_ring_arr[BNXT_TX_HDL];
5053 return cpr->cp_ring_struct.fw_ring_id;
5054 } else {
5055 return bnxt_cp_ring_from_grp(bp, &txr->tx_ring_struct);
5056 }
5057 }
5058
5059 static int bnxt_alloc_rss_indir_tbl(struct bnxt *bp)
5060 {
5061 int entries;
5062
5063 if (bp->flags & BNXT_FLAG_CHIP_P5)
5064 entries = BNXT_MAX_RSS_TABLE_ENTRIES_P5;
5065 else
5066 entries = HW_HASH_INDEX_SIZE;
5067
5068 bp->rss_indir_tbl_entries = entries;
5069 bp->rss_indir_tbl = kmalloc_array(entries, sizeof(*bp->rss_indir_tbl),
5070 GFP_KERNEL);
5071 if (!bp->rss_indir_tbl)
5072 return -ENOMEM;
5073 return 0;
5074 }
5075
5076 static void bnxt_set_dflt_rss_indir_tbl(struct bnxt *bp)
5077 {
5078 u16 max_rings, max_entries, pad, i;
5079
5080 if (!bp->rx_nr_rings)
5081 return;
5082
5083 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5084 max_rings = bp->rx_nr_rings - 1;
5085 else
5086 max_rings = bp->rx_nr_rings;
5087
5088 max_entries = bnxt_get_rxfh_indir_size(bp->dev);
5089
5090 for (i = 0; i < max_entries; i++)
5091 bp->rss_indir_tbl[i] = ethtool_rxfh_indir_default(i, max_rings);
5092
5093 pad = bp->rss_indir_tbl_entries - max_entries;
5094 if (pad)
5095 memset(&bp->rss_indir_tbl[i], 0, pad * sizeof(u16));
5096 }
5097
5098 static u16 bnxt_get_max_rss_ring(struct bnxt *bp)
5099 {
5100 u16 i, tbl_size, max_ring = 0;
5101
5102 if (!bp->rss_indir_tbl)
5103 return 0;
5104
5105 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5106 for (i = 0; i < tbl_size; i++)
5107 max_ring = max(max_ring, bp->rss_indir_tbl[i]);
5108 return max_ring;
5109 }
5110
5111 int bnxt_get_nr_rss_ctxs(struct bnxt *bp, int rx_rings)
5112 {
5113 if (bp->flags & BNXT_FLAG_CHIP_P5)
5114 return DIV_ROUND_UP(rx_rings, BNXT_RSS_TABLE_ENTRIES_P5);
5115 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
5116 return 2;
5117 return 1;
5118 }
5119
5120 static void __bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5121 {
5122 bool no_rss = !(vnic->flags & BNXT_VNIC_RSS_FLAG);
5123 u16 i, j;
5124
5125 /* Fill the RSS indirection table with ring group ids */
5126 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++) {
5127 if (!no_rss)
5128 j = bp->rss_indir_tbl[i];
5129 vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
5130 }
5131 }
5132
5133 static void __bnxt_fill_hw_rss_tbl_p5(struct bnxt *bp,
5134 struct bnxt_vnic_info *vnic)
5135 {
5136 __le16 *ring_tbl = vnic->rss_table;
5137 struct bnxt_rx_ring_info *rxr;
5138 u16 tbl_size, i;
5139
5140 tbl_size = bnxt_get_rxfh_indir_size(bp->dev);
5141
5142 for (i = 0; i < tbl_size; i++) {
5143 u16 ring_id, j;
5144
5145 j = bp->rss_indir_tbl[i];
5146 rxr = &bp->rx_ring[j];
5147
5148 ring_id = rxr->rx_ring_struct.fw_ring_id;
5149 *ring_tbl++ = cpu_to_le16(ring_id);
5150 ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5151 *ring_tbl++ = cpu_to_le16(ring_id);
5152 }
5153 }
5154
5155 static void bnxt_fill_hw_rss_tbl(struct bnxt *bp, struct bnxt_vnic_info *vnic)
5156 {
5157 if (bp->flags & BNXT_FLAG_CHIP_P5)
5158 __bnxt_fill_hw_rss_tbl_p5(bp, vnic);
5159 else
5160 __bnxt_fill_hw_rss_tbl(bp, vnic);
5161 }
5162
5163 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
5164 {
5165 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5166 struct hwrm_vnic_rss_cfg_input req = {0};
5167
5168 if ((bp->flags & BNXT_FLAG_CHIP_P5) ||
5169 vnic->fw_rss_cos_lb_ctx[0] == INVALID_HW_RING_ID)
5170 return 0;
5171
5172 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
5173 if (set_rss) {
5174 bnxt_fill_hw_rss_tbl(bp, vnic);
5175 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
5176 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5177 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
5178 req.hash_key_tbl_addr =
5179 cpu_to_le64(vnic->rss_hash_key_dma_addr);
5180 }
5181 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5182 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5183 }
5184
5185 static int bnxt_hwrm_vnic_set_rss_p5(struct bnxt *bp, u16 vnic_id, bool set_rss)
5186 {
5187 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5188 struct hwrm_vnic_rss_cfg_input req = {0};
5189 dma_addr_t ring_tbl_map;
5190 u32 i, nr_ctxs;
5191
5192 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
5193 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5194 if (!set_rss) {
5195 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5196 return 0;
5197 }
5198 bnxt_fill_hw_rss_tbl(bp, vnic);
5199 req.hash_type = cpu_to_le32(bp->rss_hash_cfg);
5200 req.hash_mode_flags = VNIC_RSS_CFG_REQ_HASH_MODE_FLAGS_DEFAULT;
5201 req.hash_key_tbl_addr = cpu_to_le64(vnic->rss_hash_key_dma_addr);
5202 ring_tbl_map = vnic->rss_table_dma_addr;
5203 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
5204 for (i = 0; i < nr_ctxs; ring_tbl_map += BNXT_RSS_TABLE_SIZE_P5, i++) {
5205 int rc;
5206
5207 req.ring_grp_tbl_addr = cpu_to_le64(ring_tbl_map);
5208 req.ring_table_pair_index = i;
5209 req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[i]);
5210 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5211 if (rc)
5212 return rc;
5213 }
5214 return 0;
5215 }
5216
5217 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
5218 {
5219 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5220 struct hwrm_vnic_plcmodes_cfg_input req = {0};
5221
5222 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
5223 req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
5224 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
5225 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
5226 req.enables =
5227 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
5228 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
5229 /* thresholds not implemented in firmware yet */
5230 req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
5231 req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
5232 req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
5233 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5234 }
5235
5236 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id,
5237 u16 ctx_idx)
5238 {
5239 struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
5240
5241 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
5242 req.rss_cos_lb_ctx_id =
5243 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx]);
5244
5245 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5246 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] = INVALID_HW_RING_ID;
5247 }
5248
5249 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
5250 {
5251 int i, j;
5252
5253 for (i = 0; i < bp->nr_vnics; i++) {
5254 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
5255
5256 for (j = 0; j < BNXT_MAX_CTX_PER_VNIC; j++) {
5257 if (vnic->fw_rss_cos_lb_ctx[j] != INVALID_HW_RING_ID)
5258 bnxt_hwrm_vnic_ctx_free_one(bp, i, j);
5259 }
5260 }
5261 bp->rsscos_nr_ctxs = 0;
5262 }
5263
5264 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id, u16 ctx_idx)
5265 {
5266 int rc;
5267 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
5268 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
5269 bp->hwrm_cmd_resp_addr;
5270
5271 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
5272 -1);
5273
5274 mutex_lock(&bp->hwrm_cmd_lock);
5275 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5276 if (!rc)
5277 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx[ctx_idx] =
5278 le16_to_cpu(resp->rss_cos_lb_ctx_id);
5279 mutex_unlock(&bp->hwrm_cmd_lock);
5280
5281 return rc;
5282 }
5283
5284 static u32 bnxt_get_roce_vnic_mode(struct bnxt *bp)
5285 {
5286 if (bp->flags & BNXT_FLAG_ROCE_MIRROR_CAP)
5287 return VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE;
5288 return VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE;
5289 }
5290
5291 int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
5292 {
5293 unsigned int ring = 0, grp_idx;
5294 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5295 struct hwrm_vnic_cfg_input req = {0};
5296 u16 def_vlan = 0;
5297
5298 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
5299
5300 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5301 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[0];
5302
5303 req.default_rx_ring_id =
5304 cpu_to_le16(rxr->rx_ring_struct.fw_ring_id);
5305 req.default_cmpl_ring_id =
5306 cpu_to_le16(bnxt_cp_ring_for_rx(bp, rxr));
5307 req.enables =
5308 cpu_to_le32(VNIC_CFG_REQ_ENABLES_DEFAULT_RX_RING_ID |
5309 VNIC_CFG_REQ_ENABLES_DEFAULT_CMPL_RING_ID);
5310 goto vnic_mru;
5311 }
5312 req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP);
5313 /* Only RSS support for now TBD: COS & LB */
5314 if (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID) {
5315 req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[0]);
5316 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5317 VNIC_CFG_REQ_ENABLES_MRU);
5318 } else if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG) {
5319 req.rss_rule =
5320 cpu_to_le16(bp->vnic_info[0].fw_rss_cos_lb_ctx[0]);
5321 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_RSS_RULE |
5322 VNIC_CFG_REQ_ENABLES_MRU);
5323 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE);
5324 } else {
5325 req.rss_rule = cpu_to_le16(0xffff);
5326 }
5327
5328 if (BNXT_CHIP_TYPE_NITRO_A0(bp) &&
5329 (vnic->fw_rss_cos_lb_ctx[0] != INVALID_HW_RING_ID)) {
5330 req.cos_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx[1]);
5331 req.enables |= cpu_to_le32(VNIC_CFG_REQ_ENABLES_COS_RULE);
5332 } else {
5333 req.cos_rule = cpu_to_le16(0xffff);
5334 }
5335
5336 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
5337 ring = 0;
5338 else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
5339 ring = vnic_id - 1;
5340 else if ((vnic_id == 1) && BNXT_CHIP_TYPE_NITRO_A0(bp))
5341 ring = bp->rx_nr_rings - 1;
5342
5343 grp_idx = bp->rx_ring[ring].bnapi->index;
5344 req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
5345 req.lb_rule = cpu_to_le16(0xffff);
5346 vnic_mru:
5347 req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + VLAN_HLEN);
5348
5349 req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
5350 #ifdef CONFIG_BNXT_SRIOV
5351 if (BNXT_VF(bp))
5352 def_vlan = bp->vf.vlan;
5353 #endif
5354 if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
5355 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
5356 if (!vnic_id && bnxt_ulp_registered(bp->edev, BNXT_ROCE_ULP))
5357 req.flags |= cpu_to_le32(bnxt_get_roce_vnic_mode(bp));
5358
5359 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5360 }
5361
5362 static void bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
5363 {
5364 if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
5365 struct hwrm_vnic_free_input req = {0};
5366
5367 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
5368 req.vnic_id =
5369 cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
5370
5371 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5372 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
5373 }
5374 }
5375
5376 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
5377 {
5378 u16 i;
5379
5380 for (i = 0; i < bp->nr_vnics; i++)
5381 bnxt_hwrm_vnic_free_one(bp, i);
5382 }
5383
5384 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
5385 unsigned int start_rx_ring_idx,
5386 unsigned int nr_rings)
5387 {
5388 int rc = 0;
5389 unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
5390 struct hwrm_vnic_alloc_input req = {0};
5391 struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5392 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
5393
5394 if (bp->flags & BNXT_FLAG_CHIP_P5)
5395 goto vnic_no_ring_grps;
5396
5397 /* map ring groups to this vnic */
5398 for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
5399 grp_idx = bp->rx_ring[i].bnapi->index;
5400 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
5401 netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
5402 j, nr_rings);
5403 break;
5404 }
5405 vnic->fw_grp_ids[j] = bp->grp_info[grp_idx].fw_grp_id;
5406 }
5407
5408 vnic_no_ring_grps:
5409 for (i = 0; i < BNXT_MAX_CTX_PER_VNIC; i++)
5410 vnic->fw_rss_cos_lb_ctx[i] = INVALID_HW_RING_ID;
5411 if (vnic_id == 0)
5412 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
5413
5414 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
5415
5416 mutex_lock(&bp->hwrm_cmd_lock);
5417 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5418 if (!rc)
5419 vnic->fw_vnic_id = le32_to_cpu(resp->vnic_id);
5420 mutex_unlock(&bp->hwrm_cmd_lock);
5421 return rc;
5422 }
5423
5424 static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp)
5425 {
5426 struct hwrm_vnic_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
5427 struct hwrm_vnic_qcaps_input req = {0};
5428 int rc;
5429
5430 bp->hw_ring_stats_size = sizeof(struct ctx_hw_stats);
5431 bp->flags &= ~(BNXT_FLAG_NEW_RSS_CAP | BNXT_FLAG_ROCE_MIRROR_CAP);
5432 if (bp->hwrm_spec_code < 0x10600)
5433 return 0;
5434
5435 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_QCAPS, -1, -1);
5436 mutex_lock(&bp->hwrm_cmd_lock);
5437 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5438 if (!rc) {
5439 u32 flags = le32_to_cpu(resp->flags);
5440
5441 if (!(bp->flags & BNXT_FLAG_CHIP_P5) &&
5442 (flags & VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP))
5443 bp->flags |= BNXT_FLAG_NEW_RSS_CAP;
5444 if (flags &
5445 VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP)
5446 bp->flags |= BNXT_FLAG_ROCE_MIRROR_CAP;
5447
5448 /* Older P5 fw before EXT_HW_STATS support did not set
5449 * VLAN_STRIP_CAP properly.
5450 */
5451 if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) ||
5452 (BNXT_CHIP_P5_THOR(bp) &&
5453 !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))
5454 bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;
5455 bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);
5456 if (bp->max_tpa_v2) {
5457 if (BNXT_CHIP_P5_THOR(bp))
5458 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;
5459 else
5460 bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;
5461 }
5462 }
5463 mutex_unlock(&bp->hwrm_cmd_lock);
5464 return rc;
5465 }
5466
5467 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
5468 {
5469 u16 i;
5470 u32 rc = 0;
5471
5472 if (bp->flags & BNXT_FLAG_CHIP_P5)
5473 return 0;
5474
5475 mutex_lock(&bp->hwrm_cmd_lock);
5476 for (i = 0; i < bp->rx_nr_rings; i++) {
5477 struct hwrm_ring_grp_alloc_input req = {0};
5478 struct hwrm_ring_grp_alloc_output *resp =
5479 bp->hwrm_cmd_resp_addr;
5480 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
5481
5482 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
5483
5484 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
5485 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
5486 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
5487 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
5488
5489 rc = _hwrm_send_message(bp, &req, sizeof(req),
5490 HWRM_CMD_TIMEOUT);
5491 if (rc)
5492 break;
5493
5494 bp->grp_info[grp_idx].fw_grp_id =
5495 le32_to_cpu(resp->ring_group_id);
5496 }
5497 mutex_unlock(&bp->hwrm_cmd_lock);
5498 return rc;
5499 }
5500
5501 static void bnxt_hwrm_ring_grp_free(struct bnxt *bp)
5502 {
5503 u16 i;
5504 struct hwrm_ring_grp_free_input req = {0};
5505
5506 if (!bp->grp_info || (bp->flags & BNXT_FLAG_CHIP_P5))
5507 return;
5508
5509 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
5510
5511 mutex_lock(&bp->hwrm_cmd_lock);
5512 for (i = 0; i < bp->cp_nr_rings; i++) {
5513 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
5514 continue;
5515 req.ring_group_id =
5516 cpu_to_le32(bp->grp_info[i].fw_grp_id);
5517
5518 _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5519 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
5520 }
5521 mutex_unlock(&bp->hwrm_cmd_lock);
5522 }
5523
5524 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
5525 struct bnxt_ring_struct *ring,
5526 u32 ring_type, u32 map_index)
5527 {
5528 int rc = 0, err = 0;
5529 struct hwrm_ring_alloc_input req = {0};
5530 struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
5531 struct bnxt_ring_mem_info *rmem = &ring->ring_mem;
5532 struct bnxt_ring_grp_info *grp_info;
5533 u16 ring_id;
5534
5535 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
5536
5537 req.enables = 0;
5538 if (rmem->nr_pages > 1) {
5539 req.page_tbl_addr = cpu_to_le64(rmem->pg_tbl_map);
5540 /* Page size is in log2 units */
5541 req.page_size = BNXT_PAGE_SHIFT;
5542 req.page_tbl_depth = 1;
5543 } else {
5544 req.page_tbl_addr = cpu_to_le64(rmem->dma_arr[0]);
5545 }
5546 req.fbo = 0;
5547 /* Association of ring index with doorbell index and MSIX number */
5548 req.logical_id = cpu_to_le16(map_index);
5549
5550 switch (ring_type) {
5551 case HWRM_RING_ALLOC_TX: {
5552 struct bnxt_tx_ring_info *txr;
5553
5554 txr = container_of(ring, struct bnxt_tx_ring_info,
5555 tx_ring_struct);
5556 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
5557 /* Association of transmit ring with completion ring */
5558 grp_info = &bp->grp_info[ring->grp_idx];
5559 req.cmpl_ring_id = cpu_to_le16(bnxt_cp_ring_for_tx(bp, txr));
5560 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
5561 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5562 req.queue_id = cpu_to_le16(ring->queue_id);
5563 break;
5564 }
5565 case HWRM_RING_ALLOC_RX:
5566 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5567 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
5568 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5569 u16 flags = 0;
5570
5571 /* Association of rx ring with stats context */
5572 grp_info = &bp->grp_info[ring->grp_idx];
5573 req.rx_buf_size = cpu_to_le16(bp->rx_buf_use_size);
5574 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5575 req.enables |= cpu_to_le32(
5576 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5577 if (NET_IP_ALIGN == 2)
5578 flags = RING_ALLOC_REQ_FLAGS_RX_SOP_PAD;
5579 req.flags = cpu_to_le16(flags);
5580 }
5581 break;
5582 case HWRM_RING_ALLOC_AGG:
5583 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5584 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
5585 /* Association of agg ring with rx ring */
5586 grp_info = &bp->grp_info[ring->grp_idx];
5587 req.rx_ring_id = cpu_to_le16(grp_info->rx_fw_ring_id);
5588 req.rx_buf_size = cpu_to_le16(BNXT_RX_PAGE_SIZE);
5589 req.stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);
5590 req.enables |= cpu_to_le32(
5591 RING_ALLOC_REQ_ENABLES_RX_RING_ID_VALID |
5592 RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID);
5593 } else {
5594 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
5595 }
5596 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
5597 break;
5598 case HWRM_RING_ALLOC_CMPL:
5599 req.ring_type = RING_ALLOC_REQ_RING_TYPE_L2_CMPL;
5600 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5601 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5602 /* Association of cp ring with nq */
5603 grp_info = &bp->grp_info[map_index];
5604 req.nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);
5605 req.cq_handle = cpu_to_le64(ring->handle);
5606 req.enables |= cpu_to_le32(
5607 RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID);
5608 } else if (bp->flags & BNXT_FLAG_USING_MSIX) {
5609 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5610 }
5611 break;
5612 case HWRM_RING_ALLOC_NQ:
5613 req.ring_type = RING_ALLOC_REQ_RING_TYPE_NQ;
5614 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
5615 if (bp->flags & BNXT_FLAG_USING_MSIX)
5616 req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
5617 break;
5618 default:
5619 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
5620 ring_type);
5621 return -1;
5622 }
5623
5624 mutex_lock(&bp->hwrm_cmd_lock);
5625 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5626 err = le16_to_cpu(resp->error_code);
5627 ring_id = le16_to_cpu(resp->ring_id);
5628 mutex_unlock(&bp->hwrm_cmd_lock);
5629
5630 if (rc || err) {
5631 netdev_err(bp->dev, "hwrm_ring_alloc type %d failed. rc:%x err:%x\n",
5632 ring_type, rc, err);
5633 return -EIO;
5634 }
5635 ring->fw_ring_id = ring_id;
5636 return rc;
5637 }
5638
5639 static int bnxt_hwrm_set_async_event_cr(struct bnxt *bp, int idx)
5640 {
5641 int rc;
5642
5643 if (BNXT_PF(bp)) {
5644 struct hwrm_func_cfg_input req = {0};
5645
5646 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
5647 req.fid = cpu_to_le16(0xffff);
5648 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5649 req.async_event_cr = cpu_to_le16(idx);
5650 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5651 } else {
5652 struct hwrm_func_vf_cfg_input req = {0};
5653
5654 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_VF_CFG, -1, -1);
5655 req.enables =
5656 cpu_to_le32(FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR);
5657 req.async_event_cr = cpu_to_le16(idx);
5658 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5659 }
5660 return rc;
5661 }
5662
5663 static void bnxt_set_db(struct bnxt *bp, struct bnxt_db_info *db, u32 ring_type,
5664 u32 map_idx, u32 xid)
5665 {
5666 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5667 if (BNXT_PF(bp))
5668 db->doorbell = bp->bar1 + DB_PF_OFFSET_P5;
5669 else
5670 db->doorbell = bp->bar1 + DB_VF_OFFSET_P5;
5671 switch (ring_type) {
5672 case HWRM_RING_ALLOC_TX:
5673 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SQ;
5674 break;
5675 case HWRM_RING_ALLOC_RX:
5676 case HWRM_RING_ALLOC_AGG:
5677 db->db_key64 = DBR_PATH_L2 | DBR_TYPE_SRQ;
5678 break;
5679 case HWRM_RING_ALLOC_CMPL:
5680 db->db_key64 = DBR_PATH_L2;
5681 break;
5682 case HWRM_RING_ALLOC_NQ:
5683 db->db_key64 = DBR_PATH_L2;
5684 break;
5685 }
5686 db->db_key64 |= (u64)xid << DBR_XID_SFT;
5687 } else {
5688 db->doorbell = bp->bar1 + map_idx * 0x80;
5689 switch (ring_type) {
5690 case HWRM_RING_ALLOC_TX:
5691 db->db_key32 = DB_KEY_TX;
5692 break;
5693 case HWRM_RING_ALLOC_RX:
5694 case HWRM_RING_ALLOC_AGG:
5695 db->db_key32 = DB_KEY_RX;
5696 break;
5697 case HWRM_RING_ALLOC_CMPL:
5698 db->db_key32 = DB_KEY_CP;
5699 break;
5700 }
5701 }
5702 }
5703
5704 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
5705 {
5706 bool agg_rings = !!(bp->flags & BNXT_FLAG_AGG_RINGS);
5707 int i, rc = 0;
5708 u32 type;
5709
5710 if (bp->flags & BNXT_FLAG_CHIP_P5)
5711 type = HWRM_RING_ALLOC_NQ;
5712 else
5713 type = HWRM_RING_ALLOC_CMPL;
5714 for (i = 0; i < bp->cp_nr_rings; i++) {
5715 struct bnxt_napi *bnapi = bp->bnapi[i];
5716 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5717 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
5718 u32 map_idx = ring->map_idx;
5719 unsigned int vector;
5720
5721 vector = bp->irq_tbl[map_idx].vector;
5722 disable_irq_nosync(vector);
5723 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5724 if (rc) {
5725 enable_irq(vector);
5726 goto err_out;
5727 }
5728 bnxt_set_db(bp, &cpr->cp_db, type, map_idx, ring->fw_ring_id);
5729 bnxt_db_nq(bp, &cpr->cp_db, cpr->cp_raw_cons);
5730 enable_irq(vector);
5731 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
5732
5733 if (!i) {
5734 rc = bnxt_hwrm_set_async_event_cr(bp, ring->fw_ring_id);
5735 if (rc)
5736 netdev_warn(bp->dev, "Failed to set async event completion ring.\n");
5737 }
5738 }
5739
5740 type = HWRM_RING_ALLOC_TX;
5741 for (i = 0; i < bp->tx_nr_rings; i++) {
5742 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5743 struct bnxt_ring_struct *ring;
5744 u32 map_idx;
5745
5746 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5747 struct bnxt_napi *bnapi = txr->bnapi;
5748 struct bnxt_cp_ring_info *cpr, *cpr2;
5749 u32 type2 = HWRM_RING_ALLOC_CMPL;
5750
5751 cpr = &bnapi->cp_ring;
5752 cpr2 = cpr->cp_ring_arr[BNXT_TX_HDL];
5753 ring = &cpr2->cp_ring_struct;
5754 ring->handle = BNXT_TX_HDL;
5755 map_idx = bnapi->index;
5756 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5757 if (rc)
5758 goto err_out;
5759 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5760 ring->fw_ring_id);
5761 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5762 }
5763 ring = &txr->tx_ring_struct;
5764 map_idx = i;
5765 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5766 if (rc)
5767 goto err_out;
5768 bnxt_set_db(bp, &txr->tx_db, type, map_idx, ring->fw_ring_id);
5769 }
5770
5771 type = HWRM_RING_ALLOC_RX;
5772 for (i = 0; i < bp->rx_nr_rings; i++) {
5773 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5774 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5775 struct bnxt_napi *bnapi = rxr->bnapi;
5776 u32 map_idx = bnapi->index;
5777
5778 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5779 if (rc)
5780 goto err_out;
5781 bnxt_set_db(bp, &rxr->rx_db, type, map_idx, ring->fw_ring_id);
5782 /* If we have agg rings, post agg buffers first. */
5783 if (!agg_rings)
5784 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5785 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
5786 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5787 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5788 u32 type2 = HWRM_RING_ALLOC_CMPL;
5789 struct bnxt_cp_ring_info *cpr2;
5790
5791 cpr2 = cpr->cp_ring_arr[BNXT_RX_HDL];
5792 ring = &cpr2->cp_ring_struct;
5793 ring->handle = BNXT_RX_HDL;
5794 rc = hwrm_ring_alloc_send_msg(bp, ring, type2, map_idx);
5795 if (rc)
5796 goto err_out;
5797 bnxt_set_db(bp, &cpr2->cp_db, type2, map_idx,
5798 ring->fw_ring_id);
5799 bnxt_db_cq(bp, &cpr2->cp_db, cpr2->cp_raw_cons);
5800 }
5801 }
5802
5803 if (agg_rings) {
5804 type = HWRM_RING_ALLOC_AGG;
5805 for (i = 0; i < bp->rx_nr_rings; i++) {
5806 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5807 struct bnxt_ring_struct *ring =
5808 &rxr->rx_agg_ring_struct;
5809 u32 grp_idx = ring->grp_idx;
5810 u32 map_idx = grp_idx + bp->rx_nr_rings;
5811
5812 rc = hwrm_ring_alloc_send_msg(bp, ring, type, map_idx);
5813 if (rc)
5814 goto err_out;
5815
5816 bnxt_set_db(bp, &rxr->rx_agg_db, type, map_idx,
5817 ring->fw_ring_id);
5818 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
5819 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
5820 bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
5821 }
5822 }
5823 err_out:
5824 return rc;
5825 }
5826
5827 static int hwrm_ring_free_send_msg(struct bnxt *bp,
5828 struct bnxt_ring_struct *ring,
5829 u32 ring_type, int cmpl_ring_id)
5830 {
5831 int rc;
5832 struct hwrm_ring_free_input req = {0};
5833 struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
5834 u16 error_code;
5835
5836 if (BNXT_NO_FW_ACCESS(bp))
5837 return 0;
5838
5839 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
5840 req.ring_type = ring_type;
5841 req.ring_id = cpu_to_le16(ring->fw_ring_id);
5842
5843 mutex_lock(&bp->hwrm_cmd_lock);
5844 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5845 error_code = le16_to_cpu(resp->error_code);
5846 mutex_unlock(&bp->hwrm_cmd_lock);
5847
5848 if (rc || error_code) {
5849 netdev_err(bp->dev, "hwrm_ring_free type %d failed. rc:%x err:%x\n",
5850 ring_type, rc, error_code);
5851 return -EIO;
5852 }
5853 return 0;
5854 }
5855
5856 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
5857 {
5858 u32 type;
5859 int i;
5860
5861 if (!bp->bnapi)
5862 return;
5863
5864 for (i = 0; i < bp->tx_nr_rings; i++) {
5865 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
5866 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
5867
5868 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5869 u32 cmpl_ring_id = bnxt_cp_ring_for_tx(bp, txr);
5870
5871 hwrm_ring_free_send_msg(bp, ring,
5872 RING_FREE_REQ_RING_TYPE_TX,
5873 close_path ? cmpl_ring_id :
5874 INVALID_HW_RING_ID);
5875 ring->fw_ring_id = INVALID_HW_RING_ID;
5876 }
5877 }
5878
5879 for (i = 0; i < bp->rx_nr_rings; i++) {
5880 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5881 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
5882 u32 grp_idx = rxr->bnapi->index;
5883
5884 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5885 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5886
5887 hwrm_ring_free_send_msg(bp, ring,
5888 RING_FREE_REQ_RING_TYPE_RX,
5889 close_path ? cmpl_ring_id :
5890 INVALID_HW_RING_ID);
5891 ring->fw_ring_id = INVALID_HW_RING_ID;
5892 bp->grp_info[grp_idx].rx_fw_ring_id =
5893 INVALID_HW_RING_ID;
5894 }
5895 }
5896
5897 if (bp->flags & BNXT_FLAG_CHIP_P5)
5898 type = RING_FREE_REQ_RING_TYPE_RX_AGG;
5899 else
5900 type = RING_FREE_REQ_RING_TYPE_RX;
5901 for (i = 0; i < bp->rx_nr_rings; i++) {
5902 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
5903 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
5904 u32 grp_idx = rxr->bnapi->index;
5905
5906 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5907 u32 cmpl_ring_id = bnxt_cp_ring_for_rx(bp, rxr);
5908
5909 hwrm_ring_free_send_msg(bp, ring, type,
5910 close_path ? cmpl_ring_id :
5911 INVALID_HW_RING_ID);
5912 ring->fw_ring_id = INVALID_HW_RING_ID;
5913 bp->grp_info[grp_idx].agg_fw_ring_id =
5914 INVALID_HW_RING_ID;
5915 }
5916 }
5917
5918 /* The completion rings are about to be freed. After that the
5919 * IRQ doorbell will not work anymore. So we need to disable
5920 * IRQ here.
5921 */
5922 bnxt_disable_int_sync(bp);
5923
5924 if (bp->flags & BNXT_FLAG_CHIP_P5)
5925 type = RING_FREE_REQ_RING_TYPE_NQ;
5926 else
5927 type = RING_FREE_REQ_RING_TYPE_L2_CMPL;
5928 for (i = 0; i < bp->cp_nr_rings; i++) {
5929 struct bnxt_napi *bnapi = bp->bnapi[i];
5930 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5931 struct bnxt_ring_struct *ring;
5932 int j;
5933
5934 for (j = 0; j < 2; j++) {
5935 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
5936
5937 if (cpr2) {
5938 ring = &cpr2->cp_ring_struct;
5939 if (ring->fw_ring_id == INVALID_HW_RING_ID)
5940 continue;
5941 hwrm_ring_free_send_msg(bp, ring,
5942 RING_FREE_REQ_RING_TYPE_L2_CMPL,
5943 INVALID_HW_RING_ID);
5944 ring->fw_ring_id = INVALID_HW_RING_ID;
5945 }
5946 }
5947 ring = &cpr->cp_ring_struct;
5948 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
5949 hwrm_ring_free_send_msg(bp, ring, type,
5950 INVALID_HW_RING_ID);
5951 ring->fw_ring_id = INVALID_HW_RING_ID;
5952 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
5953 }
5954 }
5955 }
5956
5957 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
5958 bool shared);
5959
5960 static int bnxt_hwrm_get_rings(struct bnxt *bp)
5961 {
5962 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
5963 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
5964 struct hwrm_func_qcfg_input req = {0};
5965 int rc;
5966
5967 if (bp->hwrm_spec_code < 0x10601)
5968 return 0;
5969
5970 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
5971 req.fid = cpu_to_le16(0xffff);
5972 mutex_lock(&bp->hwrm_cmd_lock);
5973 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
5974 if (rc) {
5975 mutex_unlock(&bp->hwrm_cmd_lock);
5976 return rc;
5977 }
5978
5979 hw_resc->resv_tx_rings = le16_to_cpu(resp->alloc_tx_rings);
5980 if (BNXT_NEW_RM(bp)) {
5981 u16 cp, stats;
5982
5983 hw_resc->resv_rx_rings = le16_to_cpu(resp->alloc_rx_rings);
5984 hw_resc->resv_hw_ring_grps =
5985 le32_to_cpu(resp->alloc_hw_ring_grps);
5986 hw_resc->resv_vnics = le16_to_cpu(resp->alloc_vnics);
5987 cp = le16_to_cpu(resp->alloc_cmpl_rings);
5988 stats = le16_to_cpu(resp->alloc_stat_ctx);
5989 hw_resc->resv_irqs = cp;
5990 if (bp->flags & BNXT_FLAG_CHIP_P5) {
5991 int rx = hw_resc->resv_rx_rings;
5992 int tx = hw_resc->resv_tx_rings;
5993
5994 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5995 rx >>= 1;
5996 if (cp < (rx + tx)) {
5997 bnxt_trim_rings(bp, &rx, &tx, cp, false);
5998 if (bp->flags & BNXT_FLAG_AGG_RINGS)
5999 rx <<= 1;
6000 hw_resc->resv_rx_rings = rx;
6001 hw_resc->resv_tx_rings = tx;
6002 }
6003 hw_resc->resv_irqs = le16_to_cpu(resp->alloc_msix);
6004 hw_resc->resv_hw_ring_grps = rx;
6005 }
6006 hw_resc->resv_cp_rings = cp;
6007 hw_resc->resv_stat_ctxs = stats;
6008 }
6009 mutex_unlock(&bp->hwrm_cmd_lock);
6010 return 0;
6011 }
6012
6013 /* Caller must hold bp->hwrm_cmd_lock */
6014 int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings)
6015 {
6016 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6017 struct hwrm_func_qcfg_input req = {0};
6018 int rc;
6019
6020 if (bp->hwrm_spec_code < 0x10601)
6021 return 0;
6022
6023 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6024 req.fid = cpu_to_le16(fid);
6025 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6026 if (!rc)
6027 *tx_rings = le16_to_cpu(resp->alloc_tx_rings);
6028
6029 return rc;
6030 }
6031
6032 static bool bnxt_rfs_supported(struct bnxt *bp);
6033
6034 static void
6035 __bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, struct hwrm_func_cfg_input *req,
6036 int tx_rings, int rx_rings, int ring_grps,
6037 int cp_rings, int stats, int vnics)
6038 {
6039 u32 enables = 0;
6040
6041 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_CFG, -1, -1);
6042 req->fid = cpu_to_le16(0xffff);
6043 enables |= tx_rings ? FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6044 req->num_tx_rings = cpu_to_le16(tx_rings);
6045 if (BNXT_NEW_RM(bp)) {
6046 enables |= rx_rings ? FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS : 0;
6047 enables |= stats ? FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6048 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6049 enables |= cp_rings ? FUNC_CFG_REQ_ENABLES_NUM_MSIX : 0;
6050 enables |= tx_rings + ring_grps ?
6051 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6052 enables |= rx_rings ?
6053 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6054 } else {
6055 enables |= cp_rings ?
6056 FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6057 enables |= ring_grps ?
6058 FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS |
6059 FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6060 }
6061 enables |= vnics ? FUNC_CFG_REQ_ENABLES_NUM_VNICS : 0;
6062
6063 req->num_rx_rings = cpu_to_le16(rx_rings);
6064 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6065 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6066 req->num_msix = cpu_to_le16(cp_rings);
6067 req->num_rsscos_ctxs =
6068 cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6069 } else {
6070 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6071 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6072 req->num_rsscos_ctxs = cpu_to_le16(1);
6073 if (!(bp->flags & BNXT_FLAG_NEW_RSS_CAP) &&
6074 bnxt_rfs_supported(bp))
6075 req->num_rsscos_ctxs =
6076 cpu_to_le16(ring_grps + 1);
6077 }
6078 req->num_stat_ctxs = cpu_to_le16(stats);
6079 req->num_vnics = cpu_to_le16(vnics);
6080 }
6081 req->enables = cpu_to_le32(enables);
6082 }
6083
6084 static void
6085 __bnxt_hwrm_reserve_vf_rings(struct bnxt *bp,
6086 struct hwrm_func_vf_cfg_input *req, int tx_rings,
6087 int rx_rings, int ring_grps, int cp_rings,
6088 int stats, int vnics)
6089 {
6090 u32 enables = 0;
6091
6092 bnxt_hwrm_cmd_hdr_init(bp, req, HWRM_FUNC_VF_CFG, -1, -1);
6093 enables |= tx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS : 0;
6094 enables |= rx_rings ? FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS |
6095 FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS : 0;
6096 enables |= stats ? FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS : 0;
6097 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6098 enables |= tx_rings + ring_grps ?
6099 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6100 } else {
6101 enables |= cp_rings ?
6102 FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS : 0;
6103 enables |= ring_grps ?
6104 FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS : 0;
6105 }
6106 enables |= vnics ? FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS : 0;
6107 enables |= FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS;
6108
6109 req->num_l2_ctxs = cpu_to_le16(BNXT_VF_MAX_L2_CTX);
6110 req->num_tx_rings = cpu_to_le16(tx_rings);
6111 req->num_rx_rings = cpu_to_le16(rx_rings);
6112 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6113 req->num_cmpl_rings = cpu_to_le16(tx_rings + ring_grps);
6114 req->num_rsscos_ctxs = cpu_to_le16(DIV_ROUND_UP(ring_grps, 64));
6115 } else {
6116 req->num_cmpl_rings = cpu_to_le16(cp_rings);
6117 req->num_hw_ring_grps = cpu_to_le16(ring_grps);
6118 req->num_rsscos_ctxs = cpu_to_le16(BNXT_VF_MAX_RSS_CTX);
6119 }
6120 req->num_stat_ctxs = cpu_to_le16(stats);
6121 req->num_vnics = cpu_to_le16(vnics);
6122
6123 req->enables = cpu_to_le32(enables);
6124 }
6125
6126 static int
6127 bnxt_hwrm_reserve_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6128 int ring_grps, int cp_rings, int stats, int vnics)
6129 {
6130 struct hwrm_func_cfg_input req = {0};
6131 int rc;
6132
6133 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6134 cp_rings, stats, vnics);
6135 if (!req.enables)
6136 return 0;
6137
6138 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6139 if (rc)
6140 return rc;
6141
6142 if (bp->hwrm_spec_code < 0x10601)
6143 bp->hw_resc.resv_tx_rings = tx_rings;
6144
6145 return bnxt_hwrm_get_rings(bp);
6146 }
6147
6148 static int
6149 bnxt_hwrm_reserve_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6150 int ring_grps, int cp_rings, int stats, int vnics)
6151 {
6152 struct hwrm_func_vf_cfg_input req = {0};
6153 int rc;
6154
6155 if (!BNXT_NEW_RM(bp)) {
6156 bp->hw_resc.resv_tx_rings = tx_rings;
6157 return 0;
6158 }
6159
6160 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6161 cp_rings, stats, vnics);
6162 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6163 if (rc)
6164 return rc;
6165
6166 return bnxt_hwrm_get_rings(bp);
6167 }
6168
6169 static int bnxt_hwrm_reserve_rings(struct bnxt *bp, int tx, int rx, int grp,
6170 int cp, int stat, int vnic)
6171 {
6172 if (BNXT_PF(bp))
6173 return bnxt_hwrm_reserve_pf_rings(bp, tx, rx, grp, cp, stat,
6174 vnic);
6175 else
6176 return bnxt_hwrm_reserve_vf_rings(bp, tx, rx, grp, cp, stat,
6177 vnic);
6178 }
6179
6180 int bnxt_nq_rings_in_use(struct bnxt *bp)
6181 {
6182 int cp = bp->cp_nr_rings;
6183 int ulp_msix, ulp_base;
6184
6185 ulp_msix = bnxt_get_ulp_msix_num(bp);
6186 if (ulp_msix) {
6187 ulp_base = bnxt_get_ulp_msix_base(bp);
6188 cp += ulp_msix;
6189 if ((ulp_base + ulp_msix) > cp)
6190 cp = ulp_base + ulp_msix;
6191 }
6192 return cp;
6193 }
6194
6195 static int bnxt_cp_rings_in_use(struct bnxt *bp)
6196 {
6197 int cp;
6198
6199 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6200 return bnxt_nq_rings_in_use(bp);
6201
6202 cp = bp->tx_nr_rings + bp->rx_nr_rings;
6203 return cp;
6204 }
6205
6206 static int bnxt_get_func_stat_ctxs(struct bnxt *bp)
6207 {
6208 int ulp_stat = bnxt_get_ulp_stat_ctxs(bp);
6209 int cp = bp->cp_nr_rings;
6210
6211 if (!ulp_stat)
6212 return cp;
6213
6214 if (bnxt_nq_rings_in_use(bp) > cp + bnxt_get_ulp_msix_num(bp))
6215 return bnxt_get_ulp_msix_base(bp) + ulp_stat;
6216
6217 return cp + ulp_stat;
6218 }
6219
6220 /* Check if a default RSS map needs to be setup. This function is only
6221 * used on older firmware that does not require reserving RX rings.
6222 */
6223 static void bnxt_check_rss_tbl_no_rmgr(struct bnxt *bp)
6224 {
6225 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6226
6227 /* The RSS map is valid for RX rings set to resv_rx_rings */
6228 if (hw_resc->resv_rx_rings != bp->rx_nr_rings) {
6229 hw_resc->resv_rx_rings = bp->rx_nr_rings;
6230 if (!netif_is_rxfh_configured(bp->dev))
6231 bnxt_set_dflt_rss_indir_tbl(bp);
6232 }
6233 }
6234
6235 static bool bnxt_need_reserve_rings(struct bnxt *bp)
6236 {
6237 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6238 int cp = bnxt_cp_rings_in_use(bp);
6239 int nq = bnxt_nq_rings_in_use(bp);
6240 int rx = bp->rx_nr_rings, stat;
6241 int vnic = 1, grp = rx;
6242
6243 if (hw_resc->resv_tx_rings != bp->tx_nr_rings &&
6244 bp->hwrm_spec_code >= 0x10601)
6245 return true;
6246
6247 /* Old firmware does not need RX ring reservations but we still
6248 * need to setup a default RSS map when needed. With new firmware
6249 * we go through RX ring reservations first and then set up the
6250 * RSS map for the successfully reserved RX rings when needed.
6251 */
6252 if (!BNXT_NEW_RM(bp)) {
6253 bnxt_check_rss_tbl_no_rmgr(bp);
6254 return false;
6255 }
6256 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6257 vnic = rx + 1;
6258 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6259 rx <<= 1;
6260 stat = bnxt_get_func_stat_ctxs(bp);
6261 if (hw_resc->resv_rx_rings != rx || hw_resc->resv_cp_rings != cp ||
6262 hw_resc->resv_vnics != vnic || hw_resc->resv_stat_ctxs != stat ||
6263 (hw_resc->resv_hw_ring_grps != grp &&
6264 !(bp->flags & BNXT_FLAG_CHIP_P5)))
6265 return true;
6266 if ((bp->flags & BNXT_FLAG_CHIP_P5) && BNXT_PF(bp) &&
6267 hw_resc->resv_irqs != nq)
6268 return true;
6269 return false;
6270 }
6271
6272 static int __bnxt_reserve_rings(struct bnxt *bp)
6273 {
6274 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
6275 int cp = bnxt_nq_rings_in_use(bp);
6276 int tx = bp->tx_nr_rings;
6277 int rx = bp->rx_nr_rings;
6278 int grp, rx_rings, rc;
6279 int vnic = 1, stat;
6280 bool sh = false;
6281
6282 if (!bnxt_need_reserve_rings(bp))
6283 return 0;
6284
6285 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
6286 sh = true;
6287 if ((bp->flags & BNXT_FLAG_RFS) && !(bp->flags & BNXT_FLAG_CHIP_P5))
6288 vnic = rx + 1;
6289 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6290 rx <<= 1;
6291 grp = bp->rx_nr_rings;
6292 stat = bnxt_get_func_stat_ctxs(bp);
6293
6294 rc = bnxt_hwrm_reserve_rings(bp, tx, rx, grp, cp, stat, vnic);
6295 if (rc)
6296 return rc;
6297
6298 tx = hw_resc->resv_tx_rings;
6299 if (BNXT_NEW_RM(bp)) {
6300 rx = hw_resc->resv_rx_rings;
6301 cp = hw_resc->resv_irqs;
6302 grp = hw_resc->resv_hw_ring_grps;
6303 vnic = hw_resc->resv_vnics;
6304 stat = hw_resc->resv_stat_ctxs;
6305 }
6306
6307 rx_rings = rx;
6308 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
6309 if (rx >= 2) {
6310 rx_rings = rx >> 1;
6311 } else {
6312 if (netif_running(bp->dev))
6313 return -ENOMEM;
6314
6315 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
6316 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
6317 bp->dev->hw_features &= ~NETIF_F_LRO;
6318 bp->dev->features &= ~NETIF_F_LRO;
6319 bnxt_set_ring_params(bp);
6320 }
6321 }
6322 rx_rings = min_t(int, rx_rings, grp);
6323 cp = min_t(int, cp, bp->cp_nr_rings);
6324 if (stat > bnxt_get_ulp_stat_ctxs(bp))
6325 stat -= bnxt_get_ulp_stat_ctxs(bp);
6326 cp = min_t(int, cp, stat);
6327 rc = bnxt_trim_rings(bp, &rx_rings, &tx, cp, sh);
6328 if (bp->flags & BNXT_FLAG_AGG_RINGS)
6329 rx = rx_rings << 1;
6330 cp = sh ? max_t(int, tx, rx_rings) : tx + rx_rings;
6331 bp->tx_nr_rings = tx;
6332
6333 /* If we cannot reserve all the RX rings, reset the RSS map only
6334 * if absolutely necessary
6335 */
6336 if (rx_rings != bp->rx_nr_rings) {
6337 netdev_warn(bp->dev, "Able to reserve only %d out of %d requested RX rings\n",
6338 rx_rings, bp->rx_nr_rings);
6339 if ((bp->dev->priv_flags & IFF_RXFH_CONFIGURED) &&
6340 (bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings) !=
6341 bnxt_get_nr_rss_ctxs(bp, rx_rings) ||
6342 bnxt_get_max_rss_ring(bp) >= rx_rings)) {
6343 netdev_warn(bp->dev, "RSS table entries reverting to default\n");
6344 bp->dev->priv_flags &= ~IFF_RXFH_CONFIGURED;
6345 }
6346 }
6347 bp->rx_nr_rings = rx_rings;
6348 bp->cp_nr_rings = cp;
6349
6350 if (!tx || !rx || !cp || !grp || !vnic || !stat)
6351 return -ENOMEM;
6352
6353 if (!netif_is_rxfh_configured(bp->dev))
6354 bnxt_set_dflt_rss_indir_tbl(bp);
6355
6356 return rc;
6357 }
6358
6359 static int bnxt_hwrm_check_vf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6360 int ring_grps, int cp_rings, int stats,
6361 int vnics)
6362 {
6363 struct hwrm_func_vf_cfg_input req = {0};
6364 u32 flags;
6365
6366 if (!BNXT_NEW_RM(bp))
6367 return 0;
6368
6369 __bnxt_hwrm_reserve_vf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6370 cp_rings, stats, vnics);
6371 flags = FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST |
6372 FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6373 FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6374 FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6375 FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST |
6376 FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST;
6377 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6378 flags |= FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6379
6380 req.flags = cpu_to_le32(flags);
6381 return hwrm_send_message_silent(bp, &req, sizeof(req),
6382 HWRM_CMD_TIMEOUT);
6383 }
6384
6385 static int bnxt_hwrm_check_pf_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6386 int ring_grps, int cp_rings, int stats,
6387 int vnics)
6388 {
6389 struct hwrm_func_cfg_input req = {0};
6390 u32 flags;
6391
6392 __bnxt_hwrm_reserve_pf_rings(bp, &req, tx_rings, rx_rings, ring_grps,
6393 cp_rings, stats, vnics);
6394 flags = FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST;
6395 if (BNXT_NEW_RM(bp)) {
6396 flags |= FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST |
6397 FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST |
6398 FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST |
6399 FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST;
6400 if (bp->flags & BNXT_FLAG_CHIP_P5)
6401 flags |= FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST |
6402 FUNC_CFG_REQ_FLAGS_NQ_ASSETS_TEST;
6403 else
6404 flags |= FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST;
6405 }
6406
6407 req.flags = cpu_to_le32(flags);
6408 return hwrm_send_message_silent(bp, &req, sizeof(req),
6409 HWRM_CMD_TIMEOUT);
6410 }
6411
6412 static int bnxt_hwrm_check_rings(struct bnxt *bp, int tx_rings, int rx_rings,
6413 int ring_grps, int cp_rings, int stats,
6414 int vnics)
6415 {
6416 if (bp->hwrm_spec_code < 0x10801)
6417 return 0;
6418
6419 if (BNXT_PF(bp))
6420 return bnxt_hwrm_check_pf_rings(bp, tx_rings, rx_rings,
6421 ring_grps, cp_rings, stats,
6422 vnics);
6423
6424 return bnxt_hwrm_check_vf_rings(bp, tx_rings, rx_rings, ring_grps,
6425 cp_rings, stats, vnics);
6426 }
6427
6428 static void bnxt_hwrm_coal_params_qcaps(struct bnxt *bp)
6429 {
6430 struct hwrm_ring_aggint_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
6431 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6432 struct hwrm_ring_aggint_qcaps_input req = {0};
6433 int rc;
6434
6435 coal_cap->cmpl_params = BNXT_LEGACY_COAL_CMPL_PARAMS;
6436 coal_cap->num_cmpl_dma_aggr_max = 63;
6437 coal_cap->num_cmpl_dma_aggr_during_int_max = 63;
6438 coal_cap->cmpl_aggr_dma_tmr_max = 65535;
6439 coal_cap->cmpl_aggr_dma_tmr_during_int_max = 65535;
6440 coal_cap->int_lat_tmr_min_max = 65535;
6441 coal_cap->int_lat_tmr_max_max = 65535;
6442 coal_cap->num_cmpl_aggr_int_max = 65535;
6443 coal_cap->timer_units = 80;
6444
6445 if (bp->hwrm_spec_code < 0x10902)
6446 return;
6447
6448 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_AGGINT_QCAPS, -1, -1);
6449 mutex_lock(&bp->hwrm_cmd_lock);
6450 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6451 if (!rc) {
6452 coal_cap->cmpl_params = le32_to_cpu(resp->cmpl_params);
6453 coal_cap->nq_params = le32_to_cpu(resp->nq_params);
6454 coal_cap->num_cmpl_dma_aggr_max =
6455 le16_to_cpu(resp->num_cmpl_dma_aggr_max);
6456 coal_cap->num_cmpl_dma_aggr_during_int_max =
6457 le16_to_cpu(resp->num_cmpl_dma_aggr_during_int_max);
6458 coal_cap->cmpl_aggr_dma_tmr_max =
6459 le16_to_cpu(resp->cmpl_aggr_dma_tmr_max);
6460 coal_cap->cmpl_aggr_dma_tmr_during_int_max =
6461 le16_to_cpu(resp->cmpl_aggr_dma_tmr_during_int_max);
6462 coal_cap->int_lat_tmr_min_max =
6463 le16_to_cpu(resp->int_lat_tmr_min_max);
6464 coal_cap->int_lat_tmr_max_max =
6465 le16_to_cpu(resp->int_lat_tmr_max_max);
6466 coal_cap->num_cmpl_aggr_int_max =
6467 le16_to_cpu(resp->num_cmpl_aggr_int_max);
6468 coal_cap->timer_units = le16_to_cpu(resp->timer_units);
6469 }
6470 mutex_unlock(&bp->hwrm_cmd_lock);
6471 }
6472
6473 static u16 bnxt_usec_to_coal_tmr(struct bnxt *bp, u16 usec)
6474 {
6475 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6476
6477 return usec * 1000 / coal_cap->timer_units;
6478 }
6479
6480 static void bnxt_hwrm_set_coal_params(struct bnxt *bp,
6481 struct bnxt_coal *hw_coal,
6482 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
6483 {
6484 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6485 u32 cmpl_params = coal_cap->cmpl_params;
6486 u16 val, tmr, max, flags = 0;
6487
6488 max = hw_coal->bufs_per_record * 128;
6489 if (hw_coal->budget)
6490 max = hw_coal->bufs_per_record * hw_coal->budget;
6491 max = min_t(u16, max, coal_cap->num_cmpl_aggr_int_max);
6492
6493 val = clamp_t(u16, hw_coal->coal_bufs, 1, max);
6494 req->num_cmpl_aggr_int = cpu_to_le16(val);
6495
6496 val = min_t(u16, val, coal_cap->num_cmpl_dma_aggr_max);
6497 req->num_cmpl_dma_aggr = cpu_to_le16(val);
6498
6499 val = clamp_t(u16, hw_coal->coal_bufs_irq, 1,
6500 coal_cap->num_cmpl_dma_aggr_during_int_max);
6501 req->num_cmpl_dma_aggr_during_int = cpu_to_le16(val);
6502
6503 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks);
6504 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_max_max);
6505 req->int_lat_tmr_max = cpu_to_le16(tmr);
6506
6507 /* min timer set to 1/2 of interrupt timer */
6508 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN) {
6509 val = tmr / 2;
6510 val = clamp_t(u16, val, 1, coal_cap->int_lat_tmr_min_max);
6511 req->int_lat_tmr_min = cpu_to_le16(val);
6512 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6513 }
6514
6515 /* buf timer set to 1/4 of interrupt timer */
6516 val = clamp_t(u16, tmr / 4, 1, coal_cap->cmpl_aggr_dma_tmr_max);
6517 req->cmpl_aggr_dma_tmr = cpu_to_le16(val);
6518
6519 if (cmpl_params &
6520 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT) {
6521 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks_irq);
6522 val = clamp_t(u16, tmr, 1,
6523 coal_cap->cmpl_aggr_dma_tmr_during_int_max);
6524 req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(val);
6525 req->enables |=
6526 cpu_to_le16(BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE);
6527 }
6528
6529 if (cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET)
6530 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
6531 if ((cmpl_params & RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE) &&
6532 hw_coal->idle_thresh && hw_coal->coal_ticks < hw_coal->idle_thresh)
6533 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
6534 req->flags = cpu_to_le16(flags);
6535 req->enables |= cpu_to_le16(BNXT_COAL_CMPL_ENABLES);
6536 }
6537
6538 /* Caller holds bp->hwrm_cmd_lock */
6539 static int __bnxt_hwrm_set_coal_nq(struct bnxt *bp, struct bnxt_napi *bnapi,
6540 struct bnxt_coal *hw_coal)
6541 {
6542 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
6543 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6544 struct bnxt_coal_cap *coal_cap = &bp->coal_cap;
6545 u32 nq_params = coal_cap->nq_params;
6546 u16 tmr;
6547
6548 if (!(nq_params & RING_AGGINT_QCAPS_RESP_NQ_PARAMS_INT_LAT_TMR_MIN))
6549 return 0;
6550
6551 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
6552 -1, -1);
6553 req.ring_id = cpu_to_le16(cpr->cp_ring_struct.fw_ring_id);
6554 req.flags =
6555 cpu_to_le16(RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_IS_NQ);
6556
6557 tmr = bnxt_usec_to_coal_tmr(bp, hw_coal->coal_ticks) / 2;
6558 tmr = clamp_t(u16, tmr, 1, coal_cap->int_lat_tmr_min_max);
6559 req.int_lat_tmr_min = cpu_to_le16(tmr);
6560 req.enables |= cpu_to_le16(BNXT_COAL_CMPL_MIN_TMR_ENABLE);
6561 return _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6562 }
6563
6564 int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi)
6565 {
6566 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0};
6567 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6568 struct bnxt_coal coal;
6569
6570 /* Tick values in micro seconds.
6571 * 1 coal_buf x bufs_per_record = 1 completion record.
6572 */
6573 memcpy(&coal, &bp->rx_coal, sizeof(struct bnxt_coal));
6574
6575 coal.coal_ticks = cpr->rx_ring_coal.coal_ticks;
6576 coal.coal_bufs = cpr->rx_ring_coal.coal_bufs;
6577
6578 if (!bnapi->rx_ring)
6579 return -ENODEV;
6580
6581 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6582 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6583
6584 bnxt_hwrm_set_coal_params(bp, &coal, &req_rx);
6585
6586 req_rx.ring_id = cpu_to_le16(bnxt_cp_ring_for_rx(bp, bnapi->rx_ring));
6587
6588 return hwrm_send_message(bp, &req_rx, sizeof(req_rx),
6589 HWRM_CMD_TIMEOUT);
6590 }
6591
6592 int bnxt_hwrm_set_coal(struct bnxt *bp)
6593 {
6594 int i, rc = 0;
6595 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
6596 req_tx = {0}, *req;
6597
6598 bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
6599 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6600 bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
6601 HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
6602
6603 bnxt_hwrm_set_coal_params(bp, &bp->rx_coal, &req_rx);
6604 bnxt_hwrm_set_coal_params(bp, &bp->tx_coal, &req_tx);
6605
6606 mutex_lock(&bp->hwrm_cmd_lock);
6607 for (i = 0; i < bp->cp_nr_rings; i++) {
6608 struct bnxt_napi *bnapi = bp->bnapi[i];
6609 struct bnxt_coal *hw_coal;
6610 u16 ring_id;
6611
6612 req = &req_rx;
6613 if (!bnapi->rx_ring) {
6614 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6615 req = &req_tx;
6616 } else {
6617 ring_id = bnxt_cp_ring_for_rx(bp, bnapi->rx_ring);
6618 }
6619 req->ring_id = cpu_to_le16(ring_id);
6620
6621 rc = _hwrm_send_message(bp, req, sizeof(*req),
6622 HWRM_CMD_TIMEOUT);
6623 if (rc)
6624 break;
6625
6626 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
6627 continue;
6628
6629 if (bnapi->rx_ring && bnapi->tx_ring) {
6630 req = &req_tx;
6631 ring_id = bnxt_cp_ring_for_tx(bp, bnapi->tx_ring);
6632 req->ring_id = cpu_to_le16(ring_id);
6633 rc = _hwrm_send_message(bp, req, sizeof(*req),
6634 HWRM_CMD_TIMEOUT);
6635 if (rc)
6636 break;
6637 }
6638 if (bnapi->rx_ring)
6639 hw_coal = &bp->rx_coal;
6640 else
6641 hw_coal = &bp->tx_coal;
6642 __bnxt_hwrm_set_coal_nq(bp, bnapi, hw_coal);
6643 }
6644 mutex_unlock(&bp->hwrm_cmd_lock);
6645 return rc;
6646 }
6647
6648 static void bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
6649 {
6650 struct hwrm_stat_ctx_clr_stats_input req0 = {0};
6651 struct hwrm_stat_ctx_free_input req = {0};
6652 int i;
6653
6654 if (!bp->bnapi)
6655 return;
6656
6657 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6658 return;
6659
6660 bnxt_hwrm_cmd_hdr_init(bp, &req0, HWRM_STAT_CTX_CLR_STATS, -1, -1);
6661 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
6662
6663 mutex_lock(&bp->hwrm_cmd_lock);
6664 for (i = 0; i < bp->cp_nr_rings; i++) {
6665 struct bnxt_napi *bnapi = bp->bnapi[i];
6666 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6667
6668 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
6669 req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
6670 if (BNXT_FW_MAJ(bp) <= 20) {
6671 req0.stat_ctx_id = req.stat_ctx_id;
6672 _hwrm_send_message(bp, &req0, sizeof(req0),
6673 HWRM_CMD_TIMEOUT);
6674 }
6675 _hwrm_send_message(bp, &req, sizeof(req),
6676 HWRM_CMD_TIMEOUT);
6677
6678 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
6679 }
6680 }
6681 mutex_unlock(&bp->hwrm_cmd_lock);
6682 }
6683
6684 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
6685 {
6686 int rc = 0, i;
6687 struct hwrm_stat_ctx_alloc_input req = {0};
6688 struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
6689
6690 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
6691 return 0;
6692
6693 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
6694
6695 req.stats_dma_length = cpu_to_le16(bp->hw_ring_stats_size);
6696 req.update_period_ms = cpu_to_le32(bp->stats_coal_ticks / 1000);
6697
6698 mutex_lock(&bp->hwrm_cmd_lock);
6699 for (i = 0; i < bp->cp_nr_rings; i++) {
6700 struct bnxt_napi *bnapi = bp->bnapi[i];
6701 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
6702
6703 req.stats_dma_addr = cpu_to_le64(cpr->stats.hw_stats_map);
6704
6705 rc = _hwrm_send_message(bp, &req, sizeof(req),
6706 HWRM_CMD_TIMEOUT);
6707 if (rc)
6708 break;
6709
6710 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
6711
6712 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
6713 }
6714 mutex_unlock(&bp->hwrm_cmd_lock);
6715 return rc;
6716 }
6717
6718 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
6719 {
6720 struct hwrm_func_qcfg_input req = {0};
6721 struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
6722 u32 min_db_offset = 0;
6723 u16 flags;
6724 int rc;
6725
6726 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
6727 req.fid = cpu_to_le16(0xffff);
6728 mutex_lock(&bp->hwrm_cmd_lock);
6729 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6730 if (rc)
6731 goto func_qcfg_exit;
6732
6733 #ifdef CONFIG_BNXT_SRIOV
6734 if (BNXT_VF(bp)) {
6735 struct bnxt_vf_info *vf = &bp->vf;
6736
6737 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
6738 } else {
6739 bp->pf.registered_vfs = le16_to_cpu(resp->registered_vfs);
6740 }
6741 #endif
6742 flags = le16_to_cpu(resp->flags);
6743 if (flags & (FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED |
6744 FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED)) {
6745 bp->fw_cap |= BNXT_FW_CAP_LLDP_AGENT;
6746 if (flags & FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED)
6747 bp->fw_cap |= BNXT_FW_CAP_DCBX_AGENT;
6748 }
6749 if (BNXT_PF(bp) && (flags & FUNC_QCFG_RESP_FLAGS_MULTI_HOST))
6750 bp->flags |= BNXT_FLAG_MULTI_HOST;
6751 if (flags & FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED)
6752 bp->fw_cap |= BNXT_FW_CAP_RING_MONITOR;
6753
6754 switch (resp->port_partition_type) {
6755 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
6756 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
6757 case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
6758 bp->port_partition_type = resp->port_partition_type;
6759 break;
6760 }
6761 if (bp->hwrm_spec_code < 0x10707 ||
6762 resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEB)
6763 bp->br_mode = BRIDGE_MODE_VEB;
6764 else if (resp->evb_mode == FUNC_QCFG_RESP_EVB_MODE_VEPA)
6765 bp->br_mode = BRIDGE_MODE_VEPA;
6766 else
6767 bp->br_mode = BRIDGE_MODE_UNDEF;
6768
6769 bp->max_mtu = le16_to_cpu(resp->max_mtu_configured);
6770 if (!bp->max_mtu)
6771 bp->max_mtu = BNXT_MAX_MTU;
6772
6773 if (bp->db_size)
6774 goto func_qcfg_exit;
6775
6776 if (bp->flags & BNXT_FLAG_CHIP_P5) {
6777 if (BNXT_PF(bp))
6778 min_db_offset = DB_PF_OFFSET_P5;
6779 else
6780 min_db_offset = DB_VF_OFFSET_P5;
6781 }
6782 bp->db_size = PAGE_ALIGN(le16_to_cpu(resp->l2_doorbell_bar_size_kb) *
6783 1024);
6784 if (!bp->db_size || bp->db_size > pci_resource_len(bp->pdev, 2) ||
6785 bp->db_size <= min_db_offset)
6786 bp->db_size = pci_resource_len(bp->pdev, 2);
6787
6788 func_qcfg_exit:
6789 mutex_unlock(&bp->hwrm_cmd_lock);
6790 return rc;
6791 }
6792
6793 static void bnxt_init_ctx_initializer(struct bnxt_ctx_mem_info *ctx,
6794 struct hwrm_func_backing_store_qcaps_output *resp)
6795 {
6796 struct bnxt_mem_init *mem_init;
6797 u16 init_mask;
6798 u8 init_val;
6799 u8 *offset;
6800 int i;
6801
6802 init_val = resp->ctx_kind_initializer;
6803 init_mask = le16_to_cpu(resp->ctx_init_mask);
6804 offset = &resp->qp_init_offset;
6805 mem_init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
6806 for (i = 0; i < BNXT_CTX_MEM_INIT_MAX; i++, mem_init++, offset++) {
6807 mem_init->init_val = init_val;
6808 mem_init->offset = BNXT_MEM_INVALID_OFFSET;
6809 if (!init_mask)
6810 continue;
6811 if (i == BNXT_CTX_MEM_INIT_STAT)
6812 offset = &resp->stat_init_offset;
6813 if (init_mask & (1 << i))
6814 mem_init->offset = *offset * 4;
6815 else
6816 mem_init->init_val = 0;
6817 }
6818 ctx->mem_init[BNXT_CTX_MEM_INIT_QP].size = ctx->qp_entry_size;
6819 ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ].size = ctx->srq_entry_size;
6820 ctx->mem_init[BNXT_CTX_MEM_INIT_CQ].size = ctx->cq_entry_size;
6821 ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC].size = ctx->vnic_entry_size;
6822 ctx->mem_init[BNXT_CTX_MEM_INIT_STAT].size = ctx->stat_entry_size;
6823 ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV].size = ctx->mrav_entry_size;
6824 }
6825
6826 static int bnxt_hwrm_func_backing_store_qcaps(struct bnxt *bp)
6827 {
6828 struct hwrm_func_backing_store_qcaps_input req = {0};
6829 struct hwrm_func_backing_store_qcaps_output *resp =
6830 bp->hwrm_cmd_resp_addr;
6831 int rc;
6832
6833 if (bp->hwrm_spec_code < 0x10902 || BNXT_VF(bp) || bp->ctx)
6834 return 0;
6835
6836 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_QCAPS, -1, -1);
6837 mutex_lock(&bp->hwrm_cmd_lock);
6838 rc = _hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
6839 if (!rc) {
6840 struct bnxt_ctx_pg_info *ctx_pg;
6841 struct bnxt_ctx_mem_info *ctx;
6842 int i, tqm_rings;
6843
6844 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
6845 if (!ctx) {
6846 rc = -ENOMEM;
6847 goto ctx_err;
6848 }
6849 ctx->qp_max_entries = le32_to_cpu(resp->qp_max_entries);
6850 ctx->qp_min_qp1_entries = le16_to_cpu(resp->qp_min_qp1_entries);
6851 ctx->qp_max_l2_entries = le16_to_cpu(resp->qp_max_l2_entries);
6852 ctx->qp_entry_size = le16_to_cpu(resp->qp_entry_size);
6853 ctx->srq_max_l2_entries = le16_to_cpu(resp->srq_max_l2_entries);
6854 ctx->srq_max_entries = le32_to_cpu(resp->srq_max_entries);
6855 ctx->srq_entry_size = le16_to_cpu(resp->srq_entry_size);
6856 ctx->cq_max_l2_entries = le16_to_cpu(resp->cq_max_l2_entries);
6857 ctx->cq_max_entries = le32_to_cpu(resp->cq_max_entries);
6858 ctx->cq_entry_size = le16_to_cpu(resp->cq_entry_size);
6859 ctx->vnic_max_vnic_entries =
6860 le16_to_cpu(resp->vnic_max_vnic_entries);
6861 ctx->vnic_max_ring_table_entries =
6862 le16_to_cpu(resp->vnic_max_ring_table_entries);
6863 ctx->vnic_entry_size = le16_to_cpu(resp->vnic_entry_size);
6864 ctx->stat_max_entries = le32_to_cpu(resp->stat_max_entries);
6865 ctx->stat_entry_size = le16_to_cpu(resp->stat_entry_size);
6866 ctx->tqm_entry_size = le16_to_cpu(resp->tqm_entry_size);
6867 ctx->tqm_min_entries_per_ring =
6868 le32_to_cpu(resp->tqm_min_entries_per_ring);
6869 ctx->tqm_max_entries_per_ring =
6870 le32_to_cpu(resp->tqm_max_entries_per_ring);
6871 ctx->tqm_entries_multiple = resp->tqm_entries_multiple;
6872 if (!ctx->tqm_entries_multiple)
6873 ctx->tqm_entries_multiple = 1;
6874 ctx->mrav_max_entries = le32_to_cpu(resp->mrav_max_entries);
6875 ctx->mrav_entry_size = le16_to_cpu(resp->mrav_entry_size);
6876 ctx->mrav_num_entries_units =
6877 le16_to_cpu(resp->mrav_num_entries_units);
6878 ctx->tim_entry_size = le16_to_cpu(resp->tim_entry_size);
6879 ctx->tim_max_entries = le32_to_cpu(resp->tim_max_entries);
6880
6881 bnxt_init_ctx_initializer(ctx, resp);
6882
6883 ctx->tqm_fp_rings_count = resp->tqm_fp_rings_count;
6884 if (!ctx->tqm_fp_rings_count)
6885 ctx->tqm_fp_rings_count = bp->max_q;
6886 else if (ctx->tqm_fp_rings_count > BNXT_MAX_TQM_FP_RINGS)
6887 ctx->tqm_fp_rings_count = BNXT_MAX_TQM_FP_RINGS;
6888
6889 tqm_rings = ctx->tqm_fp_rings_count + BNXT_MAX_TQM_SP_RINGS;
6890 ctx_pg = kcalloc(tqm_rings, sizeof(*ctx_pg), GFP_KERNEL);
6891 if (!ctx_pg) {
6892 kfree(ctx);
6893 rc = -ENOMEM;
6894 goto ctx_err;
6895 }
6896 for (i = 0; i < tqm_rings; i++, ctx_pg++)
6897 ctx->tqm_mem[i] = ctx_pg;
6898 bp->ctx = ctx;
6899 } else {
6900 rc = 0;
6901 }
6902 ctx_err:
6903 mutex_unlock(&bp->hwrm_cmd_lock);
6904 return rc;
6905 }
6906
6907 static void bnxt_hwrm_set_pg_attr(struct bnxt_ring_mem_info *rmem, u8 *pg_attr,
6908 __le64 *pg_dir)
6909 {
6910 u8 pg_size = 0;
6911
6912 if (!rmem->nr_pages)
6913 return;
6914
6915 if (BNXT_PAGE_SHIFT == 13)
6916 pg_size = 1 << 4;
6917 else if (BNXT_PAGE_SIZE == 16)
6918 pg_size = 2 << 4;
6919
6920 *pg_attr = pg_size;
6921 if (rmem->depth >= 1) {
6922 if (rmem->depth == 2)
6923 *pg_attr |= 2;
6924 else
6925 *pg_attr |= 1;
6926 *pg_dir = cpu_to_le64(rmem->pg_tbl_map);
6927 } else {
6928 *pg_dir = cpu_to_le64(rmem->dma_arr[0]);
6929 }
6930 }
6931
6932 #define FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES \
6933 (FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP | \
6934 FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ | \
6935 FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ | \
6936 FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC | \
6937 FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT)
6938
6939 static int bnxt_hwrm_func_backing_store_cfg(struct bnxt *bp, u32 enables)
6940 {
6941 struct hwrm_func_backing_store_cfg_input req = {0};
6942 struct bnxt_ctx_mem_info *ctx = bp->ctx;
6943 struct bnxt_ctx_pg_info *ctx_pg;
6944 u32 req_len = sizeof(req);
6945 __le32 *num_entries;
6946 __le64 *pg_dir;
6947 u32 flags = 0;
6948 u8 *pg_attr;
6949 u32 ena;
6950 int i;
6951
6952 if (!ctx)
6953 return 0;
6954
6955 if (req_len > bp->hwrm_max_ext_req_len)
6956 req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN;
6957 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1);
6958 req.enables = cpu_to_le32(enables);
6959
6960 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP) {
6961 ctx_pg = &ctx->qp_mem;
6962 req.qp_num_entries = cpu_to_le32(ctx_pg->entries);
6963 req.qp_num_qp1_entries = cpu_to_le16(ctx->qp_min_qp1_entries);
6964 req.qp_num_l2_entries = cpu_to_le16(ctx->qp_max_l2_entries);
6965 req.qp_entry_size = cpu_to_le16(ctx->qp_entry_size);
6966 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6967 &req.qpc_pg_size_qpc_lvl,
6968 &req.qpc_page_dir);
6969 }
6970 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ) {
6971 ctx_pg = &ctx->srq_mem;
6972 req.srq_num_entries = cpu_to_le32(ctx_pg->entries);
6973 req.srq_num_l2_entries = cpu_to_le16(ctx->srq_max_l2_entries);
6974 req.srq_entry_size = cpu_to_le16(ctx->srq_entry_size);
6975 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6976 &req.srq_pg_size_srq_lvl,
6977 &req.srq_page_dir);
6978 }
6979 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ) {
6980 ctx_pg = &ctx->cq_mem;
6981 req.cq_num_entries = cpu_to_le32(ctx_pg->entries);
6982 req.cq_num_l2_entries = cpu_to_le16(ctx->cq_max_l2_entries);
6983 req.cq_entry_size = cpu_to_le16(ctx->cq_entry_size);
6984 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, &req.cq_pg_size_cq_lvl,
6985 &req.cq_page_dir);
6986 }
6987 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC) {
6988 ctx_pg = &ctx->vnic_mem;
6989 req.vnic_num_vnic_entries =
6990 cpu_to_le16(ctx->vnic_max_vnic_entries);
6991 req.vnic_num_ring_table_entries =
6992 cpu_to_le16(ctx->vnic_max_ring_table_entries);
6993 req.vnic_entry_size = cpu_to_le16(ctx->vnic_entry_size);
6994 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
6995 &req.vnic_pg_size_vnic_lvl,
6996 &req.vnic_page_dir);
6997 }
6998 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT) {
6999 ctx_pg = &ctx->stat_mem;
7000 req.stat_num_entries = cpu_to_le32(ctx->stat_max_entries);
7001 req.stat_entry_size = cpu_to_le16(ctx->stat_entry_size);
7002 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7003 &req.stat_pg_size_stat_lvl,
7004 &req.stat_page_dir);
7005 }
7006 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV) {
7007 ctx_pg = &ctx->mrav_mem;
7008 req.mrav_num_entries = cpu_to_le32(ctx_pg->entries);
7009 if (ctx->mrav_num_entries_units)
7010 flags |=
7011 FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT;
7012 req.mrav_entry_size = cpu_to_le16(ctx->mrav_entry_size);
7013 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7014 &req.mrav_pg_size_mrav_lvl,
7015 &req.mrav_page_dir);
7016 }
7017 if (enables & FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM) {
7018 ctx_pg = &ctx->tim_mem;
7019 req.tim_num_entries = cpu_to_le32(ctx_pg->entries);
7020 req.tim_entry_size = cpu_to_le16(ctx->tim_entry_size);
7021 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem,
7022 &req.tim_pg_size_tim_lvl,
7023 &req.tim_page_dir);
7024 }
7025 for (i = 0, num_entries = &req.tqm_sp_num_entries,
7026 pg_attr = &req.tqm_sp_pg_size_tqm_sp_lvl,
7027 pg_dir = &req.tqm_sp_page_dir,
7028 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP;
7029 i < BNXT_MAX_TQM_RINGS;
7030 i++, num_entries++, pg_attr++, pg_dir++, ena <<= 1) {
7031 if (!(enables & ena))
7032 continue;
7033
7034 req.tqm_entry_size = cpu_to_le16(ctx->tqm_entry_size);
7035 ctx_pg = ctx->tqm_mem[i];
7036 *num_entries = cpu_to_le32(ctx_pg->entries);
7037 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir);
7038 }
7039 req.flags = cpu_to_le32(flags);
7040 return hwrm_send_message(bp, &req, req_len, HWRM_CMD_TIMEOUT);
7041 }
7042
7043 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp,
7044 struct bnxt_ctx_pg_info *ctx_pg)
7045 {
7046 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7047
7048 rmem->page_size = BNXT_PAGE_SIZE;
7049 rmem->pg_arr = ctx_pg->ctx_pg_arr;
7050 rmem->dma_arr = ctx_pg->ctx_dma_arr;
7051 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG;
7052 if (rmem->depth >= 1)
7053 rmem->flags |= BNXT_RMEM_USE_FULL_PAGE_FLAG;
7054 return bnxt_alloc_ring(bp, rmem);
7055 }
7056
7057 static int bnxt_alloc_ctx_pg_tbls(struct bnxt *bp,
7058 struct bnxt_ctx_pg_info *ctx_pg, u32 mem_size,
7059 u8 depth, struct bnxt_mem_init *mem_init)
7060 {
7061 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7062 int rc;
7063
7064 if (!mem_size)
7065 return -EINVAL;
7066
7067 ctx_pg->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7068 if (ctx_pg->nr_pages > MAX_CTX_TOTAL_PAGES) {
7069 ctx_pg->nr_pages = 0;
7070 return -EINVAL;
7071 }
7072 if (ctx_pg->nr_pages > MAX_CTX_PAGES || depth > 1) {
7073 int nr_tbls, i;
7074
7075 rmem->depth = 2;
7076 ctx_pg->ctx_pg_tbl = kcalloc(MAX_CTX_PAGES, sizeof(ctx_pg),
7077 GFP_KERNEL);
7078 if (!ctx_pg->ctx_pg_tbl)
7079 return -ENOMEM;
7080 nr_tbls = DIV_ROUND_UP(ctx_pg->nr_pages, MAX_CTX_PAGES);
7081 rmem->nr_pages = nr_tbls;
7082 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7083 if (rc)
7084 return rc;
7085 for (i = 0; i < nr_tbls; i++) {
7086 struct bnxt_ctx_pg_info *pg_tbl;
7087
7088 pg_tbl = kzalloc(sizeof(*pg_tbl), GFP_KERNEL);
7089 if (!pg_tbl)
7090 return -ENOMEM;
7091 ctx_pg->ctx_pg_tbl[i] = pg_tbl;
7092 rmem = &pg_tbl->ring_mem;
7093 rmem->pg_tbl = ctx_pg->ctx_pg_arr[i];
7094 rmem->pg_tbl_map = ctx_pg->ctx_dma_arr[i];
7095 rmem->depth = 1;
7096 rmem->nr_pages = MAX_CTX_PAGES;
7097 rmem->mem_init = mem_init;
7098 if (i == (nr_tbls - 1)) {
7099 int rem = ctx_pg->nr_pages % MAX_CTX_PAGES;
7100
7101 if (rem)
7102 rmem->nr_pages = rem;
7103 }
7104 rc = bnxt_alloc_ctx_mem_blk(bp, pg_tbl);
7105 if (rc)
7106 break;
7107 }
7108 } else {
7109 rmem->nr_pages = DIV_ROUND_UP(mem_size, BNXT_PAGE_SIZE);
7110 if (rmem->nr_pages > 1 || depth)
7111 rmem->depth = 1;
7112 rmem->mem_init = mem_init;
7113 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg);
7114 }
7115 return rc;
7116 }
7117
7118 static void bnxt_free_ctx_pg_tbls(struct bnxt *bp,
7119 struct bnxt_ctx_pg_info *ctx_pg)
7120 {
7121 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem;
7122
7123 if (rmem->depth > 1 || ctx_pg->nr_pages > MAX_CTX_PAGES ||
7124 ctx_pg->ctx_pg_tbl) {
7125 int i, nr_tbls = rmem->nr_pages;
7126
7127 for (i = 0; i < nr_tbls; i++) {
7128 struct bnxt_ctx_pg_info *pg_tbl;
7129 struct bnxt_ring_mem_info *rmem2;
7130
7131 pg_tbl = ctx_pg->ctx_pg_tbl[i];
7132 if (!pg_tbl)
7133 continue;
7134 rmem2 = &pg_tbl->ring_mem;
7135 bnxt_free_ring(bp, rmem2);
7136 ctx_pg->ctx_pg_arr[i] = NULL;
7137 kfree(pg_tbl);
7138 ctx_pg->ctx_pg_tbl[i] = NULL;
7139 }
7140 kfree(ctx_pg->ctx_pg_tbl);
7141 ctx_pg->ctx_pg_tbl = NULL;
7142 }
7143 bnxt_free_ring(bp, rmem);
7144 ctx_pg->nr_pages = 0;
7145 }
7146
7147 static void bnxt_free_ctx_mem(struct bnxt *bp)
7148 {
7149 struct bnxt_ctx_mem_info *ctx = bp->ctx;
7150 int i;
7151
7152 if (!ctx)
7153 return;
7154
7155 if (ctx->tqm_mem[0]) {
7156 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++)
7157 bnxt_free_ctx_pg_tbls(bp, ctx->tqm_mem[i]);
7158 kfree(ctx->tqm_mem[0]);
7159 ctx->tqm_mem[0] = NULL;
7160 }
7161
7162 bnxt_free_ctx_pg_tbls(bp, &ctx->tim_mem);
7163 bnxt_free_ctx_pg_tbls(bp, &ctx->mrav_mem);
7164 bnxt_free_ctx_pg_tbls(bp, &ctx->stat_mem);
7165 bnxt_free_ctx_pg_tbls(bp, &ctx->vnic_mem);
7166 bnxt_free_ctx_pg_tbls(bp, &ctx->cq_mem);
7167 bnxt_free_ctx_pg_tbls(bp, &ctx->srq_mem);
7168 bnxt_free_ctx_pg_tbls(bp, &ctx->qp_mem);
7169 ctx->flags &= ~BNXT_CTX_FLAG_INITED;
7170 }
7171
7172 static int bnxt_alloc_ctx_mem(struct bnxt *bp)
7173 {
7174 struct bnxt_ctx_pg_info *ctx_pg;
7175 struct bnxt_ctx_mem_info *ctx;
7176 struct bnxt_mem_init *init;
7177 u32 mem_size, ena, entries;
7178 u32 entries_sp, min;
7179 u32 num_mr, num_ah;
7180 u32 extra_srqs = 0;
7181 u32 extra_qps = 0;
7182 u8 pg_lvl = 1;
7183 int i, rc;
7184
7185 rc = bnxt_hwrm_func_backing_store_qcaps(bp);
7186 if (rc) {
7187 netdev_err(bp->dev, "Failed querying context mem capability, rc = %d.\n",
7188 rc);
7189 return rc;
7190 }
7191 ctx = bp->ctx;
7192 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED))
7193 return 0;
7194
7195 if ((bp->flags & BNXT_FLAG_ROCE_CAP) && !is_kdump_kernel()) {
7196 pg_lvl = 2;
7197 extra_qps = 65536;
7198 extra_srqs = 8192;
7199 }
7200
7201 ctx_pg = &ctx->qp_mem;
7202 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries +
7203 extra_qps;
7204 if (ctx->qp_entry_size) {
7205 mem_size = ctx->qp_entry_size * ctx_pg->entries;
7206 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_QP];
7207 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7208 if (rc)
7209 return rc;
7210 }
7211
7212 ctx_pg = &ctx->srq_mem;
7213 ctx_pg->entries = ctx->srq_max_l2_entries + extra_srqs;
7214 if (ctx->srq_entry_size) {
7215 mem_size = ctx->srq_entry_size * ctx_pg->entries;
7216 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_SRQ];
7217 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7218 if (rc)
7219 return rc;
7220 }
7221
7222 ctx_pg = &ctx->cq_mem;
7223 ctx_pg->entries = ctx->cq_max_l2_entries + extra_qps * 2;
7224 if (ctx->cq_entry_size) {
7225 mem_size = ctx->cq_entry_size * ctx_pg->entries;
7226 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_CQ];
7227 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, pg_lvl, init);
7228 if (rc)
7229 return rc;
7230 }
7231
7232 ctx_pg = &ctx->vnic_mem;
7233 ctx_pg->entries = ctx->vnic_max_vnic_entries +
7234 ctx->vnic_max_ring_table_entries;
7235 if (ctx->vnic_entry_size) {
7236 mem_size = ctx->vnic_entry_size * ctx_pg->entries;
7237 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_VNIC];
7238 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7239 if (rc)
7240 return rc;
7241 }
7242
7243 ctx_pg = &ctx->stat_mem;
7244 ctx_pg->entries = ctx->stat_max_entries;
7245 if (ctx->stat_entry_size) {
7246 mem_size = ctx->stat_entry_size * ctx_pg->entries;
7247 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_STAT];
7248 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, init);
7249 if (rc)
7250 return rc;
7251 }
7252
7253 ena = 0;
7254 if (!(bp->flags & BNXT_FLAG_ROCE_CAP))
7255 goto skip_rdma;
7256
7257 ctx_pg = &ctx->mrav_mem;
7258 /* 128K extra is needed to accommodate static AH context
7259 * allocation by f/w.
7260 */
7261 num_mr = 1024 * 256;
7262 num_ah = 1024 * 128;
7263 ctx_pg->entries = num_mr + num_ah;
7264 if (ctx->mrav_entry_size) {
7265 mem_size = ctx->mrav_entry_size * ctx_pg->entries;
7266 init = &ctx->mem_init[BNXT_CTX_MEM_INIT_MRAV];
7267 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 2, init);
7268 if (rc)
7269 return rc;
7270 }
7271 ena = FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
7272 if (ctx->mrav_num_entries_units)
7273 ctx_pg->entries =
7274 ((num_mr / ctx->mrav_num_entries_units) << 16) |
7275 (num_ah / ctx->mrav_num_entries_units);
7276
7277 ctx_pg = &ctx->tim_mem;
7278 ctx_pg->entries = ctx->qp_mem.entries;
7279 if (ctx->tim_entry_size) {
7280 mem_size = ctx->tim_entry_size * ctx_pg->entries;
7281 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1, NULL);
7282 if (rc)
7283 return rc;
7284 }
7285 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM;
7286
7287 skip_rdma:
7288 min = ctx->tqm_min_entries_per_ring;
7289 entries_sp = ctx->vnic_max_vnic_entries + ctx->qp_max_l2_entries +
7290 2 * (extra_qps + ctx->qp_min_qp1_entries) + min;
7291 entries_sp = roundup(entries_sp, ctx->tqm_entries_multiple);
7292 entries = ctx->qp_max_l2_entries + extra_qps + ctx->qp_min_qp1_entries;
7293 entries = roundup(entries, ctx->tqm_entries_multiple);
7294 entries = clamp_t(u32, entries, min, ctx->tqm_max_entries_per_ring);
7295 for (i = 0; i < ctx->tqm_fp_rings_count + 1; i++) {
7296 ctx_pg = ctx->tqm_mem[i];
7297 ctx_pg->entries = i ? entries : entries_sp;
7298 if (ctx->tqm_entry_size) {
7299 mem_size = ctx->tqm_entry_size * ctx_pg->entries;
7300 rc = bnxt_alloc_ctx_pg_tbls(bp, ctx_pg, mem_size, 1,
7301 NULL);
7302 if (rc)
7303 return rc;
7304 }
7305 ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP << i;
7306 }
7307 ena |= FUNC_BACKING_STORE_CFG_REQ_DFLT_ENABLES;
7308 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena);
7309 if (rc) {
7310 netdev_err(bp->dev, "Failed configuring context mem, rc = %d.\n",
7311 rc);
7312 return rc;
7313 }
7314 ctx->flags |= BNXT_CTX_FLAG_INITED;
7315 return 0;
7316 }
7317
7318 int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all)
7319 {
7320 struct hwrm_func_resource_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7321 struct hwrm_func_resource_qcaps_input req = {0};
7322 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7323 int rc;
7324
7325 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESOURCE_QCAPS, -1, -1);
7326 req.fid = cpu_to_le16(0xffff);
7327
7328 mutex_lock(&bp->hwrm_cmd_lock);
7329 rc = _hwrm_send_message_silent(bp, &req, sizeof(req),
7330 HWRM_CMD_TIMEOUT);
7331 if (rc)
7332 goto hwrm_func_resc_qcaps_exit;
7333
7334 hw_resc->max_tx_sch_inputs = le16_to_cpu(resp->max_tx_scheduler_inputs);
7335 if (!all)
7336 goto hwrm_func_resc_qcaps_exit;
7337
7338 hw_resc->min_rsscos_ctxs = le16_to_cpu(resp->min_rsscos_ctx);
7339 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7340 hw_resc->min_cp_rings = le16_to_cpu(resp->min_cmpl_rings);
7341 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7342 hw_resc->min_tx_rings = le16_to_cpu(resp->min_tx_rings);
7343 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7344 hw_resc->min_rx_rings = le16_to_cpu(resp->min_rx_rings);
7345 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7346 hw_resc->min_hw_ring_grps = le16_to_cpu(resp->min_hw_ring_grps);
7347 hw_resc->max_hw_ring_grps = le16_to_cpu(resp->max_hw_ring_grps);
7348 hw_resc->min_l2_ctxs = le16_to_cpu(resp->min_l2_ctxs);
7349 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7350 hw_resc->min_vnics = le16_to_cpu(resp->min_vnics);
7351 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7352 hw_resc->min_stat_ctxs = le16_to_cpu(resp->min_stat_ctx);
7353 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7354
7355 if (bp->flags & BNXT_FLAG_CHIP_P5) {
7356 u16 max_msix = le16_to_cpu(resp->max_msix);
7357
7358 hw_resc->max_nqs = max_msix;
7359 hw_resc->max_hw_ring_grps = hw_resc->max_rx_rings;
7360 }
7361
7362 if (BNXT_PF(bp)) {
7363 struct bnxt_pf_info *pf = &bp->pf;
7364
7365 pf->vf_resv_strategy =
7366 le16_to_cpu(resp->vf_reservation_strategy);
7367 if (pf->vf_resv_strategy > BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC)
7368 pf->vf_resv_strategy = BNXT_VF_RESV_STRATEGY_MAXIMAL;
7369 }
7370 hwrm_func_resc_qcaps_exit:
7371 mutex_unlock(&bp->hwrm_cmd_lock);
7372 return rc;
7373 }
7374
7375 static int __bnxt_hwrm_func_qcaps(struct bnxt *bp)
7376 {
7377 int rc = 0;
7378 struct hwrm_func_qcaps_input req = {0};
7379 struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
7380 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
7381 u32 flags, flags_ext;
7382
7383 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
7384 req.fid = cpu_to_le16(0xffff);
7385
7386 mutex_lock(&bp->hwrm_cmd_lock);
7387 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7388 if (rc)
7389 goto hwrm_func_qcaps_exit;
7390
7391 flags = le32_to_cpu(resp->flags);
7392 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED)
7393 bp->flags |= BNXT_FLAG_ROCEV1_CAP;
7394 if (flags & FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED)
7395 bp->flags |= BNXT_FLAG_ROCEV2_CAP;
7396 if (flags & FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED)
7397 bp->fw_cap |= BNXT_FW_CAP_PCIE_STATS_SUPPORTED;
7398 if (flags & FUNC_QCAPS_RESP_FLAGS_HOT_RESET_CAPABLE)
7399 bp->fw_cap |= BNXT_FW_CAP_HOT_RESET;
7400 if (flags & FUNC_QCAPS_RESP_FLAGS_EXT_STATS_SUPPORTED)
7401 bp->fw_cap |= BNXT_FW_CAP_EXT_STATS_SUPPORTED;
7402 if (flags & FUNC_QCAPS_RESP_FLAGS_ERROR_RECOVERY_CAPABLE)
7403 bp->fw_cap |= BNXT_FW_CAP_ERROR_RECOVERY;
7404 if (flags & FUNC_QCAPS_RESP_FLAGS_ERR_RECOVER_RELOAD)
7405 bp->fw_cap |= BNXT_FW_CAP_ERR_RECOVER_RELOAD;
7406 if (!(flags & FUNC_QCAPS_RESP_FLAGS_VLAN_ACCELERATION_TX_DISABLED))
7407 bp->fw_cap |= BNXT_FW_CAP_VLAN_TX_INSERT;
7408
7409 flags_ext = le32_to_cpu(resp->flags_ext);
7410 if (flags_ext & FUNC_QCAPS_RESP_FLAGS_EXT_EXT_HW_STATS_SUPPORTED)
7411 bp->fw_cap |= BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED;
7412
7413 bp->tx_push_thresh = 0;
7414 if ((flags & FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED) &&
7415 BNXT_FW_MAJ(bp) > 217)
7416 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
7417
7418 hw_resc->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
7419 hw_resc->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
7420 hw_resc->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
7421 hw_resc->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
7422 hw_resc->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
7423 if (!hw_resc->max_hw_ring_grps)
7424 hw_resc->max_hw_ring_grps = hw_resc->max_tx_rings;
7425 hw_resc->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
7426 hw_resc->max_vnics = le16_to_cpu(resp->max_vnics);
7427 hw_resc->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
7428
7429 if (BNXT_PF(bp)) {
7430 struct bnxt_pf_info *pf = &bp->pf;
7431
7432 pf->fw_fid = le16_to_cpu(resp->fid);
7433 pf->port_id = le16_to_cpu(resp->port_id);
7434 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
7435 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
7436 pf->max_vfs = le16_to_cpu(resp->max_vfs);
7437 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
7438 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
7439 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
7440 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
7441 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
7442 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
7443 bp->flags &= ~BNXT_FLAG_WOL_CAP;
7444 if (flags & FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED)
7445 bp->flags |= BNXT_FLAG_WOL_CAP;
7446 } else {
7447 #ifdef CONFIG_BNXT_SRIOV
7448 struct bnxt_vf_info *vf = &bp->vf;
7449
7450 vf->fw_fid = le16_to_cpu(resp->fid);
7451 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
7452 #endif
7453 }
7454
7455 hwrm_func_qcaps_exit:
7456 mutex_unlock(&bp->hwrm_cmd_lock);
7457 return rc;
7458 }
7459
7460 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp);
7461
7462 static int bnxt_hwrm_func_qcaps(struct bnxt *bp)
7463 {
7464 int rc;
7465
7466 rc = __bnxt_hwrm_func_qcaps(bp);
7467 if (rc)
7468 return rc;
7469 rc = bnxt_hwrm_queue_qportcfg(bp);
7470 if (rc) {
7471 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %d\n", rc);
7472 return rc;
7473 }
7474 if (bp->hwrm_spec_code >= 0x10803) {
7475 rc = bnxt_alloc_ctx_mem(bp);
7476 if (rc)
7477 return rc;
7478 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
7479 if (!rc)
7480 bp->fw_cap |= BNXT_FW_CAP_NEW_RM;
7481 }
7482 return 0;
7483 }
7484
7485 static int bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(struct bnxt *bp)
7486 {
7487 struct hwrm_cfa_adv_flow_mgnt_qcaps_input req = {0};
7488 struct hwrm_cfa_adv_flow_mgnt_qcaps_output *resp;
7489 int rc = 0;
7490 u32 flags;
7491
7492 if (!(bp->fw_cap & BNXT_FW_CAP_CFA_ADV_FLOW))
7493 return 0;
7494
7495 resp = bp->hwrm_cmd_resp_addr;
7496 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_ADV_FLOW_MGNT_QCAPS, -1, -1);
7497
7498 mutex_lock(&bp->hwrm_cmd_lock);
7499 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7500 if (rc)
7501 goto hwrm_cfa_adv_qcaps_exit;
7502
7503 flags = le32_to_cpu(resp->flags);
7504 if (flags &
7505 CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED)
7506 bp->fw_cap |= BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2;
7507
7508 hwrm_cfa_adv_qcaps_exit:
7509 mutex_unlock(&bp->hwrm_cmd_lock);
7510 return rc;
7511 }
7512
7513 static int __bnxt_alloc_fw_health(struct bnxt *bp)
7514 {
7515 if (bp->fw_health)
7516 return 0;
7517
7518 bp->fw_health = kzalloc(sizeof(*bp->fw_health), GFP_KERNEL);
7519 if (!bp->fw_health)
7520 return -ENOMEM;
7521
7522 return 0;
7523 }
7524
7525 static int bnxt_alloc_fw_health(struct bnxt *bp)
7526 {
7527 int rc;
7528
7529 if (!(bp->fw_cap & BNXT_FW_CAP_HOT_RESET) &&
7530 !(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7531 return 0;
7532
7533 rc = __bnxt_alloc_fw_health(bp);
7534 if (rc) {
7535 bp->fw_cap &= ~BNXT_FW_CAP_HOT_RESET;
7536 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7537 return rc;
7538 }
7539
7540 return 0;
7541 }
7542
7543 static void __bnxt_map_fw_health_reg(struct bnxt *bp, u32 reg)
7544 {
7545 writel(reg & BNXT_GRC_BASE_MASK, bp->bar0 +
7546 BNXT_GRCPF_REG_WINDOW_BASE_OUT +
7547 BNXT_FW_HEALTH_WIN_MAP_OFF);
7548 }
7549
7550 bool bnxt_is_fw_healthy(struct bnxt *bp)
7551 {
7552 if (bp->fw_health && bp->fw_health->status_reliable) {
7553 u32 fw_status;
7554
7555 fw_status = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
7556 if (fw_status && !BNXT_FW_IS_HEALTHY(fw_status))
7557 return false;
7558 }
7559
7560 return true;
7561 }
7562
7563 static void bnxt_inv_fw_health_reg(struct bnxt *bp)
7564 {
7565 struct bnxt_fw_health *fw_health = bp->fw_health;
7566 u32 reg_type;
7567
7568 if (!fw_health || !fw_health->status_reliable)
7569 return;
7570
7571 reg_type = BNXT_FW_HEALTH_REG_TYPE(fw_health->regs[BNXT_FW_HEALTH_REG]);
7572 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC)
7573 fw_health->status_reliable = false;
7574 }
7575
7576 static void bnxt_try_map_fw_health_reg(struct bnxt *bp)
7577 {
7578 void __iomem *hs;
7579 u32 status_loc;
7580 u32 reg_type;
7581 u32 sig;
7582
7583 if (bp->fw_health)
7584 bp->fw_health->status_reliable = false;
7585
7586 __bnxt_map_fw_health_reg(bp, HCOMM_STATUS_STRUCT_LOC);
7587 hs = bp->bar0 + BNXT_FW_HEALTH_WIN_OFF(HCOMM_STATUS_STRUCT_LOC);
7588
7589 sig = readl(hs + offsetof(struct hcomm_status, sig_ver));
7590 if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) {
7591 if (!bp->chip_num) {
7592 __bnxt_map_fw_health_reg(bp, BNXT_GRC_REG_BASE);
7593 bp->chip_num = readl(bp->bar0 +
7594 BNXT_FW_HEALTH_WIN_BASE +
7595 BNXT_GRC_REG_CHIP_NUM);
7596 }
7597 if (!BNXT_CHIP_P5(bp))
7598 return;
7599
7600 status_loc = BNXT_GRC_REG_STATUS_P5 |
7601 BNXT_FW_HEALTH_REG_TYPE_BAR0;
7602 } else {
7603 status_loc = readl(hs + offsetof(struct hcomm_status,
7604 fw_status_loc));
7605 }
7606
7607 if (__bnxt_alloc_fw_health(bp)) {
7608 netdev_warn(bp->dev, "no memory for firmware status checks\n");
7609 return;
7610 }
7611
7612 bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc;
7613 reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc);
7614 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) {
7615 __bnxt_map_fw_health_reg(bp, status_loc);
7616 bp->fw_health->mapped_regs[BNXT_FW_HEALTH_REG] =
7617 BNXT_FW_HEALTH_WIN_OFF(status_loc);
7618 }
7619
7620 bp->fw_health->status_reliable = true;
7621 }
7622
7623 static int bnxt_map_fw_health_regs(struct bnxt *bp)
7624 {
7625 struct bnxt_fw_health *fw_health = bp->fw_health;
7626 u32 reg_base = 0xffffffff;
7627 int i;
7628
7629 bp->fw_health->status_reliable = false;
7630 /* Only pre-map the monitoring GRC registers using window 3 */
7631 for (i = 0; i < 4; i++) {
7632 u32 reg = fw_health->regs[i];
7633
7634 if (BNXT_FW_HEALTH_REG_TYPE(reg) != BNXT_FW_HEALTH_REG_TYPE_GRC)
7635 continue;
7636 if (reg_base == 0xffffffff)
7637 reg_base = reg & BNXT_GRC_BASE_MASK;
7638 if ((reg & BNXT_GRC_BASE_MASK) != reg_base)
7639 return -ERANGE;
7640 fw_health->mapped_regs[i] = BNXT_FW_HEALTH_WIN_OFF(reg);
7641 }
7642 bp->fw_health->status_reliable = true;
7643 if (reg_base == 0xffffffff)
7644 return 0;
7645
7646 __bnxt_map_fw_health_reg(bp, reg_base);
7647 return 0;
7648 }
7649
7650 static int bnxt_hwrm_error_recovery_qcfg(struct bnxt *bp)
7651 {
7652 struct hwrm_error_recovery_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
7653 struct bnxt_fw_health *fw_health = bp->fw_health;
7654 struct hwrm_error_recovery_qcfg_input req = {0};
7655 int rc, i;
7656
7657 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY))
7658 return 0;
7659
7660 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_ERROR_RECOVERY_QCFG, -1, -1);
7661 mutex_lock(&bp->hwrm_cmd_lock);
7662 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7663 if (rc)
7664 goto err_recovery_out;
7665 fw_health->flags = le32_to_cpu(resp->flags);
7666 if ((fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) &&
7667 !(bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL)) {
7668 rc = -EINVAL;
7669 goto err_recovery_out;
7670 }
7671 fw_health->polling_dsecs = le32_to_cpu(resp->driver_polling_freq);
7672 fw_health->master_func_wait_dsecs =
7673 le32_to_cpu(resp->master_func_wait_period);
7674 fw_health->normal_func_wait_dsecs =
7675 le32_to_cpu(resp->normal_func_wait_period);
7676 fw_health->post_reset_wait_dsecs =
7677 le32_to_cpu(resp->master_func_wait_period_after_reset);
7678 fw_health->post_reset_max_wait_dsecs =
7679 le32_to_cpu(resp->max_bailout_time_after_reset);
7680 fw_health->regs[BNXT_FW_HEALTH_REG] =
7681 le32_to_cpu(resp->fw_health_status_reg);
7682 fw_health->regs[BNXT_FW_HEARTBEAT_REG] =
7683 le32_to_cpu(resp->fw_heartbeat_reg);
7684 fw_health->regs[BNXT_FW_RESET_CNT_REG] =
7685 le32_to_cpu(resp->fw_reset_cnt_reg);
7686 fw_health->regs[BNXT_FW_RESET_INPROG_REG] =
7687 le32_to_cpu(resp->reset_inprogress_reg);
7688 fw_health->fw_reset_inprog_reg_mask =
7689 le32_to_cpu(resp->reset_inprogress_reg_mask);
7690 fw_health->fw_reset_seq_cnt = resp->reg_array_cnt;
7691 if (fw_health->fw_reset_seq_cnt >= 16) {
7692 rc = -EINVAL;
7693 goto err_recovery_out;
7694 }
7695 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++) {
7696 fw_health->fw_reset_seq_regs[i] =
7697 le32_to_cpu(resp->reset_reg[i]);
7698 fw_health->fw_reset_seq_vals[i] =
7699 le32_to_cpu(resp->reset_reg_val[i]);
7700 fw_health->fw_reset_seq_delay_msec[i] =
7701 resp->delay_after_reset[i];
7702 }
7703 err_recovery_out:
7704 mutex_unlock(&bp->hwrm_cmd_lock);
7705 if (!rc)
7706 rc = bnxt_map_fw_health_regs(bp);
7707 if (rc)
7708 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY;
7709 return rc;
7710 }
7711
7712 static int bnxt_hwrm_func_reset(struct bnxt *bp)
7713 {
7714 struct hwrm_func_reset_input req = {0};
7715
7716 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
7717 req.enables = 0;
7718
7719 return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
7720 }
7721
7722 static void bnxt_nvm_cfg_ver_get(struct bnxt *bp)
7723 {
7724 struct hwrm_nvm_get_dev_info_output nvm_info;
7725
7726 if (!bnxt_hwrm_nvm_get_dev_info(bp, &nvm_info))
7727 snprintf(bp->nvm_cfg_ver, FW_VER_STR_LEN, "%d.%d.%d",
7728 nvm_info.nvm_cfg_ver_maj, nvm_info.nvm_cfg_ver_min,
7729 nvm_info.nvm_cfg_ver_upd);
7730 }
7731
7732 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
7733 {
7734 int rc = 0;
7735 struct hwrm_queue_qportcfg_input req = {0};
7736 struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
7737 u8 i, j, *qptr;
7738 bool no_rdma;
7739
7740 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
7741
7742 mutex_lock(&bp->hwrm_cmd_lock);
7743 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7744 if (rc)
7745 goto qportcfg_exit;
7746
7747 if (!resp->max_configurable_queues) {
7748 rc = -EINVAL;
7749 goto qportcfg_exit;
7750 }
7751 bp->max_tc = resp->max_configurable_queues;
7752 bp->max_lltc = resp->max_configurable_lossless_queues;
7753 if (bp->max_tc > BNXT_MAX_QUEUE)
7754 bp->max_tc = BNXT_MAX_QUEUE;
7755
7756 no_rdma = !(bp->flags & BNXT_FLAG_ROCE_CAP);
7757 qptr = &resp->queue_id0;
7758 for (i = 0, j = 0; i < bp->max_tc; i++) {
7759 bp->q_info[j].queue_id = *qptr;
7760 bp->q_ids[i] = *qptr++;
7761 bp->q_info[j].queue_profile = *qptr++;
7762 bp->tc_to_qidx[j] = j;
7763 if (!BNXT_CNPQ(bp->q_info[j].queue_profile) ||
7764 (no_rdma && BNXT_PF(bp)))
7765 j++;
7766 }
7767 bp->max_q = bp->max_tc;
7768 bp->max_tc = max_t(u8, j, 1);
7769
7770 if (resp->queue_cfg_info & QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG)
7771 bp->max_tc = 1;
7772
7773 if (bp->max_lltc > bp->max_tc)
7774 bp->max_lltc = bp->max_tc;
7775
7776 qportcfg_exit:
7777 mutex_unlock(&bp->hwrm_cmd_lock);
7778 return rc;
7779 }
7780
7781 static int __bnxt_hwrm_ver_get(struct bnxt *bp, bool silent)
7782 {
7783 struct hwrm_ver_get_input req = {0};
7784 int rc;
7785
7786 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
7787 req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
7788 req.hwrm_intf_min = HWRM_VERSION_MINOR;
7789 req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
7790
7791 rc = bnxt_hwrm_do_send_msg(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT,
7792 silent);
7793 return rc;
7794 }
7795
7796 static int bnxt_hwrm_ver_get(struct bnxt *bp)
7797 {
7798 struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
7799 u16 fw_maj, fw_min, fw_bld, fw_rsv;
7800 u32 dev_caps_cfg, hwrm_ver;
7801 int rc, len;
7802
7803 bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
7804 mutex_lock(&bp->hwrm_cmd_lock);
7805 rc = __bnxt_hwrm_ver_get(bp, false);
7806 if (rc)
7807 goto hwrm_ver_get_exit;
7808
7809 memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
7810
7811 bp->hwrm_spec_code = resp->hwrm_intf_maj_8b << 16 |
7812 resp->hwrm_intf_min_8b << 8 |
7813 resp->hwrm_intf_upd_8b;
7814 if (resp->hwrm_intf_maj_8b < 1) {
7815 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
7816 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
7817 resp->hwrm_intf_upd_8b);
7818 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
7819 }
7820
7821 hwrm_ver = HWRM_VERSION_MAJOR << 16 | HWRM_VERSION_MINOR << 8 |
7822 HWRM_VERSION_UPDATE;
7823
7824 if (bp->hwrm_spec_code > hwrm_ver)
7825 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
7826 HWRM_VERSION_MAJOR, HWRM_VERSION_MINOR,
7827 HWRM_VERSION_UPDATE);
7828 else
7829 snprintf(bp->hwrm_ver_supp, FW_VER_STR_LEN, "%d.%d.%d",
7830 resp->hwrm_intf_maj_8b, resp->hwrm_intf_min_8b,
7831 resp->hwrm_intf_upd_8b);
7832
7833 fw_maj = le16_to_cpu(resp->hwrm_fw_major);
7834 if (bp->hwrm_spec_code > 0x10803 && fw_maj) {
7835 fw_min = le16_to_cpu(resp->hwrm_fw_minor);
7836 fw_bld = le16_to_cpu(resp->hwrm_fw_build);
7837 fw_rsv = le16_to_cpu(resp->hwrm_fw_patch);
7838 len = FW_VER_STR_LEN;
7839 } else {
7840 fw_maj = resp->hwrm_fw_maj_8b;
7841 fw_min = resp->hwrm_fw_min_8b;
7842 fw_bld = resp->hwrm_fw_bld_8b;
7843 fw_rsv = resp->hwrm_fw_rsvd_8b;
7844 len = BC_HWRM_STR_LEN;
7845 }
7846 bp->fw_ver_code = BNXT_FW_VER_CODE(fw_maj, fw_min, fw_bld, fw_rsv);
7847 snprintf(bp->fw_ver_str, len, "%d.%d.%d.%d", fw_maj, fw_min, fw_bld,
7848 fw_rsv);
7849
7850 if (strlen(resp->active_pkg_name)) {
7851 int fw_ver_len = strlen(bp->fw_ver_str);
7852
7853 snprintf(bp->fw_ver_str + fw_ver_len,
7854 FW_VER_STR_LEN - fw_ver_len - 1, "/pkg %s",
7855 resp->active_pkg_name);
7856 bp->fw_cap |= BNXT_FW_CAP_PKG_VER;
7857 }
7858
7859 bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
7860 if (!bp->hwrm_cmd_timeout)
7861 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
7862
7863 if (resp->hwrm_intf_maj_8b >= 1) {
7864 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
7865 bp->hwrm_max_ext_req_len = le16_to_cpu(resp->max_ext_req_len);
7866 }
7867 if (bp->hwrm_max_ext_req_len < HWRM_MAX_REQ_LEN)
7868 bp->hwrm_max_ext_req_len = HWRM_MAX_REQ_LEN;
7869
7870 bp->chip_num = le16_to_cpu(resp->chip_num);
7871 bp->chip_rev = resp->chip_rev;
7872 if (bp->chip_num == CHIP_NUM_58700 && !resp->chip_rev &&
7873 !resp->chip_metal)
7874 bp->flags |= BNXT_FLAG_CHIP_NITRO_A0;
7875
7876 dev_caps_cfg = le32_to_cpu(resp->dev_caps_cfg);
7877 if ((dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED) &&
7878 (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED))
7879 bp->fw_cap |= BNXT_FW_CAP_SHORT_CMD;
7880
7881 if (dev_caps_cfg & VER_GET_RESP_DEV_CAPS_CFG_KONG_MB_CHNL_SUPPORTED)
7882 bp->fw_cap |= BNXT_FW_CAP_KONG_MB_CHNL;
7883
7884 if (dev_caps_cfg &
7885 VER_GET_RESP_DEV_CAPS_CFG_FLOW_HANDLE_64BIT_SUPPORTED)
7886 bp->fw_cap |= BNXT_FW_CAP_OVS_64BIT_HANDLE;
7887
7888 if (dev_caps_cfg &
7889 VER_GET_RESP_DEV_CAPS_CFG_TRUSTED_VF_SUPPORTED)
7890 bp->fw_cap |= BNXT_FW_CAP_TRUSTED_VF;
7891
7892 if (dev_caps_cfg &
7893 VER_GET_RESP_DEV_CAPS_CFG_CFA_ADV_FLOW_MGNT_SUPPORTED)
7894 bp->fw_cap |= BNXT_FW_CAP_CFA_ADV_FLOW;
7895
7896 hwrm_ver_get_exit:
7897 mutex_unlock(&bp->hwrm_cmd_lock);
7898 return rc;
7899 }
7900
7901 int bnxt_hwrm_fw_set_time(struct bnxt *bp)
7902 {
7903 struct hwrm_fw_set_time_input req = {0};
7904 struct tm tm;
7905 time64_t now = ktime_get_real_seconds();
7906
7907 if ((BNXT_VF(bp) && bp->hwrm_spec_code < 0x10901) ||
7908 bp->hwrm_spec_code < 0x10400)
7909 return -EOPNOTSUPP;
7910
7911 time64_to_tm(now, 0, &tm);
7912 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_SET_TIME, -1, -1);
7913 req.year = cpu_to_le16(1900 + tm.tm_year);
7914 req.month = 1 + tm.tm_mon;
7915 req.day = tm.tm_mday;
7916 req.hour = tm.tm_hour;
7917 req.minute = tm.tm_min;
7918 req.second = tm.tm_sec;
7919 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
7920 }
7921
7922 static void bnxt_add_one_ctr(u64 hw, u64 *sw, u64 mask)
7923 {
7924 u64 sw_tmp;
7925
7926 hw &= mask;
7927 sw_tmp = (*sw & ~mask) | hw;
7928 if (hw < (*sw & mask))
7929 sw_tmp += mask + 1;
7930 WRITE_ONCE(*sw, sw_tmp);
7931 }
7932
7933 static void __bnxt_accumulate_stats(__le64 *hw_stats, u64 *sw_stats, u64 *masks,
7934 int count, bool ignore_zero)
7935 {
7936 int i;
7937
7938 for (i = 0; i < count; i++) {
7939 u64 hw = le64_to_cpu(READ_ONCE(hw_stats[i]));
7940
7941 if (ignore_zero && !hw)
7942 continue;
7943
7944 if (masks[i] == -1ULL)
7945 sw_stats[i] = hw;
7946 else
7947 bnxt_add_one_ctr(hw, &sw_stats[i], masks[i]);
7948 }
7949 }
7950
7951 static void bnxt_accumulate_stats(struct bnxt_stats_mem *stats)
7952 {
7953 if (!stats->hw_stats)
7954 return;
7955
7956 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
7957 stats->hw_masks, stats->len / 8, false);
7958 }
7959
7960 static void bnxt_accumulate_all_stats(struct bnxt *bp)
7961 {
7962 struct bnxt_stats_mem *ring0_stats;
7963 bool ignore_zero = false;
7964 int i;
7965
7966 /* Chip bug. Counter intermittently becomes 0. */
7967 if (bp->flags & BNXT_FLAG_CHIP_P5)
7968 ignore_zero = true;
7969
7970 for (i = 0; i < bp->cp_nr_rings; i++) {
7971 struct bnxt_napi *bnapi = bp->bnapi[i];
7972 struct bnxt_cp_ring_info *cpr;
7973 struct bnxt_stats_mem *stats;
7974
7975 cpr = &bnapi->cp_ring;
7976 stats = &cpr->stats;
7977 if (!i)
7978 ring0_stats = stats;
7979 __bnxt_accumulate_stats(stats->hw_stats, stats->sw_stats,
7980 ring0_stats->hw_masks,
7981 ring0_stats->len / 8, ignore_zero);
7982 }
7983 if (bp->flags & BNXT_FLAG_PORT_STATS) {
7984 struct bnxt_stats_mem *stats = &bp->port_stats;
7985 __le64 *hw_stats = stats->hw_stats;
7986 u64 *sw_stats = stats->sw_stats;
7987 u64 *masks = stats->hw_masks;
7988 int cnt;
7989
7990 cnt = sizeof(struct rx_port_stats) / 8;
7991 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
7992
7993 hw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
7994 sw_stats += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
7995 masks += BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
7996 cnt = sizeof(struct tx_port_stats) / 8;
7997 __bnxt_accumulate_stats(hw_stats, sw_stats, masks, cnt, false);
7998 }
7999 if (bp->flags & BNXT_FLAG_PORT_STATS_EXT) {
8000 bnxt_accumulate_stats(&bp->rx_port_stats_ext);
8001 bnxt_accumulate_stats(&bp->tx_port_stats_ext);
8002 }
8003 }
8004
8005 static int bnxt_hwrm_port_qstats(struct bnxt *bp, u8 flags)
8006 {
8007 struct bnxt_pf_info *pf = &bp->pf;
8008 struct hwrm_port_qstats_input req = {0};
8009
8010 if (!(bp->flags & BNXT_FLAG_PORT_STATS))
8011 return 0;
8012
8013 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8014 return -EOPNOTSUPP;
8015
8016 req.flags = flags;
8017 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
8018 req.port_id = cpu_to_le16(pf->port_id);
8019 req.tx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map +
8020 BNXT_TX_PORT_STATS_BYTE_OFFSET);
8021 req.rx_stat_host_addr = cpu_to_le64(bp->port_stats.hw_stats_map);
8022 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8023 }
8024
8025 static int bnxt_hwrm_port_qstats_ext(struct bnxt *bp, u8 flags)
8026 {
8027 struct hwrm_port_qstats_ext_output *resp = bp->hwrm_cmd_resp_addr;
8028 struct hwrm_queue_pri2cos_qcfg_input req2 = {0};
8029 struct hwrm_port_qstats_ext_input req = {0};
8030 struct bnxt_pf_info *pf = &bp->pf;
8031 u32 tx_stat_size;
8032 int rc;
8033
8034 if (!(bp->flags & BNXT_FLAG_PORT_STATS_EXT))
8035 return 0;
8036
8037 if (flags && !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED))
8038 return -EOPNOTSUPP;
8039
8040 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS_EXT, -1, -1);
8041 req.flags = flags;
8042 req.port_id = cpu_to_le16(pf->port_id);
8043 req.rx_stat_size = cpu_to_le16(sizeof(struct rx_port_stats_ext));
8044 req.rx_stat_host_addr = cpu_to_le64(bp->rx_port_stats_ext.hw_stats_map);
8045 tx_stat_size = bp->tx_port_stats_ext.hw_stats ?
8046 sizeof(struct tx_port_stats_ext) : 0;
8047 req.tx_stat_size = cpu_to_le16(tx_stat_size);
8048 req.tx_stat_host_addr = cpu_to_le64(bp->tx_port_stats_ext.hw_stats_map);
8049 mutex_lock(&bp->hwrm_cmd_lock);
8050 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8051 if (!rc) {
8052 bp->fw_rx_stats_ext_size = le16_to_cpu(resp->rx_stat_size) / 8;
8053 bp->fw_tx_stats_ext_size = tx_stat_size ?
8054 le16_to_cpu(resp->tx_stat_size) / 8 : 0;
8055 } else {
8056 bp->fw_rx_stats_ext_size = 0;
8057 bp->fw_tx_stats_ext_size = 0;
8058 }
8059 if (flags)
8060 goto qstats_done;
8061
8062 if (bp->fw_tx_stats_ext_size <=
8063 offsetof(struct tx_port_stats_ext, pfc_pri0_tx_duration_us) / 8) {
8064 mutex_unlock(&bp->hwrm_cmd_lock);
8065 bp->pri2cos_valid = 0;
8066 return rc;
8067 }
8068
8069 bnxt_hwrm_cmd_hdr_init(bp, &req2, HWRM_QUEUE_PRI2COS_QCFG, -1, -1);
8070 req2.flags = cpu_to_le32(QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN);
8071
8072 rc = _hwrm_send_message(bp, &req2, sizeof(req2), HWRM_CMD_TIMEOUT);
8073 if (!rc) {
8074 struct hwrm_queue_pri2cos_qcfg_output *resp2;
8075 u8 *pri2cos;
8076 int i, j;
8077
8078 resp2 = bp->hwrm_cmd_resp_addr;
8079 pri2cos = &resp2->pri0_cos_queue_id;
8080 for (i = 0; i < 8; i++) {
8081 u8 queue_id = pri2cos[i];
8082 u8 queue_idx;
8083
8084 /* Per port queue IDs start from 0, 10, 20, etc */
8085 queue_idx = queue_id % 10;
8086 if (queue_idx > BNXT_MAX_QUEUE) {
8087 bp->pri2cos_valid = false;
8088 goto qstats_done;
8089 }
8090 for (j = 0; j < bp->max_q; j++) {
8091 if (bp->q_ids[j] == queue_id)
8092 bp->pri2cos_idx[i] = queue_idx;
8093 }
8094 }
8095 bp->pri2cos_valid = 1;
8096 }
8097 qstats_done:
8098 mutex_unlock(&bp->hwrm_cmd_lock);
8099 return rc;
8100 }
8101
8102 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
8103 {
8104 if (bp->vxlan_fw_dst_port_id != INVALID_HW_RING_ID)
8105 bnxt_hwrm_tunnel_dst_port_free(
8106 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
8107 if (bp->nge_fw_dst_port_id != INVALID_HW_RING_ID)
8108 bnxt_hwrm_tunnel_dst_port_free(
8109 bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
8110 }
8111
8112 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
8113 {
8114 int rc, i;
8115 u32 tpa_flags = 0;
8116
8117 if (set_tpa)
8118 tpa_flags = bp->flags & BNXT_FLAG_TPA;
8119 else if (BNXT_NO_FW_ACCESS(bp))
8120 return 0;
8121 for (i = 0; i < bp->nr_vnics; i++) {
8122 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
8123 if (rc) {
8124 netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
8125 i, rc);
8126 return rc;
8127 }
8128 }
8129 return 0;
8130 }
8131
8132 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
8133 {
8134 int i;
8135
8136 for (i = 0; i < bp->nr_vnics; i++)
8137 bnxt_hwrm_vnic_set_rss(bp, i, false);
8138 }
8139
8140 static void bnxt_clear_vnic(struct bnxt *bp)
8141 {
8142 if (!bp->vnic_info)
8143 return;
8144
8145 bnxt_hwrm_clear_vnic_filter(bp);
8146 if (!(bp->flags & BNXT_FLAG_CHIP_P5)) {
8147 /* clear all RSS setting before free vnic ctx */
8148 bnxt_hwrm_clear_vnic_rss(bp);
8149 bnxt_hwrm_vnic_ctx_free(bp);
8150 }
8151 /* before free the vnic, undo the vnic tpa settings */
8152 if (bp->flags & BNXT_FLAG_TPA)
8153 bnxt_set_tpa(bp, false);
8154 bnxt_hwrm_vnic_free(bp);
8155 if (bp->flags & BNXT_FLAG_CHIP_P5)
8156 bnxt_hwrm_vnic_ctx_free(bp);
8157 }
8158
8159 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
8160 bool irq_re_init)
8161 {
8162 bnxt_clear_vnic(bp);
8163 bnxt_hwrm_ring_free(bp, close_path);
8164 bnxt_hwrm_ring_grp_free(bp);
8165 if (irq_re_init) {
8166 bnxt_hwrm_stat_ctx_free(bp);
8167 bnxt_hwrm_free_tunnel_ports(bp);
8168 }
8169 }
8170
8171 static int bnxt_hwrm_set_br_mode(struct bnxt *bp, u16 br_mode)
8172 {
8173 struct hwrm_func_cfg_input req = {0};
8174
8175 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
8176 req.fid = cpu_to_le16(0xffff);
8177 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_EVB_MODE);
8178 if (br_mode == BRIDGE_MODE_VEB)
8179 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEB;
8180 else if (br_mode == BRIDGE_MODE_VEPA)
8181 req.evb_mode = FUNC_CFG_REQ_EVB_MODE_VEPA;
8182 else
8183 return -EINVAL;
8184 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8185 }
8186
8187 static int bnxt_hwrm_set_cache_line_size(struct bnxt *bp, int size)
8188 {
8189 struct hwrm_func_cfg_input req = {0};
8190
8191 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10803)
8192 return 0;
8193
8194 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_CFG, -1, -1);
8195 req.fid = cpu_to_le16(0xffff);
8196 req.enables = cpu_to_le32(FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE);
8197 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64;
8198 if (size == 128)
8199 req.options = FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128;
8200
8201 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
8202 }
8203
8204 static int __bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8205 {
8206 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
8207 int rc;
8208
8209 if (vnic->flags & BNXT_VNIC_RFS_NEW_RSS_FLAG)
8210 goto skip_rss_ctx;
8211
8212 /* allocate context for vnic */
8213 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 0);
8214 if (rc) {
8215 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8216 vnic_id, rc);
8217 goto vnic_setup_err;
8218 }
8219 bp->rsscos_nr_ctxs++;
8220
8221 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8222 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, 1);
8223 if (rc) {
8224 netdev_err(bp->dev, "hwrm vnic %d cos ctx alloc failure rc: %x\n",
8225 vnic_id, rc);
8226 goto vnic_setup_err;
8227 }
8228 bp->rsscos_nr_ctxs++;
8229 }
8230
8231 skip_rss_ctx:
8232 /* configure default vnic, ring grp */
8233 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8234 if (rc) {
8235 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8236 vnic_id, rc);
8237 goto vnic_setup_err;
8238 }
8239
8240 /* Enable RSS hashing on vnic */
8241 rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
8242 if (rc) {
8243 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
8244 vnic_id, rc);
8245 goto vnic_setup_err;
8246 }
8247
8248 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8249 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8250 if (rc) {
8251 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8252 vnic_id, rc);
8253 }
8254 }
8255
8256 vnic_setup_err:
8257 return rc;
8258 }
8259
8260 static int __bnxt_setup_vnic_p5(struct bnxt *bp, u16 vnic_id)
8261 {
8262 int rc, i, nr_ctxs;
8263
8264 nr_ctxs = bnxt_get_nr_rss_ctxs(bp, bp->rx_nr_rings);
8265 for (i = 0; i < nr_ctxs; i++) {
8266 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id, i);
8267 if (rc) {
8268 netdev_err(bp->dev, "hwrm vnic %d ctx %d alloc failure rc: %x\n",
8269 vnic_id, i, rc);
8270 break;
8271 }
8272 bp->rsscos_nr_ctxs++;
8273 }
8274 if (i < nr_ctxs)
8275 return -ENOMEM;
8276
8277 rc = bnxt_hwrm_vnic_set_rss_p5(bp, vnic_id, true);
8278 if (rc) {
8279 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %d\n",
8280 vnic_id, rc);
8281 return rc;
8282 }
8283 rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
8284 if (rc) {
8285 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
8286 vnic_id, rc);
8287 return rc;
8288 }
8289 if (bp->flags & BNXT_FLAG_AGG_RINGS) {
8290 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
8291 if (rc) {
8292 netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
8293 vnic_id, rc);
8294 }
8295 }
8296 return rc;
8297 }
8298
8299 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
8300 {
8301 if (bp->flags & BNXT_FLAG_CHIP_P5)
8302 return __bnxt_setup_vnic_p5(bp, vnic_id);
8303 else
8304 return __bnxt_setup_vnic(bp, vnic_id);
8305 }
8306
8307 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
8308 {
8309 #ifdef CONFIG_RFS_ACCEL
8310 int i, rc = 0;
8311
8312 if (bp->flags & BNXT_FLAG_CHIP_P5)
8313 return 0;
8314
8315 for (i = 0; i < bp->rx_nr_rings; i++) {
8316 struct bnxt_vnic_info *vnic;
8317 u16 vnic_id = i + 1;
8318 u16 ring_id = i;
8319
8320 if (vnic_id >= bp->nr_vnics)
8321 break;
8322
8323 vnic = &bp->vnic_info[vnic_id];
8324 vnic->flags |= BNXT_VNIC_RFS_FLAG;
8325 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
8326 vnic->flags |= BNXT_VNIC_RFS_NEW_RSS_FLAG;
8327 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
8328 if (rc) {
8329 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
8330 vnic_id, rc);
8331 break;
8332 }
8333 rc = bnxt_setup_vnic(bp, vnic_id);
8334 if (rc)
8335 break;
8336 }
8337 return rc;
8338 #else
8339 return 0;
8340 #endif
8341 }
8342
8343 /* Allow PF and VF with default VLAN to be in promiscuous mode */
8344 static bool bnxt_promisc_ok(struct bnxt *bp)
8345 {
8346 #ifdef CONFIG_BNXT_SRIOV
8347 if (BNXT_VF(bp) && !bp->vf.vlan)
8348 return false;
8349 #endif
8350 return true;
8351 }
8352
8353 static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
8354 {
8355 unsigned int rc = 0;
8356
8357 rc = bnxt_hwrm_vnic_alloc(bp, 1, bp->rx_nr_rings - 1, 1);
8358 if (rc) {
8359 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8360 rc);
8361 return rc;
8362 }
8363
8364 rc = bnxt_hwrm_vnic_cfg(bp, 1);
8365 if (rc) {
8366 netdev_err(bp->dev, "Cannot allocate special vnic for NS2 A0: %x\n",
8367 rc);
8368 return rc;
8369 }
8370 return rc;
8371 }
8372
8373 static int bnxt_cfg_rx_mode(struct bnxt *);
8374 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
8375
8376 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
8377 {
8378 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
8379 int rc = 0;
8380 unsigned int rx_nr_rings = bp->rx_nr_rings;
8381
8382 if (irq_re_init) {
8383 rc = bnxt_hwrm_stat_ctx_alloc(bp);
8384 if (rc) {
8385 netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
8386 rc);
8387 goto err_out;
8388 }
8389 }
8390
8391 rc = bnxt_hwrm_ring_alloc(bp);
8392 if (rc) {
8393 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
8394 goto err_out;
8395 }
8396
8397 rc = bnxt_hwrm_ring_grp_alloc(bp);
8398 if (rc) {
8399 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
8400 goto err_out;
8401 }
8402
8403 if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8404 rx_nr_rings--;
8405
8406 /* default vnic 0 */
8407 rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, rx_nr_rings);
8408 if (rc) {
8409 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
8410 goto err_out;
8411 }
8412
8413 rc = bnxt_setup_vnic(bp, 0);
8414 if (rc)
8415 goto err_out;
8416
8417 if (bp->flags & BNXT_FLAG_RFS) {
8418 rc = bnxt_alloc_rfs_vnics(bp);
8419 if (rc)
8420 goto err_out;
8421 }
8422
8423 if (bp->flags & BNXT_FLAG_TPA) {
8424 rc = bnxt_set_tpa(bp, true);
8425 if (rc)
8426 goto err_out;
8427 }
8428
8429 if (BNXT_VF(bp))
8430 bnxt_update_vf_mac(bp);
8431
8432 /* Filter for default vnic 0 */
8433 rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
8434 if (rc) {
8435 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
8436 goto err_out;
8437 }
8438 vnic->uc_filter_count = 1;
8439
8440 vnic->rx_mask = 0;
8441 if (bp->dev->flags & IFF_BROADCAST)
8442 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
8443
8444 if ((bp->dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
8445 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
8446
8447 if (bp->dev->flags & IFF_ALLMULTI) {
8448 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
8449 vnic->mc_list_count = 0;
8450 } else {
8451 u32 mask = 0;
8452
8453 bnxt_mc_list_updated(bp, &mask);
8454 vnic->rx_mask |= mask;
8455 }
8456
8457 rc = bnxt_cfg_rx_mode(bp);
8458 if (rc)
8459 goto err_out;
8460
8461 rc = bnxt_hwrm_set_coal(bp);
8462 if (rc)
8463 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
8464 rc);
8465
8466 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8467 rc = bnxt_setup_nitroa0_vnic(bp);
8468 if (rc)
8469 netdev_err(bp->dev, "Special vnic setup failure for NS2 A0 rc: %x\n",
8470 rc);
8471 }
8472
8473 if (BNXT_VF(bp)) {
8474 bnxt_hwrm_func_qcfg(bp);
8475 netdev_update_features(bp->dev);
8476 }
8477
8478 return 0;
8479
8480 err_out:
8481 bnxt_hwrm_resource_free(bp, 0, true);
8482
8483 return rc;
8484 }
8485
8486 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
8487 {
8488 bnxt_hwrm_resource_free(bp, 1, irq_re_init);
8489 return 0;
8490 }
8491
8492 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
8493 {
8494 bnxt_init_cp_rings(bp);
8495 bnxt_init_rx_rings(bp);
8496 bnxt_init_tx_rings(bp);
8497 bnxt_init_ring_grps(bp, irq_re_init);
8498 bnxt_init_vnics(bp);
8499
8500 return bnxt_init_chip(bp, irq_re_init);
8501 }
8502
8503 static int bnxt_set_real_num_queues(struct bnxt *bp)
8504 {
8505 int rc;
8506 struct net_device *dev = bp->dev;
8507
8508 rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings -
8509 bp->tx_nr_rings_xdp);
8510 if (rc)
8511 return rc;
8512
8513 rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
8514 if (rc)
8515 return rc;
8516
8517 #ifdef CONFIG_RFS_ACCEL
8518 if (bp->flags & BNXT_FLAG_RFS)
8519 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
8520 #endif
8521
8522 return rc;
8523 }
8524
8525 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
8526 bool shared)
8527 {
8528 int _rx = *rx, _tx = *tx;
8529
8530 if (shared) {
8531 *rx = min_t(int, _rx, max);
8532 *tx = min_t(int, _tx, max);
8533 } else {
8534 if (max < 2)
8535 return -ENOMEM;
8536
8537 while (_rx + _tx > max) {
8538 if (_rx > _tx && _rx > 1)
8539 _rx--;
8540 else if (_tx > 1)
8541 _tx--;
8542 }
8543 *rx = _rx;
8544 *tx = _tx;
8545 }
8546 return 0;
8547 }
8548
8549 static void bnxt_setup_msix(struct bnxt *bp)
8550 {
8551 const int len = sizeof(bp->irq_tbl[0].name);
8552 struct net_device *dev = bp->dev;
8553 int tcs, i;
8554
8555 tcs = netdev_get_num_tc(dev);
8556 if (tcs) {
8557 int i, off, count;
8558
8559 for (i = 0; i < tcs; i++) {
8560 count = bp->tx_nr_rings_per_tc;
8561 off = i * count;
8562 netdev_set_tc_queue(dev, i, count, off);
8563 }
8564 }
8565
8566 for (i = 0; i < bp->cp_nr_rings; i++) {
8567 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8568 char *attr;
8569
8570 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
8571 attr = "TxRx";
8572 else if (i < bp->rx_nr_rings)
8573 attr = "rx";
8574 else
8575 attr = "tx";
8576
8577 snprintf(bp->irq_tbl[map_idx].name, len, "%s-%s-%d", dev->name,
8578 attr, i);
8579 bp->irq_tbl[map_idx].handler = bnxt_msix;
8580 }
8581 }
8582
8583 static void bnxt_setup_inta(struct bnxt *bp)
8584 {
8585 const int len = sizeof(bp->irq_tbl[0].name);
8586
8587 if (netdev_get_num_tc(bp->dev))
8588 netdev_reset_tc(bp->dev);
8589
8590 snprintf(bp->irq_tbl[0].name, len, "%s-%s-%d", bp->dev->name, "TxRx",
8591 0);
8592 bp->irq_tbl[0].handler = bnxt_inta;
8593 }
8594
8595 static int bnxt_init_int_mode(struct bnxt *bp);
8596
8597 static int bnxt_setup_int_mode(struct bnxt *bp)
8598 {
8599 int rc;
8600
8601 if (!bp->irq_tbl) {
8602 rc = bnxt_init_int_mode(bp);
8603 if (rc || !bp->irq_tbl)
8604 return rc ?: -ENODEV;
8605 }
8606
8607 if (bp->flags & BNXT_FLAG_USING_MSIX)
8608 bnxt_setup_msix(bp);
8609 else
8610 bnxt_setup_inta(bp);
8611
8612 rc = bnxt_set_real_num_queues(bp);
8613 return rc;
8614 }
8615
8616 #ifdef CONFIG_RFS_ACCEL
8617 static unsigned int bnxt_get_max_func_rss_ctxs(struct bnxt *bp)
8618 {
8619 return bp->hw_resc.max_rsscos_ctxs;
8620 }
8621
8622 static unsigned int bnxt_get_max_func_vnics(struct bnxt *bp)
8623 {
8624 return bp->hw_resc.max_vnics;
8625 }
8626 #endif
8627
8628 unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp)
8629 {
8630 return bp->hw_resc.max_stat_ctxs;
8631 }
8632
8633 unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp)
8634 {
8635 return bp->hw_resc.max_cp_rings;
8636 }
8637
8638 static unsigned int bnxt_get_max_func_cp_rings_for_en(struct bnxt *bp)
8639 {
8640 unsigned int cp = bp->hw_resc.max_cp_rings;
8641
8642 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
8643 cp -= bnxt_get_ulp_msix_num(bp);
8644
8645 return cp;
8646 }
8647
8648 static unsigned int bnxt_get_max_func_irqs(struct bnxt *bp)
8649 {
8650 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
8651
8652 if (bp->flags & BNXT_FLAG_CHIP_P5)
8653 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_nqs);
8654
8655 return min_t(unsigned int, hw_resc->max_irqs, hw_resc->max_cp_rings);
8656 }
8657
8658 static void bnxt_set_max_func_irqs(struct bnxt *bp, unsigned int max_irqs)
8659 {
8660 bp->hw_resc.max_irqs = max_irqs;
8661 }
8662
8663 unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp)
8664 {
8665 unsigned int cp;
8666
8667 cp = bnxt_get_max_func_cp_rings_for_en(bp);
8668 if (bp->flags & BNXT_FLAG_CHIP_P5)
8669 return cp - bp->rx_nr_rings - bp->tx_nr_rings;
8670 else
8671 return cp - bp->cp_nr_rings;
8672 }
8673
8674 unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp)
8675 {
8676 return bnxt_get_max_func_stat_ctxs(bp) - bnxt_get_func_stat_ctxs(bp);
8677 }
8678
8679 int bnxt_get_avail_msix(struct bnxt *bp, int num)
8680 {
8681 int max_cp = bnxt_get_max_func_cp_rings(bp);
8682 int max_irq = bnxt_get_max_func_irqs(bp);
8683 int total_req = bp->cp_nr_rings + num;
8684 int max_idx, avail_msix;
8685
8686 max_idx = bp->total_irqs;
8687 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
8688 max_idx = min_t(int, bp->total_irqs, max_cp);
8689 avail_msix = max_idx - bp->cp_nr_rings;
8690 if (!BNXT_NEW_RM(bp) || avail_msix >= num)
8691 return avail_msix;
8692
8693 if (max_irq < total_req) {
8694 num = max_irq - bp->cp_nr_rings;
8695 if (num <= 0)
8696 return 0;
8697 }
8698 return num;
8699 }
8700
8701 static int bnxt_get_num_msix(struct bnxt *bp)
8702 {
8703 if (!BNXT_NEW_RM(bp))
8704 return bnxt_get_max_func_irqs(bp);
8705
8706 return bnxt_nq_rings_in_use(bp);
8707 }
8708
8709 static int bnxt_init_msix(struct bnxt *bp)
8710 {
8711 int i, total_vecs, max, rc = 0, min = 1, ulp_msix;
8712 struct msix_entry *msix_ent;
8713
8714 total_vecs = bnxt_get_num_msix(bp);
8715 max = bnxt_get_max_func_irqs(bp);
8716 if (total_vecs > max)
8717 total_vecs = max;
8718
8719 if (!total_vecs)
8720 return 0;
8721
8722 msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
8723 if (!msix_ent)
8724 return -ENOMEM;
8725
8726 for (i = 0; i < total_vecs; i++) {
8727 msix_ent[i].entry = i;
8728 msix_ent[i].vector = 0;
8729 }
8730
8731 if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
8732 min = 2;
8733
8734 total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
8735 ulp_msix = bnxt_get_ulp_msix_num(bp);
8736 if (total_vecs < 0 || total_vecs < ulp_msix) {
8737 rc = -ENODEV;
8738 goto msix_setup_exit;
8739 }
8740
8741 bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
8742 if (bp->irq_tbl) {
8743 for (i = 0; i < total_vecs; i++)
8744 bp->irq_tbl[i].vector = msix_ent[i].vector;
8745
8746 bp->total_irqs = total_vecs;
8747 /* Trim rings based upon num of vectors allocated */
8748 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
8749 total_vecs - ulp_msix, min == 1);
8750 if (rc)
8751 goto msix_setup_exit;
8752
8753 bp->cp_nr_rings = (min == 1) ?
8754 max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
8755 bp->tx_nr_rings + bp->rx_nr_rings;
8756
8757 } else {
8758 rc = -ENOMEM;
8759 goto msix_setup_exit;
8760 }
8761 bp->flags |= BNXT_FLAG_USING_MSIX;
8762 kfree(msix_ent);
8763 return 0;
8764
8765 msix_setup_exit:
8766 netdev_err(bp->dev, "bnxt_init_msix err: %x\n", rc);
8767 kfree(bp->irq_tbl);
8768 bp->irq_tbl = NULL;
8769 pci_disable_msix(bp->pdev);
8770 kfree(msix_ent);
8771 return rc;
8772 }
8773
8774 static int bnxt_init_inta(struct bnxt *bp)
8775 {
8776 bp->irq_tbl = kzalloc(sizeof(struct bnxt_irq), GFP_KERNEL);
8777 if (!bp->irq_tbl)
8778 return -ENOMEM;
8779
8780 bp->total_irqs = 1;
8781 bp->rx_nr_rings = 1;
8782 bp->tx_nr_rings = 1;
8783 bp->cp_nr_rings = 1;
8784 bp->flags |= BNXT_FLAG_SHARED_RINGS;
8785 bp->irq_tbl[0].vector = bp->pdev->irq;
8786 return 0;
8787 }
8788
8789 static int bnxt_init_int_mode(struct bnxt *bp)
8790 {
8791 int rc = -ENODEV;
8792
8793 if (bp->flags & BNXT_FLAG_MSIX_CAP)
8794 rc = bnxt_init_msix(bp);
8795
8796 if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
8797 /* fallback to INTA */
8798 rc = bnxt_init_inta(bp);
8799 }
8800 return rc;
8801 }
8802
8803 static void bnxt_clear_int_mode(struct bnxt *bp)
8804 {
8805 if (bp->flags & BNXT_FLAG_USING_MSIX)
8806 pci_disable_msix(bp->pdev);
8807
8808 kfree(bp->irq_tbl);
8809 bp->irq_tbl = NULL;
8810 bp->flags &= ~BNXT_FLAG_USING_MSIX;
8811 }
8812
8813 int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init)
8814 {
8815 int tcs = netdev_get_num_tc(bp->dev);
8816 bool irq_cleared = false;
8817 int rc;
8818
8819 if (!bnxt_need_reserve_rings(bp))
8820 return 0;
8821
8822 if (irq_re_init && BNXT_NEW_RM(bp) &&
8823 bnxt_get_num_msix(bp) != bp->total_irqs) {
8824 bnxt_ulp_irq_stop(bp);
8825 bnxt_clear_int_mode(bp);
8826 irq_cleared = true;
8827 }
8828 rc = __bnxt_reserve_rings(bp);
8829 if (irq_cleared) {
8830 if (!rc)
8831 rc = bnxt_init_int_mode(bp);
8832 bnxt_ulp_irq_restart(bp, rc);
8833 }
8834 if (rc) {
8835 netdev_err(bp->dev, "ring reservation/IRQ init failure rc: %d\n", rc);
8836 return rc;
8837 }
8838 if (tcs && (bp->tx_nr_rings_per_tc * tcs != bp->tx_nr_rings)) {
8839 netdev_err(bp->dev, "tx ring reservation failure\n");
8840 netdev_reset_tc(bp->dev);
8841 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
8842 return -ENOMEM;
8843 }
8844 return 0;
8845 }
8846
8847 static void bnxt_free_irq(struct bnxt *bp)
8848 {
8849 struct bnxt_irq *irq;
8850 int i;
8851
8852 #ifdef CONFIG_RFS_ACCEL
8853 free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
8854 bp->dev->rx_cpu_rmap = NULL;
8855 #endif
8856 if (!bp->irq_tbl || !bp->bnapi)
8857 return;
8858
8859 for (i = 0; i < bp->cp_nr_rings; i++) {
8860 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8861
8862 irq = &bp->irq_tbl[map_idx];
8863 if (irq->requested) {
8864 if (irq->have_cpumask) {
8865 irq_set_affinity_hint(irq->vector, NULL);
8866 free_cpumask_var(irq->cpu_mask);
8867 irq->have_cpumask = 0;
8868 }
8869 free_irq(irq->vector, bp->bnapi[i]);
8870 }
8871
8872 irq->requested = 0;
8873 }
8874 }
8875
8876 static int bnxt_request_irq(struct bnxt *bp)
8877 {
8878 int i, j, rc = 0;
8879 unsigned long flags = 0;
8880 #ifdef CONFIG_RFS_ACCEL
8881 struct cpu_rmap *rmap;
8882 #endif
8883
8884 rc = bnxt_setup_int_mode(bp);
8885 if (rc) {
8886 netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
8887 rc);
8888 return rc;
8889 }
8890 #ifdef CONFIG_RFS_ACCEL
8891 rmap = bp->dev->rx_cpu_rmap;
8892 #endif
8893 if (!(bp->flags & BNXT_FLAG_USING_MSIX))
8894 flags = IRQF_SHARED;
8895
8896 for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
8897 int map_idx = bnxt_cp_num_to_irq_num(bp, i);
8898 struct bnxt_irq *irq = &bp->irq_tbl[map_idx];
8899
8900 #ifdef CONFIG_RFS_ACCEL
8901 if (rmap && bp->bnapi[i]->rx_ring) {
8902 rc = irq_cpu_rmap_add(rmap, irq->vector);
8903 if (rc)
8904 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
8905 j);
8906 j++;
8907 }
8908 #endif
8909 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
8910 bp->bnapi[i]);
8911 if (rc)
8912 break;
8913
8914 irq->requested = 1;
8915
8916 if (zalloc_cpumask_var(&irq->cpu_mask, GFP_KERNEL)) {
8917 int numa_node = dev_to_node(&bp->pdev->dev);
8918
8919 irq->have_cpumask = 1;
8920 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
8921 irq->cpu_mask);
8922 rc = irq_set_affinity_hint(irq->vector, irq->cpu_mask);
8923 if (rc) {
8924 netdev_warn(bp->dev,
8925 "Set affinity failed, IRQ = %d\n",
8926 irq->vector);
8927 break;
8928 }
8929 }
8930 }
8931 return rc;
8932 }
8933
8934 static void bnxt_del_napi(struct bnxt *bp)
8935 {
8936 int i;
8937
8938 if (!bp->bnapi)
8939 return;
8940
8941 for (i = 0; i < bp->cp_nr_rings; i++) {
8942 struct bnxt_napi *bnapi = bp->bnapi[i];
8943
8944 __netif_napi_del(&bnapi->napi);
8945 }
8946 /* We called __netif_napi_del(), we need
8947 * to respect an RCU grace period before freeing napi structures.
8948 */
8949 synchronize_net();
8950 }
8951
8952 static void bnxt_init_napi(struct bnxt *bp)
8953 {
8954 int i;
8955 unsigned int cp_nr_rings = bp->cp_nr_rings;
8956 struct bnxt_napi *bnapi;
8957
8958 if (bp->flags & BNXT_FLAG_USING_MSIX) {
8959 int (*poll_fn)(struct napi_struct *, int) = bnxt_poll;
8960
8961 if (bp->flags & BNXT_FLAG_CHIP_P5)
8962 poll_fn = bnxt_poll_p5;
8963 else if (BNXT_CHIP_TYPE_NITRO_A0(bp))
8964 cp_nr_rings--;
8965 for (i = 0; i < cp_nr_rings; i++) {
8966 bnapi = bp->bnapi[i];
8967 netif_napi_add(bp->dev, &bnapi->napi, poll_fn, 64);
8968 }
8969 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
8970 bnapi = bp->bnapi[cp_nr_rings];
8971 netif_napi_add(bp->dev, &bnapi->napi,
8972 bnxt_poll_nitroa0, 64);
8973 }
8974 } else {
8975 bnapi = bp->bnapi[0];
8976 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
8977 }
8978 }
8979
8980 static void bnxt_disable_napi(struct bnxt *bp)
8981 {
8982 int i;
8983
8984 if (!bp->bnapi ||
8985 test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state))
8986 return;
8987
8988 for (i = 0; i < bp->cp_nr_rings; i++) {
8989 struct bnxt_cp_ring_info *cpr = &bp->bnapi[i]->cp_ring;
8990
8991 if (bp->bnapi[i]->rx_ring)
8992 cancel_work_sync(&cpr->dim.work);
8993
8994 napi_disable(&bp->bnapi[i]->napi);
8995 }
8996 }
8997
8998 static void bnxt_enable_napi(struct bnxt *bp)
8999 {
9000 int i;
9001
9002 clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state);
9003 for (i = 0; i < bp->cp_nr_rings; i++) {
9004 struct bnxt_napi *bnapi = bp->bnapi[i];
9005 struct bnxt_cp_ring_info *cpr;
9006
9007 cpr = &bnapi->cp_ring;
9008 if (bnapi->in_reset)
9009 cpr->sw_stats.rx.rx_resets++;
9010 bnapi->in_reset = false;
9011
9012 if (bnapi->rx_ring) {
9013 INIT_WORK(&cpr->dim.work, bnxt_dim_work);
9014 cpr->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
9015 }
9016 napi_enable(&bnapi->napi);
9017 }
9018 }
9019
9020 void bnxt_tx_disable(struct bnxt *bp)
9021 {
9022 int i;
9023 struct bnxt_tx_ring_info *txr;
9024
9025 if (bp->tx_ring) {
9026 for (i = 0; i < bp->tx_nr_rings; i++) {
9027 txr = &bp->tx_ring[i];
9028 txr->dev_state = BNXT_DEV_STATE_CLOSING;
9029 }
9030 }
9031 /* Drop carrier first to prevent TX timeout */
9032 netif_carrier_off(bp->dev);
9033 /* Stop all TX queues */
9034 netif_tx_disable(bp->dev);
9035 }
9036
9037 void bnxt_tx_enable(struct bnxt *bp)
9038 {
9039 int i;
9040 struct bnxt_tx_ring_info *txr;
9041
9042 for (i = 0; i < bp->tx_nr_rings; i++) {
9043 txr = &bp->tx_ring[i];
9044 txr->dev_state = 0;
9045 }
9046 netif_tx_wake_all_queues(bp->dev);
9047 if (bp->link_info.link_up)
9048 netif_carrier_on(bp->dev);
9049 }
9050
9051 static char *bnxt_report_fec(struct bnxt_link_info *link_info)
9052 {
9053 u8 active_fec = link_info->active_fec_sig_mode &
9054 PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;
9055
9056 switch (active_fec) {
9057 default:
9058 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:
9059 return "None";
9060 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:
9061 return "Clause 74 BaseR";
9062 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:
9063 return "Clause 91 RS(528,514)";
9064 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:
9065 return "Clause 91 RS544_1XN";
9066 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:
9067 return "Clause 91 RS(544,514)";
9068 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:
9069 return "Clause 91 RS272_1XN";
9070 case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:
9071 return "Clause 91 RS(272,257)";
9072 }
9073 }
9074
9075 static void bnxt_report_link(struct bnxt *bp)
9076 {
9077 if (bp->link_info.link_up) {
9078 const char *duplex;
9079 const char *flow_ctrl;
9080 u32 speed;
9081 u16 fec;
9082
9083 netif_carrier_on(bp->dev);
9084 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
9085 if (speed == SPEED_UNKNOWN) {
9086 netdev_info(bp->dev, "NIC Link is Up, speed unknown\n");
9087 return;
9088 }
9089 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
9090 duplex = "full";
9091 else
9092 duplex = "half";
9093 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
9094 flow_ctrl = "ON - receive & transmit";
9095 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
9096 flow_ctrl = "ON - transmit";
9097 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
9098 flow_ctrl = "ON - receive";
9099 else
9100 flow_ctrl = "none";
9101 netdev_info(bp->dev, "NIC Link is Up, %u Mbps %s duplex, Flow control: %s\n",
9102 speed, duplex, flow_ctrl);
9103 if (bp->flags & BNXT_FLAG_EEE_CAP)
9104 netdev_info(bp->dev, "EEE is %s\n",
9105 bp->eee.eee_active ? "active" :
9106 "not active");
9107 fec = bp->link_info.fec_cfg;
9108 if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))
9109 netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",
9110 (fec & BNXT_FEC_AUTONEG) ? "on" : "off",
9111 bnxt_report_fec(&bp->link_info));
9112 } else {
9113 netif_carrier_off(bp->dev);
9114 netdev_err(bp->dev, "NIC Link is Down\n");
9115 }
9116 }
9117
9118 static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)
9119 {
9120 if (!resp->supported_speeds_auto_mode &&
9121 !resp->supported_speeds_force_mode &&
9122 !resp->supported_pam4_speeds_auto_mode &&
9123 !resp->supported_pam4_speeds_force_mode)
9124 return true;
9125 return false;
9126 }
9127
9128 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
9129 {
9130 int rc = 0;
9131 struct hwrm_port_phy_qcaps_input req = {0};
9132 struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
9133 struct bnxt_link_info *link_info = &bp->link_info;
9134
9135 bp->flags &= ~BNXT_FLAG_EEE_CAP;
9136 if (bp->test_info)
9137 bp->test_info->flags &= ~(BNXT_TEST_FL_EXT_LPBK |
9138 BNXT_TEST_FL_AN_PHY_LPBK);
9139 if (bp->hwrm_spec_code < 0x10201)
9140 return 0;
9141
9142 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
9143
9144 mutex_lock(&bp->hwrm_cmd_lock);
9145 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9146 if (rc)
9147 goto hwrm_phy_qcaps_exit;
9148
9149 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED) {
9150 struct ethtool_eee *eee = &bp->eee;
9151 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
9152
9153 bp->flags |= BNXT_FLAG_EEE_CAP;
9154 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9155 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
9156 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
9157 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
9158 PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
9159 }
9160 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_EXTERNAL_LPBK_SUPPORTED) {
9161 if (bp->test_info)
9162 bp->test_info->flags |= BNXT_TEST_FL_EXT_LPBK;
9163 }
9164 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_AUTONEG_LPBK_SUPPORTED) {
9165 if (bp->test_info)
9166 bp->test_info->flags |= BNXT_TEST_FL_AN_PHY_LPBK;
9167 }
9168 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED) {
9169 if (BNXT_PF(bp))
9170 bp->fw_cap |= BNXT_FW_CAP_SHARED_PORT_CFG;
9171 }
9172 if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET)
9173 bp->fw_cap |= BNXT_FW_CAP_PORT_STATS_NO_RESET;
9174
9175 if (bp->hwrm_spec_code >= 0x10a01) {
9176 if (bnxt_phy_qcaps_no_speed(resp)) {
9177 link_info->phy_state = BNXT_PHY_STATE_DISABLED;
9178 netdev_warn(bp->dev, "Ethernet link disabled\n");
9179 } else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {
9180 link_info->phy_state = BNXT_PHY_STATE_ENABLED;
9181 netdev_info(bp->dev, "Ethernet link enabled\n");
9182 /* Phy re-enabled, reprobe the speeds */
9183 link_info->support_auto_speeds = 0;
9184 link_info->support_pam4_auto_speeds = 0;
9185 }
9186 }
9187 if (resp->supported_speeds_auto_mode)
9188 link_info->support_auto_speeds =
9189 le16_to_cpu(resp->supported_speeds_auto_mode);
9190 if (resp->supported_pam4_speeds_auto_mode)
9191 link_info->support_pam4_auto_speeds =
9192 le16_to_cpu(resp->supported_pam4_speeds_auto_mode);
9193
9194 bp->port_count = resp->port_cnt;
9195
9196 hwrm_phy_qcaps_exit:
9197 mutex_unlock(&bp->hwrm_cmd_lock);
9198 return rc;
9199 }
9200
9201 static bool bnxt_support_dropped(u16 advertising, u16 supported)
9202 {
9203 u16 diff = advertising ^ supported;
9204
9205 return ((supported | diff) != supported);
9206 }
9207
9208 int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
9209 {
9210 int rc = 0;
9211 struct bnxt_link_info *link_info = &bp->link_info;
9212 struct hwrm_port_phy_qcfg_input req = {0};
9213 struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9214 u8 link_up = link_info->link_up;
9215 bool support_changed = false;
9216
9217 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
9218
9219 mutex_lock(&bp->hwrm_cmd_lock);
9220 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9221 if (rc) {
9222 mutex_unlock(&bp->hwrm_cmd_lock);
9223 return rc;
9224 }
9225
9226 memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
9227 link_info->phy_link_status = resp->link;
9228 link_info->duplex = resp->duplex_cfg;
9229 if (bp->hwrm_spec_code >= 0x10800)
9230 link_info->duplex = resp->duplex_state;
9231 link_info->pause = resp->pause;
9232 link_info->auto_mode = resp->auto_mode;
9233 link_info->auto_pause_setting = resp->auto_pause;
9234 link_info->lp_pause = resp->link_partner_adv_pause;
9235 link_info->force_pause_setting = resp->force_pause;
9236 link_info->duplex_setting = resp->duplex_cfg;
9237 if (link_info->phy_link_status == BNXT_LINK_LINK)
9238 link_info->link_speed = le16_to_cpu(resp->link_speed);
9239 else
9240 link_info->link_speed = 0;
9241 link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
9242 link_info->force_pam4_link_speed =
9243 le16_to_cpu(resp->force_pam4_link_speed);
9244 link_info->support_speeds = le16_to_cpu(resp->support_speeds);
9245 link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);
9246 link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
9247 link_info->auto_pam4_link_speeds =
9248 le16_to_cpu(resp->auto_pam4_link_speed_mask);
9249 link_info->lp_auto_link_speeds =
9250 le16_to_cpu(resp->link_partner_adv_speeds);
9251 link_info->lp_auto_pam4_link_speeds =
9252 resp->link_partner_pam4_adv_speeds;
9253 link_info->preemphasis = le32_to_cpu(resp->preemphasis);
9254 link_info->phy_ver[0] = resp->phy_maj;
9255 link_info->phy_ver[1] = resp->phy_min;
9256 link_info->phy_ver[2] = resp->phy_bld;
9257 link_info->media_type = resp->media_type;
9258 link_info->phy_type = resp->phy_type;
9259 link_info->transceiver = resp->xcvr_pkg_type;
9260 link_info->phy_addr = resp->eee_config_phy_addr &
9261 PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
9262 link_info->module_status = resp->module_status;
9263
9264 if (bp->flags & BNXT_FLAG_EEE_CAP) {
9265 struct ethtool_eee *eee = &bp->eee;
9266 u16 fw_speeds;
9267
9268 eee->eee_active = 0;
9269 if (resp->eee_config_phy_addr &
9270 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
9271 eee->eee_active = 1;
9272 fw_speeds = le16_to_cpu(
9273 resp->link_partner_adv_eee_link_speed_mask);
9274 eee->lp_advertised =
9275 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9276 }
9277
9278 /* Pull initial EEE config */
9279 if (!chng_link_state) {
9280 if (resp->eee_config_phy_addr &
9281 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
9282 eee->eee_enabled = 1;
9283
9284 fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
9285 eee->advertised =
9286 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
9287
9288 if (resp->eee_config_phy_addr &
9289 PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
9290 __le32 tmr;
9291
9292 eee->tx_lpi_enabled = 1;
9293 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
9294 eee->tx_lpi_timer = le32_to_cpu(tmr) &
9295 PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
9296 }
9297 }
9298 }
9299
9300 link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;
9301 if (bp->hwrm_spec_code >= 0x10504) {
9302 link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);
9303 link_info->active_fec_sig_mode = resp->active_fec_signal_mode;
9304 }
9305 /* TODO: need to add more logic to report VF link */
9306 if (chng_link_state) {
9307 if (link_info->phy_link_status == BNXT_LINK_LINK)
9308 link_info->link_up = 1;
9309 else
9310 link_info->link_up = 0;
9311 if (link_up != link_info->link_up)
9312 bnxt_report_link(bp);
9313 } else {
9314 /* alwasy link down if not require to update link state */
9315 link_info->link_up = 0;
9316 }
9317 mutex_unlock(&bp->hwrm_cmd_lock);
9318
9319 if (!BNXT_PHY_CFG_ABLE(bp))
9320 return 0;
9321
9322 /* Check if any advertised speeds are no longer supported. The caller
9323 * holds the link_lock mutex, so we can modify link_info settings.
9324 */
9325 if (bnxt_support_dropped(link_info->advertising,
9326 link_info->support_auto_speeds)) {
9327 link_info->advertising = link_info->support_auto_speeds;
9328 support_changed = true;
9329 }
9330 if (bnxt_support_dropped(link_info->advertising_pam4,
9331 link_info->support_pam4_auto_speeds)) {
9332 link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;
9333 support_changed = true;
9334 }
9335 if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))
9336 bnxt_hwrm_set_link_setting(bp, true, false);
9337 return 0;
9338 }
9339
9340 static void bnxt_get_port_module_status(struct bnxt *bp)
9341 {
9342 struct bnxt_link_info *link_info = &bp->link_info;
9343 struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
9344 u8 module_status;
9345
9346 if (bnxt_update_link(bp, true))
9347 return;
9348
9349 module_status = link_info->module_status;
9350 switch (module_status) {
9351 case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
9352 case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
9353 case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
9354 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
9355 bp->pf.port_id);
9356 if (bp->hwrm_spec_code >= 0x10201) {
9357 netdev_warn(bp->dev, "Module part number %s\n",
9358 resp->phy_vendor_partnumber);
9359 }
9360 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
9361 netdev_warn(bp->dev, "TX is disabled\n");
9362 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
9363 netdev_warn(bp->dev, "SFP+ module is shutdown\n");
9364 }
9365 }
9366
9367 static void
9368 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9369 {
9370 if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
9371 if (bp->hwrm_spec_code >= 0x10201)
9372 req->auto_pause =
9373 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
9374 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9375 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
9376 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9377 req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
9378 req->enables |=
9379 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9380 } else {
9381 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
9382 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
9383 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
9384 req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
9385 req->enables |=
9386 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
9387 if (bp->hwrm_spec_code >= 0x10201) {
9388 req->auto_pause = req->force_pause;
9389 req->enables |= cpu_to_le32(
9390 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
9391 }
9392 }
9393 }
9394
9395 static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
9396 {
9397 if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {
9398 req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
9399 if (bp->link_info.advertising) {
9400 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
9401 req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);
9402 }
9403 if (bp->link_info.advertising_pam4) {
9404 req->enables |=
9405 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK);
9406 req->auto_link_pam4_speed_mask =
9407 cpu_to_le16(bp->link_info.advertising_pam4);
9408 }
9409 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
9410 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
9411 } else {
9412 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
9413 if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {
9414 req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9415 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);
9416 } else {
9417 req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);
9418 }
9419 }
9420
9421 /* tell chimp that the setting takes effect immediately */
9422 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
9423 }
9424
9425 int bnxt_hwrm_set_pause(struct bnxt *bp)
9426 {
9427 struct hwrm_port_phy_cfg_input req = {0};
9428 int rc;
9429
9430 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9431 bnxt_hwrm_set_pause_common(bp, &req);
9432
9433 if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
9434 bp->link_info.force_link_chng)
9435 bnxt_hwrm_set_link_common(bp, &req);
9436
9437 mutex_lock(&bp->hwrm_cmd_lock);
9438 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9439 if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
9440 /* since changing of pause setting doesn't trigger any link
9441 * change event, the driver needs to update the current pause
9442 * result upon successfully return of the phy_cfg command
9443 */
9444 bp->link_info.pause =
9445 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
9446 bp->link_info.auto_pause_setting = 0;
9447 if (!bp->link_info.force_link_chng)
9448 bnxt_report_link(bp);
9449 }
9450 bp->link_info.force_link_chng = false;
9451 mutex_unlock(&bp->hwrm_cmd_lock);
9452 return rc;
9453 }
9454
9455 static void bnxt_hwrm_set_eee(struct bnxt *bp,
9456 struct hwrm_port_phy_cfg_input *req)
9457 {
9458 struct ethtool_eee *eee = &bp->eee;
9459
9460 if (eee->eee_enabled) {
9461 u16 eee_speeds;
9462 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
9463
9464 if (eee->tx_lpi_enabled)
9465 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
9466 else
9467 flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
9468
9469 req->flags |= cpu_to_le32(flags);
9470 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
9471 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
9472 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
9473 } else {
9474 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
9475 }
9476 }
9477
9478 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
9479 {
9480 struct hwrm_port_phy_cfg_input req = {0};
9481
9482 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9483 if (set_pause)
9484 bnxt_hwrm_set_pause_common(bp, &req);
9485
9486 bnxt_hwrm_set_link_common(bp, &req);
9487
9488 if (set_eee)
9489 bnxt_hwrm_set_eee(bp, &req);
9490 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9491 }
9492
9493 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
9494 {
9495 struct hwrm_port_phy_cfg_input req = {0};
9496
9497 if (!BNXT_SINGLE_PF(bp))
9498 return 0;
9499
9500 if (pci_num_vf(bp->pdev))
9501 return 0;
9502
9503 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
9504 req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN);
9505 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9506 }
9507
9508 static int bnxt_fw_init_one(struct bnxt *bp);
9509
9510 static int bnxt_fw_reset_via_optee(struct bnxt *bp)
9511 {
9512 #ifdef CONFIG_TEE_BNXT_FW
9513 int rc = tee_bnxt_fw_load();
9514
9515 if (rc)
9516 netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc);
9517
9518 return rc;
9519 #else
9520 netdev_err(bp->dev, "OP-TEE not supported\n");
9521 return -ENODEV;
9522 #endif
9523 }
9524
9525 static int bnxt_try_recover_fw(struct bnxt *bp)
9526 {
9527 if (bp->fw_health && bp->fw_health->status_reliable) {
9528 int retry = 0, rc;
9529 u32 sts;
9530
9531 mutex_lock(&bp->hwrm_cmd_lock);
9532 do {
9533 rc = __bnxt_hwrm_ver_get(bp, true);
9534 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
9535 if (!sts || !BNXT_FW_IS_BOOTING(sts))
9536 break;
9537 retry++;
9538 } while (rc == -EBUSY && retry < BNXT_FW_RETRY);
9539 mutex_unlock(&bp->hwrm_cmd_lock);
9540
9541 if (!BNXT_FW_IS_HEALTHY(sts)) {
9542 netdev_err(bp->dev,
9543 "Firmware not responding, status: 0x%x\n",
9544 sts);
9545 rc = -ENODEV;
9546 }
9547 if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) {
9548 netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n");
9549 return bnxt_fw_reset_via_optee(bp);
9550 }
9551 return rc;
9552 }
9553
9554 return -ENODEV;
9555 }
9556
9557 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up)
9558 {
9559 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr;
9560 struct hwrm_func_drv_if_change_input req = {0};
9561 bool fw_reset = !bp->irq_tbl;
9562 bool resc_reinit = false;
9563 int rc, retry = 0;
9564 u32 flags = 0;
9565
9566 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE))
9567 return 0;
9568
9569 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_IF_CHANGE, -1, -1);
9570 if (up)
9571 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP);
9572 mutex_lock(&bp->hwrm_cmd_lock);
9573 while (retry < BNXT_FW_IF_RETRY) {
9574 rc = _hwrm_send_message(bp, &req, sizeof(req),
9575 HWRM_CMD_TIMEOUT);
9576 if (rc != -EAGAIN)
9577 break;
9578
9579 msleep(50);
9580 retry++;
9581 }
9582 if (!rc)
9583 flags = le32_to_cpu(resp->flags);
9584 mutex_unlock(&bp->hwrm_cmd_lock);
9585
9586 if (rc == -EAGAIN)
9587 return rc;
9588 if (rc && up) {
9589 rc = bnxt_try_recover_fw(bp);
9590 fw_reset = true;
9591 }
9592 if (rc)
9593 return rc;
9594
9595 if (!up) {
9596 bnxt_inv_fw_health_reg(bp);
9597 return 0;
9598 }
9599
9600 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_RESC_CHANGE)
9601 resc_reinit = true;
9602 if (flags & FUNC_DRV_IF_CHANGE_RESP_FLAGS_HOT_FW_RESET_DONE)
9603 fw_reset = true;
9604 else if (bp->fw_health && !bp->fw_health->status_reliable)
9605 bnxt_try_map_fw_health_reg(bp);
9606
9607 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state) && !fw_reset) {
9608 netdev_err(bp->dev, "RESET_DONE not set during FW reset.\n");
9609 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9610 return -ENODEV;
9611 }
9612 if (resc_reinit || fw_reset) {
9613 if (fw_reset) {
9614 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9615 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
9616 bnxt_ulp_stop(bp);
9617 bnxt_free_ctx_mem(bp);
9618 kfree(bp->ctx);
9619 bp->ctx = NULL;
9620 bnxt_dcb_free(bp);
9621 rc = bnxt_fw_init_one(bp);
9622 if (rc) {
9623 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9624 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9625 return rc;
9626 }
9627 bnxt_clear_int_mode(bp);
9628 rc = bnxt_init_int_mode(bp);
9629 if (rc) {
9630 clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9631 netdev_err(bp->dev, "init int mode failed\n");
9632 return rc;
9633 }
9634 }
9635 if (BNXT_NEW_RM(bp)) {
9636 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
9637
9638 rc = bnxt_hwrm_func_resc_qcaps(bp, true);
9639 if (rc)
9640 netdev_err(bp->dev, "resc_qcaps failed\n");
9641
9642 hw_resc->resv_cp_rings = 0;
9643 hw_resc->resv_stat_ctxs = 0;
9644 hw_resc->resv_irqs = 0;
9645 hw_resc->resv_tx_rings = 0;
9646 hw_resc->resv_rx_rings = 0;
9647 hw_resc->resv_hw_ring_grps = 0;
9648 hw_resc->resv_vnics = 0;
9649 if (!fw_reset) {
9650 bp->tx_nr_rings = 0;
9651 bp->rx_nr_rings = 0;
9652 }
9653 }
9654 }
9655 return rc;
9656 }
9657
9658 static int bnxt_hwrm_port_led_qcaps(struct bnxt *bp)
9659 {
9660 struct hwrm_port_led_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
9661 struct hwrm_port_led_qcaps_input req = {0};
9662 struct bnxt_pf_info *pf = &bp->pf;
9663 int rc;
9664
9665 bp->num_leds = 0;
9666 if (BNXT_VF(bp) || bp->hwrm_spec_code < 0x10601)
9667 return 0;
9668
9669 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_LED_QCAPS, -1, -1);
9670 req.port_id = cpu_to_le16(pf->port_id);
9671 mutex_lock(&bp->hwrm_cmd_lock);
9672 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9673 if (rc) {
9674 mutex_unlock(&bp->hwrm_cmd_lock);
9675 return rc;
9676 }
9677 if (resp->num_leds > 0 && resp->num_leds < BNXT_MAX_LED) {
9678 int i;
9679
9680 bp->num_leds = resp->num_leds;
9681 memcpy(bp->leds, &resp->led0_id, sizeof(bp->leds[0]) *
9682 bp->num_leds);
9683 for (i = 0; i < bp->num_leds; i++) {
9684 struct bnxt_led_info *led = &bp->leds[i];
9685 __le16 caps = led->led_state_caps;
9686
9687 if (!led->led_group_id ||
9688 !BNXT_LED_ALT_BLINK_CAP(caps)) {
9689 bp->num_leds = 0;
9690 break;
9691 }
9692 }
9693 }
9694 mutex_unlock(&bp->hwrm_cmd_lock);
9695 return 0;
9696 }
9697
9698 int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp)
9699 {
9700 struct hwrm_wol_filter_alloc_input req = {0};
9701 struct hwrm_wol_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
9702 int rc;
9703
9704 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_ALLOC, -1, -1);
9705 req.port_id = cpu_to_le16(bp->pf.port_id);
9706 req.wol_type = WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT;
9707 req.enables = cpu_to_le32(WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS);
9708 memcpy(req.mac_address, bp->dev->dev_addr, ETH_ALEN);
9709 mutex_lock(&bp->hwrm_cmd_lock);
9710 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9711 if (!rc)
9712 bp->wol_filter_id = resp->wol_filter_id;
9713 mutex_unlock(&bp->hwrm_cmd_lock);
9714 return rc;
9715 }
9716
9717 int bnxt_hwrm_free_wol_fltr(struct bnxt *bp)
9718 {
9719 struct hwrm_wol_filter_free_input req = {0};
9720
9721 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_FREE, -1, -1);
9722 req.port_id = cpu_to_le16(bp->pf.port_id);
9723 req.enables = cpu_to_le32(WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID);
9724 req.wol_filter_id = bp->wol_filter_id;
9725 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9726 }
9727
9728 static u16 bnxt_hwrm_get_wol_fltrs(struct bnxt *bp, u16 handle)
9729 {
9730 struct hwrm_wol_filter_qcfg_input req = {0};
9731 struct hwrm_wol_filter_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
9732 u16 next_handle = 0;
9733 int rc;
9734
9735 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_WOL_FILTER_QCFG, -1, -1);
9736 req.port_id = cpu_to_le16(bp->pf.port_id);
9737 req.handle = cpu_to_le16(handle);
9738 mutex_lock(&bp->hwrm_cmd_lock);
9739 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9740 if (!rc) {
9741 next_handle = le16_to_cpu(resp->next_handle);
9742 if (next_handle != 0) {
9743 if (resp->wol_type ==
9744 WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT) {
9745 bp->wol = 1;
9746 bp->wol_filter_id = resp->wol_filter_id;
9747 }
9748 }
9749 }
9750 mutex_unlock(&bp->hwrm_cmd_lock);
9751 return next_handle;
9752 }
9753
9754 static void bnxt_get_wol_settings(struct bnxt *bp)
9755 {
9756 u16 handle = 0;
9757
9758 bp->wol = 0;
9759 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_WOL_CAP))
9760 return;
9761
9762 do {
9763 handle = bnxt_hwrm_get_wol_fltrs(bp, handle);
9764 } while (handle && handle != 0xffff);
9765 }
9766
9767 #ifdef CONFIG_BNXT_HWMON
9768 static ssize_t bnxt_show_temp(struct device *dev,
9769 struct device_attribute *devattr, char *buf)
9770 {
9771 struct hwrm_temp_monitor_query_input req = {0};
9772 struct hwrm_temp_monitor_query_output *resp;
9773 struct bnxt *bp = dev_get_drvdata(dev);
9774 u32 len = 0;
9775 int rc;
9776
9777 resp = bp->hwrm_cmd_resp_addr;
9778 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
9779 mutex_lock(&bp->hwrm_cmd_lock);
9780 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9781 if (!rc)
9782 len = sprintf(buf, "%u\n", resp->temp * 1000); /* display millidegree */
9783 mutex_unlock(&bp->hwrm_cmd_lock);
9784 return rc ?: len;
9785 }
9786 static SENSOR_DEVICE_ATTR(temp1_input, 0444, bnxt_show_temp, NULL, 0);
9787
9788 static struct attribute *bnxt_attrs[] = {
9789 &sensor_dev_attr_temp1_input.dev_attr.attr,
9790 NULL
9791 };
9792 ATTRIBUTE_GROUPS(bnxt);
9793
9794 static void bnxt_hwmon_close(struct bnxt *bp)
9795 {
9796 if (bp->hwmon_dev) {
9797 hwmon_device_unregister(bp->hwmon_dev);
9798 bp->hwmon_dev = NULL;
9799 }
9800 }
9801
9802 static void bnxt_hwmon_open(struct bnxt *bp)
9803 {
9804 struct hwrm_temp_monitor_query_input req = {0};
9805 struct pci_dev *pdev = bp->pdev;
9806 int rc;
9807
9808 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TEMP_MONITOR_QUERY, -1, -1);
9809 rc = hwrm_send_message_silent(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
9810 if (rc == -EACCES || rc == -EOPNOTSUPP) {
9811 bnxt_hwmon_close(bp);
9812 return;
9813 }
9814
9815 if (bp->hwmon_dev)
9816 return;
9817
9818 bp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev,
9819 DRV_MODULE_NAME, bp,
9820 bnxt_groups);
9821 if (IS_ERR(bp->hwmon_dev)) {
9822 bp->hwmon_dev = NULL;
9823 dev_warn(&pdev->dev, "Cannot register hwmon device\n");
9824 }
9825 }
9826 #else
9827 static void bnxt_hwmon_close(struct bnxt *bp)
9828 {
9829 }
9830
9831 static void bnxt_hwmon_open(struct bnxt *bp)
9832 {
9833 }
9834 #endif
9835
9836 static bool bnxt_eee_config_ok(struct bnxt *bp)
9837 {
9838 struct ethtool_eee *eee = &bp->eee;
9839 struct bnxt_link_info *link_info = &bp->link_info;
9840
9841 if (!(bp->flags & BNXT_FLAG_EEE_CAP))
9842 return true;
9843
9844 if (eee->eee_enabled) {
9845 u32 advertising =
9846 _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
9847
9848 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
9849 eee->eee_enabled = 0;
9850 return false;
9851 }
9852 if (eee->advertised & ~advertising) {
9853 eee->advertised = advertising & eee->supported;
9854 return false;
9855 }
9856 }
9857 return true;
9858 }
9859
9860 static int bnxt_update_phy_setting(struct bnxt *bp)
9861 {
9862 int rc;
9863 bool update_link = false;
9864 bool update_pause = false;
9865 bool update_eee = false;
9866 struct bnxt_link_info *link_info = &bp->link_info;
9867
9868 rc = bnxt_update_link(bp, true);
9869 if (rc) {
9870 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
9871 rc);
9872 return rc;
9873 }
9874 if (!BNXT_SINGLE_PF(bp))
9875 return 0;
9876
9877 if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
9878 (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
9879 link_info->req_flow_ctrl)
9880 update_pause = true;
9881 if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
9882 link_info->force_pause_setting != link_info->req_flow_ctrl)
9883 update_pause = true;
9884 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
9885 if (BNXT_AUTO_MODE(link_info->auto_mode))
9886 update_link = true;
9887 if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&
9888 link_info->req_link_speed != link_info->force_link_speed)
9889 update_link = true;
9890 else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&
9891 link_info->req_link_speed != link_info->force_pam4_link_speed)
9892 update_link = true;
9893 if (link_info->req_duplex != link_info->duplex_setting)
9894 update_link = true;
9895 } else {
9896 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
9897 update_link = true;
9898 if (link_info->advertising != link_info->auto_link_speeds ||
9899 link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)
9900 update_link = true;
9901 }
9902
9903 /* The last close may have shutdown the link, so need to call
9904 * PHY_CFG to bring it back up.
9905 */
9906 if (!bp->link_info.link_up)
9907 update_link = true;
9908
9909 if (!bnxt_eee_config_ok(bp))
9910 update_eee = true;
9911
9912 if (update_link)
9913 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
9914 else if (update_pause)
9915 rc = bnxt_hwrm_set_pause(bp);
9916 if (rc) {
9917 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
9918 rc);
9919 return rc;
9920 }
9921
9922 return rc;
9923 }
9924
9925 /* Common routine to pre-map certain register block to different GRC window.
9926 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
9927 * in PF and 3 windows in VF that can be customized to map in different
9928 * register blocks.
9929 */
9930 static void bnxt_preset_reg_win(struct bnxt *bp)
9931 {
9932 if (BNXT_PF(bp)) {
9933 /* CAG registers map to GRC window #4 */
9934 writel(BNXT_CAG_REG_BASE,
9935 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
9936 }
9937 }
9938
9939 static int bnxt_init_dflt_ring_mode(struct bnxt *bp);
9940
9941 static int bnxt_reinit_after_abort(struct bnxt *bp)
9942 {
9943 int rc;
9944
9945 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
9946 return -EBUSY;
9947
9948 if (bp->dev->reg_state == NETREG_UNREGISTERED)
9949 return -ENODEV;
9950
9951 rc = bnxt_fw_init_one(bp);
9952 if (!rc) {
9953 bnxt_clear_int_mode(bp);
9954 rc = bnxt_init_int_mode(bp);
9955 if (!rc) {
9956 clear_bit(BNXT_STATE_ABORT_ERR, &bp->state);
9957 set_bit(BNXT_STATE_FW_RESET_DET, &bp->state);
9958 }
9959 }
9960 return rc;
9961 }
9962
9963 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
9964 {
9965 int rc = 0;
9966
9967 bnxt_preset_reg_win(bp);
9968 netif_carrier_off(bp->dev);
9969 if (irq_re_init) {
9970 /* Reserve rings now if none were reserved at driver probe. */
9971 rc = bnxt_init_dflt_ring_mode(bp);
9972 if (rc) {
9973 netdev_err(bp->dev, "Failed to reserve default rings at open\n");
9974 return rc;
9975 }
9976 }
9977 rc = bnxt_reserve_rings(bp, irq_re_init);
9978 if (rc)
9979 return rc;
9980 if ((bp->flags & BNXT_FLAG_RFS) &&
9981 !(bp->flags & BNXT_FLAG_USING_MSIX)) {
9982 /* disable RFS if falling back to INTA */
9983 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
9984 bp->flags &= ~BNXT_FLAG_RFS;
9985 }
9986
9987 rc = bnxt_alloc_mem(bp, irq_re_init);
9988 if (rc) {
9989 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
9990 goto open_err_free_mem;
9991 }
9992
9993 if (irq_re_init) {
9994 bnxt_init_napi(bp);
9995 rc = bnxt_request_irq(bp);
9996 if (rc) {
9997 netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
9998 goto open_err_irq;
9999 }
10000 }
10001
10002 rc = bnxt_init_nic(bp, irq_re_init);
10003 if (rc) {
10004 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10005 goto open_err_irq;
10006 }
10007
10008 bnxt_enable_napi(bp);
10009 bnxt_debug_dev_init(bp);
10010
10011 if (link_re_init) {
10012 mutex_lock(&bp->link_lock);
10013 rc = bnxt_update_phy_setting(bp);
10014 mutex_unlock(&bp->link_lock);
10015 if (rc) {
10016 netdev_warn(bp->dev, "failed to update phy settings\n");
10017 if (BNXT_SINGLE_PF(bp)) {
10018 bp->link_info.phy_retry = true;
10019 bp->link_info.phy_retry_expires =
10020 jiffies + 5 * HZ;
10021 }
10022 }
10023 }
10024
10025 if (irq_re_init)
10026 udp_tunnel_nic_reset_ntf(bp->dev);
10027
10028 set_bit(BNXT_STATE_OPEN, &bp->state);
10029 bnxt_enable_int(bp);
10030 /* Enable TX queues */
10031 bnxt_tx_enable(bp);
10032 mod_timer(&bp->timer, jiffies + bp->current_interval);
10033 /* Poll link status and check for SFP+ module status */
10034 bnxt_get_port_module_status(bp);
10035
10036 /* VF-reps may need to be re-opened after the PF is re-opened */
10037 if (BNXT_PF(bp))
10038 bnxt_vf_reps_open(bp);
10039 return 0;
10040
10041 open_err_irq:
10042 bnxt_del_napi(bp);
10043
10044 open_err_free_mem:
10045 bnxt_free_skbs(bp);
10046 bnxt_free_irq(bp);
10047 bnxt_free_mem(bp, true);
10048 return rc;
10049 }
10050
10051 /* rtnl_lock held */
10052 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10053 {
10054 int rc = 0;
10055
10056 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state))
10057 rc = -EIO;
10058 if (!rc)
10059 rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
10060 if (rc) {
10061 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
10062 dev_close(bp->dev);
10063 }
10064 return rc;
10065 }
10066
10067 /* rtnl_lock held, open the NIC half way by allocating all resources, but
10068 * NAPI, IRQ, and TX are not enabled. This is mainly used for offline
10069 * self tests.
10070 */
10071 int bnxt_half_open_nic(struct bnxt *bp)
10072 {
10073 int rc = 0;
10074
10075 rc = bnxt_alloc_mem(bp, false);
10076 if (rc) {
10077 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
10078 goto half_open_err;
10079 }
10080 rc = bnxt_init_nic(bp, false);
10081 if (rc) {
10082 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
10083 goto half_open_err;
10084 }
10085 return 0;
10086
10087 half_open_err:
10088 bnxt_free_skbs(bp);
10089 bnxt_free_mem(bp, false);
10090 dev_close(bp->dev);
10091 return rc;
10092 }
10093
10094 /* rtnl_lock held, this call can only be made after a previous successful
10095 * call to bnxt_half_open_nic().
10096 */
10097 void bnxt_half_close_nic(struct bnxt *bp)
10098 {
10099 bnxt_hwrm_resource_free(bp, false, false);
10100 bnxt_free_skbs(bp);
10101 bnxt_free_mem(bp, false);
10102 }
10103
10104 static void bnxt_reenable_sriov(struct bnxt *bp)
10105 {
10106 if (BNXT_PF(bp)) {
10107 struct bnxt_pf_info *pf = &bp->pf;
10108 int n = pf->active_vfs;
10109
10110 if (n)
10111 bnxt_cfg_hw_sriov(bp, &n, true);
10112 }
10113 }
10114
10115 static int bnxt_open(struct net_device *dev)
10116 {
10117 struct bnxt *bp = netdev_priv(dev);
10118 int rc;
10119
10120 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) {
10121 rc = bnxt_reinit_after_abort(bp);
10122 if (rc) {
10123 if (rc == -EBUSY)
10124 netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n");
10125 else
10126 netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n");
10127 return -ENODEV;
10128 }
10129 }
10130
10131 rc = bnxt_hwrm_if_change(bp, true);
10132 if (rc)
10133 return rc;
10134 rc = __bnxt_open_nic(bp, true, true);
10135 if (rc) {
10136 bnxt_hwrm_if_change(bp, false);
10137 } else {
10138 if (test_and_clear_bit(BNXT_STATE_FW_RESET_DET, &bp->state)) {
10139 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10140 bnxt_ulp_start(bp, 0);
10141 bnxt_reenable_sriov(bp);
10142 }
10143 }
10144 bnxt_hwmon_open(bp);
10145 }
10146
10147 return rc;
10148 }
10149
10150 static bool bnxt_drv_busy(struct bnxt *bp)
10151 {
10152 return (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state) ||
10153 test_bit(BNXT_STATE_READ_STATS, &bp->state));
10154 }
10155
10156 static void bnxt_get_ring_stats(struct bnxt *bp,
10157 struct rtnl_link_stats64 *stats);
10158
10159 static void __bnxt_close_nic(struct bnxt *bp, bool irq_re_init,
10160 bool link_re_init)
10161 {
10162 /* Close the VF-reps before closing PF */
10163 if (BNXT_PF(bp))
10164 bnxt_vf_reps_close(bp);
10165
10166 /* Change device state to avoid TX queue wake up's */
10167 bnxt_tx_disable(bp);
10168
10169 clear_bit(BNXT_STATE_OPEN, &bp->state);
10170 smp_mb__after_atomic();
10171 while (bnxt_drv_busy(bp))
10172 msleep(20);
10173
10174 /* Flush rings and and disable interrupts */
10175 bnxt_shutdown_nic(bp, irq_re_init);
10176
10177 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
10178
10179 bnxt_debug_dev_exit(bp);
10180 bnxt_disable_napi(bp);
10181 del_timer_sync(&bp->timer);
10182 bnxt_free_skbs(bp);
10183
10184 /* Save ring stats before shutdown */
10185 if (bp->bnapi && irq_re_init)
10186 bnxt_get_ring_stats(bp, &bp->net_stats_prev);
10187 if (irq_re_init) {
10188 bnxt_free_irq(bp);
10189 bnxt_del_napi(bp);
10190 }
10191 bnxt_free_mem(bp, irq_re_init);
10192 }
10193
10194 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
10195 {
10196 int rc = 0;
10197
10198 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
10199 /* If we get here, it means firmware reset is in progress
10200 * while we are trying to close. We can safely proceed with
10201 * the close because we are holding rtnl_lock(). Some firmware
10202 * messages may fail as we proceed to close. We set the
10203 * ABORT_ERR flag here so that the FW reset thread will later
10204 * abort when it gets the rtnl_lock() and sees the flag.
10205 */
10206 netdev_warn(bp->dev, "FW reset in progress during close, FW reset will be aborted\n");
10207 set_bit(BNXT_STATE_ABORT_ERR, &bp->state);
10208 }
10209
10210 #ifdef CONFIG_BNXT_SRIOV
10211 if (bp->sriov_cfg) {
10212 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
10213 !bp->sriov_cfg,
10214 BNXT_SRIOV_CFG_WAIT_TMO);
10215 if (rc)
10216 netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
10217 }
10218 #endif
10219 __bnxt_close_nic(bp, irq_re_init, link_re_init);
10220 return rc;
10221 }
10222
10223 static int bnxt_close(struct net_device *dev)
10224 {
10225 struct bnxt *bp = netdev_priv(dev);
10226
10227 bnxt_hwmon_close(bp);
10228 bnxt_close_nic(bp, true, true);
10229 bnxt_hwrm_shutdown_link(bp);
10230 bnxt_hwrm_if_change(bp, false);
10231 return 0;
10232 }
10233
10234 static int bnxt_hwrm_port_phy_read(struct bnxt *bp, u16 phy_addr, u16 reg,
10235 u16 *val)
10236 {
10237 struct hwrm_port_phy_mdio_read_output *resp = bp->hwrm_cmd_resp_addr;
10238 struct hwrm_port_phy_mdio_read_input req = {0};
10239 int rc;
10240
10241 if (bp->hwrm_spec_code < 0x10a00)
10242 return -EOPNOTSUPP;
10243
10244 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_READ, -1, -1);
10245 req.port_id = cpu_to_le16(bp->pf.port_id);
10246 req.phy_addr = phy_addr;
10247 req.reg_addr = cpu_to_le16(reg & 0x1f);
10248 if (mdio_phy_id_is_c45(phy_addr)) {
10249 req.cl45_mdio = 1;
10250 req.phy_addr = mdio_phy_id_prtad(phy_addr);
10251 req.dev_addr = mdio_phy_id_devad(phy_addr);
10252 req.reg_addr = cpu_to_le16(reg);
10253 }
10254
10255 mutex_lock(&bp->hwrm_cmd_lock);
10256 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10257 if (!rc)
10258 *val = le16_to_cpu(resp->reg_data);
10259 mutex_unlock(&bp->hwrm_cmd_lock);
10260 return rc;
10261 }
10262
10263 static int bnxt_hwrm_port_phy_write(struct bnxt *bp, u16 phy_addr, u16 reg,
10264 u16 val)
10265 {
10266 struct hwrm_port_phy_mdio_write_input req = {0};
10267
10268 if (bp->hwrm_spec_code < 0x10a00)
10269 return -EOPNOTSUPP;
10270
10271 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_MDIO_WRITE, -1, -1);
10272 req.port_id = cpu_to_le16(bp->pf.port_id);
10273 req.phy_addr = phy_addr;
10274 req.reg_addr = cpu_to_le16(reg & 0x1f);
10275 if (mdio_phy_id_is_c45(phy_addr)) {
10276 req.cl45_mdio = 1;
10277 req.phy_addr = mdio_phy_id_prtad(phy_addr);
10278 req.dev_addr = mdio_phy_id_devad(phy_addr);
10279 req.reg_addr = cpu_to_le16(reg);
10280 }
10281 req.reg_data = cpu_to_le16(val);
10282
10283 return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10284 }
10285
10286 /* rtnl_lock held */
10287 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10288 {
10289 struct mii_ioctl_data *mdio = if_mii(ifr);
10290 struct bnxt *bp = netdev_priv(dev);
10291 int rc;
10292
10293 switch (cmd) {
10294 case SIOCGMIIPHY:
10295 mdio->phy_id = bp->link_info.phy_addr;
10296
10297 fallthrough;
10298 case SIOCGMIIREG: {
10299 u16 mii_regval = 0;
10300
10301 if (!netif_running(dev))
10302 return -EAGAIN;
10303
10304 rc = bnxt_hwrm_port_phy_read(bp, mdio->phy_id, mdio->reg_num,
10305 &mii_regval);
10306 mdio->val_out = mii_regval;
10307 return rc;
10308 }
10309
10310 case SIOCSMIIREG:
10311 if (!netif_running(dev))
10312 return -EAGAIN;
10313
10314 return bnxt_hwrm_port_phy_write(bp, mdio->phy_id, mdio->reg_num,
10315 mdio->val_in);
10316
10317 default:
10318 /* do nothing */
10319 break;
10320 }
10321 return -EOPNOTSUPP;
10322 }
10323
10324 static void bnxt_get_ring_stats(struct bnxt *bp,
10325 struct rtnl_link_stats64 *stats)
10326 {
10327 int i;
10328
10329 for (i = 0; i < bp->cp_nr_rings; i++) {
10330 struct bnxt_napi *bnapi = bp->bnapi[i];
10331 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
10332 u64 *sw = cpr->stats.sw_stats;
10333
10334 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_ucast_pkts);
10335 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10336 stats->rx_packets += BNXT_GET_RING_STATS64(sw, rx_bcast_pkts);
10337
10338 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_ucast_pkts);
10339 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_mcast_pkts);
10340 stats->tx_packets += BNXT_GET_RING_STATS64(sw, tx_bcast_pkts);
10341
10342 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_ucast_bytes);
10343 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_mcast_bytes);
10344 stats->rx_bytes += BNXT_GET_RING_STATS64(sw, rx_bcast_bytes);
10345
10346 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_ucast_bytes);
10347 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_mcast_bytes);
10348 stats->tx_bytes += BNXT_GET_RING_STATS64(sw, tx_bcast_bytes);
10349
10350 stats->rx_missed_errors +=
10351 BNXT_GET_RING_STATS64(sw, rx_discard_pkts);
10352
10353 stats->multicast += BNXT_GET_RING_STATS64(sw, rx_mcast_pkts);
10354
10355 stats->tx_dropped += BNXT_GET_RING_STATS64(sw, tx_error_pkts);
10356 }
10357 }
10358
10359 static void bnxt_add_prev_stats(struct bnxt *bp,
10360 struct rtnl_link_stats64 *stats)
10361 {
10362 struct rtnl_link_stats64 *prev_stats = &bp->net_stats_prev;
10363
10364 stats->rx_packets += prev_stats->rx_packets;
10365 stats->tx_packets += prev_stats->tx_packets;
10366 stats->rx_bytes += prev_stats->rx_bytes;
10367 stats->tx_bytes += prev_stats->tx_bytes;
10368 stats->rx_missed_errors += prev_stats->rx_missed_errors;
10369 stats->multicast += prev_stats->multicast;
10370 stats->tx_dropped += prev_stats->tx_dropped;
10371 }
10372
10373 static void
10374 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
10375 {
10376 struct bnxt *bp = netdev_priv(dev);
10377
10378 set_bit(BNXT_STATE_READ_STATS, &bp->state);
10379 /* Make sure bnxt_close_nic() sees that we are reading stats before
10380 * we check the BNXT_STATE_OPEN flag.
10381 */
10382 smp_mb__after_atomic();
10383 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10384 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10385 *stats = bp->net_stats_prev;
10386 return;
10387 }
10388
10389 bnxt_get_ring_stats(bp, stats);
10390 bnxt_add_prev_stats(bp, stats);
10391
10392 if (bp->flags & BNXT_FLAG_PORT_STATS) {
10393 u64 *rx = bp->port_stats.sw_stats;
10394 u64 *tx = bp->port_stats.sw_stats +
10395 BNXT_TX_PORT_STATS_BYTE_OFFSET / 8;
10396
10397 stats->rx_crc_errors =
10398 BNXT_GET_RX_PORT_STATS64(rx, rx_fcs_err_frames);
10399 stats->rx_frame_errors =
10400 BNXT_GET_RX_PORT_STATS64(rx, rx_align_err_frames);
10401 stats->rx_length_errors =
10402 BNXT_GET_RX_PORT_STATS64(rx, rx_undrsz_frames) +
10403 BNXT_GET_RX_PORT_STATS64(rx, rx_ovrsz_frames) +
10404 BNXT_GET_RX_PORT_STATS64(rx, rx_runt_frames);
10405 stats->rx_errors =
10406 BNXT_GET_RX_PORT_STATS64(rx, rx_false_carrier_frames) +
10407 BNXT_GET_RX_PORT_STATS64(rx, rx_jbr_frames);
10408 stats->collisions =
10409 BNXT_GET_TX_PORT_STATS64(tx, tx_total_collisions);
10410 stats->tx_fifo_errors =
10411 BNXT_GET_TX_PORT_STATS64(tx, tx_fifo_underruns);
10412 stats->tx_errors = BNXT_GET_TX_PORT_STATS64(tx, tx_err);
10413 }
10414 clear_bit(BNXT_STATE_READ_STATS, &bp->state);
10415 }
10416
10417 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
10418 {
10419 struct net_device *dev = bp->dev;
10420 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10421 struct netdev_hw_addr *ha;
10422 u8 *haddr;
10423 int mc_count = 0;
10424 bool update = false;
10425 int off = 0;
10426
10427 netdev_for_each_mc_addr(ha, dev) {
10428 if (mc_count >= BNXT_MAX_MC_ADDRS) {
10429 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10430 vnic->mc_list_count = 0;
10431 return false;
10432 }
10433 haddr = ha->addr;
10434 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
10435 memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
10436 update = true;
10437 }
10438 off += ETH_ALEN;
10439 mc_count++;
10440 }
10441 if (mc_count)
10442 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
10443
10444 if (mc_count != vnic->mc_list_count) {
10445 vnic->mc_list_count = mc_count;
10446 update = true;
10447 }
10448 return update;
10449 }
10450
10451 static bool bnxt_uc_list_updated(struct bnxt *bp)
10452 {
10453 struct net_device *dev = bp->dev;
10454 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10455 struct netdev_hw_addr *ha;
10456 int off = 0;
10457
10458 if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
10459 return true;
10460
10461 netdev_for_each_uc_addr(ha, dev) {
10462 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
10463 return true;
10464
10465 off += ETH_ALEN;
10466 }
10467 return false;
10468 }
10469
10470 static void bnxt_set_rx_mode(struct net_device *dev)
10471 {
10472 struct bnxt *bp = netdev_priv(dev);
10473 struct bnxt_vnic_info *vnic;
10474 bool mc_update = false;
10475 bool uc_update;
10476 u32 mask;
10477
10478 if (!test_bit(BNXT_STATE_OPEN, &bp->state))
10479 return;
10480
10481 vnic = &bp->vnic_info[0];
10482 mask = vnic->rx_mask;
10483 mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
10484 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
10485 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST |
10486 CFA_L2_SET_RX_MASK_REQ_MASK_BCAST);
10487
10488 if ((dev->flags & IFF_PROMISC) && bnxt_promisc_ok(bp))
10489 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10490
10491 uc_update = bnxt_uc_list_updated(bp);
10492
10493 if (dev->flags & IFF_BROADCAST)
10494 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
10495 if (dev->flags & IFF_ALLMULTI) {
10496 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10497 vnic->mc_list_count = 0;
10498 } else {
10499 mc_update = bnxt_mc_list_updated(bp, &mask);
10500 }
10501
10502 if (mask != vnic->rx_mask || uc_update || mc_update) {
10503 vnic->rx_mask = mask;
10504
10505 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
10506 bnxt_queue_sp_work(bp);
10507 }
10508 }
10509
10510 static int bnxt_cfg_rx_mode(struct bnxt *bp)
10511 {
10512 struct net_device *dev = bp->dev;
10513 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
10514 struct netdev_hw_addr *ha;
10515 int i, off = 0, rc;
10516 bool uc_update;
10517
10518 netif_addr_lock_bh(dev);
10519 uc_update = bnxt_uc_list_updated(bp);
10520 netif_addr_unlock_bh(dev);
10521
10522 if (!uc_update)
10523 goto skip_uc;
10524
10525 mutex_lock(&bp->hwrm_cmd_lock);
10526 for (i = 1; i < vnic->uc_filter_count; i++) {
10527 struct hwrm_cfa_l2_filter_free_input req = {0};
10528
10529 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
10530 -1);
10531
10532 req.l2_filter_id = vnic->fw_l2_filter_id[i];
10533
10534 rc = _hwrm_send_message(bp, &req, sizeof(req),
10535 HWRM_CMD_TIMEOUT);
10536 }
10537 mutex_unlock(&bp->hwrm_cmd_lock);
10538
10539 vnic->uc_filter_count = 1;
10540
10541 netif_addr_lock_bh(dev);
10542 if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
10543 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
10544 } else {
10545 netdev_for_each_uc_addr(ha, dev) {
10546 memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
10547 off += ETH_ALEN;
10548 vnic->uc_filter_count++;
10549 }
10550 }
10551 netif_addr_unlock_bh(dev);
10552
10553 for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
10554 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
10555 if (rc) {
10556 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
10557 rc);
10558 vnic->uc_filter_count = i;
10559 return rc;
10560 }
10561 }
10562
10563 skip_uc:
10564 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
10565 if (rc && vnic->mc_list_count) {
10566 netdev_info(bp->dev, "Failed setting MC filters rc: %d, turning on ALL_MCAST mode\n",
10567 rc);
10568 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
10569 vnic->mc_list_count = 0;
10570 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
10571 }
10572 if (rc)
10573 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %d\n",
10574 rc);
10575
10576 return rc;
10577 }
10578
10579 static bool bnxt_can_reserve_rings(struct bnxt *bp)
10580 {
10581 #ifdef CONFIG_BNXT_SRIOV
10582 if (BNXT_NEW_RM(bp) && BNXT_VF(bp)) {
10583 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
10584
10585 /* No minimum rings were provisioned by the PF. Don't
10586 * reserve rings by default when device is down.
10587 */
10588 if (hw_resc->min_tx_rings || hw_resc->resv_tx_rings)
10589 return true;
10590
10591 if (!netif_running(bp->dev))
10592 return false;
10593 }
10594 #endif
10595 return true;
10596 }
10597
10598 /* If the chip and firmware supports RFS */
10599 static bool bnxt_rfs_supported(struct bnxt *bp)
10600 {
10601 if (bp->flags & BNXT_FLAG_CHIP_P5) {
10602 if (bp->fw_cap & BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2)
10603 return true;
10604 return false;
10605 }
10606 if (BNXT_PF(bp) && !BNXT_CHIP_TYPE_NITRO_A0(bp))
10607 return true;
10608 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
10609 return true;
10610 return false;
10611 }
10612
10613 /* If runtime conditions support RFS */
10614 static bool bnxt_rfs_capable(struct bnxt *bp)
10615 {
10616 #ifdef CONFIG_RFS_ACCEL
10617 int vnics, max_vnics, max_rss_ctxs;
10618
10619 if (bp->flags & BNXT_FLAG_CHIP_P5)
10620 return bnxt_rfs_supported(bp);
10621 if (!(bp->flags & BNXT_FLAG_MSIX_CAP) || !bnxt_can_reserve_rings(bp))
10622 return false;
10623
10624 vnics = 1 + bp->rx_nr_rings;
10625 max_vnics = bnxt_get_max_func_vnics(bp);
10626 max_rss_ctxs = bnxt_get_max_func_rss_ctxs(bp);
10627
10628 /* RSS contexts not a limiting factor */
10629 if (bp->flags & BNXT_FLAG_NEW_RSS_CAP)
10630 max_rss_ctxs = max_vnics;
10631 if (vnics > max_vnics || vnics > max_rss_ctxs) {
10632 if (bp->rx_nr_rings > 1)
10633 netdev_warn(bp->dev,
10634 "Not enough resources to support NTUPLE filters, enough resources for up to %d rx rings\n",
10635 min(max_rss_ctxs - 1, max_vnics - 1));
10636 return false;
10637 }
10638
10639 if (!BNXT_NEW_RM(bp))
10640 return true;
10641
10642 if (vnics == bp->hw_resc.resv_vnics)
10643 return true;
10644
10645 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, vnics);
10646 if (vnics <= bp->hw_resc.resv_vnics)
10647 return true;
10648
10649 netdev_warn(bp->dev, "Unable to reserve resources to support NTUPLE filters.\n");
10650 bnxt_hwrm_reserve_rings(bp, 0, 0, 0, 0, 0, 1);
10651 return false;
10652 #else
10653 return false;
10654 #endif
10655 }
10656
10657 static netdev_features_t bnxt_fix_features(struct net_device *dev,
10658 netdev_features_t features)
10659 {
10660 struct bnxt *bp = netdev_priv(dev);
10661 netdev_features_t vlan_features;
10662
10663 if ((features & NETIF_F_NTUPLE) && !bnxt_rfs_capable(bp))
10664 features &= ~NETIF_F_NTUPLE;
10665
10666 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
10667 features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
10668
10669 if (!(features & NETIF_F_GRO))
10670 features &= ~NETIF_F_GRO_HW;
10671
10672 if (features & NETIF_F_GRO_HW)
10673 features &= ~NETIF_F_LRO;
10674
10675 /* Both CTAG and STAG VLAN accelaration on the RX side have to be
10676 * turned on or off together.
10677 */
10678 vlan_features = features & BNXT_HW_FEATURE_VLAN_ALL_RX;
10679 if (vlan_features != BNXT_HW_FEATURE_VLAN_ALL_RX) {
10680 if (dev->features & BNXT_HW_FEATURE_VLAN_ALL_RX)
10681 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
10682 else if (vlan_features)
10683 features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
10684 }
10685 #ifdef CONFIG_BNXT_SRIOV
10686 if (BNXT_VF(bp) && bp->vf.vlan)
10687 features &= ~BNXT_HW_FEATURE_VLAN_ALL_RX;
10688 #endif
10689 return features;
10690 }
10691
10692 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
10693 {
10694 struct bnxt *bp = netdev_priv(dev);
10695 u32 flags = bp->flags;
10696 u32 changes;
10697 int rc = 0;
10698 bool re_init = false;
10699 bool update_tpa = false;
10700
10701 flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
10702 if (features & NETIF_F_GRO_HW)
10703 flags |= BNXT_FLAG_GRO;
10704 else if (features & NETIF_F_LRO)
10705 flags |= BNXT_FLAG_LRO;
10706
10707 if (bp->flags & BNXT_FLAG_NO_AGG_RINGS)
10708 flags &= ~BNXT_FLAG_TPA;
10709
10710 if (features & BNXT_HW_FEATURE_VLAN_ALL_RX)
10711 flags |= BNXT_FLAG_STRIP_VLAN;
10712
10713 if (features & NETIF_F_NTUPLE)
10714 flags |= BNXT_FLAG_RFS;
10715
10716 changes = flags ^ bp->flags;
10717 if (changes & BNXT_FLAG_TPA) {
10718 update_tpa = true;
10719 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
10720 (flags & BNXT_FLAG_TPA) == 0 ||
10721 (bp->flags & BNXT_FLAG_CHIP_P5))
10722 re_init = true;
10723 }
10724
10725 if (changes & ~BNXT_FLAG_TPA)
10726 re_init = true;
10727
10728 if (flags != bp->flags) {
10729 u32 old_flags = bp->flags;
10730
10731 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
10732 bp->flags = flags;
10733 if (update_tpa)
10734 bnxt_set_ring_params(bp);
10735 return rc;
10736 }
10737
10738 if (re_init) {
10739 bnxt_close_nic(bp, false, false);
10740 bp->flags = flags;
10741 if (update_tpa)
10742 bnxt_set_ring_params(bp);
10743
10744 return bnxt_open_nic(bp, false, false);
10745 }
10746 if (update_tpa) {
10747 bp->flags = flags;
10748 rc = bnxt_set_tpa(bp,
10749 (flags & BNXT_FLAG_TPA) ?
10750 true : false);
10751 if (rc)
10752 bp->flags = old_flags;
10753 }
10754 }
10755 return rc;
10756 }
10757
10758 int bnxt_dbg_hwrm_rd_reg(struct bnxt *bp, u32 reg_off, u16 num_words,
10759 u32 *reg_buf)
10760 {
10761 struct hwrm_dbg_read_direct_output *resp = bp->hwrm_cmd_resp_addr;
10762 struct hwrm_dbg_read_direct_input req = {0};
10763 __le32 *dbg_reg_buf;
10764 dma_addr_t mapping;
10765 int rc, i;
10766
10767 dbg_reg_buf = dma_alloc_coherent(&bp->pdev->dev, num_words * 4,
10768 &mapping, GFP_KERNEL);
10769 if (!dbg_reg_buf)
10770 return -ENOMEM;
10771 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_READ_DIRECT, -1, -1);
10772 req.host_dest_addr = cpu_to_le64(mapping);
10773 req.read_addr = cpu_to_le32(reg_off + CHIMP_REG_VIEW_ADDR);
10774 req.read_len32 = cpu_to_le32(num_words);
10775 mutex_lock(&bp->hwrm_cmd_lock);
10776 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10777 if (rc || resp->error_code) {
10778 rc = -EIO;
10779 goto dbg_rd_reg_exit;
10780 }
10781 for (i = 0; i < num_words; i++)
10782 reg_buf[i] = le32_to_cpu(dbg_reg_buf[i]);
10783
10784 dbg_rd_reg_exit:
10785 mutex_unlock(&bp->hwrm_cmd_lock);
10786 dma_free_coherent(&bp->pdev->dev, num_words * 4, dbg_reg_buf, mapping);
10787 return rc;
10788 }
10789
10790 static int bnxt_dbg_hwrm_ring_info_get(struct bnxt *bp, u8 ring_type,
10791 u32 ring_id, u32 *prod, u32 *cons)
10792 {
10793 struct hwrm_dbg_ring_info_get_output *resp = bp->hwrm_cmd_resp_addr;
10794 struct hwrm_dbg_ring_info_get_input req = {0};
10795 int rc;
10796
10797 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_DBG_RING_INFO_GET, -1, -1);
10798 req.ring_type = ring_type;
10799 req.fw_ring_id = cpu_to_le32(ring_id);
10800 mutex_lock(&bp->hwrm_cmd_lock);
10801 rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
10802 if (!rc) {
10803 *prod = le32_to_cpu(resp->producer_index);
10804 *cons = le32_to_cpu(resp->consumer_index);
10805 }
10806 mutex_unlock(&bp->hwrm_cmd_lock);
10807 return rc;
10808 }
10809
10810 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
10811 {
10812 struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
10813 int i = bnapi->index;
10814
10815 if (!txr)
10816 return;
10817
10818 netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
10819 i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
10820 txr->tx_cons);
10821 }
10822
10823 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
10824 {
10825 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
10826 int i = bnapi->index;
10827
10828 if (!rxr)
10829 return;
10830
10831 netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
10832 i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
10833 rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
10834 rxr->rx_sw_agg_prod);
10835 }
10836
10837 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
10838 {
10839 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
10840 int i = bnapi->index;
10841
10842 netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
10843 i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
10844 }
10845
10846 static void bnxt_dbg_dump_states(struct bnxt *bp)
10847 {
10848 int i;
10849 struct bnxt_napi *bnapi;
10850
10851 for (i = 0; i < bp->cp_nr_rings; i++) {
10852 bnapi = bp->bnapi[i];
10853 if (netif_msg_drv(bp)) {
10854 bnxt_dump_tx_sw_state(bnapi);
10855 bnxt_dump_rx_sw_state(bnapi);
10856 bnxt_dump_cp_sw_state(bnapi);
10857 }
10858 }
10859 }
10860
10861 static int bnxt_hwrm_rx_ring_reset(struct bnxt *bp, int ring_nr)
10862 {
10863 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[ring_nr];
10864 struct hwrm_ring_reset_input req = {0};
10865 struct bnxt_napi *bnapi = rxr->bnapi;
10866 struct bnxt_cp_ring_info *cpr;
10867 u16 cp_ring_id;
10868
10869 cpr = &bnapi->cp_ring;
10870 cp_ring_id = cpr->cp_ring_struct.fw_ring_id;
10871 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_RESET, cp_ring_id, -1);
10872 req.ring_type = RING_RESET_REQ_RING_TYPE_RX_RING_GRP;
10873 req.ring_id = cpu_to_le16(bp->grp_info[bnapi->index].fw_grp_id);
10874 return hwrm_send_message_silent(bp, &req, sizeof(req),
10875 HWRM_CMD_TIMEOUT);
10876 }
10877
10878 static void bnxt_reset_task(struct bnxt *bp, bool silent)
10879 {
10880 if (!silent)
10881 bnxt_dbg_dump_states(bp);
10882 if (netif_running(bp->dev)) {
10883 int rc;
10884
10885 if (silent) {
10886 bnxt_close_nic(bp, false, false);
10887 bnxt_open_nic(bp, false, false);
10888 } else {
10889 bnxt_ulp_stop(bp);
10890 bnxt_close_nic(bp, true, false);
10891 rc = bnxt_open_nic(bp, true, false);
10892 bnxt_ulp_start(bp, rc);
10893 }
10894 }
10895 }
10896
10897 static void bnxt_tx_timeout(struct net_device *dev, unsigned int txqueue)
10898 {
10899 struct bnxt *bp = netdev_priv(dev);
10900
10901 netdev_err(bp->dev, "TX timeout detected, starting reset task!\n");
10902 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
10903 bnxt_queue_sp_work(bp);
10904 }
10905
10906 static void bnxt_fw_health_check(struct bnxt *bp)
10907 {
10908 struct bnxt_fw_health *fw_health = bp->fw_health;
10909 u32 val;
10910
10911 if (!fw_health->enabled || test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
10912 return;
10913
10914 if (fw_health->tmr_counter) {
10915 fw_health->tmr_counter--;
10916 return;
10917 }
10918
10919 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
10920 if (val == fw_health->last_fw_heartbeat)
10921 goto fw_reset;
10922
10923 fw_health->last_fw_heartbeat = val;
10924
10925 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
10926 if (val != fw_health->last_fw_reset_cnt)
10927 goto fw_reset;
10928
10929 fw_health->tmr_counter = fw_health->tmr_multiplier;
10930 return;
10931
10932 fw_reset:
10933 set_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event);
10934 bnxt_queue_sp_work(bp);
10935 }
10936
10937 static void bnxt_timer(struct timer_list *t)
10938 {
10939 struct bnxt *bp = from_timer(bp, t, timer);
10940 struct net_device *dev = bp->dev;
10941
10942 if (!netif_running(dev) || !test_bit(BNXT_STATE_OPEN, &bp->state))
10943 return;
10944
10945 if (atomic_read(&bp->intr_sem) != 0)
10946 goto bnxt_restart_timer;
10947
10948 if (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)
10949 bnxt_fw_health_check(bp);
10950
10951 if (bp->link_info.link_up && bp->stats_coal_ticks) {
10952 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
10953 bnxt_queue_sp_work(bp);
10954 }
10955
10956 if (bnxt_tc_flower_enabled(bp)) {
10957 set_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event);
10958 bnxt_queue_sp_work(bp);
10959 }
10960
10961 #ifdef CONFIG_RFS_ACCEL
10962 if ((bp->flags & BNXT_FLAG_RFS) && bp->ntp_fltr_count) {
10963 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
10964 bnxt_queue_sp_work(bp);
10965 }
10966 #endif /*CONFIG_RFS_ACCEL*/
10967
10968 if (bp->link_info.phy_retry) {
10969 if (time_after(jiffies, bp->link_info.phy_retry_expires)) {
10970 bp->link_info.phy_retry = false;
10971 netdev_warn(bp->dev, "failed to update phy settings after maximum retries.\n");
10972 } else {
10973 set_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event);
10974 bnxt_queue_sp_work(bp);
10975 }
10976 }
10977
10978 if ((bp->flags & BNXT_FLAG_CHIP_P5) && !bp->chip_rev &&
10979 netif_carrier_ok(dev)) {
10980 set_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event);
10981 bnxt_queue_sp_work(bp);
10982 }
10983 bnxt_restart_timer:
10984 mod_timer(&bp->timer, jiffies + bp->current_interval);
10985 }
10986
10987 static void bnxt_rtnl_lock_sp(struct bnxt *bp)
10988 {
10989 /* We are called from bnxt_sp_task which has BNXT_STATE_IN_SP_TASK
10990 * set. If the device is being closed, bnxt_close() may be holding
10991 * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear. So we
10992 * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
10993 */
10994 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
10995 rtnl_lock();
10996 }
10997
10998 static void bnxt_rtnl_unlock_sp(struct bnxt *bp)
10999 {
11000 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11001 rtnl_unlock();
11002 }
11003
11004 /* Only called from bnxt_sp_task() */
11005 static void bnxt_reset(struct bnxt *bp, bool silent)
11006 {
11007 bnxt_rtnl_lock_sp(bp);
11008 if (test_bit(BNXT_STATE_OPEN, &bp->state))
11009 bnxt_reset_task(bp, silent);
11010 bnxt_rtnl_unlock_sp(bp);
11011 }
11012
11013 /* Only called from bnxt_sp_task() */
11014 static void bnxt_rx_ring_reset(struct bnxt *bp)
11015 {
11016 int i;
11017
11018 bnxt_rtnl_lock_sp(bp);
11019 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11020 bnxt_rtnl_unlock_sp(bp);
11021 return;
11022 }
11023 /* Disable and flush TPA before resetting the RX ring */
11024 if (bp->flags & BNXT_FLAG_TPA)
11025 bnxt_set_tpa(bp, false);
11026 for (i = 0; i < bp->rx_nr_rings; i++) {
11027 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
11028 struct bnxt_cp_ring_info *cpr;
11029 int rc;
11030
11031 if (!rxr->bnapi->in_reset)
11032 continue;
11033
11034 rc = bnxt_hwrm_rx_ring_reset(bp, i);
11035 if (rc) {
11036 if (rc == -EINVAL || rc == -EOPNOTSUPP)
11037 netdev_info_once(bp->dev, "RX ring reset not supported by firmware, falling back to global reset\n");
11038 else
11039 netdev_warn(bp->dev, "RX ring reset failed, rc = %d, falling back to global reset\n",
11040 rc);
11041 bnxt_reset_task(bp, true);
11042 break;
11043 }
11044 bnxt_free_one_rx_ring_skbs(bp, i);
11045 rxr->rx_prod = 0;
11046 rxr->rx_agg_prod = 0;
11047 rxr->rx_sw_agg_prod = 0;
11048 rxr->rx_next_cons = 0;
11049 rxr->bnapi->in_reset = false;
11050 bnxt_alloc_one_rx_ring(bp, i);
11051 cpr = &rxr->bnapi->cp_ring;
11052 cpr->sw_stats.rx.rx_resets++;
11053 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11054 bnxt_db_write(bp, &rxr->rx_agg_db, rxr->rx_agg_prod);
11055 bnxt_db_write(bp, &rxr->rx_db, rxr->rx_prod);
11056 }
11057 if (bp->flags & BNXT_FLAG_TPA)
11058 bnxt_set_tpa(bp, true);
11059 bnxt_rtnl_unlock_sp(bp);
11060 }
11061
11062 static void bnxt_fw_reset_close(struct bnxt *bp)
11063 {
11064 bnxt_ulp_stop(bp);
11065 /* When firmware is in fatal state, quiesce device and disable
11066 * bus master to prevent any potential bad DMAs before freeing
11067 * kernel memory.
11068 */
11069 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) {
11070 u16 val = 0;
11071
11072 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
11073 if (val == 0xffff)
11074 bp->fw_reset_min_dsecs = 0;
11075 bnxt_tx_disable(bp);
11076 bnxt_disable_napi(bp);
11077 bnxt_disable_int_sync(bp);
11078 bnxt_free_irq(bp);
11079 bnxt_clear_int_mode(bp);
11080 pci_disable_device(bp->pdev);
11081 }
11082 __bnxt_close_nic(bp, true, false);
11083 bnxt_clear_int_mode(bp);
11084 bnxt_hwrm_func_drv_unrgtr(bp);
11085 if (pci_is_enabled(bp->pdev))
11086 pci_disable_device(bp->pdev);
11087 bnxt_free_ctx_mem(bp);
11088 kfree(bp->ctx);
11089 bp->ctx = NULL;
11090 }
11091
11092 static bool is_bnxt_fw_ok(struct bnxt *bp)
11093 {
11094 struct bnxt_fw_health *fw_health = bp->fw_health;
11095 bool no_heartbeat = false, has_reset = false;
11096 u32 val;
11097
11098 val = bnxt_fw_health_readl(bp, BNXT_FW_HEARTBEAT_REG);
11099 if (val == fw_health->last_fw_heartbeat)
11100 no_heartbeat = true;
11101
11102 val = bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG);
11103 if (val != fw_health->last_fw_reset_cnt)
11104 has_reset = true;
11105
11106 if (!no_heartbeat && has_reset)
11107 return true;
11108
11109 return false;
11110 }
11111
11112 /* rtnl_lock is acquired before calling this function */
11113 static void bnxt_force_fw_reset(struct bnxt *bp)
11114 {
11115 struct bnxt_fw_health *fw_health = bp->fw_health;
11116 u32 wait_dsecs;
11117
11118 if (!test_bit(BNXT_STATE_OPEN, &bp->state) ||
11119 test_bit(BNXT_STATE_IN_FW_RESET, &bp->state))
11120 return;
11121
11122 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11123 bnxt_fw_reset_close(bp);
11124 wait_dsecs = fw_health->master_func_wait_dsecs;
11125 if (fw_health->master) {
11126 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU)
11127 wait_dsecs = 0;
11128 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
11129 } else {
11130 bp->fw_reset_timestamp = jiffies + wait_dsecs * HZ / 10;
11131 wait_dsecs = fw_health->normal_func_wait_dsecs;
11132 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11133 }
11134
11135 bp->fw_reset_min_dsecs = fw_health->post_reset_wait_dsecs;
11136 bp->fw_reset_max_dsecs = fw_health->post_reset_max_wait_dsecs;
11137 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
11138 }
11139
11140 void bnxt_fw_exception(struct bnxt *bp)
11141 {
11142 netdev_warn(bp->dev, "Detected firmware fatal condition, initiating reset\n");
11143 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
11144 bnxt_rtnl_lock_sp(bp);
11145 bnxt_force_fw_reset(bp);
11146 bnxt_rtnl_unlock_sp(bp);
11147 }
11148
11149 /* Returns the number of registered VFs, or 1 if VF configuration is pending, or
11150 * < 0 on error.
11151 */
11152 static int bnxt_get_registered_vfs(struct bnxt *bp)
11153 {
11154 #ifdef CONFIG_BNXT_SRIOV
11155 int rc;
11156
11157 if (!BNXT_PF(bp))
11158 return 0;
11159
11160 rc = bnxt_hwrm_func_qcfg(bp);
11161 if (rc) {
11162 netdev_err(bp->dev, "func_qcfg cmd failed, rc = %d\n", rc);
11163 return rc;
11164 }
11165 if (bp->pf.registered_vfs)
11166 return bp->pf.registered_vfs;
11167 if (bp->sriov_cfg)
11168 return 1;
11169 #endif
11170 return 0;
11171 }
11172
11173 void bnxt_fw_reset(struct bnxt *bp)
11174 {
11175 bnxt_rtnl_lock_sp(bp);
11176 if (test_bit(BNXT_STATE_OPEN, &bp->state) &&
11177 !test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
11178 int n = 0, tmo;
11179
11180 set_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11181 if (bp->pf.active_vfs &&
11182 !test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))
11183 n = bnxt_get_registered_vfs(bp);
11184 if (n < 0) {
11185 netdev_err(bp->dev, "Firmware reset aborted, rc = %d\n",
11186 n);
11187 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11188 dev_close(bp->dev);
11189 goto fw_reset_exit;
11190 } else if (n > 0) {
11191 u16 vf_tmo_dsecs = n * 10;
11192
11193 if (bp->fw_reset_max_dsecs < vf_tmo_dsecs)
11194 bp->fw_reset_max_dsecs = vf_tmo_dsecs;
11195 bp->fw_reset_state =
11196 BNXT_FW_RESET_STATE_POLL_VF;
11197 bnxt_queue_fw_reset_work(bp, HZ / 10);
11198 goto fw_reset_exit;
11199 }
11200 bnxt_fw_reset_close(bp);
11201 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11202 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
11203 tmo = HZ / 10;
11204 } else {
11205 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11206 tmo = bp->fw_reset_min_dsecs * HZ / 10;
11207 }
11208 bnxt_queue_fw_reset_work(bp, tmo);
11209 }
11210 fw_reset_exit:
11211 bnxt_rtnl_unlock_sp(bp);
11212 }
11213
11214 static void bnxt_chk_missed_irq(struct bnxt *bp)
11215 {
11216 int i;
11217
11218 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
11219 return;
11220
11221 for (i = 0; i < bp->cp_nr_rings; i++) {
11222 struct bnxt_napi *bnapi = bp->bnapi[i];
11223 struct bnxt_cp_ring_info *cpr;
11224 u32 fw_ring_id;
11225 int j;
11226
11227 if (!bnapi)
11228 continue;
11229
11230 cpr = &bnapi->cp_ring;
11231 for (j = 0; j < 2; j++) {
11232 struct bnxt_cp_ring_info *cpr2 = cpr->cp_ring_arr[j];
11233 u32 val[2];
11234
11235 if (!cpr2 || cpr2->has_more_work ||
11236 !bnxt_has_work(bp, cpr2))
11237 continue;
11238
11239 if (cpr2->cp_raw_cons != cpr2->last_cp_raw_cons) {
11240 cpr2->last_cp_raw_cons = cpr2->cp_raw_cons;
11241 continue;
11242 }
11243 fw_ring_id = cpr2->cp_ring_struct.fw_ring_id;
11244 bnxt_dbg_hwrm_ring_info_get(bp,
11245 DBG_RING_INFO_GET_REQ_RING_TYPE_L2_CMPL,
11246 fw_ring_id, &val[0], &val[1]);
11247 cpr->sw_stats.cmn.missed_irqs++;
11248 }
11249 }
11250 }
11251
11252 static void bnxt_cfg_ntp_filters(struct bnxt *);
11253
11254 static void bnxt_init_ethtool_link_settings(struct bnxt *bp)
11255 {
11256 struct bnxt_link_info *link_info = &bp->link_info;
11257
11258 if (BNXT_AUTO_MODE(link_info->auto_mode)) {
11259 link_info->autoneg = BNXT_AUTONEG_SPEED;
11260 if (bp->hwrm_spec_code >= 0x10201) {
11261 if (link_info->auto_pause_setting &
11262 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
11263 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11264 } else {
11265 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
11266 }
11267 link_info->advertising = link_info->auto_link_speeds;
11268 link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;
11269 } else {
11270 link_info->req_link_speed = link_info->force_link_speed;
11271 link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;
11272 if (link_info->force_pam4_link_speed) {
11273 link_info->req_link_speed =
11274 link_info->force_pam4_link_speed;
11275 link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;
11276 }
11277 link_info->req_duplex = link_info->duplex_setting;
11278 }
11279 if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
11280 link_info->req_flow_ctrl =
11281 link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
11282 else
11283 link_info->req_flow_ctrl = link_info->force_pause_setting;
11284 }
11285
11286 static void bnxt_fw_echo_reply(struct bnxt *bp)
11287 {
11288 struct bnxt_fw_health *fw_health = bp->fw_health;
11289 struct hwrm_func_echo_response_input req = {0};
11290
11291 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_ECHO_RESPONSE, -1, -1);
11292 req.event_data1 = cpu_to_le32(fw_health->echo_req_data1);
11293 req.event_data2 = cpu_to_le32(fw_health->echo_req_data2);
11294 hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11295 }
11296
11297 static void bnxt_sp_task(struct work_struct *work)
11298 {
11299 struct bnxt *bp = container_of(work, struct bnxt, sp_task);
11300
11301 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11302 smp_mb__after_atomic();
11303 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
11304 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11305 return;
11306 }
11307
11308 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
11309 bnxt_cfg_rx_mode(bp);
11310
11311 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
11312 bnxt_cfg_ntp_filters(bp);
11313 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
11314 bnxt_hwrm_exec_fwd_req(bp);
11315 if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event)) {
11316 bnxt_hwrm_port_qstats(bp, 0);
11317 bnxt_hwrm_port_qstats_ext(bp, 0);
11318 bnxt_accumulate_all_stats(bp);
11319 }
11320
11321 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
11322 int rc;
11323
11324 mutex_lock(&bp->link_lock);
11325 if (test_and_clear_bit(BNXT_LINK_SPEED_CHNG_SP_EVENT,
11326 &bp->sp_event))
11327 bnxt_hwrm_phy_qcaps(bp);
11328
11329 rc = bnxt_update_link(bp, true);
11330 if (rc)
11331 netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
11332 rc);
11333
11334 if (test_and_clear_bit(BNXT_LINK_CFG_CHANGE_SP_EVENT,
11335 &bp->sp_event))
11336 bnxt_init_ethtool_link_settings(bp);
11337 mutex_unlock(&bp->link_lock);
11338 }
11339 if (test_and_clear_bit(BNXT_UPDATE_PHY_SP_EVENT, &bp->sp_event)) {
11340 int rc;
11341
11342 mutex_lock(&bp->link_lock);
11343 rc = bnxt_update_phy_setting(bp);
11344 mutex_unlock(&bp->link_lock);
11345 if (rc) {
11346 netdev_warn(bp->dev, "update phy settings retry failed\n");
11347 } else {
11348 bp->link_info.phy_retry = false;
11349 netdev_info(bp->dev, "update phy settings retry succeeded\n");
11350 }
11351 }
11352 if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event)) {
11353 mutex_lock(&bp->link_lock);
11354 bnxt_get_port_module_status(bp);
11355 mutex_unlock(&bp->link_lock);
11356 }
11357
11358 if (test_and_clear_bit(BNXT_FLOW_STATS_SP_EVENT, &bp->sp_event))
11359 bnxt_tc_flow_stats_work(bp);
11360
11361 if (test_and_clear_bit(BNXT_RING_COAL_NOW_SP_EVENT, &bp->sp_event))
11362 bnxt_chk_missed_irq(bp);
11363
11364 if (test_and_clear_bit(BNXT_FW_ECHO_REQUEST_SP_EVENT, &bp->sp_event))
11365 bnxt_fw_echo_reply(bp);
11366
11367 /* These functions below will clear BNXT_STATE_IN_SP_TASK. They
11368 * must be the last functions to be called before exiting.
11369 */
11370 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
11371 bnxt_reset(bp, false);
11372
11373 if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
11374 bnxt_reset(bp, true);
11375
11376 if (test_and_clear_bit(BNXT_RST_RING_SP_EVENT, &bp->sp_event))
11377 bnxt_rx_ring_reset(bp);
11378
11379 if (test_and_clear_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event))
11380 bnxt_devlink_health_report(bp, BNXT_FW_RESET_NOTIFY_SP_EVENT);
11381
11382 if (test_and_clear_bit(BNXT_FW_EXCEPTION_SP_EVENT, &bp->sp_event)) {
11383 if (!is_bnxt_fw_ok(bp))
11384 bnxt_devlink_health_report(bp,
11385 BNXT_FW_EXCEPTION_SP_EVENT);
11386 }
11387
11388 smp_mb__before_atomic();
11389 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
11390 }
11391
11392 /* Under rtnl_lock */
11393 int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
11394 int tx_xdp)
11395 {
11396 int max_rx, max_tx, tx_sets = 1;
11397 int tx_rings_needed, stats;
11398 int rx_rings = rx;
11399 int cp, vnics, rc;
11400
11401 if (tcs)
11402 tx_sets = tcs;
11403
11404 rc = bnxt_get_max_rings(bp, &max_rx, &max_tx, sh);
11405 if (rc)
11406 return rc;
11407
11408 if (max_rx < rx)
11409 return -ENOMEM;
11410
11411 tx_rings_needed = tx * tx_sets + tx_xdp;
11412 if (max_tx < tx_rings_needed)
11413 return -ENOMEM;
11414
11415 vnics = 1;
11416 if ((bp->flags & (BNXT_FLAG_RFS | BNXT_FLAG_CHIP_P5)) == BNXT_FLAG_RFS)
11417 vnics += rx_rings;
11418
11419 if (bp->flags & BNXT_FLAG_AGG_RINGS)
11420 rx_rings <<= 1;
11421 cp = sh ? max_t(int, tx_rings_needed, rx) : tx_rings_needed + rx;
11422 stats = cp;
11423 if (BNXT_NEW_RM(bp)) {
11424 cp += bnxt_get_ulp_msix_num(bp);
11425 stats += bnxt_get_ulp_stat_ctxs(bp);
11426 }
11427 return bnxt_hwrm_check_rings(bp, tx_rings_needed, rx_rings, rx, cp,
11428 stats, vnics);
11429 }
11430
11431 static void bnxt_unmap_bars(struct bnxt *bp, struct pci_dev *pdev)
11432 {
11433 if (bp->bar2) {
11434 pci_iounmap(pdev, bp->bar2);
11435 bp->bar2 = NULL;
11436 }
11437
11438 if (bp->bar1) {
11439 pci_iounmap(pdev, bp->bar1);
11440 bp->bar1 = NULL;
11441 }
11442
11443 if (bp->bar0) {
11444 pci_iounmap(pdev, bp->bar0);
11445 bp->bar0 = NULL;
11446 }
11447 }
11448
11449 static void bnxt_cleanup_pci(struct bnxt *bp)
11450 {
11451 bnxt_unmap_bars(bp, bp->pdev);
11452 pci_release_regions(bp->pdev);
11453 if (pci_is_enabled(bp->pdev))
11454 pci_disable_device(bp->pdev);
11455 }
11456
11457 static void bnxt_init_dflt_coal(struct bnxt *bp)
11458 {
11459 struct bnxt_coal *coal;
11460
11461 /* Tick values in micro seconds.
11462 * 1 coal_buf x bufs_per_record = 1 completion record.
11463 */
11464 coal = &bp->rx_coal;
11465 coal->coal_ticks = 10;
11466 coal->coal_bufs = 30;
11467 coal->coal_ticks_irq = 1;
11468 coal->coal_bufs_irq = 2;
11469 coal->idle_thresh = 50;
11470 coal->bufs_per_record = 2;
11471 coal->budget = 64; /* NAPI budget */
11472
11473 coal = &bp->tx_coal;
11474 coal->coal_ticks = 28;
11475 coal->coal_bufs = 30;
11476 coal->coal_ticks_irq = 2;
11477 coal->coal_bufs_irq = 2;
11478 coal->bufs_per_record = 1;
11479
11480 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS;
11481 }
11482
11483 static int bnxt_fw_init_one_p1(struct bnxt *bp)
11484 {
11485 int rc;
11486
11487 bp->fw_cap = 0;
11488 rc = bnxt_hwrm_ver_get(bp);
11489 bnxt_try_map_fw_health_reg(bp);
11490 if (rc) {
11491 rc = bnxt_try_recover_fw(bp);
11492 if (rc)
11493 return rc;
11494 rc = bnxt_hwrm_ver_get(bp);
11495 if (rc)
11496 return rc;
11497 }
11498
11499 if (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL) {
11500 rc = bnxt_alloc_kong_hwrm_resources(bp);
11501 if (rc)
11502 bp->fw_cap &= ~BNXT_FW_CAP_KONG_MB_CHNL;
11503 }
11504
11505 if ((bp->fw_cap & BNXT_FW_CAP_SHORT_CMD) ||
11506 bp->hwrm_max_ext_req_len > BNXT_HWRM_MAX_REQ_LEN) {
11507 rc = bnxt_alloc_hwrm_short_cmd_req(bp);
11508 if (rc)
11509 return rc;
11510 }
11511 bnxt_nvm_cfg_ver_get(bp);
11512
11513 rc = bnxt_hwrm_func_reset(bp);
11514 if (rc)
11515 return -ENODEV;
11516
11517 bnxt_hwrm_fw_set_time(bp);
11518 return 0;
11519 }
11520
11521 static int bnxt_fw_init_one_p2(struct bnxt *bp)
11522 {
11523 int rc;
11524
11525 /* Get the MAX capabilities for this function */
11526 rc = bnxt_hwrm_func_qcaps(bp);
11527 if (rc) {
11528 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
11529 rc);
11530 return -ENODEV;
11531 }
11532
11533 rc = bnxt_hwrm_cfa_adv_flow_mgnt_qcaps(bp);
11534 if (rc)
11535 netdev_warn(bp->dev, "hwrm query adv flow mgnt failure rc: %d\n",
11536 rc);
11537
11538 if (bnxt_alloc_fw_health(bp)) {
11539 netdev_warn(bp->dev, "no memory for firmware error recovery\n");
11540 } else {
11541 rc = bnxt_hwrm_error_recovery_qcfg(bp);
11542 if (rc)
11543 netdev_warn(bp->dev, "hwrm query error recovery failure rc: %d\n",
11544 rc);
11545 }
11546
11547 rc = bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false);
11548 if (rc)
11549 return -ENODEV;
11550
11551 bnxt_hwrm_func_qcfg(bp);
11552 bnxt_hwrm_vnic_qcaps(bp);
11553 bnxt_hwrm_port_led_qcaps(bp);
11554 bnxt_ethtool_init(bp);
11555 bnxt_dcb_init(bp);
11556 return 0;
11557 }
11558
11559 static void bnxt_set_dflt_rss_hash_type(struct bnxt *bp)
11560 {
11561 bp->flags &= ~BNXT_FLAG_UDP_RSS_CAP;
11562 bp->rss_hash_cfg = VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 |
11563 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 |
11564 VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 |
11565 VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6;
11566 if (BNXT_CHIP_P4_PLUS(bp) && bp->hwrm_spec_code >= 0x10501) {
11567 bp->flags |= BNXT_FLAG_UDP_RSS_CAP;
11568 bp->rss_hash_cfg |= VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 |
11569 VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6;
11570 }
11571 }
11572
11573 static void bnxt_set_dflt_rfs(struct bnxt *bp)
11574 {
11575 struct net_device *dev = bp->dev;
11576
11577 dev->hw_features &= ~NETIF_F_NTUPLE;
11578 dev->features &= ~NETIF_F_NTUPLE;
11579 bp->flags &= ~BNXT_FLAG_RFS;
11580 if (bnxt_rfs_supported(bp)) {
11581 dev->hw_features |= NETIF_F_NTUPLE;
11582 if (bnxt_rfs_capable(bp)) {
11583 bp->flags |= BNXT_FLAG_RFS;
11584 dev->features |= NETIF_F_NTUPLE;
11585 }
11586 }
11587 }
11588
11589 static void bnxt_fw_init_one_p3(struct bnxt *bp)
11590 {
11591 struct pci_dev *pdev = bp->pdev;
11592
11593 bnxt_set_dflt_rss_hash_type(bp);
11594 bnxt_set_dflt_rfs(bp);
11595
11596 bnxt_get_wol_settings(bp);
11597 if (bp->flags & BNXT_FLAG_WOL_CAP)
11598 device_set_wakeup_enable(&pdev->dev, bp->wol);
11599 else
11600 device_set_wakeup_capable(&pdev->dev, false);
11601
11602 bnxt_hwrm_set_cache_line_size(bp, cache_line_size());
11603 bnxt_hwrm_coal_params_qcaps(bp);
11604 }
11605
11606 static int bnxt_fw_init_one(struct bnxt *bp)
11607 {
11608 int rc;
11609
11610 rc = bnxt_fw_init_one_p1(bp);
11611 if (rc) {
11612 netdev_err(bp->dev, "Firmware init phase 1 failed\n");
11613 return rc;
11614 }
11615 rc = bnxt_fw_init_one_p2(bp);
11616 if (rc) {
11617 netdev_err(bp->dev, "Firmware init phase 2 failed\n");
11618 return rc;
11619 }
11620 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, false);
11621 if (rc)
11622 return rc;
11623
11624 /* In case fw capabilities have changed, destroy the unneeded
11625 * reporters and create newly capable ones.
11626 */
11627 bnxt_dl_fw_reporters_destroy(bp, false);
11628 bnxt_dl_fw_reporters_create(bp);
11629 bnxt_fw_init_one_p3(bp);
11630 return 0;
11631 }
11632
11633 static void bnxt_fw_reset_writel(struct bnxt *bp, int reg_idx)
11634 {
11635 struct bnxt_fw_health *fw_health = bp->fw_health;
11636 u32 reg = fw_health->fw_reset_seq_regs[reg_idx];
11637 u32 val = fw_health->fw_reset_seq_vals[reg_idx];
11638 u32 reg_type, reg_off, delay_msecs;
11639
11640 delay_msecs = fw_health->fw_reset_seq_delay_msec[reg_idx];
11641 reg_type = BNXT_FW_HEALTH_REG_TYPE(reg);
11642 reg_off = BNXT_FW_HEALTH_REG_OFF(reg);
11643 switch (reg_type) {
11644 case BNXT_FW_HEALTH_REG_TYPE_CFG:
11645 pci_write_config_dword(bp->pdev, reg_off, val);
11646 break;
11647 case BNXT_FW_HEALTH_REG_TYPE_GRC:
11648 writel(reg_off & BNXT_GRC_BASE_MASK,
11649 bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4);
11650 reg_off = (reg_off & BNXT_GRC_OFFSET_MASK) + 0x2000;
11651 fallthrough;
11652 case BNXT_FW_HEALTH_REG_TYPE_BAR0:
11653 writel(val, bp->bar0 + reg_off);
11654 break;
11655 case BNXT_FW_HEALTH_REG_TYPE_BAR1:
11656 writel(val, bp->bar1 + reg_off);
11657 break;
11658 }
11659 if (delay_msecs) {
11660 pci_read_config_dword(bp->pdev, 0, &val);
11661 msleep(delay_msecs);
11662 }
11663 }
11664
11665 static void bnxt_reset_all(struct bnxt *bp)
11666 {
11667 struct bnxt_fw_health *fw_health = bp->fw_health;
11668 int i, rc;
11669
11670 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11671 bnxt_fw_reset_via_optee(bp);
11672 bp->fw_reset_timestamp = jiffies;
11673 return;
11674 }
11675
11676 if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_HOST) {
11677 for (i = 0; i < fw_health->fw_reset_seq_cnt; i++)
11678 bnxt_fw_reset_writel(bp, i);
11679 } else if (fw_health->flags & ERROR_RECOVERY_QCFG_RESP_FLAGS_CO_CPU) {
11680 struct hwrm_fw_reset_input req = {0};
11681
11682 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FW_RESET, -1, -1);
11683 req.resp_addr = cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr);
11684 req.embedded_proc_type = FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP;
11685 req.selfrst_status = FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP;
11686 req.flags = FW_RESET_REQ_FLAGS_RESET_GRACEFUL;
11687 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
11688 if (rc != -ENODEV)
11689 netdev_warn(bp->dev, "Unable to reset FW rc=%d\n", rc);
11690 }
11691 bp->fw_reset_timestamp = jiffies;
11692 }
11693
11694 static bool bnxt_fw_reset_timeout(struct bnxt *bp)
11695 {
11696 return time_after(jiffies, bp->fw_reset_timestamp +
11697 (bp->fw_reset_max_dsecs * HZ / 10));
11698 }
11699
11700 static void bnxt_fw_reset_task(struct work_struct *work)
11701 {
11702 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work);
11703 int rc;
11704
11705 if (!test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) {
11706 netdev_err(bp->dev, "bnxt_fw_reset_task() called when not in fw reset mode!\n");
11707 return;
11708 }
11709
11710 switch (bp->fw_reset_state) {
11711 case BNXT_FW_RESET_STATE_POLL_VF: {
11712 int n = bnxt_get_registered_vfs(bp);
11713 int tmo;
11714
11715 if (n < 0) {
11716 netdev_err(bp->dev, "Firmware reset aborted, subsequent func_qcfg cmd failed, rc = %d, %d msecs since reset timestamp\n",
11717 n, jiffies_to_msecs(jiffies -
11718 bp->fw_reset_timestamp));
11719 goto fw_reset_abort;
11720 } else if (n > 0) {
11721 if (bnxt_fw_reset_timeout(bp)) {
11722 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11723 bp->fw_reset_state = 0;
11724 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n",
11725 n);
11726 return;
11727 }
11728 bnxt_queue_fw_reset_work(bp, HZ / 10);
11729 return;
11730 }
11731 bp->fw_reset_timestamp = jiffies;
11732 rtnl_lock();
11733 bnxt_fw_reset_close(bp);
11734 if (bp->fw_cap & BNXT_FW_CAP_ERR_RECOVER_RELOAD) {
11735 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW_DOWN;
11736 tmo = HZ / 10;
11737 } else {
11738 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11739 tmo = bp->fw_reset_min_dsecs * HZ / 10;
11740 }
11741 rtnl_unlock();
11742 bnxt_queue_fw_reset_work(bp, tmo);
11743 return;
11744 }
11745 case BNXT_FW_RESET_STATE_POLL_FW_DOWN: {
11746 u32 val;
11747
11748 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
11749 if (!(val & BNXT_FW_STATUS_SHUTDOWN) &&
11750 !bnxt_fw_reset_timeout(bp)) {
11751 bnxt_queue_fw_reset_work(bp, HZ / 5);
11752 return;
11753 }
11754
11755 if (!bp->fw_health->master) {
11756 u32 wait_dsecs = bp->fw_health->normal_func_wait_dsecs;
11757
11758 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11759 bnxt_queue_fw_reset_work(bp, wait_dsecs * HZ / 10);
11760 return;
11761 }
11762 bp->fw_reset_state = BNXT_FW_RESET_STATE_RESET_FW;
11763 }
11764 fallthrough;
11765 case BNXT_FW_RESET_STATE_RESET_FW:
11766 bnxt_reset_all(bp);
11767 bp->fw_reset_state = BNXT_FW_RESET_STATE_ENABLE_DEV;
11768 bnxt_queue_fw_reset_work(bp, bp->fw_reset_min_dsecs * HZ / 10);
11769 return;
11770 case BNXT_FW_RESET_STATE_ENABLE_DEV:
11771 bnxt_inv_fw_health_reg(bp);
11772 if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state) &&
11773 !bp->fw_reset_min_dsecs) {
11774 u16 val;
11775
11776 pci_read_config_word(bp->pdev, PCI_SUBSYSTEM_ID, &val);
11777 if (val == 0xffff) {
11778 if (bnxt_fw_reset_timeout(bp)) {
11779 netdev_err(bp->dev, "Firmware reset aborted, PCI config space invalid\n");
11780 goto fw_reset_abort;
11781 }
11782 bnxt_queue_fw_reset_work(bp, HZ / 1000);
11783 return;
11784 }
11785 }
11786 clear_bit(BNXT_STATE_FW_FATAL_COND, &bp->state);
11787 if (pci_enable_device(bp->pdev)) {
11788 netdev_err(bp->dev, "Cannot re-enable PCI device\n");
11789 goto fw_reset_abort;
11790 }
11791 pci_set_master(bp->pdev);
11792 bp->fw_reset_state = BNXT_FW_RESET_STATE_POLL_FW;
11793 fallthrough;
11794 case BNXT_FW_RESET_STATE_POLL_FW:
11795 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT;
11796 rc = __bnxt_hwrm_ver_get(bp, true);
11797 if (rc) {
11798 if (bnxt_fw_reset_timeout(bp)) {
11799 netdev_err(bp->dev, "Firmware reset aborted\n");
11800 goto fw_reset_abort_status;
11801 }
11802 bnxt_queue_fw_reset_work(bp, HZ / 5);
11803 return;
11804 }
11805 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
11806 bp->fw_reset_state = BNXT_FW_RESET_STATE_OPENING;
11807 fallthrough;
11808 case BNXT_FW_RESET_STATE_OPENING:
11809 while (!rtnl_trylock()) {
11810 bnxt_queue_fw_reset_work(bp, HZ / 10);
11811 return;
11812 }
11813 rc = bnxt_open(bp->dev);
11814 if (rc) {
11815 netdev_err(bp->dev, "bnxt_open_nic() failed\n");
11816 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11817 dev_close(bp->dev);
11818 }
11819
11820 bp->fw_reset_state = 0;
11821 /* Make sure fw_reset_state is 0 before clearing the flag */
11822 smp_mb__before_atomic();
11823 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11824 bnxt_ulp_start(bp, rc);
11825 if (!rc)
11826 bnxt_reenable_sriov(bp);
11827 bnxt_dl_health_recovery_done(bp);
11828 bnxt_dl_health_status_update(bp, true);
11829 rtnl_unlock();
11830 break;
11831 }
11832 return;
11833
11834 fw_reset_abort_status:
11835 if (bp->fw_health->status_reliable ||
11836 (bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) {
11837 u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG);
11838
11839 netdev_err(bp->dev, "fw_health_status 0x%x\n", sts);
11840 }
11841 fw_reset_abort:
11842 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
11843 if (bp->fw_reset_state != BNXT_FW_RESET_STATE_POLL_VF)
11844 bnxt_dl_health_status_update(bp, false);
11845 bp->fw_reset_state = 0;
11846 rtnl_lock();
11847 dev_close(bp->dev);
11848 rtnl_unlock();
11849 }
11850
11851 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
11852 {
11853 int rc;
11854 struct bnxt *bp = netdev_priv(dev);
11855
11856 SET_NETDEV_DEV(dev, &pdev->dev);
11857
11858 /* enable device (incl. PCI PM wakeup), and bus-mastering */
11859 rc = pci_enable_device(pdev);
11860 if (rc) {
11861 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
11862 goto init_err;
11863 }
11864
11865 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11866 dev_err(&pdev->dev,
11867 "Cannot find PCI device base address, aborting\n");
11868 rc = -ENODEV;
11869 goto init_err_disable;
11870 }
11871
11872 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11873 if (rc) {
11874 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
11875 goto init_err_disable;
11876 }
11877
11878 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
11879 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
11880 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
11881 rc = -EIO;
11882 goto init_err_release;
11883 }
11884
11885 pci_set_master(pdev);
11886
11887 bp->dev = dev;
11888 bp->pdev = pdev;
11889
11890 /* Doorbell BAR bp->bar1 is mapped after bnxt_fw_init_one_p2()
11891 * determines the BAR size.
11892 */
11893 bp->bar0 = pci_ioremap_bar(pdev, 0);
11894 if (!bp->bar0) {
11895 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
11896 rc = -ENOMEM;
11897 goto init_err_release;
11898 }
11899
11900 bp->bar2 = pci_ioremap_bar(pdev, 4);
11901 if (!bp->bar2) {
11902 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
11903 rc = -ENOMEM;
11904 goto init_err_release;
11905 }
11906
11907 pci_enable_pcie_error_reporting(pdev);
11908
11909 INIT_WORK(&bp->sp_task, bnxt_sp_task);
11910 INIT_DELAYED_WORK(&bp->fw_reset_task, bnxt_fw_reset_task);
11911
11912 spin_lock_init(&bp->ntp_fltr_lock);
11913 #if BITS_PER_LONG == 32
11914 spin_lock_init(&bp->db_lock);
11915 #endif
11916
11917 bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
11918 bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
11919
11920 bnxt_init_dflt_coal(bp);
11921
11922 timer_setup(&bp->timer, bnxt_timer, 0);
11923 bp->current_interval = BNXT_TIMER_INTERVAL;
11924
11925 bp->vxlan_fw_dst_port_id = INVALID_HW_RING_ID;
11926 bp->nge_fw_dst_port_id = INVALID_HW_RING_ID;
11927
11928 clear_bit(BNXT_STATE_OPEN, &bp->state);
11929 return 0;
11930
11931 init_err_release:
11932 bnxt_unmap_bars(bp, pdev);
11933 pci_release_regions(pdev);
11934
11935 init_err_disable:
11936 pci_disable_device(pdev);
11937
11938 init_err:
11939 return rc;
11940 }
11941
11942 /* rtnl_lock held */
11943 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
11944 {
11945 struct sockaddr *addr = p;
11946 struct bnxt *bp = netdev_priv(dev);
11947 int rc = 0;
11948
11949 if (!is_valid_ether_addr(addr->sa_data))
11950 return -EADDRNOTAVAIL;
11951
11952 if (ether_addr_equal(addr->sa_data, dev->dev_addr))
11953 return 0;
11954
11955 rc = bnxt_approve_mac(bp, addr->sa_data, true);
11956 if (rc)
11957 return rc;
11958
11959 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
11960 if (netif_running(dev)) {
11961 bnxt_close_nic(bp, false, false);
11962 rc = bnxt_open_nic(bp, false, false);
11963 }
11964
11965 return rc;
11966 }
11967
11968 /* rtnl_lock held */
11969 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
11970 {
11971 struct bnxt *bp = netdev_priv(dev);
11972
11973 if (netif_running(dev))
11974 bnxt_close_nic(bp, true, false);
11975
11976 dev->mtu = new_mtu;
11977 bnxt_set_ring_params(bp);
11978
11979 if (netif_running(dev))
11980 return bnxt_open_nic(bp, true, false);
11981
11982 return 0;
11983 }
11984
11985 int bnxt_setup_mq_tc(struct net_device *dev, u8 tc)
11986 {
11987 struct bnxt *bp = netdev_priv(dev);
11988 bool sh = false;
11989 int rc;
11990
11991 if (tc > bp->max_tc) {
11992 netdev_err(dev, "Too many traffic classes requested: %d. Max supported is %d.\n",
11993 tc, bp->max_tc);
11994 return -EINVAL;
11995 }
11996
11997 if (netdev_get_num_tc(dev) == tc)
11998 return 0;
11999
12000 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
12001 sh = true;
12002
12003 rc = bnxt_check_rings(bp, bp->tx_nr_rings_per_tc, bp->rx_nr_rings,
12004 sh, tc, bp->tx_nr_rings_xdp);
12005 if (rc)
12006 return rc;
12007
12008 /* Needs to close the device and do hw resource re-allocations */
12009 if (netif_running(bp->dev))
12010 bnxt_close_nic(bp, true, false);
12011
12012 if (tc) {
12013 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
12014 netdev_set_num_tc(dev, tc);
12015 } else {
12016 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12017 netdev_reset_tc(dev);
12018 }
12019 bp->tx_nr_rings += bp->tx_nr_rings_xdp;
12020 bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
12021 bp->tx_nr_rings + bp->rx_nr_rings;
12022
12023 if (netif_running(bp->dev))
12024 return bnxt_open_nic(bp, true, false);
12025
12026 return 0;
12027 }
12028
12029 static int bnxt_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
12030 void *cb_priv)
12031 {
12032 struct bnxt *bp = cb_priv;
12033
12034 if (!bnxt_tc_flower_enabled(bp) ||
12035 !tc_cls_can_offload_and_chain0(bp->dev, type_data))
12036 return -EOPNOTSUPP;
12037
12038 switch (type) {
12039 case TC_SETUP_CLSFLOWER:
12040 return bnxt_tc_setup_flower(bp, bp->pf.fw_fid, type_data);
12041 default:
12042 return -EOPNOTSUPP;
12043 }
12044 }
12045
12046 LIST_HEAD(bnxt_block_cb_list);
12047
12048 static int bnxt_setup_tc(struct net_device *dev, enum tc_setup_type type,
12049 void *type_data)
12050 {
12051 struct bnxt *bp = netdev_priv(dev);
12052
12053 switch (type) {
12054 case TC_SETUP_BLOCK:
12055 return flow_block_cb_setup_simple(type_data,
12056 &bnxt_block_cb_list,
12057 bnxt_setup_tc_block_cb,
12058 bp, bp, true);
12059 case TC_SETUP_QDISC_MQPRIO: {
12060 struct tc_mqprio_qopt *mqprio = type_data;
12061
12062 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
12063
12064 return bnxt_setup_mq_tc(dev, mqprio->num_tc);
12065 }
12066 default:
12067 return -EOPNOTSUPP;
12068 }
12069 }
12070
12071 #ifdef CONFIG_RFS_ACCEL
12072 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
12073 struct bnxt_ntuple_filter *f2)
12074 {
12075 struct flow_keys *keys1 = &f1->fkeys;
12076 struct flow_keys *keys2 = &f2->fkeys;
12077
12078 if (keys1->basic.n_proto != keys2->basic.n_proto ||
12079 keys1->basic.ip_proto != keys2->basic.ip_proto)
12080 return false;
12081
12082 if (keys1->basic.n_proto == htons(ETH_P_IP)) {
12083 if (keys1->addrs.v4addrs.src != keys2->addrs.v4addrs.src ||
12084 keys1->addrs.v4addrs.dst != keys2->addrs.v4addrs.dst)
12085 return false;
12086 } else {
12087 if (memcmp(&keys1->addrs.v6addrs.src, &keys2->addrs.v6addrs.src,
12088 sizeof(keys1->addrs.v6addrs.src)) ||
12089 memcmp(&keys1->addrs.v6addrs.dst, &keys2->addrs.v6addrs.dst,
12090 sizeof(keys1->addrs.v6addrs.dst)))
12091 return false;
12092 }
12093
12094 if (keys1->ports.ports == keys2->ports.ports &&
12095 keys1->control.flags == keys2->control.flags &&
12096 ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr) &&
12097 ether_addr_equal(f1->dst_mac_addr, f2->dst_mac_addr))
12098 return true;
12099
12100 return false;
12101 }
12102
12103 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
12104 u16 rxq_index, u32 flow_id)
12105 {
12106 struct bnxt *bp = netdev_priv(dev);
12107 struct bnxt_ntuple_filter *fltr, *new_fltr;
12108 struct flow_keys *fkeys;
12109 struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
12110 int rc = 0, idx, bit_id, l2_idx = 0;
12111 struct hlist_head *head;
12112 u32 flags;
12113
12114 if (!ether_addr_equal(dev->dev_addr, eth->h_dest)) {
12115 struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
12116 int off = 0, j;
12117
12118 netif_addr_lock_bh(dev);
12119 for (j = 0; j < vnic->uc_filter_count; j++, off += ETH_ALEN) {
12120 if (ether_addr_equal(eth->h_dest,
12121 vnic->uc_list + off)) {
12122 l2_idx = j + 1;
12123 break;
12124 }
12125 }
12126 netif_addr_unlock_bh(dev);
12127 if (!l2_idx)
12128 return -EINVAL;
12129 }
12130 new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
12131 if (!new_fltr)
12132 return -ENOMEM;
12133
12134 fkeys = &new_fltr->fkeys;
12135 if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
12136 rc = -EPROTONOSUPPORT;
12137 goto err_free;
12138 }
12139
12140 if ((fkeys->basic.n_proto != htons(ETH_P_IP) &&
12141 fkeys->basic.n_proto != htons(ETH_P_IPV6)) ||
12142 ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
12143 (fkeys->basic.ip_proto != IPPROTO_UDP))) {
12144 rc = -EPROTONOSUPPORT;
12145 goto err_free;
12146 }
12147 if (fkeys->basic.n_proto == htons(ETH_P_IPV6) &&
12148 bp->hwrm_spec_code < 0x10601) {
12149 rc = -EPROTONOSUPPORT;
12150 goto err_free;
12151 }
12152 flags = fkeys->control.flags;
12153 if (((flags & FLOW_DIS_ENCAPSULATION) &&
12154 bp->hwrm_spec_code < 0x10601) || (flags & FLOW_DIS_IS_FRAGMENT)) {
12155 rc = -EPROTONOSUPPORT;
12156 goto err_free;
12157 }
12158
12159 memcpy(new_fltr->dst_mac_addr, eth->h_dest, ETH_ALEN);
12160 memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
12161
12162 idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
12163 head = &bp->ntp_fltr_hash_tbl[idx];
12164 rcu_read_lock();
12165 hlist_for_each_entry_rcu(fltr, head, hash) {
12166 if (bnxt_fltr_match(fltr, new_fltr)) {
12167 rcu_read_unlock();
12168 rc = 0;
12169 goto err_free;
12170 }
12171 }
12172 rcu_read_unlock();
12173
12174 spin_lock_bh(&bp->ntp_fltr_lock);
12175 bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
12176 BNXT_NTP_FLTR_MAX_FLTR, 0);
12177 if (bit_id < 0) {
12178 spin_unlock_bh(&bp->ntp_fltr_lock);
12179 rc = -ENOMEM;
12180 goto err_free;
12181 }
12182
12183 new_fltr->sw_id = (u16)bit_id;
12184 new_fltr->flow_id = flow_id;
12185 new_fltr->l2_fltr_idx = l2_idx;
12186 new_fltr->rxq = rxq_index;
12187 hlist_add_head_rcu(&new_fltr->hash, head);
12188 bp->ntp_fltr_count++;
12189 spin_unlock_bh(&bp->ntp_fltr_lock);
12190
12191 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
12192 bnxt_queue_sp_work(bp);
12193
12194 return new_fltr->sw_id;
12195
12196 err_free:
12197 kfree(new_fltr);
12198 return rc;
12199 }
12200
12201 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
12202 {
12203 int i;
12204
12205 for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
12206 struct hlist_head *head;
12207 struct hlist_node *tmp;
12208 struct bnxt_ntuple_filter *fltr;
12209 int rc;
12210
12211 head = &bp->ntp_fltr_hash_tbl[i];
12212 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
12213 bool del = false;
12214
12215 if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
12216 if (rps_may_expire_flow(bp->dev, fltr->rxq,
12217 fltr->flow_id,
12218 fltr->sw_id)) {
12219 bnxt_hwrm_cfa_ntuple_filter_free(bp,
12220 fltr);
12221 del = true;
12222 }
12223 } else {
12224 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
12225 fltr);
12226 if (rc)
12227 del = true;
12228 else
12229 set_bit(BNXT_FLTR_VALID, &fltr->state);
12230 }
12231
12232 if (del) {
12233 spin_lock_bh(&bp->ntp_fltr_lock);
12234 hlist_del_rcu(&fltr->hash);
12235 bp->ntp_fltr_count--;
12236 spin_unlock_bh(&bp->ntp_fltr_lock);
12237 synchronize_rcu();
12238 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
12239 kfree(fltr);
12240 }
12241 }
12242 }
12243 if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
12244 netdev_info(bp->dev, "Receive PF driver unload event!\n");
12245 }
12246
12247 #else
12248
12249 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
12250 {
12251 }
12252
12253 #endif /* CONFIG_RFS_ACCEL */
12254
12255 static int bnxt_udp_tunnel_sync(struct net_device *netdev, unsigned int table)
12256 {
12257 struct bnxt *bp = netdev_priv(netdev);
12258 struct udp_tunnel_info ti;
12259 unsigned int cmd;
12260
12261 udp_tunnel_nic_get_port(netdev, table, 0, &ti);
12262 if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
12263 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN;
12264 else
12265 cmd = TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE;
12266
12267 if (ti.port)
12268 return bnxt_hwrm_tunnel_dst_port_alloc(bp, ti.port, cmd);
12269
12270 return bnxt_hwrm_tunnel_dst_port_free(bp, cmd);
12271 }
12272
12273 static const struct udp_tunnel_nic_info bnxt_udp_tunnels = {
12274 .sync_table = bnxt_udp_tunnel_sync,
12275 .flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP |
12276 UDP_TUNNEL_NIC_INFO_OPEN_ONLY,
12277 .tables = {
12278 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
12279 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
12280 },
12281 };
12282
12283 static int bnxt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
12284 struct net_device *dev, u32 filter_mask,
12285 int nlflags)
12286 {
12287 struct bnxt *bp = netdev_priv(dev);
12288
12289 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, bp->br_mode, 0, 0,
12290 nlflags, filter_mask, NULL);
12291 }
12292
12293 static int bnxt_bridge_setlink(struct net_device *dev, struct nlmsghdr *nlh,
12294 u16 flags, struct netlink_ext_ack *extack)
12295 {
12296 struct bnxt *bp = netdev_priv(dev);
12297 struct nlattr *attr, *br_spec;
12298 int rem, rc = 0;
12299
12300 if (bp->hwrm_spec_code < 0x10708 || !BNXT_SINGLE_PF(bp))
12301 return -EOPNOTSUPP;
12302
12303 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
12304 if (!br_spec)
12305 return -EINVAL;
12306
12307 nla_for_each_nested(attr, br_spec, rem) {
12308 u16 mode;
12309
12310 if (nla_type(attr) != IFLA_BRIDGE_MODE)
12311 continue;
12312
12313 if (nla_len(attr) < sizeof(mode))
12314 return -EINVAL;
12315
12316 mode = nla_get_u16(attr);
12317 if (mode == bp->br_mode)
12318 break;
12319
12320 rc = bnxt_hwrm_set_br_mode(bp, mode);
12321 if (!rc)
12322 bp->br_mode = mode;
12323 break;
12324 }
12325 return rc;
12326 }
12327
12328 int bnxt_get_port_parent_id(struct net_device *dev,
12329 struct netdev_phys_item_id *ppid)
12330 {
12331 struct bnxt *bp = netdev_priv(dev);
12332
12333 if (bp->eswitch_mode != DEVLINK_ESWITCH_MODE_SWITCHDEV)
12334 return -EOPNOTSUPP;
12335
12336 /* The PF and it's VF-reps only support the switchdev framework */
12337 if (!BNXT_PF(bp) || !(bp->flags & BNXT_FLAG_DSN_VALID))
12338 return -EOPNOTSUPP;
12339
12340 ppid->id_len = sizeof(bp->dsn);
12341 memcpy(ppid->id, bp->dsn, ppid->id_len);
12342
12343 return 0;
12344 }
12345
12346 static struct devlink_port *bnxt_get_devlink_port(struct net_device *dev)
12347 {
12348 struct bnxt *bp = netdev_priv(dev);
12349
12350 return &bp->dl_port;
12351 }
12352
12353 static const struct net_device_ops bnxt_netdev_ops = {
12354 .ndo_open = bnxt_open,
12355 .ndo_start_xmit = bnxt_start_xmit,
12356 .ndo_stop = bnxt_close,
12357 .ndo_get_stats64 = bnxt_get_stats64,
12358 .ndo_set_rx_mode = bnxt_set_rx_mode,
12359 .ndo_do_ioctl = bnxt_ioctl,
12360 .ndo_validate_addr = eth_validate_addr,
12361 .ndo_set_mac_address = bnxt_change_mac_addr,
12362 .ndo_change_mtu = bnxt_change_mtu,
12363 .ndo_fix_features = bnxt_fix_features,
12364 .ndo_set_features = bnxt_set_features,
12365 .ndo_tx_timeout = bnxt_tx_timeout,
12366 #ifdef CONFIG_BNXT_SRIOV
12367 .ndo_get_vf_config = bnxt_get_vf_config,
12368 .ndo_set_vf_mac = bnxt_set_vf_mac,
12369 .ndo_set_vf_vlan = bnxt_set_vf_vlan,
12370 .ndo_set_vf_rate = bnxt_set_vf_bw,
12371 .ndo_set_vf_link_state = bnxt_set_vf_link_state,
12372 .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk,
12373 .ndo_set_vf_trust = bnxt_set_vf_trust,
12374 #endif
12375 .ndo_setup_tc = bnxt_setup_tc,
12376 #ifdef CONFIG_RFS_ACCEL
12377 .ndo_rx_flow_steer = bnxt_rx_flow_steer,
12378 #endif
12379 .ndo_bpf = bnxt_xdp,
12380 .ndo_xdp_xmit = bnxt_xdp_xmit,
12381 .ndo_bridge_getlink = bnxt_bridge_getlink,
12382 .ndo_bridge_setlink = bnxt_bridge_setlink,
12383 .ndo_get_devlink_port = bnxt_get_devlink_port,
12384 };
12385
12386 static void bnxt_remove_one(struct pci_dev *pdev)
12387 {
12388 struct net_device *dev = pci_get_drvdata(pdev);
12389 struct bnxt *bp = netdev_priv(dev);
12390
12391 if (BNXT_PF(bp))
12392 bnxt_sriov_disable(bp);
12393
12394 if (BNXT_PF(bp))
12395 devlink_port_type_clear(&bp->dl_port);
12396 pci_disable_pcie_error_reporting(pdev);
12397 unregister_netdev(dev);
12398 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state);
12399 /* Flush any pending tasks */
12400 cancel_work_sync(&bp->sp_task);
12401 cancel_delayed_work_sync(&bp->fw_reset_task);
12402 bp->sp_event = 0;
12403
12404 bnxt_dl_fw_reporters_destroy(bp, true);
12405 bnxt_dl_unregister(bp);
12406 bnxt_shutdown_tc(bp);
12407
12408 bnxt_clear_int_mode(bp);
12409 bnxt_hwrm_func_drv_unrgtr(bp);
12410 bnxt_free_hwrm_resources(bp);
12411 bnxt_free_hwrm_short_cmd_req(bp);
12412 bnxt_ethtool_free(bp);
12413 bnxt_dcb_free(bp);
12414 kfree(bp->edev);
12415 bp->edev = NULL;
12416 kfree(bp->fw_health);
12417 bp->fw_health = NULL;
12418 bnxt_cleanup_pci(bp);
12419 bnxt_free_ctx_mem(bp);
12420 kfree(bp->ctx);
12421 bp->ctx = NULL;
12422 kfree(bp->rss_indir_tbl);
12423 bp->rss_indir_tbl = NULL;
12424 bnxt_free_port_stats(bp);
12425 free_netdev(dev);
12426 }
12427
12428 static int bnxt_probe_phy(struct bnxt *bp, bool fw_dflt)
12429 {
12430 int rc = 0;
12431 struct bnxt_link_info *link_info = &bp->link_info;
12432
12433 rc = bnxt_hwrm_phy_qcaps(bp);
12434 if (rc) {
12435 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
12436 rc);
12437 return rc;
12438 }
12439 if (!fw_dflt)
12440 return 0;
12441
12442 rc = bnxt_update_link(bp, false);
12443 if (rc) {
12444 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
12445 rc);
12446 return rc;
12447 }
12448
12449 /* Older firmware does not have supported_auto_speeds, so assume
12450 * that all supported speeds can be autonegotiated.
12451 */
12452 if (link_info->auto_link_speeds && !link_info->support_auto_speeds)
12453 link_info->support_auto_speeds = link_info->support_speeds;
12454
12455 bnxt_init_ethtool_link_settings(bp);
12456 return 0;
12457 }
12458
12459 static int bnxt_get_max_irq(struct pci_dev *pdev)
12460 {
12461 u16 ctrl;
12462
12463 if (!pdev->msix_cap)
12464 return 1;
12465
12466 pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
12467 return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
12468 }
12469
12470 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
12471 int *max_cp)
12472 {
12473 struct bnxt_hw_resc *hw_resc = &bp->hw_resc;
12474 int max_ring_grps = 0, max_irq;
12475
12476 *max_tx = hw_resc->max_tx_rings;
12477 *max_rx = hw_resc->max_rx_rings;
12478 *max_cp = bnxt_get_max_func_cp_rings_for_en(bp);
12479 max_irq = min_t(int, bnxt_get_max_func_irqs(bp) -
12480 bnxt_get_ulp_msix_num(bp),
12481 hw_resc->max_stat_ctxs - bnxt_get_ulp_stat_ctxs(bp));
12482 if (!(bp->flags & BNXT_FLAG_CHIP_P5))
12483 *max_cp = min_t(int, *max_cp, max_irq);
12484 max_ring_grps = hw_resc->max_hw_ring_grps;
12485 if (BNXT_CHIP_TYPE_NITRO_A0(bp) && BNXT_PF(bp)) {
12486 *max_cp -= 1;
12487 *max_rx -= 2;
12488 }
12489 if (bp->flags & BNXT_FLAG_AGG_RINGS)
12490 *max_rx >>= 1;
12491 if (bp->flags & BNXT_FLAG_CHIP_P5) {
12492 bnxt_trim_rings(bp, max_rx, max_tx, *max_cp, false);
12493 /* On P5 chips, max_cp output param should be available NQs */
12494 *max_cp = max_irq;
12495 }
12496 *max_rx = min_t(int, *max_rx, max_ring_grps);
12497 }
12498
12499 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
12500 {
12501 int rx, tx, cp;
12502
12503 _bnxt_get_max_rings(bp, &rx, &tx, &cp);
12504 *max_rx = rx;
12505 *max_tx = tx;
12506 if (!rx || !tx || !cp)
12507 return -ENOMEM;
12508
12509 return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
12510 }
12511
12512 static int bnxt_get_dflt_rings(struct bnxt *bp, int *max_rx, int *max_tx,
12513 bool shared)
12514 {
12515 int rc;
12516
12517 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
12518 if (rc && (bp->flags & BNXT_FLAG_AGG_RINGS)) {
12519 /* Not enough rings, try disabling agg rings. */
12520 bp->flags &= ~BNXT_FLAG_AGG_RINGS;
12521 rc = bnxt_get_max_rings(bp, max_rx, max_tx, shared);
12522 if (rc) {
12523 /* set BNXT_FLAG_AGG_RINGS back for consistency */
12524 bp->flags |= BNXT_FLAG_AGG_RINGS;
12525 return rc;
12526 }
12527 bp->flags |= BNXT_FLAG_NO_AGG_RINGS;
12528 bp->dev->hw_features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12529 bp->dev->features &= ~(NETIF_F_LRO | NETIF_F_GRO_HW);
12530 bnxt_set_ring_params(bp);
12531 }
12532
12533 if (bp->flags & BNXT_FLAG_ROCE_CAP) {
12534 int max_cp, max_stat, max_irq;
12535
12536 /* Reserve minimum resources for RoCE */
12537 max_cp = bnxt_get_max_func_cp_rings(bp);
12538 max_stat = bnxt_get_max_func_stat_ctxs(bp);
12539 max_irq = bnxt_get_max_func_irqs(bp);
12540 if (max_cp <= BNXT_MIN_ROCE_CP_RINGS ||
12541 max_irq <= BNXT_MIN_ROCE_CP_RINGS ||
12542 max_stat <= BNXT_MIN_ROCE_STAT_CTXS)
12543 return 0;
12544
12545 max_cp -= BNXT_MIN_ROCE_CP_RINGS;
12546 max_irq -= BNXT_MIN_ROCE_CP_RINGS;
12547 max_stat -= BNXT_MIN_ROCE_STAT_CTXS;
12548 max_cp = min_t(int, max_cp, max_irq);
12549 max_cp = min_t(int, max_cp, max_stat);
12550 rc = bnxt_trim_rings(bp, max_rx, max_tx, max_cp, shared);
12551 if (rc)
12552 rc = 0;
12553 }
12554 return rc;
12555 }
12556
12557 /* In initial default shared ring setting, each shared ring must have a
12558 * RX/TX ring pair.
12559 */
12560 static void bnxt_trim_dflt_sh_rings(struct bnxt *bp)
12561 {
12562 bp->cp_nr_rings = min_t(int, bp->tx_nr_rings_per_tc, bp->rx_nr_rings);
12563 bp->rx_nr_rings = bp->cp_nr_rings;
12564 bp->tx_nr_rings_per_tc = bp->cp_nr_rings;
12565 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12566 }
12567
12568 static int bnxt_set_dflt_rings(struct bnxt *bp, bool sh)
12569 {
12570 int dflt_rings, max_rx_rings, max_tx_rings, rc;
12571
12572 if (!bnxt_can_reserve_rings(bp))
12573 return 0;
12574
12575 if (sh)
12576 bp->flags |= BNXT_FLAG_SHARED_RINGS;
12577 dflt_rings = is_kdump_kernel() ? 1 : netif_get_num_default_rss_queues();
12578 /* Reduce default rings on multi-port cards so that total default
12579 * rings do not exceed CPU count.
12580 */
12581 if (bp->port_count > 1) {
12582 int max_rings =
12583 max_t(int, num_online_cpus() / bp->port_count, 1);
12584
12585 dflt_rings = min_t(int, dflt_rings, max_rings);
12586 }
12587 rc = bnxt_get_dflt_rings(bp, &max_rx_rings, &max_tx_rings, sh);
12588 if (rc)
12589 return rc;
12590 bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
12591 bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
12592 if (sh)
12593 bnxt_trim_dflt_sh_rings(bp);
12594 else
12595 bp->cp_nr_rings = bp->tx_nr_rings_per_tc + bp->rx_nr_rings;
12596 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
12597
12598 rc = __bnxt_reserve_rings(bp);
12599 if (rc)
12600 netdev_warn(bp->dev, "Unable to reserve tx rings\n");
12601 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12602 if (sh)
12603 bnxt_trim_dflt_sh_rings(bp);
12604
12605 /* Rings may have been trimmed, re-reserve the trimmed rings. */
12606 if (bnxt_need_reserve_rings(bp)) {
12607 rc = __bnxt_reserve_rings(bp);
12608 if (rc)
12609 netdev_warn(bp->dev, "2nd rings reservation failed.\n");
12610 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12611 }
12612 if (BNXT_CHIP_TYPE_NITRO_A0(bp)) {
12613 bp->rx_nr_rings++;
12614 bp->cp_nr_rings++;
12615 }
12616 if (rc) {
12617 bp->tx_nr_rings = 0;
12618 bp->rx_nr_rings = 0;
12619 }
12620 return rc;
12621 }
12622
12623 static int bnxt_init_dflt_ring_mode(struct bnxt *bp)
12624 {
12625 int rc;
12626
12627 if (bp->tx_nr_rings)
12628 return 0;
12629
12630 bnxt_ulp_irq_stop(bp);
12631 bnxt_clear_int_mode(bp);
12632 rc = bnxt_set_dflt_rings(bp, true);
12633 if (rc) {
12634 netdev_err(bp->dev, "Not enough rings available.\n");
12635 goto init_dflt_ring_err;
12636 }
12637 rc = bnxt_init_int_mode(bp);
12638 if (rc)
12639 goto init_dflt_ring_err;
12640
12641 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12642 if (bnxt_rfs_supported(bp) && bnxt_rfs_capable(bp)) {
12643 bp->flags |= BNXT_FLAG_RFS;
12644 bp->dev->features |= NETIF_F_NTUPLE;
12645 }
12646 init_dflt_ring_err:
12647 bnxt_ulp_irq_restart(bp, rc);
12648 return rc;
12649 }
12650
12651 int bnxt_restore_pf_fw_resources(struct bnxt *bp)
12652 {
12653 int rc;
12654
12655 ASSERT_RTNL();
12656 bnxt_hwrm_func_qcaps(bp);
12657
12658 if (netif_running(bp->dev))
12659 __bnxt_close_nic(bp, true, false);
12660
12661 bnxt_ulp_irq_stop(bp);
12662 bnxt_clear_int_mode(bp);
12663 rc = bnxt_init_int_mode(bp);
12664 bnxt_ulp_irq_restart(bp, rc);
12665
12666 if (netif_running(bp->dev)) {
12667 if (rc)
12668 dev_close(bp->dev);
12669 else
12670 rc = bnxt_open_nic(bp, true, false);
12671 }
12672
12673 return rc;
12674 }
12675
12676 static int bnxt_init_mac_addr(struct bnxt *bp)
12677 {
12678 int rc = 0;
12679
12680 if (BNXT_PF(bp)) {
12681 memcpy(bp->dev->dev_addr, bp->pf.mac_addr, ETH_ALEN);
12682 } else {
12683 #ifdef CONFIG_BNXT_SRIOV
12684 struct bnxt_vf_info *vf = &bp->vf;
12685 bool strict_approval = true;
12686
12687 if (is_valid_ether_addr(vf->mac_addr)) {
12688 /* overwrite netdev dev_addr with admin VF MAC */
12689 memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
12690 /* Older PF driver or firmware may not approve this
12691 * correctly.
12692 */
12693 strict_approval = false;
12694 } else {
12695 eth_hw_addr_random(bp->dev);
12696 }
12697 rc = bnxt_approve_mac(bp, bp->dev->dev_addr, strict_approval);
12698 #endif
12699 }
12700 return rc;
12701 }
12702
12703 #define BNXT_VPD_LEN 512
12704 static void bnxt_vpd_read_info(struct bnxt *bp)
12705 {
12706 struct pci_dev *pdev = bp->pdev;
12707 int i, len, pos, ro_size, size;
12708 ssize_t vpd_size;
12709 u8 *vpd_data;
12710
12711 vpd_data = kmalloc(BNXT_VPD_LEN, GFP_KERNEL);
12712 if (!vpd_data)
12713 return;
12714
12715 vpd_size = pci_read_vpd(pdev, 0, BNXT_VPD_LEN, vpd_data);
12716 if (vpd_size <= 0) {
12717 netdev_err(bp->dev, "Unable to read VPD\n");
12718 goto exit;
12719 }
12720
12721 i = pci_vpd_find_tag(vpd_data, 0, vpd_size, PCI_VPD_LRDT_RO_DATA);
12722 if (i < 0) {
12723 netdev_err(bp->dev, "VPD READ-Only not found\n");
12724 goto exit;
12725 }
12726
12727 ro_size = pci_vpd_lrdt_size(&vpd_data[i]);
12728 i += PCI_VPD_LRDT_TAG_SIZE;
12729 if (i + ro_size > vpd_size)
12730 goto exit;
12731
12732 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
12733 PCI_VPD_RO_KEYWORD_PARTNO);
12734 if (pos < 0)
12735 goto read_sn;
12736
12737 len = pci_vpd_info_field_size(&vpd_data[pos]);
12738 pos += PCI_VPD_INFO_FLD_HDR_SIZE;
12739 if (len + pos > vpd_size)
12740 goto read_sn;
12741
12742 size = min(len, BNXT_VPD_FLD_LEN - 1);
12743 memcpy(bp->board_partno, &vpd_data[pos], size);
12744
12745 read_sn:
12746 pos = pci_vpd_find_info_keyword(vpd_data, i, ro_size,
12747 PCI_VPD_RO_KEYWORD_SERIALNO);
12748 if (pos < 0)
12749 goto exit;
12750
12751 len = pci_vpd_info_field_size(&vpd_data[pos]);
12752 pos += PCI_VPD_INFO_FLD_HDR_SIZE;
12753 if (len + pos > vpd_size)
12754 goto exit;
12755
12756 size = min(len, BNXT_VPD_FLD_LEN - 1);
12757 memcpy(bp->board_serialno, &vpd_data[pos], size);
12758 exit:
12759 kfree(vpd_data);
12760 }
12761
12762 static int bnxt_pcie_dsn_get(struct bnxt *bp, u8 dsn[])
12763 {
12764 struct pci_dev *pdev = bp->pdev;
12765 u64 qword;
12766
12767 qword = pci_get_dsn(pdev);
12768 if (!qword) {
12769 netdev_info(bp->dev, "Unable to read adapter's DSN\n");
12770 return -EOPNOTSUPP;
12771 }
12772
12773 put_unaligned_le64(qword, dsn);
12774
12775 bp->flags |= BNXT_FLAG_DSN_VALID;
12776 return 0;
12777 }
12778
12779 static int bnxt_map_db_bar(struct bnxt *bp)
12780 {
12781 if (!bp->db_size)
12782 return -ENODEV;
12783 bp->bar1 = pci_iomap(bp->pdev, 2, bp->db_size);
12784 if (!bp->bar1)
12785 return -ENOMEM;
12786 return 0;
12787 }
12788
12789 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
12790 {
12791 struct net_device *dev;
12792 struct bnxt *bp;
12793 int rc, max_irqs;
12794
12795 if (pci_is_bridge(pdev))
12796 return -ENODEV;
12797
12798 /* Clear any pending DMA transactions from crash kernel
12799 * while loading driver in capture kernel.
12800 */
12801 if (is_kdump_kernel()) {
12802 pci_clear_master(pdev);
12803 pcie_flr(pdev);
12804 }
12805
12806 max_irqs = bnxt_get_max_irq(pdev);
12807 dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
12808 if (!dev)
12809 return -ENOMEM;
12810
12811 bp = netdev_priv(dev);
12812 bp->msg_enable = BNXT_DEF_MSG_ENABLE;
12813 bnxt_set_max_func_irqs(bp, max_irqs);
12814
12815 if (bnxt_vf_pciid(ent->driver_data))
12816 bp->flags |= BNXT_FLAG_VF;
12817
12818 if (pdev->msix_cap)
12819 bp->flags |= BNXT_FLAG_MSIX_CAP;
12820
12821 rc = bnxt_init_board(pdev, dev);
12822 if (rc < 0)
12823 goto init_err_free;
12824
12825 dev->netdev_ops = &bnxt_netdev_ops;
12826 dev->watchdog_timeo = BNXT_TX_TIMEOUT;
12827 dev->ethtool_ops = &bnxt_ethtool_ops;
12828 pci_set_drvdata(pdev, dev);
12829
12830 rc = bnxt_alloc_hwrm_resources(bp);
12831 if (rc)
12832 goto init_err_pci_clean;
12833
12834 mutex_init(&bp->hwrm_cmd_lock);
12835 mutex_init(&bp->link_lock);
12836
12837 rc = bnxt_fw_init_one_p1(bp);
12838 if (rc)
12839 goto init_err_pci_clean;
12840
12841 if (BNXT_PF(bp))
12842 bnxt_vpd_read_info(bp);
12843
12844 if (BNXT_CHIP_P5(bp)) {
12845 bp->flags |= BNXT_FLAG_CHIP_P5;
12846 if (BNXT_CHIP_SR2(bp))
12847 bp->flags |= BNXT_FLAG_CHIP_SR2;
12848 }
12849
12850 rc = bnxt_alloc_rss_indir_tbl(bp);
12851 if (rc)
12852 goto init_err_pci_clean;
12853
12854 rc = bnxt_fw_init_one_p2(bp);
12855 if (rc)
12856 goto init_err_pci_clean;
12857
12858 rc = bnxt_map_db_bar(bp);
12859 if (rc) {
12860 dev_err(&pdev->dev, "Cannot map doorbell BAR rc = %d, aborting\n",
12861 rc);
12862 goto init_err_pci_clean;
12863 }
12864
12865 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12866 NETIF_F_TSO | NETIF_F_TSO6 |
12867 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
12868 NETIF_F_GSO_IPXIP4 |
12869 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
12870 NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
12871 NETIF_F_RXCSUM | NETIF_F_GRO;
12872
12873 if (BNXT_SUPPORTS_TPA(bp))
12874 dev->hw_features |= NETIF_F_LRO;
12875
12876 dev->hw_enc_features =
12877 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12878 NETIF_F_TSO | NETIF_F_TSO6 |
12879 NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
12880 NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
12881 NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
12882 dev->udp_tunnel_nic_info = &bnxt_udp_tunnels;
12883
12884 dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
12885 NETIF_F_GSO_GRE_CSUM;
12886 dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
12887 if (bp->fw_cap & BNXT_FW_CAP_VLAN_RX_STRIP)
12888 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_RX;
12889 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT)
12890 dev->hw_features |= BNXT_HW_FEATURE_VLAN_ALL_TX;
12891 if (BNXT_SUPPORTS_TPA(bp))
12892 dev->hw_features |= NETIF_F_GRO_HW;
12893 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
12894 if (dev->features & NETIF_F_GRO_HW)
12895 dev->features &= ~NETIF_F_LRO;
12896 dev->priv_flags |= IFF_UNICAST_FLT;
12897
12898 #ifdef CONFIG_BNXT_SRIOV
12899 init_waitqueue_head(&bp->sriov_cfg_wait);
12900 mutex_init(&bp->sriov_lock);
12901 #endif
12902 if (BNXT_SUPPORTS_TPA(bp)) {
12903 bp->gro_func = bnxt_gro_func_5730x;
12904 if (BNXT_CHIP_P4(bp))
12905 bp->gro_func = bnxt_gro_func_5731x;
12906 else if (BNXT_CHIP_P5(bp))
12907 bp->gro_func = bnxt_gro_func_5750x;
12908 }
12909 if (!BNXT_CHIP_P4_PLUS(bp))
12910 bp->flags |= BNXT_FLAG_DOUBLE_DB;
12911
12912 bp->ulp_probe = bnxt_ulp_probe;
12913
12914 rc = bnxt_init_mac_addr(bp);
12915 if (rc) {
12916 dev_err(&pdev->dev, "Unable to initialize mac address.\n");
12917 rc = -EADDRNOTAVAIL;
12918 goto init_err_pci_clean;
12919 }
12920
12921 if (BNXT_PF(bp)) {
12922 /* Read the adapter's DSN to use as the eswitch switch_id */
12923 rc = bnxt_pcie_dsn_get(bp, bp->dsn);
12924 }
12925
12926 /* MTU range: 60 - FW defined max */
12927 dev->min_mtu = ETH_ZLEN;
12928 dev->max_mtu = bp->max_mtu;
12929
12930 rc = bnxt_probe_phy(bp, true);
12931 if (rc)
12932 goto init_err_pci_clean;
12933
12934 bnxt_set_rx_skb_mode(bp, false);
12935 bnxt_set_tpa_flags(bp);
12936 bnxt_set_ring_params(bp);
12937 rc = bnxt_set_dflt_rings(bp, true);
12938 if (rc) {
12939 netdev_err(bp->dev, "Not enough rings available.\n");
12940 rc = -ENOMEM;
12941 goto init_err_pci_clean;
12942 }
12943
12944 bnxt_fw_init_one_p3(bp);
12945
12946 if (dev->hw_features & BNXT_HW_FEATURE_VLAN_ALL_RX)
12947 bp->flags |= BNXT_FLAG_STRIP_VLAN;
12948
12949 rc = bnxt_init_int_mode(bp);
12950 if (rc)
12951 goto init_err_pci_clean;
12952
12953 /* No TC has been set yet and rings may have been trimmed due to
12954 * limited MSIX, so we re-initialize the TX rings per TC.
12955 */
12956 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
12957
12958 if (BNXT_PF(bp)) {
12959 if (!bnxt_pf_wq) {
12960 bnxt_pf_wq =
12961 create_singlethread_workqueue("bnxt_pf_wq");
12962 if (!bnxt_pf_wq) {
12963 dev_err(&pdev->dev, "Unable to create workqueue.\n");
12964 rc = -ENOMEM;
12965 goto init_err_pci_clean;
12966 }
12967 }
12968 rc = bnxt_init_tc(bp);
12969 if (rc)
12970 netdev_err(dev, "Failed to initialize TC flower offload, err = %d.\n",
12971 rc);
12972 }
12973
12974 bnxt_dl_register(bp);
12975
12976 rc = register_netdev(dev);
12977 if (rc)
12978 goto init_err_cleanup;
12979
12980 if (BNXT_PF(bp))
12981 devlink_port_type_eth_set(&bp->dl_port, bp->dev);
12982 bnxt_dl_fw_reporters_create(bp);
12983
12984 netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
12985 board_info[ent->driver_data].name,
12986 (long)pci_resource_start(pdev, 0), dev->dev_addr);
12987 pcie_print_link_status(pdev);
12988
12989 pci_save_state(pdev);
12990 return 0;
12991
12992 init_err_cleanup:
12993 bnxt_dl_unregister(bp);
12994 bnxt_shutdown_tc(bp);
12995 bnxt_clear_int_mode(bp);
12996
12997 init_err_pci_clean:
12998 bnxt_hwrm_func_drv_unrgtr(bp);
12999 bnxt_free_hwrm_short_cmd_req(bp);
13000 bnxt_free_hwrm_resources(bp);
13001 kfree(bp->fw_health);
13002 bp->fw_health = NULL;
13003 bnxt_cleanup_pci(bp);
13004 bnxt_free_ctx_mem(bp);
13005 kfree(bp->ctx);
13006 bp->ctx = NULL;
13007 kfree(bp->rss_indir_tbl);
13008 bp->rss_indir_tbl = NULL;
13009
13010 init_err_free:
13011 free_netdev(dev);
13012 return rc;
13013 }
13014
13015 static void bnxt_shutdown(struct pci_dev *pdev)
13016 {
13017 struct net_device *dev = pci_get_drvdata(pdev);
13018 struct bnxt *bp;
13019
13020 if (!dev)
13021 return;
13022
13023 rtnl_lock();
13024 bp = netdev_priv(dev);
13025 if (!bp)
13026 goto shutdown_exit;
13027
13028 if (netif_running(dev))
13029 dev_close(dev);
13030
13031 bnxt_ulp_shutdown(bp);
13032 bnxt_clear_int_mode(bp);
13033 pci_disable_device(pdev);
13034
13035 if (system_state == SYSTEM_POWER_OFF) {
13036 pci_wake_from_d3(pdev, bp->wol);
13037 pci_set_power_state(pdev, PCI_D3hot);
13038 }
13039
13040 shutdown_exit:
13041 rtnl_unlock();
13042 }
13043
13044 #ifdef CONFIG_PM_SLEEP
13045 static int bnxt_suspend(struct device *device)
13046 {
13047 struct net_device *dev = dev_get_drvdata(device);
13048 struct bnxt *bp = netdev_priv(dev);
13049 int rc = 0;
13050
13051 rtnl_lock();
13052 bnxt_ulp_stop(bp);
13053 if (netif_running(dev)) {
13054 netif_device_detach(dev);
13055 rc = bnxt_close(dev);
13056 }
13057 bnxt_hwrm_func_drv_unrgtr(bp);
13058 pci_disable_device(bp->pdev);
13059 bnxt_free_ctx_mem(bp);
13060 kfree(bp->ctx);
13061 bp->ctx = NULL;
13062 rtnl_unlock();
13063 return rc;
13064 }
13065
13066 static int bnxt_resume(struct device *device)
13067 {
13068 struct net_device *dev = dev_get_drvdata(device);
13069 struct bnxt *bp = netdev_priv(dev);
13070 int rc = 0;
13071
13072 rtnl_lock();
13073 rc = pci_enable_device(bp->pdev);
13074 if (rc) {
13075 netdev_err(dev, "Cannot re-enable PCI device during resume, err = %d\n",
13076 rc);
13077 goto resume_exit;
13078 }
13079 pci_set_master(bp->pdev);
13080 if (bnxt_hwrm_ver_get(bp)) {
13081 rc = -ENODEV;
13082 goto resume_exit;
13083 }
13084 rc = bnxt_hwrm_func_reset(bp);
13085 if (rc) {
13086 rc = -EBUSY;
13087 goto resume_exit;
13088 }
13089
13090 rc = bnxt_hwrm_func_qcaps(bp);
13091 if (rc)
13092 goto resume_exit;
13093
13094 if (bnxt_hwrm_func_drv_rgtr(bp, NULL, 0, false)) {
13095 rc = -ENODEV;
13096 goto resume_exit;
13097 }
13098
13099 bnxt_get_wol_settings(bp);
13100 if (netif_running(dev)) {
13101 rc = bnxt_open(dev);
13102 if (!rc)
13103 netif_device_attach(dev);
13104 }
13105
13106 resume_exit:
13107 bnxt_ulp_start(bp, rc);
13108 if (!rc)
13109 bnxt_reenable_sriov(bp);
13110 rtnl_unlock();
13111 return rc;
13112 }
13113
13114 static SIMPLE_DEV_PM_OPS(bnxt_pm_ops, bnxt_suspend, bnxt_resume);
13115 #define BNXT_PM_OPS (&bnxt_pm_ops)
13116
13117 #else
13118
13119 #define BNXT_PM_OPS NULL
13120
13121 #endif /* CONFIG_PM_SLEEP */
13122
13123 /**
13124 * bnxt_io_error_detected - called when PCI error is detected
13125 * @pdev: Pointer to PCI device
13126 * @state: The current pci connection state
13127 *
13128 * This function is called after a PCI bus error affecting
13129 * this device has been detected.
13130 */
13131 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
13132 pci_channel_state_t state)
13133 {
13134 struct net_device *netdev = pci_get_drvdata(pdev);
13135 struct bnxt *bp = netdev_priv(netdev);
13136
13137 netdev_info(netdev, "PCI I/O error detected\n");
13138
13139 rtnl_lock();
13140 netif_device_detach(netdev);
13141
13142 bnxt_ulp_stop(bp);
13143
13144 if (state == pci_channel_io_perm_failure) {
13145 rtnl_unlock();
13146 return PCI_ERS_RESULT_DISCONNECT;
13147 }
13148
13149 if (state == pci_channel_io_frozen)
13150 set_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN, &bp->state);
13151
13152 if (netif_running(netdev))
13153 bnxt_close(netdev);
13154
13155 pci_disable_device(pdev);
13156 bnxt_free_ctx_mem(bp);
13157 kfree(bp->ctx);
13158 bp->ctx = NULL;
13159 rtnl_unlock();
13160
13161 /* Request a slot slot reset. */
13162 return PCI_ERS_RESULT_NEED_RESET;
13163 }
13164
13165 /**
13166 * bnxt_io_slot_reset - called after the pci bus has been reset.
13167 * @pdev: Pointer to PCI device
13168 *
13169 * Restart the card from scratch, as if from a cold-boot.
13170 * At this point, the card has exprienced a hard reset,
13171 * followed by fixups by BIOS, and has its config space
13172 * set up identically to what it was at cold boot.
13173 */
13174 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
13175 {
13176 pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
13177 struct net_device *netdev = pci_get_drvdata(pdev);
13178 struct bnxt *bp = netdev_priv(netdev);
13179 int err = 0, off;
13180
13181 netdev_info(bp->dev, "PCI Slot Reset\n");
13182
13183 rtnl_lock();
13184
13185 if (pci_enable_device(pdev)) {
13186 dev_err(&pdev->dev,
13187 "Cannot re-enable PCI device after reset.\n");
13188 } else {
13189 pci_set_master(pdev);
13190 /* Upon fatal error, our device internal logic that latches to
13191 * BAR value is getting reset and will restore only upon
13192 * rewritting the BARs.
13193 *
13194 * As pci_restore_state() does not re-write the BARs if the
13195 * value is same as saved value earlier, driver needs to
13196 * write the BARs to 0 to force restore, in case of fatal error.
13197 */
13198 if (test_and_clear_bit(BNXT_STATE_PCI_CHANNEL_IO_FROZEN,
13199 &bp->state)) {
13200 for (off = PCI_BASE_ADDRESS_0;
13201 off <= PCI_BASE_ADDRESS_5; off += 4)
13202 pci_write_config_dword(bp->pdev, off, 0);
13203 }
13204 pci_restore_state(pdev);
13205 pci_save_state(pdev);
13206
13207 err = bnxt_hwrm_func_reset(bp);
13208 if (!err)
13209 result = PCI_ERS_RESULT_RECOVERED;
13210 }
13211
13212 rtnl_unlock();
13213
13214 return result;
13215 }
13216
13217 /**
13218 * bnxt_io_resume - called when traffic can start flowing again.
13219 * @pdev: Pointer to PCI device
13220 *
13221 * This callback is called when the error recovery driver tells
13222 * us that its OK to resume normal operation.
13223 */
13224 static void bnxt_io_resume(struct pci_dev *pdev)
13225 {
13226 struct net_device *netdev = pci_get_drvdata(pdev);
13227 struct bnxt *bp = netdev_priv(netdev);
13228 int err;
13229
13230 netdev_info(bp->dev, "PCI Slot Resume\n");
13231 rtnl_lock();
13232
13233 err = bnxt_hwrm_func_qcaps(bp);
13234 if (!err && netif_running(netdev))
13235 err = bnxt_open(netdev);
13236
13237 bnxt_ulp_start(bp, err);
13238 if (!err) {
13239 bnxt_reenable_sriov(bp);
13240 netif_device_attach(netdev);
13241 }
13242
13243 rtnl_unlock();
13244 }
13245
13246 static const struct pci_error_handlers bnxt_err_handler = {
13247 .error_detected = bnxt_io_error_detected,
13248 .slot_reset = bnxt_io_slot_reset,
13249 .resume = bnxt_io_resume
13250 };
13251
13252 static struct pci_driver bnxt_pci_driver = {
13253 .name = DRV_MODULE_NAME,
13254 .id_table = bnxt_pci_tbl,
13255 .probe = bnxt_init_one,
13256 .remove = bnxt_remove_one,
13257 .shutdown = bnxt_shutdown,
13258 .driver.pm = BNXT_PM_OPS,
13259 .err_handler = &bnxt_err_handler,
13260 #if defined(CONFIG_BNXT_SRIOV)
13261 .sriov_configure = bnxt_sriov_configure,
13262 #endif
13263 };
13264
13265 static int __init bnxt_init(void)
13266 {
13267 bnxt_debug_init();
13268 return pci_register_driver(&bnxt_pci_driver);
13269 }
13270
13271 static void __exit bnxt_exit(void)
13272 {
13273 pci_unregister_driver(&bnxt_pci_driver);
13274 if (bnxt_pf_wq)
13275 destroy_workqueue(bnxt_pf_wq);
13276 bnxt_debug_exit();
13277 }
13278
13279 module_init(bnxt_init);
13280 module_exit(bnxt_exit);
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