1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
59 #define BNXT_TX_TIMEOUT (5 * HZ)
61 static const char version
[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION
);
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
72 #define BNXT_TX_PUSH_THRESH 164
85 /* indexed by enum above */
89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
99 static const struct pci_device_id bnxt_pci_tbl
[] = {
100 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
101 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
102 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
103 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
104 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
105 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
106 #ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= BCM57304_VF
},
108 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= BCM57404_VF
},
113 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
115 static const u16 bnxt_vf_req_snif
[] = {
118 HWRM_CFA_L2_FILTER_ALLOC
,
121 static bool bnxt_vf_pciid(enum board_idx idx
)
123 return (idx
== BCM57304_VF
|| idx
== BCM57404_VF
);
126 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
127 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
128 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
130 #define BNXT_CP_DB_REARM(db, raw_cons) \
131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
133 #define BNXT_CP_DB(db, raw_cons) \
134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
136 #define BNXT_CP_DB_IRQ_DIS(db) \
137 writel(DB_CP_IRQ_DIS_FLAGS, db)
139 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
141 /* Tell compiler to fetch tx indices from memory. */
144 return bp
->tx_ring_size
-
145 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
148 static const u16 bnxt_lhint_arr
[] = {
149 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
150 TX_BD_FLAGS_LHINT_512_TO_1023
,
151 TX_BD_FLAGS_LHINT_1024_TO_2047
,
152 TX_BD_FLAGS_LHINT_1024_TO_2047
,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
170 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
172 struct bnxt
*bp
= netdev_priv(dev
);
174 struct tx_bd_ext
*txbd1
;
175 struct netdev_queue
*txq
;
178 unsigned int length
, pad
= 0;
179 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
181 struct pci_dev
*pdev
= bp
->pdev
;
182 struct bnxt_tx_ring_info
*txr
;
183 struct bnxt_sw_tx_bd
*tx_buf
;
185 i
= skb_get_queue_mapping(skb
);
186 if (unlikely(i
>= bp
->tx_nr_rings
)) {
187 dev_kfree_skb_any(skb
);
191 txr
= &bp
->tx_ring
[i
];
192 txq
= netdev_get_tx_queue(dev
, i
);
195 free_size
= bnxt_tx_avail(bp
, txr
);
196 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
197 netif_tx_stop_queue(txq
);
198 return NETDEV_TX_BUSY
;
202 len
= skb_headlen(skb
);
203 last_frag
= skb_shinfo(skb
)->nr_frags
;
205 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
207 txbd
->tx_bd_opaque
= prod
;
209 tx_buf
= &txr
->tx_buf_ring
[prod
];
211 tx_buf
->nr_frags
= last_frag
;
215 if (skb_vlan_tag_present(skb
)) {
216 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
217 skb_vlan_tag_get(skb
);
218 /* Currently supports 8021Q, 8021AD vlan offloads
219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
221 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
222 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
225 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
226 struct tx_push_buffer
*tx_push_buf
= txr
->tx_push
;
227 struct tx_push_bd
*tx_push
= &tx_push_buf
->push_bd
;
228 struct tx_bd_ext
*tx_push1
= &tx_push
->txbd2
;
229 void *pdata
= tx_push_buf
->data
;
233 /* Set COAL_NOW to be ready quickly for the next push */
234 tx_push
->tx_bd_len_flags_type
=
235 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
236 TX_BD_TYPE_LONG_TX_BD
|
237 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
238 TX_BD_FLAGS_COAL_NOW
|
239 TX_BD_FLAGS_PACKET_END
|
240 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
242 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
243 tx_push1
->tx_bd_hsize_lflags
=
244 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
246 tx_push1
->tx_bd_hsize_lflags
= 0;
248 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
249 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
251 end
= PTR_ALIGN(pdata
+ length
+ 1, 8) - 1;
254 skb_copy_from_linear_data(skb
, pdata
, len
);
256 for (j
= 0; j
< last_frag
; j
++) {
257 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
260 fptr
= skb_frag_address_safe(frag
);
264 memcpy(pdata
, fptr
, skb_frag_size(frag
));
265 pdata
+= skb_frag_size(frag
);
268 txbd
->tx_bd_len_flags_type
= tx_push
->tx_bd_len_flags_type
;
269 txbd
->tx_bd_haddr
= txr
->data_mapping
;
270 prod
= NEXT_TX(prod
);
271 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
272 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
273 prod
= NEXT_TX(prod
);
275 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
278 netdev_tx_sent_queue(txq
, skb
->len
);
280 push_len
= (length
+ sizeof(*tx_push
) + 7) / 8;
282 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
, 16);
283 __iowrite64_copy(txr
->tx_doorbell
+ 4, tx_push_buf
+ 1,
286 __iowrite64_copy(txr
->tx_doorbell
, tx_push_buf
,
295 if (length
< BNXT_MIN_PKT_SIZE
) {
296 pad
= BNXT_MIN_PKT_SIZE
- length
;
297 if (skb_pad(skb
, pad
)) {
298 /* SKB already freed. */
302 length
= BNXT_MIN_PKT_SIZE
;
305 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
307 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
308 dev_kfree_skb_any(skb
);
313 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
314 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
315 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
317 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
319 prod
= NEXT_TX(prod
);
320 txbd1
= (struct tx_bd_ext
*)
321 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
323 txbd1
->tx_bd_hsize_lflags
= 0;
324 if (skb_is_gso(skb
)) {
327 if (skb
->encapsulation
)
328 hdr_len
= skb_inner_network_offset(skb
) +
329 skb_inner_network_header_len(skb
) +
330 inner_tcp_hdrlen(skb
);
332 hdr_len
= skb_transport_offset(skb
) +
335 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
337 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
338 length
= skb_shinfo(skb
)->gso_size
;
339 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
341 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
342 txbd1
->tx_bd_hsize_lflags
=
343 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
344 txbd1
->tx_bd_mss
= 0;
348 flags
|= bnxt_lhint_arr
[length
];
349 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
351 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
352 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
353 for (i
= 0; i
< last_frag
; i
++) {
354 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
356 prod
= NEXT_TX(prod
);
357 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
359 len
= skb_frag_size(frag
);
360 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
363 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
366 tx_buf
= &txr
->tx_buf_ring
[prod
];
367 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
369 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
371 flags
= len
<< TX_BD_LEN_SHIFT
;
372 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
376 txbd
->tx_bd_len_flags_type
=
377 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
378 TX_BD_FLAGS_PACKET_END
);
380 netdev_tx_sent_queue(txq
, skb
->len
);
382 /* Sync BD data before updating doorbell */
385 prod
= NEXT_TX(prod
);
388 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
389 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
395 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
396 netif_tx_stop_queue(txq
);
398 /* netif_tx_stop_queue() must be done before checking
399 * tx index in bnxt_tx_avail() below, because in
400 * bnxt_tx_int(), we update tx index before checking for
401 * netif_tx_queue_stopped().
404 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
405 netif_tx_wake_queue(txq
);
412 /* start back at beginning and unmap skb */
414 tx_buf
= &txr
->tx_buf_ring
[prod
];
416 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
417 skb_headlen(skb
), PCI_DMA_TODEVICE
);
418 prod
= NEXT_TX(prod
);
420 /* unmap remaining mapped pages */
421 for (i
= 0; i
< last_frag
; i
++) {
422 prod
= NEXT_TX(prod
);
423 tx_buf
= &txr
->tx_buf_ring
[prod
];
424 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
425 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
429 dev_kfree_skb_any(skb
);
433 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
435 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
436 int index
= txr
- &bp
->tx_ring
[0];
437 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
438 u16 cons
= txr
->tx_cons
;
439 struct pci_dev
*pdev
= bp
->pdev
;
441 unsigned int tx_bytes
= 0;
443 for (i
= 0; i
< nr_pkts
; i
++) {
444 struct bnxt_sw_tx_bd
*tx_buf
;
448 tx_buf
= &txr
->tx_buf_ring
[cons
];
449 cons
= NEXT_TX(cons
);
453 if (tx_buf
->is_push
) {
458 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
459 skb_headlen(skb
), PCI_DMA_TODEVICE
);
460 last
= tx_buf
->nr_frags
;
462 for (j
= 0; j
< last
; j
++) {
463 cons
= NEXT_TX(cons
);
464 tx_buf
= &txr
->tx_buf_ring
[cons
];
467 dma_unmap_addr(tx_buf
, mapping
),
468 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
473 cons
= NEXT_TX(cons
);
475 tx_bytes
+= skb
->len
;
476 dev_kfree_skb_any(skb
);
479 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
482 /* Need to make the tx_cons update visible to bnxt_start_xmit()
483 * before checking for netif_tx_queue_stopped(). Without the
484 * memory barrier, there is a small possibility that bnxt_start_xmit()
485 * will miss it and cause the queue to be stopped forever.
489 if (unlikely(netif_tx_queue_stopped(txq
)) &&
490 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
491 __netif_tx_lock(txq
, smp_processor_id());
492 if (netif_tx_queue_stopped(txq
) &&
493 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
494 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
495 netif_tx_wake_queue(txq
);
496 __netif_tx_unlock(txq
);
500 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
504 struct pci_dev
*pdev
= bp
->pdev
;
506 data
= kmalloc(bp
->rx_buf_size
, gfp
);
510 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
511 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
513 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
520 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
521 struct bnxt_rx_ring_info
*rxr
,
524 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
525 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
529 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
534 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
536 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
541 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
544 u16 prod
= rxr
->rx_prod
;
545 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
546 struct rx_bd
*cons_bd
, *prod_bd
;
548 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
549 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
551 prod_rx_buf
->data
= data
;
553 dma_unmap_addr_set(prod_rx_buf
, mapping
,
554 dma_unmap_addr(cons_rx_buf
, mapping
));
556 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
557 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
559 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
562 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
564 u16 next
, max
= rxr
->rx_agg_bmap_size
;
566 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
568 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
572 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
573 struct bnxt_rx_ring_info
*rxr
,
577 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
578 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
579 struct pci_dev
*pdev
= bp
->pdev
;
582 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
584 page
= alloc_page(gfp
);
588 mapping
= dma_map_page(&pdev
->dev
, page
, 0, PAGE_SIZE
,
590 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
595 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
596 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
598 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
599 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
600 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
602 rx_agg_buf
->page
= page
;
603 rx_agg_buf
->mapping
= mapping
;
604 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
605 rxbd
->rx_bd_opaque
= sw_prod
;
609 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
612 struct bnxt
*bp
= bnapi
->bp
;
613 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
614 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
615 u16 prod
= rxr
->rx_agg_prod
;
616 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
619 for (i
= 0; i
< agg_bufs
; i
++) {
621 struct rx_agg_cmp
*agg
;
622 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
623 struct rx_bd
*prod_bd
;
626 agg
= (struct rx_agg_cmp
*)
627 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
628 cons
= agg
->rx_agg_cmp_opaque
;
629 __clear_bit(cons
, rxr
->rx_agg_bmap
);
631 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
632 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
634 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
635 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
636 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
638 /* It is possible for sw_prod to be equal to cons, so
639 * set cons_rx_buf->page to NULL first.
641 page
= cons_rx_buf
->page
;
642 cons_rx_buf
->page
= NULL
;
643 prod_rx_buf
->page
= page
;
645 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
647 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
649 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
650 prod_bd
->rx_bd_opaque
= sw_prod
;
652 prod
= NEXT_RX_AGG(prod
);
653 sw_prod
= NEXT_RX_AGG(sw_prod
);
654 cp_cons
= NEXT_CMP(cp_cons
);
656 rxr
->rx_agg_prod
= prod
;
657 rxr
->rx_sw_agg_prod
= sw_prod
;
660 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
661 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
662 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
668 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
670 bnxt_reuse_rx_data(rxr
, cons
, data
);
674 skb
= build_skb(data
, 0);
675 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
682 skb_reserve(skb
, BNXT_RX_OFFSET
);
687 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
688 struct sk_buff
*skb
, u16 cp_cons
,
691 struct pci_dev
*pdev
= bp
->pdev
;
692 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
693 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
694 u16 prod
= rxr
->rx_agg_prod
;
697 for (i
= 0; i
< agg_bufs
; i
++) {
699 struct rx_agg_cmp
*agg
;
700 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
704 agg
= (struct rx_agg_cmp
*)
705 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
706 cons
= agg
->rx_agg_cmp_opaque
;
707 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
708 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
710 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
711 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
, 0, frag_len
);
712 __clear_bit(cons
, rxr
->rx_agg_bmap
);
714 /* It is possible for bnxt_alloc_rx_page() to allocate
715 * a sw_prod index that equals the cons index, so we
716 * need to clear the cons entry now.
718 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
719 page
= cons_rx_buf
->page
;
720 cons_rx_buf
->page
= NULL
;
722 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
723 struct skb_shared_info
*shinfo
;
724 unsigned int nr_frags
;
726 shinfo
= skb_shinfo(skb
);
727 nr_frags
= --shinfo
->nr_frags
;
728 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
732 cons_rx_buf
->page
= page
;
734 /* Update prod since possibly some pages have been
737 rxr
->rx_agg_prod
= prod
;
738 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
742 dma_unmap_page(&pdev
->dev
, mapping
, PAGE_SIZE
,
745 skb
->data_len
+= frag_len
;
746 skb
->len
+= frag_len
;
747 skb
->truesize
+= PAGE_SIZE
;
749 prod
= NEXT_RX_AGG(prod
);
750 cp_cons
= NEXT_CMP(cp_cons
);
752 rxr
->rx_agg_prod
= prod
;
756 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
757 u8 agg_bufs
, u32
*raw_cons
)
760 struct rx_agg_cmp
*agg
;
762 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
763 last
= RING_CMP(*raw_cons
);
764 agg
= (struct rx_agg_cmp
*)
765 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
766 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
769 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
773 struct bnxt
*bp
= bnapi
->bp
;
774 struct pci_dev
*pdev
= bp
->pdev
;
777 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
781 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
782 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
784 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
786 dma_sync_single_for_device(&pdev
->dev
, mapping
,
794 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
795 struct rx_tpa_start_cmp
*tpa_start
,
796 struct rx_tpa_start_cmp_ext
*tpa_start1
)
798 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
800 struct bnxt_tpa_info
*tpa_info
;
801 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
802 struct rx_bd
*prod_bd
;
805 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
807 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
808 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
809 tpa_info
= &rxr
->rx_tpa
[agg_id
];
811 prod_rx_buf
->data
= tpa_info
->data
;
813 mapping
= tpa_info
->mapping
;
814 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
816 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
818 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
820 tpa_info
->data
= cons_rx_buf
->data
;
821 cons_rx_buf
->data
= NULL
;
822 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
825 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
826 RX_TPA_START_CMP_LEN_SHIFT
;
827 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
828 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
830 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
831 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
832 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
834 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
836 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
838 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
839 tpa_info
->gso_type
= 0;
840 if (netif_msg_rx_err(bp
))
841 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
843 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
844 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
846 rxr
->rx_prod
= NEXT_RX(prod
);
847 cons
= NEXT_RX(cons
);
848 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
850 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
851 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
852 cons_rx_buf
->data
= NULL
;
855 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
856 u16 cp_cons
, u32 agg_bufs
)
859 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
862 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
863 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
865 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt_tpa_info
*tpa_info
,
866 struct rx_tpa_end_cmp
*tpa_end
,
867 struct rx_tpa_end_cmp_ext
*tpa_end1
,
872 int payload_off
, tcp_opt_len
= 0;
876 segs
= TPA_END_TPA_SEGS(tpa_end
);
880 NAPI_GRO_CB(skb
)->count
= segs
;
881 skb_shinfo(skb
)->gso_size
=
882 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
883 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
884 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
885 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
886 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
887 if (TPA_END_GRO_TS(tpa_end
))
890 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
893 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
895 skb_set_network_header(skb
, nw_off
);
897 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
898 len
= skb
->len
- skb_transport_offset(skb
);
900 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
901 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
904 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
906 skb_set_network_header(skb
, nw_off
);
908 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
909 len
= skb
->len
- skb_transport_offset(skb
);
911 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
913 dev_kfree_skb_any(skb
);
916 tcp_gro_complete(skb
);
918 if (nw_off
) { /* tunnel */
919 struct udphdr
*uh
= NULL
;
921 if (skb
->protocol
== htons(ETH_P_IP
)) {
922 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
924 if (iph
->protocol
== IPPROTO_UDP
)
925 uh
= (struct udphdr
*)(iph
+ 1);
927 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
929 if (iph
->nexthdr
== IPPROTO_UDP
)
930 uh
= (struct udphdr
*)(iph
+ 1);
934 skb_shinfo(skb
)->gso_type
|=
935 SKB_GSO_UDP_TUNNEL_CSUM
;
937 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
944 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
945 struct bnxt_napi
*bnapi
,
947 struct rx_tpa_end_cmp
*tpa_end
,
948 struct rx_tpa_end_cmp_ext
*tpa_end1
,
951 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
952 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
953 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
955 u16 cp_cons
= RING_CMP(*raw_cons
);
957 struct bnxt_tpa_info
*tpa_info
;
961 tpa_info
= &rxr
->rx_tpa
[agg_id
];
962 data
= tpa_info
->data
;
965 mapping
= tpa_info
->mapping
;
967 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
968 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
971 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
972 return ERR_PTR(-EBUSY
);
975 cp_cons
= NEXT_CMP(cp_cons
);
978 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
979 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
980 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
981 agg_bufs
, (int)MAX_SKB_FRAGS
);
985 if (len
<= bp
->rx_copy_thresh
) {
986 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
988 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
993 dma_addr_t new_mapping
;
995 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
997 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1001 tpa_info
->data
= new_data
;
1002 tpa_info
->mapping
= new_mapping
;
1004 skb
= build_skb(data
, 0);
1005 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
1006 PCI_DMA_FROMDEVICE
);
1010 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1013 skb_reserve(skb
, BNXT_RX_OFFSET
);
1018 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1020 /* Page reuse already handled by bnxt_rx_pages(). */
1024 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1026 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1027 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1029 if (tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) {
1030 netdev_features_t features
= skb
->dev
->features
;
1031 u16 vlan_proto
= tpa_info
->metadata
>>
1032 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1034 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1035 vlan_proto
== ETH_P_8021Q
) ||
1036 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1037 vlan_proto
== ETH_P_8021AD
)) {
1038 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1039 tpa_info
->metadata
&
1040 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1044 skb_checksum_none_assert(skb
);
1045 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1046 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1048 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1051 if (TPA_END_GRO(tpa_end
))
1052 skb
= bnxt_gro_skb(tpa_info
, tpa_end
, tpa_end1
, skb
);
1057 /* returns the following:
1058 * 1 - 1 packet successfully received
1059 * 0 - successful TPA_START, packet not completed yet
1060 * -EBUSY - completion ring does not have all the agg buffers yet
1061 * -ENOMEM - packet aborted due to out of memory
1062 * -EIO - packet aborted due to hw error indicated in BD
1064 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1067 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1068 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1069 struct net_device
*dev
= bp
->dev
;
1070 struct rx_cmp
*rxcmp
;
1071 struct rx_cmp_ext
*rxcmp1
;
1072 u32 tmp_raw_cons
= *raw_cons
;
1073 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1074 struct bnxt_sw_rx_bd
*rx_buf
;
1076 u8
*data
, agg_bufs
, cmp_type
;
1077 dma_addr_t dma_addr
;
1078 struct sk_buff
*skb
;
1081 rxcmp
= (struct rx_cmp
*)
1082 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1084 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1085 cp_cons
= RING_CMP(tmp_raw_cons
);
1086 rxcmp1
= (struct rx_cmp_ext
*)
1087 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1089 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1092 cmp_type
= RX_CMP_TYPE(rxcmp
);
1094 prod
= rxr
->rx_prod
;
1096 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1097 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1098 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1100 goto next_rx_no_prod
;
1102 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1103 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1104 (struct rx_tpa_end_cmp
*)rxcmp
,
1105 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1108 if (unlikely(IS_ERR(skb
)))
1113 skb_record_rx_queue(skb
, bnapi
->index
);
1114 skb_mark_napi_id(skb
, &bnapi
->napi
);
1115 if (bnxt_busy_polling(bnapi
))
1116 netif_receive_skb(skb
);
1118 napi_gro_receive(&bnapi
->napi
, skb
);
1121 goto next_rx_no_prod
;
1124 cons
= rxcmp
->rx_cmp_opaque
;
1125 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1126 data
= rx_buf
->data
;
1129 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1130 RX_CMP_AGG_BUFS_SHIFT
;
1133 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1136 cp_cons
= NEXT_CMP(cp_cons
);
1140 rx_buf
->data
= NULL
;
1141 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1142 bnxt_reuse_rx_data(rxr
, cons
, data
);
1144 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1150 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1151 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1153 if (len
<= bp
->rx_copy_thresh
) {
1154 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1155 bnxt_reuse_rx_data(rxr
, cons
, data
);
1161 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1169 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1176 if (RX_CMP_HASH_VALID(rxcmp
)) {
1177 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1178 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1180 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1181 if (hash_type
!= 1 && hash_type
!= 3)
1182 type
= PKT_HASH_TYPE_L3
;
1183 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1186 skb
->protocol
= eth_type_trans(skb
, dev
);
1188 if (rxcmp1
->rx_cmp_flags2
&
1189 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) {
1190 netdev_features_t features
= skb
->dev
->features
;
1191 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1192 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1194 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1195 vlan_proto
== ETH_P_8021Q
) ||
1196 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1197 vlan_proto
== ETH_P_8021AD
))
1198 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1200 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1203 skb_checksum_none_assert(skb
);
1204 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1205 if (dev
->features
& NETIF_F_RXCSUM
) {
1206 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1207 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1210 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1211 if (dev
->features
& NETIF_F_RXCSUM
)
1212 cpr
->rx_l4_csum_errors
++;
1216 skb_record_rx_queue(skb
, bnapi
->index
);
1217 skb_mark_napi_id(skb
, &bnapi
->napi
);
1218 if (bnxt_busy_polling(bnapi
))
1219 netif_receive_skb(skb
);
1221 napi_gro_receive(&bnapi
->napi
, skb
);
1225 rxr
->rx_prod
= NEXT_RX(prod
);
1228 *raw_cons
= tmp_raw_cons
;
1233 static int bnxt_async_event_process(struct bnxt
*bp
,
1234 struct hwrm_async_event_cmpl
*cmpl
)
1236 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1238 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1240 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1241 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1242 schedule_work(&bp
->sp_task
);
1245 netdev_err(bp
->dev
, "unhandled ASYNC event (id 0x%x)\n",
1252 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1254 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1255 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1256 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1257 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1259 switch (cmpl_type
) {
1260 case CMPL_BASE_TYPE_HWRM_DONE
:
1261 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1262 if (seq_id
== bp
->hwrm_intr_seq_id
)
1263 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1265 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1268 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1269 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1271 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1272 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1273 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1278 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1279 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1280 schedule_work(&bp
->sp_task
);
1283 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1284 bnxt_async_event_process(bp
,
1285 (struct hwrm_async_event_cmpl
*)txcmp
);
1294 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1296 struct bnxt_napi
*bnapi
= dev_instance
;
1297 struct bnxt
*bp
= bnapi
->bp
;
1298 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1299 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1301 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1302 napi_schedule(&bnapi
->napi
);
1306 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1308 u32 raw_cons
= cpr
->cp_raw_cons
;
1309 u16 cons
= RING_CMP(raw_cons
);
1310 struct tx_cmp
*txcmp
;
1312 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1314 return TX_CMP_VALID(txcmp
, raw_cons
);
1317 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1319 struct bnxt_napi
*bnapi
= dev_instance
;
1320 struct bnxt
*bp
= bnapi
->bp
;
1321 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1322 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1325 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1327 if (!bnxt_has_work(bp
, cpr
)) {
1328 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1329 /* return if erroneous interrupt */
1330 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1334 /* disable ring IRQ */
1335 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1337 /* Return here if interrupt is shared and is disabled. */
1338 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1341 napi_schedule(&bnapi
->napi
);
1345 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1347 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1348 u32 raw_cons
= cpr
->cp_raw_cons
;
1352 bool rx_event
= false;
1353 bool agg_event
= false;
1354 struct tx_cmp
*txcmp
;
1359 cons
= RING_CMP(raw_cons
);
1360 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1362 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1365 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1367 /* return full budget so NAPI will complete. */
1368 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1370 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1371 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1372 if (likely(rc
>= 0))
1374 else if (rc
== -EBUSY
) /* partial completion */
1377 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1378 CMPL_BASE_TYPE_HWRM_DONE
) ||
1379 (TX_CMP_TYPE(txcmp
) ==
1380 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1381 (TX_CMP_TYPE(txcmp
) ==
1382 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1383 bnxt_hwrm_handler(bp
, txcmp
);
1385 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1387 if (rx_pkts
== budget
)
1391 cpr
->cp_raw_cons
= raw_cons
;
1392 /* ACK completion ring before freeing tx ring and producing new
1393 * buffers in rx/agg rings to prevent overflowing the completion
1396 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1399 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1402 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1404 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1405 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1407 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1408 rxr
->rx_agg_doorbell
);
1409 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1410 rxr
->rx_agg_doorbell
);
1416 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1418 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1419 struct bnxt
*bp
= bnapi
->bp
;
1420 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1423 if (!bnxt_lock_napi(bnapi
))
1427 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1429 if (work_done
>= budget
)
1432 if (!bnxt_has_work(bp
, cpr
)) {
1433 napi_complete(napi
);
1434 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1439 bnxt_unlock_napi(bnapi
);
1443 #ifdef CONFIG_NET_RX_BUSY_POLL
1444 static int bnxt_busy_poll(struct napi_struct
*napi
)
1446 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1447 struct bnxt
*bp
= bnapi
->bp
;
1448 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1449 int rx_work
, budget
= 4;
1451 if (atomic_read(&bp
->intr_sem
) != 0)
1452 return LL_FLUSH_FAILED
;
1454 if (!bnxt_lock_poll(bnapi
))
1455 return LL_FLUSH_BUSY
;
1457 rx_work
= bnxt_poll_work(bp
, bnapi
, budget
);
1459 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1461 bnxt_unlock_poll(bnapi
);
1466 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1469 struct pci_dev
*pdev
= bp
->pdev
;
1474 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1475 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1476 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1479 for (j
= 0; j
< max_idx
;) {
1480 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1481 struct sk_buff
*skb
= tx_buf
->skb
;
1491 if (tx_buf
->is_push
) {
1497 dma_unmap_single(&pdev
->dev
,
1498 dma_unmap_addr(tx_buf
, mapping
),
1502 last
= tx_buf
->nr_frags
;
1504 for (k
= 0; k
< last
; k
++, j
++) {
1505 int ring_idx
= j
& bp
->tx_ring_mask
;
1506 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1508 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1511 dma_unmap_addr(tx_buf
, mapping
),
1512 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1516 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1520 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1522 int i
, max_idx
, max_agg_idx
;
1523 struct pci_dev
*pdev
= bp
->pdev
;
1528 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1529 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1530 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1531 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1535 for (j
= 0; j
< MAX_TPA
; j
++) {
1536 struct bnxt_tpa_info
*tpa_info
=
1538 u8
*data
= tpa_info
->data
;
1545 dma_unmap_addr(tpa_info
, mapping
),
1546 bp
->rx_buf_use_size
,
1547 PCI_DMA_FROMDEVICE
);
1549 tpa_info
->data
= NULL
;
1555 for (j
= 0; j
< max_idx
; j
++) {
1556 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1557 u8
*data
= rx_buf
->data
;
1562 dma_unmap_single(&pdev
->dev
,
1563 dma_unmap_addr(rx_buf
, mapping
),
1564 bp
->rx_buf_use_size
,
1565 PCI_DMA_FROMDEVICE
);
1567 rx_buf
->data
= NULL
;
1572 for (j
= 0; j
< max_agg_idx
; j
++) {
1573 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1574 &rxr
->rx_agg_ring
[j
];
1575 struct page
*page
= rx_agg_buf
->page
;
1580 dma_unmap_page(&pdev
->dev
,
1581 dma_unmap_addr(rx_agg_buf
, mapping
),
1582 PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1584 rx_agg_buf
->page
= NULL
;
1585 __clear_bit(j
, rxr
->rx_agg_bmap
);
1592 static void bnxt_free_skbs(struct bnxt
*bp
)
1594 bnxt_free_tx_skbs(bp
);
1595 bnxt_free_rx_skbs(bp
);
1598 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1600 struct pci_dev
*pdev
= bp
->pdev
;
1603 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1604 if (!ring
->pg_arr
[i
])
1607 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1608 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1610 ring
->pg_arr
[i
] = NULL
;
1613 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1614 ring
->pg_tbl
, ring
->pg_tbl_map
);
1615 ring
->pg_tbl
= NULL
;
1617 if (ring
->vmem_size
&& *ring
->vmem
) {
1623 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1626 struct pci_dev
*pdev
= bp
->pdev
;
1628 if (ring
->nr_pages
> 1) {
1629 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1637 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1638 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1642 if (!ring
->pg_arr
[i
])
1645 if (ring
->nr_pages
> 1)
1646 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1649 if (ring
->vmem_size
) {
1650 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1657 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1664 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1665 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1666 struct bnxt_ring_struct
*ring
;
1671 kfree(rxr
->rx_agg_bmap
);
1672 rxr
->rx_agg_bmap
= NULL
;
1674 ring
= &rxr
->rx_ring_struct
;
1675 bnxt_free_ring(bp
, ring
);
1677 ring
= &rxr
->rx_agg_ring_struct
;
1678 bnxt_free_ring(bp
, ring
);
1682 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
1684 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
1689 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
1692 if (bp
->flags
& BNXT_FLAG_TPA
)
1695 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1696 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1697 struct bnxt_ring_struct
*ring
;
1699 ring
= &rxr
->rx_ring_struct
;
1701 rc
= bnxt_alloc_ring(bp
, ring
);
1708 ring
= &rxr
->rx_agg_ring_struct
;
1709 rc
= bnxt_alloc_ring(bp
, ring
);
1713 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
1714 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
1715 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
1716 if (!rxr
->rx_agg_bmap
)
1720 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
1721 sizeof(struct bnxt_tpa_info
),
1731 static void bnxt_free_tx_rings(struct bnxt
*bp
)
1734 struct pci_dev
*pdev
= bp
->pdev
;
1739 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1740 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1741 struct bnxt_ring_struct
*ring
;
1744 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
1745 txr
->tx_push
, txr
->tx_push_mapping
);
1746 txr
->tx_push
= NULL
;
1749 ring
= &txr
->tx_ring_struct
;
1751 bnxt_free_ring(bp
, ring
);
1755 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
1758 struct pci_dev
*pdev
= bp
->pdev
;
1760 bp
->tx_push_size
= 0;
1761 if (bp
->tx_push_thresh
) {
1764 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
1765 bp
->tx_push_thresh
);
1767 if (push_size
> 256) {
1769 bp
->tx_push_thresh
= 0;
1772 bp
->tx_push_size
= push_size
;
1775 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
1776 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1777 struct bnxt_ring_struct
*ring
;
1779 ring
= &txr
->tx_ring_struct
;
1781 rc
= bnxt_alloc_ring(bp
, ring
);
1785 if (bp
->tx_push_size
) {
1788 /* One pre-allocated DMA buffer to backup
1791 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
1793 &txr
->tx_push_mapping
,
1799 mapping
= txr
->tx_push_mapping
+
1800 sizeof(struct tx_push_bd
);
1801 txr
->data_mapping
= cpu_to_le64(mapping
);
1803 memset(txr
->tx_push
, 0, sizeof(struct tx_push_bd
));
1805 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
1806 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
1812 static void bnxt_free_cp_rings(struct bnxt
*bp
)
1819 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1820 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1821 struct bnxt_cp_ring_info
*cpr
;
1822 struct bnxt_ring_struct
*ring
;
1827 cpr
= &bnapi
->cp_ring
;
1828 ring
= &cpr
->cp_ring_struct
;
1830 bnxt_free_ring(bp
, ring
);
1834 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
1838 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1839 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1840 struct bnxt_cp_ring_info
*cpr
;
1841 struct bnxt_ring_struct
*ring
;
1846 cpr
= &bnapi
->cp_ring
;
1847 ring
= &cpr
->cp_ring_struct
;
1849 rc
= bnxt_alloc_ring(bp
, ring
);
1856 static void bnxt_init_ring_struct(struct bnxt
*bp
)
1860 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1861 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1862 struct bnxt_cp_ring_info
*cpr
;
1863 struct bnxt_rx_ring_info
*rxr
;
1864 struct bnxt_tx_ring_info
*txr
;
1865 struct bnxt_ring_struct
*ring
;
1870 cpr
= &bnapi
->cp_ring
;
1871 ring
= &cpr
->cp_ring_struct
;
1872 ring
->nr_pages
= bp
->cp_nr_pages
;
1873 ring
->page_size
= HW_CMPD_RING_SIZE
;
1874 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
1875 ring
->dma_arr
= cpr
->cp_desc_mapping
;
1876 ring
->vmem_size
= 0;
1878 rxr
= bnapi
->rx_ring
;
1882 ring
= &rxr
->rx_ring_struct
;
1883 ring
->nr_pages
= bp
->rx_nr_pages
;
1884 ring
->page_size
= HW_RXBD_RING_SIZE
;
1885 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
1886 ring
->dma_arr
= rxr
->rx_desc_mapping
;
1887 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
1888 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
1890 ring
= &rxr
->rx_agg_ring_struct
;
1891 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
1892 ring
->page_size
= HW_RXBD_RING_SIZE
;
1893 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
1894 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
1895 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
1896 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
1899 txr
= bnapi
->tx_ring
;
1903 ring
= &txr
->tx_ring_struct
;
1904 ring
->nr_pages
= bp
->tx_nr_pages
;
1905 ring
->page_size
= HW_RXBD_RING_SIZE
;
1906 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
1907 ring
->dma_arr
= txr
->tx_desc_mapping
;
1908 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
1909 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
1913 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
1917 struct rx_bd
**rx_buf_ring
;
1919 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
1920 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
1924 rxbd
= rx_buf_ring
[i
];
1928 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
1929 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
1930 rxbd
->rx_bd_opaque
= prod
;
1935 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
1937 struct net_device
*dev
= bp
->dev
;
1938 struct bnxt_rx_ring_info
*rxr
;
1939 struct bnxt_ring_struct
*ring
;
1943 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
1944 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
1946 if (NET_IP_ALIGN
== 2)
1947 type
|= RX_BD_FLAGS_SOP
;
1949 rxr
= &bp
->rx_ring
[ring_nr
];
1950 ring
= &rxr
->rx_ring_struct
;
1951 bnxt_init_rxbd_pages(ring
, type
);
1953 prod
= rxr
->rx_prod
;
1954 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
1955 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1956 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
1957 ring_nr
, i
, bp
->rx_ring_size
);
1960 prod
= NEXT_RX(prod
);
1962 rxr
->rx_prod
= prod
;
1963 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1965 ring
= &rxr
->rx_agg_ring_struct
;
1966 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1968 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
1971 type
= ((u32
)PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
1972 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
1974 bnxt_init_rxbd_pages(ring
, type
);
1976 prod
= rxr
->rx_agg_prod
;
1977 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
1978 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1979 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
1980 ring_nr
, i
, bp
->rx_ring_size
);
1983 prod
= NEXT_RX_AGG(prod
);
1985 rxr
->rx_agg_prod
= prod
;
1987 if (bp
->flags
& BNXT_FLAG_TPA
) {
1992 for (i
= 0; i
< MAX_TPA
; i
++) {
1993 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
1998 rxr
->rx_tpa
[i
].data
= data
;
1999 rxr
->rx_tpa
[i
].mapping
= mapping
;
2002 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2010 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2014 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2015 rc
= bnxt_init_one_rx_ring(bp
, i
);
2023 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2027 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2030 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2031 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2032 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2034 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2040 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2042 kfree(bp
->grp_info
);
2043 bp
->grp_info
= NULL
;
2046 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2051 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2052 sizeof(struct bnxt_ring_grp_info
),
2057 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2059 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2060 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2061 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2062 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2063 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2068 static void bnxt_free_vnics(struct bnxt
*bp
)
2070 kfree(bp
->vnic_info
);
2071 bp
->vnic_info
= NULL
;
2075 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2079 #ifdef CONFIG_RFS_ACCEL
2080 if (bp
->flags
& BNXT_FLAG_RFS
)
2081 num_vnics
+= bp
->rx_nr_rings
;
2084 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2089 bp
->nr_vnics
= num_vnics
;
2093 static void bnxt_init_vnics(struct bnxt
*bp
)
2097 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2098 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2100 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2101 vnic
->fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
2102 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2104 if (bp
->vnic_info
[i
].rss_hash_key
) {
2106 prandom_bytes(vnic
->rss_hash_key
,
2109 memcpy(vnic
->rss_hash_key
,
2110 bp
->vnic_info
[0].rss_hash_key
,
2116 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2120 pages
= ring_size
/ desc_per_pg
;
2127 while (pages
& (pages
- 1))
2133 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2135 bp
->flags
&= ~BNXT_FLAG_TPA
;
2136 if (bp
->dev
->features
& NETIF_F_LRO
)
2137 bp
->flags
|= BNXT_FLAG_LRO
;
2138 if ((bp
->dev
->features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
2139 bp
->flags
|= BNXT_FLAG_GRO
;
2142 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2145 void bnxt_set_ring_params(struct bnxt
*bp
)
2147 u32 ring_size
, rx_size
, rx_space
;
2148 u32 agg_factor
= 0, agg_ring_size
= 0;
2150 /* 8 for CRC and VLAN */
2151 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2153 rx_space
= rx_size
+ NET_SKB_PAD
+
2154 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2156 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2157 ring_size
= bp
->rx_ring_size
;
2158 bp
->rx_agg_ring_size
= 0;
2159 bp
->rx_agg_nr_pages
= 0;
2161 if (bp
->flags
& BNXT_FLAG_TPA
)
2164 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2165 if (rx_space
> PAGE_SIZE
) {
2168 bp
->flags
|= BNXT_FLAG_JUMBO
;
2169 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2170 if (jumbo_factor
> agg_factor
)
2171 agg_factor
= jumbo_factor
;
2173 agg_ring_size
= ring_size
* agg_factor
;
2175 if (agg_ring_size
) {
2176 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2178 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2179 u32 tmp
= agg_ring_size
;
2181 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2182 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2183 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2184 tmp
, agg_ring_size
);
2186 bp
->rx_agg_ring_size
= agg_ring_size
;
2187 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2188 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2189 rx_space
= rx_size
+ NET_SKB_PAD
+
2190 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2193 bp
->rx_buf_use_size
= rx_size
;
2194 bp
->rx_buf_size
= rx_space
;
2196 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2197 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2199 ring_size
= bp
->tx_ring_size
;
2200 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2201 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2203 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2204 bp
->cp_ring_size
= ring_size
;
2206 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2207 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2208 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2209 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2210 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2211 ring_size
, bp
->cp_ring_size
);
2213 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2214 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2217 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2220 struct bnxt_vnic_info
*vnic
;
2221 struct pci_dev
*pdev
= bp
->pdev
;
2226 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2227 vnic
= &bp
->vnic_info
[i
];
2229 kfree(vnic
->fw_grp_ids
);
2230 vnic
->fw_grp_ids
= NULL
;
2232 kfree(vnic
->uc_list
);
2233 vnic
->uc_list
= NULL
;
2235 if (vnic
->mc_list
) {
2236 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2237 vnic
->mc_list
, vnic
->mc_list_mapping
);
2238 vnic
->mc_list
= NULL
;
2241 if (vnic
->rss_table
) {
2242 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2244 vnic
->rss_table_dma_addr
);
2245 vnic
->rss_table
= NULL
;
2248 vnic
->rss_hash_key
= NULL
;
2253 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2255 int i
, rc
= 0, size
;
2256 struct bnxt_vnic_info
*vnic
;
2257 struct pci_dev
*pdev
= bp
->pdev
;
2260 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2261 vnic
= &bp
->vnic_info
[i
];
2263 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2264 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2267 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2268 if (!vnic
->uc_list
) {
2275 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2276 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2278 dma_alloc_coherent(&pdev
->dev
,
2280 &vnic
->mc_list_mapping
,
2282 if (!vnic
->mc_list
) {
2288 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2289 max_rings
= bp
->rx_nr_rings
;
2293 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2294 if (!vnic
->fw_grp_ids
) {
2299 /* Allocate rss table and hash key */
2300 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2301 &vnic
->rss_table_dma_addr
,
2303 if (!vnic
->rss_table
) {
2308 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2310 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2311 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2319 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2321 struct pci_dev
*pdev
= bp
->pdev
;
2323 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2324 bp
->hwrm_cmd_resp_dma_addr
);
2326 bp
->hwrm_cmd_resp_addr
= NULL
;
2327 if (bp
->hwrm_dbg_resp_addr
) {
2328 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2329 bp
->hwrm_dbg_resp_addr
,
2330 bp
->hwrm_dbg_resp_dma_addr
);
2332 bp
->hwrm_dbg_resp_addr
= NULL
;
2336 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2338 struct pci_dev
*pdev
= bp
->pdev
;
2340 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2341 &bp
->hwrm_cmd_resp_dma_addr
,
2343 if (!bp
->hwrm_cmd_resp_addr
)
2345 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2346 HWRM_DBG_REG_BUF_SIZE
,
2347 &bp
->hwrm_dbg_resp_dma_addr
,
2349 if (!bp
->hwrm_dbg_resp_addr
)
2350 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2355 static void bnxt_free_stats(struct bnxt
*bp
)
2358 struct pci_dev
*pdev
= bp
->pdev
;
2363 size
= sizeof(struct ctx_hw_stats
);
2365 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2366 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2367 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2369 if (cpr
->hw_stats
) {
2370 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2372 cpr
->hw_stats
= NULL
;
2377 static int bnxt_alloc_stats(struct bnxt
*bp
)
2380 struct pci_dev
*pdev
= bp
->pdev
;
2382 size
= sizeof(struct ctx_hw_stats
);
2384 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2385 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2386 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2388 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2394 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2399 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2406 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2407 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2408 struct bnxt_cp_ring_info
*cpr
;
2409 struct bnxt_rx_ring_info
*rxr
;
2410 struct bnxt_tx_ring_info
*txr
;
2415 cpr
= &bnapi
->cp_ring
;
2416 cpr
->cp_raw_cons
= 0;
2418 txr
= bnapi
->tx_ring
;
2424 rxr
= bnapi
->rx_ring
;
2427 rxr
->rx_agg_prod
= 0;
2428 rxr
->rx_sw_agg_prod
= 0;
2433 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2435 #ifdef CONFIG_RFS_ACCEL
2438 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2439 * safe to delete the hash table.
2441 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2442 struct hlist_head
*head
;
2443 struct hlist_node
*tmp
;
2444 struct bnxt_ntuple_filter
*fltr
;
2446 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2447 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2448 hlist_del(&fltr
->hash
);
2453 kfree(bp
->ntp_fltr_bmap
);
2454 bp
->ntp_fltr_bmap
= NULL
;
2456 bp
->ntp_fltr_count
= 0;
2460 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2462 #ifdef CONFIG_RFS_ACCEL
2465 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2468 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2469 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2471 bp
->ntp_fltr_count
= 0;
2472 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2475 if (!bp
->ntp_fltr_bmap
)
2484 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2486 bnxt_free_vnic_attributes(bp
);
2487 bnxt_free_tx_rings(bp
);
2488 bnxt_free_rx_rings(bp
);
2489 bnxt_free_cp_rings(bp
);
2490 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2492 bnxt_free_stats(bp
);
2493 bnxt_free_ring_grps(bp
);
2494 bnxt_free_vnics(bp
);
2502 bnxt_clear_ring_indices(bp
);
2506 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2508 int i
, j
, rc
, size
, arr_size
;
2512 /* Allocate bnapi mem pointer array and mem block for
2515 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2517 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2518 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2524 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2525 bp
->bnapi
[i
] = bnapi
;
2526 bp
->bnapi
[i
]->index
= i
;
2527 bp
->bnapi
[i
]->bp
= bp
;
2530 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
2531 sizeof(struct bnxt_rx_ring_info
),
2536 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2537 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
2538 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
2541 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
2542 sizeof(struct bnxt_tx_ring_info
),
2547 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
2550 j
= bp
->rx_nr_rings
;
2552 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
2553 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
2554 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
2557 rc
= bnxt_alloc_stats(bp
);
2561 rc
= bnxt_alloc_ntp_fltrs(bp
);
2565 rc
= bnxt_alloc_vnics(bp
);
2570 bnxt_init_ring_struct(bp
);
2572 rc
= bnxt_alloc_rx_rings(bp
);
2576 rc
= bnxt_alloc_tx_rings(bp
);
2580 rc
= bnxt_alloc_cp_rings(bp
);
2584 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2585 BNXT_VNIC_UCAST_FLAG
;
2586 rc
= bnxt_alloc_vnic_attributes(bp
);
2592 bnxt_free_mem(bp
, true);
2596 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
2597 u16 cmpl_ring
, u16 target_id
)
2599 struct hwrm_cmd_req_hdr
*req
= request
;
2601 req
->cmpl_ring_req_type
=
2602 cpu_to_le32(req_type
| (cmpl_ring
<< HWRM_CMPL_RING_SFT
));
2603 req
->target_id_seq_id
= cpu_to_le32(target_id
<< HWRM_TARGET_FID_SFT
);
2604 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
2607 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2609 int i
, intr_process
, rc
;
2610 struct hwrm_cmd_req_hdr
*req
= msg
;
2612 __le32
*resp_len
, *valid
;
2613 u16 cp_ring_id
, len
= 0;
2614 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2616 req
->target_id_seq_id
|= cpu_to_le32(bp
->hwrm_cmd_seq
++);
2617 memset(resp
, 0, PAGE_SIZE
);
2618 cp_ring_id
= (le32_to_cpu(req
->cmpl_ring_req_type
) &
2619 HWRM_CMPL_RING_MASK
) >>
2621 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
2623 /* Write request msg to hwrm channel */
2624 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
2626 for (i
= msg_len
; i
< HWRM_MAX_REQ_LEN
; i
+= 4)
2627 writel(0, bp
->bar0
+ i
);
2629 /* currently supports only one outstanding message */
2631 bp
->hwrm_intr_seq_id
= le32_to_cpu(req
->target_id_seq_id
) &
2634 /* Ring channel doorbell */
2635 writel(1, bp
->bar0
+ 0x100);
2639 /* Wait until hwrm response cmpl interrupt is processed */
2640 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
2642 usleep_range(600, 800);
2645 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
2646 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
2647 req
->cmpl_ring_req_type
);
2651 /* Check if response len is updated */
2652 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
2653 for (i
= 0; i
< timeout
; i
++) {
2654 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
2658 usleep_range(600, 800);
2662 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2663 timeout
, req
->cmpl_ring_req_type
,
2664 req
->target_id_seq_id
, *resp_len
);
2668 /* Last word of resp contains valid bit */
2669 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
2670 for (i
= 0; i
< timeout
; i
++) {
2671 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
2673 usleep_range(600, 800);
2677 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2678 timeout
, req
->cmpl_ring_req_type
,
2679 req
->target_id_seq_id
, len
, *valid
);
2684 rc
= le16_to_cpu(resp
->error_code
);
2686 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2687 le16_to_cpu(resp
->req_type
),
2688 le16_to_cpu(resp
->seq_id
), rc
);
2694 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2698 mutex_lock(&bp
->hwrm_cmd_lock
);
2699 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
2700 mutex_unlock(&bp
->hwrm_cmd_lock
);
2704 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
2706 struct hwrm_func_drv_rgtr_input req
= {0};
2709 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
2712 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
2713 FUNC_DRV_RGTR_REQ_ENABLES_VER
|
2714 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
2716 /* TODO: current async event fwd bits are not defined and the firmware
2717 * only checks if it is non-zero to enable async event forwarding
2719 req
.async_event_fwd
[0] |= cpu_to_le32(1);
2720 req
.os_type
= cpu_to_le16(1);
2721 req
.ver_maj
= DRV_VER_MAJ
;
2722 req
.ver_min
= DRV_VER_MIN
;
2723 req
.ver_upd
= DRV_VER_UPD
;
2726 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
2727 u32
*data
= (u32
*)vf_req_snif_bmap
;
2729 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
2730 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
2731 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
2733 for (i
= 0; i
< 8; i
++)
2734 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
2737 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
2740 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2743 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
2745 struct hwrm_func_drv_unrgtr_input req
= {0};
2747 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
2748 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2751 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
2754 struct hwrm_tunnel_dst_port_free_input req
= {0};
2756 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
2757 req
.tunnel_type
= tunnel_type
;
2759 switch (tunnel_type
) {
2760 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
2761 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
2763 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
2764 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
2770 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2772 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2777 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
2781 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
2782 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2784 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
2786 req
.tunnel_type
= tunnel_type
;
2787 req
.tunnel_dst_port_val
= port
;
2789 mutex_lock(&bp
->hwrm_cmd_lock
);
2790 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2792 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2797 if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
)
2798 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2800 else if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
)
2801 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2803 mutex_unlock(&bp
->hwrm_cmd_lock
);
2807 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
2809 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
2810 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2812 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
2813 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
2815 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
2816 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
2817 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
2818 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2821 #ifdef CONFIG_RFS_ACCEL
2822 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
2823 struct bnxt_ntuple_filter
*fltr
)
2825 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
2827 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
2828 req
.ntuple_filter_id
= fltr
->filter_id
;
2829 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2832 #define BNXT_NTP_FLTR_FLAGS \
2833 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2834 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2835 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2836 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2837 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2838 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2839 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2840 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2841 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2842 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2843 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2844 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2845 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2846 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2848 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
2849 struct bnxt_ntuple_filter
*fltr
)
2852 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
2853 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
2854 bp
->hwrm_cmd_resp_addr
;
2855 struct flow_keys
*keys
= &fltr
->fkeys
;
2856 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
2858 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
2859 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[0];
2861 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
2863 req
.ethertype
= htons(ETH_P_IP
);
2864 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
2865 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
2866 req
.ip_protocol
= keys
->basic
.ip_proto
;
2868 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
2869 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2870 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
2871 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2873 req
.src_port
= keys
->ports
.src
;
2874 req
.src_port_mask
= cpu_to_be16(0xffff);
2875 req
.dst_port
= keys
->ports
.dst
;
2876 req
.dst_port_mask
= cpu_to_be16(0xffff);
2878 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2879 mutex_lock(&bp
->hwrm_cmd_lock
);
2880 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2882 fltr
->filter_id
= resp
->ntuple_filter_id
;
2883 mutex_unlock(&bp
->hwrm_cmd_lock
);
2888 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
2892 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
2893 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2895 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
2896 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
2897 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
2898 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
2900 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
2901 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
2902 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
2903 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
2904 req
.l2_addr_mask
[0] = 0xff;
2905 req
.l2_addr_mask
[1] = 0xff;
2906 req
.l2_addr_mask
[2] = 0xff;
2907 req
.l2_addr_mask
[3] = 0xff;
2908 req
.l2_addr_mask
[4] = 0xff;
2909 req
.l2_addr_mask
[5] = 0xff;
2911 mutex_lock(&bp
->hwrm_cmd_lock
);
2912 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2914 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
2916 mutex_unlock(&bp
->hwrm_cmd_lock
);
2920 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
2922 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
2925 /* Any associated ntuple filters will also be cleared by firmware. */
2926 mutex_lock(&bp
->hwrm_cmd_lock
);
2927 for (i
= 0; i
< num_of_vnics
; i
++) {
2928 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2930 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
2931 struct hwrm_cfa_l2_filter_free_input req
= {0};
2933 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
2934 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
2936 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
2938 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
2941 vnic
->uc_filter_count
= 0;
2943 mutex_unlock(&bp
->hwrm_cmd_lock
);
2948 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
2950 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2951 struct hwrm_vnic_tpa_cfg_input req
= {0};
2953 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
2956 u16 mss
= bp
->dev
->mtu
- 40;
2957 u32 nsegs
, n
, segs
= 0, flags
;
2959 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
2960 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
2961 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
2962 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
2963 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
2964 if (tpa_flags
& BNXT_FLAG_GRO
)
2965 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
2967 req
.flags
= cpu_to_le32(flags
);
2970 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
2971 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
2972 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
2974 /* Number of segs are log2 units, and first packet is not
2975 * included as part of this units.
2977 if (mss
<= PAGE_SIZE
) {
2978 n
= PAGE_SIZE
/ mss
;
2979 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
2981 n
= mss
/ PAGE_SIZE
;
2982 if (mss
& (PAGE_SIZE
- 1))
2984 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
2987 segs
= ilog2(nsegs
);
2988 req
.max_agg_segs
= cpu_to_le16(segs
);
2989 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
2991 req
.min_agg_len
= cpu_to_le32(512);
2993 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2995 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2998 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
3000 u32 i
, j
, max_rings
;
3001 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3002 struct hwrm_vnic_rss_cfg_input req
= {0};
3004 if (vnic
->fw_rss_cos_lb_ctx
== INVALID_HW_RING_ID
)
3007 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3009 vnic
->hash_type
= BNXT_RSS_HASH_TYPE_FLAG_IPV4
|
3010 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4
|
3011 BNXT_RSS_HASH_TYPE_FLAG_IPV6
|
3012 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6
;
3014 req
.hash_type
= cpu_to_le32(vnic
->hash_type
);
3016 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3017 max_rings
= bp
->rx_nr_rings
;
3021 /* Fill the RSS indirection table with ring group ids */
3022 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3025 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3028 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3029 req
.hash_key_tbl_addr
=
3030 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3032 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3033 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3036 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3038 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3039 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3041 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3042 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3043 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3044 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3046 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3047 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3048 /* thresholds not implemented in firmware yet */
3049 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3050 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3051 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3052 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3055 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
)
3057 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3059 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3060 req
.rss_cos_lb_ctx_id
=
3061 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
);
3063 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3064 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3067 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3071 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3072 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3074 if (vnic
->fw_rss_cos_lb_ctx
!= INVALID_HW_RING_ID
)
3075 bnxt_hwrm_vnic_ctx_free_one(bp
, i
);
3077 bp
->rsscos_nr_ctxs
= 0;
3080 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
)
3083 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3084 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3085 bp
->hwrm_cmd_resp_addr
;
3087 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3090 mutex_lock(&bp
->hwrm_cmd_lock
);
3091 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3093 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
=
3094 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3095 mutex_unlock(&bp
->hwrm_cmd_lock
);
3100 static int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3102 unsigned int ring
= 0, grp_idx
;
3103 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3104 struct hwrm_vnic_cfg_input req
= {0};
3106 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3107 /* Only RSS support for now TBD: COS & LB */
3108 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
|
3109 VNIC_CFG_REQ_ENABLES_RSS_RULE
);
3110 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3111 req
.cos_rule
= cpu_to_le16(0xffff);
3112 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3114 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3117 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3118 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3119 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3121 req
.lb_rule
= cpu_to_le16(0xffff);
3122 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3125 if (bp
->flags
& BNXT_FLAG_STRIP_VLAN
)
3126 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3128 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3131 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3135 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3136 struct hwrm_vnic_free_input req
= {0};
3138 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3140 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3142 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3145 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3150 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3154 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3155 bnxt_hwrm_vnic_free_one(bp
, i
);
3158 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3159 unsigned int start_rx_ring_idx
,
3160 unsigned int nr_rings
)
3163 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3164 struct hwrm_vnic_alloc_input req
= {0};
3165 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3167 /* map ring groups to this vnic */
3168 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3169 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3170 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3171 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3175 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3176 bp
->grp_info
[grp_idx
].fw_grp_id
;
3179 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3181 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3183 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3185 mutex_lock(&bp
->hwrm_cmd_lock
);
3186 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3188 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3189 mutex_unlock(&bp
->hwrm_cmd_lock
);
3193 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3198 mutex_lock(&bp
->hwrm_cmd_lock
);
3199 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3200 struct hwrm_ring_grp_alloc_input req
= {0};
3201 struct hwrm_ring_grp_alloc_output
*resp
=
3202 bp
->hwrm_cmd_resp_addr
;
3203 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3205 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3207 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3208 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3209 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3210 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3212 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3217 bp
->grp_info
[grp_idx
].fw_grp_id
=
3218 le32_to_cpu(resp
->ring_group_id
);
3220 mutex_unlock(&bp
->hwrm_cmd_lock
);
3224 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3228 struct hwrm_ring_grp_free_input req
= {0};
3233 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3235 mutex_lock(&bp
->hwrm_cmd_lock
);
3236 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3237 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3240 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3242 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3246 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3248 mutex_unlock(&bp
->hwrm_cmd_lock
);
3252 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3253 struct bnxt_ring_struct
*ring
,
3254 u32 ring_type
, u32 map_index
,
3257 int rc
= 0, err
= 0;
3258 struct hwrm_ring_alloc_input req
= {0};
3259 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3262 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3265 if (ring
->nr_pages
> 1) {
3266 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3267 /* Page size is in log2 units */
3268 req
.page_size
= BNXT_PAGE_SHIFT
;
3269 req
.page_tbl_depth
= 1;
3271 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3274 /* Association of ring index with doorbell index and MSIX number */
3275 req
.logical_id
= cpu_to_le16(map_index
);
3277 switch (ring_type
) {
3278 case HWRM_RING_ALLOC_TX
:
3279 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3280 /* Association of transmit ring with completion ring */
3282 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3283 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3284 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3285 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3287 case HWRM_RING_ALLOC_RX
:
3288 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3289 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3291 case HWRM_RING_ALLOC_AGG
:
3292 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3293 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3295 case HWRM_RING_ALLOC_CMPL
:
3296 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3297 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3298 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3299 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3302 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3307 mutex_lock(&bp
->hwrm_cmd_lock
);
3308 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3309 err
= le16_to_cpu(resp
->error_code
);
3310 ring_id
= le16_to_cpu(resp
->ring_id
);
3311 mutex_unlock(&bp
->hwrm_cmd_lock
);
3314 switch (ring_type
) {
3315 case RING_FREE_REQ_RING_TYPE_CMPL
:
3316 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3320 case RING_FREE_REQ_RING_TYPE_RX
:
3321 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3325 case RING_FREE_REQ_RING_TYPE_TX
:
3326 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3331 netdev_err(bp
->dev
, "Invalid ring\n");
3335 ring
->fw_ring_id
= ring_id
;
3339 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3343 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3344 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3345 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3346 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3348 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
3349 INVALID_STATS_CTX_ID
);
3352 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3353 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3354 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3357 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3358 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3359 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3360 u32 map_idx
= txr
->bnapi
->index
;
3361 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
3363 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
3364 map_idx
, fw_stats_ctx
);
3367 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3370 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3371 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3372 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3373 u32 map_idx
= rxr
->bnapi
->index
;
3375 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
3376 map_idx
, INVALID_STATS_CTX_ID
);
3379 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3380 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3381 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
3384 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3385 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3386 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3387 struct bnxt_ring_struct
*ring
=
3388 &rxr
->rx_agg_ring_struct
;
3389 u32 grp_idx
= rxr
->bnapi
->index
;
3390 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
3392 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3393 HWRM_RING_ALLOC_AGG
,
3395 INVALID_STATS_CTX_ID
);
3399 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3400 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3401 rxr
->rx_agg_doorbell
);
3402 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
3409 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3410 struct bnxt_ring_struct
*ring
,
3411 u32 ring_type
, int cmpl_ring_id
)
3414 struct hwrm_ring_free_input req
= {0};
3415 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3418 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
3419 req
.ring_type
= ring_type
;
3420 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3422 mutex_lock(&bp
->hwrm_cmd_lock
);
3423 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3424 error_code
= le16_to_cpu(resp
->error_code
);
3425 mutex_unlock(&bp
->hwrm_cmd_lock
);
3427 if (rc
|| error_code
) {
3428 switch (ring_type
) {
3429 case RING_FREE_REQ_RING_TYPE_CMPL
:
3430 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3433 case RING_FREE_REQ_RING_TYPE_RX
:
3434 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3437 case RING_FREE_REQ_RING_TYPE_TX
:
3438 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3442 netdev_err(bp
->dev
, "Invalid ring\n");
3449 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
3456 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3457 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3458 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3459 u32 grp_idx
= txr
->bnapi
->index
;
3460 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3462 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3463 hwrm_ring_free_send_msg(bp
, ring
,
3464 RING_FREE_REQ_RING_TYPE_TX
,
3465 close_path
? cmpl_ring_id
:
3466 INVALID_HW_RING_ID
);
3467 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3471 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3472 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3473 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3474 u32 grp_idx
= rxr
->bnapi
->index
;
3475 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3477 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3478 hwrm_ring_free_send_msg(bp
, ring
,
3479 RING_FREE_REQ_RING_TYPE_RX
,
3480 close_path
? cmpl_ring_id
:
3481 INVALID_HW_RING_ID
);
3482 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3483 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
3488 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3489 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3490 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
3491 u32 grp_idx
= rxr
->bnapi
->index
;
3492 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3494 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3495 hwrm_ring_free_send_msg(bp
, ring
,
3496 RING_FREE_REQ_RING_TYPE_RX
,
3497 close_path
? cmpl_ring_id
:
3498 INVALID_HW_RING_ID
);
3499 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3500 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
3505 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3506 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3507 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3508 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3510 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3511 hwrm_ring_free_send_msg(bp
, ring
,
3512 RING_FREE_REQ_RING_TYPE_CMPL
,
3513 INVALID_HW_RING_ID
);
3514 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3515 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
3520 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
3523 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req
= {0};
3524 u16 max_buf
, max_buf_irq
;
3525 u16 buf_tmr
, buf_tmr_irq
;
3528 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
,
3531 /* Each rx completion (2 records) should be DMAed immediately */
3532 max_buf
= min_t(u16
, bp
->coal_bufs
/ 4, 2);
3533 /* max_buf must not be zero */
3534 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
3535 max_buf_irq
= clamp_t(u16
, bp
->coal_bufs_irq
, 1, 63);
3536 buf_tmr
= max_t(u16
, bp
->coal_ticks
/ 4, 1);
3537 buf_tmr_irq
= max_t(u16
, bp
->coal_ticks_irq
, 1);
3539 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3541 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3542 * if coal_ticks is less than 25 us.
3544 if (BNXT_COAL_TIMER_TO_USEC(bp
->coal_ticks
) < 25)
3545 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
3547 req
.flags
= cpu_to_le16(flags
);
3548 req
.num_cmpl_dma_aggr
= cpu_to_le16(max_buf
);
3549 req
.num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_buf_irq
);
3550 req
.cmpl_aggr_dma_tmr
= cpu_to_le16(buf_tmr
);
3551 req
.cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmr_irq
);
3552 req
.int_lat_tmr_min
= cpu_to_le16(buf_tmr
);
3553 req
.int_lat_tmr_max
= cpu_to_le16(bp
->coal_ticks
);
3554 req
.num_cmpl_aggr_int
= cpu_to_le16(bp
->coal_bufs
);
3556 mutex_lock(&bp
->hwrm_cmd_lock
);
3557 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3558 req
.ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3560 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3565 mutex_unlock(&bp
->hwrm_cmd_lock
);
3569 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
3572 struct hwrm_stat_ctx_free_input req
= {0};
3577 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
3579 mutex_lock(&bp
->hwrm_cmd_lock
);
3580 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3581 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3582 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3584 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
3585 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
3587 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3592 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3595 mutex_unlock(&bp
->hwrm_cmd_lock
);
3599 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
3602 struct hwrm_stat_ctx_alloc_input req
= {0};
3603 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3605 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
3607 req
.update_period_ms
= cpu_to_le32(1000);
3609 mutex_lock(&bp
->hwrm_cmd_lock
);
3610 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3611 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3612 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3614 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
3616 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3621 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
3623 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
3625 mutex_unlock(&bp
->hwrm_cmd_lock
);
3629 int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
3632 struct hwrm_func_qcaps_input req
= {0};
3633 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3635 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
3636 req
.fid
= cpu_to_le16(0xffff);
3638 mutex_lock(&bp
->hwrm_cmd_lock
);
3639 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3641 goto hwrm_func_qcaps_exit
;
3644 struct bnxt_pf_info
*pf
= &bp
->pf
;
3646 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
3647 pf
->port_id
= le16_to_cpu(resp
->port_id
);
3648 memcpy(pf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3649 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
3650 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3651 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3652 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3653 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3654 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3655 if (!pf
->max_hw_ring_grps
)
3656 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
3657 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3658 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3659 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3660 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
3661 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
3662 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
3663 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
3664 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
3665 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
3666 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
3667 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
3669 #ifdef CONFIG_BNXT_SRIOV
3670 struct bnxt_vf_info
*vf
= &bp
->vf
;
3672 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
3673 memcpy(vf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3674 if (is_valid_ether_addr(vf
->mac_addr
))
3675 /* overwrite netdev dev_adr with admin VF MAC */
3676 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
3678 random_ether_addr(bp
->dev
->dev_addr
);
3680 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3681 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3682 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3683 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3684 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3685 if (!vf
->max_hw_ring_grps
)
3686 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
3687 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3688 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3689 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3693 bp
->tx_push_thresh
= 0;
3695 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
3696 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
3698 hwrm_func_qcaps_exit
:
3699 mutex_unlock(&bp
->hwrm_cmd_lock
);
3703 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
3705 struct hwrm_func_reset_input req
= {0};
3707 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
3710 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
3713 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
3716 struct hwrm_queue_qportcfg_input req
= {0};
3717 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3720 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
3722 mutex_lock(&bp
->hwrm_cmd_lock
);
3723 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3727 if (!resp
->max_configurable_queues
) {
3731 bp
->max_tc
= resp
->max_configurable_queues
;
3732 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
3733 bp
->max_tc
= BNXT_MAX_QUEUE
;
3735 qptr
= &resp
->queue_id0
;
3736 for (i
= 0; i
< bp
->max_tc
; i
++) {
3737 bp
->q_info
[i
].queue_id
= *qptr
++;
3738 bp
->q_info
[i
].queue_profile
= *qptr
++;
3742 mutex_unlock(&bp
->hwrm_cmd_lock
);
3746 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
3749 struct hwrm_ver_get_input req
= {0};
3750 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3752 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
3753 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
3754 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
3755 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
3756 mutex_lock(&bp
->hwrm_cmd_lock
);
3757 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3759 goto hwrm_ver_get_exit
;
3761 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
3763 if (resp
->hwrm_intf_maj
< 1) {
3764 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3765 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
3766 resp
->hwrm_intf_upd
);
3767 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3769 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "bc %d.%d.%d rm %d.%d.%d",
3770 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
3771 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
3774 mutex_unlock(&bp
->hwrm_cmd_lock
);
3778 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
3780 if (bp
->vxlan_port_cnt
) {
3781 bnxt_hwrm_tunnel_dst_port_free(
3782 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
3784 bp
->vxlan_port_cnt
= 0;
3785 if (bp
->nge_port_cnt
) {
3786 bnxt_hwrm_tunnel_dst_port_free(
3787 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
3789 bp
->nge_port_cnt
= 0;
3792 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
3798 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
3799 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3800 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
3802 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3810 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
3814 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3815 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
3818 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
3821 if (bp
->vnic_info
) {
3822 bnxt_hwrm_clear_vnic_filter(bp
);
3823 /* clear all RSS setting before free vnic ctx */
3824 bnxt_hwrm_clear_vnic_rss(bp
);
3825 bnxt_hwrm_vnic_ctx_free(bp
);
3826 /* before free the vnic, undo the vnic tpa settings */
3827 if (bp
->flags
& BNXT_FLAG_TPA
)
3828 bnxt_set_tpa(bp
, false);
3829 bnxt_hwrm_vnic_free(bp
);
3831 bnxt_hwrm_ring_free(bp
, close_path
);
3832 bnxt_hwrm_ring_grp_free(bp
);
3834 bnxt_hwrm_stat_ctx_free(bp
);
3835 bnxt_hwrm_free_tunnel_ports(bp
);
3839 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
3843 /* allocate context for vnic */
3844 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
);
3846 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3848 goto vnic_setup_err
;
3850 bp
->rsscos_nr_ctxs
++;
3852 /* configure default vnic, ring grp */
3853 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
3855 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
3857 goto vnic_setup_err
;
3860 /* Enable RSS hashing on vnic */
3861 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
3863 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
3865 goto vnic_setup_err
;
3868 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3869 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
3871 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
3880 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
3882 #ifdef CONFIG_RFS_ACCEL
3885 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3886 u16 vnic_id
= i
+ 1;
3889 if (vnic_id
>= bp
->nr_vnics
)
3892 bp
->vnic_info
[vnic_id
].flags
|= BNXT_VNIC_RFS_FLAG
;
3893 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
3895 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3899 rc
= bnxt_setup_vnic(bp
, vnic_id
);
3909 static int bnxt_cfg_rx_mode(struct bnxt
*);
3911 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
3916 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
3918 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
3924 rc
= bnxt_hwrm_ring_alloc(bp
);
3926 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
3930 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
3932 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
3936 /* default vnic 0 */
3937 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, bp
->rx_nr_rings
);
3939 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
3943 rc
= bnxt_setup_vnic(bp
, 0);
3947 if (bp
->flags
& BNXT_FLAG_RFS
) {
3948 rc
= bnxt_alloc_rfs_vnics(bp
);
3953 if (bp
->flags
& BNXT_FLAG_TPA
) {
3954 rc
= bnxt_set_tpa(bp
, true);
3960 bnxt_update_vf_mac(bp
);
3962 /* Filter for default vnic 0 */
3963 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
3965 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
3968 bp
->vnic_info
[0].uc_filter_count
= 1;
3970 bp
->vnic_info
[0].rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
3972 if ((bp
->dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
3973 bp
->vnic_info
[0].rx_mask
|=
3974 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
3976 rc
= bnxt_cfg_rx_mode(bp
);
3980 rc
= bnxt_hwrm_set_coal(bp
);
3982 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
3988 bnxt_hwrm_resource_free(bp
, 0, true);
3993 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
3995 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
3999 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
4001 bnxt_init_rx_rings(bp
);
4002 bnxt_init_tx_rings(bp
);
4003 bnxt_init_ring_grps(bp
, irq_re_init
);
4004 bnxt_init_vnics(bp
);
4006 return bnxt_init_chip(bp
, irq_re_init
);
4009 static void bnxt_disable_int(struct bnxt
*bp
)
4016 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4017 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4018 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4020 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4024 static void bnxt_enable_int(struct bnxt
*bp
)
4028 atomic_set(&bp
->intr_sem
, 0);
4029 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4030 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4031 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4033 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4037 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4040 struct net_device
*dev
= bp
->dev
;
4042 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4046 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4050 #ifdef CONFIG_RFS_ACCEL
4051 if (bp
->flags
& BNXT_FLAG_RFS
)
4052 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4058 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4061 int _rx
= *rx
, _tx
= *tx
;
4064 *rx
= min_t(int, _rx
, max
);
4065 *tx
= min_t(int, _tx
, max
);
4070 while (_rx
+ _tx
> max
) {
4071 if (_rx
> _tx
&& _rx
> 1)
4082 static int bnxt_setup_msix(struct bnxt
*bp
)
4084 struct msix_entry
*msix_ent
;
4085 struct net_device
*dev
= bp
->dev
;
4086 int i
, total_vecs
, rc
= 0, min
= 1;
4087 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4089 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
4090 total_vecs
= bp
->cp_nr_rings
;
4092 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
4096 for (i
= 0; i
< total_vecs
; i
++) {
4097 msix_ent
[i
].entry
= i
;
4098 msix_ent
[i
].vector
= 0;
4101 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
4104 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
4105 if (total_vecs
< 0) {
4107 goto msix_setup_exit
;
4110 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4114 /* Trim rings based upon num of vectors allocated */
4115 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
4116 total_vecs
, min
== 1);
4118 goto msix_setup_exit
;
4120 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4121 tcs
= netdev_get_num_tc(dev
);
4123 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4124 if (bp
->tx_nr_rings_per_tc
== 0) {
4125 netdev_reset_tc(dev
);
4126 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4130 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4131 for (i
= 0; i
< tcs
; i
++) {
4132 count
= bp
->tx_nr_rings_per_tc
;
4134 netdev_set_tc_queue(dev
, i
, count
, off
);
4138 bp
->cp_nr_rings
= total_vecs
;
4140 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4143 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
4144 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4146 else if (i
< bp
->rx_nr_rings
)
4151 snprintf(bp
->irq_tbl
[i
].name
, len
,
4152 "%s-%s-%d", dev
->name
, attr
, i
);
4153 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4155 rc
= bnxt_set_real_num_queues(bp
);
4157 goto msix_setup_exit
;
4160 goto msix_setup_exit
;
4162 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
4167 netdev_err(bp
->dev
, "bnxt_setup_msix err: %x\n", rc
);
4168 pci_disable_msix(bp
->pdev
);
4173 static int bnxt_setup_inta(struct bnxt
*bp
)
4176 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4178 if (netdev_get_num_tc(bp
->dev
))
4179 netdev_reset_tc(bp
->dev
);
4181 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4186 bp
->rx_nr_rings
= 1;
4187 bp
->tx_nr_rings
= 1;
4188 bp
->cp_nr_rings
= 1;
4189 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4190 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
4191 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
4192 snprintf(bp
->irq_tbl
[0].name
, len
,
4193 "%s-%s-%d", bp
->dev
->name
, "TxRx", 0);
4194 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4195 rc
= bnxt_set_real_num_queues(bp
);
4199 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4203 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
4204 rc
= bnxt_setup_msix(bp
);
4206 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4207 /* fallback to INTA */
4208 rc
= bnxt_setup_inta(bp
);
4213 static void bnxt_free_irq(struct bnxt
*bp
)
4215 struct bnxt_irq
*irq
;
4218 #ifdef CONFIG_RFS_ACCEL
4219 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
4220 bp
->dev
->rx_cpu_rmap
= NULL
;
4225 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4226 irq
= &bp
->irq_tbl
[i
];
4228 free_irq(irq
->vector
, bp
->bnapi
[i
]);
4231 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4232 pci_disable_msix(bp
->pdev
);
4237 static int bnxt_request_irq(struct bnxt
*bp
)
4240 unsigned long flags
= 0;
4241 #ifdef CONFIG_RFS_ACCEL
4242 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
4245 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
4246 flags
= IRQF_SHARED
;
4248 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
4249 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
4250 #ifdef CONFIG_RFS_ACCEL
4251 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
4252 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
4254 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
4259 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
4269 static void bnxt_del_napi(struct bnxt
*bp
)
4276 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4277 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4279 napi_hash_del(&bnapi
->napi
);
4280 netif_napi_del(&bnapi
->napi
);
4284 static void bnxt_init_napi(struct bnxt
*bp
)
4287 struct bnxt_napi
*bnapi
;
4289 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4290 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4291 bnapi
= bp
->bnapi
[i
];
4292 netif_napi_add(bp
->dev
, &bnapi
->napi
,
4296 bnapi
= bp
->bnapi
[0];
4297 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
4301 static void bnxt_disable_napi(struct bnxt
*bp
)
4308 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4309 napi_disable(&bp
->bnapi
[i
]->napi
);
4310 bnxt_disable_poll(bp
->bnapi
[i
]);
4314 static void bnxt_enable_napi(struct bnxt
*bp
)
4318 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4319 bnxt_enable_poll(bp
->bnapi
[i
]);
4320 napi_enable(&bp
->bnapi
[i
]->napi
);
4324 static void bnxt_tx_disable(struct bnxt
*bp
)
4327 struct bnxt_tx_ring_info
*txr
;
4328 struct netdev_queue
*txq
;
4331 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4332 txr
= &bp
->tx_ring
[i
];
4333 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4334 __netif_tx_lock(txq
, smp_processor_id());
4335 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
4336 __netif_tx_unlock(txq
);
4339 /* Stop all TX queues */
4340 netif_tx_disable(bp
->dev
);
4341 netif_carrier_off(bp
->dev
);
4344 static void bnxt_tx_enable(struct bnxt
*bp
)
4347 struct bnxt_tx_ring_info
*txr
;
4348 struct netdev_queue
*txq
;
4350 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4351 txr
= &bp
->tx_ring
[i
];
4352 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4355 netif_tx_wake_all_queues(bp
->dev
);
4356 if (bp
->link_info
.link_up
)
4357 netif_carrier_on(bp
->dev
);
4360 static void bnxt_report_link(struct bnxt
*bp
)
4362 if (bp
->link_info
.link_up
) {
4364 const char *flow_ctrl
;
4367 netif_carrier_on(bp
->dev
);
4368 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
4372 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
4373 flow_ctrl
= "ON - receive & transmit";
4374 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
4375 flow_ctrl
= "ON - transmit";
4376 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
4377 flow_ctrl
= "ON - receive";
4380 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
4381 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4382 speed
, duplex
, flow_ctrl
);
4384 netif_carrier_off(bp
->dev
);
4385 netdev_err(bp
->dev
, "NIC Link is Down\n");
4389 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
4392 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4393 struct hwrm_port_phy_qcfg_input req
= {0};
4394 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4395 u8 link_up
= link_info
->link_up
;
4397 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
4399 mutex_lock(&bp
->hwrm_cmd_lock
);
4400 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4402 mutex_unlock(&bp
->hwrm_cmd_lock
);
4406 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
4407 link_info
->phy_link_status
= resp
->link
;
4408 link_info
->duplex
= resp
->duplex
;
4409 link_info
->pause
= resp
->pause
;
4410 link_info
->auto_mode
= resp
->auto_mode
;
4411 link_info
->auto_pause_setting
= resp
->auto_pause
;
4412 link_info
->force_pause_setting
= resp
->force_pause
;
4413 link_info
->duplex_setting
= resp
->duplex
;
4414 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4415 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
4417 link_info
->link_speed
= 0;
4418 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
4419 link_info
->auto_link_speed
= le16_to_cpu(resp
->auto_link_speed
);
4420 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
4421 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
4422 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
4423 link_info
->phy_ver
[0] = resp
->phy_maj
;
4424 link_info
->phy_ver
[1] = resp
->phy_min
;
4425 link_info
->phy_ver
[2] = resp
->phy_bld
;
4426 link_info
->media_type
= resp
->media_type
;
4427 link_info
->transceiver
= resp
->transceiver_type
;
4428 link_info
->phy_addr
= resp
->phy_addr
;
4430 /* TODO: need to add more logic to report VF link */
4431 if (chng_link_state
) {
4432 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4433 link_info
->link_up
= 1;
4435 link_info
->link_up
= 0;
4436 if (link_up
!= link_info
->link_up
)
4437 bnxt_report_link(bp
);
4439 /* alwasy link down if not require to update link state */
4440 link_info
->link_up
= 0;
4442 mutex_unlock(&bp
->hwrm_cmd_lock
);
4447 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
4449 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
4450 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4451 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4452 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4453 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4455 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4457 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4458 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
4459 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4460 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
4462 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
4466 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
4467 struct hwrm_port_phy_cfg_input
*req
)
4469 u8 autoneg
= bp
->link_info
.autoneg
;
4470 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
4471 u32 advertising
= bp
->link_info
.advertising
;
4473 if (autoneg
& BNXT_AUTONEG_SPEED
) {
4475 PORT_PHY_CFG_REQ_AUTO_MODE_MASK
;
4477 req
->enables
|= cpu_to_le32(
4478 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
4479 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
4481 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
4483 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
4485 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
4486 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
4489 /* currently don't support half duplex */
4490 req
->auto_duplex
= PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL
;
4491 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
);
4492 /* tell chimp that the setting takes effect immediately */
4493 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
4496 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
4498 struct hwrm_port_phy_cfg_input req
= {0};
4501 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4502 bnxt_hwrm_set_pause_common(bp
, &req
);
4504 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
4505 bp
->link_info
.force_link_chng
)
4506 bnxt_hwrm_set_link_common(bp
, &req
);
4508 mutex_lock(&bp
->hwrm_cmd_lock
);
4509 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4510 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
4511 /* since changing of pause setting doesn't trigger any link
4512 * change event, the driver needs to update the current pause
4513 * result upon successfully return of the phy_cfg command
4515 bp
->link_info
.pause
=
4516 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
4517 bp
->link_info
.auto_pause_setting
= 0;
4518 if (!bp
->link_info
.force_link_chng
)
4519 bnxt_report_link(bp
);
4521 bp
->link_info
.force_link_chng
= false;
4522 mutex_unlock(&bp
->hwrm_cmd_lock
);
4526 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
)
4528 struct hwrm_port_phy_cfg_input req
= {0};
4530 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4532 bnxt_hwrm_set_pause_common(bp
, &req
);
4534 bnxt_hwrm_set_link_common(bp
, &req
);
4535 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4538 static int bnxt_update_phy_setting(struct bnxt
*bp
)
4541 bool update_link
= false;
4542 bool update_pause
= false;
4543 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4545 rc
= bnxt_update_link(bp
, true);
4547 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
4551 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4552 link_info
->auto_pause_setting
!= link_info
->req_flow_ctrl
)
4553 update_pause
= true;
4554 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4555 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
4556 update_pause
= true;
4557 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4558 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
4560 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
4562 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
4565 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
4567 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
4572 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
);
4573 else if (update_pause
)
4574 rc
= bnxt_hwrm_set_pause(bp
);
4576 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
4584 /* Common routine to pre-map certain register block to different GRC window.
4585 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4586 * in PF and 3 windows in VF that can be customized to map in different
4589 static void bnxt_preset_reg_win(struct bnxt
*bp
)
4592 /* CAG registers map to GRC window #4 */
4593 writel(BNXT_CAG_REG_BASE
,
4594 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
4598 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4602 bnxt_preset_reg_win(bp
);
4603 netif_carrier_off(bp
->dev
);
4605 rc
= bnxt_setup_int_mode(bp
);
4607 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
4612 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
4613 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4614 /* disable RFS if falling back to INTA */
4615 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
4616 bp
->flags
&= ~BNXT_FLAG_RFS
;
4619 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
4621 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
4622 goto open_err_free_mem
;
4627 rc
= bnxt_request_irq(bp
);
4629 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
4634 bnxt_enable_napi(bp
);
4636 rc
= bnxt_init_nic(bp
, irq_re_init
);
4638 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
4643 rc
= bnxt_update_phy_setting(bp
);
4645 netdev_warn(bp
->dev
, "failed to update phy settings\n");
4649 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4650 vxlan_get_rx_port(bp
->dev
);
4652 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4654 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
))
4655 bp
->nge_port_cnt
= 1;
4658 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
4659 bnxt_enable_int(bp
);
4660 /* Enable TX queues */
4662 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4663 bnxt_update_link(bp
, true);
4668 bnxt_disable_napi(bp
);
4674 bnxt_free_mem(bp
, true);
4678 /* rtnl_lock held */
4679 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4683 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
4685 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
4691 static int bnxt_open(struct net_device
*dev
)
4693 struct bnxt
*bp
= netdev_priv(dev
);
4696 rc
= bnxt_hwrm_func_reset(bp
);
4698 netdev_err(bp
->dev
, "hwrm chip reset failure rc: %x\n",
4703 return __bnxt_open_nic(bp
, true, true);
4706 static void bnxt_disable_int_sync(struct bnxt
*bp
)
4710 atomic_inc(&bp
->intr_sem
);
4711 if (!netif_running(bp
->dev
))
4714 bnxt_disable_int(bp
);
4715 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
4716 synchronize_irq(bp
->irq_tbl
[i
].vector
);
4719 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4723 #ifdef CONFIG_BNXT_SRIOV
4724 if (bp
->sriov_cfg
) {
4725 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
4727 BNXT_SRIOV_CFG_WAIT_TMO
);
4729 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
4732 /* Change device state to avoid TX queue wake up's */
4733 bnxt_tx_disable(bp
);
4735 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
4736 smp_mb__after_atomic();
4737 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
4740 /* Flush rings before disabling interrupts */
4741 bnxt_shutdown_nic(bp
, irq_re_init
);
4743 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4745 bnxt_disable_napi(bp
);
4746 bnxt_disable_int_sync(bp
);
4747 del_timer_sync(&bp
->timer
);
4754 bnxt_free_mem(bp
, irq_re_init
);
4758 static int bnxt_close(struct net_device
*dev
)
4760 struct bnxt
*bp
= netdev_priv(dev
);
4762 bnxt_close_nic(bp
, true, true);
4766 /* rtnl_lock held */
4767 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4773 if (!netif_running(dev
))
4780 if (!netif_running(dev
))
4792 static struct rtnl_link_stats64
*
4793 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
4796 struct bnxt
*bp
= netdev_priv(dev
);
4798 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
4803 /* TODO check if we need to synchronize with bnxt_close path */
4804 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4805 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4806 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4807 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
4809 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
4810 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4811 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
4813 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
4814 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
4815 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
4817 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
4818 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
4819 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
4821 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
4822 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
4823 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
4825 stats
->rx_missed_errors
+=
4826 le64_to_cpu(hw_stats
->rx_discard_pkts
);
4828 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4830 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
4836 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
4838 struct net_device
*dev
= bp
->dev
;
4839 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4840 struct netdev_hw_addr
*ha
;
4843 bool update
= false;
4846 netdev_for_each_mc_addr(ha
, dev
) {
4847 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
4848 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4849 vnic
->mc_list_count
= 0;
4853 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
4854 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
4861 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
4863 if (mc_count
!= vnic
->mc_list_count
) {
4864 vnic
->mc_list_count
= mc_count
;
4870 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
4872 struct net_device
*dev
= bp
->dev
;
4873 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4874 struct netdev_hw_addr
*ha
;
4877 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
4880 netdev_for_each_uc_addr(ha
, dev
) {
4881 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
4889 static void bnxt_set_rx_mode(struct net_device
*dev
)
4891 struct bnxt
*bp
= netdev_priv(dev
);
4892 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4893 u32 mask
= vnic
->rx_mask
;
4894 bool mc_update
= false;
4897 if (!netif_running(dev
))
4900 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
4901 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
4902 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
4904 /* Only allow PF to be in promiscuous mode */
4905 if ((dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
4906 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4908 uc_update
= bnxt_uc_list_updated(bp
);
4910 if (dev
->flags
& IFF_ALLMULTI
) {
4911 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4912 vnic
->mc_list_count
= 0;
4914 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
4917 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
4918 vnic
->rx_mask
= mask
;
4920 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
4921 schedule_work(&bp
->sp_task
);
4925 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
4927 struct net_device
*dev
= bp
->dev
;
4928 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4929 struct netdev_hw_addr
*ha
;
4933 netif_addr_lock_bh(dev
);
4934 uc_update
= bnxt_uc_list_updated(bp
);
4935 netif_addr_unlock_bh(dev
);
4940 mutex_lock(&bp
->hwrm_cmd_lock
);
4941 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
4942 struct hwrm_cfa_l2_filter_free_input req
= {0};
4944 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
4947 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
4949 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4952 mutex_unlock(&bp
->hwrm_cmd_lock
);
4954 vnic
->uc_filter_count
= 1;
4956 netif_addr_lock_bh(dev
);
4957 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
4958 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4960 netdev_for_each_uc_addr(ha
, dev
) {
4961 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
4963 vnic
->uc_filter_count
++;
4966 netif_addr_unlock_bh(dev
);
4968 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
4969 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
4971 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
4973 vnic
->uc_filter_count
= i
;
4979 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
4981 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
4987 static bool bnxt_rfs_capable(struct bnxt
*bp
)
4989 #ifdef CONFIG_RFS_ACCEL
4990 struct bnxt_pf_info
*pf
= &bp
->pf
;
4993 if (BNXT_VF(bp
) || !(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
4996 vnics
= 1 + bp
->rx_nr_rings
;
4997 if (vnics
> pf
->max_rsscos_ctxs
|| vnics
> pf
->max_vnics
)
5006 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
5007 netdev_features_t features
)
5009 struct bnxt
*bp
= netdev_priv(dev
);
5011 if (!bnxt_rfs_capable(bp
))
5012 features
&= ~NETIF_F_NTUPLE
;
5016 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
5018 struct bnxt
*bp
= netdev_priv(dev
);
5019 u32 flags
= bp
->flags
;
5022 bool re_init
= false;
5023 bool update_tpa
= false;
5025 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
5026 if ((features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
5027 flags
|= BNXT_FLAG_GRO
;
5028 if (features
& NETIF_F_LRO
)
5029 flags
|= BNXT_FLAG_LRO
;
5031 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
5032 flags
|= BNXT_FLAG_STRIP_VLAN
;
5034 if (features
& NETIF_F_NTUPLE
)
5035 flags
|= BNXT_FLAG_RFS
;
5037 changes
= flags
^ bp
->flags
;
5038 if (changes
& BNXT_FLAG_TPA
) {
5040 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
5041 (flags
& BNXT_FLAG_TPA
) == 0)
5045 if (changes
& ~BNXT_FLAG_TPA
)
5048 if (flags
!= bp
->flags
) {
5049 u32 old_flags
= bp
->flags
;
5053 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5055 bnxt_set_ring_params(bp
);
5060 bnxt_close_nic(bp
, false, false);
5062 bnxt_set_ring_params(bp
);
5064 return bnxt_open_nic(bp
, false, false);
5067 rc
= bnxt_set_tpa(bp
,
5068 (flags
& BNXT_FLAG_TPA
) ?
5071 bp
->flags
= old_flags
;
5077 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
5079 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
5080 int i
= bnapi
->index
;
5085 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5086 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
5090 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
5092 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
5093 int i
= bnapi
->index
;
5098 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5099 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
5100 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
5101 rxr
->rx_sw_agg_prod
);
5104 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
5106 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5107 int i
= bnapi
->index
;
5109 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5110 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
5113 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
5116 struct bnxt_napi
*bnapi
;
5118 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5119 bnapi
= bp
->bnapi
[i
];
5120 if (netif_msg_drv(bp
)) {
5121 bnxt_dump_tx_sw_state(bnapi
);
5122 bnxt_dump_rx_sw_state(bnapi
);
5123 bnxt_dump_cp_sw_state(bnapi
);
5128 static void bnxt_reset_task(struct bnxt
*bp
)
5130 bnxt_dbg_dump_states(bp
);
5131 if (netif_running(bp
->dev
)) {
5132 bnxt_close_nic(bp
, false, false);
5133 bnxt_open_nic(bp
, false, false);
5137 static void bnxt_tx_timeout(struct net_device
*dev
)
5139 struct bnxt
*bp
= netdev_priv(dev
);
5141 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
5142 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
5143 schedule_work(&bp
->sp_task
);
5146 #ifdef CONFIG_NET_POLL_CONTROLLER
5147 static void bnxt_poll_controller(struct net_device
*dev
)
5149 struct bnxt
*bp
= netdev_priv(dev
);
5152 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5153 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5155 disable_irq(irq
->vector
);
5156 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
5157 enable_irq(irq
->vector
);
5162 static void bnxt_timer(unsigned long data
)
5164 struct bnxt
*bp
= (struct bnxt
*)data
;
5165 struct net_device
*dev
= bp
->dev
;
5167 if (!netif_running(dev
))
5170 if (atomic_read(&bp
->intr_sem
) != 0)
5171 goto bnxt_restart_timer
;
5174 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5177 static void bnxt_cfg_ntp_filters(struct bnxt
*);
5179 static void bnxt_sp_task(struct work_struct
*work
)
5181 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
5184 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5185 smp_mb__after_atomic();
5186 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5187 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5191 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
5192 bnxt_cfg_rx_mode(bp
);
5194 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
5195 bnxt_cfg_ntp_filters(bp
);
5196 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
5197 rc
= bnxt_update_link(bp
, true);
5199 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
5202 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
5203 bnxt_hwrm_exec_fwd_req(bp
);
5204 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5205 bnxt_hwrm_tunnel_dst_port_alloc(
5207 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5209 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5210 bnxt_hwrm_tunnel_dst_port_free(
5211 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5213 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
)) {
5214 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5215 * for BNXT_STATE_IN_SP_TASK to clear.
5217 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5219 bnxt_reset_task(bp
);
5220 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5224 smp_mb__before_atomic();
5225 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5228 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5231 struct bnxt
*bp
= netdev_priv(dev
);
5233 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5235 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5236 rc
= pci_enable_device(pdev
);
5238 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
5242 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5244 "Cannot find PCI device base address, aborting\n");
5246 goto init_err_disable
;
5249 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5251 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
5252 goto init_err_disable
;
5255 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
5256 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
5257 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
5258 goto init_err_disable
;
5261 pci_set_master(pdev
);
5266 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
5268 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
5270 goto init_err_release
;
5273 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
5275 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
5277 goto init_err_release
;
5280 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
5282 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
5284 goto init_err_release
;
5287 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
5289 spin_lock_init(&bp
->ntp_fltr_lock
);
5291 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
5292 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
5294 bp
->coal_ticks
= BNXT_USEC_TO_COAL_TIMER(4);
5296 bp
->coal_ticks_irq
= BNXT_USEC_TO_COAL_TIMER(1);
5297 bp
->coal_bufs_irq
= 2;
5299 init_timer(&bp
->timer
);
5300 bp
->timer
.data
= (unsigned long)bp
;
5301 bp
->timer
.function
= bnxt_timer
;
5302 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
5304 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5310 pci_iounmap(pdev
, bp
->bar2
);
5315 pci_iounmap(pdev
, bp
->bar1
);
5320 pci_iounmap(pdev
, bp
->bar0
);
5324 pci_release_regions(pdev
);
5327 pci_disable_device(pdev
);
5333 /* rtnl_lock held */
5334 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
5336 struct sockaddr
*addr
= p
;
5337 struct bnxt
*bp
= netdev_priv(dev
);
5340 if (!is_valid_ether_addr(addr
->sa_data
))
5341 return -EADDRNOTAVAIL
;
5343 #ifdef CONFIG_BNXT_SRIOV
5344 if (BNXT_VF(bp
) && is_valid_ether_addr(bp
->vf
.mac_addr
))
5345 return -EADDRNOTAVAIL
;
5348 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
5351 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5352 if (netif_running(dev
)) {
5353 bnxt_close_nic(bp
, false, false);
5354 rc
= bnxt_open_nic(bp
, false, false);
5360 /* rtnl_lock held */
5361 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
5363 struct bnxt
*bp
= netdev_priv(dev
);
5365 if (new_mtu
< 60 || new_mtu
> 9000)
5368 if (netif_running(dev
))
5369 bnxt_close_nic(bp
, false, false);
5372 bnxt_set_ring_params(bp
);
5374 if (netif_running(dev
))
5375 return bnxt_open_nic(bp
, false, false);
5380 static int bnxt_setup_tc(struct net_device
*dev
, u8 tc
)
5382 struct bnxt
*bp
= netdev_priv(dev
);
5384 if (tc
> bp
->max_tc
) {
5385 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
5390 if (netdev_get_num_tc(dev
) == tc
)
5394 int max_rx_rings
, max_tx_rings
, rc
;
5397 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5400 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5401 if (rc
|| bp
->tx_nr_rings_per_tc
* tc
> max_tx_rings
)
5405 /* Needs to close the device and do hw resource re-allocations */
5406 if (netif_running(bp
->dev
))
5407 bnxt_close_nic(bp
, true, false);
5410 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
5411 netdev_set_num_tc(dev
, tc
);
5413 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5414 netdev_reset_tc(dev
);
5416 bp
->cp_nr_rings
= max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
);
5417 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5419 if (netif_running(bp
->dev
))
5420 return bnxt_open_nic(bp
, true, false);
5425 #ifdef CONFIG_RFS_ACCEL
5426 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
5427 struct bnxt_ntuple_filter
*f2
)
5429 struct flow_keys
*keys1
= &f1
->fkeys
;
5430 struct flow_keys
*keys2
= &f2
->fkeys
;
5432 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
5433 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
5434 keys1
->ports
.ports
== keys2
->ports
.ports
&&
5435 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
5436 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
5437 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
))
5443 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
5444 u16 rxq_index
, u32 flow_id
)
5446 struct bnxt
*bp
= netdev_priv(dev
);
5447 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
5448 struct flow_keys
*fkeys
;
5449 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
5450 int rc
= 0, idx
, bit_id
;
5451 struct hlist_head
*head
;
5453 if (skb
->encapsulation
)
5454 return -EPROTONOSUPPORT
;
5456 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
5460 fkeys
= &new_fltr
->fkeys
;
5461 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
5462 rc
= -EPROTONOSUPPORT
;
5466 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
)) ||
5467 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
5468 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
5469 rc
= -EPROTONOSUPPORT
;
5473 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
5475 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
5476 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
5478 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
5479 if (bnxt_fltr_match(fltr
, new_fltr
)) {
5487 spin_lock_bh(&bp
->ntp_fltr_lock
);
5488 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
5489 BNXT_NTP_FLTR_MAX_FLTR
, 0);
5491 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5496 new_fltr
->sw_id
= (u16
)bit_id
;
5497 new_fltr
->flow_id
= flow_id
;
5498 new_fltr
->rxq
= rxq_index
;
5499 hlist_add_head_rcu(&new_fltr
->hash
, head
);
5500 bp
->ntp_fltr_count
++;
5501 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5503 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
5504 schedule_work(&bp
->sp_task
);
5506 return new_fltr
->sw_id
;
5513 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5517 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
5518 struct hlist_head
*head
;
5519 struct hlist_node
*tmp
;
5520 struct bnxt_ntuple_filter
*fltr
;
5523 head
= &bp
->ntp_fltr_hash_tbl
[i
];
5524 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
5527 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
5528 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
5531 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
5536 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
5541 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
5545 spin_lock_bh(&bp
->ntp_fltr_lock
);
5546 hlist_del_rcu(&fltr
->hash
);
5547 bp
->ntp_fltr_count
--;
5548 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5550 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
5559 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5563 #endif /* CONFIG_RFS_ACCEL */
5565 static void bnxt_add_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5568 struct bnxt
*bp
= netdev_priv(dev
);
5570 if (!netif_running(dev
))
5573 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5576 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= port
)
5579 bp
->vxlan_port_cnt
++;
5580 if (bp
->vxlan_port_cnt
== 1) {
5581 bp
->vxlan_port
= port
;
5582 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
5583 schedule_work(&bp
->sp_task
);
5587 static void bnxt_del_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5590 struct bnxt
*bp
= netdev_priv(dev
);
5592 if (!netif_running(dev
))
5595 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5598 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
== port
) {
5599 bp
->vxlan_port_cnt
--;
5601 if (bp
->vxlan_port_cnt
== 0) {
5602 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
5603 schedule_work(&bp
->sp_task
);
5608 static const struct net_device_ops bnxt_netdev_ops
= {
5609 .ndo_open
= bnxt_open
,
5610 .ndo_start_xmit
= bnxt_start_xmit
,
5611 .ndo_stop
= bnxt_close
,
5612 .ndo_get_stats64
= bnxt_get_stats64
,
5613 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
5614 .ndo_do_ioctl
= bnxt_ioctl
,
5615 .ndo_validate_addr
= eth_validate_addr
,
5616 .ndo_set_mac_address
= bnxt_change_mac_addr
,
5617 .ndo_change_mtu
= bnxt_change_mtu
,
5618 .ndo_fix_features
= bnxt_fix_features
,
5619 .ndo_set_features
= bnxt_set_features
,
5620 .ndo_tx_timeout
= bnxt_tx_timeout
,
5621 #ifdef CONFIG_BNXT_SRIOV
5622 .ndo_get_vf_config
= bnxt_get_vf_config
,
5623 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
5624 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
5625 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
5626 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
5627 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
5629 #ifdef CONFIG_NET_POLL_CONTROLLER
5630 .ndo_poll_controller
= bnxt_poll_controller
,
5632 .ndo_setup_tc
= bnxt_setup_tc
,
5633 #ifdef CONFIG_RFS_ACCEL
5634 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
5636 .ndo_add_vxlan_port
= bnxt_add_vxlan_port
,
5637 .ndo_del_vxlan_port
= bnxt_del_vxlan_port
,
5638 #ifdef CONFIG_NET_RX_BUSY_POLL
5639 .ndo_busy_poll
= bnxt_busy_poll
,
5643 static void bnxt_remove_one(struct pci_dev
*pdev
)
5645 struct net_device
*dev
= pci_get_drvdata(pdev
);
5646 struct bnxt
*bp
= netdev_priv(dev
);
5649 bnxt_sriov_disable(bp
);
5651 unregister_netdev(dev
);
5652 cancel_work_sync(&bp
->sp_task
);
5655 bnxt_hwrm_func_drv_unrgtr(bp
);
5656 bnxt_free_hwrm_resources(bp
);
5657 pci_iounmap(pdev
, bp
->bar2
);
5658 pci_iounmap(pdev
, bp
->bar1
);
5659 pci_iounmap(pdev
, bp
->bar0
);
5662 pci_release_regions(pdev
);
5663 pci_disable_device(pdev
);
5666 static int bnxt_probe_phy(struct bnxt
*bp
)
5669 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5670 char phy_ver
[PHY_VER_STR_LEN
];
5672 rc
= bnxt_update_link(bp
, false);
5674 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
5679 /*initialize the ethool setting copy with NVM settings */
5680 if (BNXT_AUTO_MODE(link_info
->auto_mode
)) {
5681 link_info
->autoneg
= BNXT_AUTONEG_SPEED
|
5682 BNXT_AUTONEG_FLOW_CTRL
;
5683 link_info
->advertising
= link_info
->auto_link_speeds
;
5684 link_info
->req_flow_ctrl
= link_info
->auto_pause_setting
;
5686 link_info
->req_link_speed
= link_info
->force_link_speed
;
5687 link_info
->req_duplex
= link_info
->duplex_setting
;
5688 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
5690 snprintf(phy_ver
, PHY_VER_STR_LEN
, " ph %d.%d.%d",
5691 link_info
->phy_ver
[0],
5692 link_info
->phy_ver
[1],
5693 link_info
->phy_ver
[2]);
5694 strcat(bp
->fw_ver_str
, phy_ver
);
5698 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
5702 if (!pdev
->msix_cap
)
5705 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
5706 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
5709 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
5712 int max_ring_grps
= 0;
5714 #ifdef CONFIG_BNXT_SRIOV
5716 *max_tx
= bp
->vf
.max_tx_rings
;
5717 *max_rx
= bp
->vf
.max_rx_rings
;
5718 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
5719 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
5720 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
5724 *max_tx
= bp
->pf
.max_tx_rings
;
5725 *max_rx
= bp
->pf
.max_rx_rings
;
5726 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
5727 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
5728 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
5731 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5733 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
5736 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
5740 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
5741 if (!rx
|| !tx
|| !cp
)
5746 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
5749 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
5751 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
5755 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
5756 dflt_rings
= netif_get_num_default_rss_queues();
5757 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5760 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
5761 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
5762 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5763 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
5764 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
5765 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5769 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
5771 static int version_printed
;
5772 struct net_device
*dev
;
5776 if (version_printed
++ == 0)
5777 pr_info("%s", version
);
5779 max_irqs
= bnxt_get_max_irq(pdev
);
5780 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
5784 bp
= netdev_priv(dev
);
5786 if (bnxt_vf_pciid(ent
->driver_data
))
5787 bp
->flags
|= BNXT_FLAG_VF
;
5790 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
5792 rc
= bnxt_init_board(pdev
, dev
);
5796 dev
->netdev_ops
= &bnxt_netdev_ops
;
5797 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
5798 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
5800 pci_set_drvdata(pdev
, dev
);
5802 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5803 NETIF_F_TSO
| NETIF_F_TSO6
|
5804 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5805 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
|
5807 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
;
5809 dev
->hw_enc_features
=
5810 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5811 NETIF_F_TSO
| NETIF_F_TSO6
|
5812 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5813 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
;
5814 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
5815 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
5816 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
5817 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
5818 dev
->priv_flags
|= IFF_UNICAST_FLT
;
5820 #ifdef CONFIG_BNXT_SRIOV
5821 init_waitqueue_head(&bp
->sriov_cfg_wait
);
5823 rc
= bnxt_alloc_hwrm_resources(bp
);
5827 mutex_init(&bp
->hwrm_cmd_lock
);
5828 bnxt_hwrm_ver_get(bp
);
5830 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
5834 /* Get the MAX capabilities for this function */
5835 rc
= bnxt_hwrm_func_qcaps(bp
);
5837 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
5843 rc
= bnxt_hwrm_queue_qportcfg(bp
);
5845 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
5851 bnxt_set_tpa_flags(bp
);
5852 bnxt_set_ring_params(bp
);
5854 bp
->pf
.max_irqs
= max_irqs
;
5855 #if defined(CONFIG_BNXT_SRIOV)
5857 bp
->vf
.max_irqs
= max_irqs
;
5859 bnxt_set_dflt_rings(bp
);
5862 dev
->hw_features
|= NETIF_F_NTUPLE
;
5863 if (bnxt_rfs_capable(bp
)) {
5864 bp
->flags
|= BNXT_FLAG_RFS
;
5865 dev
->features
|= NETIF_F_NTUPLE
;
5869 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
5870 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
5872 rc
= bnxt_probe_phy(bp
);
5876 rc
= register_netdev(dev
);
5880 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
5881 board_info
[ent
->driver_data
].name
,
5882 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
5887 pci_iounmap(pdev
, bp
->bar0
);
5888 pci_release_regions(pdev
);
5889 pci_disable_device(pdev
);
5896 static struct pci_driver bnxt_pci_driver
= {
5897 .name
= DRV_MODULE_NAME
,
5898 .id_table
= bnxt_pci_tbl
,
5899 .probe
= bnxt_init_one
,
5900 .remove
= bnxt_remove_one
,
5901 #if defined(CONFIG_BNXT_SRIOV)
5902 .sriov_configure
= bnxt_sriov_configure
,
5906 module_pci_driver(bnxt_pci_driver
);