2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
22 #include "thunder_bgx.h"
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
36 int lmacid
; /* ID within BGX */
37 int lmacid_bd
; /* ID on board */
38 struct net_device netdev
;
39 struct phy_device
*phydev
;
40 unsigned int last_duplex
;
41 unsigned int last_link
;
42 unsigned int last_speed
;
44 struct delayed_work dwork
;
45 struct workqueue_struct
*check_link
;
50 struct lmac lmac
[MAX_LMAC_PER_BGX
];
54 void __iomem
*reg_base
;
60 static struct bgx
*bgx_vnic
[MAX_BGX_THUNDER
];
61 static int lmac_count
; /* Total no of LMACs in system */
63 static int bgx_xaui_check_link(struct lmac
*lmac
);
65 /* Supported devices */
66 static const struct pci_device_id bgx_id_table
[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_BGX
) },
68 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_RGX
) },
69 { 0, } /* end of table */
72 MODULE_AUTHOR("Cavium Inc");
73 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
74 MODULE_LICENSE("GPL v2");
75 MODULE_VERSION(DRV_VERSION
);
76 MODULE_DEVICE_TABLE(pci
, bgx_id_table
);
78 /* The Cavium ThunderX network controller can *only* be found in SoCs
79 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
80 * registers on this platform are implicitly strongly ordered with respect
81 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
82 * with no memory barriers in this driver. The readq()/writeq() functions add
83 * explicit ordering operation which in this case are redundant, and only
87 /* Register read/write APIs */
88 static u64
bgx_reg_read(struct bgx
*bgx
, u8 lmac
, u64 offset
)
90 void __iomem
*addr
= bgx
->reg_base
+ ((u32
)lmac
<< 20) + offset
;
92 return readq_relaxed(addr
);
95 static void bgx_reg_write(struct bgx
*bgx
, u8 lmac
, u64 offset
, u64 val
)
97 void __iomem
*addr
= bgx
->reg_base
+ ((u32
)lmac
<< 20) + offset
;
99 writeq_relaxed(val
, addr
);
102 static void bgx_reg_modify(struct bgx
*bgx
, u8 lmac
, u64 offset
, u64 val
)
104 void __iomem
*addr
= bgx
->reg_base
+ ((u32
)lmac
<< 20) + offset
;
106 writeq_relaxed(val
| readq_relaxed(addr
), addr
);
109 static int bgx_poll_reg(struct bgx
*bgx
, u8 lmac
, u64 reg
, u64 mask
, bool zero
)
115 reg_val
= bgx_reg_read(bgx
, lmac
, reg
);
116 if (zero
&& !(reg_val
& mask
))
118 if (!zero
&& (reg_val
& mask
))
120 usleep_range(1000, 2000);
126 static int max_bgx_per_node
;
127 static void set_max_bgx_per_node(struct pci_dev
*pdev
)
131 if (max_bgx_per_node
)
134 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &sdevid
);
136 case PCI_SUBSYS_DEVID_81XX_BGX
:
137 case PCI_SUBSYS_DEVID_81XX_RGX
:
138 max_bgx_per_node
= MAX_BGX_PER_CN81XX
;
140 case PCI_SUBSYS_DEVID_83XX_BGX
:
141 max_bgx_per_node
= MAX_BGX_PER_CN83XX
;
143 case PCI_SUBSYS_DEVID_88XX_BGX
:
145 max_bgx_per_node
= MAX_BGX_PER_CN88XX
;
150 static struct bgx
*get_bgx(int node
, int bgx_idx
)
152 int idx
= (node
* max_bgx_per_node
) + bgx_idx
;
154 return bgx_vnic
[idx
];
157 /* Return number of BGX present in HW */
158 unsigned bgx_get_map(int node
)
163 for (i
= 0; i
< max_bgx_per_node
; i
++) {
164 if (bgx_vnic
[(node
* max_bgx_per_node
) + i
])
170 EXPORT_SYMBOL(bgx_get_map
);
172 /* Return number of LMAC configured for this BGX */
173 int bgx_get_lmac_count(int node
, int bgx_idx
)
177 bgx
= get_bgx(node
, bgx_idx
);
179 return bgx
->lmac_count
;
183 EXPORT_SYMBOL(bgx_get_lmac_count
);
185 /* Returns the current link status of LMAC */
186 void bgx_get_lmac_link_state(int node
, int bgx_idx
, int lmacid
, void *status
)
188 struct bgx_link_status
*link
= (struct bgx_link_status
*)status
;
192 bgx
= get_bgx(node
, bgx_idx
);
196 lmac
= &bgx
->lmac
[lmacid
];
197 link
->mac_type
= lmac
->lmac_type
;
198 link
->link_up
= lmac
->link_up
;
199 link
->duplex
= lmac
->last_duplex
;
200 link
->speed
= lmac
->last_speed
;
202 EXPORT_SYMBOL(bgx_get_lmac_link_state
);
204 const u8
*bgx_get_lmac_mac(int node
, int bgx_idx
, int lmacid
)
206 struct bgx
*bgx
= get_bgx(node
, bgx_idx
);
209 return bgx
->lmac
[lmacid
].mac
;
213 EXPORT_SYMBOL(bgx_get_lmac_mac
);
215 void bgx_set_lmac_mac(int node
, int bgx_idx
, int lmacid
, const u8
*mac
)
217 struct bgx
*bgx
= get_bgx(node
, bgx_idx
);
222 ether_addr_copy(bgx
->lmac
[lmacid
].mac
, mac
);
224 EXPORT_SYMBOL(bgx_set_lmac_mac
);
226 void bgx_lmac_rx_tx_enable(int node
, int bgx_idx
, int lmacid
, bool enable
)
228 struct bgx
*bgx
= get_bgx(node
, bgx_idx
);
234 lmac
= &bgx
->lmac
[lmacid
];
236 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_CMRX_CFG
);
238 cfg
|= CMR_PKT_RX_EN
| CMR_PKT_TX_EN
;
240 cfg
&= ~(CMR_PKT_RX_EN
| CMR_PKT_TX_EN
);
241 bgx_reg_write(bgx
, lmacid
, BGX_CMRX_CFG
, cfg
);
244 xcv_setup_link(enable
? lmac
->link_up
: 0, lmac
->last_speed
);
246 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable
);
248 void bgx_lmac_get_pfc(int node
, int bgx_idx
, int lmacid
, void *pause
)
250 struct pfc
*pfc
= (struct pfc
*)pause
;
251 struct bgx
*bgx
= get_bgx(node
, bgx_idx
);
257 lmac
= &bgx
->lmac
[lmacid
];
261 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SMUX_CBFC_CTL
);
262 pfc
->fc_rx
= cfg
& RX_EN
;
263 pfc
->fc_tx
= cfg
& TX_EN
;
266 EXPORT_SYMBOL(bgx_lmac_get_pfc
);
268 void bgx_lmac_set_pfc(int node
, int bgx_idx
, int lmacid
, void *pause
)
270 struct pfc
*pfc
= (struct pfc
*)pause
;
271 struct bgx
*bgx
= get_bgx(node
, bgx_idx
);
277 lmac
= &bgx
->lmac
[lmacid
];
281 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SMUX_CBFC_CTL
);
282 cfg
&= ~(RX_EN
| TX_EN
);
283 cfg
|= (pfc
->fc_rx
? RX_EN
: 0x00);
284 cfg
|= (pfc
->fc_tx
? TX_EN
: 0x00);
285 bgx_reg_write(bgx
, lmacid
, BGX_SMUX_CBFC_CTL
, cfg
);
287 EXPORT_SYMBOL(bgx_lmac_set_pfc
);
289 static void bgx_sgmii_change_link_state(struct lmac
*lmac
)
291 struct bgx
*bgx
= lmac
->bgx
;
296 cmr_cfg
= bgx_reg_read(bgx
, lmac
->lmacid
, BGX_CMRX_CFG
);
298 bgx_reg_write(bgx
, lmac
->lmacid
, BGX_CMRX_CFG
, cmr_cfg
);
300 port_cfg
= bgx_reg_read(bgx
, lmac
->lmacid
, BGX_GMP_GMI_PRTX_CFG
);
301 misc_ctl
= bgx_reg_read(bgx
, lmac
->lmacid
, BGX_GMP_PCS_MISCX_CTL
);
304 misc_ctl
&= ~PCS_MISC_CTL_GMX_ENO
;
305 port_cfg
&= ~GMI_PORT_CFG_DUPLEX
;
306 port_cfg
|= (lmac
->last_duplex
<< 2);
308 misc_ctl
|= PCS_MISC_CTL_GMX_ENO
;
311 switch (lmac
->last_speed
) {
313 port_cfg
&= ~GMI_PORT_CFG_SPEED
; /* speed 0 */
314 port_cfg
|= GMI_PORT_CFG_SPEED_MSB
; /* speed_msb 1 */
315 port_cfg
&= ~GMI_PORT_CFG_SLOT_TIME
; /* slottime 0 */
316 misc_ctl
&= ~PCS_MISC_CTL_SAMP_PT_MASK
;
317 misc_ctl
|= 50; /* samp_pt */
318 bgx_reg_write(bgx
, lmac
->lmacid
, BGX_GMP_GMI_TXX_SLOT
, 64);
319 bgx_reg_write(bgx
, lmac
->lmacid
, BGX_GMP_GMI_TXX_BURST
, 0);
322 port_cfg
&= ~GMI_PORT_CFG_SPEED
; /* speed 0 */
323 port_cfg
&= ~GMI_PORT_CFG_SPEED_MSB
; /* speed_msb 0 */
324 port_cfg
&= ~GMI_PORT_CFG_SLOT_TIME
; /* slottime 0 */
325 misc_ctl
&= ~PCS_MISC_CTL_SAMP_PT_MASK
;
326 misc_ctl
|= 5; /* samp_pt */
327 bgx_reg_write(bgx
, lmac
->lmacid
, BGX_GMP_GMI_TXX_SLOT
, 64);
328 bgx_reg_write(bgx
, lmac
->lmacid
, BGX_GMP_GMI_TXX_BURST
, 0);
331 port_cfg
|= GMI_PORT_CFG_SPEED
; /* speed 1 */
332 port_cfg
&= ~GMI_PORT_CFG_SPEED_MSB
; /* speed_msb 0 */
333 port_cfg
|= GMI_PORT_CFG_SLOT_TIME
; /* slottime 1 */
334 misc_ctl
&= ~PCS_MISC_CTL_SAMP_PT_MASK
;
335 misc_ctl
|= 1; /* samp_pt */
336 bgx_reg_write(bgx
, lmac
->lmacid
, BGX_GMP_GMI_TXX_SLOT
, 512);
337 if (lmac
->last_duplex
)
338 bgx_reg_write(bgx
, lmac
->lmacid
,
339 BGX_GMP_GMI_TXX_BURST
, 0);
341 bgx_reg_write(bgx
, lmac
->lmacid
,
342 BGX_GMP_GMI_TXX_BURST
, 8192);
347 bgx_reg_write(bgx
, lmac
->lmacid
, BGX_GMP_PCS_MISCX_CTL
, misc_ctl
);
348 bgx_reg_write(bgx
, lmac
->lmacid
, BGX_GMP_GMI_PRTX_CFG
, port_cfg
);
350 port_cfg
= bgx_reg_read(bgx
, lmac
->lmacid
, BGX_GMP_GMI_PRTX_CFG
);
354 bgx_reg_write(bgx
, lmac
->lmacid
, BGX_CMRX_CFG
, cmr_cfg
);
356 if (bgx
->is_rgx
&& (cmr_cfg
& (CMR_PKT_RX_EN
| CMR_PKT_TX_EN
)))
357 xcv_setup_link(lmac
->link_up
, lmac
->last_speed
);
360 static void bgx_lmac_handler(struct net_device
*netdev
)
362 struct lmac
*lmac
= container_of(netdev
, struct lmac
, netdev
);
363 struct phy_device
*phydev
;
364 int link_changed
= 0;
369 phydev
= lmac
->phydev
;
371 if (!phydev
->link
&& lmac
->last_link
)
375 (lmac
->last_duplex
!= phydev
->duplex
||
376 lmac
->last_link
!= phydev
->link
||
377 lmac
->last_speed
!= phydev
->speed
)) {
381 lmac
->last_link
= phydev
->link
;
382 lmac
->last_speed
= phydev
->speed
;
383 lmac
->last_duplex
= phydev
->duplex
;
388 if (link_changed
> 0)
389 lmac
->link_up
= true;
391 lmac
->link_up
= false;
394 bgx_sgmii_change_link_state(lmac
);
396 bgx_xaui_check_link(lmac
);
399 u64
bgx_get_rx_stats(int node
, int bgx_idx
, int lmac
, int idx
)
403 bgx
= get_bgx(node
, bgx_idx
);
409 return bgx_reg_read(bgx
, lmac
, BGX_CMRX_RX_STAT0
+ (idx
* 8));
411 EXPORT_SYMBOL(bgx_get_rx_stats
);
413 u64
bgx_get_tx_stats(int node
, int bgx_idx
, int lmac
, int idx
)
417 bgx
= get_bgx(node
, bgx_idx
);
421 return bgx_reg_read(bgx
, lmac
, BGX_CMRX_TX_STAT0
+ (idx
* 8));
423 EXPORT_SYMBOL(bgx_get_tx_stats
);
425 static void bgx_flush_dmac_addrs(struct bgx
*bgx
, int lmac
)
429 while (bgx
->lmac
[lmac
].dmac
> 0) {
430 offset
= ((bgx
->lmac
[lmac
].dmac
- 1) * sizeof(u64
)) +
431 (lmac
* MAX_DMAC_PER_LMAC
* sizeof(u64
));
432 bgx_reg_write(bgx
, 0, BGX_CMR_RX_DMACX_CAM
+ offset
, 0);
433 bgx
->lmac
[lmac
].dmac
--;
437 /* Configure BGX LMAC in internal loopback mode */
438 void bgx_lmac_internal_loopback(int node
, int bgx_idx
,
439 int lmac_idx
, bool enable
)
445 bgx
= get_bgx(node
, bgx_idx
);
449 lmac
= &bgx
->lmac
[lmac_idx
];
450 if (lmac
->is_sgmii
) {
451 cfg
= bgx_reg_read(bgx
, lmac_idx
, BGX_GMP_PCS_MRX_CTL
);
453 cfg
|= PCS_MRX_CTL_LOOPBACK1
;
455 cfg
&= ~PCS_MRX_CTL_LOOPBACK1
;
456 bgx_reg_write(bgx
, lmac_idx
, BGX_GMP_PCS_MRX_CTL
, cfg
);
458 cfg
= bgx_reg_read(bgx
, lmac_idx
, BGX_SPUX_CONTROL1
);
460 cfg
|= SPU_CTL_LOOPBACK
;
462 cfg
&= ~SPU_CTL_LOOPBACK
;
463 bgx_reg_write(bgx
, lmac_idx
, BGX_SPUX_CONTROL1
, cfg
);
466 EXPORT_SYMBOL(bgx_lmac_internal_loopback
);
468 static int bgx_lmac_sgmii_init(struct bgx
*bgx
, struct lmac
*lmac
)
470 int lmacid
= lmac
->lmacid
;
473 bgx_reg_modify(bgx
, lmacid
, BGX_GMP_GMI_TXX_THRESH
, 0x30);
474 /* max packet size */
475 bgx_reg_modify(bgx
, lmacid
, BGX_GMP_GMI_RXX_JABBER
, MAX_FRAME_SIZE
);
477 /* Disable frame alignment if using preamble */
478 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_GMP_GMI_TXX_APPEND
);
480 bgx_reg_write(bgx
, lmacid
, BGX_GMP_GMI_TXX_SGMII_CTL
, 0);
483 bgx_reg_modify(bgx
, lmacid
, BGX_CMRX_CFG
, CMR_EN
);
486 bgx_reg_modify(bgx
, lmacid
, BGX_GMP_PCS_MRX_CTL
, PCS_MRX_CTL_RESET
);
487 if (bgx_poll_reg(bgx
, lmacid
, BGX_GMP_PCS_MRX_CTL
,
488 PCS_MRX_CTL_RESET
, true)) {
489 dev_err(&bgx
->pdev
->dev
, "BGX PCS reset not completed\n");
493 /* power down, reset autoneg, autoneg enable */
494 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_GMP_PCS_MRX_CTL
);
495 cfg
&= ~PCS_MRX_CTL_PWR_DN
;
496 cfg
|= PCS_MRX_CTL_RST_AN
;
498 cfg
|= PCS_MRX_CTL_AN_EN
;
500 /* In scenarios where PHY driver is not present or it's a
501 * non-standard PHY, FW sets AN_EN to inform Linux driver
502 * to do auto-neg and link polling or not.
504 if (cfg
& PCS_MRX_CTL_AN_EN
)
505 lmac
->autoneg
= true;
507 bgx_reg_write(bgx
, lmacid
, BGX_GMP_PCS_MRX_CTL
, cfg
);
509 if (lmac
->lmac_type
== BGX_MODE_QSGMII
) {
510 /* Disable disparity check for QSGMII */
511 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_GMP_PCS_MISCX_CTL
);
512 cfg
&= ~PCS_MISC_CTL_DISP_EN
;
513 bgx_reg_write(bgx
, lmacid
, BGX_GMP_PCS_MISCX_CTL
, cfg
);
517 if ((lmac
->lmac_type
== BGX_MODE_SGMII
) && lmac
->phydev
) {
518 if (bgx_poll_reg(bgx
, lmacid
, BGX_GMP_PCS_MRX_STATUS
,
519 PCS_MRX_STATUS_AN_CPT
, false)) {
520 dev_err(&bgx
->pdev
->dev
, "BGX AN_CPT not completed\n");
528 static int bgx_lmac_xaui_init(struct bgx
*bgx
, struct lmac
*lmac
)
531 int lmacid
= lmac
->lmacid
;
534 bgx_reg_modify(bgx
, lmacid
, BGX_SPUX_CONTROL1
, SPU_CTL_RESET
);
535 if (bgx_poll_reg(bgx
, lmacid
, BGX_SPUX_CONTROL1
, SPU_CTL_RESET
, true)) {
536 dev_err(&bgx
->pdev
->dev
, "BGX SPU reset not completed\n");
541 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_CMRX_CFG
);
543 bgx_reg_write(bgx
, lmacid
, BGX_CMRX_CFG
, cfg
);
545 bgx_reg_modify(bgx
, lmacid
, BGX_SPUX_CONTROL1
, SPU_CTL_LOW_POWER
);
546 /* Set interleaved running disparity for RXAUI */
547 if (lmac
->lmac_type
== BGX_MODE_RXAUI
)
548 bgx_reg_modify(bgx
, lmacid
, BGX_SPUX_MISC_CONTROL
,
549 SPU_MISC_CTL_INTLV_RDISP
);
551 /* Clear receive packet disable */
552 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_MISC_CONTROL
);
553 cfg
&= ~SPU_MISC_CTL_RX_DIS
;
554 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_MISC_CONTROL
, cfg
);
556 /* clear all interrupts */
557 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SMUX_RX_INT
);
558 bgx_reg_write(bgx
, lmacid
, BGX_SMUX_RX_INT
, cfg
);
559 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SMUX_TX_INT
);
560 bgx_reg_write(bgx
, lmacid
, BGX_SMUX_TX_INT
, cfg
);
561 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_INT
);
562 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_INT
, cfg
);
564 if (lmac
->use_training
) {
565 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_BR_PMD_LP_CUP
, 0x00);
566 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_BR_PMD_LD_CUP
, 0x00);
567 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_BR_PMD_LD_REP
, 0x00);
568 /* training enable */
569 bgx_reg_modify(bgx
, lmacid
,
570 BGX_SPUX_BR_PMD_CRTL
, SPU_PMD_CRTL_TRAIN_EN
);
573 /* Append FCS to each packet */
574 bgx_reg_modify(bgx
, lmacid
, BGX_SMUX_TX_APPEND
, SMU_TX_APPEND_FCS_D
);
576 /* Disable forward error correction */
577 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_FEC_CONTROL
);
578 cfg
&= ~SPU_FEC_CTL_FEC_EN
;
579 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_FEC_CONTROL
, cfg
);
581 /* Disable autoneg */
582 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_AN_CONTROL
);
583 cfg
= cfg
& ~(SPU_AN_CTL_AN_EN
| SPU_AN_CTL_XNP_EN
);
584 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_AN_CONTROL
, cfg
);
586 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_AN_ADV
);
587 if (lmac
->lmac_type
== BGX_MODE_10G_KR
)
589 else if (lmac
->lmac_type
== BGX_MODE_40G_KR
)
592 cfg
&= ~((1 << 23) | (1 << 24));
593 cfg
= cfg
& (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
594 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_AN_ADV
, cfg
);
596 cfg
= bgx_reg_read(bgx
, 0, BGX_SPU_DBG_CONTROL
);
597 cfg
&= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN
;
598 bgx_reg_write(bgx
, 0, BGX_SPU_DBG_CONTROL
, cfg
);
601 bgx_reg_modify(bgx
, lmacid
, BGX_CMRX_CFG
, CMR_EN
);
603 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_CONTROL1
);
604 cfg
&= ~SPU_CTL_LOW_POWER
;
605 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_CONTROL1
, cfg
);
607 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SMUX_TX_CTL
);
608 cfg
&= ~SMU_TX_CTL_UNI_EN
;
609 cfg
|= SMU_TX_CTL_DIC_EN
;
610 bgx_reg_write(bgx
, lmacid
, BGX_SMUX_TX_CTL
, cfg
);
612 /* Enable receive and transmission of pause frames */
613 bgx_reg_write(bgx
, lmacid
, BGX_SMUX_CBFC_CTL
, ((0xffffULL
<< 32) |
614 BCK_EN
| DRP_EN
| TX_EN
| RX_EN
));
615 /* Configure pause time and interval */
616 bgx_reg_write(bgx
, lmacid
,
617 BGX_SMUX_TX_PAUSE_PKT_TIME
, DEFAULT_PAUSE_TIME
);
618 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SMUX_TX_PAUSE_PKT_INTERVAL
);
620 bgx_reg_write(bgx
, lmacid
, BGX_SMUX_TX_PAUSE_PKT_INTERVAL
,
621 cfg
| (DEFAULT_PAUSE_TIME
- 0x1000));
622 bgx_reg_write(bgx
, lmacid
, BGX_SMUX_TX_PAUSE_ZERO
, 0x01);
624 /* take lmac_count into account */
625 bgx_reg_modify(bgx
, lmacid
, BGX_SMUX_TX_THRESH
, (0x100 - 1));
626 /* max packet size */
627 bgx_reg_modify(bgx
, lmacid
, BGX_SMUX_RX_JABBER
, MAX_FRAME_SIZE
);
632 static int bgx_xaui_check_link(struct lmac
*lmac
)
634 struct bgx
*bgx
= lmac
->bgx
;
635 int lmacid
= lmac
->lmacid
;
636 int lmac_type
= lmac
->lmac_type
;
639 if (lmac
->use_training
) {
640 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_INT
);
641 if (!(cfg
& (1ull << 13))) {
642 cfg
= (1ull << 13) | (1ull << 14);
643 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_INT
, cfg
);
644 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_BR_PMD_CRTL
);
646 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_BR_PMD_CRTL
, cfg
);
651 /* wait for PCS to come out of reset */
652 if (bgx_poll_reg(bgx
, lmacid
, BGX_SPUX_CONTROL1
, SPU_CTL_RESET
, true)) {
653 dev_err(&bgx
->pdev
->dev
, "BGX SPU reset not completed\n");
657 if ((lmac_type
== BGX_MODE_10G_KR
) || (lmac_type
== BGX_MODE_XFI
) ||
658 (lmac_type
== BGX_MODE_40G_KR
) || (lmac_type
== BGX_MODE_XLAUI
)) {
659 if (bgx_poll_reg(bgx
, lmacid
, BGX_SPUX_BR_STATUS1
,
660 SPU_BR_STATUS_BLK_LOCK
, false)) {
661 dev_err(&bgx
->pdev
->dev
,
662 "SPU_BR_STATUS_BLK_LOCK not completed\n");
666 if (bgx_poll_reg(bgx
, lmacid
, BGX_SPUX_BX_STATUS
,
667 SPU_BX_STATUS_RX_ALIGN
, false)) {
668 dev_err(&bgx
->pdev
->dev
,
669 "SPU_BX_STATUS_RX_ALIGN not completed\n");
674 /* Clear rcvflt bit (latching high) and read it back */
675 if (bgx_reg_read(bgx
, lmacid
, BGX_SPUX_STATUS2
) & SPU_STATUS2_RCVFLT
)
676 bgx_reg_modify(bgx
, lmacid
,
677 BGX_SPUX_STATUS2
, SPU_STATUS2_RCVFLT
);
678 if (bgx_reg_read(bgx
, lmacid
, BGX_SPUX_STATUS2
) & SPU_STATUS2_RCVFLT
) {
679 dev_err(&bgx
->pdev
->dev
, "Receive fault, retry training\n");
680 if (lmac
->use_training
) {
681 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_INT
);
682 if (!(cfg
& (1ull << 13))) {
683 cfg
= (1ull << 13) | (1ull << 14);
684 bgx_reg_write(bgx
, lmacid
, BGX_SPUX_INT
, cfg
);
685 cfg
= bgx_reg_read(bgx
, lmacid
,
686 BGX_SPUX_BR_PMD_CRTL
);
688 bgx_reg_write(bgx
, lmacid
,
689 BGX_SPUX_BR_PMD_CRTL
, cfg
);
696 /* Wait for BGX RX to be idle */
697 if (bgx_poll_reg(bgx
, lmacid
, BGX_SMUX_CTL
, SMU_CTL_RX_IDLE
, false)) {
698 dev_err(&bgx
->pdev
->dev
, "SMU RX not idle\n");
702 /* Wait for BGX TX to be idle */
703 if (bgx_poll_reg(bgx
, lmacid
, BGX_SMUX_CTL
, SMU_CTL_TX_IDLE
, false)) {
704 dev_err(&bgx
->pdev
->dev
, "SMU TX not idle\n");
708 /* Check for MAC RX faults */
709 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SMUX_RX_CTL
);
710 /* 0 - Link is okay, 1 - Local fault, 2 - Remote fault */
711 cfg
&= SMU_RX_CTL_STATUS
;
715 /* Rx local/remote fault seen.
716 * Do lmac reinit to see if condition recovers
718 bgx_lmac_xaui_init(bgx
, lmac
);
723 static void bgx_poll_for_sgmii_link(struct lmac
*lmac
)
725 u64 pcs_link
, an_result
;
728 pcs_link
= bgx_reg_read(lmac
->bgx
, lmac
->lmacid
,
729 BGX_GMP_PCS_MRX_STATUS
);
731 /*Link state bit is sticky, read it again*/
732 if (!(pcs_link
& PCS_MRX_STATUS_LINK
))
733 pcs_link
= bgx_reg_read(lmac
->bgx
, lmac
->lmacid
,
734 BGX_GMP_PCS_MRX_STATUS
);
736 if (bgx_poll_reg(lmac
->bgx
, lmac
->lmacid
, BGX_GMP_PCS_MRX_STATUS
,
737 PCS_MRX_STATUS_AN_CPT
, false)) {
738 lmac
->link_up
= false;
739 lmac
->last_speed
= SPEED_UNKNOWN
;
740 lmac
->last_duplex
= DUPLEX_UNKNOWN
;
744 lmac
->link_up
= ((pcs_link
& PCS_MRX_STATUS_LINK
) != 0) ? true : false;
745 an_result
= bgx_reg_read(lmac
->bgx
, lmac
->lmacid
,
746 BGX_GMP_PCS_ANX_AN_RESULTS
);
748 speed
= (an_result
>> 3) & 0x3;
749 lmac
->last_duplex
= (an_result
>> 1) & 0x1;
752 lmac
->last_speed
= 10;
755 lmac
->last_speed
= 100;
758 lmac
->last_speed
= 1000;
761 lmac
->link_up
= false;
762 lmac
->last_speed
= SPEED_UNKNOWN
;
763 lmac
->last_duplex
= DUPLEX_UNKNOWN
;
769 if (lmac
->last_link
!= lmac
->link_up
) {
771 bgx_sgmii_change_link_state(lmac
);
772 lmac
->last_link
= lmac
->link_up
;
775 queue_delayed_work(lmac
->check_link
, &lmac
->dwork
, HZ
* 3);
778 static void bgx_poll_for_link(struct work_struct
*work
)
781 u64 spu_link
, smu_link
;
783 lmac
= container_of(work
, struct lmac
, dwork
.work
);
784 if (lmac
->is_sgmii
) {
785 bgx_poll_for_sgmii_link(lmac
);
789 /* Receive link is latching low. Force it high and verify it */
790 bgx_reg_modify(lmac
->bgx
, lmac
->lmacid
,
791 BGX_SPUX_STATUS1
, SPU_STATUS1_RCV_LNK
);
792 bgx_poll_reg(lmac
->bgx
, lmac
->lmacid
, BGX_SPUX_STATUS1
,
793 SPU_STATUS1_RCV_LNK
, false);
795 spu_link
= bgx_reg_read(lmac
->bgx
, lmac
->lmacid
, BGX_SPUX_STATUS1
);
796 smu_link
= bgx_reg_read(lmac
->bgx
, lmac
->lmacid
, BGX_SMUX_RX_CTL
);
798 if ((spu_link
& SPU_STATUS1_RCV_LNK
) &&
799 !(smu_link
& SMU_RX_CTL_STATUS
)) {
801 if (lmac
->lmac_type
== BGX_MODE_XLAUI
)
802 lmac
->last_speed
= 40000;
804 lmac
->last_speed
= 10000;
805 lmac
->last_duplex
= 1;
808 lmac
->last_speed
= SPEED_UNKNOWN
;
809 lmac
->last_duplex
= DUPLEX_UNKNOWN
;
812 if (lmac
->last_link
!= lmac
->link_up
) {
814 if (bgx_xaui_check_link(lmac
)) {
815 /* Errors, clear link_up state */
817 lmac
->last_speed
= SPEED_UNKNOWN
;
818 lmac
->last_duplex
= DUPLEX_UNKNOWN
;
821 lmac
->last_link
= lmac
->link_up
;
824 queue_delayed_work(lmac
->check_link
, &lmac
->dwork
, HZ
* 2);
827 static int phy_interface_mode(u8 lmac_type
)
829 if (lmac_type
== BGX_MODE_QSGMII
)
830 return PHY_INTERFACE_MODE_QSGMII
;
831 if (lmac_type
== BGX_MODE_RGMII
)
832 return PHY_INTERFACE_MODE_RGMII
;
834 return PHY_INTERFACE_MODE_SGMII
;
837 static int bgx_lmac_enable(struct bgx
*bgx
, u8 lmacid
)
842 lmac
= &bgx
->lmac
[lmacid
];
845 if ((lmac
->lmac_type
== BGX_MODE_SGMII
) ||
846 (lmac
->lmac_type
== BGX_MODE_QSGMII
) ||
847 (lmac
->lmac_type
== BGX_MODE_RGMII
)) {
849 if (bgx_lmac_sgmii_init(bgx
, lmac
))
853 if (bgx_lmac_xaui_init(bgx
, lmac
))
857 if (lmac
->is_sgmii
) {
858 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_GMP_GMI_TXX_APPEND
);
859 cfg
|= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
860 bgx_reg_modify(bgx
, lmacid
, BGX_GMP_GMI_TXX_APPEND
, cfg
);
861 bgx_reg_write(bgx
, lmacid
, BGX_GMP_GMI_TXX_MIN_PKT
, 60 - 1);
863 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_SMUX_TX_APPEND
);
864 cfg
|= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
865 bgx_reg_modify(bgx
, lmacid
, BGX_SMUX_TX_APPEND
, cfg
);
866 bgx_reg_write(bgx
, lmacid
, BGX_SMUX_TX_MIN_PKT
, 60 + 4);
870 bgx_reg_modify(bgx
, lmacid
, BGX_CMRX_CFG
, CMR_EN
);
872 /* Restore default cfg, incase low level firmware changed it */
873 bgx_reg_write(bgx
, lmacid
, BGX_CMRX_RX_DMAC_CTL
, 0x03);
875 if ((lmac
->lmac_type
!= BGX_MODE_XFI
) &&
876 (lmac
->lmac_type
!= BGX_MODE_XLAUI
) &&
877 (lmac
->lmac_type
!= BGX_MODE_40G_KR
) &&
878 (lmac
->lmac_type
!= BGX_MODE_10G_KR
)) {
881 bgx_reg_write(bgx
, lmacid
,
882 BGX_GMP_PCS_LINKX_TIMER
,
883 PCS_LINKX_TIMER_COUNT
);
886 /* Default to below link speed and duplex */
887 lmac
->link_up
= true;
888 lmac
->last_speed
= 1000;
889 lmac
->last_duplex
= 1;
890 bgx_sgmii_change_link_state(lmac
);
894 lmac
->phydev
->dev_flags
= 0;
896 if (phy_connect_direct(&lmac
->netdev
, lmac
->phydev
,
898 phy_interface_mode(lmac
->lmac_type
)))
901 phy_start_aneg(lmac
->phydev
);
906 lmac
->check_link
= alloc_workqueue("check_link", WQ_UNBOUND
|
908 if (!lmac
->check_link
)
910 INIT_DELAYED_WORK(&lmac
->dwork
, bgx_poll_for_link
);
911 queue_delayed_work(lmac
->check_link
, &lmac
->dwork
, 0);
916 static void bgx_lmac_disable(struct bgx
*bgx
, u8 lmacid
)
921 lmac
= &bgx
->lmac
[lmacid
];
922 if (lmac
->check_link
) {
923 /* Destroy work queue */
924 cancel_delayed_work_sync(&lmac
->dwork
);
925 destroy_workqueue(lmac
->check_link
);
928 /* Disable packet reception */
929 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_CMRX_CFG
);
930 cfg
&= ~CMR_PKT_RX_EN
;
931 bgx_reg_write(bgx
, lmacid
, BGX_CMRX_CFG
, cfg
);
933 /* Give chance for Rx/Tx FIFO to get drained */
934 bgx_poll_reg(bgx
, lmacid
, BGX_CMRX_RX_FIFO_LEN
, (u64
)0x1FFF, true);
935 bgx_poll_reg(bgx
, lmacid
, BGX_CMRX_TX_FIFO_LEN
, (u64
)0x3FFF, true);
937 /* Disable packet transmission */
938 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_CMRX_CFG
);
939 cfg
&= ~CMR_PKT_TX_EN
;
940 bgx_reg_write(bgx
, lmacid
, BGX_CMRX_CFG
, cfg
);
942 /* Disable serdes lanes */
944 bgx_reg_modify(bgx
, lmacid
,
945 BGX_SPUX_CONTROL1
, SPU_CTL_LOW_POWER
);
947 bgx_reg_modify(bgx
, lmacid
,
948 BGX_GMP_PCS_MRX_CTL
, PCS_MRX_CTL_PWR_DN
);
951 cfg
= bgx_reg_read(bgx
, lmacid
, BGX_CMRX_CFG
);
953 bgx_reg_write(bgx
, lmacid
, BGX_CMRX_CFG
, cfg
);
955 bgx_flush_dmac_addrs(bgx
, lmacid
);
957 if ((lmac
->lmac_type
!= BGX_MODE_XFI
) &&
958 (lmac
->lmac_type
!= BGX_MODE_XLAUI
) &&
959 (lmac
->lmac_type
!= BGX_MODE_40G_KR
) &&
960 (lmac
->lmac_type
!= BGX_MODE_10G_KR
) && lmac
->phydev
)
961 phy_disconnect(lmac
->phydev
);
966 static void bgx_init_hw(struct bgx
*bgx
)
971 bgx_reg_modify(bgx
, 0, BGX_CMR_GLOBAL_CFG
, CMR_GLOBAL_CFG_FCS_STRIP
);
972 if (bgx_reg_read(bgx
, 0, BGX_CMR_BIST_STATUS
))
973 dev_err(&bgx
->pdev
->dev
, "BGX%d BIST failed\n", bgx
->bgx_id
);
975 /* Set lmac type and lane2serdes mapping */
976 for (i
= 0; i
< bgx
->lmac_count
; i
++) {
977 lmac
= &bgx
->lmac
[i
];
978 bgx_reg_write(bgx
, i
, BGX_CMRX_CFG
,
979 (lmac
->lmac_type
<< 8) | lmac
->lane_to_sds
);
980 bgx
->lmac
[i
].lmacid_bd
= lmac_count
;
984 bgx_reg_write(bgx
, 0, BGX_CMR_TX_LMACS
, bgx
->lmac_count
);
985 bgx_reg_write(bgx
, 0, BGX_CMR_RX_LMACS
, bgx
->lmac_count
);
987 /* Set the backpressure AND mask */
988 for (i
= 0; i
< bgx
->lmac_count
; i
++)
989 bgx_reg_modify(bgx
, 0, BGX_CMR_CHAN_MSK_AND
,
990 ((1ULL << MAX_BGX_CHANS_PER_LMAC
) - 1) <<
991 (i
* MAX_BGX_CHANS_PER_LMAC
));
993 /* Disable all MAC filtering */
994 for (i
= 0; i
< RX_DMAC_COUNT
; i
++)
995 bgx_reg_write(bgx
, 0, BGX_CMR_RX_DMACX_CAM
+ (i
* 8), 0x00);
997 /* Disable MAC steering (NCSI traffic) */
998 for (i
= 0; i
< RX_TRAFFIC_STEER_RULE_COUNT
; i
++)
999 bgx_reg_write(bgx
, 0, BGX_CMR_RX_STREERING
+ (i
* 8), 0x00);
1002 static u8
bgx_get_lane2sds_cfg(struct bgx
*bgx
, struct lmac
*lmac
)
1004 return (u8
)(bgx_reg_read(bgx
, lmac
->lmacid
, BGX_CMRX_CFG
) & 0xFF);
1007 static void bgx_print_qlm_mode(struct bgx
*bgx
, u8 lmacid
)
1009 struct device
*dev
= &bgx
->pdev
->dev
;
1013 if (!bgx
->is_dlm
&& lmacid
)
1016 lmac
= &bgx
->lmac
[lmacid
];
1018 sprintf(str
, "BGX%d QLM mode", bgx
->bgx_id
);
1020 sprintf(str
, "BGX%d LMAC%d mode", bgx
->bgx_id
, lmacid
);
1022 switch (lmac
->lmac_type
) {
1023 case BGX_MODE_SGMII
:
1024 dev_info(dev
, "%s: SGMII\n", (char *)str
);
1027 dev_info(dev
, "%s: XAUI\n", (char *)str
);
1029 case BGX_MODE_RXAUI
:
1030 dev_info(dev
, "%s: RXAUI\n", (char *)str
);
1033 if (!lmac
->use_training
)
1034 dev_info(dev
, "%s: XFI\n", (char *)str
);
1036 dev_info(dev
, "%s: 10G_KR\n", (char *)str
);
1038 case BGX_MODE_XLAUI
:
1039 if (!lmac
->use_training
)
1040 dev_info(dev
, "%s: XLAUI\n", (char *)str
);
1042 dev_info(dev
, "%s: 40G_KR4\n", (char *)str
);
1044 case BGX_MODE_QSGMII
:
1045 dev_info(dev
, "%s: QSGMII\n", (char *)str
);
1047 case BGX_MODE_RGMII
:
1048 dev_info(dev
, "%s: RGMII\n", (char *)str
);
1050 case BGX_MODE_INVALID
:
1056 static void lmac_set_lane2sds(struct bgx
*bgx
, struct lmac
*lmac
)
1058 switch (lmac
->lmac_type
) {
1059 case BGX_MODE_SGMII
:
1061 lmac
->lane_to_sds
= lmac
->lmacid
;
1064 case BGX_MODE_XLAUI
:
1065 case BGX_MODE_RGMII
:
1066 lmac
->lane_to_sds
= 0xE4;
1068 case BGX_MODE_RXAUI
:
1069 lmac
->lane_to_sds
= (lmac
->lmacid
) ? 0xE : 0x4;
1071 case BGX_MODE_QSGMII
:
1072 /* There is no way to determine if DLM0/2 is QSGMII or
1073 * DLM1/3 is configured to QSGMII as bootloader will
1074 * configure all LMACs, so take whatever is configured
1075 * by low level firmware.
1077 lmac
->lane_to_sds
= bgx_get_lane2sds_cfg(bgx
, lmac
);
1080 lmac
->lane_to_sds
= 0;
1085 static void lmac_set_training(struct bgx
*bgx
, struct lmac
*lmac
, int lmacid
)
1087 if ((lmac
->lmac_type
!= BGX_MODE_10G_KR
) &&
1088 (lmac
->lmac_type
!= BGX_MODE_40G_KR
)) {
1089 lmac
->use_training
= 0;
1093 lmac
->use_training
= bgx_reg_read(bgx
, lmacid
, BGX_SPUX_BR_PMD_CRTL
) &
1094 SPU_PMD_CRTL_TRAIN_EN
;
1097 static void bgx_set_lmac_config(struct bgx
*bgx
, u8 idx
)
1104 lmac
= &bgx
->lmac
[idx
];
1106 if (!bgx
->is_dlm
|| bgx
->is_rgx
) {
1107 /* Read LMAC0 type to figure out QLM mode
1108 * This is configured by low level firmware
1110 cmr_cfg
= bgx_reg_read(bgx
, 0, BGX_CMRX_CFG
);
1111 lmac
->lmac_type
= (cmr_cfg
>> 8) & 0x07;
1113 lmac
->lmac_type
= BGX_MODE_RGMII
;
1114 lmac_set_training(bgx
, lmac
, 0);
1115 lmac_set_lane2sds(bgx
, lmac
);
1119 /* For DLMs or SLMs on 80/81/83xx so many lane configurations
1120 * are possible and vary across boards. Also Kernel doesn't have
1121 * any way to identify board type/info and since firmware does,
1122 * just take lmac type and serdes lane config as is.
1124 cmr_cfg
= bgx_reg_read(bgx
, idx
, BGX_CMRX_CFG
);
1125 lmac_type
= (u8
)((cmr_cfg
>> 8) & 0x07);
1126 lane_to_sds
= (u8
)(cmr_cfg
& 0xFF);
1127 /* Check if config is reset value */
1128 if ((lmac_type
== 0) && (lane_to_sds
== 0xE4))
1129 lmac
->lmac_type
= BGX_MODE_INVALID
;
1131 lmac
->lmac_type
= lmac_type
;
1132 lmac
->lane_to_sds
= lane_to_sds
;
1133 lmac_set_training(bgx
, lmac
, lmac
->lmacid
);
1136 static void bgx_get_qlm_mode(struct bgx
*bgx
)
1141 /* Init all LMAC's type to invalid */
1142 for (idx
= 0; idx
< bgx
->max_lmac
; idx
++) {
1143 lmac
= &bgx
->lmac
[idx
];
1145 lmac
->lmac_type
= BGX_MODE_INVALID
;
1146 lmac
->use_training
= false;
1149 /* It is assumed that low level firmware sets this value */
1150 bgx
->lmac_count
= bgx_reg_read(bgx
, 0, BGX_CMR_RX_LMACS
) & 0x7;
1151 if (bgx
->lmac_count
> bgx
->max_lmac
)
1152 bgx
->lmac_count
= bgx
->max_lmac
;
1154 for (idx
= 0; idx
< bgx
->lmac_count
; idx
++) {
1155 bgx_set_lmac_config(bgx
, idx
);
1156 bgx_print_qlm_mode(bgx
, idx
);
1162 static int acpi_get_mac_address(struct device
*dev
, struct acpi_device
*adev
,
1168 ret
= fwnode_property_read_u8_array(acpi_fwnode_handle(adev
),
1169 "mac-address", mac
, ETH_ALEN
);
1173 if (!is_valid_ether_addr(mac
)) {
1174 dev_err(dev
, "MAC address invalid: %pM\n", mac
);
1179 dev_info(dev
, "MAC address set to: %pM\n", mac
);
1181 memcpy(dst
, mac
, ETH_ALEN
);
1186 /* Currently only sets the MAC address. */
1187 static acpi_status
bgx_acpi_register_phy(acpi_handle handle
,
1188 u32 lvl
, void *context
, void **rv
)
1190 struct bgx
*bgx
= context
;
1191 struct device
*dev
= &bgx
->pdev
->dev
;
1192 struct acpi_device
*adev
;
1194 if (acpi_bus_get_device(handle
, &adev
))
1197 acpi_get_mac_address(dev
, adev
, bgx
->lmac
[bgx
->acpi_lmac_idx
].mac
);
1199 SET_NETDEV_DEV(&bgx
->lmac
[bgx
->acpi_lmac_idx
].netdev
, dev
);
1201 bgx
->lmac
[bgx
->acpi_lmac_idx
].lmacid
= bgx
->acpi_lmac_idx
;
1202 bgx
->acpi_lmac_idx
++; /* move to next LMAC */
1207 static acpi_status
bgx_acpi_match_id(acpi_handle handle
, u32 lvl
,
1208 void *context
, void **ret_val
)
1210 struct acpi_buffer string
= { ACPI_ALLOCATE_BUFFER
, NULL
};
1211 struct bgx
*bgx
= context
;
1214 snprintf(bgx_sel
, 5, "BGX%d", bgx
->bgx_id
);
1215 if (ACPI_FAILURE(acpi_get_name(handle
, ACPI_SINGLE_NAME
, &string
))) {
1216 pr_warn("Invalid link device\n");
1220 if (strncmp(string
.pointer
, bgx_sel
, 4))
1223 acpi_walk_namespace(ACPI_TYPE_DEVICE
, handle
, 1,
1224 bgx_acpi_register_phy
, NULL
, bgx
, NULL
);
1226 kfree(string
.pointer
);
1227 return AE_CTRL_TERMINATE
;
1230 static int bgx_init_acpi_phy(struct bgx
*bgx
)
1232 acpi_get_devices(NULL
, bgx_acpi_match_id
, bgx
, (void **)NULL
);
1238 static int bgx_init_acpi_phy(struct bgx
*bgx
)
1243 #endif /* CONFIG_ACPI */
1245 #if IS_ENABLED(CONFIG_OF_MDIO)
1247 static int bgx_init_of_phy(struct bgx
*bgx
)
1249 struct fwnode_handle
*fwn
;
1250 struct device_node
*node
= NULL
;
1253 device_for_each_child_node(&bgx
->pdev
->dev
, fwn
) {
1254 struct phy_device
*pd
;
1255 struct device_node
*phy_np
;
1258 /* Should always be an OF node. But if it is not, we
1259 * cannot handle it, so exit the loop.
1261 node
= to_of_node(fwn
);
1265 mac
= of_get_mac_address(node
);
1267 ether_addr_copy(bgx
->lmac
[lmac
].mac
, mac
);
1269 SET_NETDEV_DEV(&bgx
->lmac
[lmac
].netdev
, &bgx
->pdev
->dev
);
1270 bgx
->lmac
[lmac
].lmacid
= lmac
;
1272 phy_np
= of_parse_phandle(node
, "phy-handle", 0);
1273 /* If there is no phy or defective firmware presents
1274 * this cortina phy, for which there is no driver
1275 * support, ignore it.
1278 !of_device_is_compatible(phy_np
, "cortina,cs4223-slice")) {
1279 /* Wait until the phy drivers are available */
1280 pd
= of_phy_find_device(phy_np
);
1283 bgx
->lmac
[lmac
].phydev
= pd
;
1287 if (lmac
== bgx
->max_lmac
) {
1295 /* We are bailing out, try not to leak device reference counts
1296 * for phy devices we may have already found.
1299 if (bgx
->lmac
[lmac
].phydev
) {
1300 put_device(&bgx
->lmac
[lmac
].phydev
->mdio
.dev
);
1301 bgx
->lmac
[lmac
].phydev
= NULL
;
1306 return -EPROBE_DEFER
;
1311 static int bgx_init_of_phy(struct bgx
*bgx
)
1316 #endif /* CONFIG_OF_MDIO */
1318 static int bgx_init_phy(struct bgx
*bgx
)
1321 return bgx_init_acpi_phy(bgx
);
1323 return bgx_init_of_phy(bgx
);
1326 static int bgx_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1329 struct device
*dev
= &pdev
->dev
;
1330 struct bgx
*bgx
= NULL
;
1334 bgx
= devm_kzalloc(dev
, sizeof(*bgx
), GFP_KERNEL
);
1339 pci_set_drvdata(pdev
, bgx
);
1341 err
= pci_enable_device(pdev
);
1343 dev_err(dev
, "Failed to enable PCI device\n");
1344 pci_set_drvdata(pdev
, NULL
);
1348 err
= pci_request_regions(pdev
, DRV_NAME
);
1350 dev_err(dev
, "PCI request regions failed 0x%x\n", err
);
1351 goto err_disable_device
;
1354 /* MAP configuration registers */
1355 bgx
->reg_base
= pcim_iomap(pdev
, PCI_CFG_REG_BAR_NUM
, 0);
1356 if (!bgx
->reg_base
) {
1357 dev_err(dev
, "BGX: Cannot map CSR memory space, aborting\n");
1359 goto err_release_regions
;
1362 set_max_bgx_per_node(pdev
);
1364 pci_read_config_word(pdev
, PCI_DEVICE_ID
, &sdevid
);
1365 if (sdevid
!= PCI_DEVICE_ID_THUNDER_RGX
) {
1366 bgx
->bgx_id
= (pci_resource_start(pdev
,
1367 PCI_CFG_REG_BAR_NUM
) >> 24) & BGX_ID_MASK
;
1368 bgx
->bgx_id
+= nic_get_node_id(pdev
) * max_bgx_per_node
;
1369 bgx
->max_lmac
= MAX_LMAC_PER_BGX
;
1370 bgx_vnic
[bgx
->bgx_id
] = bgx
;
1374 bgx
->bgx_id
= MAX_BGX_PER_CN81XX
- 1;
1375 bgx_vnic
[bgx
->bgx_id
] = bgx
;
1379 /* On 81xx all are DLMs and on 83xx there are 3 BGX QLMs and one
1380 * BGX i.e BGX2 can be split across 2 DLMs.
1382 pci_read_config_word(pdev
, PCI_SUBSYSTEM_ID
, &sdevid
);
1383 if ((sdevid
== PCI_SUBSYS_DEVID_81XX_BGX
) ||
1384 ((sdevid
== PCI_SUBSYS_DEVID_83XX_BGX
) && (bgx
->bgx_id
== 2)))
1387 bgx_get_qlm_mode(bgx
);
1389 err
= bgx_init_phy(bgx
);
1395 /* Enable all LMACs */
1396 for (lmac
= 0; lmac
< bgx
->lmac_count
; lmac
++) {
1397 err
= bgx_lmac_enable(bgx
, lmac
);
1399 dev_err(dev
, "BGX%d failed to enable lmac%d\n",
1402 bgx_lmac_disable(bgx
, --lmac
);
1410 bgx_vnic
[bgx
->bgx_id
] = NULL
;
1411 err_release_regions
:
1412 pci_release_regions(pdev
);
1414 pci_disable_device(pdev
);
1415 pci_set_drvdata(pdev
, NULL
);
1419 static void bgx_remove(struct pci_dev
*pdev
)
1421 struct bgx
*bgx
= pci_get_drvdata(pdev
);
1424 /* Disable all LMACs */
1425 for (lmac
= 0; lmac
< bgx
->lmac_count
; lmac
++)
1426 bgx_lmac_disable(bgx
, lmac
);
1428 bgx_vnic
[bgx
->bgx_id
] = NULL
;
1429 pci_release_regions(pdev
);
1430 pci_disable_device(pdev
);
1431 pci_set_drvdata(pdev
, NULL
);
1434 static struct pci_driver bgx_driver
= {
1436 .id_table
= bgx_id_table
,
1438 .remove
= bgx_remove
,
1441 static int __init
bgx_init_module(void)
1443 pr_info("%s, ver %s\n", DRV_NAME
, DRV_VERSION
);
1445 return pci_register_driver(&bgx_driver
);
1448 static void __exit
bgx_cleanup_module(void)
1450 pci_unregister_driver(&bgx_driver
);
1453 module_init(bgx_init_module
);
1454 module_exit(bgx_cleanup_module
);