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net: hns3: add MTU initialization for hardware
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
1 /*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/if_vlan.h>
21 #include <net/rtnetlink.h>
22 #include "hclge_cmd.h"
23 #include "hclge_dcb.h"
24 #include "hclge_main.h"
25 #include "hclge_mbx.h"
26 #include "hclge_mdio.h"
27 #include "hclge_tm.h"
28 #include "hnae3.h"
29
30 #define HCLGE_NAME "hclge"
31 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
32 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
33 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
34 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35
36 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
37 enum hclge_mta_dmac_sel_type mta_mac_sel,
38 bool enable);
39 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
40 static int hclge_init_vlan_config(struct hclge_dev *hdev);
41 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
42
43 static struct hnae3_ae_algo ae_algo;
44
45 static const struct pci_device_id ae_algo_pci_tbl[] = {
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
50 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
51 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
52 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
53 /* required last entry */
54 {0, }
55 };
56
57 static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
58 "Mac Loopback test",
59 "Serdes Loopback test",
60 "Phy Loopback test"
61 };
62
63 static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
64 {"igu_rx_oversize_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
66 {"igu_rx_undersize_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
68 {"igu_rx_out_all_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
70 {"igu_rx_uni_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
72 {"igu_rx_multi_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
74 {"igu_rx_broad_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
76 {"egu_tx_out_all_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
78 {"egu_tx_uni_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
80 {"egu_tx_multi_pkt",
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
82 {"egu_tx_broad_pkt",
83 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
84 {"ssu_ppp_mac_key_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
86 {"ssu_ppp_host_key_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
88 {"ppp_ssu_mac_rlt_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
90 {"ppp_ssu_host_rlt_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
92 {"ssu_tx_in_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
94 {"ssu_tx_out_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
96 {"ssu_rx_in_num",
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
98 {"ssu_rx_out_num",
99 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
100 };
101
102 static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
103 {"igu_rx_err_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
105 {"igu_rx_no_eof_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
107 {"igu_rx_no_sof_pkt",
108 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
109 {"egu_tx_1588_pkt",
110 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
111 {"ssu_full_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
113 {"ssu_part_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
115 {"ppp_key_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
117 {"ppp_rlt_drop_num",
118 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
119 {"ssu_key_drop_num",
120 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
121 {"pkt_curr_buf_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
123 {"qcn_fb_rcv_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
125 {"qcn_fb_drop_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
127 {"qcn_fb_invaild_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
129 {"rx_packet_tc0_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
131 {"rx_packet_tc1_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
133 {"rx_packet_tc2_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
135 {"rx_packet_tc3_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
137 {"rx_packet_tc4_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
139 {"rx_packet_tc5_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
141 {"rx_packet_tc6_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
143 {"rx_packet_tc7_in_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
145 {"rx_packet_tc0_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
147 {"rx_packet_tc1_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
149 {"rx_packet_tc2_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
151 {"rx_packet_tc3_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
153 {"rx_packet_tc4_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
155 {"rx_packet_tc5_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
157 {"rx_packet_tc6_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
159 {"rx_packet_tc7_out_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
161 {"tx_packet_tc0_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
163 {"tx_packet_tc1_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
165 {"tx_packet_tc2_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
167 {"tx_packet_tc3_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
169 {"tx_packet_tc4_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
171 {"tx_packet_tc5_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
173 {"tx_packet_tc6_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
175 {"tx_packet_tc7_in_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
177 {"tx_packet_tc0_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
179 {"tx_packet_tc1_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
181 {"tx_packet_tc2_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
183 {"tx_packet_tc3_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
185 {"tx_packet_tc4_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
187 {"tx_packet_tc5_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
189 {"tx_packet_tc6_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
191 {"tx_packet_tc7_out_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
193 {"pkt_curr_buf_tc0_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
195 {"pkt_curr_buf_tc1_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
197 {"pkt_curr_buf_tc2_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
199 {"pkt_curr_buf_tc3_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
201 {"pkt_curr_buf_tc4_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
203 {"pkt_curr_buf_tc5_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
205 {"pkt_curr_buf_tc6_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
207 {"pkt_curr_buf_tc7_cnt",
208 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
209 {"mb_uncopy_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
211 {"lo_pri_unicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
213 {"hi_pri_multicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
215 {"lo_pri_multicast_rlt_drop_num",
216 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
217 {"rx_oq_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
219 {"tx_oq_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
221 {"nic_l2_err_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
223 {"roc_l2_err_drop_pkt_cnt",
224 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
225 };
226
227 static const struct hclge_comm_stats_str g_mac_stats_string[] = {
228 {"mac_tx_mac_pause_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
230 {"mac_rx_mac_pause_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
232 {"mac_tx_pfc_pri0_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
234 {"mac_tx_pfc_pri1_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
236 {"mac_tx_pfc_pri2_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
238 {"mac_tx_pfc_pri3_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
240 {"mac_tx_pfc_pri4_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
242 {"mac_tx_pfc_pri5_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
244 {"mac_tx_pfc_pri6_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
246 {"mac_tx_pfc_pri7_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
248 {"mac_rx_pfc_pri0_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
250 {"mac_rx_pfc_pri1_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
252 {"mac_rx_pfc_pri2_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
254 {"mac_rx_pfc_pri3_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
256 {"mac_rx_pfc_pri4_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
258 {"mac_rx_pfc_pri5_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
260 {"mac_rx_pfc_pri6_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
262 {"mac_rx_pfc_pri7_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
264 {"mac_tx_total_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
266 {"mac_tx_total_oct_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
268 {"mac_tx_good_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
270 {"mac_tx_bad_pkt_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
272 {"mac_tx_good_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
274 {"mac_tx_bad_oct_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
276 {"mac_tx_uni_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
278 {"mac_tx_multi_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
280 {"mac_tx_broad_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
282 {"mac_tx_undersize_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
284 {"mac_tx_oversize_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
286 {"mac_tx_64_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
288 {"mac_tx_65_127_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
290 {"mac_tx_128_255_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
292 {"mac_tx_256_511_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
294 {"mac_tx_512_1023_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
296 {"mac_tx_1024_1518_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
298 {"mac_tx_1519_max_oct_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
300 {"mac_rx_total_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
302 {"mac_rx_total_oct_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
304 {"mac_rx_good_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
306 {"mac_rx_bad_pkt_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
308 {"mac_rx_good_oct_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
310 {"mac_rx_bad_oct_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
312 {"mac_rx_uni_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
314 {"mac_rx_multi_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
316 {"mac_rx_broad_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
318 {"mac_rx_undersize_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
320 {"mac_rx_oversize_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
322 {"mac_rx_64_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
324 {"mac_rx_65_127_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
326 {"mac_rx_128_255_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
328 {"mac_rx_256_511_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
330 {"mac_rx_512_1023_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
332 {"mac_rx_1024_1518_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
334 {"mac_rx_1519_max_oct_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
336
337 {"mac_tx_fragment_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
339 {"mac_tx_undermin_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
341 {"mac_tx_jabber_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
343 {"mac_tx_err_all_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
345 {"mac_tx_from_app_good_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
347 {"mac_tx_from_app_bad_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
349 {"mac_rx_fragment_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
351 {"mac_rx_undermin_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
353 {"mac_rx_jabber_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
355 {"mac_rx_fcs_err_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
357 {"mac_rx_send_app_good_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
359 {"mac_rx_send_app_bad_pkt_num",
360 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
361 };
362
363 static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
364 {
365 #define HCLGE_64_BIT_CMD_NUM 5
366 #define HCLGE_64_BIT_RTN_DATANUM 4
367 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
368 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
369 __le64 *desc_data;
370 int i, k, n;
371 int ret;
372
373 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
374 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
375 if (ret) {
376 dev_err(&hdev->pdev->dev,
377 "Get 64 bit pkt stats fail, status = %d.\n", ret);
378 return ret;
379 }
380
381 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
382 if (unlikely(i == 0)) {
383 desc_data = (__le64 *)(&desc[i].data[0]);
384 n = HCLGE_64_BIT_RTN_DATANUM - 1;
385 } else {
386 desc_data = (__le64 *)(&desc[i]);
387 n = HCLGE_64_BIT_RTN_DATANUM;
388 }
389 for (k = 0; k < n; k++) {
390 *data++ += le64_to_cpu(*desc_data);
391 desc_data++;
392 }
393 }
394
395 return 0;
396 }
397
398 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
399 {
400 stats->pkt_curr_buf_cnt = 0;
401 stats->pkt_curr_buf_tc0_cnt = 0;
402 stats->pkt_curr_buf_tc1_cnt = 0;
403 stats->pkt_curr_buf_tc2_cnt = 0;
404 stats->pkt_curr_buf_tc3_cnt = 0;
405 stats->pkt_curr_buf_tc4_cnt = 0;
406 stats->pkt_curr_buf_tc5_cnt = 0;
407 stats->pkt_curr_buf_tc6_cnt = 0;
408 stats->pkt_curr_buf_tc7_cnt = 0;
409 }
410
411 static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
412 {
413 #define HCLGE_32_BIT_CMD_NUM 8
414 #define HCLGE_32_BIT_RTN_DATANUM 8
415
416 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
417 struct hclge_32_bit_stats *all_32_bit_stats;
418 __le32 *desc_data;
419 int i, k, n;
420 u64 *data;
421 int ret;
422
423 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
424 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
425
426 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
427 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
428 if (ret) {
429 dev_err(&hdev->pdev->dev,
430 "Get 32 bit pkt stats fail, status = %d.\n", ret);
431
432 return ret;
433 }
434
435 hclge_reset_partial_32bit_counter(all_32_bit_stats);
436 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
437 if (unlikely(i == 0)) {
438 __le16 *desc_data_16bit;
439
440 all_32_bit_stats->igu_rx_err_pkt +=
441 le32_to_cpu(desc[i].data[0]);
442
443 desc_data_16bit = (__le16 *)&desc[i].data[1];
444 all_32_bit_stats->igu_rx_no_eof_pkt +=
445 le16_to_cpu(*desc_data_16bit);
446
447 desc_data_16bit++;
448 all_32_bit_stats->igu_rx_no_sof_pkt +=
449 le16_to_cpu(*desc_data_16bit);
450
451 desc_data = &desc[i].data[2];
452 n = HCLGE_32_BIT_RTN_DATANUM - 4;
453 } else {
454 desc_data = (__le32 *)&desc[i];
455 n = HCLGE_32_BIT_RTN_DATANUM;
456 }
457 for (k = 0; k < n; k++) {
458 *data++ += le32_to_cpu(*desc_data);
459 desc_data++;
460 }
461 }
462
463 return 0;
464 }
465
466 static int hclge_mac_update_stats(struct hclge_dev *hdev)
467 {
468 #define HCLGE_MAC_CMD_NUM 17
469 #define HCLGE_RTN_DATA_NUM 4
470
471 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
472 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
473 __le64 *desc_data;
474 int i, k, n;
475 int ret;
476
477 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
478 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
479 if (ret) {
480 dev_err(&hdev->pdev->dev,
481 "Get MAC pkt stats fail, status = %d.\n", ret);
482
483 return ret;
484 }
485
486 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
487 if (unlikely(i == 0)) {
488 desc_data = (__le64 *)(&desc[i].data[0]);
489 n = HCLGE_RTN_DATA_NUM - 2;
490 } else {
491 desc_data = (__le64 *)(&desc[i]);
492 n = HCLGE_RTN_DATA_NUM;
493 }
494 for (k = 0; k < n; k++) {
495 *data++ += le64_to_cpu(*desc_data);
496 desc_data++;
497 }
498 }
499
500 return 0;
501 }
502
503 static int hclge_tqps_update_stats(struct hnae3_handle *handle)
504 {
505 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
506 struct hclge_vport *vport = hclge_get_vport(handle);
507 struct hclge_dev *hdev = vport->back;
508 struct hnae3_queue *queue;
509 struct hclge_desc desc[1];
510 struct hclge_tqp *tqp;
511 int ret, i;
512
513 for (i = 0; i < kinfo->num_tqps; i++) {
514 queue = handle->kinfo.tqp[i];
515 tqp = container_of(queue, struct hclge_tqp, q);
516 /* command : HCLGE_OPC_QUERY_IGU_STAT */
517 hclge_cmd_setup_basic_desc(&desc[0],
518 HCLGE_OPC_QUERY_RX_STATUS,
519 true);
520
521 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
522 ret = hclge_cmd_send(&hdev->hw, desc, 1);
523 if (ret) {
524 dev_err(&hdev->pdev->dev,
525 "Query tqp stat fail, status = %d,queue = %d\n",
526 ret, i);
527 return ret;
528 }
529 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
530 le32_to_cpu(desc[0].data[1]);
531 }
532
533 for (i = 0; i < kinfo->num_tqps; i++) {
534 queue = handle->kinfo.tqp[i];
535 tqp = container_of(queue, struct hclge_tqp, q);
536 /* command : HCLGE_OPC_QUERY_IGU_STAT */
537 hclge_cmd_setup_basic_desc(&desc[0],
538 HCLGE_OPC_QUERY_TX_STATUS,
539 true);
540
541 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
542 ret = hclge_cmd_send(&hdev->hw, desc, 1);
543 if (ret) {
544 dev_err(&hdev->pdev->dev,
545 "Query tqp stat fail, status = %d,queue = %d\n",
546 ret, i);
547 return ret;
548 }
549 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
550 le32_to_cpu(desc[0].data[1]);
551 }
552
553 return 0;
554 }
555
556 static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
557 {
558 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
559 struct hclge_tqp *tqp;
560 u64 *buff = data;
561 int i;
562
563 for (i = 0; i < kinfo->num_tqps; i++) {
564 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
565 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
566 }
567
568 for (i = 0; i < kinfo->num_tqps; i++) {
569 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
570 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
571 }
572
573 return buff;
574 }
575
576 static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
577 {
578 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
579
580 return kinfo->num_tqps * (2);
581 }
582
583 static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
584 {
585 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
586 u8 *buff = data;
587 int i = 0;
588
589 for (i = 0; i < kinfo->num_tqps; i++) {
590 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
591 struct hclge_tqp, q);
592 snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd",
593 tqp->index);
594 buff = buff + ETH_GSTRING_LEN;
595 }
596
597 for (i = 0; i < kinfo->num_tqps; i++) {
598 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
599 struct hclge_tqp, q);
600 snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd",
601 tqp->index);
602 buff = buff + ETH_GSTRING_LEN;
603 }
604
605 return buff;
606 }
607
608 static u64 *hclge_comm_get_stats(void *comm_stats,
609 const struct hclge_comm_stats_str strs[],
610 int size, u64 *data)
611 {
612 u64 *buf = data;
613 u32 i;
614
615 for (i = 0; i < size; i++)
616 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
617
618 return buf + size;
619 }
620
621 static u8 *hclge_comm_get_strings(u32 stringset,
622 const struct hclge_comm_stats_str strs[],
623 int size, u8 *data)
624 {
625 char *buff = (char *)data;
626 u32 i;
627
628 if (stringset != ETH_SS_STATS)
629 return buff;
630
631 for (i = 0; i < size; i++) {
632 snprintf(buff, ETH_GSTRING_LEN,
633 strs[i].desc);
634 buff = buff + ETH_GSTRING_LEN;
635 }
636
637 return (u8 *)buff;
638 }
639
640 static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
641 struct net_device_stats *net_stats)
642 {
643 net_stats->tx_dropped = 0;
644 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
645 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
646 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
647
648 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
649 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
650 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
651 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
652 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
653
654 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
655 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
656
657 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
658 net_stats->rx_length_errors =
659 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
660 net_stats->rx_length_errors +=
661 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
662 net_stats->rx_over_errors =
663 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
664 }
665
666 static void hclge_update_stats_for_all(struct hclge_dev *hdev)
667 {
668 struct hnae3_handle *handle;
669 int status;
670
671 handle = &hdev->vport[0].nic;
672 if (handle->client) {
673 status = hclge_tqps_update_stats(handle);
674 if (status) {
675 dev_err(&hdev->pdev->dev,
676 "Update TQPS stats fail, status = %d.\n",
677 status);
678 }
679 }
680
681 status = hclge_mac_update_stats(hdev);
682 if (status)
683 dev_err(&hdev->pdev->dev,
684 "Update MAC stats fail, status = %d.\n", status);
685
686 status = hclge_32_bit_update_stats(hdev);
687 if (status)
688 dev_err(&hdev->pdev->dev,
689 "Update 32 bit stats fail, status = %d.\n",
690 status);
691
692 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
693 }
694
695 static void hclge_update_stats(struct hnae3_handle *handle,
696 struct net_device_stats *net_stats)
697 {
698 struct hclge_vport *vport = hclge_get_vport(handle);
699 struct hclge_dev *hdev = vport->back;
700 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
701 int status;
702
703 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
704 return;
705
706 status = hclge_mac_update_stats(hdev);
707 if (status)
708 dev_err(&hdev->pdev->dev,
709 "Update MAC stats fail, status = %d.\n",
710 status);
711
712 status = hclge_32_bit_update_stats(hdev);
713 if (status)
714 dev_err(&hdev->pdev->dev,
715 "Update 32 bit stats fail, status = %d.\n",
716 status);
717
718 status = hclge_64_bit_update_stats(hdev);
719 if (status)
720 dev_err(&hdev->pdev->dev,
721 "Update 64 bit stats fail, status = %d.\n",
722 status);
723
724 status = hclge_tqps_update_stats(handle);
725 if (status)
726 dev_err(&hdev->pdev->dev,
727 "Update TQPS stats fail, status = %d.\n",
728 status);
729
730 hclge_update_netstat(hw_stats, net_stats);
731
732 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
733 }
734
735 static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
736 {
737 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
738
739 struct hclge_vport *vport = hclge_get_vport(handle);
740 struct hclge_dev *hdev = vport->back;
741 int count = 0;
742
743 /* Loopback test support rules:
744 * mac: only GE mode support
745 * serdes: all mac mode will support include GE/XGE/LGE/CGE
746 * phy: only support when phy device exist on board
747 */
748 if (stringset == ETH_SS_TEST) {
749 /* clear loopback bit flags at first */
750 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
751 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
752 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
753 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
754 count += 1;
755 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
756 } else {
757 count = -EOPNOTSUPP;
758 }
759 } else if (stringset == ETH_SS_STATS) {
760 count = ARRAY_SIZE(g_mac_stats_string) +
761 ARRAY_SIZE(g_all_32bit_stats_string) +
762 ARRAY_SIZE(g_all_64bit_stats_string) +
763 hclge_tqps_get_sset_count(handle, stringset);
764 }
765
766 return count;
767 }
768
769 static void hclge_get_strings(struct hnae3_handle *handle,
770 u32 stringset,
771 u8 *data)
772 {
773 u8 *p = (char *)data;
774 int size;
775
776 if (stringset == ETH_SS_STATS) {
777 size = ARRAY_SIZE(g_mac_stats_string);
778 p = hclge_comm_get_strings(stringset,
779 g_mac_stats_string,
780 size,
781 p);
782 size = ARRAY_SIZE(g_all_32bit_stats_string);
783 p = hclge_comm_get_strings(stringset,
784 g_all_32bit_stats_string,
785 size,
786 p);
787 size = ARRAY_SIZE(g_all_64bit_stats_string);
788 p = hclge_comm_get_strings(stringset,
789 g_all_64bit_stats_string,
790 size,
791 p);
792 p = hclge_tqps_get_strings(handle, p);
793 } else if (stringset == ETH_SS_TEST) {
794 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
795 memcpy(p,
796 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
797 ETH_GSTRING_LEN);
798 p += ETH_GSTRING_LEN;
799 }
800 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
801 memcpy(p,
802 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
803 ETH_GSTRING_LEN);
804 p += ETH_GSTRING_LEN;
805 }
806 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
807 memcpy(p,
808 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
809 ETH_GSTRING_LEN);
810 p += ETH_GSTRING_LEN;
811 }
812 }
813 }
814
815 static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
816 {
817 struct hclge_vport *vport = hclge_get_vport(handle);
818 struct hclge_dev *hdev = vport->back;
819 u64 *p;
820
821 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
822 g_mac_stats_string,
823 ARRAY_SIZE(g_mac_stats_string),
824 data);
825 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
826 g_all_32bit_stats_string,
827 ARRAY_SIZE(g_all_32bit_stats_string),
828 p);
829 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
830 g_all_64bit_stats_string,
831 ARRAY_SIZE(g_all_64bit_stats_string),
832 p);
833 p = hclge_tqps_get_stats(handle, p);
834 }
835
836 static int hclge_parse_func_status(struct hclge_dev *hdev,
837 struct hclge_func_status_cmd *status)
838 {
839 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
840 return -EINVAL;
841
842 /* Set the pf to main pf */
843 if (status->pf_state & HCLGE_PF_STATE_MAIN)
844 hdev->flag |= HCLGE_FLAG_MAIN;
845 else
846 hdev->flag &= ~HCLGE_FLAG_MAIN;
847
848 return 0;
849 }
850
851 static int hclge_query_function_status(struct hclge_dev *hdev)
852 {
853 struct hclge_func_status_cmd *req;
854 struct hclge_desc desc;
855 int timeout = 0;
856 int ret;
857
858 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
859 req = (struct hclge_func_status_cmd *)desc.data;
860
861 do {
862 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
863 if (ret) {
864 dev_err(&hdev->pdev->dev,
865 "query function status failed %d.\n",
866 ret);
867
868 return ret;
869 }
870
871 /* Check pf reset is done */
872 if (req->pf_state)
873 break;
874 usleep_range(1000, 2000);
875 } while (timeout++ < 5);
876
877 ret = hclge_parse_func_status(hdev, req);
878
879 return ret;
880 }
881
882 static int hclge_query_pf_resource(struct hclge_dev *hdev)
883 {
884 struct hclge_pf_res_cmd *req;
885 struct hclge_desc desc;
886 int ret;
887
888 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
889 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
890 if (ret) {
891 dev_err(&hdev->pdev->dev,
892 "query pf resource failed %d.\n", ret);
893 return ret;
894 }
895
896 req = (struct hclge_pf_res_cmd *)desc.data;
897 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
898 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
899
900 if (hnae3_dev_roce_supported(hdev)) {
901 hdev->num_roce_msi =
902 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
903 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
904
905 /* PF should have NIC vectors and Roce vectors,
906 * NIC vectors are queued before Roce vectors.
907 */
908 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
909 } else {
910 hdev->num_msi =
911 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
912 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
913 }
914
915 return 0;
916 }
917
918 static int hclge_parse_speed(int speed_cmd, int *speed)
919 {
920 switch (speed_cmd) {
921 case 6:
922 *speed = HCLGE_MAC_SPEED_10M;
923 break;
924 case 7:
925 *speed = HCLGE_MAC_SPEED_100M;
926 break;
927 case 0:
928 *speed = HCLGE_MAC_SPEED_1G;
929 break;
930 case 1:
931 *speed = HCLGE_MAC_SPEED_10G;
932 break;
933 case 2:
934 *speed = HCLGE_MAC_SPEED_25G;
935 break;
936 case 3:
937 *speed = HCLGE_MAC_SPEED_40G;
938 break;
939 case 4:
940 *speed = HCLGE_MAC_SPEED_50G;
941 break;
942 case 5:
943 *speed = HCLGE_MAC_SPEED_100G;
944 break;
945 default:
946 return -EINVAL;
947 }
948
949 return 0;
950 }
951
952 static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
953 {
954 struct hclge_cfg_param_cmd *req;
955 u64 mac_addr_tmp_high;
956 u64 mac_addr_tmp;
957 int i;
958
959 req = (struct hclge_cfg_param_cmd *)desc[0].data;
960
961 /* get the configuration */
962 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
963 HCLGE_CFG_VMDQ_M,
964 HCLGE_CFG_VMDQ_S);
965 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
966 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
967 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
968 HCLGE_CFG_TQP_DESC_N_M,
969 HCLGE_CFG_TQP_DESC_N_S);
970
971 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
972 HCLGE_CFG_PHY_ADDR_M,
973 HCLGE_CFG_PHY_ADDR_S);
974 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
975 HCLGE_CFG_MEDIA_TP_M,
976 HCLGE_CFG_MEDIA_TP_S);
977 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
978 HCLGE_CFG_RX_BUF_LEN_M,
979 HCLGE_CFG_RX_BUF_LEN_S);
980 /* get mac_address */
981 mac_addr_tmp = __le32_to_cpu(req->param[2]);
982 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
983 HCLGE_CFG_MAC_ADDR_H_M,
984 HCLGE_CFG_MAC_ADDR_H_S);
985
986 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
987
988 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
989 HCLGE_CFG_DEFAULT_SPEED_M,
990 HCLGE_CFG_DEFAULT_SPEED_S);
991 cfg->rss_size_max = hnae_get_field(__le32_to_cpu(req->param[3]),
992 HCLGE_CFG_RSS_SIZE_M,
993 HCLGE_CFG_RSS_SIZE_S);
994
995 for (i = 0; i < ETH_ALEN; i++)
996 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
997
998 req = (struct hclge_cfg_param_cmd *)desc[1].data;
999 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
1000 }
1001
1002 /* hclge_get_cfg: query the static parameter from flash
1003 * @hdev: pointer to struct hclge_dev
1004 * @hcfg: the config structure to be getted
1005 */
1006 static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
1007 {
1008 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
1009 struct hclge_cfg_param_cmd *req;
1010 int i, ret;
1011
1012 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
1013 u32 offset = 0;
1014
1015 req = (struct hclge_cfg_param_cmd *)desc[i].data;
1016 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1017 true);
1018 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
1019 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1020 /* Len should be united by 4 bytes when send to hardware */
1021 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
1022 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1023 req->offset = cpu_to_le32(offset);
1024 }
1025
1026 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1027 if (ret) {
1028 dev_err(&hdev->pdev->dev,
1029 "get config failed %d.\n", ret);
1030 return ret;
1031 }
1032
1033 hclge_parse_cfg(hcfg, desc);
1034 return 0;
1035 }
1036
1037 static int hclge_get_cap(struct hclge_dev *hdev)
1038 {
1039 int ret;
1040
1041 ret = hclge_query_function_status(hdev);
1042 if (ret) {
1043 dev_err(&hdev->pdev->dev,
1044 "query function status error %d.\n", ret);
1045 return ret;
1046 }
1047
1048 /* get pf resource */
1049 ret = hclge_query_pf_resource(hdev);
1050 if (ret) {
1051 dev_err(&hdev->pdev->dev,
1052 "query pf resource error %d.\n", ret);
1053 return ret;
1054 }
1055
1056 return 0;
1057 }
1058
1059 static int hclge_configure(struct hclge_dev *hdev)
1060 {
1061 struct hclge_cfg cfg;
1062 int ret, i;
1063
1064 ret = hclge_get_cfg(hdev, &cfg);
1065 if (ret) {
1066 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1067 return ret;
1068 }
1069
1070 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1071 hdev->base_tqp_pid = 0;
1072 hdev->rss_size_max = cfg.rss_size_max;
1073 hdev->rx_buf_len = cfg.rx_buf_len;
1074 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
1075 hdev->hw.mac.media_type = cfg.media_type;
1076 hdev->hw.mac.phy_addr = cfg.phy_addr;
1077 hdev->num_desc = cfg.tqp_desc_num;
1078 hdev->tm_info.num_pg = 1;
1079 hdev->tc_max = cfg.tc_num;
1080 hdev->tm_info.hw_pfc_map = 0;
1081
1082 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1083 if (ret) {
1084 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1085 return ret;
1086 }
1087
1088 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1089 (hdev->tc_max < 1)) {
1090 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1091 hdev->tc_max);
1092 hdev->tc_max = 1;
1093 }
1094
1095 /* Dev does not support DCB */
1096 if (!hnae3_dev_dcb_supported(hdev)) {
1097 hdev->tc_max = 1;
1098 hdev->pfc_max = 0;
1099 } else {
1100 hdev->pfc_max = hdev->tc_max;
1101 }
1102
1103 hdev->tm_info.num_tc = hdev->tc_max;
1104
1105 /* Currently not support uncontiuous tc */
1106 for (i = 0; i < hdev->tm_info.num_tc; i++)
1107 hnae_set_bit(hdev->hw_tc_map, i, 1);
1108
1109 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1110
1111 return ret;
1112 }
1113
1114 static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1115 int tso_mss_max)
1116 {
1117 struct hclge_cfg_tso_status_cmd *req;
1118 struct hclge_desc desc;
1119 u16 tso_mss;
1120
1121 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1122
1123 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
1124
1125 tso_mss = 0;
1126 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1127 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1128 req->tso_mss_min = cpu_to_le16(tso_mss);
1129
1130 tso_mss = 0;
1131 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
1132 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1133 req->tso_mss_max = cpu_to_le16(tso_mss);
1134
1135 return hclge_cmd_send(&hdev->hw, &desc, 1);
1136 }
1137
1138 static int hclge_alloc_tqps(struct hclge_dev *hdev)
1139 {
1140 struct hclge_tqp *tqp;
1141 int i;
1142
1143 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1144 sizeof(struct hclge_tqp), GFP_KERNEL);
1145 if (!hdev->htqp)
1146 return -ENOMEM;
1147
1148 tqp = hdev->htqp;
1149
1150 for (i = 0; i < hdev->num_tqps; i++) {
1151 tqp->dev = &hdev->pdev->dev;
1152 tqp->index = i;
1153
1154 tqp->q.ae_algo = &ae_algo;
1155 tqp->q.buf_size = hdev->rx_buf_len;
1156 tqp->q.desc_num = hdev->num_desc;
1157 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1158 i * HCLGE_TQP_REG_SIZE;
1159
1160 tqp++;
1161 }
1162
1163 return 0;
1164 }
1165
1166 static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1167 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1168 {
1169 struct hclge_tqp_map_cmd *req;
1170 struct hclge_desc desc;
1171 int ret;
1172
1173 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1174
1175 req = (struct hclge_tqp_map_cmd *)desc.data;
1176 req->tqp_id = cpu_to_le16(tqp_pid);
1177 req->tqp_vf = func_id;
1178 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1179 1 << HCLGE_TQP_MAP_EN_B;
1180 req->tqp_vid = cpu_to_le16(tqp_vid);
1181
1182 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1183 if (ret) {
1184 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1185 ret);
1186 return ret;
1187 }
1188
1189 return 0;
1190 }
1191
1192 static int hclge_assign_tqp(struct hclge_vport *vport,
1193 struct hnae3_queue **tqp, u16 num_tqps)
1194 {
1195 struct hclge_dev *hdev = vport->back;
1196 int i, alloced;
1197
1198 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1199 alloced < num_tqps; i++) {
1200 if (!hdev->htqp[i].alloced) {
1201 hdev->htqp[i].q.handle = &vport->nic;
1202 hdev->htqp[i].q.tqp_index = alloced;
1203 tqp[alloced] = &hdev->htqp[i].q;
1204 hdev->htqp[i].alloced = true;
1205 alloced++;
1206 }
1207 }
1208 vport->alloc_tqps = num_tqps;
1209
1210 return 0;
1211 }
1212
1213 static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1214 {
1215 struct hnae3_handle *nic = &vport->nic;
1216 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1217 struct hclge_dev *hdev = vport->back;
1218 int i, ret;
1219
1220 kinfo->num_desc = hdev->num_desc;
1221 kinfo->rx_buf_len = hdev->rx_buf_len;
1222 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1223 kinfo->rss_size
1224 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1225 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1226
1227 for (i = 0; i < HNAE3_MAX_TC; i++) {
1228 if (hdev->hw_tc_map & BIT(i)) {
1229 kinfo->tc_info[i].enable = true;
1230 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1231 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1232 kinfo->tc_info[i].tc = i;
1233 } else {
1234 /* Set to default queue if TC is disable */
1235 kinfo->tc_info[i].enable = false;
1236 kinfo->tc_info[i].tqp_offset = 0;
1237 kinfo->tc_info[i].tqp_count = 1;
1238 kinfo->tc_info[i].tc = 0;
1239 }
1240 }
1241
1242 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1243 sizeof(struct hnae3_queue *), GFP_KERNEL);
1244 if (!kinfo->tqp)
1245 return -ENOMEM;
1246
1247 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1248 if (ret) {
1249 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1250 return -EINVAL;
1251 }
1252
1253 return 0;
1254 }
1255
1256 static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1257 struct hclge_vport *vport)
1258 {
1259 struct hnae3_handle *nic = &vport->nic;
1260 struct hnae3_knic_private_info *kinfo;
1261 u16 i;
1262
1263 kinfo = &nic->kinfo;
1264 for (i = 0; i < kinfo->num_tqps; i++) {
1265 struct hclge_tqp *q =
1266 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1267 bool is_pf;
1268 int ret;
1269
1270 is_pf = !(vport->vport_id);
1271 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1272 i, is_pf);
1273 if (ret)
1274 return ret;
1275 }
1276
1277 return 0;
1278 }
1279
1280 static int hclge_map_tqp(struct hclge_dev *hdev)
1281 {
1282 struct hclge_vport *vport = hdev->vport;
1283 u16 i, num_vport;
1284
1285 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1286 for (i = 0; i < num_vport; i++) {
1287 int ret;
1288
1289 ret = hclge_map_tqp_to_vport(hdev, vport);
1290 if (ret)
1291 return ret;
1292
1293 vport++;
1294 }
1295
1296 return 0;
1297 }
1298
1299 static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1300 {
1301 /* this would be initialized later */
1302 }
1303
1304 static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1305 {
1306 struct hnae3_handle *nic = &vport->nic;
1307 struct hclge_dev *hdev = vport->back;
1308 int ret;
1309
1310 nic->pdev = hdev->pdev;
1311 nic->ae_algo = &ae_algo;
1312 nic->numa_node_mask = hdev->numa_node_mask;
1313
1314 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1315 ret = hclge_knic_setup(vport, num_tqps);
1316 if (ret) {
1317 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1318 ret);
1319 return ret;
1320 }
1321 } else {
1322 hclge_unic_setup(vport, num_tqps);
1323 }
1324
1325 return 0;
1326 }
1327
1328 static int hclge_alloc_vport(struct hclge_dev *hdev)
1329 {
1330 struct pci_dev *pdev = hdev->pdev;
1331 struct hclge_vport *vport;
1332 u32 tqp_main_vport;
1333 u32 tqp_per_vport;
1334 int num_vport, i;
1335 int ret;
1336
1337 /* We need to alloc a vport for main NIC of PF */
1338 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1339
1340 if (hdev->num_tqps < num_vport)
1341 num_vport = hdev->num_tqps;
1342
1343 /* Alloc the same number of TQPs for every vport */
1344 tqp_per_vport = hdev->num_tqps / num_vport;
1345 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1346
1347 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1348 GFP_KERNEL);
1349 if (!vport)
1350 return -ENOMEM;
1351
1352 hdev->vport = vport;
1353 hdev->num_alloc_vport = num_vport;
1354
1355 #ifdef CONFIG_PCI_IOV
1356 /* Enable SRIOV */
1357 if (hdev->num_req_vfs) {
1358 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1359 hdev->num_req_vfs);
1360 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1361 if (ret) {
1362 hdev->num_alloc_vfs = 0;
1363 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1364 ret);
1365 return ret;
1366 }
1367 }
1368 hdev->num_alloc_vfs = hdev->num_req_vfs;
1369 #endif
1370
1371 for (i = 0; i < num_vport; i++) {
1372 vport->back = hdev;
1373 vport->vport_id = i;
1374
1375 if (i == 0)
1376 ret = hclge_vport_setup(vport, tqp_main_vport);
1377 else
1378 ret = hclge_vport_setup(vport, tqp_per_vport);
1379 if (ret) {
1380 dev_err(&pdev->dev,
1381 "vport setup failed for vport %d, %d\n",
1382 i, ret);
1383 return ret;
1384 }
1385
1386 vport++;
1387 }
1388
1389 return 0;
1390 }
1391
1392 static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1393 struct hclge_pkt_buf_alloc *buf_alloc)
1394 {
1395 /* TX buffer size is unit by 128 byte */
1396 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1397 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1398 struct hclge_tx_buff_alloc_cmd *req;
1399 struct hclge_desc desc;
1400 int ret;
1401 u8 i;
1402
1403 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1404
1405 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1406 for (i = 0; i < HCLGE_TC_NUM; i++) {
1407 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
1408
1409 req->tx_pkt_buff[i] =
1410 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1411 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1412 }
1413
1414 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1415 if (ret) {
1416 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1417 ret);
1418 return ret;
1419 }
1420
1421 return 0;
1422 }
1423
1424 static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1425 struct hclge_pkt_buf_alloc *buf_alloc)
1426 {
1427 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
1428
1429 if (ret) {
1430 dev_err(&hdev->pdev->dev,
1431 "tx buffer alloc failed %d\n", ret);
1432 return ret;
1433 }
1434
1435 return 0;
1436 }
1437
1438 static int hclge_get_tc_num(struct hclge_dev *hdev)
1439 {
1440 int i, cnt = 0;
1441
1442 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1443 if (hdev->hw_tc_map & BIT(i))
1444 cnt++;
1445 return cnt;
1446 }
1447
1448 static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1449 {
1450 int i, cnt = 0;
1451
1452 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1453 if (hdev->hw_tc_map & BIT(i) &&
1454 hdev->tm_info.hw_pfc_map & BIT(i))
1455 cnt++;
1456 return cnt;
1457 }
1458
1459 /* Get the number of pfc enabled TCs, which have private buffer */
1460 static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1461 struct hclge_pkt_buf_alloc *buf_alloc)
1462 {
1463 struct hclge_priv_buf *priv;
1464 int i, cnt = 0;
1465
1466 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1467 priv = &buf_alloc->priv_buf[i];
1468 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1469 priv->enable)
1470 cnt++;
1471 }
1472
1473 return cnt;
1474 }
1475
1476 /* Get the number of pfc disabled TCs, which have private buffer */
1477 static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1478 struct hclge_pkt_buf_alloc *buf_alloc)
1479 {
1480 struct hclge_priv_buf *priv;
1481 int i, cnt = 0;
1482
1483 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1484 priv = &buf_alloc->priv_buf[i];
1485 if (hdev->hw_tc_map & BIT(i) &&
1486 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1487 priv->enable)
1488 cnt++;
1489 }
1490
1491 return cnt;
1492 }
1493
1494 static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1495 {
1496 struct hclge_priv_buf *priv;
1497 u32 rx_priv = 0;
1498 int i;
1499
1500 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1501 priv = &buf_alloc->priv_buf[i];
1502 if (priv->enable)
1503 rx_priv += priv->buf_size;
1504 }
1505 return rx_priv;
1506 }
1507
1508 static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
1509 {
1510 u32 i, total_tx_size = 0;
1511
1512 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1513 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
1514
1515 return total_tx_size;
1516 }
1517
1518 static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1519 struct hclge_pkt_buf_alloc *buf_alloc,
1520 u32 rx_all)
1521 {
1522 u32 shared_buf_min, shared_buf_tc, shared_std;
1523 int tc_num, pfc_enable_num;
1524 u32 shared_buf;
1525 u32 rx_priv;
1526 int i;
1527
1528 tc_num = hclge_get_tc_num(hdev);
1529 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1530
1531 if (hnae3_dev_dcb_supported(hdev))
1532 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1533 else
1534 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1535
1536 shared_buf_tc = pfc_enable_num * hdev->mps +
1537 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1538 hdev->mps;
1539 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1540
1541 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
1542 if (rx_all <= rx_priv + shared_std)
1543 return false;
1544
1545 shared_buf = rx_all - rx_priv;
1546 buf_alloc->s_buf.buf_size = shared_buf;
1547 buf_alloc->s_buf.self.high = shared_buf;
1548 buf_alloc->s_buf.self.low = 2 * hdev->mps;
1549
1550 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1551 if ((hdev->hw_tc_map & BIT(i)) &&
1552 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1553 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1554 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1555 } else {
1556 buf_alloc->s_buf.tc_thrd[i].low = 0;
1557 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
1558 }
1559 }
1560
1561 return true;
1562 }
1563
1564 static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1565 struct hclge_pkt_buf_alloc *buf_alloc)
1566 {
1567 u32 i, total_size;
1568
1569 total_size = hdev->pkt_buf_size;
1570
1571 /* alloc tx buffer for all enabled tc */
1572 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1573 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1574
1575 if (total_size < HCLGE_DEFAULT_TX_BUF)
1576 return -ENOMEM;
1577
1578 if (hdev->hw_tc_map & BIT(i))
1579 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1580 else
1581 priv->tx_buf_size = 0;
1582
1583 total_size -= priv->tx_buf_size;
1584 }
1585
1586 return 0;
1587 }
1588
1589 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1590 * @hdev: pointer to struct hclge_dev
1591 * @buf_alloc: pointer to buffer calculation data
1592 * @return: 0: calculate sucessful, negative: fail
1593 */
1594 static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1595 struct hclge_pkt_buf_alloc *buf_alloc)
1596 {
1597 u32 rx_all = hdev->pkt_buf_size;
1598 int no_pfc_priv_num, pfc_priv_num;
1599 struct hclge_priv_buf *priv;
1600 int i;
1601
1602 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
1603
1604 /* When DCB is not supported, rx private
1605 * buffer is not allocated.
1606 */
1607 if (!hnae3_dev_dcb_supported(hdev)) {
1608 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1609 return -ENOMEM;
1610
1611 return 0;
1612 }
1613
1614 /* step 1, try to alloc private buffer for all enabled tc */
1615 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1616 priv = &buf_alloc->priv_buf[i];
1617 if (hdev->hw_tc_map & BIT(i)) {
1618 priv->enable = 1;
1619 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1620 priv->wl.low = hdev->mps;
1621 priv->wl.high = priv->wl.low + hdev->mps;
1622 priv->buf_size = priv->wl.high +
1623 HCLGE_DEFAULT_DV;
1624 } else {
1625 priv->wl.low = 0;
1626 priv->wl.high = 2 * hdev->mps;
1627 priv->buf_size = priv->wl.high;
1628 }
1629 } else {
1630 priv->enable = 0;
1631 priv->wl.low = 0;
1632 priv->wl.high = 0;
1633 priv->buf_size = 0;
1634 }
1635 }
1636
1637 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1638 return 0;
1639
1640 /* step 2, try to decrease the buffer size of
1641 * no pfc TC's private buffer
1642 */
1643 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1644 priv = &buf_alloc->priv_buf[i];
1645
1646 priv->enable = 0;
1647 priv->wl.low = 0;
1648 priv->wl.high = 0;
1649 priv->buf_size = 0;
1650
1651 if (!(hdev->hw_tc_map & BIT(i)))
1652 continue;
1653
1654 priv->enable = 1;
1655
1656 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1657 priv->wl.low = 128;
1658 priv->wl.high = priv->wl.low + hdev->mps;
1659 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1660 } else {
1661 priv->wl.low = 0;
1662 priv->wl.high = hdev->mps;
1663 priv->buf_size = priv->wl.high;
1664 }
1665 }
1666
1667 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1668 return 0;
1669
1670 /* step 3, try to reduce the number of pfc disabled TCs,
1671 * which have private buffer
1672 */
1673 /* get the total no pfc enable TC number, which have private buffer */
1674 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
1675
1676 /* let the last to be cleared first */
1677 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1678 priv = &buf_alloc->priv_buf[i];
1679
1680 if (hdev->hw_tc_map & BIT(i) &&
1681 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1682 /* Clear the no pfc TC private buffer */
1683 priv->wl.low = 0;
1684 priv->wl.high = 0;
1685 priv->buf_size = 0;
1686 priv->enable = 0;
1687 no_pfc_priv_num--;
1688 }
1689
1690 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1691 no_pfc_priv_num == 0)
1692 break;
1693 }
1694
1695 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1696 return 0;
1697
1698 /* step 4, try to reduce the number of pfc enabled TCs
1699 * which have private buffer.
1700 */
1701 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
1702
1703 /* let the last to be cleared first */
1704 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1705 priv = &buf_alloc->priv_buf[i];
1706
1707 if (hdev->hw_tc_map & BIT(i) &&
1708 hdev->tm_info.hw_pfc_map & BIT(i)) {
1709 /* Reduce the number of pfc TC with private buffer */
1710 priv->wl.low = 0;
1711 priv->enable = 0;
1712 priv->wl.high = 0;
1713 priv->buf_size = 0;
1714 pfc_priv_num--;
1715 }
1716
1717 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
1718 pfc_priv_num == 0)
1719 break;
1720 }
1721 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
1722 return 0;
1723
1724 return -ENOMEM;
1725 }
1726
1727 static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1728 struct hclge_pkt_buf_alloc *buf_alloc)
1729 {
1730 struct hclge_rx_priv_buff_cmd *req;
1731 struct hclge_desc desc;
1732 int ret;
1733 int i;
1734
1735 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1736 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
1737
1738 /* Alloc private buffer TCs */
1739 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1740 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
1741
1742 req->buf_num[i] =
1743 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1744 req->buf_num[i] |=
1745 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
1746 }
1747
1748 req->shared_buf =
1749 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
1750 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1751
1752 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1753 if (ret) {
1754 dev_err(&hdev->pdev->dev,
1755 "rx private buffer alloc cmd failed %d\n", ret);
1756 return ret;
1757 }
1758
1759 return 0;
1760 }
1761
1762 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1763
1764 static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1765 struct hclge_pkt_buf_alloc *buf_alloc)
1766 {
1767 struct hclge_rx_priv_wl_buf *req;
1768 struct hclge_priv_buf *priv;
1769 struct hclge_desc desc[2];
1770 int i, j;
1771 int ret;
1772
1773 for (i = 0; i < 2; i++) {
1774 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1775 false);
1776 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1777
1778 /* The first descriptor set the NEXT bit to 1 */
1779 if (i == 0)
1780 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1781 else
1782 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1783
1784 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1785 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1786
1787 priv = &buf_alloc->priv_buf[idx];
1788 req->tc_wl[j].high =
1789 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1790 req->tc_wl[j].high |=
1791 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1792 HCLGE_RX_PRIV_EN_B);
1793 req->tc_wl[j].low =
1794 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1795 req->tc_wl[j].low |=
1796 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1797 HCLGE_RX_PRIV_EN_B);
1798 }
1799 }
1800
1801 /* Send 2 descriptor at one time */
1802 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1803 if (ret) {
1804 dev_err(&hdev->pdev->dev,
1805 "rx private waterline config cmd failed %d\n",
1806 ret);
1807 return ret;
1808 }
1809 return 0;
1810 }
1811
1812 static int hclge_common_thrd_config(struct hclge_dev *hdev,
1813 struct hclge_pkt_buf_alloc *buf_alloc)
1814 {
1815 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
1816 struct hclge_rx_com_thrd *req;
1817 struct hclge_desc desc[2];
1818 struct hclge_tc_thrd *tc;
1819 int i, j;
1820 int ret;
1821
1822 for (i = 0; i < 2; i++) {
1823 hclge_cmd_setup_basic_desc(&desc[i],
1824 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1825 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1826
1827 /* The first descriptor set the NEXT bit to 1 */
1828 if (i == 0)
1829 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1830 else
1831 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1832
1833 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1834 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1835
1836 req->com_thrd[j].high =
1837 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1838 req->com_thrd[j].high |=
1839 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1840 HCLGE_RX_PRIV_EN_B);
1841 req->com_thrd[j].low =
1842 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1843 req->com_thrd[j].low |=
1844 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1845 HCLGE_RX_PRIV_EN_B);
1846 }
1847 }
1848
1849 /* Send 2 descriptors at one time */
1850 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1851 if (ret) {
1852 dev_err(&hdev->pdev->dev,
1853 "common threshold config cmd failed %d\n", ret);
1854 return ret;
1855 }
1856 return 0;
1857 }
1858
1859 static int hclge_common_wl_config(struct hclge_dev *hdev,
1860 struct hclge_pkt_buf_alloc *buf_alloc)
1861 {
1862 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
1863 struct hclge_rx_com_wl *req;
1864 struct hclge_desc desc;
1865 int ret;
1866
1867 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1868
1869 req = (struct hclge_rx_com_wl *)desc.data;
1870 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1871 req->com_wl.high |=
1872 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1873 HCLGE_RX_PRIV_EN_B);
1874
1875 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1876 req->com_wl.low |=
1877 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1878 HCLGE_RX_PRIV_EN_B);
1879
1880 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1881 if (ret) {
1882 dev_err(&hdev->pdev->dev,
1883 "common waterline config cmd failed %d\n", ret);
1884 return ret;
1885 }
1886
1887 return 0;
1888 }
1889
1890 int hclge_buffer_alloc(struct hclge_dev *hdev)
1891 {
1892 struct hclge_pkt_buf_alloc *pkt_buf;
1893 int ret;
1894
1895 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1896 if (!pkt_buf)
1897 return -ENOMEM;
1898
1899 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
1900 if (ret) {
1901 dev_err(&hdev->pdev->dev,
1902 "could not calc tx buffer size for all TCs %d\n", ret);
1903 goto out;
1904 }
1905
1906 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
1907 if (ret) {
1908 dev_err(&hdev->pdev->dev,
1909 "could not alloc tx buffers %d\n", ret);
1910 goto out;
1911 }
1912
1913 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
1914 if (ret) {
1915 dev_err(&hdev->pdev->dev,
1916 "could not calc rx priv buffer size for all TCs %d\n",
1917 ret);
1918 goto out;
1919 }
1920
1921 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
1922 if (ret) {
1923 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1924 ret);
1925 goto out;
1926 }
1927
1928 if (hnae3_dev_dcb_supported(hdev)) {
1929 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
1930 if (ret) {
1931 dev_err(&hdev->pdev->dev,
1932 "could not configure rx private waterline %d\n",
1933 ret);
1934 goto out;
1935 }
1936
1937 ret = hclge_common_thrd_config(hdev, pkt_buf);
1938 if (ret) {
1939 dev_err(&hdev->pdev->dev,
1940 "could not configure common threshold %d\n",
1941 ret);
1942 goto out;
1943 }
1944 }
1945
1946 ret = hclge_common_wl_config(hdev, pkt_buf);
1947 if (ret)
1948 dev_err(&hdev->pdev->dev,
1949 "could not configure common waterline %d\n", ret);
1950
1951 out:
1952 kfree(pkt_buf);
1953 return ret;
1954 }
1955
1956 static int hclge_init_roce_base_info(struct hclge_vport *vport)
1957 {
1958 struct hnae3_handle *roce = &vport->roce;
1959 struct hnae3_handle *nic = &vport->nic;
1960
1961 roce->rinfo.num_vectors = vport->back->num_roce_msi;
1962
1963 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1964 vport->back->num_msi_left == 0)
1965 return -EINVAL;
1966
1967 roce->rinfo.base_vector = vport->back->roce_base_vector;
1968
1969 roce->rinfo.netdev = nic->kinfo.netdev;
1970 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1971
1972 roce->pdev = nic->pdev;
1973 roce->ae_algo = nic->ae_algo;
1974 roce->numa_node_mask = nic->numa_node_mask;
1975
1976 return 0;
1977 }
1978
1979 static int hclge_init_msi(struct hclge_dev *hdev)
1980 {
1981 struct pci_dev *pdev = hdev->pdev;
1982 int vectors;
1983 int i;
1984
1985 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1986 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1987 if (vectors < 0) {
1988 dev_err(&pdev->dev,
1989 "failed(%d) to allocate MSI/MSI-X vectors\n",
1990 vectors);
1991 return vectors;
1992 }
1993 if (vectors < hdev->num_msi)
1994 dev_warn(&hdev->pdev->dev,
1995 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1996 hdev->num_msi, vectors);
1997
1998 hdev->num_msi = vectors;
1999 hdev->num_msi_left = vectors;
2000 hdev->base_msi_vector = pdev->irq;
2001 hdev->roce_base_vector = hdev->base_msi_vector +
2002 HCLGE_ROCE_VECTOR_OFFSET;
2003
2004 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
2005 sizeof(u16), GFP_KERNEL);
2006 if (!hdev->vector_status) {
2007 pci_free_irq_vectors(pdev);
2008 return -ENOMEM;
2009 }
2010
2011 for (i = 0; i < hdev->num_msi; i++)
2012 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2013
2014 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2015 sizeof(int), GFP_KERNEL);
2016 if (!hdev->vector_irq) {
2017 pci_free_irq_vectors(pdev);
2018 return -ENOMEM;
2019 }
2020
2021 return 0;
2022 }
2023
2024 static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2025 {
2026 struct hclge_mac *mac = &hdev->hw.mac;
2027
2028 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2029 mac->duplex = (u8)duplex;
2030 else
2031 mac->duplex = HCLGE_MAC_FULL;
2032
2033 mac->speed = speed;
2034 }
2035
2036 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2037 {
2038 struct hclge_config_mac_speed_dup_cmd *req;
2039 struct hclge_desc desc;
2040 int ret;
2041
2042 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
2043
2044 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2045
2046 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2047
2048 switch (speed) {
2049 case HCLGE_MAC_SPEED_10M:
2050 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2051 HCLGE_CFG_SPEED_S, 6);
2052 break;
2053 case HCLGE_MAC_SPEED_100M:
2054 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2055 HCLGE_CFG_SPEED_S, 7);
2056 break;
2057 case HCLGE_MAC_SPEED_1G:
2058 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2059 HCLGE_CFG_SPEED_S, 0);
2060 break;
2061 case HCLGE_MAC_SPEED_10G:
2062 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2063 HCLGE_CFG_SPEED_S, 1);
2064 break;
2065 case HCLGE_MAC_SPEED_25G:
2066 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2067 HCLGE_CFG_SPEED_S, 2);
2068 break;
2069 case HCLGE_MAC_SPEED_40G:
2070 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2071 HCLGE_CFG_SPEED_S, 3);
2072 break;
2073 case HCLGE_MAC_SPEED_50G:
2074 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2075 HCLGE_CFG_SPEED_S, 4);
2076 break;
2077 case HCLGE_MAC_SPEED_100G:
2078 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2079 HCLGE_CFG_SPEED_S, 5);
2080 break;
2081 default:
2082 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
2083 return -EINVAL;
2084 }
2085
2086 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2087 1);
2088
2089 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2090 if (ret) {
2091 dev_err(&hdev->pdev->dev,
2092 "mac speed/duplex config cmd failed %d.\n", ret);
2093 return ret;
2094 }
2095
2096 hclge_check_speed_dup(hdev, duplex, speed);
2097
2098 return 0;
2099 }
2100
2101 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2102 u8 duplex)
2103 {
2104 struct hclge_vport *vport = hclge_get_vport(handle);
2105 struct hclge_dev *hdev = vport->back;
2106
2107 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2108 }
2109
2110 static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2111 u8 *duplex)
2112 {
2113 struct hclge_query_an_speed_dup_cmd *req;
2114 struct hclge_desc desc;
2115 int speed_tmp;
2116 int ret;
2117
2118 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
2119
2120 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2121 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2122 if (ret) {
2123 dev_err(&hdev->pdev->dev,
2124 "mac speed/autoneg/duplex query cmd failed %d\n",
2125 ret);
2126 return ret;
2127 }
2128
2129 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2130 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2131 HCLGE_QUERY_SPEED_S);
2132
2133 ret = hclge_parse_speed(speed_tmp, speed);
2134 if (ret) {
2135 dev_err(&hdev->pdev->dev,
2136 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2137 return -EIO;
2138 }
2139
2140 return 0;
2141 }
2142
2143 static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2144 {
2145 struct hclge_config_auto_neg_cmd *req;
2146 struct hclge_desc desc;
2147 u32 flag = 0;
2148 int ret;
2149
2150 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2151
2152 req = (struct hclge_config_auto_neg_cmd *)desc.data;
2153 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2154 req->cfg_an_cmd_flag = cpu_to_le32(flag);
2155
2156 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2157 if (ret) {
2158 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2159 ret);
2160 return ret;
2161 }
2162
2163 return 0;
2164 }
2165
2166 static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2167 {
2168 struct hclge_vport *vport = hclge_get_vport(handle);
2169 struct hclge_dev *hdev = vport->back;
2170
2171 return hclge_set_autoneg_en(hdev, enable);
2172 }
2173
2174 static int hclge_get_autoneg(struct hnae3_handle *handle)
2175 {
2176 struct hclge_vport *vport = hclge_get_vport(handle);
2177 struct hclge_dev *hdev = vport->back;
2178 struct phy_device *phydev = hdev->hw.mac.phydev;
2179
2180 if (phydev)
2181 return phydev->autoneg;
2182
2183 return hdev->hw.mac.autoneg;
2184 }
2185
2186 static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
2187 bool mask_vlan,
2188 u8 *mac_mask)
2189 {
2190 struct hclge_mac_vlan_mask_entry_cmd *req;
2191 struct hclge_desc desc;
2192 int status;
2193
2194 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
2195 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
2196
2197 hnae_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
2198 mask_vlan ? 1 : 0);
2199 ether_addr_copy(req->mac_mask, mac_mask);
2200
2201 status = hclge_cmd_send(&hdev->hw, &desc, 1);
2202 if (status)
2203 dev_err(&hdev->pdev->dev,
2204 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2205 status);
2206
2207 return status;
2208 }
2209
2210 static int hclge_mac_init(struct hclge_dev *hdev)
2211 {
2212 struct hnae3_handle *handle = &hdev->vport[0].nic;
2213 struct net_device *netdev = handle->kinfo.netdev;
2214 struct hclge_mac *mac = &hdev->hw.mac;
2215 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2216 int mtu;
2217 int ret;
2218
2219 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2220 if (ret) {
2221 dev_err(&hdev->pdev->dev,
2222 "Config mac speed dup fail ret=%d\n", ret);
2223 return ret;
2224 }
2225
2226 mac->link = 0;
2227
2228 /* Initialize the MTA table work mode */
2229 hdev->accept_mta_mc = true;
2230 hdev->enable_mta = true;
2231 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2232
2233 ret = hclge_set_mta_filter_mode(hdev,
2234 hdev->mta_mac_sel_type,
2235 hdev->enable_mta);
2236 if (ret) {
2237 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2238 ret);
2239 return ret;
2240 }
2241
2242 ret = hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2243 if (ret) {
2244 dev_err(&hdev->pdev->dev,
2245 "set mta filter mode fail ret=%d\n", ret);
2246 return ret;
2247 }
2248
2249 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
2250 if (ret) {
2251 dev_err(&hdev->pdev->dev,
2252 "set default mac_vlan_mask fail ret=%d\n", ret);
2253 return ret;
2254 }
2255
2256 if (netdev)
2257 mtu = netdev->mtu;
2258 else
2259 mtu = ETH_DATA_LEN;
2260
2261 ret = hclge_set_mtu(handle, mtu);
2262 if (ret) {
2263 dev_err(&hdev->pdev->dev,
2264 "set mtu failed ret=%d\n", ret);
2265 return ret;
2266 }
2267
2268 return 0;
2269 }
2270
2271 static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2272 {
2273 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2274 schedule_work(&hdev->mbx_service_task);
2275 }
2276
2277 static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2278 {
2279 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2280 schedule_work(&hdev->rst_service_task);
2281 }
2282
2283 static void hclge_task_schedule(struct hclge_dev *hdev)
2284 {
2285 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2286 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2287 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2288 (void)schedule_work(&hdev->service_task);
2289 }
2290
2291 static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2292 {
2293 struct hclge_link_status_cmd *req;
2294 struct hclge_desc desc;
2295 int link_status;
2296 int ret;
2297
2298 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2299 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2300 if (ret) {
2301 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2302 ret);
2303 return ret;
2304 }
2305
2306 req = (struct hclge_link_status_cmd *)desc.data;
2307 link_status = req->status & HCLGE_LINK_STATUS;
2308
2309 return !!link_status;
2310 }
2311
2312 static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2313 {
2314 int mac_state;
2315 int link_stat;
2316
2317 mac_state = hclge_get_mac_link_status(hdev);
2318
2319 if (hdev->hw.mac.phydev) {
2320 if (!genphy_read_status(hdev->hw.mac.phydev))
2321 link_stat = mac_state &
2322 hdev->hw.mac.phydev->link;
2323 else
2324 link_stat = 0;
2325
2326 } else {
2327 link_stat = mac_state;
2328 }
2329
2330 return !!link_stat;
2331 }
2332
2333 static void hclge_update_link_status(struct hclge_dev *hdev)
2334 {
2335 struct hnae3_client *client = hdev->nic_client;
2336 struct hnae3_handle *handle;
2337 int state;
2338 int i;
2339
2340 if (!client)
2341 return;
2342 state = hclge_get_mac_phy_link(hdev);
2343 if (state != hdev->hw.mac.link) {
2344 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2345 handle = &hdev->vport[i].nic;
2346 client->ops->link_status_change(handle, state);
2347 }
2348 hdev->hw.mac.link = state;
2349 }
2350 }
2351
2352 static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2353 {
2354 struct hclge_mac mac = hdev->hw.mac;
2355 u8 duplex;
2356 int speed;
2357 int ret;
2358
2359 /* get the speed and duplex as autoneg'result from mac cmd when phy
2360 * doesn't exit.
2361 */
2362 if (mac.phydev || !mac.autoneg)
2363 return 0;
2364
2365 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2366 if (ret) {
2367 dev_err(&hdev->pdev->dev,
2368 "mac autoneg/speed/duplex query failed %d\n", ret);
2369 return ret;
2370 }
2371
2372 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2373 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2374 if (ret) {
2375 dev_err(&hdev->pdev->dev,
2376 "mac speed/duplex config failed %d\n", ret);
2377 return ret;
2378 }
2379 }
2380
2381 return 0;
2382 }
2383
2384 static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2385 {
2386 struct hclge_vport *vport = hclge_get_vport(handle);
2387 struct hclge_dev *hdev = vport->back;
2388
2389 return hclge_update_speed_duplex(hdev);
2390 }
2391
2392 static int hclge_get_status(struct hnae3_handle *handle)
2393 {
2394 struct hclge_vport *vport = hclge_get_vport(handle);
2395 struct hclge_dev *hdev = vport->back;
2396
2397 hclge_update_link_status(hdev);
2398
2399 return hdev->hw.mac.link;
2400 }
2401
2402 static void hclge_service_timer(struct timer_list *t)
2403 {
2404 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
2405
2406 mod_timer(&hdev->service_timer, jiffies + HZ);
2407 hdev->hw_stats.stats_timer++;
2408 hclge_task_schedule(hdev);
2409 }
2410
2411 static void hclge_service_complete(struct hclge_dev *hdev)
2412 {
2413 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2414
2415 /* Flush memory before next watchdog */
2416 smp_mb__before_atomic();
2417 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2418 }
2419
2420 static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2421 {
2422 u32 rst_src_reg;
2423 u32 cmdq_src_reg;
2424
2425 /* fetch the events from their corresponding regs */
2426 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2427 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2428
2429 /* Assumption: If by any chance reset and mailbox events are reported
2430 * together then we will only process reset event in this go and will
2431 * defer the processing of the mailbox events. Since, we would have not
2432 * cleared RX CMDQ event this time we would receive again another
2433 * interrupt from H/W just for the mailbox.
2434 */
2435
2436 /* check for vector0 reset event sources */
2437 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2438 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2439 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2440 return HCLGE_VECTOR0_EVENT_RST;
2441 }
2442
2443 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2444 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2445 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2446 return HCLGE_VECTOR0_EVENT_RST;
2447 }
2448
2449 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2450 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2451 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2452 return HCLGE_VECTOR0_EVENT_RST;
2453 }
2454
2455 /* check for vector0 mailbox(=CMDQ RX) event source */
2456 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2457 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2458 *clearval = cmdq_src_reg;
2459 return HCLGE_VECTOR0_EVENT_MBX;
2460 }
2461
2462 return HCLGE_VECTOR0_EVENT_OTHER;
2463 }
2464
2465 static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2466 u32 regclr)
2467 {
2468 switch (event_type) {
2469 case HCLGE_VECTOR0_EVENT_RST:
2470 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2471 break;
2472 case HCLGE_VECTOR0_EVENT_MBX:
2473 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2474 break;
2475 }
2476 }
2477
2478 static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2479 {
2480 writel(enable ? 1 : 0, vector->addr);
2481 }
2482
2483 static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2484 {
2485 struct hclge_dev *hdev = data;
2486 u32 event_cause;
2487 u32 clearval;
2488
2489 hclge_enable_vector(&hdev->misc_vector, false);
2490 event_cause = hclge_check_event_cause(hdev, &clearval);
2491
2492 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2493 switch (event_cause) {
2494 case HCLGE_VECTOR0_EVENT_RST:
2495 hclge_reset_task_schedule(hdev);
2496 break;
2497 case HCLGE_VECTOR0_EVENT_MBX:
2498 /* If we are here then,
2499 * 1. Either we are not handling any mbx task and we are not
2500 * scheduled as well
2501 * OR
2502 * 2. We could be handling a mbx task but nothing more is
2503 * scheduled.
2504 * In both cases, we should schedule mbx task as there are more
2505 * mbx messages reported by this interrupt.
2506 */
2507 hclge_mbx_task_schedule(hdev);
2508
2509 default:
2510 dev_dbg(&hdev->pdev->dev,
2511 "received unknown or unhandled event of vector0\n");
2512 break;
2513 }
2514
2515 /* we should clear the source of interrupt */
2516 hclge_clear_event_cause(hdev, event_cause, clearval);
2517 hclge_enable_vector(&hdev->misc_vector, true);
2518
2519 return IRQ_HANDLED;
2520 }
2521
2522 static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2523 {
2524 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2525 hdev->num_msi_left += 1;
2526 hdev->num_msi_used -= 1;
2527 }
2528
2529 static void hclge_get_misc_vector(struct hclge_dev *hdev)
2530 {
2531 struct hclge_misc_vector *vector = &hdev->misc_vector;
2532
2533 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2534
2535 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2536 hdev->vector_status[0] = 0;
2537
2538 hdev->num_msi_left -= 1;
2539 hdev->num_msi_used += 1;
2540 }
2541
2542 static int hclge_misc_irq_init(struct hclge_dev *hdev)
2543 {
2544 int ret;
2545
2546 hclge_get_misc_vector(hdev);
2547
2548 /* this would be explicitly freed in the end */
2549 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2550 0, "hclge_misc", hdev);
2551 if (ret) {
2552 hclge_free_vector(hdev, 0);
2553 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2554 hdev->misc_vector.vector_irq);
2555 }
2556
2557 return ret;
2558 }
2559
2560 static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2561 {
2562 free_irq(hdev->misc_vector.vector_irq, hdev);
2563 hclge_free_vector(hdev, 0);
2564 }
2565
2566 static int hclge_notify_client(struct hclge_dev *hdev,
2567 enum hnae3_reset_notify_type type)
2568 {
2569 struct hnae3_client *client = hdev->nic_client;
2570 u16 i;
2571
2572 if (!client->ops->reset_notify)
2573 return -EOPNOTSUPP;
2574
2575 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2576 struct hnae3_handle *handle = &hdev->vport[i].nic;
2577 int ret;
2578
2579 ret = client->ops->reset_notify(handle, type);
2580 if (ret)
2581 return ret;
2582 }
2583
2584 return 0;
2585 }
2586
2587 static int hclge_reset_wait(struct hclge_dev *hdev)
2588 {
2589 #define HCLGE_RESET_WATI_MS 100
2590 #define HCLGE_RESET_WAIT_CNT 5
2591 u32 val, reg, reg_bit;
2592 u32 cnt = 0;
2593
2594 switch (hdev->reset_type) {
2595 case HNAE3_GLOBAL_RESET:
2596 reg = HCLGE_GLOBAL_RESET_REG;
2597 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2598 break;
2599 case HNAE3_CORE_RESET:
2600 reg = HCLGE_GLOBAL_RESET_REG;
2601 reg_bit = HCLGE_CORE_RESET_BIT;
2602 break;
2603 case HNAE3_FUNC_RESET:
2604 reg = HCLGE_FUN_RST_ING;
2605 reg_bit = HCLGE_FUN_RST_ING_B;
2606 break;
2607 default:
2608 dev_err(&hdev->pdev->dev,
2609 "Wait for unsupported reset type: %d\n",
2610 hdev->reset_type);
2611 return -EINVAL;
2612 }
2613
2614 val = hclge_read_dev(&hdev->hw, reg);
2615 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2616 msleep(HCLGE_RESET_WATI_MS);
2617 val = hclge_read_dev(&hdev->hw, reg);
2618 cnt++;
2619 }
2620
2621 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2622 dev_warn(&hdev->pdev->dev,
2623 "Wait for reset timeout: %d\n", hdev->reset_type);
2624 return -EBUSY;
2625 }
2626
2627 return 0;
2628 }
2629
2630 static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2631 {
2632 struct hclge_desc desc;
2633 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2634 int ret;
2635
2636 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2637 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2638 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2639 req->fun_reset_vfid = func_id;
2640
2641 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2642 if (ret)
2643 dev_err(&hdev->pdev->dev,
2644 "send function reset cmd fail, status =%d\n", ret);
2645
2646 return ret;
2647 }
2648
2649 static void hclge_do_reset(struct hclge_dev *hdev)
2650 {
2651 struct pci_dev *pdev = hdev->pdev;
2652 u32 val;
2653
2654 switch (hdev->reset_type) {
2655 case HNAE3_GLOBAL_RESET:
2656 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2657 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2658 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2659 dev_info(&pdev->dev, "Global Reset requested\n");
2660 break;
2661 case HNAE3_CORE_RESET:
2662 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2663 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2664 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2665 dev_info(&pdev->dev, "Core Reset requested\n");
2666 break;
2667 case HNAE3_FUNC_RESET:
2668 dev_info(&pdev->dev, "PF Reset requested\n");
2669 hclge_func_reset_cmd(hdev, 0);
2670 /* schedule again to check later */
2671 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2672 hclge_reset_task_schedule(hdev);
2673 break;
2674 default:
2675 dev_warn(&pdev->dev,
2676 "Unsupported reset type: %d\n", hdev->reset_type);
2677 break;
2678 }
2679 }
2680
2681 static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2682 unsigned long *addr)
2683 {
2684 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2685
2686 /* return the highest priority reset level amongst all */
2687 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2688 rst_level = HNAE3_GLOBAL_RESET;
2689 else if (test_bit(HNAE3_CORE_RESET, addr))
2690 rst_level = HNAE3_CORE_RESET;
2691 else if (test_bit(HNAE3_IMP_RESET, addr))
2692 rst_level = HNAE3_IMP_RESET;
2693 else if (test_bit(HNAE3_FUNC_RESET, addr))
2694 rst_level = HNAE3_FUNC_RESET;
2695
2696 /* now, clear all other resets */
2697 clear_bit(HNAE3_GLOBAL_RESET, addr);
2698 clear_bit(HNAE3_CORE_RESET, addr);
2699 clear_bit(HNAE3_IMP_RESET, addr);
2700 clear_bit(HNAE3_FUNC_RESET, addr);
2701
2702 return rst_level;
2703 }
2704
2705 static void hclge_reset(struct hclge_dev *hdev)
2706 {
2707 /* perform reset of the stack & ae device for a client */
2708
2709 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2710
2711 if (!hclge_reset_wait(hdev)) {
2712 rtnl_lock();
2713 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2714 hclge_reset_ae_dev(hdev->ae_dev);
2715 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2716 rtnl_unlock();
2717 } else {
2718 /* schedule again to check pending resets later */
2719 set_bit(hdev->reset_type, &hdev->reset_pending);
2720 hclge_reset_task_schedule(hdev);
2721 }
2722
2723 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2724 }
2725
2726 static void hclge_reset_event(struct hnae3_handle *handle,
2727 enum hnae3_reset_type reset)
2728 {
2729 struct hclge_vport *vport = hclge_get_vport(handle);
2730 struct hclge_dev *hdev = vport->back;
2731
2732 dev_info(&hdev->pdev->dev,
2733 "Receive reset event , reset_type is %d", reset);
2734
2735 switch (reset) {
2736 case HNAE3_FUNC_RESET:
2737 case HNAE3_CORE_RESET:
2738 case HNAE3_GLOBAL_RESET:
2739 /* request reset & schedule reset task */
2740 set_bit(reset, &hdev->reset_request);
2741 hclge_reset_task_schedule(hdev);
2742 break;
2743 default:
2744 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2745 break;
2746 }
2747 }
2748
2749 static void hclge_reset_subtask(struct hclge_dev *hdev)
2750 {
2751 /* check if there is any ongoing reset in the hardware. This status can
2752 * be checked from reset_pending. If there is then, we need to wait for
2753 * hardware to complete reset.
2754 * a. If we are able to figure out in reasonable time that hardware
2755 * has fully resetted then, we can proceed with driver, client
2756 * reset.
2757 * b. else, we can come back later to check this status so re-sched
2758 * now.
2759 */
2760 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2761 if (hdev->reset_type != HNAE3_NONE_RESET)
2762 hclge_reset(hdev);
2763
2764 /* check if we got any *new* reset requests to be honored */
2765 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2766 if (hdev->reset_type != HNAE3_NONE_RESET)
2767 hclge_do_reset(hdev);
2768
2769 hdev->reset_type = HNAE3_NONE_RESET;
2770 }
2771
2772 static void hclge_reset_service_task(struct work_struct *work)
2773 {
2774 struct hclge_dev *hdev =
2775 container_of(work, struct hclge_dev, rst_service_task);
2776
2777 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2778 return;
2779
2780 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2781
2782 hclge_reset_subtask(hdev);
2783
2784 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
2785 }
2786
2787 static void hclge_mailbox_service_task(struct work_struct *work)
2788 {
2789 struct hclge_dev *hdev =
2790 container_of(work, struct hclge_dev, mbx_service_task);
2791
2792 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2793 return;
2794
2795 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2796
2797 hclge_mbx_handler(hdev);
2798
2799 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2800 }
2801
2802 static void hclge_service_task(struct work_struct *work)
2803 {
2804 struct hclge_dev *hdev =
2805 container_of(work, struct hclge_dev, service_task);
2806
2807 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2808 hclge_update_stats_for_all(hdev);
2809 hdev->hw_stats.stats_timer = 0;
2810 }
2811
2812 hclge_update_speed_duplex(hdev);
2813 hclge_update_link_status(hdev);
2814 hclge_service_complete(hdev);
2815 }
2816
2817 static void hclge_disable_sriov(struct hclge_dev *hdev)
2818 {
2819 /* If our VFs are assigned we cannot shut down SR-IOV
2820 * without causing issues, so just leave the hardware
2821 * available but disabled
2822 */
2823 if (pci_vfs_assigned(hdev->pdev)) {
2824 dev_warn(&hdev->pdev->dev,
2825 "disabling driver while VFs are assigned\n");
2826 return;
2827 }
2828
2829 pci_disable_sriov(hdev->pdev);
2830 }
2831
2832 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2833 {
2834 /* VF handle has no client */
2835 if (!handle->client)
2836 return container_of(handle, struct hclge_vport, nic);
2837 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2838 return container_of(handle, struct hclge_vport, roce);
2839 else
2840 return container_of(handle, struct hclge_vport, nic);
2841 }
2842
2843 static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2844 struct hnae3_vector_info *vector_info)
2845 {
2846 struct hclge_vport *vport = hclge_get_vport(handle);
2847 struct hnae3_vector_info *vector = vector_info;
2848 struct hclge_dev *hdev = vport->back;
2849 int alloc = 0;
2850 int i, j;
2851
2852 vector_num = min(hdev->num_msi_left, vector_num);
2853
2854 for (j = 0; j < vector_num; j++) {
2855 for (i = 1; i < hdev->num_msi; i++) {
2856 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2857 vector->vector = pci_irq_vector(hdev->pdev, i);
2858 vector->io_addr = hdev->hw.io_base +
2859 HCLGE_VECTOR_REG_BASE +
2860 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2861 vport->vport_id *
2862 HCLGE_VECTOR_VF_OFFSET;
2863 hdev->vector_status[i] = vport->vport_id;
2864 hdev->vector_irq[i] = vector->vector;
2865
2866 vector++;
2867 alloc++;
2868
2869 break;
2870 }
2871 }
2872 }
2873 hdev->num_msi_left -= alloc;
2874 hdev->num_msi_used += alloc;
2875
2876 return alloc;
2877 }
2878
2879 static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2880 {
2881 int i;
2882
2883 for (i = 0; i < hdev->num_msi; i++)
2884 if (vector == hdev->vector_irq[i])
2885 return i;
2886
2887 return -EINVAL;
2888 }
2889
2890 static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2891 {
2892 return HCLGE_RSS_KEY_SIZE;
2893 }
2894
2895 static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2896 {
2897 return HCLGE_RSS_IND_TBL_SIZE;
2898 }
2899
2900 static int hclge_get_rss_algo(struct hclge_dev *hdev)
2901 {
2902 struct hclge_rss_config_cmd *req;
2903 struct hclge_desc desc;
2904 int rss_hash_algo;
2905 int ret;
2906
2907 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2908
2909 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2910 if (ret) {
2911 dev_err(&hdev->pdev->dev,
2912 "Get link status error, status =%d\n", ret);
2913 return ret;
2914 }
2915
2916 req = (struct hclge_rss_config_cmd *)desc.data;
2917 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2918
2919 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2920 return ETH_RSS_HASH_TOP;
2921
2922 return -EINVAL;
2923 }
2924
2925 static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2926 const u8 hfunc, const u8 *key)
2927 {
2928 struct hclge_rss_config_cmd *req;
2929 struct hclge_desc desc;
2930 int key_offset;
2931 int key_size;
2932 int ret;
2933
2934 req = (struct hclge_rss_config_cmd *)desc.data;
2935
2936 for (key_offset = 0; key_offset < 3; key_offset++) {
2937 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2938 false);
2939
2940 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2941 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2942
2943 if (key_offset == 2)
2944 key_size =
2945 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2946 else
2947 key_size = HCLGE_RSS_HASH_KEY_NUM;
2948
2949 memcpy(req->hash_key,
2950 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2951
2952 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2953 if (ret) {
2954 dev_err(&hdev->pdev->dev,
2955 "Configure RSS config fail, status = %d\n",
2956 ret);
2957 return ret;
2958 }
2959 }
2960 return 0;
2961 }
2962
2963 static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2964 {
2965 struct hclge_rss_indirection_table_cmd *req;
2966 struct hclge_desc desc;
2967 int i, j;
2968 int ret;
2969
2970 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
2971
2972 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2973 hclge_cmd_setup_basic_desc
2974 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2975
2976 req->start_table_index =
2977 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2978 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
2979
2980 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2981 req->rss_result[j] =
2982 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2983
2984 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2985 if (ret) {
2986 dev_err(&hdev->pdev->dev,
2987 "Configure rss indir table fail,status = %d\n",
2988 ret);
2989 return ret;
2990 }
2991 }
2992 return 0;
2993 }
2994
2995 static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2996 u16 *tc_size, u16 *tc_offset)
2997 {
2998 struct hclge_rss_tc_mode_cmd *req;
2999 struct hclge_desc desc;
3000 int ret;
3001 int i;
3002
3003 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
3004 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
3005
3006 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3007 u16 mode = 0;
3008
3009 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3010 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3011 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3012 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3013 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
3014
3015 req->rss_tc_mode[i] = cpu_to_le16(mode);
3016 }
3017
3018 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3019 if (ret) {
3020 dev_err(&hdev->pdev->dev,
3021 "Configure rss tc mode fail, status = %d\n", ret);
3022 return ret;
3023 }
3024
3025 return 0;
3026 }
3027
3028 static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3029 {
3030 struct hclge_rss_input_tuple_cmd *req;
3031 struct hclge_desc desc;
3032 int ret;
3033
3034 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3035
3036 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3037 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3038 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3039 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3040 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3041 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3042 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3043 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
3044 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3045 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3046 if (ret) {
3047 dev_err(&hdev->pdev->dev,
3048 "Configure rss input fail, status = %d\n", ret);
3049 return ret;
3050 }
3051
3052 return 0;
3053 }
3054
3055 static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3056 u8 *key, u8 *hfunc)
3057 {
3058 struct hclge_vport *vport = hclge_get_vport(handle);
3059 struct hclge_dev *hdev = vport->back;
3060 int i;
3061
3062 /* Get hash algorithm */
3063 if (hfunc)
3064 *hfunc = hclge_get_rss_algo(hdev);
3065
3066 /* Get the RSS Key required by the user */
3067 if (key)
3068 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3069
3070 /* Get indirect table */
3071 if (indir)
3072 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3073 indir[i] = vport->rss_indirection_tbl[i];
3074
3075 return 0;
3076 }
3077
3078 static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3079 const u8 *key, const u8 hfunc)
3080 {
3081 struct hclge_vport *vport = hclge_get_vport(handle);
3082 struct hclge_dev *hdev = vport->back;
3083 u8 hash_algo;
3084 int ret, i;
3085
3086 /* Set the RSS Hash Key if specififed by the user */
3087 if (key) {
3088 /* Update the shadow RSS key with user specified qids */
3089 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3090
3091 if (hfunc == ETH_RSS_HASH_TOP ||
3092 hfunc == ETH_RSS_HASH_NO_CHANGE)
3093 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3094 else
3095 return -EINVAL;
3096 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3097 if (ret)
3098 return ret;
3099 }
3100
3101 /* Update the shadow RSS table with user specified qids */
3102 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3103 vport->rss_indirection_tbl[i] = indir[i];
3104
3105 /* Update the hardware */
3106 ret = hclge_set_rss_indir_table(hdev, indir);
3107 return ret;
3108 }
3109
3110 static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3111 {
3112 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3113
3114 if (nfc->data & RXH_L4_B_2_3)
3115 hash_sets |= HCLGE_D_PORT_BIT;
3116 else
3117 hash_sets &= ~HCLGE_D_PORT_BIT;
3118
3119 if (nfc->data & RXH_IP_SRC)
3120 hash_sets |= HCLGE_S_IP_BIT;
3121 else
3122 hash_sets &= ~HCLGE_S_IP_BIT;
3123
3124 if (nfc->data & RXH_IP_DST)
3125 hash_sets |= HCLGE_D_IP_BIT;
3126 else
3127 hash_sets &= ~HCLGE_D_IP_BIT;
3128
3129 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3130 hash_sets |= HCLGE_V_TAG_BIT;
3131
3132 return hash_sets;
3133 }
3134
3135 static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3136 struct ethtool_rxnfc *nfc)
3137 {
3138 struct hclge_vport *vport = hclge_get_vport(handle);
3139 struct hclge_dev *hdev = vport->back;
3140 struct hclge_rss_input_tuple_cmd *req;
3141 struct hclge_desc desc;
3142 u8 tuple_sets;
3143 int ret;
3144
3145 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3146 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3147 return -EINVAL;
3148
3149 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3150 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3151 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3152 if (ret) {
3153 dev_err(&hdev->pdev->dev,
3154 "Read rss tuple fail, status = %d\n", ret);
3155 return ret;
3156 }
3157
3158 hclge_cmd_reuse_desc(&desc, false);
3159
3160 tuple_sets = hclge_get_rss_hash_bits(nfc);
3161 switch (nfc->flow_type) {
3162 case TCP_V4_FLOW:
3163 req->ipv4_tcp_en = tuple_sets;
3164 break;
3165 case TCP_V6_FLOW:
3166 req->ipv6_tcp_en = tuple_sets;
3167 break;
3168 case UDP_V4_FLOW:
3169 req->ipv4_udp_en = tuple_sets;
3170 break;
3171 case UDP_V6_FLOW:
3172 req->ipv6_udp_en = tuple_sets;
3173 break;
3174 case SCTP_V4_FLOW:
3175 req->ipv4_sctp_en = tuple_sets;
3176 break;
3177 case SCTP_V6_FLOW:
3178 if ((nfc->data & RXH_L4_B_0_1) ||
3179 (nfc->data & RXH_L4_B_2_3))
3180 return -EINVAL;
3181
3182 req->ipv6_sctp_en = tuple_sets;
3183 break;
3184 case IPV4_FLOW:
3185 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3186 break;
3187 case IPV6_FLOW:
3188 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3189 break;
3190 default:
3191 return -EINVAL;
3192 }
3193
3194 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3195 if (ret)
3196 dev_err(&hdev->pdev->dev,
3197 "Set rss tuple fail, status = %d\n", ret);
3198
3199 return ret;
3200 }
3201
3202 static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3203 struct ethtool_rxnfc *nfc)
3204 {
3205 struct hclge_vport *vport = hclge_get_vport(handle);
3206 struct hclge_dev *hdev = vport->back;
3207 struct hclge_rss_input_tuple_cmd *req;
3208 struct hclge_desc desc;
3209 u8 tuple_sets;
3210 int ret;
3211
3212 nfc->data = 0;
3213
3214 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3215 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3216 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3217 if (ret) {
3218 dev_err(&hdev->pdev->dev,
3219 "Read rss tuple fail, status = %d\n", ret);
3220 return ret;
3221 }
3222
3223 switch (nfc->flow_type) {
3224 case TCP_V4_FLOW:
3225 tuple_sets = req->ipv4_tcp_en;
3226 break;
3227 case UDP_V4_FLOW:
3228 tuple_sets = req->ipv4_udp_en;
3229 break;
3230 case TCP_V6_FLOW:
3231 tuple_sets = req->ipv6_tcp_en;
3232 break;
3233 case UDP_V6_FLOW:
3234 tuple_sets = req->ipv6_udp_en;
3235 break;
3236 case SCTP_V4_FLOW:
3237 tuple_sets = req->ipv4_sctp_en;
3238 break;
3239 case SCTP_V6_FLOW:
3240 tuple_sets = req->ipv6_sctp_en;
3241 break;
3242 case IPV4_FLOW:
3243 case IPV6_FLOW:
3244 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3245 break;
3246 default:
3247 return -EINVAL;
3248 }
3249
3250 if (!tuple_sets)
3251 return 0;
3252
3253 if (tuple_sets & HCLGE_D_PORT_BIT)
3254 nfc->data |= RXH_L4_B_2_3;
3255 if (tuple_sets & HCLGE_S_PORT_BIT)
3256 nfc->data |= RXH_L4_B_0_1;
3257 if (tuple_sets & HCLGE_D_IP_BIT)
3258 nfc->data |= RXH_IP_DST;
3259 if (tuple_sets & HCLGE_S_IP_BIT)
3260 nfc->data |= RXH_IP_SRC;
3261
3262 return 0;
3263 }
3264
3265 static int hclge_get_tc_size(struct hnae3_handle *handle)
3266 {
3267 struct hclge_vport *vport = hclge_get_vport(handle);
3268 struct hclge_dev *hdev = vport->back;
3269
3270 return hdev->rss_size_max;
3271 }
3272
3273 int hclge_rss_init_hw(struct hclge_dev *hdev)
3274 {
3275 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3276 struct hclge_vport *vport = hdev->vport;
3277 u16 tc_offset[HCLGE_MAX_TC_NUM];
3278 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3279 u16 tc_valid[HCLGE_MAX_TC_NUM];
3280 u16 tc_size[HCLGE_MAX_TC_NUM];
3281 u32 *rss_indir = NULL;
3282 u16 rss_size = 0, roundup_size;
3283 const u8 *key;
3284 int i, ret, j;
3285
3286 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3287 if (!rss_indir)
3288 return -ENOMEM;
3289
3290 /* Get default RSS key */
3291 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3292
3293 /* Initialize RSS indirect table for each vport */
3294 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3295 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3296 vport[j].rss_indirection_tbl[i] =
3297 i % vport[j].alloc_rss_size;
3298
3299 /* vport 0 is for PF */
3300 if (j != 0)
3301 continue;
3302
3303 rss_size = vport[j].alloc_rss_size;
3304 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3305 }
3306 }
3307 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3308 if (ret)
3309 goto err;
3310
3311 key = rss_key;
3312 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3313 if (ret)
3314 goto err;
3315
3316 ret = hclge_set_rss_input_tuple(hdev);
3317 if (ret)
3318 goto err;
3319
3320 /* Each TC have the same queue size, and tc_size set to hardware is
3321 * the log2 of roundup power of two of rss_size, the acutal queue
3322 * size is limited by indirection table.
3323 */
3324 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3325 dev_err(&hdev->pdev->dev,
3326 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3327 rss_size);
3328 ret = -EINVAL;
3329 goto err;
3330 }
3331
3332 roundup_size = roundup_pow_of_two(rss_size);
3333 roundup_size = ilog2(roundup_size);
3334
3335 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
3336 tc_valid[i] = 0;
3337
3338 if (!(hdev->hw_tc_map & BIT(i)))
3339 continue;
3340
3341 tc_valid[i] = 1;
3342 tc_size[i] = roundup_size;
3343 tc_offset[i] = rss_size * i;
3344 }
3345
3346 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3347
3348 err:
3349 kfree(rss_indir);
3350
3351 return ret;
3352 }
3353
3354 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3355 int vector_id, bool en,
3356 struct hnae3_ring_chain_node *ring_chain)
3357 {
3358 struct hclge_dev *hdev = vport->back;
3359 struct hnae3_ring_chain_node *node;
3360 struct hclge_desc desc;
3361 struct hclge_ctrl_vector_chain_cmd *req
3362 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3363 enum hclge_cmd_status status;
3364 enum hclge_opcode_type op;
3365 u16 tqp_type_and_id;
3366 int i;
3367
3368 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3369 hclge_cmd_setup_basic_desc(&desc, op, false);
3370 req->int_vector_id = vector_id;
3371
3372 i = 0;
3373 for (node = ring_chain; node; node = node->next) {
3374 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
3375 hnae_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3376 HCLGE_INT_TYPE_S,
3377 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
3378 hnae_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3379 HCLGE_TQP_ID_S, node->tqp_index);
3380 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
3381 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3382 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3383 req->vfid = vport->vport_id;
3384
3385 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3386 if (status) {
3387 dev_err(&hdev->pdev->dev,
3388 "Map TQP fail, status is %d.\n",
3389 status);
3390 return -EIO;
3391 }
3392 i = 0;
3393
3394 hclge_cmd_setup_basic_desc(&desc,
3395 op,
3396 false);
3397 req->int_vector_id = vector_id;
3398 }
3399 }
3400
3401 if (i > 0) {
3402 req->int_cause_num = i;
3403 req->vfid = vport->vport_id;
3404 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3405 if (status) {
3406 dev_err(&hdev->pdev->dev,
3407 "Map TQP fail, status is %d.\n", status);
3408 return -EIO;
3409 }
3410 }
3411
3412 return 0;
3413 }
3414
3415 static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3416 int vector,
3417 struct hnae3_ring_chain_node *ring_chain)
3418 {
3419 struct hclge_vport *vport = hclge_get_vport(handle);
3420 struct hclge_dev *hdev = vport->back;
3421 int vector_id;
3422
3423 vector_id = hclge_get_vector_index(hdev, vector);
3424 if (vector_id < 0) {
3425 dev_err(&hdev->pdev->dev,
3426 "Get vector index fail. vector_id =%d\n", vector_id);
3427 return vector_id;
3428 }
3429
3430 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
3431 }
3432
3433 static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3434 int vector,
3435 struct hnae3_ring_chain_node *ring_chain)
3436 {
3437 struct hclge_vport *vport = hclge_get_vport(handle);
3438 struct hclge_dev *hdev = vport->back;
3439 int vector_id, ret;
3440
3441 vector_id = hclge_get_vector_index(hdev, vector);
3442 if (vector_id < 0) {
3443 dev_err(&handle->pdev->dev,
3444 "Get vector index fail. ret =%d\n", vector_id);
3445 return vector_id;
3446 }
3447
3448 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
3449 if (ret) {
3450 dev_err(&handle->pdev->dev,
3451 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3452 vector_id,
3453 ret);
3454 return ret;
3455 }
3456
3457 /* Free this MSIX or MSI vector */
3458 hclge_free_vector(hdev, vector_id);
3459
3460 return 0;
3461 }
3462
3463 int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3464 struct hclge_promisc_param *param)
3465 {
3466 struct hclge_promisc_cfg_cmd *req;
3467 struct hclge_desc desc;
3468 int ret;
3469
3470 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3471
3472 req = (struct hclge_promisc_cfg_cmd *)desc.data;
3473 req->vf_id = param->vf_id;
3474 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3475
3476 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3477 if (ret) {
3478 dev_err(&hdev->pdev->dev,
3479 "Set promisc mode fail, status is %d.\n", ret);
3480 return ret;
3481 }
3482 return 0;
3483 }
3484
3485 void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3486 bool en_mc, bool en_bc, int vport_id)
3487 {
3488 if (!param)
3489 return;
3490
3491 memset(param, 0, sizeof(struct hclge_promisc_param));
3492 if (en_uc)
3493 param->enable = HCLGE_PROMISC_EN_UC;
3494 if (en_mc)
3495 param->enable |= HCLGE_PROMISC_EN_MC;
3496 if (en_bc)
3497 param->enable |= HCLGE_PROMISC_EN_BC;
3498 param->vf_id = vport_id;
3499 }
3500
3501 static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3502 {
3503 struct hclge_vport *vport = hclge_get_vport(handle);
3504 struct hclge_dev *hdev = vport->back;
3505 struct hclge_promisc_param param;
3506
3507 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3508 hclge_cmd_set_promisc_mode(hdev, &param);
3509 }
3510
3511 static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3512 {
3513 struct hclge_desc desc;
3514 struct hclge_config_mac_mode_cmd *req =
3515 (struct hclge_config_mac_mode_cmd *)desc.data;
3516 u32 loop_en = 0;
3517 int ret;
3518
3519 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
3520 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3521 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3522 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3523 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3524 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3525 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3526 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3527 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3528 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3529 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3530 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3531 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3532 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3533 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3534 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3535
3536 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3537 if (ret)
3538 dev_err(&hdev->pdev->dev,
3539 "mac enable fail, ret =%d.\n", ret);
3540 }
3541
3542 static int hclge_set_loopback(struct hnae3_handle *handle,
3543 enum hnae3_loop loop_mode, bool en)
3544 {
3545 struct hclge_vport *vport = hclge_get_vport(handle);
3546 struct hclge_config_mac_mode_cmd *req;
3547 struct hclge_dev *hdev = vport->back;
3548 struct hclge_desc desc;
3549 u32 loop_en;
3550 int ret;
3551
3552 switch (loop_mode) {
3553 case HNAE3_MAC_INTER_LOOP_MAC:
3554 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3555 /* 1 Read out the MAC mode config at first */
3556 hclge_cmd_setup_basic_desc(&desc,
3557 HCLGE_OPC_CONFIG_MAC_MODE,
3558 true);
3559 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3560 if (ret) {
3561 dev_err(&hdev->pdev->dev,
3562 "mac loopback get fail, ret =%d.\n",
3563 ret);
3564 return ret;
3565 }
3566
3567 /* 2 Then setup the loopback flag */
3568 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3569 if (en)
3570 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3571 else
3572 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3573
3574 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3575
3576 /* 3 Config mac work mode with loopback flag
3577 * and its original configure parameters
3578 */
3579 hclge_cmd_reuse_desc(&desc, false);
3580 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3581 if (ret)
3582 dev_err(&hdev->pdev->dev,
3583 "mac loopback set fail, ret =%d.\n", ret);
3584 break;
3585 default:
3586 ret = -ENOTSUPP;
3587 dev_err(&hdev->pdev->dev,
3588 "loop_mode %d is not supported\n", loop_mode);
3589 break;
3590 }
3591
3592 return ret;
3593 }
3594
3595 static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3596 int stream_id, bool enable)
3597 {
3598 struct hclge_desc desc;
3599 struct hclge_cfg_com_tqp_queue_cmd *req =
3600 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3601 int ret;
3602
3603 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3604 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3605 req->stream_id = cpu_to_le16(stream_id);
3606 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3607
3608 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3609 if (ret)
3610 dev_err(&hdev->pdev->dev,
3611 "Tqp enable fail, status =%d.\n", ret);
3612 return ret;
3613 }
3614
3615 static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3616 {
3617 struct hclge_vport *vport = hclge_get_vport(handle);
3618 struct hnae3_queue *queue;
3619 struct hclge_tqp *tqp;
3620 int i;
3621
3622 for (i = 0; i < vport->alloc_tqps; i++) {
3623 queue = handle->kinfo.tqp[i];
3624 tqp = container_of(queue, struct hclge_tqp, q);
3625 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3626 }
3627 }
3628
3629 static int hclge_ae_start(struct hnae3_handle *handle)
3630 {
3631 struct hclge_vport *vport = hclge_get_vport(handle);
3632 struct hclge_dev *hdev = vport->back;
3633 int i, queue_id, ret;
3634
3635 for (i = 0; i < vport->alloc_tqps; i++) {
3636 /* todo clear interrupt */
3637 /* ring enable */
3638 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3639 if (queue_id < 0) {
3640 dev_warn(&hdev->pdev->dev,
3641 "Get invalid queue id, ignore it\n");
3642 continue;
3643 }
3644
3645 hclge_tqp_enable(hdev, queue_id, 0, true);
3646 }
3647 /* mac enable */
3648 hclge_cfg_mac_mode(hdev, true);
3649 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
3650 mod_timer(&hdev->service_timer, jiffies + HZ);
3651
3652 ret = hclge_mac_start_phy(hdev);
3653 if (ret)
3654 return ret;
3655
3656 /* reset tqp stats */
3657 hclge_reset_tqp_stats(handle);
3658
3659 return 0;
3660 }
3661
3662 static void hclge_ae_stop(struct hnae3_handle *handle)
3663 {
3664 struct hclge_vport *vport = hclge_get_vport(handle);
3665 struct hclge_dev *hdev = vport->back;
3666 int i, queue_id;
3667
3668 for (i = 0; i < vport->alloc_tqps; i++) {
3669 /* Ring disable */
3670 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3671 if (queue_id < 0) {
3672 dev_warn(&hdev->pdev->dev,
3673 "Get invalid queue id, ignore it\n");
3674 continue;
3675 }
3676
3677 hclge_tqp_enable(hdev, queue_id, 0, false);
3678 }
3679 /* Mac disable */
3680 hclge_cfg_mac_mode(hdev, false);
3681
3682 hclge_mac_stop_phy(hdev);
3683
3684 /* reset tqp stats */
3685 hclge_reset_tqp_stats(handle);
3686 }
3687
3688 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3689 u16 cmdq_resp, u8 resp_code,
3690 enum hclge_mac_vlan_tbl_opcode op)
3691 {
3692 struct hclge_dev *hdev = vport->back;
3693 int return_status = -EIO;
3694
3695 if (cmdq_resp) {
3696 dev_err(&hdev->pdev->dev,
3697 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3698 cmdq_resp);
3699 return -EIO;
3700 }
3701
3702 if (op == HCLGE_MAC_VLAN_ADD) {
3703 if ((!resp_code) || (resp_code == 1)) {
3704 return_status = 0;
3705 } else if (resp_code == 2) {
3706 return_status = -EIO;
3707 dev_err(&hdev->pdev->dev,
3708 "add mac addr failed for uc_overflow.\n");
3709 } else if (resp_code == 3) {
3710 return_status = -EIO;
3711 dev_err(&hdev->pdev->dev,
3712 "add mac addr failed for mc_overflow.\n");
3713 } else {
3714 dev_err(&hdev->pdev->dev,
3715 "add mac addr failed for undefined, code=%d.\n",
3716 resp_code);
3717 }
3718 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3719 if (!resp_code) {
3720 return_status = 0;
3721 } else if (resp_code == 1) {
3722 return_status = -EIO;
3723 dev_dbg(&hdev->pdev->dev,
3724 "remove mac addr failed for miss.\n");
3725 } else {
3726 dev_err(&hdev->pdev->dev,
3727 "remove mac addr failed for undefined, code=%d.\n",
3728 resp_code);
3729 }
3730 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3731 if (!resp_code) {
3732 return_status = 0;
3733 } else if (resp_code == 1) {
3734 return_status = -EIO;
3735 dev_dbg(&hdev->pdev->dev,
3736 "lookup mac addr failed for miss.\n");
3737 } else {
3738 dev_err(&hdev->pdev->dev,
3739 "lookup mac addr failed for undefined, code=%d.\n",
3740 resp_code);
3741 }
3742 } else {
3743 return_status = -EIO;
3744 dev_err(&hdev->pdev->dev,
3745 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3746 op);
3747 }
3748
3749 return return_status;
3750 }
3751
3752 static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3753 {
3754 int word_num;
3755 int bit_num;
3756
3757 if (vfid > 255 || vfid < 0)
3758 return -EIO;
3759
3760 if (vfid >= 0 && vfid <= 191) {
3761 word_num = vfid / 32;
3762 bit_num = vfid % 32;
3763 if (clr)
3764 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3765 else
3766 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
3767 } else {
3768 word_num = (vfid - 192) / 32;
3769 bit_num = vfid % 32;
3770 if (clr)
3771 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
3772 else
3773 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
3774 }
3775
3776 return 0;
3777 }
3778
3779 static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3780 {
3781 #define HCLGE_DESC_NUMBER 3
3782 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3783 int i, j;
3784
3785 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3786 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3787 if (desc[i].data[j])
3788 return false;
3789
3790 return true;
3791 }
3792
3793 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
3794 const u8 *addr)
3795 {
3796 const unsigned char *mac_addr = addr;
3797 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3798 (mac_addr[0]) | (mac_addr[1] << 8);
3799 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3800
3801 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3802 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3803 }
3804
3805 static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3806 const u8 *addr)
3807 {
3808 u16 high_val = addr[1] | (addr[0] << 8);
3809 struct hclge_dev *hdev = vport->back;
3810 u32 rsh = 4 - hdev->mta_mac_sel_type;
3811 u16 ret_val = (high_val >> rsh) & 0xfff;
3812
3813 return ret_val;
3814 }
3815
3816 static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3817 enum hclge_mta_dmac_sel_type mta_mac_sel,
3818 bool enable)
3819 {
3820 struct hclge_mta_filter_mode_cmd *req;
3821 struct hclge_desc desc;
3822 int ret;
3823
3824 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
3825 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3826
3827 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3828 enable);
3829 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3830 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3831
3832 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3833 if (ret) {
3834 dev_err(&hdev->pdev->dev,
3835 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3836 ret);
3837 return ret;
3838 }
3839
3840 return 0;
3841 }
3842
3843 int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3844 u8 func_id,
3845 bool enable)
3846 {
3847 struct hclge_cfg_func_mta_filter_cmd *req;
3848 struct hclge_desc desc;
3849 int ret;
3850
3851 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
3852 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3853
3854 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3855 enable);
3856 req->function_id = func_id;
3857
3858 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3859 if (ret) {
3860 dev_err(&hdev->pdev->dev,
3861 "Config func_id enable failed for cmd_send, ret =%d.\n",
3862 ret);
3863 return ret;
3864 }
3865
3866 return 0;
3867 }
3868
3869 static int hclge_set_mta_table_item(struct hclge_vport *vport,
3870 u16 idx,
3871 bool enable)
3872 {
3873 struct hclge_dev *hdev = vport->back;
3874 struct hclge_cfg_func_mta_item_cmd *req;
3875 struct hclge_desc desc;
3876 u16 item_idx = 0;
3877 int ret;
3878
3879 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
3880 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3881 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3882
3883 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3884 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3885 req->item_idx = cpu_to_le16(item_idx);
3886
3887 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3888 if (ret) {
3889 dev_err(&hdev->pdev->dev,
3890 "Config mta table item failed for cmd_send, ret =%d.\n",
3891 ret);
3892 return ret;
3893 }
3894
3895 return 0;
3896 }
3897
3898 static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3899 struct hclge_mac_vlan_tbl_entry_cmd *req)
3900 {
3901 struct hclge_dev *hdev = vport->back;
3902 struct hclge_desc desc;
3903 u8 resp_code;
3904 u16 retval;
3905 int ret;
3906
3907 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3908
3909 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3910
3911 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3912 if (ret) {
3913 dev_err(&hdev->pdev->dev,
3914 "del mac addr failed for cmd_send, ret =%d.\n",
3915 ret);
3916 return ret;
3917 }
3918 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3919 retval = le16_to_cpu(desc.retval);
3920
3921 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
3922 HCLGE_MAC_VLAN_REMOVE);
3923 }
3924
3925 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3926 struct hclge_mac_vlan_tbl_entry_cmd *req,
3927 struct hclge_desc *desc,
3928 bool is_mc)
3929 {
3930 struct hclge_dev *hdev = vport->back;
3931 u8 resp_code;
3932 u16 retval;
3933 int ret;
3934
3935 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3936 if (is_mc) {
3937 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3938 memcpy(desc[0].data,
3939 req,
3940 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3941 hclge_cmd_setup_basic_desc(&desc[1],
3942 HCLGE_OPC_MAC_VLAN_ADD,
3943 true);
3944 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3945 hclge_cmd_setup_basic_desc(&desc[2],
3946 HCLGE_OPC_MAC_VLAN_ADD,
3947 true);
3948 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3949 } else {
3950 memcpy(desc[0].data,
3951 req,
3952 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3953 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3954 }
3955 if (ret) {
3956 dev_err(&hdev->pdev->dev,
3957 "lookup mac addr failed for cmd_send, ret =%d.\n",
3958 ret);
3959 return ret;
3960 }
3961 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3962 retval = le16_to_cpu(desc[0].retval);
3963
3964 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
3965 HCLGE_MAC_VLAN_LKUP);
3966 }
3967
3968 static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
3969 struct hclge_mac_vlan_tbl_entry_cmd *req,
3970 struct hclge_desc *mc_desc)
3971 {
3972 struct hclge_dev *hdev = vport->back;
3973 int cfg_status;
3974 u8 resp_code;
3975 u16 retval;
3976 int ret;
3977
3978 if (!mc_desc) {
3979 struct hclge_desc desc;
3980
3981 hclge_cmd_setup_basic_desc(&desc,
3982 HCLGE_OPC_MAC_VLAN_ADD,
3983 false);
3984 memcpy(desc.data, req,
3985 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
3986 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3987 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3988 retval = le16_to_cpu(desc.retval);
3989
3990 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
3991 resp_code,
3992 HCLGE_MAC_VLAN_ADD);
3993 } else {
3994 hclge_cmd_reuse_desc(&mc_desc[0], false);
3995 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3996 hclge_cmd_reuse_desc(&mc_desc[1], false);
3997 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3998 hclge_cmd_reuse_desc(&mc_desc[2], false);
3999 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
4000 memcpy(mc_desc[0].data, req,
4001 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
4002 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
4003 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
4004 retval = le16_to_cpu(mc_desc[0].retval);
4005
4006 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
4007 resp_code,
4008 HCLGE_MAC_VLAN_ADD);
4009 }
4010
4011 if (ret) {
4012 dev_err(&hdev->pdev->dev,
4013 "add mac addr failed for cmd_send, ret =%d.\n",
4014 ret);
4015 return ret;
4016 }
4017
4018 return cfg_status;
4019 }
4020
4021 static int hclge_add_uc_addr(struct hnae3_handle *handle,
4022 const unsigned char *addr)
4023 {
4024 struct hclge_vport *vport = hclge_get_vport(handle);
4025
4026 return hclge_add_uc_addr_common(vport, addr);
4027 }
4028
4029 int hclge_add_uc_addr_common(struct hclge_vport *vport,
4030 const unsigned char *addr)
4031 {
4032 struct hclge_dev *hdev = vport->back;
4033 struct hclge_mac_vlan_tbl_entry_cmd req;
4034 enum hclge_cmd_status status;
4035 u16 egress_port = 0;
4036
4037 /* mac addr check */
4038 if (is_zero_ether_addr(addr) ||
4039 is_broadcast_ether_addr(addr) ||
4040 is_multicast_ether_addr(addr)) {
4041 dev_err(&hdev->pdev->dev,
4042 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4043 addr,
4044 is_zero_ether_addr(addr),
4045 is_broadcast_ether_addr(addr),
4046 is_multicast_ether_addr(addr));
4047 return -EINVAL;
4048 }
4049
4050 memset(&req, 0, sizeof(req));
4051 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4052 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4053 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
4054 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4055
4056 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
4057 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
4058 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4059 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
4060 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
4061 HCLGE_MAC_EPORT_PFID_S, 0);
4062
4063 req.egress_port = cpu_to_le16(egress_port);
4064
4065 hclge_prepare_mac_addr(&req, addr);
4066
4067 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
4068
4069 return status;
4070 }
4071
4072 static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4073 const unsigned char *addr)
4074 {
4075 struct hclge_vport *vport = hclge_get_vport(handle);
4076
4077 return hclge_rm_uc_addr_common(vport, addr);
4078 }
4079
4080 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4081 const unsigned char *addr)
4082 {
4083 struct hclge_dev *hdev = vport->back;
4084 struct hclge_mac_vlan_tbl_entry_cmd req;
4085 enum hclge_cmd_status status;
4086
4087 /* mac addr check */
4088 if (is_zero_ether_addr(addr) ||
4089 is_broadcast_ether_addr(addr) ||
4090 is_multicast_ether_addr(addr)) {
4091 dev_dbg(&hdev->pdev->dev,
4092 "Remove mac err! invalid mac:%pM.\n",
4093 addr);
4094 return -EINVAL;
4095 }
4096
4097 memset(&req, 0, sizeof(req));
4098 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4099 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4100 hclge_prepare_mac_addr(&req, addr);
4101 status = hclge_remove_mac_vlan_tbl(vport, &req);
4102
4103 return status;
4104 }
4105
4106 static int hclge_add_mc_addr(struct hnae3_handle *handle,
4107 const unsigned char *addr)
4108 {
4109 struct hclge_vport *vport = hclge_get_vport(handle);
4110
4111 return hclge_add_mc_addr_common(vport, addr);
4112 }
4113
4114 int hclge_add_mc_addr_common(struct hclge_vport *vport,
4115 const unsigned char *addr)
4116 {
4117 struct hclge_dev *hdev = vport->back;
4118 struct hclge_mac_vlan_tbl_entry_cmd req;
4119 struct hclge_desc desc[3];
4120 u16 tbl_idx;
4121 int status;
4122
4123 /* mac addr check */
4124 if (!is_multicast_ether_addr(addr)) {
4125 dev_err(&hdev->pdev->dev,
4126 "Add mc mac err! invalid mac:%pM.\n",
4127 addr);
4128 return -EINVAL;
4129 }
4130 memset(&req, 0, sizeof(req));
4131 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4132 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4133 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4134 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4135 hclge_prepare_mac_addr(&req, addr);
4136 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4137 if (!status) {
4138 /* This mac addr exist, update VFID for it */
4139 hclge_update_desc_vfid(desc, vport->vport_id, false);
4140 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4141 } else {
4142 /* This mac addr do not exist, add new entry for it */
4143 memset(desc[0].data, 0, sizeof(desc[0].data));
4144 memset(desc[1].data, 0, sizeof(desc[0].data));
4145 memset(desc[2].data, 0, sizeof(desc[0].data));
4146 hclge_update_desc_vfid(desc, vport->vport_id, false);
4147 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4148 }
4149
4150 /* Set MTA table for this MAC address */
4151 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4152 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4153
4154 return status;
4155 }
4156
4157 static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4158 const unsigned char *addr)
4159 {
4160 struct hclge_vport *vport = hclge_get_vport(handle);
4161
4162 return hclge_rm_mc_addr_common(vport, addr);
4163 }
4164
4165 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4166 const unsigned char *addr)
4167 {
4168 struct hclge_dev *hdev = vport->back;
4169 struct hclge_mac_vlan_tbl_entry_cmd req;
4170 enum hclge_cmd_status status;
4171 struct hclge_desc desc[3];
4172 u16 tbl_idx;
4173
4174 /* mac addr check */
4175 if (!is_multicast_ether_addr(addr)) {
4176 dev_dbg(&hdev->pdev->dev,
4177 "Remove mc mac err! invalid mac:%pM.\n",
4178 addr);
4179 return -EINVAL;
4180 }
4181
4182 memset(&req, 0, sizeof(req));
4183 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4184 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4185 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4186 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4187 hclge_prepare_mac_addr(&req, addr);
4188 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4189 if (!status) {
4190 /* This mac addr exist, remove this handle's VFID for it */
4191 hclge_update_desc_vfid(desc, vport->vport_id, true);
4192
4193 if (hclge_is_all_function_id_zero(desc))
4194 /* All the vfid is zero, so need to delete this entry */
4195 status = hclge_remove_mac_vlan_tbl(vport, &req);
4196 else
4197 /* Not all the vfid is zero, update the vfid */
4198 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4199
4200 } else {
4201 /* This mac addr do not exist, can't delete it */
4202 dev_err(&hdev->pdev->dev,
4203 "Rm multicast mac addr failed, ret = %d.\n",
4204 status);
4205 return -EIO;
4206 }
4207
4208 /* Set MTB table for this MAC address */
4209 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4210 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4211
4212 return status;
4213 }
4214
4215 static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4216 {
4217 struct hclge_vport *vport = hclge_get_vport(handle);
4218 struct hclge_dev *hdev = vport->back;
4219
4220 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4221 }
4222
4223 static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4224 {
4225 const unsigned char *new_addr = (const unsigned char *)p;
4226 struct hclge_vport *vport = hclge_get_vport(handle);
4227 struct hclge_dev *hdev = vport->back;
4228
4229 /* mac addr check */
4230 if (is_zero_ether_addr(new_addr) ||
4231 is_broadcast_ether_addr(new_addr) ||
4232 is_multicast_ether_addr(new_addr)) {
4233 dev_err(&hdev->pdev->dev,
4234 "Change uc mac err! invalid mac:%p.\n",
4235 new_addr);
4236 return -EINVAL;
4237 }
4238
4239 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4240
4241 if (!hclge_add_uc_addr(handle, new_addr)) {
4242 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4243 return 0;
4244 }
4245
4246 return -EIO;
4247 }
4248
4249 static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4250 bool filter_en)
4251 {
4252 struct hclge_vlan_filter_ctrl_cmd *req;
4253 struct hclge_desc desc;
4254 int ret;
4255
4256 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4257
4258 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
4259 req->vlan_type = vlan_type;
4260 req->vlan_fe = filter_en;
4261
4262 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4263 if (ret) {
4264 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4265 ret);
4266 return ret;
4267 }
4268
4269 return 0;
4270 }
4271
4272 #define HCLGE_FILTER_TYPE_VF 0
4273 #define HCLGE_FILTER_TYPE_PORT 1
4274
4275 static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4276 {
4277 struct hclge_vport *vport = hclge_get_vport(handle);
4278 struct hclge_dev *hdev = vport->back;
4279
4280 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4281 }
4282
4283 int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4284 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4285 {
4286 #define HCLGE_MAX_VF_BYTES 16
4287 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4288 struct hclge_vlan_filter_vf_cfg_cmd *req1;
4289 struct hclge_desc desc[2];
4290 u8 vf_byte_val;
4291 u8 vf_byte_off;
4292 int ret;
4293
4294 hclge_cmd_setup_basic_desc(&desc[0],
4295 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4296 hclge_cmd_setup_basic_desc(&desc[1],
4297 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4298
4299 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4300
4301 vf_byte_off = vfid / 8;
4302 vf_byte_val = 1 << (vfid % 8);
4303
4304 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4305 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
4306
4307 req0->vlan_id = cpu_to_le16(vlan);
4308 req0->vlan_cfg = is_kill;
4309
4310 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4311 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4312 else
4313 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4314
4315 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4316 if (ret) {
4317 dev_err(&hdev->pdev->dev,
4318 "Send vf vlan command fail, ret =%d.\n",
4319 ret);
4320 return ret;
4321 }
4322
4323 if (!is_kill) {
4324 if (!req0->resp_code || req0->resp_code == 1)
4325 return 0;
4326
4327 dev_err(&hdev->pdev->dev,
4328 "Add vf vlan filter fail, ret =%d.\n",
4329 req0->resp_code);
4330 } else {
4331 if (!req0->resp_code)
4332 return 0;
4333
4334 dev_err(&hdev->pdev->dev,
4335 "Kill vf vlan filter fail, ret =%d.\n",
4336 req0->resp_code);
4337 }
4338
4339 return -EIO;
4340 }
4341
4342 static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4343 __be16 proto, u16 vlan_id,
4344 bool is_kill)
4345 {
4346 struct hclge_vport *vport = hclge_get_vport(handle);
4347 struct hclge_dev *hdev = vport->back;
4348 struct hclge_vlan_filter_pf_cfg_cmd *req;
4349 struct hclge_desc desc;
4350 u8 vlan_offset_byte_val;
4351 u8 vlan_offset_byte;
4352 u8 vlan_offset_160;
4353 int ret;
4354
4355 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4356
4357 vlan_offset_160 = vlan_id / 160;
4358 vlan_offset_byte = (vlan_id % 160) / 8;
4359 vlan_offset_byte_val = 1 << (vlan_id % 8);
4360
4361 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
4362 req->vlan_offset = vlan_offset_160;
4363 req->vlan_cfg = is_kill;
4364 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4365
4366 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4367 if (ret) {
4368 dev_err(&hdev->pdev->dev,
4369 "port vlan command, send fail, ret =%d.\n",
4370 ret);
4371 return ret;
4372 }
4373
4374 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4375 if (ret) {
4376 dev_err(&hdev->pdev->dev,
4377 "Set pf vlan filter config fail, ret =%d.\n",
4378 ret);
4379 return -EIO;
4380 }
4381
4382 return 0;
4383 }
4384
4385 static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4386 u16 vlan, u8 qos, __be16 proto)
4387 {
4388 struct hclge_vport *vport = hclge_get_vport(handle);
4389 struct hclge_dev *hdev = vport->back;
4390
4391 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4392 return -EINVAL;
4393 if (proto != htons(ETH_P_8021Q))
4394 return -EPROTONOSUPPORT;
4395
4396 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4397 }
4398
4399 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4400 {
4401 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4402 struct hclge_vport_vtag_tx_cfg_cmd *req;
4403 struct hclge_dev *hdev = vport->back;
4404 struct hclge_desc desc;
4405 int status;
4406
4407 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4408
4409 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4410 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4411 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
4412 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG_B,
4413 vcfg->accept_tag ? 1 : 0);
4414 hnae_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG_B,
4415 vcfg->accept_untag ? 1 : 0);
4416 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4417 vcfg->insert_tag1_en ? 1 : 0);
4418 hnae_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4419 vcfg->insert_tag2_en ? 1 : 0);
4420 hnae_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
4421
4422 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4423 req->vf_bitmap[req->vf_offset] =
4424 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4425
4426 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4427 if (status)
4428 dev_err(&hdev->pdev->dev,
4429 "Send port txvlan cfg command fail, ret =%d\n",
4430 status);
4431
4432 return status;
4433 }
4434
4435 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4436 {
4437 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4438 struct hclge_vport_vtag_rx_cfg_cmd *req;
4439 struct hclge_dev *hdev = vport->back;
4440 struct hclge_desc desc;
4441 int status;
4442
4443 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4444
4445 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
4446 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4447 vcfg->strip_tag1_en ? 1 : 0);
4448 hnae_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4449 vcfg->strip_tag2_en ? 1 : 0);
4450 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4451 vcfg->vlan1_vlan_prionly ? 1 : 0);
4452 hnae_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4453 vcfg->vlan2_vlan_prionly ? 1 : 0);
4454
4455 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4456 req->vf_bitmap[req->vf_offset] =
4457 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4458
4459 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4460 if (status)
4461 dev_err(&hdev->pdev->dev,
4462 "Send port rxvlan cfg command fail, ret =%d\n",
4463 status);
4464
4465 return status;
4466 }
4467
4468 static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4469 {
4470 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4471 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4472 struct hclge_desc desc;
4473 int status;
4474
4475 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4476 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4477 rx_req->ot_fst_vlan_type =
4478 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4479 rx_req->ot_sec_vlan_type =
4480 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4481 rx_req->in_fst_vlan_type =
4482 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4483 rx_req->in_sec_vlan_type =
4484 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4485
4486 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4487 if (status) {
4488 dev_err(&hdev->pdev->dev,
4489 "Send rxvlan protocol type command fail, ret =%d\n",
4490 status);
4491 return status;
4492 }
4493
4494 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4495
4496 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data;
4497 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4498 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4499
4500 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4501 if (status)
4502 dev_err(&hdev->pdev->dev,
4503 "Send txvlan protocol type command fail, ret =%d\n",
4504 status);
4505
4506 return status;
4507 }
4508
4509 static int hclge_init_vlan_config(struct hclge_dev *hdev)
4510 {
4511 #define HCLGE_DEF_VLAN_TYPE 0x8100
4512
4513 struct hnae3_handle *handle;
4514 struct hclge_vport *vport;
4515 int ret;
4516 int i;
4517
4518 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4519 if (ret)
4520 return ret;
4521
4522 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
4523 if (ret)
4524 return ret;
4525
4526 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4527 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4528 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4529 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4530 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4531 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4532
4533 ret = hclge_set_vlan_protocol_type(hdev);
4534 if (ret)
4535 return ret;
4536
4537 for (i = 0; i < hdev->num_alloc_vport; i++) {
4538 vport = &hdev->vport[i];
4539 vport->txvlan_cfg.accept_tag = true;
4540 vport->txvlan_cfg.accept_untag = true;
4541 vport->txvlan_cfg.insert_tag1_en = false;
4542 vport->txvlan_cfg.insert_tag2_en = false;
4543 vport->txvlan_cfg.default_tag1 = 0;
4544 vport->txvlan_cfg.default_tag2 = 0;
4545
4546 ret = hclge_set_vlan_tx_offload_cfg(vport);
4547 if (ret)
4548 return ret;
4549
4550 vport->rxvlan_cfg.strip_tag1_en = false;
4551 vport->rxvlan_cfg.strip_tag2_en = true;
4552 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4553 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4554
4555 ret = hclge_set_vlan_rx_offload_cfg(vport);
4556 if (ret)
4557 return ret;
4558 }
4559
4560 handle = &hdev->vport[0].nic;
4561 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
4562 }
4563
4564 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
4565 {
4566 struct hclge_vport *vport = hclge_get_vport(handle);
4567
4568 vport->rxvlan_cfg.strip_tag1_en = false;
4569 vport->rxvlan_cfg.strip_tag2_en = enable;
4570 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4571 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4572
4573 return hclge_set_vlan_rx_offload_cfg(vport);
4574 }
4575
4576 static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4577 {
4578 struct hclge_vport *vport = hclge_get_vport(handle);
4579 struct hclge_config_max_frm_size_cmd *req;
4580 struct hclge_dev *hdev = vport->back;
4581 struct hclge_desc desc;
4582 int max_frm_size;
4583 int ret;
4584
4585 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4586
4587 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4588 max_frm_size > HCLGE_MAC_MAX_FRAME)
4589 return -EINVAL;
4590
4591 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4592
4593 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4594
4595 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
4596 req->max_frm_size = cpu_to_le16(max_frm_size);
4597
4598 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4599 if (ret) {
4600 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4601 return ret;
4602 }
4603
4604 hdev->mps = max_frm_size;
4605
4606 return 0;
4607 }
4608
4609 static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4610 bool enable)
4611 {
4612 struct hclge_reset_tqp_queue_cmd *req;
4613 struct hclge_desc desc;
4614 int ret;
4615
4616 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4617
4618 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4619 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4620 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4621
4622 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4623 if (ret) {
4624 dev_err(&hdev->pdev->dev,
4625 "Send tqp reset cmd error, status =%d\n", ret);
4626 return ret;
4627 }
4628
4629 return 0;
4630 }
4631
4632 static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4633 {
4634 struct hclge_reset_tqp_queue_cmd *req;
4635 struct hclge_desc desc;
4636 int ret;
4637
4638 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4639
4640 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
4641 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4642
4643 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4644 if (ret) {
4645 dev_err(&hdev->pdev->dev,
4646 "Get reset status error, status =%d\n", ret);
4647 return ret;
4648 }
4649
4650 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4651 }
4652
4653 void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4654 {
4655 struct hclge_vport *vport = hclge_get_vport(handle);
4656 struct hclge_dev *hdev = vport->back;
4657 int reset_try_times = 0;
4658 int reset_status;
4659 int ret;
4660
4661 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4662 if (ret) {
4663 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4664 return;
4665 }
4666
4667 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4668 if (ret) {
4669 dev_warn(&hdev->pdev->dev,
4670 "Send reset tqp cmd fail, ret = %d\n", ret);
4671 return;
4672 }
4673
4674 reset_try_times = 0;
4675 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4676 /* Wait for tqp hw reset */
4677 msleep(20);
4678 reset_status = hclge_get_reset_status(hdev, queue_id);
4679 if (reset_status)
4680 break;
4681 }
4682
4683 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4684 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4685 return;
4686 }
4687
4688 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4689 if (ret) {
4690 dev_warn(&hdev->pdev->dev,
4691 "Deassert the soft reset fail, ret = %d\n", ret);
4692 return;
4693 }
4694 }
4695
4696 static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4697 {
4698 struct hclge_vport *vport = hclge_get_vport(handle);
4699 struct hclge_dev *hdev = vport->back;
4700
4701 return hdev->fw_version;
4702 }
4703
4704 static void hclge_get_flowctrl_adv(struct hnae3_handle *handle,
4705 u32 *flowctrl_adv)
4706 {
4707 struct hclge_vport *vport = hclge_get_vport(handle);
4708 struct hclge_dev *hdev = vport->back;
4709 struct phy_device *phydev = hdev->hw.mac.phydev;
4710
4711 if (!phydev)
4712 return;
4713
4714 *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) |
4715 (phydev->advertising & ADVERTISED_Asym_Pause);
4716 }
4717
4718 static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4719 {
4720 struct phy_device *phydev = hdev->hw.mac.phydev;
4721
4722 if (!phydev)
4723 return;
4724
4725 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
4726
4727 if (rx_en)
4728 phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
4729
4730 if (tx_en)
4731 phydev->advertising ^= ADVERTISED_Asym_Pause;
4732 }
4733
4734 static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4735 {
4736 int ret;
4737
4738 if (rx_en && tx_en)
4739 hdev->fc_mode_last_time = HCLGE_FC_FULL;
4740 else if (rx_en && !tx_en)
4741 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
4742 else if (!rx_en && tx_en)
4743 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
4744 else
4745 hdev->fc_mode_last_time = HCLGE_FC_NONE;
4746
4747 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
4748 return 0;
4749
4750 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
4751 if (ret) {
4752 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
4753 ret);
4754 return ret;
4755 }
4756
4757 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
4758
4759 return 0;
4760 }
4761
4762 int hclge_cfg_flowctrl(struct hclge_dev *hdev)
4763 {
4764 struct phy_device *phydev = hdev->hw.mac.phydev;
4765 u16 remote_advertising = 0;
4766 u16 local_advertising = 0;
4767 u32 rx_pause, tx_pause;
4768 u8 flowctl;
4769
4770 if (!phydev->link || !phydev->autoneg)
4771 return 0;
4772
4773 if (phydev->advertising & ADVERTISED_Pause)
4774 local_advertising = ADVERTISE_PAUSE_CAP;
4775
4776 if (phydev->advertising & ADVERTISED_Asym_Pause)
4777 local_advertising |= ADVERTISE_PAUSE_ASYM;
4778
4779 if (phydev->pause)
4780 remote_advertising = LPA_PAUSE_CAP;
4781
4782 if (phydev->asym_pause)
4783 remote_advertising |= LPA_PAUSE_ASYM;
4784
4785 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
4786 remote_advertising);
4787 tx_pause = flowctl & FLOW_CTRL_TX;
4788 rx_pause = flowctl & FLOW_CTRL_RX;
4789
4790 if (phydev->duplex == HCLGE_MAC_HALF) {
4791 tx_pause = 0;
4792 rx_pause = 0;
4793 }
4794
4795 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
4796 }
4797
4798 static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4799 u32 *rx_en, u32 *tx_en)
4800 {
4801 struct hclge_vport *vport = hclge_get_vport(handle);
4802 struct hclge_dev *hdev = vport->back;
4803
4804 *auto_neg = hclge_get_autoneg(handle);
4805
4806 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4807 *rx_en = 0;
4808 *tx_en = 0;
4809 return;
4810 }
4811
4812 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4813 *rx_en = 1;
4814 *tx_en = 0;
4815 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4816 *tx_en = 1;
4817 *rx_en = 0;
4818 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4819 *rx_en = 1;
4820 *tx_en = 1;
4821 } else {
4822 *rx_en = 0;
4823 *tx_en = 0;
4824 }
4825 }
4826
4827 static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
4828 u32 rx_en, u32 tx_en)
4829 {
4830 struct hclge_vport *vport = hclge_get_vport(handle);
4831 struct hclge_dev *hdev = vport->back;
4832 struct phy_device *phydev = hdev->hw.mac.phydev;
4833 u32 fc_autoneg;
4834
4835 /* Only support flow control negotiation for netdev with
4836 * phy attached for now.
4837 */
4838 if (!phydev)
4839 return -EOPNOTSUPP;
4840
4841 fc_autoneg = hclge_get_autoneg(handle);
4842 if (auto_neg != fc_autoneg) {
4843 dev_info(&hdev->pdev->dev,
4844 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
4845 return -EOPNOTSUPP;
4846 }
4847
4848 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4849 dev_info(&hdev->pdev->dev,
4850 "Priority flow control enabled. Cannot set link flow control.\n");
4851 return -EOPNOTSUPP;
4852 }
4853
4854 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
4855
4856 if (!fc_autoneg)
4857 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
4858
4859 return phy_start_aneg(phydev);
4860 }
4861
4862 static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4863 u8 *auto_neg, u32 *speed, u8 *duplex)
4864 {
4865 struct hclge_vport *vport = hclge_get_vport(handle);
4866 struct hclge_dev *hdev = vport->back;
4867
4868 if (speed)
4869 *speed = hdev->hw.mac.speed;
4870 if (duplex)
4871 *duplex = hdev->hw.mac.duplex;
4872 if (auto_neg)
4873 *auto_neg = hdev->hw.mac.autoneg;
4874 }
4875
4876 static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4877 {
4878 struct hclge_vport *vport = hclge_get_vport(handle);
4879 struct hclge_dev *hdev = vport->back;
4880
4881 if (media_type)
4882 *media_type = hdev->hw.mac.media_type;
4883 }
4884
4885 static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4886 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4887 {
4888 struct hclge_vport *vport = hclge_get_vport(handle);
4889 struct hclge_dev *hdev = vport->back;
4890 struct phy_device *phydev = hdev->hw.mac.phydev;
4891 int mdix_ctrl, mdix, retval, is_resolved;
4892
4893 if (!phydev) {
4894 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4895 *tp_mdix = ETH_TP_MDI_INVALID;
4896 return;
4897 }
4898
4899 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4900
4901 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4902 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4903 HCLGE_PHY_MDIX_CTRL_S);
4904
4905 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4906 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4907 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4908
4909 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4910
4911 switch (mdix_ctrl) {
4912 case 0x0:
4913 *tp_mdix_ctrl = ETH_TP_MDI;
4914 break;
4915 case 0x1:
4916 *tp_mdix_ctrl = ETH_TP_MDI_X;
4917 break;
4918 case 0x3:
4919 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4920 break;
4921 default:
4922 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4923 break;
4924 }
4925
4926 if (!is_resolved)
4927 *tp_mdix = ETH_TP_MDI_INVALID;
4928 else if (mdix)
4929 *tp_mdix = ETH_TP_MDI_X;
4930 else
4931 *tp_mdix = ETH_TP_MDI;
4932 }
4933
4934 static int hclge_init_client_instance(struct hnae3_client *client,
4935 struct hnae3_ae_dev *ae_dev)
4936 {
4937 struct hclge_dev *hdev = ae_dev->priv;
4938 struct hclge_vport *vport;
4939 int i, ret;
4940
4941 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4942 vport = &hdev->vport[i];
4943
4944 switch (client->type) {
4945 case HNAE3_CLIENT_KNIC:
4946
4947 hdev->nic_client = client;
4948 vport->nic.client = client;
4949 ret = client->ops->init_instance(&vport->nic);
4950 if (ret)
4951 goto err;
4952
4953 if (hdev->roce_client &&
4954 hnae3_dev_roce_supported(hdev)) {
4955 struct hnae3_client *rc = hdev->roce_client;
4956
4957 ret = hclge_init_roce_base_info(vport);
4958 if (ret)
4959 goto err;
4960
4961 ret = rc->ops->init_instance(&vport->roce);
4962 if (ret)
4963 goto err;
4964 }
4965
4966 break;
4967 case HNAE3_CLIENT_UNIC:
4968 hdev->nic_client = client;
4969 vport->nic.client = client;
4970
4971 ret = client->ops->init_instance(&vport->nic);
4972 if (ret)
4973 goto err;
4974
4975 break;
4976 case HNAE3_CLIENT_ROCE:
4977 if (hnae3_dev_roce_supported(hdev)) {
4978 hdev->roce_client = client;
4979 vport->roce.client = client;
4980 }
4981
4982 if (hdev->roce_client && hdev->nic_client) {
4983 ret = hclge_init_roce_base_info(vport);
4984 if (ret)
4985 goto err;
4986
4987 ret = client->ops->init_instance(&vport->roce);
4988 if (ret)
4989 goto err;
4990 }
4991 }
4992 }
4993
4994 return 0;
4995 err:
4996 return ret;
4997 }
4998
4999 static void hclge_uninit_client_instance(struct hnae3_client *client,
5000 struct hnae3_ae_dev *ae_dev)
5001 {
5002 struct hclge_dev *hdev = ae_dev->priv;
5003 struct hclge_vport *vport;
5004 int i;
5005
5006 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5007 vport = &hdev->vport[i];
5008 if (hdev->roce_client) {
5009 hdev->roce_client->ops->uninit_instance(&vport->roce,
5010 0);
5011 hdev->roce_client = NULL;
5012 vport->roce.client = NULL;
5013 }
5014 if (client->type == HNAE3_CLIENT_ROCE)
5015 return;
5016 if (client->ops->uninit_instance) {
5017 client->ops->uninit_instance(&vport->nic, 0);
5018 hdev->nic_client = NULL;
5019 vport->nic.client = NULL;
5020 }
5021 }
5022 }
5023
5024 static int hclge_pci_init(struct hclge_dev *hdev)
5025 {
5026 struct pci_dev *pdev = hdev->pdev;
5027 struct hclge_hw *hw;
5028 int ret;
5029
5030 ret = pci_enable_device(pdev);
5031 if (ret) {
5032 dev_err(&pdev->dev, "failed to enable PCI device\n");
5033 goto err_no_drvdata;
5034 }
5035
5036 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5037 if (ret) {
5038 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5039 if (ret) {
5040 dev_err(&pdev->dev,
5041 "can't set consistent PCI DMA");
5042 goto err_disable_device;
5043 }
5044 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5045 }
5046
5047 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5048 if (ret) {
5049 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5050 goto err_disable_device;
5051 }
5052
5053 pci_set_master(pdev);
5054 hw = &hdev->hw;
5055 hw->back = hdev;
5056 hw->io_base = pcim_iomap(pdev, 2, 0);
5057 if (!hw->io_base) {
5058 dev_err(&pdev->dev, "Can't map configuration register space\n");
5059 ret = -ENOMEM;
5060 goto err_clr_master;
5061 }
5062
5063 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5064
5065 return 0;
5066 err_clr_master:
5067 pci_clear_master(pdev);
5068 pci_release_regions(pdev);
5069 err_disable_device:
5070 pci_disable_device(pdev);
5071 err_no_drvdata:
5072 pci_set_drvdata(pdev, NULL);
5073
5074 return ret;
5075 }
5076
5077 static void hclge_pci_uninit(struct hclge_dev *hdev)
5078 {
5079 struct pci_dev *pdev = hdev->pdev;
5080
5081 pci_free_irq_vectors(pdev);
5082 pci_clear_master(pdev);
5083 pci_release_mem_regions(pdev);
5084 pci_disable_device(pdev);
5085 }
5086
5087 static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5088 {
5089 struct pci_dev *pdev = ae_dev->pdev;
5090 struct hclge_dev *hdev;
5091 int ret;
5092
5093 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5094 if (!hdev) {
5095 ret = -ENOMEM;
5096 goto err_hclge_dev;
5097 }
5098
5099 hdev->pdev = pdev;
5100 hdev->ae_dev = ae_dev;
5101 hdev->reset_type = HNAE3_NONE_RESET;
5102 hdev->reset_request = 0;
5103 hdev->reset_pending = 0;
5104 ae_dev->priv = hdev;
5105
5106 ret = hclge_pci_init(hdev);
5107 if (ret) {
5108 dev_err(&pdev->dev, "PCI init failed\n");
5109 goto err_pci_init;
5110 }
5111
5112 /* Firmware command queue initialize */
5113 ret = hclge_cmd_queue_init(hdev);
5114 if (ret) {
5115 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
5116 return ret;
5117 }
5118
5119 /* Firmware command initialize */
5120 ret = hclge_cmd_init(hdev);
5121 if (ret)
5122 goto err_cmd_init;
5123
5124 ret = hclge_get_cap(hdev);
5125 if (ret) {
5126 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5127 ret);
5128 return ret;
5129 }
5130
5131 ret = hclge_configure(hdev);
5132 if (ret) {
5133 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5134 return ret;
5135 }
5136
5137 ret = hclge_init_msi(hdev);
5138 if (ret) {
5139 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
5140 return ret;
5141 }
5142
5143 ret = hclge_misc_irq_init(hdev);
5144 if (ret) {
5145 dev_err(&pdev->dev,
5146 "Misc IRQ(vector0) init error, ret = %d.\n",
5147 ret);
5148 return ret;
5149 }
5150
5151 ret = hclge_alloc_tqps(hdev);
5152 if (ret) {
5153 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
5154 return ret;
5155 }
5156
5157 ret = hclge_alloc_vport(hdev);
5158 if (ret) {
5159 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
5160 return ret;
5161 }
5162
5163 ret = hclge_map_tqp(hdev);
5164 if (ret) {
5165 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5166 return ret;
5167 }
5168
5169 ret = hclge_mac_mdio_config(hdev);
5170 if (ret) {
5171 dev_warn(&hdev->pdev->dev,
5172 "mdio config fail ret=%d\n", ret);
5173 return ret;
5174 }
5175
5176 ret = hclge_mac_init(hdev);
5177 if (ret) {
5178 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5179 return ret;
5180 }
5181 ret = hclge_buffer_alloc(hdev);
5182 if (ret) {
5183 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5184 return ret;
5185 }
5186
5187 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5188 if (ret) {
5189 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5190 return ret;
5191 }
5192
5193 ret = hclge_init_vlan_config(hdev);
5194 if (ret) {
5195 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5196 return ret;
5197 }
5198
5199 ret = hclge_tm_schd_init(hdev);
5200 if (ret) {
5201 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5202 return ret;
5203 }
5204
5205 ret = hclge_rss_init_hw(hdev);
5206 if (ret) {
5207 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5208 return ret;
5209 }
5210
5211 hclge_dcb_ops_set(hdev);
5212
5213 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
5214 INIT_WORK(&hdev->service_task, hclge_service_task);
5215 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
5216 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
5217
5218 /* Enable MISC vector(vector0) */
5219 hclge_enable_vector(&hdev->misc_vector, true);
5220
5221 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5222 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5223 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5224 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5225 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5226 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5227
5228 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5229 return 0;
5230
5231 err_cmd_init:
5232 pci_release_regions(pdev);
5233 err_pci_init:
5234 pci_set_drvdata(pdev, NULL);
5235 err_hclge_dev:
5236 return ret;
5237 }
5238
5239 static void hclge_stats_clear(struct hclge_dev *hdev)
5240 {
5241 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5242 }
5243
5244 static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5245 {
5246 struct hclge_dev *hdev = ae_dev->priv;
5247 struct pci_dev *pdev = ae_dev->pdev;
5248 int ret;
5249
5250 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5251
5252 hclge_stats_clear(hdev);
5253
5254 ret = hclge_cmd_init(hdev);
5255 if (ret) {
5256 dev_err(&pdev->dev, "Cmd queue init failed\n");
5257 return ret;
5258 }
5259
5260 ret = hclge_get_cap(hdev);
5261 if (ret) {
5262 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5263 ret);
5264 return ret;
5265 }
5266
5267 ret = hclge_configure(hdev);
5268 if (ret) {
5269 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5270 return ret;
5271 }
5272
5273 ret = hclge_map_tqp(hdev);
5274 if (ret) {
5275 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5276 return ret;
5277 }
5278
5279 ret = hclge_mac_init(hdev);
5280 if (ret) {
5281 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5282 return ret;
5283 }
5284
5285 ret = hclge_buffer_alloc(hdev);
5286 if (ret) {
5287 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
5288 return ret;
5289 }
5290
5291 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5292 if (ret) {
5293 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5294 return ret;
5295 }
5296
5297 ret = hclge_init_vlan_config(hdev);
5298 if (ret) {
5299 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5300 return ret;
5301 }
5302
5303 ret = hclge_tm_schd_init(hdev);
5304 if (ret) {
5305 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
5306 return ret;
5307 }
5308
5309 ret = hclge_rss_init_hw(hdev);
5310 if (ret) {
5311 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5312 return ret;
5313 }
5314
5315 /* Enable MISC vector(vector0) */
5316 hclge_enable_vector(&hdev->misc_vector, true);
5317
5318 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5319 HCLGE_DRIVER_NAME);
5320
5321 return 0;
5322 }
5323
5324 static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5325 {
5326 struct hclge_dev *hdev = ae_dev->priv;
5327 struct hclge_mac *mac = &hdev->hw.mac;
5328
5329 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5330
5331 if (IS_ENABLED(CONFIG_PCI_IOV))
5332 hclge_disable_sriov(hdev);
5333
5334 if (hdev->service_timer.function)
5335 del_timer_sync(&hdev->service_timer);
5336 if (hdev->service_task.func)
5337 cancel_work_sync(&hdev->service_task);
5338 if (hdev->rst_service_task.func)
5339 cancel_work_sync(&hdev->rst_service_task);
5340 if (hdev->mbx_service_task.func)
5341 cancel_work_sync(&hdev->mbx_service_task);
5342
5343 if (mac->phydev)
5344 mdiobus_unregister(mac->mdio_bus);
5345
5346 /* Disable MISC vector(vector0) */
5347 hclge_enable_vector(&hdev->misc_vector, false);
5348 hclge_destroy_cmd_queue(&hdev->hw);
5349 hclge_misc_irq_uninit(hdev);
5350 hclge_pci_uninit(hdev);
5351 ae_dev->priv = NULL;
5352 }
5353
5354 static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5355 {
5356 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5357 struct hclge_vport *vport = hclge_get_vport(handle);
5358 struct hclge_dev *hdev = vport->back;
5359
5360 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5361 }
5362
5363 static void hclge_get_channels(struct hnae3_handle *handle,
5364 struct ethtool_channels *ch)
5365 {
5366 struct hclge_vport *vport = hclge_get_vport(handle);
5367
5368 ch->max_combined = hclge_get_max_channels(handle);
5369 ch->other_count = 1;
5370 ch->max_other = 1;
5371 ch->combined_count = vport->alloc_tqps;
5372 }
5373
5374 static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5375 u16 *free_tqps, u16 *max_rss_size)
5376 {
5377 struct hclge_vport *vport = hclge_get_vport(handle);
5378 struct hclge_dev *hdev = vport->back;
5379 u16 temp_tqps = 0;
5380 int i;
5381
5382 for (i = 0; i < hdev->num_tqps; i++) {
5383 if (!hdev->htqp[i].alloced)
5384 temp_tqps++;
5385 }
5386 *free_tqps = temp_tqps;
5387 *max_rss_size = hdev->rss_size_max;
5388 }
5389
5390 static void hclge_release_tqp(struct hclge_vport *vport)
5391 {
5392 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5393 struct hclge_dev *hdev = vport->back;
5394 int i;
5395
5396 for (i = 0; i < kinfo->num_tqps; i++) {
5397 struct hclge_tqp *tqp =
5398 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5399
5400 tqp->q.handle = NULL;
5401 tqp->q.tqp_index = 0;
5402 tqp->alloced = false;
5403 }
5404
5405 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5406 kinfo->tqp = NULL;
5407 }
5408
5409 static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5410 {
5411 struct hclge_vport *vport = hclge_get_vport(handle);
5412 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5413 struct hclge_dev *hdev = vport->back;
5414 int cur_rss_size = kinfo->rss_size;
5415 int cur_tqps = kinfo->num_tqps;
5416 u16 tc_offset[HCLGE_MAX_TC_NUM];
5417 u16 tc_valid[HCLGE_MAX_TC_NUM];
5418 u16 tc_size[HCLGE_MAX_TC_NUM];
5419 u16 roundup_size;
5420 u32 *rss_indir;
5421 int ret, i;
5422
5423 hclge_release_tqp(vport);
5424
5425 ret = hclge_knic_setup(vport, new_tqps_num);
5426 if (ret) {
5427 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5428 return ret;
5429 }
5430
5431 ret = hclge_map_tqp_to_vport(hdev, vport);
5432 if (ret) {
5433 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5434 return ret;
5435 }
5436
5437 ret = hclge_tm_schd_init(hdev);
5438 if (ret) {
5439 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5440 return ret;
5441 }
5442
5443 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5444 roundup_size = ilog2(roundup_size);
5445 /* Set the RSS TC mode according to the new RSS size */
5446 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5447 tc_valid[i] = 0;
5448
5449 if (!(hdev->hw_tc_map & BIT(i)))
5450 continue;
5451
5452 tc_valid[i] = 1;
5453 tc_size[i] = roundup_size;
5454 tc_offset[i] = kinfo->rss_size * i;
5455 }
5456 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5457 if (ret)
5458 return ret;
5459
5460 /* Reinitializes the rss indirect table according to the new RSS size */
5461 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5462 if (!rss_indir)
5463 return -ENOMEM;
5464
5465 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5466 rss_indir[i] = i % kinfo->rss_size;
5467
5468 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5469 if (ret)
5470 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5471 ret);
5472
5473 kfree(rss_indir);
5474
5475 if (!ret)
5476 dev_info(&hdev->pdev->dev,
5477 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5478 cur_rss_size, kinfo->rss_size,
5479 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5480
5481 return ret;
5482 }
5483
5484 static const struct hnae3_ae_ops hclge_ops = {
5485 .init_ae_dev = hclge_init_ae_dev,
5486 .uninit_ae_dev = hclge_uninit_ae_dev,
5487 .init_client_instance = hclge_init_client_instance,
5488 .uninit_client_instance = hclge_uninit_client_instance,
5489 .map_ring_to_vector = hclge_map_ring_to_vector,
5490 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
5491 .get_vector = hclge_get_vector,
5492 .set_promisc_mode = hclge_set_promisc_mode,
5493 .set_loopback = hclge_set_loopback,
5494 .start = hclge_ae_start,
5495 .stop = hclge_ae_stop,
5496 .get_status = hclge_get_status,
5497 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5498 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5499 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5500 .get_media_type = hclge_get_media_type,
5501 .get_rss_key_size = hclge_get_rss_key_size,
5502 .get_rss_indir_size = hclge_get_rss_indir_size,
5503 .get_rss = hclge_get_rss,
5504 .set_rss = hclge_set_rss,
5505 .set_rss_tuple = hclge_set_rss_tuple,
5506 .get_rss_tuple = hclge_get_rss_tuple,
5507 .get_tc_size = hclge_get_tc_size,
5508 .get_mac_addr = hclge_get_mac_addr,
5509 .set_mac_addr = hclge_set_mac_addr,
5510 .add_uc_addr = hclge_add_uc_addr,
5511 .rm_uc_addr = hclge_rm_uc_addr,
5512 .add_mc_addr = hclge_add_mc_addr,
5513 .rm_mc_addr = hclge_rm_mc_addr,
5514 .set_autoneg = hclge_set_autoneg,
5515 .get_autoneg = hclge_get_autoneg,
5516 .get_pauseparam = hclge_get_pauseparam,
5517 .set_pauseparam = hclge_set_pauseparam,
5518 .set_mtu = hclge_set_mtu,
5519 .reset_queue = hclge_reset_tqp,
5520 .get_stats = hclge_get_stats,
5521 .update_stats = hclge_update_stats,
5522 .get_strings = hclge_get_strings,
5523 .get_sset_count = hclge_get_sset_count,
5524 .get_fw_version = hclge_get_fw_version,
5525 .get_mdix_mode = hclge_get_mdix_mode,
5526 .enable_vlan_filter = hclge_enable_vlan_filter,
5527 .set_vlan_filter = hclge_set_port_vlan_filter,
5528 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
5529 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
5530 .reset_event = hclge_reset_event,
5531 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
5532 .set_channels = hclge_set_channels,
5533 .get_channels = hclge_get_channels,
5534 .get_flowctrl_adv = hclge_get_flowctrl_adv,
5535 };
5536
5537 static struct hnae3_ae_algo ae_algo = {
5538 .ops = &hclge_ops,
5539 .name = HCLGE_NAME,
5540 .pdev_id_table = ae_algo_pci_tbl,
5541 };
5542
5543 static int hclge_init(void)
5544 {
5545 pr_info("%s is initializing\n", HCLGE_NAME);
5546
5547 return hnae3_register_ae_algo(&ae_algo);
5548 }
5549
5550 static void hclge_exit(void)
5551 {
5552 hnae3_unregister_ae_algo(&ae_algo);
5553 }
5554 module_init(hclge_init);
5555 module_exit(hclge_exit);
5556
5557 MODULE_LICENSE("GPL");
5558 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5559 MODULE_DESCRIPTION("HCLGE Driver");
5560 MODULE_VERSION(HCLGE_MOD_VERSION);
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