2 * Copyright (c) 2016-2017 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/device.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/netdevice.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <net/rtnetlink.h>
21 #include "hclge_cmd.h"
22 #include "hclge_dcb.h"
23 #include "hclge_main.h"
24 #include "hclge_mbx.h"
25 #include "hclge_mdio.h"
29 #define HCLGE_NAME "hclge"
30 #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
31 #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
32 #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
33 #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
35 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
36 enum hclge_mta_dmac_sel_type mta_mac_sel
,
38 static int hclge_init_vlan_config(struct hclge_dev
*hdev
);
39 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
);
41 static struct hnae3_ae_algo ae_algo
;
43 static const struct pci_device_id ae_algo_pci_tbl
[] = {
44 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_GE
), 0},
45 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE
), 0},
46 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA
), 0},
47 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_25GE_RDMA_MACSEC
), 0},
48 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA
), 0},
49 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_50GE_RDMA_MACSEC
), 0},
50 {PCI_VDEVICE(HUAWEI
, HNAE3_DEV_ID_100G_RDMA_MACSEC
), 0},
51 /* required last entry */
55 static const char hns3_nic_test_strs
[][ETH_GSTRING_LEN
] = {
57 "Serdes Loopback test",
61 static const struct hclge_comm_stats_str g_all_64bit_stats_string
[] = {
62 {"igu_rx_oversize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt
)},
64 {"igu_rx_undersize_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt
)},
66 {"igu_rx_out_all_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt
)},
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt
)},
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt
)},
73 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt
)},
74 {"egu_tx_out_all_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt
)},
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt
)},
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt
)},
81 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt
)},
82 {"ssu_ppp_mac_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num
)},
84 {"ssu_ppp_host_key_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num
)},
86 {"ppp_ssu_mac_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num
)},
88 {"ppp_ssu_host_rlt_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num
)},
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num
)},
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num
)},
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num
)},
97 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num
)}
100 static const struct hclge_comm_stats_str g_all_32bit_stats_string
[] = {
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt
)},
103 {"igu_rx_no_eof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt
)},
105 {"igu_rx_no_sof_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt
)},
108 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt
)},
109 {"ssu_full_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num
)},
111 {"ssu_part_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num
)},
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num
)},
116 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num
)},
118 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num
)},
120 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt
)},
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt
)},
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt
)},
125 {"qcn_fb_invaild_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt
)},
127 {"rx_packet_tc0_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt
)},
129 {"rx_packet_tc1_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt
)},
131 {"rx_packet_tc2_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt
)},
133 {"rx_packet_tc3_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt
)},
135 {"rx_packet_tc4_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt
)},
137 {"rx_packet_tc5_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt
)},
139 {"rx_packet_tc6_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt
)},
141 {"rx_packet_tc7_in_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt
)},
143 {"rx_packet_tc0_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt
)},
145 {"rx_packet_tc1_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt
)},
147 {"rx_packet_tc2_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt
)},
149 {"rx_packet_tc3_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt
)},
151 {"rx_packet_tc4_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt
)},
153 {"rx_packet_tc5_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt
)},
155 {"rx_packet_tc6_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt
)},
157 {"rx_packet_tc7_out_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt
)},
159 {"tx_packet_tc0_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt
)},
161 {"tx_packet_tc1_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt
)},
163 {"tx_packet_tc2_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt
)},
165 {"tx_packet_tc3_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt
)},
167 {"tx_packet_tc4_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt
)},
169 {"tx_packet_tc5_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt
)},
171 {"tx_packet_tc6_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt
)},
173 {"tx_packet_tc7_in_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt
)},
175 {"tx_packet_tc0_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt
)},
177 {"tx_packet_tc1_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt
)},
179 {"tx_packet_tc2_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt
)},
181 {"tx_packet_tc3_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt
)},
183 {"tx_packet_tc4_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt
)},
185 {"tx_packet_tc5_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt
)},
187 {"tx_packet_tc6_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt
)},
189 {"tx_packet_tc7_out_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt
)},
191 {"pkt_curr_buf_tc0_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt
)},
193 {"pkt_curr_buf_tc1_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt
)},
195 {"pkt_curr_buf_tc2_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt
)},
197 {"pkt_curr_buf_tc3_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt
)},
199 {"pkt_curr_buf_tc4_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt
)},
201 {"pkt_curr_buf_tc5_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt
)},
203 {"pkt_curr_buf_tc6_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt
)},
205 {"pkt_curr_buf_tc7_cnt",
206 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt
)},
208 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num
)},
209 {"lo_pri_unicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num
)},
211 {"hi_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num
)},
213 {"lo_pri_multicast_rlt_drop_num",
214 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num
)},
215 {"rx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt
)},
217 {"tx_oq_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt
)},
219 {"nic_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt
)},
221 {"roc_l2_err_drop_pkt_cnt",
222 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt
)}
225 static const struct hclge_comm_stats_str g_mac_stats_string
[] = {
226 {"mac_tx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num
)},
228 {"mac_rx_mac_pause_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num
)},
230 {"mac_tx_pfc_pri0_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num
)},
232 {"mac_tx_pfc_pri1_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num
)},
234 {"mac_tx_pfc_pri2_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num
)},
236 {"mac_tx_pfc_pri3_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num
)},
238 {"mac_tx_pfc_pri4_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num
)},
240 {"mac_tx_pfc_pri5_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num
)},
242 {"mac_tx_pfc_pri6_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num
)},
244 {"mac_tx_pfc_pri7_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num
)},
246 {"mac_rx_pfc_pri0_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num
)},
248 {"mac_rx_pfc_pri1_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num
)},
250 {"mac_rx_pfc_pri2_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num
)},
252 {"mac_rx_pfc_pri3_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num
)},
254 {"mac_rx_pfc_pri4_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num
)},
256 {"mac_rx_pfc_pri5_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num
)},
258 {"mac_rx_pfc_pri6_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num
)},
260 {"mac_rx_pfc_pri7_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num
)},
262 {"mac_tx_total_pkt_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num
)},
264 {"mac_tx_total_oct_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num
)},
266 {"mac_tx_good_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num
)},
268 {"mac_tx_bad_pkt_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num
)},
270 {"mac_tx_good_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num
)},
272 {"mac_tx_bad_oct_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num
)},
274 {"mac_tx_uni_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num
)},
276 {"mac_tx_multi_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num
)},
278 {"mac_tx_broad_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num
)},
280 {"mac_tx_undersize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num
)},
282 {"mac_tx_oversize_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num
)},
284 {"mac_tx_64_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num
)},
286 {"mac_tx_65_127_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num
)},
288 {"mac_tx_128_255_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num
)},
290 {"mac_tx_256_511_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num
)},
292 {"mac_tx_512_1023_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num
)},
294 {"mac_tx_1024_1518_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num
)},
296 {"mac_tx_1519_max_oct_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num
)},
298 {"mac_rx_total_pkt_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num
)},
300 {"mac_rx_total_oct_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num
)},
302 {"mac_rx_good_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num
)},
304 {"mac_rx_bad_pkt_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num
)},
306 {"mac_rx_good_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num
)},
308 {"mac_rx_bad_oct_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num
)},
310 {"mac_rx_uni_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num
)},
312 {"mac_rx_multi_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num
)},
314 {"mac_rx_broad_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num
)},
316 {"mac_rx_undersize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num
)},
318 {"mac_rx_oversize_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num
)},
320 {"mac_rx_64_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num
)},
322 {"mac_rx_65_127_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num
)},
324 {"mac_rx_128_255_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num
)},
326 {"mac_rx_256_511_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num
)},
328 {"mac_rx_512_1023_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num
)},
330 {"mac_rx_1024_1518_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num
)},
332 {"mac_rx_1519_max_oct_pkt_num",
333 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num
)},
335 {"mac_tx_fragment_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num
)},
337 {"mac_tx_undermin_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num
)},
339 {"mac_tx_jabber_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num
)},
341 {"mac_tx_err_all_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num
)},
343 {"mac_tx_from_app_good_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num
)},
345 {"mac_tx_from_app_bad_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num
)},
347 {"mac_rx_fragment_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num
)},
349 {"mac_rx_undermin_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num
)},
351 {"mac_rx_jabber_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num
)},
353 {"mac_rx_fcs_err_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num
)},
355 {"mac_rx_send_app_good_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num
)},
357 {"mac_rx_send_app_bad_pkt_num",
358 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num
)}
361 static int hclge_64_bit_update_stats(struct hclge_dev
*hdev
)
363 #define HCLGE_64_BIT_CMD_NUM 5
364 #define HCLGE_64_BIT_RTN_DATANUM 4
365 u64
*data
= (u64
*)(&hdev
->hw_stats
.all_64_bit_stats
);
366 struct hclge_desc desc
[HCLGE_64_BIT_CMD_NUM
];
371 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_64_BIT
, true);
372 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_64_BIT_CMD_NUM
);
374 dev_err(&hdev
->pdev
->dev
,
375 "Get 64 bit pkt stats fail, status = %d.\n", ret
);
379 for (i
= 0; i
< HCLGE_64_BIT_CMD_NUM
; i
++) {
380 if (unlikely(i
== 0)) {
381 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
382 n
= HCLGE_64_BIT_RTN_DATANUM
- 1;
384 desc_data
= (__le64
*)(&desc
[i
]);
385 n
= HCLGE_64_BIT_RTN_DATANUM
;
387 for (k
= 0; k
< n
; k
++) {
388 *data
++ += le64_to_cpu(*desc_data
);
396 static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats
*stats
)
398 stats
->pkt_curr_buf_cnt
= 0;
399 stats
->pkt_curr_buf_tc0_cnt
= 0;
400 stats
->pkt_curr_buf_tc1_cnt
= 0;
401 stats
->pkt_curr_buf_tc2_cnt
= 0;
402 stats
->pkt_curr_buf_tc3_cnt
= 0;
403 stats
->pkt_curr_buf_tc4_cnt
= 0;
404 stats
->pkt_curr_buf_tc5_cnt
= 0;
405 stats
->pkt_curr_buf_tc6_cnt
= 0;
406 stats
->pkt_curr_buf_tc7_cnt
= 0;
409 static int hclge_32_bit_update_stats(struct hclge_dev
*hdev
)
411 #define HCLGE_32_BIT_CMD_NUM 8
412 #define HCLGE_32_BIT_RTN_DATANUM 8
414 struct hclge_desc desc
[HCLGE_32_BIT_CMD_NUM
];
415 struct hclge_32_bit_stats
*all_32_bit_stats
;
421 all_32_bit_stats
= &hdev
->hw_stats
.all_32_bit_stats
;
422 data
= (u64
*)(&all_32_bit_stats
->egu_tx_1588_pkt
);
424 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_32_BIT
, true);
425 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_32_BIT_CMD_NUM
);
427 dev_err(&hdev
->pdev
->dev
,
428 "Get 32 bit pkt stats fail, status = %d.\n", ret
);
433 hclge_reset_partial_32bit_counter(all_32_bit_stats
);
434 for (i
= 0; i
< HCLGE_32_BIT_CMD_NUM
; i
++) {
435 if (unlikely(i
== 0)) {
436 __le16
*desc_data_16bit
;
438 all_32_bit_stats
->igu_rx_err_pkt
+=
439 le32_to_cpu(desc
[i
].data
[0]);
441 desc_data_16bit
= (__le16
*)&desc
[i
].data
[1];
442 all_32_bit_stats
->igu_rx_no_eof_pkt
+=
443 le16_to_cpu(*desc_data_16bit
);
446 all_32_bit_stats
->igu_rx_no_sof_pkt
+=
447 le16_to_cpu(*desc_data_16bit
);
449 desc_data
= &desc
[i
].data
[2];
450 n
= HCLGE_32_BIT_RTN_DATANUM
- 4;
452 desc_data
= (__le32
*)&desc
[i
];
453 n
= HCLGE_32_BIT_RTN_DATANUM
;
455 for (k
= 0; k
< n
; k
++) {
456 *data
++ += le32_to_cpu(*desc_data
);
464 static int hclge_mac_update_stats(struct hclge_dev
*hdev
)
466 #define HCLGE_MAC_CMD_NUM 17
467 #define HCLGE_RTN_DATA_NUM 4
469 u64
*data
= (u64
*)(&hdev
->hw_stats
.mac_stats
);
470 struct hclge_desc desc
[HCLGE_MAC_CMD_NUM
];
475 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_STATS_MAC
, true);
476 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_MAC_CMD_NUM
);
478 dev_err(&hdev
->pdev
->dev
,
479 "Get MAC pkt stats fail, status = %d.\n", ret
);
484 for (i
= 0; i
< HCLGE_MAC_CMD_NUM
; i
++) {
485 if (unlikely(i
== 0)) {
486 desc_data
= (__le64
*)(&desc
[i
].data
[0]);
487 n
= HCLGE_RTN_DATA_NUM
- 2;
489 desc_data
= (__le64
*)(&desc
[i
]);
490 n
= HCLGE_RTN_DATA_NUM
;
492 for (k
= 0; k
< n
; k
++) {
493 *data
++ += le64_to_cpu(*desc_data
);
501 static int hclge_tqps_update_stats(struct hnae3_handle
*handle
)
503 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
504 struct hclge_vport
*vport
= hclge_get_vport(handle
);
505 struct hclge_dev
*hdev
= vport
->back
;
506 struct hnae3_queue
*queue
;
507 struct hclge_desc desc
[1];
508 struct hclge_tqp
*tqp
;
511 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
512 queue
= handle
->kinfo
.tqp
[i
];
513 tqp
= container_of(queue
, struct hclge_tqp
, q
);
514 /* command : HCLGE_OPC_QUERY_IGU_STAT */
515 hclge_cmd_setup_basic_desc(&desc
[0],
516 HCLGE_OPC_QUERY_RX_STATUS
,
519 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
520 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
522 dev_err(&hdev
->pdev
->dev
,
523 "Query tqp stat fail, status = %d,queue = %d\n",
527 tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
+=
528 le32_to_cpu(desc
[0].data
[4]);
531 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
532 queue
= handle
->kinfo
.tqp
[i
];
533 tqp
= container_of(queue
, struct hclge_tqp
, q
);
534 /* command : HCLGE_OPC_QUERY_IGU_STAT */
535 hclge_cmd_setup_basic_desc(&desc
[0],
536 HCLGE_OPC_QUERY_TX_STATUS
,
539 desc
[0].data
[0] = cpu_to_le32((tqp
->index
& 0x1ff));
540 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
542 dev_err(&hdev
->pdev
->dev
,
543 "Query tqp stat fail, status = %d,queue = %d\n",
547 tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
+=
548 le32_to_cpu(desc
[0].data
[4]);
554 static u64
*hclge_tqps_get_stats(struct hnae3_handle
*handle
, u64
*data
)
556 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
557 struct hclge_tqp
*tqp
;
561 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
562 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
563 *buff
++ = tqp
->tqp_stats
.rcb_tx_ring_pktnum_rcd
;
566 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
567 tqp
= container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
568 *buff
++ = tqp
->tqp_stats
.rcb_rx_ring_pktnum_rcd
;
574 static int hclge_tqps_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
576 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
578 return kinfo
->num_tqps
* (2);
581 static u8
*hclge_tqps_get_strings(struct hnae3_handle
*handle
, u8
*data
)
583 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
587 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
588 struct hclge_tqp
*tqp
= container_of(handle
->kinfo
.tqp
[i
],
589 struct hclge_tqp
, q
);
590 snprintf(buff
, ETH_GSTRING_LEN
, "txq#%d_pktnum_rcd",
592 buff
= buff
+ ETH_GSTRING_LEN
;
595 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
596 struct hclge_tqp
*tqp
= container_of(kinfo
->tqp
[i
],
597 struct hclge_tqp
, q
);
598 snprintf(buff
, ETH_GSTRING_LEN
, "rxq#%d_pktnum_rcd",
600 buff
= buff
+ ETH_GSTRING_LEN
;
606 static u64
*hclge_comm_get_stats(void *comm_stats
,
607 const struct hclge_comm_stats_str strs
[],
613 for (i
= 0; i
< size
; i
++)
614 buf
[i
] = HCLGE_STATS_READ(comm_stats
, strs
[i
].offset
);
619 static u8
*hclge_comm_get_strings(u32 stringset
,
620 const struct hclge_comm_stats_str strs
[],
623 char *buff
= (char *)data
;
626 if (stringset
!= ETH_SS_STATS
)
629 for (i
= 0; i
< size
; i
++) {
630 snprintf(buff
, ETH_GSTRING_LEN
,
632 buff
= buff
+ ETH_GSTRING_LEN
;
638 static void hclge_update_netstat(struct hclge_hw_stats
*hw_stats
,
639 struct net_device_stats
*net_stats
)
641 net_stats
->tx_dropped
= 0;
642 net_stats
->rx_dropped
= hw_stats
->all_32_bit_stats
.ssu_full_drop_num
;
643 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ppp_key_drop_num
;
644 net_stats
->rx_dropped
+= hw_stats
->all_32_bit_stats
.ssu_key_drop_num
;
646 net_stats
->rx_errors
= hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
647 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
648 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_eof_pkt
;
649 net_stats
->rx_errors
+= hw_stats
->all_32_bit_stats
.igu_rx_no_sof_pkt
;
650 net_stats
->rx_errors
+= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
652 net_stats
->multicast
= hw_stats
->mac_stats
.mac_tx_multi_pkt_num
;
653 net_stats
->multicast
+= hw_stats
->mac_stats
.mac_rx_multi_pkt_num
;
655 net_stats
->rx_crc_errors
= hw_stats
->mac_stats
.mac_rx_fcs_err_pkt_num
;
656 net_stats
->rx_length_errors
=
657 hw_stats
->mac_stats
.mac_rx_undersize_pkt_num
;
658 net_stats
->rx_length_errors
+=
659 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
660 net_stats
->rx_over_errors
=
661 hw_stats
->mac_stats
.mac_rx_oversize_pkt_num
;
664 static void hclge_update_stats_for_all(struct hclge_dev
*hdev
)
666 struct hnae3_handle
*handle
;
669 handle
= &hdev
->vport
[0].nic
;
670 if (handle
->client
) {
671 status
= hclge_tqps_update_stats(handle
);
673 dev_err(&hdev
->pdev
->dev
,
674 "Update TQPS stats fail, status = %d.\n",
679 status
= hclge_mac_update_stats(hdev
);
681 dev_err(&hdev
->pdev
->dev
,
682 "Update MAC stats fail, status = %d.\n", status
);
684 status
= hclge_32_bit_update_stats(hdev
);
686 dev_err(&hdev
->pdev
->dev
,
687 "Update 32 bit stats fail, status = %d.\n",
690 hclge_update_netstat(&hdev
->hw_stats
, &handle
->kinfo
.netdev
->stats
);
693 static void hclge_update_stats(struct hnae3_handle
*handle
,
694 struct net_device_stats
*net_stats
)
696 struct hclge_vport
*vport
= hclge_get_vport(handle
);
697 struct hclge_dev
*hdev
= vport
->back
;
698 struct hclge_hw_stats
*hw_stats
= &hdev
->hw_stats
;
701 status
= hclge_mac_update_stats(hdev
);
703 dev_err(&hdev
->pdev
->dev
,
704 "Update MAC stats fail, status = %d.\n",
707 status
= hclge_32_bit_update_stats(hdev
);
709 dev_err(&hdev
->pdev
->dev
,
710 "Update 32 bit stats fail, status = %d.\n",
713 status
= hclge_64_bit_update_stats(hdev
);
715 dev_err(&hdev
->pdev
->dev
,
716 "Update 64 bit stats fail, status = %d.\n",
719 status
= hclge_tqps_update_stats(handle
);
721 dev_err(&hdev
->pdev
->dev
,
722 "Update TQPS stats fail, status = %d.\n",
725 hclge_update_netstat(hw_stats
, net_stats
);
728 static int hclge_get_sset_count(struct hnae3_handle
*handle
, int stringset
)
730 #define HCLGE_LOOPBACK_TEST_FLAGS 0x7
732 struct hclge_vport
*vport
= hclge_get_vport(handle
);
733 struct hclge_dev
*hdev
= vport
->back
;
736 /* Loopback test support rules:
737 * mac: only GE mode support
738 * serdes: all mac mode will support include GE/XGE/LGE/CGE
739 * phy: only support when phy device exist on board
741 if (stringset
== ETH_SS_TEST
) {
742 /* clear loopback bit flags at first */
743 handle
->flags
= (handle
->flags
& (~HCLGE_LOOPBACK_TEST_FLAGS
));
744 if (hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_10M
||
745 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_100M
||
746 hdev
->hw
.mac
.speed
== HCLGE_MAC_SPEED_1G
) {
748 handle
->flags
|= HNAE3_SUPPORT_MAC_LOOPBACK
;
752 } else if (stringset
== ETH_SS_STATS
) {
753 count
= ARRAY_SIZE(g_mac_stats_string
) +
754 ARRAY_SIZE(g_all_32bit_stats_string
) +
755 ARRAY_SIZE(g_all_64bit_stats_string
) +
756 hclge_tqps_get_sset_count(handle
, stringset
);
762 static void hclge_get_strings(struct hnae3_handle
*handle
,
766 u8
*p
= (char *)data
;
769 if (stringset
== ETH_SS_STATS
) {
770 size
= ARRAY_SIZE(g_mac_stats_string
);
771 p
= hclge_comm_get_strings(stringset
,
775 size
= ARRAY_SIZE(g_all_32bit_stats_string
);
776 p
= hclge_comm_get_strings(stringset
,
777 g_all_32bit_stats_string
,
780 size
= ARRAY_SIZE(g_all_64bit_stats_string
);
781 p
= hclge_comm_get_strings(stringset
,
782 g_all_64bit_stats_string
,
785 p
= hclge_tqps_get_strings(handle
, p
);
786 } else if (stringset
== ETH_SS_TEST
) {
787 if (handle
->flags
& HNAE3_SUPPORT_MAC_LOOPBACK
) {
789 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_MAC
],
791 p
+= ETH_GSTRING_LEN
;
793 if (handle
->flags
& HNAE3_SUPPORT_SERDES_LOOPBACK
) {
795 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_SERDES
],
797 p
+= ETH_GSTRING_LEN
;
799 if (handle
->flags
& HNAE3_SUPPORT_PHY_LOOPBACK
) {
801 hns3_nic_test_strs
[HNAE3_MAC_INTER_LOOP_PHY
],
803 p
+= ETH_GSTRING_LEN
;
808 static void hclge_get_stats(struct hnae3_handle
*handle
, u64
*data
)
810 struct hclge_vport
*vport
= hclge_get_vport(handle
);
811 struct hclge_dev
*hdev
= vport
->back
;
814 p
= hclge_comm_get_stats(&hdev
->hw_stats
.mac_stats
,
816 ARRAY_SIZE(g_mac_stats_string
),
818 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_32_bit_stats
,
819 g_all_32bit_stats_string
,
820 ARRAY_SIZE(g_all_32bit_stats_string
),
822 p
= hclge_comm_get_stats(&hdev
->hw_stats
.all_64_bit_stats
,
823 g_all_64bit_stats_string
,
824 ARRAY_SIZE(g_all_64bit_stats_string
),
826 p
= hclge_tqps_get_stats(handle
, p
);
829 static int hclge_parse_func_status(struct hclge_dev
*hdev
,
830 struct hclge_func_status_cmd
*status
)
832 if (!(status
->pf_state
& HCLGE_PF_STATE_DONE
))
835 /* Set the pf to main pf */
836 if (status
->pf_state
& HCLGE_PF_STATE_MAIN
)
837 hdev
->flag
|= HCLGE_FLAG_MAIN
;
839 hdev
->flag
&= ~HCLGE_FLAG_MAIN
;
844 static int hclge_query_function_status(struct hclge_dev
*hdev
)
846 struct hclge_func_status_cmd
*req
;
847 struct hclge_desc desc
;
851 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_FUNC_STATUS
, true);
852 req
= (struct hclge_func_status_cmd
*)desc
.data
;
855 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
857 dev_err(&hdev
->pdev
->dev
,
858 "query function status failed %d.\n",
864 /* Check pf reset is done */
867 usleep_range(1000, 2000);
868 } while (timeout
++ < 5);
870 ret
= hclge_parse_func_status(hdev
, req
);
875 static int hclge_query_pf_resource(struct hclge_dev
*hdev
)
877 struct hclge_pf_res_cmd
*req
;
878 struct hclge_desc desc
;
881 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_PF_RSRC
, true);
882 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
884 dev_err(&hdev
->pdev
->dev
,
885 "query pf resource failed %d.\n", ret
);
889 req
= (struct hclge_pf_res_cmd
*)desc
.data
;
890 hdev
->num_tqps
= __le16_to_cpu(req
->tqp_num
);
891 hdev
->pkt_buf_size
= __le16_to_cpu(req
->buf_size
) << HCLGE_BUF_UNIT_S
;
893 if (hnae3_dev_roce_supported(hdev
)) {
895 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
896 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
898 /* PF should have NIC vectors and Roce vectors,
899 * NIC vectors are queued before Roce vectors.
901 hdev
->num_msi
= hdev
->num_roce_msi
+ HCLGE_ROCE_VECTOR_OFFSET
;
904 hnae_get_field(__le16_to_cpu(req
->pf_intr_vector_number
),
905 HCLGE_PF_VEC_NUM_M
, HCLGE_PF_VEC_NUM_S
);
911 static int hclge_parse_speed(int speed_cmd
, int *speed
)
915 *speed
= HCLGE_MAC_SPEED_10M
;
918 *speed
= HCLGE_MAC_SPEED_100M
;
921 *speed
= HCLGE_MAC_SPEED_1G
;
924 *speed
= HCLGE_MAC_SPEED_10G
;
927 *speed
= HCLGE_MAC_SPEED_25G
;
930 *speed
= HCLGE_MAC_SPEED_40G
;
933 *speed
= HCLGE_MAC_SPEED_50G
;
936 *speed
= HCLGE_MAC_SPEED_100G
;
945 static void hclge_parse_cfg(struct hclge_cfg
*cfg
, struct hclge_desc
*desc
)
947 struct hclge_cfg_param_cmd
*req
;
948 u64 mac_addr_tmp_high
;
952 req
= (struct hclge_cfg_param_cmd
*)desc
[0].data
;
954 /* get the configuration */
955 cfg
->vmdq_vport_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
958 cfg
->tc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
959 HCLGE_CFG_TC_NUM_M
, HCLGE_CFG_TC_NUM_S
);
960 cfg
->tqp_desc_num
= hnae_get_field(__le32_to_cpu(req
->param
[0]),
961 HCLGE_CFG_TQP_DESC_N_M
,
962 HCLGE_CFG_TQP_DESC_N_S
);
964 cfg
->phy_addr
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
965 HCLGE_CFG_PHY_ADDR_M
,
966 HCLGE_CFG_PHY_ADDR_S
);
967 cfg
->media_type
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
968 HCLGE_CFG_MEDIA_TP_M
,
969 HCLGE_CFG_MEDIA_TP_S
);
970 cfg
->rx_buf_len
= hnae_get_field(__le32_to_cpu(req
->param
[1]),
971 HCLGE_CFG_RX_BUF_LEN_M
,
972 HCLGE_CFG_RX_BUF_LEN_S
);
973 /* get mac_address */
974 mac_addr_tmp
= __le32_to_cpu(req
->param
[2]);
975 mac_addr_tmp_high
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
976 HCLGE_CFG_MAC_ADDR_H_M
,
977 HCLGE_CFG_MAC_ADDR_H_S
);
979 mac_addr_tmp
|= (mac_addr_tmp_high
<< 31) << 1;
981 cfg
->default_speed
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
982 HCLGE_CFG_DEFAULT_SPEED_M
,
983 HCLGE_CFG_DEFAULT_SPEED_S
);
984 cfg
->rss_size_max
= hnae_get_field(__le32_to_cpu(req
->param
[3]),
985 HCLGE_CFG_RSS_SIZE_M
,
986 HCLGE_CFG_RSS_SIZE_S
);
988 for (i
= 0; i
< ETH_ALEN
; i
++)
989 cfg
->mac_addr
[i
] = (mac_addr_tmp
>> (8 * i
)) & 0xff;
991 req
= (struct hclge_cfg_param_cmd
*)desc
[1].data
;
992 cfg
->numa_node_map
= __le32_to_cpu(req
->param
[0]);
995 /* hclge_get_cfg: query the static parameter from flash
996 * @hdev: pointer to struct hclge_dev
997 * @hcfg: the config structure to be getted
999 static int hclge_get_cfg(struct hclge_dev
*hdev
, struct hclge_cfg
*hcfg
)
1001 struct hclge_desc desc
[HCLGE_PF_CFG_DESC_NUM
];
1002 struct hclge_cfg_param_cmd
*req
;
1005 for (i
= 0; i
< HCLGE_PF_CFG_DESC_NUM
; i
++) {
1008 req
= (struct hclge_cfg_param_cmd
*)desc
[i
].data
;
1009 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_GET_CFG_PARAM
,
1011 hnae_set_field(offset
, HCLGE_CFG_OFFSET_M
,
1012 HCLGE_CFG_OFFSET_S
, i
* HCLGE_CFG_RD_LEN_BYTES
);
1013 /* Len should be united by 4 bytes when send to hardware */
1014 hnae_set_field(offset
, HCLGE_CFG_RD_LEN_M
, HCLGE_CFG_RD_LEN_S
,
1015 HCLGE_CFG_RD_LEN_BYTES
/ HCLGE_CFG_RD_LEN_UNIT
);
1016 req
->offset
= cpu_to_le32(offset
);
1019 ret
= hclge_cmd_send(&hdev
->hw
, desc
, HCLGE_PF_CFG_DESC_NUM
);
1021 dev_err(&hdev
->pdev
->dev
,
1022 "get config failed %d.\n", ret
);
1026 hclge_parse_cfg(hcfg
, desc
);
1030 static int hclge_get_cap(struct hclge_dev
*hdev
)
1034 ret
= hclge_query_function_status(hdev
);
1036 dev_err(&hdev
->pdev
->dev
,
1037 "query function status error %d.\n", ret
);
1041 /* get pf resource */
1042 ret
= hclge_query_pf_resource(hdev
);
1044 dev_err(&hdev
->pdev
->dev
,
1045 "query pf resource error %d.\n", ret
);
1052 static int hclge_configure(struct hclge_dev
*hdev
)
1054 struct hclge_cfg cfg
;
1057 ret
= hclge_get_cfg(hdev
, &cfg
);
1059 dev_err(&hdev
->pdev
->dev
, "get mac mode error %d.\n", ret
);
1063 hdev
->num_vmdq_vport
= cfg
.vmdq_vport_num
;
1064 hdev
->base_tqp_pid
= 0;
1065 hdev
->rss_size_max
= cfg
.rss_size_max
;
1066 hdev
->rx_buf_len
= cfg
.rx_buf_len
;
1067 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, cfg
.mac_addr
);
1068 hdev
->hw
.mac
.media_type
= cfg
.media_type
;
1069 hdev
->hw
.mac
.phy_addr
= cfg
.phy_addr
;
1070 hdev
->num_desc
= cfg
.tqp_desc_num
;
1071 hdev
->tm_info
.num_pg
= 1;
1072 hdev
->tc_max
= cfg
.tc_num
;
1073 hdev
->tm_info
.hw_pfc_map
= 0;
1075 ret
= hclge_parse_speed(cfg
.default_speed
, &hdev
->hw
.mac
.speed
);
1077 dev_err(&hdev
->pdev
->dev
, "Get wrong speed ret=%d.\n", ret
);
1081 if ((hdev
->tc_max
> HNAE3_MAX_TC
) ||
1082 (hdev
->tc_max
< 1)) {
1083 dev_warn(&hdev
->pdev
->dev
, "TC num = %d.\n",
1088 /* Dev does not support DCB */
1089 if (!hnae3_dev_dcb_supported(hdev
)) {
1093 hdev
->pfc_max
= hdev
->tc_max
;
1096 hdev
->tm_info
.num_tc
= hdev
->tc_max
;
1098 /* Currently not support uncontiuous tc */
1099 for (i
= 0; i
< hdev
->tm_info
.num_tc
; i
++)
1100 hnae_set_bit(hdev
->hw_tc_map
, i
, 1);
1102 hdev
->tx_sch_mode
= HCLGE_FLAG_TC_BASE_SCH_MODE
;
1107 static int hclge_config_tso(struct hclge_dev
*hdev
, int tso_mss_min
,
1110 struct hclge_cfg_tso_status_cmd
*req
;
1111 struct hclge_desc desc
;
1114 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TSO_GENERIC_CONFIG
, false);
1116 req
= (struct hclge_cfg_tso_status_cmd
*)desc
.data
;
1119 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1120 HCLGE_TSO_MSS_MIN_S
, tso_mss_min
);
1121 req
->tso_mss_min
= cpu_to_le16(tso_mss
);
1124 hnae_set_field(tso_mss
, HCLGE_TSO_MSS_MIN_M
,
1125 HCLGE_TSO_MSS_MIN_S
, tso_mss_max
);
1126 req
->tso_mss_max
= cpu_to_le16(tso_mss
);
1128 return hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1131 static int hclge_alloc_tqps(struct hclge_dev
*hdev
)
1133 struct hclge_tqp
*tqp
;
1136 hdev
->htqp
= devm_kcalloc(&hdev
->pdev
->dev
, hdev
->num_tqps
,
1137 sizeof(struct hclge_tqp
), GFP_KERNEL
);
1143 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
1144 tqp
->dev
= &hdev
->pdev
->dev
;
1147 tqp
->q
.ae_algo
= &ae_algo
;
1148 tqp
->q
.buf_size
= hdev
->rx_buf_len
;
1149 tqp
->q
.desc_num
= hdev
->num_desc
;
1150 tqp
->q
.io_base
= hdev
->hw
.io_base
+ HCLGE_TQP_REG_OFFSET
+
1151 i
* HCLGE_TQP_REG_SIZE
;
1159 static int hclge_map_tqps_to_func(struct hclge_dev
*hdev
, u16 func_id
,
1160 u16 tqp_pid
, u16 tqp_vid
, bool is_pf
)
1162 struct hclge_tqp_map_cmd
*req
;
1163 struct hclge_desc desc
;
1166 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_SET_TQP_MAP
, false);
1168 req
= (struct hclge_tqp_map_cmd
*)desc
.data
;
1169 req
->tqp_id
= cpu_to_le16(tqp_pid
);
1170 req
->tqp_vf
= func_id
;
1171 req
->tqp_flag
= !is_pf
<< HCLGE_TQP_MAP_TYPE_B
|
1172 1 << HCLGE_TQP_MAP_EN_B
;
1173 req
->tqp_vid
= cpu_to_le16(tqp_vid
);
1175 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1177 dev_err(&hdev
->pdev
->dev
, "TQP map failed %d.\n",
1185 static int hclge_assign_tqp(struct hclge_vport
*vport
,
1186 struct hnae3_queue
**tqp
, u16 num_tqps
)
1188 struct hclge_dev
*hdev
= vport
->back
;
1191 for (i
= 0, alloced
= 0; i
< hdev
->num_tqps
&&
1192 alloced
< num_tqps
; i
++) {
1193 if (!hdev
->htqp
[i
].alloced
) {
1194 hdev
->htqp
[i
].q
.handle
= &vport
->nic
;
1195 hdev
->htqp
[i
].q
.tqp_index
= alloced
;
1196 tqp
[alloced
] = &hdev
->htqp
[i
].q
;
1197 hdev
->htqp
[i
].alloced
= true;
1201 vport
->alloc_tqps
= num_tqps
;
1206 static int hclge_knic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1208 struct hnae3_handle
*nic
= &vport
->nic
;
1209 struct hnae3_knic_private_info
*kinfo
= &nic
->kinfo
;
1210 struct hclge_dev
*hdev
= vport
->back
;
1213 kinfo
->num_desc
= hdev
->num_desc
;
1214 kinfo
->rx_buf_len
= hdev
->rx_buf_len
;
1215 kinfo
->num_tc
= min_t(u16
, num_tqps
, hdev
->tm_info
.num_tc
);
1217 = min_t(u16
, hdev
->rss_size_max
, num_tqps
/ kinfo
->num_tc
);
1218 kinfo
->num_tqps
= kinfo
->rss_size
* kinfo
->num_tc
;
1220 for (i
= 0; i
< HNAE3_MAX_TC
; i
++) {
1221 if (hdev
->hw_tc_map
& BIT(i
)) {
1222 kinfo
->tc_info
[i
].enable
= true;
1223 kinfo
->tc_info
[i
].tqp_offset
= i
* kinfo
->rss_size
;
1224 kinfo
->tc_info
[i
].tqp_count
= kinfo
->rss_size
;
1225 kinfo
->tc_info
[i
].tc
= i
;
1227 /* Set to default queue if TC is disable */
1228 kinfo
->tc_info
[i
].enable
= false;
1229 kinfo
->tc_info
[i
].tqp_offset
= 0;
1230 kinfo
->tc_info
[i
].tqp_count
= 1;
1231 kinfo
->tc_info
[i
].tc
= 0;
1235 kinfo
->tqp
= devm_kcalloc(&hdev
->pdev
->dev
, kinfo
->num_tqps
,
1236 sizeof(struct hnae3_queue
*), GFP_KERNEL
);
1240 ret
= hclge_assign_tqp(vport
, kinfo
->tqp
, kinfo
->num_tqps
);
1242 dev_err(&hdev
->pdev
->dev
, "fail to assign TQPs %d.\n", ret
);
1249 static int hclge_map_tqp_to_vport(struct hclge_dev
*hdev
,
1250 struct hclge_vport
*vport
)
1252 struct hnae3_handle
*nic
= &vport
->nic
;
1253 struct hnae3_knic_private_info
*kinfo
;
1256 kinfo
= &nic
->kinfo
;
1257 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
1258 struct hclge_tqp
*q
=
1259 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
1263 is_pf
= !(vport
->vport_id
);
1264 ret
= hclge_map_tqps_to_func(hdev
, vport
->vport_id
, q
->index
,
1273 static int hclge_map_tqp(struct hclge_dev
*hdev
)
1275 struct hclge_vport
*vport
= hdev
->vport
;
1278 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1279 for (i
= 0; i
< num_vport
; i
++) {
1282 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
1292 static void hclge_unic_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1294 /* this would be initialized later */
1297 static int hclge_vport_setup(struct hclge_vport
*vport
, u16 num_tqps
)
1299 struct hnae3_handle
*nic
= &vport
->nic
;
1300 struct hclge_dev
*hdev
= vport
->back
;
1303 nic
->pdev
= hdev
->pdev
;
1304 nic
->ae_algo
= &ae_algo
;
1305 nic
->numa_node_mask
= hdev
->numa_node_mask
;
1307 if (hdev
->ae_dev
->dev_type
== HNAE3_DEV_KNIC
) {
1308 ret
= hclge_knic_setup(vport
, num_tqps
);
1310 dev_err(&hdev
->pdev
->dev
, "knic setup failed %d\n",
1315 hclge_unic_setup(vport
, num_tqps
);
1321 static int hclge_alloc_vport(struct hclge_dev
*hdev
)
1323 struct pci_dev
*pdev
= hdev
->pdev
;
1324 struct hclge_vport
*vport
;
1330 /* We need to alloc a vport for main NIC of PF */
1331 num_vport
= hdev
->num_vmdq_vport
+ hdev
->num_req_vfs
+ 1;
1333 if (hdev
->num_tqps
< num_vport
)
1334 num_vport
= hdev
->num_tqps
;
1336 /* Alloc the same number of TQPs for every vport */
1337 tqp_per_vport
= hdev
->num_tqps
/ num_vport
;
1338 tqp_main_vport
= tqp_per_vport
+ hdev
->num_tqps
% num_vport
;
1340 vport
= devm_kcalloc(&pdev
->dev
, num_vport
, sizeof(struct hclge_vport
),
1345 hdev
->vport
= vport
;
1346 hdev
->num_alloc_vport
= num_vport
;
1348 #ifdef CONFIG_PCI_IOV
1350 if (hdev
->num_req_vfs
) {
1351 dev_info(&pdev
->dev
, "active VFs(%d) found, enabling SRIOV\n",
1353 ret
= pci_enable_sriov(hdev
->pdev
, hdev
->num_req_vfs
);
1355 hdev
->num_alloc_vfs
= 0;
1356 dev_err(&pdev
->dev
, "SRIOV enable failed %d\n",
1361 hdev
->num_alloc_vfs
= hdev
->num_req_vfs
;
1364 for (i
= 0; i
< num_vport
; i
++) {
1366 vport
->vport_id
= i
;
1369 ret
= hclge_vport_setup(vport
, tqp_main_vport
);
1371 ret
= hclge_vport_setup(vport
, tqp_per_vport
);
1374 "vport setup failed for vport %d, %d\n",
1385 static int hclge_cmd_alloc_tx_buff(struct hclge_dev
*hdev
,
1386 struct hclge_pkt_buf_alloc
*buf_alloc
)
1388 /* TX buffer size is unit by 128 byte */
1389 #define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1390 #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1391 struct hclge_tx_buff_alloc_cmd
*req
;
1392 struct hclge_desc desc
;
1396 req
= (struct hclge_tx_buff_alloc_cmd
*)desc
.data
;
1398 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_TX_BUFF_ALLOC
, 0);
1399 for (i
= 0; i
< HCLGE_TC_NUM
; i
++) {
1400 u32 buf_size
= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1402 req
->tx_pkt_buff
[i
] =
1403 cpu_to_le16((buf_size
>> HCLGE_BUF_SIZE_UNIT_SHIFT
) |
1404 HCLGE_BUF_SIZE_UPDATE_EN_MSK
);
1407 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1409 dev_err(&hdev
->pdev
->dev
, "tx buffer alloc cmd failed %d.\n",
1417 static int hclge_tx_buffer_alloc(struct hclge_dev
*hdev
,
1418 struct hclge_pkt_buf_alloc
*buf_alloc
)
1420 int ret
= hclge_cmd_alloc_tx_buff(hdev
, buf_alloc
);
1423 dev_err(&hdev
->pdev
->dev
,
1424 "tx buffer alloc failed %d\n", ret
);
1431 static int hclge_get_tc_num(struct hclge_dev
*hdev
)
1435 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1436 if (hdev
->hw_tc_map
& BIT(i
))
1441 static int hclge_get_pfc_enalbe_num(struct hclge_dev
*hdev
)
1445 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1446 if (hdev
->hw_tc_map
& BIT(i
) &&
1447 hdev
->tm_info
.hw_pfc_map
& BIT(i
))
1452 /* Get the number of pfc enabled TCs, which have private buffer */
1453 static int hclge_get_pfc_priv_num(struct hclge_dev
*hdev
,
1454 struct hclge_pkt_buf_alloc
*buf_alloc
)
1456 struct hclge_priv_buf
*priv
;
1459 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1460 priv
= &buf_alloc
->priv_buf
[i
];
1461 if ((hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1469 /* Get the number of pfc disabled TCs, which have private buffer */
1470 static int hclge_get_no_pfc_priv_num(struct hclge_dev
*hdev
,
1471 struct hclge_pkt_buf_alloc
*buf_alloc
)
1473 struct hclge_priv_buf
*priv
;
1476 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1477 priv
= &buf_alloc
->priv_buf
[i
];
1478 if (hdev
->hw_tc_map
& BIT(i
) &&
1479 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
)) &&
1487 static u32
hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1489 struct hclge_priv_buf
*priv
;
1493 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1494 priv
= &buf_alloc
->priv_buf
[i
];
1496 rx_priv
+= priv
->buf_size
;
1501 static u32
hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc
*buf_alloc
)
1503 u32 i
, total_tx_size
= 0;
1505 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++)
1506 total_tx_size
+= buf_alloc
->priv_buf
[i
].tx_buf_size
;
1508 return total_tx_size
;
1511 static bool hclge_is_rx_buf_ok(struct hclge_dev
*hdev
,
1512 struct hclge_pkt_buf_alloc
*buf_alloc
,
1515 u32 shared_buf_min
, shared_buf_tc
, shared_std
;
1516 int tc_num
, pfc_enable_num
;
1521 tc_num
= hclge_get_tc_num(hdev
);
1522 pfc_enable_num
= hclge_get_pfc_enalbe_num(hdev
);
1524 if (hnae3_dev_dcb_supported(hdev
))
1525 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_DV
;
1527 shared_buf_min
= 2 * hdev
->mps
+ HCLGE_DEFAULT_NON_DCB_DV
;
1529 shared_buf_tc
= pfc_enable_num
* hdev
->mps
+
1530 (tc_num
- pfc_enable_num
) * hdev
->mps
/ 2 +
1532 shared_std
= max_t(u32
, shared_buf_min
, shared_buf_tc
);
1534 rx_priv
= hclge_get_rx_priv_buff_alloced(buf_alloc
);
1535 if (rx_all
<= rx_priv
+ shared_std
)
1538 shared_buf
= rx_all
- rx_priv
;
1539 buf_alloc
->s_buf
.buf_size
= shared_buf
;
1540 buf_alloc
->s_buf
.self
.high
= shared_buf
;
1541 buf_alloc
->s_buf
.self
.low
= 2 * hdev
->mps
;
1543 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1544 if ((hdev
->hw_tc_map
& BIT(i
)) &&
1545 (hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1546 buf_alloc
->s_buf
.tc_thrd
[i
].low
= hdev
->mps
;
1547 buf_alloc
->s_buf
.tc_thrd
[i
].high
= 2 * hdev
->mps
;
1549 buf_alloc
->s_buf
.tc_thrd
[i
].low
= 0;
1550 buf_alloc
->s_buf
.tc_thrd
[i
].high
= hdev
->mps
;
1557 static int hclge_tx_buffer_calc(struct hclge_dev
*hdev
,
1558 struct hclge_pkt_buf_alloc
*buf_alloc
)
1562 total_size
= hdev
->pkt_buf_size
;
1564 /* alloc tx buffer for all enabled tc */
1565 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1566 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1568 if (total_size
< HCLGE_DEFAULT_TX_BUF
)
1571 if (hdev
->hw_tc_map
& BIT(i
))
1572 priv
->tx_buf_size
= HCLGE_DEFAULT_TX_BUF
;
1574 priv
->tx_buf_size
= 0;
1576 total_size
-= priv
->tx_buf_size
;
1582 /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1583 * @hdev: pointer to struct hclge_dev
1584 * @buf_alloc: pointer to buffer calculation data
1585 * @return: 0: calculate sucessful, negative: fail
1587 static int hclge_rx_buffer_calc(struct hclge_dev
*hdev
,
1588 struct hclge_pkt_buf_alloc
*buf_alloc
)
1590 u32 rx_all
= hdev
->pkt_buf_size
;
1591 int no_pfc_priv_num
, pfc_priv_num
;
1592 struct hclge_priv_buf
*priv
;
1595 rx_all
-= hclge_get_tx_buff_alloced(buf_alloc
);
1597 /* When DCB is not supported, rx private
1598 * buffer is not allocated.
1600 if (!hnae3_dev_dcb_supported(hdev
)) {
1601 if (!hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1607 /* step 1, try to alloc private buffer for all enabled tc */
1608 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1609 priv
= &buf_alloc
->priv_buf
[i
];
1610 if (hdev
->hw_tc_map
& BIT(i
)) {
1612 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1613 priv
->wl
.low
= hdev
->mps
;
1614 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1615 priv
->buf_size
= priv
->wl
.high
+
1619 priv
->wl
.high
= 2 * hdev
->mps
;
1620 priv
->buf_size
= priv
->wl
.high
;
1630 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1633 /* step 2, try to decrease the buffer size of
1634 * no pfc TC's private buffer
1636 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1637 priv
= &buf_alloc
->priv_buf
[i
];
1644 if (!(hdev
->hw_tc_map
& BIT(i
)))
1649 if (hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1651 priv
->wl
.high
= priv
->wl
.low
+ hdev
->mps
;
1652 priv
->buf_size
= priv
->wl
.high
+ HCLGE_DEFAULT_DV
;
1655 priv
->wl
.high
= hdev
->mps
;
1656 priv
->buf_size
= priv
->wl
.high
;
1660 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1663 /* step 3, try to reduce the number of pfc disabled TCs,
1664 * which have private buffer
1666 /* get the total no pfc enable TC number, which have private buffer */
1667 no_pfc_priv_num
= hclge_get_no_pfc_priv_num(hdev
, buf_alloc
);
1669 /* let the last to be cleared first */
1670 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1671 priv
= &buf_alloc
->priv_buf
[i
];
1673 if (hdev
->hw_tc_map
& BIT(i
) &&
1674 !(hdev
->tm_info
.hw_pfc_map
& BIT(i
))) {
1675 /* Clear the no pfc TC private buffer */
1683 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1684 no_pfc_priv_num
== 0)
1688 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1691 /* step 4, try to reduce the number of pfc enabled TCs
1692 * which have private buffer.
1694 pfc_priv_num
= hclge_get_pfc_priv_num(hdev
, buf_alloc
);
1696 /* let the last to be cleared first */
1697 for (i
= HCLGE_MAX_TC_NUM
- 1; i
>= 0; i
--) {
1698 priv
= &buf_alloc
->priv_buf
[i
];
1700 if (hdev
->hw_tc_map
& BIT(i
) &&
1701 hdev
->tm_info
.hw_pfc_map
& BIT(i
)) {
1702 /* Reduce the number of pfc TC with private buffer */
1710 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
) ||
1714 if (hclge_is_rx_buf_ok(hdev
, buf_alloc
, rx_all
))
1720 static int hclge_rx_priv_buf_alloc(struct hclge_dev
*hdev
,
1721 struct hclge_pkt_buf_alloc
*buf_alloc
)
1723 struct hclge_rx_priv_buff_cmd
*req
;
1724 struct hclge_desc desc
;
1728 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_PRIV_BUFF_ALLOC
, false);
1729 req
= (struct hclge_rx_priv_buff_cmd
*)desc
.data
;
1731 /* Alloc private buffer TCs */
1732 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
1733 struct hclge_priv_buf
*priv
= &buf_alloc
->priv_buf
[i
];
1736 cpu_to_le16(priv
->buf_size
>> HCLGE_BUF_UNIT_S
);
1738 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B
);
1742 cpu_to_le16((buf_alloc
->s_buf
.buf_size
>> HCLGE_BUF_UNIT_S
) |
1743 (1 << HCLGE_TC0_PRI_BUF_EN_B
));
1745 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1747 dev_err(&hdev
->pdev
->dev
,
1748 "rx private buffer alloc cmd failed %d\n", ret
);
1755 #define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1757 static int hclge_rx_priv_wl_config(struct hclge_dev
*hdev
,
1758 struct hclge_pkt_buf_alloc
*buf_alloc
)
1760 struct hclge_rx_priv_wl_buf
*req
;
1761 struct hclge_priv_buf
*priv
;
1762 struct hclge_desc desc
[2];
1766 for (i
= 0; i
< 2; i
++) {
1767 hclge_cmd_setup_basic_desc(&desc
[i
], HCLGE_OPC_RX_PRIV_WL_ALLOC
,
1769 req
= (struct hclge_rx_priv_wl_buf
*)desc
[i
].data
;
1771 /* The first descriptor set the NEXT bit to 1 */
1773 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1775 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1777 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1778 u32 idx
= i
* HCLGE_TC_NUM_ONE_DESC
+ j
;
1780 priv
= &buf_alloc
->priv_buf
[idx
];
1781 req
->tc_wl
[j
].high
=
1782 cpu_to_le16(priv
->wl
.high
>> HCLGE_BUF_UNIT_S
);
1783 req
->tc_wl
[j
].high
|=
1784 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.high
) <<
1785 HCLGE_RX_PRIV_EN_B
);
1787 cpu_to_le16(priv
->wl
.low
>> HCLGE_BUF_UNIT_S
);
1788 req
->tc_wl
[j
].low
|=
1789 cpu_to_le16(HCLGE_PRIV_ENABLE(priv
->wl
.low
) <<
1790 HCLGE_RX_PRIV_EN_B
);
1794 /* Send 2 descriptor at one time */
1795 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1797 dev_err(&hdev
->pdev
->dev
,
1798 "rx private waterline config cmd failed %d\n",
1805 static int hclge_common_thrd_config(struct hclge_dev
*hdev
,
1806 struct hclge_pkt_buf_alloc
*buf_alloc
)
1808 struct hclge_shared_buf
*s_buf
= &buf_alloc
->s_buf
;
1809 struct hclge_rx_com_thrd
*req
;
1810 struct hclge_desc desc
[2];
1811 struct hclge_tc_thrd
*tc
;
1815 for (i
= 0; i
< 2; i
++) {
1816 hclge_cmd_setup_basic_desc(&desc
[i
],
1817 HCLGE_OPC_RX_COM_THRD_ALLOC
, false);
1818 req
= (struct hclge_rx_com_thrd
*)&desc
[i
].data
;
1820 /* The first descriptor set the NEXT bit to 1 */
1822 desc
[i
].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1824 desc
[i
].flag
&= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
1826 for (j
= 0; j
< HCLGE_TC_NUM_ONE_DESC
; j
++) {
1827 tc
= &s_buf
->tc_thrd
[i
* HCLGE_TC_NUM_ONE_DESC
+ j
];
1829 req
->com_thrd
[j
].high
=
1830 cpu_to_le16(tc
->high
>> HCLGE_BUF_UNIT_S
);
1831 req
->com_thrd
[j
].high
|=
1832 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->high
) <<
1833 HCLGE_RX_PRIV_EN_B
);
1834 req
->com_thrd
[j
].low
=
1835 cpu_to_le16(tc
->low
>> HCLGE_BUF_UNIT_S
);
1836 req
->com_thrd
[j
].low
|=
1837 cpu_to_le16(HCLGE_PRIV_ENABLE(tc
->low
) <<
1838 HCLGE_RX_PRIV_EN_B
);
1842 /* Send 2 descriptors at one time */
1843 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
1845 dev_err(&hdev
->pdev
->dev
,
1846 "common threshold config cmd failed %d\n", ret
);
1852 static int hclge_common_wl_config(struct hclge_dev
*hdev
,
1853 struct hclge_pkt_buf_alloc
*buf_alloc
)
1855 struct hclge_shared_buf
*buf
= &buf_alloc
->s_buf
;
1856 struct hclge_rx_com_wl
*req
;
1857 struct hclge_desc desc
;
1860 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RX_COM_WL_ALLOC
, false);
1862 req
= (struct hclge_rx_com_wl
*)desc
.data
;
1863 req
->com_wl
.high
= cpu_to_le16(buf
->self
.high
>> HCLGE_BUF_UNIT_S
);
1865 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.high
) <<
1866 HCLGE_RX_PRIV_EN_B
);
1868 req
->com_wl
.low
= cpu_to_le16(buf
->self
.low
>> HCLGE_BUF_UNIT_S
);
1870 cpu_to_le16(HCLGE_PRIV_ENABLE(buf
->self
.low
) <<
1871 HCLGE_RX_PRIV_EN_B
);
1873 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
1875 dev_err(&hdev
->pdev
->dev
,
1876 "common waterline config cmd failed %d\n", ret
);
1883 int hclge_buffer_alloc(struct hclge_dev
*hdev
)
1885 struct hclge_pkt_buf_alloc
*pkt_buf
;
1888 pkt_buf
= kzalloc(sizeof(*pkt_buf
), GFP_KERNEL
);
1892 ret
= hclge_tx_buffer_calc(hdev
, pkt_buf
);
1894 dev_err(&hdev
->pdev
->dev
,
1895 "could not calc tx buffer size for all TCs %d\n", ret
);
1899 ret
= hclge_tx_buffer_alloc(hdev
, pkt_buf
);
1901 dev_err(&hdev
->pdev
->dev
,
1902 "could not alloc tx buffers %d\n", ret
);
1906 ret
= hclge_rx_buffer_calc(hdev
, pkt_buf
);
1908 dev_err(&hdev
->pdev
->dev
,
1909 "could not calc rx priv buffer size for all TCs %d\n",
1914 ret
= hclge_rx_priv_buf_alloc(hdev
, pkt_buf
);
1916 dev_err(&hdev
->pdev
->dev
, "could not alloc rx priv buffer %d\n",
1921 if (hnae3_dev_dcb_supported(hdev
)) {
1922 ret
= hclge_rx_priv_wl_config(hdev
, pkt_buf
);
1924 dev_err(&hdev
->pdev
->dev
,
1925 "could not configure rx private waterline %d\n",
1930 ret
= hclge_common_thrd_config(hdev
, pkt_buf
);
1932 dev_err(&hdev
->pdev
->dev
,
1933 "could not configure common threshold %d\n",
1939 ret
= hclge_common_wl_config(hdev
, pkt_buf
);
1941 dev_err(&hdev
->pdev
->dev
,
1942 "could not configure common waterline %d\n", ret
);
1949 static int hclge_init_roce_base_info(struct hclge_vport
*vport
)
1951 struct hnae3_handle
*roce
= &vport
->roce
;
1952 struct hnae3_handle
*nic
= &vport
->nic
;
1954 roce
->rinfo
.num_vectors
= vport
->back
->num_roce_msi
;
1956 if (vport
->back
->num_msi_left
< vport
->roce
.rinfo
.num_vectors
||
1957 vport
->back
->num_msi_left
== 0)
1960 roce
->rinfo
.base_vector
= vport
->back
->roce_base_vector
;
1962 roce
->rinfo
.netdev
= nic
->kinfo
.netdev
;
1963 roce
->rinfo
.roce_io_base
= vport
->back
->hw
.io_base
;
1965 roce
->pdev
= nic
->pdev
;
1966 roce
->ae_algo
= nic
->ae_algo
;
1967 roce
->numa_node_mask
= nic
->numa_node_mask
;
1972 static int hclge_init_msi(struct hclge_dev
*hdev
)
1974 struct pci_dev
*pdev
= hdev
->pdev
;
1978 vectors
= pci_alloc_irq_vectors(pdev
, 1, hdev
->num_msi
,
1979 PCI_IRQ_MSI
| PCI_IRQ_MSIX
);
1982 "failed(%d) to allocate MSI/MSI-X vectors\n",
1986 if (vectors
< hdev
->num_msi
)
1987 dev_warn(&hdev
->pdev
->dev
,
1988 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1989 hdev
->num_msi
, vectors
);
1991 hdev
->num_msi
= vectors
;
1992 hdev
->num_msi_left
= vectors
;
1993 hdev
->base_msi_vector
= pdev
->irq
;
1994 hdev
->roce_base_vector
= hdev
->base_msi_vector
+
1995 HCLGE_ROCE_VECTOR_OFFSET
;
1997 hdev
->vector_status
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
1998 sizeof(u16
), GFP_KERNEL
);
1999 if (!hdev
->vector_status
) {
2000 pci_free_irq_vectors(pdev
);
2004 for (i
= 0; i
< hdev
->num_msi
; i
++)
2005 hdev
->vector_status
[i
] = HCLGE_INVALID_VPORT
;
2007 hdev
->vector_irq
= devm_kcalloc(&pdev
->dev
, hdev
->num_msi
,
2008 sizeof(int), GFP_KERNEL
);
2009 if (!hdev
->vector_irq
) {
2010 pci_free_irq_vectors(pdev
);
2017 static void hclge_check_speed_dup(struct hclge_dev
*hdev
, int duplex
, int speed
)
2019 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2021 if ((speed
== HCLGE_MAC_SPEED_10M
) || (speed
== HCLGE_MAC_SPEED_100M
))
2022 mac
->duplex
= (u8
)duplex
;
2024 mac
->duplex
= HCLGE_MAC_FULL
;
2029 int hclge_cfg_mac_speed_dup(struct hclge_dev
*hdev
, int speed
, u8 duplex
)
2031 struct hclge_config_mac_speed_dup_cmd
*req
;
2032 struct hclge_desc desc
;
2035 req
= (struct hclge_config_mac_speed_dup_cmd
*)desc
.data
;
2037 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_SPEED_DUP
, false);
2039 hnae_set_bit(req
->speed_dup
, HCLGE_CFG_DUPLEX_B
, !!duplex
);
2042 case HCLGE_MAC_SPEED_10M
:
2043 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2044 HCLGE_CFG_SPEED_S
, 6);
2046 case HCLGE_MAC_SPEED_100M
:
2047 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2048 HCLGE_CFG_SPEED_S
, 7);
2050 case HCLGE_MAC_SPEED_1G
:
2051 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2052 HCLGE_CFG_SPEED_S
, 0);
2054 case HCLGE_MAC_SPEED_10G
:
2055 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2056 HCLGE_CFG_SPEED_S
, 1);
2058 case HCLGE_MAC_SPEED_25G
:
2059 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2060 HCLGE_CFG_SPEED_S
, 2);
2062 case HCLGE_MAC_SPEED_40G
:
2063 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2064 HCLGE_CFG_SPEED_S
, 3);
2066 case HCLGE_MAC_SPEED_50G
:
2067 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2068 HCLGE_CFG_SPEED_S
, 4);
2070 case HCLGE_MAC_SPEED_100G
:
2071 hnae_set_field(req
->speed_dup
, HCLGE_CFG_SPEED_M
,
2072 HCLGE_CFG_SPEED_S
, 5);
2075 dev_err(&hdev
->pdev
->dev
, "invalid speed (%d)\n", speed
);
2079 hnae_set_bit(req
->mac_change_fec_en
, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B
,
2082 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2084 dev_err(&hdev
->pdev
->dev
,
2085 "mac speed/duplex config cmd failed %d.\n", ret
);
2089 hclge_check_speed_dup(hdev
, duplex
, speed
);
2094 static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle
*handle
, int speed
,
2097 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2098 struct hclge_dev
*hdev
= vport
->back
;
2100 return hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2103 static int hclge_query_mac_an_speed_dup(struct hclge_dev
*hdev
, int *speed
,
2106 struct hclge_query_an_speed_dup_cmd
*req
;
2107 struct hclge_desc desc
;
2111 req
= (struct hclge_query_an_speed_dup_cmd
*)desc
.data
;
2113 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_AN_RESULT
, true);
2114 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2116 dev_err(&hdev
->pdev
->dev
,
2117 "mac speed/autoneg/duplex query cmd failed %d\n",
2122 *duplex
= hnae_get_bit(req
->an_syn_dup_speed
, HCLGE_QUERY_DUPLEX_B
);
2123 speed_tmp
= hnae_get_field(req
->an_syn_dup_speed
, HCLGE_QUERY_SPEED_M
,
2124 HCLGE_QUERY_SPEED_S
);
2126 ret
= hclge_parse_speed(speed_tmp
, speed
);
2128 dev_err(&hdev
->pdev
->dev
,
2129 "could not parse speed(=%d), %d\n", speed_tmp
, ret
);
2136 static int hclge_set_autoneg_en(struct hclge_dev
*hdev
, bool enable
)
2138 struct hclge_config_auto_neg_cmd
*req
;
2139 struct hclge_desc desc
;
2143 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_AN_MODE
, false);
2145 req
= (struct hclge_config_auto_neg_cmd
*)desc
.data
;
2146 hnae_set_bit(flag
, HCLGE_MAC_CFG_AN_EN_B
, !!enable
);
2147 req
->cfg_an_cmd_flag
= cpu_to_le32(flag
);
2149 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2151 dev_err(&hdev
->pdev
->dev
, "auto neg set cmd failed %d.\n",
2159 static int hclge_set_autoneg(struct hnae3_handle
*handle
, bool enable
)
2161 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2162 struct hclge_dev
*hdev
= vport
->back
;
2164 return hclge_set_autoneg_en(hdev
, enable
);
2167 static int hclge_get_autoneg(struct hnae3_handle
*handle
)
2169 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2170 struct hclge_dev
*hdev
= vport
->back
;
2171 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
2174 return phydev
->autoneg
;
2176 return hdev
->hw
.mac
.autoneg
;
2179 static int hclge_set_default_mac_vlan_mask(struct hclge_dev
*hdev
,
2183 struct hclge_mac_vlan_mask_entry_cmd
*req
;
2184 struct hclge_desc desc
;
2187 req
= (struct hclge_mac_vlan_mask_entry_cmd
*)desc
.data
;
2188 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_MASK_SET
, false);
2190 hnae_set_bit(req
->vlan_mask
, HCLGE_VLAN_MASK_EN_B
,
2192 ether_addr_copy(req
->mac_mask
, mac_mask
);
2194 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2196 dev_err(&hdev
->pdev
->dev
,
2197 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
2203 static int hclge_mac_init(struct hclge_dev
*hdev
)
2205 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
2206 u8 mac_mask
[ETH_ALEN
] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
2209 ret
= hclge_cfg_mac_speed_dup(hdev
, hdev
->hw
.mac
.speed
, HCLGE_MAC_FULL
);
2211 dev_err(&hdev
->pdev
->dev
,
2212 "Config mac speed dup fail ret=%d\n", ret
);
2218 /* Initialize the MTA table work mode */
2219 hdev
->accept_mta_mc
= true;
2220 hdev
->enable_mta
= true;
2221 hdev
->mta_mac_sel_type
= HCLGE_MAC_ADDR_47_36
;
2223 ret
= hclge_set_mta_filter_mode(hdev
,
2224 hdev
->mta_mac_sel_type
,
2227 dev_err(&hdev
->pdev
->dev
, "set mta filter mode failed %d\n",
2232 ret
= hclge_cfg_func_mta_filter(hdev
, 0, hdev
->accept_mta_mc
);
2234 dev_err(&hdev
->pdev
->dev
,
2235 "set mta filter mode fail ret=%d\n", ret
);
2239 ret
= hclge_set_default_mac_vlan_mask(hdev
, true, mac_mask
);
2241 dev_err(&hdev
->pdev
->dev
,
2242 "set default mac_vlan_mask fail ret=%d\n", ret
);
2247 static void hclge_mbx_task_schedule(struct hclge_dev
*hdev
)
2249 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
))
2250 schedule_work(&hdev
->mbx_service_task
);
2253 static void hclge_reset_task_schedule(struct hclge_dev
*hdev
)
2255 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
))
2256 schedule_work(&hdev
->rst_service_task
);
2259 static void hclge_task_schedule(struct hclge_dev
*hdev
)
2261 if (!test_bit(HCLGE_STATE_DOWN
, &hdev
->state
) &&
2262 !test_bit(HCLGE_STATE_REMOVING
, &hdev
->state
) &&
2263 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
))
2264 (void)schedule_work(&hdev
->service_task
);
2267 static int hclge_get_mac_link_status(struct hclge_dev
*hdev
)
2269 struct hclge_link_status_cmd
*req
;
2270 struct hclge_desc desc
;
2274 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_QUERY_LINK_STATUS
, true);
2275 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2277 dev_err(&hdev
->pdev
->dev
, "get link status cmd failed %d\n",
2282 req
= (struct hclge_link_status_cmd
*)desc
.data
;
2283 link_status
= req
->status
& HCLGE_LINK_STATUS
;
2285 return !!link_status
;
2288 static int hclge_get_mac_phy_link(struct hclge_dev
*hdev
)
2293 mac_state
= hclge_get_mac_link_status(hdev
);
2295 if (hdev
->hw
.mac
.phydev
) {
2296 if (!genphy_read_status(hdev
->hw
.mac
.phydev
))
2297 link_stat
= mac_state
&
2298 hdev
->hw
.mac
.phydev
->link
;
2303 link_stat
= mac_state
;
2309 static void hclge_update_link_status(struct hclge_dev
*hdev
)
2311 struct hnae3_client
*client
= hdev
->nic_client
;
2312 struct hnae3_handle
*handle
;
2318 state
= hclge_get_mac_phy_link(hdev
);
2319 if (state
!= hdev
->hw
.mac
.link
) {
2320 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2321 handle
= &hdev
->vport
[i
].nic
;
2322 client
->ops
->link_status_change(handle
, state
);
2324 hdev
->hw
.mac
.link
= state
;
2328 static int hclge_update_speed_duplex(struct hclge_dev
*hdev
)
2330 struct hclge_mac mac
= hdev
->hw
.mac
;
2335 /* get the speed and duplex as autoneg'result from mac cmd when phy
2338 if (mac
.phydev
|| !mac
.autoneg
)
2341 ret
= hclge_query_mac_an_speed_dup(hdev
, &speed
, &duplex
);
2343 dev_err(&hdev
->pdev
->dev
,
2344 "mac autoneg/speed/duplex query failed %d\n", ret
);
2348 if ((mac
.speed
!= speed
) || (mac
.duplex
!= duplex
)) {
2349 ret
= hclge_cfg_mac_speed_dup(hdev
, speed
, duplex
);
2351 dev_err(&hdev
->pdev
->dev
,
2352 "mac speed/duplex config failed %d\n", ret
);
2360 static int hclge_update_speed_duplex_h(struct hnae3_handle
*handle
)
2362 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2363 struct hclge_dev
*hdev
= vport
->back
;
2365 return hclge_update_speed_duplex(hdev
);
2368 static int hclge_get_status(struct hnae3_handle
*handle
)
2370 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2371 struct hclge_dev
*hdev
= vport
->back
;
2373 hclge_update_link_status(hdev
);
2375 return hdev
->hw
.mac
.link
;
2378 static void hclge_service_timer(struct timer_list
*t
)
2380 struct hclge_dev
*hdev
= from_timer(hdev
, t
, service_timer
);
2382 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
2383 hclge_task_schedule(hdev
);
2386 static void hclge_service_complete(struct hclge_dev
*hdev
)
2388 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
));
2390 /* Flush memory before next watchdog */
2391 smp_mb__before_atomic();
2392 clear_bit(HCLGE_STATE_SERVICE_SCHED
, &hdev
->state
);
2395 static u32
hclge_check_event_cause(struct hclge_dev
*hdev
, u32
*clearval
)
2400 /* fetch the events from their corresponding regs */
2401 rst_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
);
2402 cmdq_src_reg
= hclge_read_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
);
2404 /* Assumption: If by any chance reset and mailbox events are reported
2405 * together then we will only process reset event in this go and will
2406 * defer the processing of the mailbox events. Since, we would have not
2407 * cleared RX CMDQ event this time we would receive again another
2408 * interrupt from H/W just for the mailbox.
2411 /* check for vector0 reset event sources */
2412 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
) & rst_src_reg
) {
2413 set_bit(HNAE3_GLOBAL_RESET
, &hdev
->reset_pending
);
2414 *clearval
= BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B
);
2415 return HCLGE_VECTOR0_EVENT_RST
;
2418 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B
) & rst_src_reg
) {
2419 set_bit(HNAE3_CORE_RESET
, &hdev
->reset_pending
);
2420 *clearval
= BIT(HCLGE_VECTOR0_CORERESET_INT_B
);
2421 return HCLGE_VECTOR0_EVENT_RST
;
2424 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B
) & rst_src_reg
) {
2425 set_bit(HNAE3_IMP_RESET
, &hdev
->reset_pending
);
2426 *clearval
= BIT(HCLGE_VECTOR0_IMPRESET_INT_B
);
2427 return HCLGE_VECTOR0_EVENT_RST
;
2430 /* check for vector0 mailbox(=CMDQ RX) event source */
2431 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
) & cmdq_src_reg
) {
2432 cmdq_src_reg
&= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B
);
2433 *clearval
= cmdq_src_reg
;
2434 return HCLGE_VECTOR0_EVENT_MBX
;
2437 return HCLGE_VECTOR0_EVENT_OTHER
;
2440 static void hclge_clear_event_cause(struct hclge_dev
*hdev
, u32 event_type
,
2443 switch (event_type
) {
2444 case HCLGE_VECTOR0_EVENT_RST
:
2445 hclge_write_dev(&hdev
->hw
, HCLGE_MISC_RESET_STS_REG
, regclr
);
2447 case HCLGE_VECTOR0_EVENT_MBX
:
2448 hclge_write_dev(&hdev
->hw
, HCLGE_VECTOR0_CMDQ_SRC_REG
, regclr
);
2453 static void hclge_enable_vector(struct hclge_misc_vector
*vector
, bool enable
)
2455 writel(enable
? 1 : 0, vector
->addr
);
2458 static irqreturn_t
hclge_misc_irq_handle(int irq
, void *data
)
2460 struct hclge_dev
*hdev
= data
;
2464 hclge_enable_vector(&hdev
->misc_vector
, false);
2465 event_cause
= hclge_check_event_cause(hdev
, &clearval
);
2467 /* vector 0 interrupt is shared with reset and mailbox source events.*/
2468 switch (event_cause
) {
2469 case HCLGE_VECTOR0_EVENT_RST
:
2470 hclge_reset_task_schedule(hdev
);
2472 case HCLGE_VECTOR0_EVENT_MBX
:
2473 /* If we are here then,
2474 * 1. Either we are not handling any mbx task and we are not
2477 * 2. We could be handling a mbx task but nothing more is
2479 * In both cases, we should schedule mbx task as there are more
2480 * mbx messages reported by this interrupt.
2482 hclge_mbx_task_schedule(hdev
);
2485 dev_dbg(&hdev
->pdev
->dev
,
2486 "received unknown or unhandled event of vector0\n");
2490 /* we should clear the source of interrupt */
2491 hclge_clear_event_cause(hdev
, event_cause
, clearval
);
2492 hclge_enable_vector(&hdev
->misc_vector
, true);
2497 static void hclge_free_vector(struct hclge_dev
*hdev
, int vector_id
)
2499 hdev
->vector_status
[vector_id
] = HCLGE_INVALID_VPORT
;
2500 hdev
->num_msi_left
+= 1;
2501 hdev
->num_msi_used
-= 1;
2504 static void hclge_get_misc_vector(struct hclge_dev
*hdev
)
2506 struct hclge_misc_vector
*vector
= &hdev
->misc_vector
;
2508 vector
->vector_irq
= pci_irq_vector(hdev
->pdev
, 0);
2510 vector
->addr
= hdev
->hw
.io_base
+ HCLGE_MISC_VECTOR_REG_BASE
;
2511 hdev
->vector_status
[0] = 0;
2513 hdev
->num_msi_left
-= 1;
2514 hdev
->num_msi_used
+= 1;
2517 static int hclge_misc_irq_init(struct hclge_dev
*hdev
)
2521 hclge_get_misc_vector(hdev
);
2523 /* this would be explicitly freed in the end */
2524 ret
= request_irq(hdev
->misc_vector
.vector_irq
, hclge_misc_irq_handle
,
2525 0, "hclge_misc", hdev
);
2527 hclge_free_vector(hdev
, 0);
2528 dev_err(&hdev
->pdev
->dev
, "request misc irq(%d) fail\n",
2529 hdev
->misc_vector
.vector_irq
);
2535 static void hclge_misc_irq_uninit(struct hclge_dev
*hdev
)
2537 free_irq(hdev
->misc_vector
.vector_irq
, hdev
);
2538 hclge_free_vector(hdev
, 0);
2541 static int hclge_notify_client(struct hclge_dev
*hdev
,
2542 enum hnae3_reset_notify_type type
)
2544 struct hnae3_client
*client
= hdev
->nic_client
;
2547 if (!client
->ops
->reset_notify
)
2550 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
2551 struct hnae3_handle
*handle
= &hdev
->vport
[i
].nic
;
2554 ret
= client
->ops
->reset_notify(handle
, type
);
2562 static int hclge_reset_wait(struct hclge_dev
*hdev
)
2564 #define HCLGE_RESET_WATI_MS 100
2565 #define HCLGE_RESET_WAIT_CNT 5
2566 u32 val
, reg
, reg_bit
;
2569 switch (hdev
->reset_type
) {
2570 case HNAE3_GLOBAL_RESET
:
2571 reg
= HCLGE_GLOBAL_RESET_REG
;
2572 reg_bit
= HCLGE_GLOBAL_RESET_BIT
;
2574 case HNAE3_CORE_RESET
:
2575 reg
= HCLGE_GLOBAL_RESET_REG
;
2576 reg_bit
= HCLGE_CORE_RESET_BIT
;
2578 case HNAE3_FUNC_RESET
:
2579 reg
= HCLGE_FUN_RST_ING
;
2580 reg_bit
= HCLGE_FUN_RST_ING_B
;
2583 dev_err(&hdev
->pdev
->dev
,
2584 "Wait for unsupported reset type: %d\n",
2589 val
= hclge_read_dev(&hdev
->hw
, reg
);
2590 while (hnae_get_bit(val
, reg_bit
) && cnt
< HCLGE_RESET_WAIT_CNT
) {
2591 msleep(HCLGE_RESET_WATI_MS
);
2592 val
= hclge_read_dev(&hdev
->hw
, reg
);
2596 if (cnt
>= HCLGE_RESET_WAIT_CNT
) {
2597 dev_warn(&hdev
->pdev
->dev
,
2598 "Wait for reset timeout: %d\n", hdev
->reset_type
);
2605 static int hclge_func_reset_cmd(struct hclge_dev
*hdev
, int func_id
)
2607 struct hclge_desc desc
;
2608 struct hclge_reset_cmd
*req
= (struct hclge_reset_cmd
*)desc
.data
;
2611 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_RST_TRIGGER
, false);
2612 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_MAC_B
, 0);
2613 hnae_set_bit(req
->mac_func_reset
, HCLGE_CFG_RESET_FUNC_B
, 1);
2614 req
->fun_reset_vfid
= func_id
;
2616 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2618 dev_err(&hdev
->pdev
->dev
,
2619 "send function reset cmd fail, status =%d\n", ret
);
2624 static void hclge_do_reset(struct hclge_dev
*hdev
)
2626 struct pci_dev
*pdev
= hdev
->pdev
;
2629 switch (hdev
->reset_type
) {
2630 case HNAE3_GLOBAL_RESET
:
2631 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2632 hnae_set_bit(val
, HCLGE_GLOBAL_RESET_BIT
, 1);
2633 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2634 dev_info(&pdev
->dev
, "Global Reset requested\n");
2636 case HNAE3_CORE_RESET
:
2637 val
= hclge_read_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
);
2638 hnae_set_bit(val
, HCLGE_CORE_RESET_BIT
, 1);
2639 hclge_write_dev(&hdev
->hw
, HCLGE_GLOBAL_RESET_REG
, val
);
2640 dev_info(&pdev
->dev
, "Core Reset requested\n");
2642 case HNAE3_FUNC_RESET
:
2643 dev_info(&pdev
->dev
, "PF Reset requested\n");
2644 hclge_func_reset_cmd(hdev
, 0);
2645 /* schedule again to check later */
2646 set_bit(HNAE3_FUNC_RESET
, &hdev
->reset_pending
);
2647 hclge_reset_task_schedule(hdev
);
2650 dev_warn(&pdev
->dev
,
2651 "Unsupported reset type: %d\n", hdev
->reset_type
);
2656 static enum hnae3_reset_type
hclge_get_reset_level(struct hclge_dev
*hdev
,
2657 unsigned long *addr
)
2659 enum hnae3_reset_type rst_level
= HNAE3_NONE_RESET
;
2661 /* return the highest priority reset level amongst all */
2662 if (test_bit(HNAE3_GLOBAL_RESET
, addr
))
2663 rst_level
= HNAE3_GLOBAL_RESET
;
2664 else if (test_bit(HNAE3_CORE_RESET
, addr
))
2665 rst_level
= HNAE3_CORE_RESET
;
2666 else if (test_bit(HNAE3_IMP_RESET
, addr
))
2667 rst_level
= HNAE3_IMP_RESET
;
2668 else if (test_bit(HNAE3_FUNC_RESET
, addr
))
2669 rst_level
= HNAE3_FUNC_RESET
;
2671 /* now, clear all other resets */
2672 clear_bit(HNAE3_GLOBAL_RESET
, addr
);
2673 clear_bit(HNAE3_CORE_RESET
, addr
);
2674 clear_bit(HNAE3_IMP_RESET
, addr
);
2675 clear_bit(HNAE3_FUNC_RESET
, addr
);
2680 static void hclge_reset(struct hclge_dev
*hdev
)
2682 /* perform reset of the stack & ae device for a client */
2684 hclge_notify_client(hdev
, HNAE3_DOWN_CLIENT
);
2686 if (!hclge_reset_wait(hdev
)) {
2688 hclge_notify_client(hdev
, HNAE3_UNINIT_CLIENT
);
2689 hclge_reset_ae_dev(hdev
->ae_dev
);
2690 hclge_notify_client(hdev
, HNAE3_INIT_CLIENT
);
2693 /* schedule again to check pending resets later */
2694 set_bit(hdev
->reset_type
, &hdev
->reset_pending
);
2695 hclge_reset_task_schedule(hdev
);
2698 hclge_notify_client(hdev
, HNAE3_UP_CLIENT
);
2701 static void hclge_reset_event(struct hnae3_handle
*handle
,
2702 enum hnae3_reset_type reset
)
2704 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2705 struct hclge_dev
*hdev
= vport
->back
;
2707 dev_info(&hdev
->pdev
->dev
,
2708 "Receive reset event , reset_type is %d", reset
);
2711 case HNAE3_FUNC_RESET
:
2712 case HNAE3_CORE_RESET
:
2713 case HNAE3_GLOBAL_RESET
:
2714 /* request reset & schedule reset task */
2715 set_bit(reset
, &hdev
->reset_request
);
2716 hclge_reset_task_schedule(hdev
);
2719 dev_warn(&hdev
->pdev
->dev
, "Unsupported reset event:%d", reset
);
2724 static void hclge_reset_subtask(struct hclge_dev
*hdev
)
2726 /* check if there is any ongoing reset in the hardware. This status can
2727 * be checked from reset_pending. If there is then, we need to wait for
2728 * hardware to complete reset.
2729 * a. If we are able to figure out in reasonable time that hardware
2730 * has fully resetted then, we can proceed with driver, client
2732 * b. else, we can come back later to check this status so re-sched
2735 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_pending
);
2736 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2739 /* check if we got any *new* reset requests to be honored */
2740 hdev
->reset_type
= hclge_get_reset_level(hdev
, &hdev
->reset_request
);
2741 if (hdev
->reset_type
!= HNAE3_NONE_RESET
)
2742 hclge_do_reset(hdev
);
2744 hdev
->reset_type
= HNAE3_NONE_RESET
;
2747 static void hclge_reset_service_task(struct work_struct
*work
)
2749 struct hclge_dev
*hdev
=
2750 container_of(work
, struct hclge_dev
, rst_service_task
);
2752 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
))
2755 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
2757 hclge_reset_subtask(hdev
);
2759 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
2762 static void hclge_mailbox_service_task(struct work_struct
*work
)
2764 struct hclge_dev
*hdev
=
2765 container_of(work
, struct hclge_dev
, mbx_service_task
);
2767 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
))
2770 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
2772 hclge_mbx_handler(hdev
);
2774 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
2777 static void hclge_service_task(struct work_struct
*work
)
2779 struct hclge_dev
*hdev
=
2780 container_of(work
, struct hclge_dev
, service_task
);
2782 hclge_update_speed_duplex(hdev
);
2783 hclge_update_link_status(hdev
);
2784 hclge_update_stats_for_all(hdev
);
2785 hclge_service_complete(hdev
);
2788 static void hclge_disable_sriov(struct hclge_dev
*hdev
)
2790 /* If our VFs are assigned we cannot shut down SR-IOV
2791 * without causing issues, so just leave the hardware
2792 * available but disabled
2794 if (pci_vfs_assigned(hdev
->pdev
)) {
2795 dev_warn(&hdev
->pdev
->dev
,
2796 "disabling driver while VFs are assigned\n");
2800 pci_disable_sriov(hdev
->pdev
);
2803 struct hclge_vport
*hclge_get_vport(struct hnae3_handle
*handle
)
2805 /* VF handle has no client */
2806 if (!handle
->client
)
2807 return container_of(handle
, struct hclge_vport
, nic
);
2808 else if (handle
->client
->type
== HNAE3_CLIENT_ROCE
)
2809 return container_of(handle
, struct hclge_vport
, roce
);
2811 return container_of(handle
, struct hclge_vport
, nic
);
2814 static int hclge_get_vector(struct hnae3_handle
*handle
, u16 vector_num
,
2815 struct hnae3_vector_info
*vector_info
)
2817 struct hclge_vport
*vport
= hclge_get_vport(handle
);
2818 struct hnae3_vector_info
*vector
= vector_info
;
2819 struct hclge_dev
*hdev
= vport
->back
;
2823 vector_num
= min(hdev
->num_msi_left
, vector_num
);
2825 for (j
= 0; j
< vector_num
; j
++) {
2826 for (i
= 1; i
< hdev
->num_msi
; i
++) {
2827 if (hdev
->vector_status
[i
] == HCLGE_INVALID_VPORT
) {
2828 vector
->vector
= pci_irq_vector(hdev
->pdev
, i
);
2829 vector
->io_addr
= hdev
->hw
.io_base
+
2830 HCLGE_VECTOR_REG_BASE
+
2831 (i
- 1) * HCLGE_VECTOR_REG_OFFSET
+
2833 HCLGE_VECTOR_VF_OFFSET
;
2834 hdev
->vector_status
[i
] = vport
->vport_id
;
2835 hdev
->vector_irq
[i
] = vector
->vector
;
2844 hdev
->num_msi_left
-= alloc
;
2845 hdev
->num_msi_used
+= alloc
;
2850 static int hclge_get_vector_index(struct hclge_dev
*hdev
, int vector
)
2854 for (i
= 0; i
< hdev
->num_msi
; i
++)
2855 if (vector
== hdev
->vector_irq
[i
])
2861 static u32
hclge_get_rss_key_size(struct hnae3_handle
*handle
)
2863 return HCLGE_RSS_KEY_SIZE
;
2866 static u32
hclge_get_rss_indir_size(struct hnae3_handle
*handle
)
2868 return HCLGE_RSS_IND_TBL_SIZE
;
2871 static int hclge_get_rss_algo(struct hclge_dev
*hdev
)
2873 struct hclge_rss_config_cmd
*req
;
2874 struct hclge_desc desc
;
2878 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
, true);
2880 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2882 dev_err(&hdev
->pdev
->dev
,
2883 "Get link status error, status =%d\n", ret
);
2887 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
2888 rss_hash_algo
= (req
->hash_config
& HCLGE_RSS_HASH_ALGO_MASK
);
2890 if (rss_hash_algo
== HCLGE_RSS_HASH_ALGO_TOEPLITZ
)
2891 return ETH_RSS_HASH_TOP
;
2896 static int hclge_set_rss_algo_key(struct hclge_dev
*hdev
,
2897 const u8 hfunc
, const u8
*key
)
2899 struct hclge_rss_config_cmd
*req
;
2900 struct hclge_desc desc
;
2905 req
= (struct hclge_rss_config_cmd
*)desc
.data
;
2907 for (key_offset
= 0; key_offset
< 3; key_offset
++) {
2908 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_GENERIC_CONFIG
,
2911 req
->hash_config
|= (hfunc
& HCLGE_RSS_HASH_ALGO_MASK
);
2912 req
->hash_config
|= (key_offset
<< HCLGE_RSS_HASH_KEY_OFFSET_B
);
2914 if (key_offset
== 2)
2916 HCLGE_RSS_KEY_SIZE
- HCLGE_RSS_HASH_KEY_NUM
* 2;
2918 key_size
= HCLGE_RSS_HASH_KEY_NUM
;
2920 memcpy(req
->hash_key
,
2921 key
+ key_offset
* HCLGE_RSS_HASH_KEY_NUM
, key_size
);
2923 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2925 dev_err(&hdev
->pdev
->dev
,
2926 "Configure RSS config fail, status = %d\n",
2934 static int hclge_set_rss_indir_table(struct hclge_dev
*hdev
, const u32
*indir
)
2936 struct hclge_rss_indirection_table_cmd
*req
;
2937 struct hclge_desc desc
;
2941 req
= (struct hclge_rss_indirection_table_cmd
*)desc
.data
;
2943 for (i
= 0; i
< HCLGE_RSS_CFG_TBL_NUM
; i
++) {
2944 hclge_cmd_setup_basic_desc
2945 (&desc
, HCLGE_OPC_RSS_INDIR_TABLE
, false);
2947 req
->start_table_index
=
2948 cpu_to_le16(i
* HCLGE_RSS_CFG_TBL_SIZE
);
2949 req
->rss_set_bitmap
= cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK
);
2951 for (j
= 0; j
< HCLGE_RSS_CFG_TBL_SIZE
; j
++)
2952 req
->rss_result
[j
] =
2953 indir
[i
* HCLGE_RSS_CFG_TBL_SIZE
+ j
];
2955 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2957 dev_err(&hdev
->pdev
->dev
,
2958 "Configure rss indir table fail,status = %d\n",
2966 static int hclge_set_rss_tc_mode(struct hclge_dev
*hdev
, u16
*tc_valid
,
2967 u16
*tc_size
, u16
*tc_offset
)
2969 struct hclge_rss_tc_mode_cmd
*req
;
2970 struct hclge_desc desc
;
2974 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_TC_MODE
, false);
2975 req
= (struct hclge_rss_tc_mode_cmd
*)desc
.data
;
2977 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
2980 hnae_set_bit(mode
, HCLGE_RSS_TC_VALID_B
, (tc_valid
[i
] & 0x1));
2981 hnae_set_field(mode
, HCLGE_RSS_TC_SIZE_M
,
2982 HCLGE_RSS_TC_SIZE_S
, tc_size
[i
]);
2983 hnae_set_field(mode
, HCLGE_RSS_TC_OFFSET_M
,
2984 HCLGE_RSS_TC_OFFSET_S
, tc_offset
[i
]);
2986 req
->rss_tc_mode
[i
] = cpu_to_le16(mode
);
2989 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
2991 dev_err(&hdev
->pdev
->dev
,
2992 "Configure rss tc mode fail, status = %d\n", ret
);
2999 static int hclge_set_rss_input_tuple(struct hclge_dev
*hdev
)
3001 struct hclge_rss_input_tuple_cmd
*req
;
3002 struct hclge_desc desc
;
3005 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, false);
3007 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3008 req
->ipv4_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3009 req
->ipv4_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3010 req
->ipv4_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
3011 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3012 req
->ipv6_tcp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3013 req
->ipv6_udp_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3014 req
->ipv6_sctp_en
= HCLGE_RSS_INPUT_TUPLE_SCTP
;
3015 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3016 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3018 dev_err(&hdev
->pdev
->dev
,
3019 "Configure rss input fail, status = %d\n", ret
);
3026 static int hclge_get_rss(struct hnae3_handle
*handle
, u32
*indir
,
3029 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3030 struct hclge_dev
*hdev
= vport
->back
;
3033 /* Get hash algorithm */
3035 *hfunc
= hclge_get_rss_algo(hdev
);
3037 /* Get the RSS Key required by the user */
3039 memcpy(key
, vport
->rss_hash_key
, HCLGE_RSS_KEY_SIZE
);
3041 /* Get indirect table */
3043 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3044 indir
[i
] = vport
->rss_indirection_tbl
[i
];
3049 static int hclge_set_rss(struct hnae3_handle
*handle
, const u32
*indir
,
3050 const u8
*key
, const u8 hfunc
)
3052 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3053 struct hclge_dev
*hdev
= vport
->back
;
3057 /* Set the RSS Hash Key if specififed by the user */
3059 /* Update the shadow RSS key with user specified qids */
3060 memcpy(vport
->rss_hash_key
, key
, HCLGE_RSS_KEY_SIZE
);
3062 if (hfunc
== ETH_RSS_HASH_TOP
||
3063 hfunc
== ETH_RSS_HASH_NO_CHANGE
)
3064 hash_algo
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3067 ret
= hclge_set_rss_algo_key(hdev
, hash_algo
, key
);
3072 /* Update the shadow RSS table with user specified qids */
3073 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
3074 vport
->rss_indirection_tbl
[i
] = indir
[i
];
3076 /* Update the hardware */
3077 ret
= hclge_set_rss_indir_table(hdev
, indir
);
3081 static u8
hclge_get_rss_hash_bits(struct ethtool_rxnfc
*nfc
)
3083 u8 hash_sets
= nfc
->data
& RXH_L4_B_0_1
? HCLGE_S_PORT_BIT
: 0;
3085 if (nfc
->data
& RXH_L4_B_2_3
)
3086 hash_sets
|= HCLGE_D_PORT_BIT
;
3088 hash_sets
&= ~HCLGE_D_PORT_BIT
;
3090 if (nfc
->data
& RXH_IP_SRC
)
3091 hash_sets
|= HCLGE_S_IP_BIT
;
3093 hash_sets
&= ~HCLGE_S_IP_BIT
;
3095 if (nfc
->data
& RXH_IP_DST
)
3096 hash_sets
|= HCLGE_D_IP_BIT
;
3098 hash_sets
&= ~HCLGE_D_IP_BIT
;
3100 if (nfc
->flow_type
== SCTP_V4_FLOW
|| nfc
->flow_type
== SCTP_V6_FLOW
)
3101 hash_sets
|= HCLGE_V_TAG_BIT
;
3106 static int hclge_set_rss_tuple(struct hnae3_handle
*handle
,
3107 struct ethtool_rxnfc
*nfc
)
3109 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3110 struct hclge_dev
*hdev
= vport
->back
;
3111 struct hclge_rss_input_tuple_cmd
*req
;
3112 struct hclge_desc desc
;
3116 if (nfc
->data
& ~(RXH_IP_SRC
| RXH_IP_DST
|
3117 RXH_L4_B_0_1
| RXH_L4_B_2_3
))
3120 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3121 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, true);
3122 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3124 dev_err(&hdev
->pdev
->dev
,
3125 "Read rss tuple fail, status = %d\n", ret
);
3129 hclge_cmd_reuse_desc(&desc
, false);
3131 tuple_sets
= hclge_get_rss_hash_bits(nfc
);
3132 switch (nfc
->flow_type
) {
3134 req
->ipv4_tcp_en
= tuple_sets
;
3137 req
->ipv6_tcp_en
= tuple_sets
;
3140 req
->ipv4_udp_en
= tuple_sets
;
3143 req
->ipv6_udp_en
= tuple_sets
;
3146 req
->ipv4_sctp_en
= tuple_sets
;
3149 if ((nfc
->data
& RXH_L4_B_0_1
) ||
3150 (nfc
->data
& RXH_L4_B_2_3
))
3153 req
->ipv6_sctp_en
= tuple_sets
;
3156 req
->ipv4_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3159 req
->ipv6_fragment_en
= HCLGE_RSS_INPUT_TUPLE_OTHER
;
3165 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3167 dev_err(&hdev
->pdev
->dev
,
3168 "Set rss tuple fail, status = %d\n", ret
);
3173 static int hclge_get_rss_tuple(struct hnae3_handle
*handle
,
3174 struct ethtool_rxnfc
*nfc
)
3176 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3177 struct hclge_dev
*hdev
= vport
->back
;
3178 struct hclge_rss_input_tuple_cmd
*req
;
3179 struct hclge_desc desc
;
3185 req
= (struct hclge_rss_input_tuple_cmd
*)desc
.data
;
3186 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RSS_INPUT_TUPLE
, true);
3187 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3189 dev_err(&hdev
->pdev
->dev
,
3190 "Read rss tuple fail, status = %d\n", ret
);
3194 switch (nfc
->flow_type
) {
3196 tuple_sets
= req
->ipv4_tcp_en
;
3199 tuple_sets
= req
->ipv4_udp_en
;
3202 tuple_sets
= req
->ipv6_tcp_en
;
3205 tuple_sets
= req
->ipv6_udp_en
;
3208 tuple_sets
= req
->ipv4_sctp_en
;
3211 tuple_sets
= req
->ipv6_sctp_en
;
3215 tuple_sets
= HCLGE_S_IP_BIT
| HCLGE_D_IP_BIT
;
3224 if (tuple_sets
& HCLGE_D_PORT_BIT
)
3225 nfc
->data
|= RXH_L4_B_2_3
;
3226 if (tuple_sets
& HCLGE_S_PORT_BIT
)
3227 nfc
->data
|= RXH_L4_B_0_1
;
3228 if (tuple_sets
& HCLGE_D_IP_BIT
)
3229 nfc
->data
|= RXH_IP_DST
;
3230 if (tuple_sets
& HCLGE_S_IP_BIT
)
3231 nfc
->data
|= RXH_IP_SRC
;
3236 static int hclge_get_tc_size(struct hnae3_handle
*handle
)
3238 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3239 struct hclge_dev
*hdev
= vport
->back
;
3241 return hdev
->rss_size_max
;
3244 int hclge_rss_init_hw(struct hclge_dev
*hdev
)
3246 const u8 hfunc
= HCLGE_RSS_HASH_ALGO_TOEPLITZ
;
3247 struct hclge_vport
*vport
= hdev
->vport
;
3248 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
3249 u8 rss_key
[HCLGE_RSS_KEY_SIZE
];
3250 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
3251 u16 tc_size
[HCLGE_MAX_TC_NUM
];
3252 u32
*rss_indir
= NULL
;
3253 u16 rss_size
= 0, roundup_size
;
3257 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
3261 /* Get default RSS key */
3262 netdev_rss_key_fill(rss_key
, HCLGE_RSS_KEY_SIZE
);
3264 /* Initialize RSS indirect table for each vport */
3265 for (j
= 0; j
< hdev
->num_vmdq_vport
+ 1; j
++) {
3266 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++) {
3267 vport
[j
].rss_indirection_tbl
[i
] =
3268 i
% vport
[j
].alloc_rss_size
;
3270 /* vport 0 is for PF */
3274 rss_size
= vport
[j
].alloc_rss_size
;
3275 rss_indir
[i
] = vport
[j
].rss_indirection_tbl
[i
];
3278 ret
= hclge_set_rss_indir_table(hdev
, rss_indir
);
3283 ret
= hclge_set_rss_algo_key(hdev
, hfunc
, key
);
3287 ret
= hclge_set_rss_input_tuple(hdev
);
3291 /* Each TC have the same queue size, and tc_size set to hardware is
3292 * the log2 of roundup power of two of rss_size, the acutal queue
3293 * size is limited by indirection table.
3295 if (rss_size
> HCLGE_RSS_TC_SIZE_7
|| rss_size
== 0) {
3296 dev_err(&hdev
->pdev
->dev
,
3297 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3303 roundup_size
= roundup_pow_of_two(rss_size
);
3304 roundup_size
= ilog2(roundup_size
);
3306 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
3309 if (!(hdev
->hw_tc_map
& BIT(i
)))
3313 tc_size
[i
] = roundup_size
;
3314 tc_offset
[i
] = rss_size
* i
;
3317 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
3325 int hclge_bind_ring_with_vector(struct hclge_vport
*vport
,
3326 int vector_id
, bool en
,
3327 struct hnae3_ring_chain_node
*ring_chain
)
3329 struct hclge_dev
*hdev
= vport
->back
;
3330 struct hnae3_ring_chain_node
*node
;
3331 struct hclge_desc desc
;
3332 struct hclge_ctrl_vector_chain_cmd
*req
3333 = (struct hclge_ctrl_vector_chain_cmd
*)desc
.data
;
3334 enum hclge_cmd_status status
;
3335 enum hclge_opcode_type op
;
3336 u16 tqp_type_and_id
;
3339 op
= en
? HCLGE_OPC_ADD_RING_TO_VECTOR
: HCLGE_OPC_DEL_RING_TO_VECTOR
;
3340 hclge_cmd_setup_basic_desc(&desc
, op
, false);
3341 req
->int_vector_id
= vector_id
;
3344 for (node
= ring_chain
; node
; node
= node
->next
) {
3345 tqp_type_and_id
= le16_to_cpu(req
->tqp_type_and_id
[i
]);
3346 hnae_set_field(tqp_type_and_id
, HCLGE_INT_TYPE_M
,
3348 hnae_get_bit(node
->flag
, HNAE3_RING_TYPE_B
));
3349 hnae_set_field(tqp_type_and_id
, HCLGE_TQP_ID_M
,
3350 HCLGE_TQP_ID_S
, node
->tqp_index
);
3351 req
->tqp_type_and_id
[i
] = cpu_to_le16(tqp_type_and_id
);
3352 if (++i
>= HCLGE_VECTOR_ELEMENTS_PER_CMD
) {
3353 req
->int_cause_num
= HCLGE_VECTOR_ELEMENTS_PER_CMD
;
3354 req
->vfid
= vport
->vport_id
;
3356 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3358 dev_err(&hdev
->pdev
->dev
,
3359 "Map TQP fail, status is %d.\n",
3365 hclge_cmd_setup_basic_desc(&desc
,
3368 req
->int_vector_id
= vector_id
;
3373 req
->int_cause_num
= i
;
3374 req
->vfid
= vport
->vport_id
;
3375 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3377 dev_err(&hdev
->pdev
->dev
,
3378 "Map TQP fail, status is %d.\n", status
);
3386 static int hclge_map_ring_to_vector(struct hnae3_handle
*handle
,
3388 struct hnae3_ring_chain_node
*ring_chain
)
3390 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3391 struct hclge_dev
*hdev
= vport
->back
;
3394 vector_id
= hclge_get_vector_index(hdev
, vector
);
3395 if (vector_id
< 0) {
3396 dev_err(&hdev
->pdev
->dev
,
3397 "Get vector index fail. vector_id =%d\n", vector_id
);
3401 return hclge_bind_ring_with_vector(vport
, vector_id
, true, ring_chain
);
3404 static int hclge_unmap_ring_frm_vector(struct hnae3_handle
*handle
,
3406 struct hnae3_ring_chain_node
*ring_chain
)
3408 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3409 struct hclge_dev
*hdev
= vport
->back
;
3412 vector_id
= hclge_get_vector_index(hdev
, vector
);
3413 if (vector_id
< 0) {
3414 dev_err(&handle
->pdev
->dev
,
3415 "Get vector index fail. ret =%d\n", vector_id
);
3419 ret
= hclge_bind_ring_with_vector(vport
, vector_id
, false, ring_chain
);
3421 dev_err(&handle
->pdev
->dev
,
3422 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3428 /* Free this MSIX or MSI vector */
3429 hclge_free_vector(hdev
, vector_id
);
3434 int hclge_cmd_set_promisc_mode(struct hclge_dev
*hdev
,
3435 struct hclge_promisc_param
*param
)
3437 struct hclge_promisc_cfg_cmd
*req
;
3438 struct hclge_desc desc
;
3441 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_PROMISC_MODE
, false);
3443 req
= (struct hclge_promisc_cfg_cmd
*)desc
.data
;
3444 req
->vf_id
= param
->vf_id
;
3445 req
->flag
= (param
->enable
<< HCLGE_PROMISC_EN_B
);
3447 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3449 dev_err(&hdev
->pdev
->dev
,
3450 "Set promisc mode fail, status is %d.\n", ret
);
3456 void hclge_promisc_param_init(struct hclge_promisc_param
*param
, bool en_uc
,
3457 bool en_mc
, bool en_bc
, int vport_id
)
3462 memset(param
, 0, sizeof(struct hclge_promisc_param
));
3464 param
->enable
= HCLGE_PROMISC_EN_UC
;
3466 param
->enable
|= HCLGE_PROMISC_EN_MC
;
3468 param
->enable
|= HCLGE_PROMISC_EN_BC
;
3469 param
->vf_id
= vport_id
;
3472 static void hclge_set_promisc_mode(struct hnae3_handle
*handle
, u32 en
)
3474 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3475 struct hclge_dev
*hdev
= vport
->back
;
3476 struct hclge_promisc_param param
;
3478 hclge_promisc_param_init(¶m
, en
, en
, true, vport
->vport_id
);
3479 hclge_cmd_set_promisc_mode(hdev
, ¶m
);
3482 static void hclge_cfg_mac_mode(struct hclge_dev
*hdev
, bool enable
)
3484 struct hclge_desc desc
;
3485 struct hclge_config_mac_mode_cmd
*req
=
3486 (struct hclge_config_mac_mode_cmd
*)desc
.data
;
3490 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAC_MODE
, false);
3491 hnae_set_bit(loop_en
, HCLGE_MAC_TX_EN_B
, enable
);
3492 hnae_set_bit(loop_en
, HCLGE_MAC_RX_EN_B
, enable
);
3493 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_TX_B
, enable
);
3494 hnae_set_bit(loop_en
, HCLGE_MAC_PAD_RX_B
, enable
);
3495 hnae_set_bit(loop_en
, HCLGE_MAC_1588_TX_B
, 0);
3496 hnae_set_bit(loop_en
, HCLGE_MAC_1588_RX_B
, 0);
3497 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3498 hnae_set_bit(loop_en
, HCLGE_MAC_LINE_LP_B
, 0);
3499 hnae_set_bit(loop_en
, HCLGE_MAC_FCS_TX_B
, enable
);
3500 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_B
, enable
);
3501 hnae_set_bit(loop_en
, HCLGE_MAC_RX_FCS_STRIP_B
, enable
);
3502 hnae_set_bit(loop_en
, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B
, enable
);
3503 hnae_set_bit(loop_en
, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B
, enable
);
3504 hnae_set_bit(loop_en
, HCLGE_MAC_TX_UNDER_MIN_ERR_B
, enable
);
3505 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3507 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3509 dev_err(&hdev
->pdev
->dev
,
3510 "mac enable fail, ret =%d.\n", ret
);
3513 static int hclge_set_loopback(struct hnae3_handle
*handle
,
3514 enum hnae3_loop loop_mode
, bool en
)
3516 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3517 struct hclge_config_mac_mode_cmd
*req
;
3518 struct hclge_dev
*hdev
= vport
->back
;
3519 struct hclge_desc desc
;
3523 switch (loop_mode
) {
3524 case HNAE3_MAC_INTER_LOOP_MAC
:
3525 req
= (struct hclge_config_mac_mode_cmd
*)&desc
.data
[0];
3526 /* 1 Read out the MAC mode config at first */
3527 hclge_cmd_setup_basic_desc(&desc
,
3528 HCLGE_OPC_CONFIG_MAC_MODE
,
3530 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3532 dev_err(&hdev
->pdev
->dev
,
3533 "mac loopback get fail, ret =%d.\n",
3538 /* 2 Then setup the loopback flag */
3539 loop_en
= le32_to_cpu(req
->txrx_pad_fcs_loop_en
);
3541 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 1);
3543 hnae_set_bit(loop_en
, HCLGE_MAC_APP_LP_B
, 0);
3545 req
->txrx_pad_fcs_loop_en
= cpu_to_le32(loop_en
);
3547 /* 3 Config mac work mode with loopback flag
3548 * and its original configure parameters
3550 hclge_cmd_reuse_desc(&desc
, false);
3551 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3553 dev_err(&hdev
->pdev
->dev
,
3554 "mac loopback set fail, ret =%d.\n", ret
);
3558 dev_err(&hdev
->pdev
->dev
,
3559 "loop_mode %d is not supported\n", loop_mode
);
3566 static int hclge_tqp_enable(struct hclge_dev
*hdev
, int tqp_id
,
3567 int stream_id
, bool enable
)
3569 struct hclge_desc desc
;
3570 struct hclge_cfg_com_tqp_queue_cmd
*req
=
3571 (struct hclge_cfg_com_tqp_queue_cmd
*)desc
.data
;
3574 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CFG_COM_TQP_QUEUE
, false);
3575 req
->tqp_id
= cpu_to_le16(tqp_id
& HCLGE_RING_ID_MASK
);
3576 req
->stream_id
= cpu_to_le16(stream_id
);
3577 req
->enable
|= enable
<< HCLGE_TQP_ENABLE_B
;
3579 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3581 dev_err(&hdev
->pdev
->dev
,
3582 "Tqp enable fail, status =%d.\n", ret
);
3586 static void hclge_reset_tqp_stats(struct hnae3_handle
*handle
)
3588 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3589 struct hnae3_queue
*queue
;
3590 struct hclge_tqp
*tqp
;
3593 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3594 queue
= handle
->kinfo
.tqp
[i
];
3595 tqp
= container_of(queue
, struct hclge_tqp
, q
);
3596 memset(&tqp
->tqp_stats
, 0, sizeof(tqp
->tqp_stats
));
3600 static int hclge_ae_start(struct hnae3_handle
*handle
)
3602 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3603 struct hclge_dev
*hdev
= vport
->back
;
3604 int i
, queue_id
, ret
;
3606 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3607 /* todo clear interrupt */
3609 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
3611 dev_warn(&hdev
->pdev
->dev
,
3612 "Get invalid queue id, ignore it\n");
3616 hclge_tqp_enable(hdev
, queue_id
, 0, true);
3619 hclge_cfg_mac_mode(hdev
, true);
3620 clear_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
3621 mod_timer(&hdev
->service_timer
, jiffies
+ HZ
);
3623 ret
= hclge_mac_start_phy(hdev
);
3627 /* reset tqp stats */
3628 hclge_reset_tqp_stats(handle
);
3633 static void hclge_ae_stop(struct hnae3_handle
*handle
)
3635 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3636 struct hclge_dev
*hdev
= vport
->back
;
3639 for (i
= 0; i
< vport
->alloc_tqps
; i
++) {
3641 queue_id
= hclge_get_queue_id(handle
->kinfo
.tqp
[i
]);
3643 dev_warn(&hdev
->pdev
->dev
,
3644 "Get invalid queue id, ignore it\n");
3648 hclge_tqp_enable(hdev
, queue_id
, 0, false);
3651 hclge_cfg_mac_mode(hdev
, false);
3653 hclge_mac_stop_phy(hdev
);
3655 /* reset tqp stats */
3656 hclge_reset_tqp_stats(handle
);
3659 static int hclge_get_mac_vlan_cmd_status(struct hclge_vport
*vport
,
3660 u16 cmdq_resp
, u8 resp_code
,
3661 enum hclge_mac_vlan_tbl_opcode op
)
3663 struct hclge_dev
*hdev
= vport
->back
;
3664 int return_status
= -EIO
;
3667 dev_err(&hdev
->pdev
->dev
,
3668 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3673 if (op
== HCLGE_MAC_VLAN_ADD
) {
3674 if ((!resp_code
) || (resp_code
== 1)) {
3676 } else if (resp_code
== 2) {
3677 return_status
= -EIO
;
3678 dev_err(&hdev
->pdev
->dev
,
3679 "add mac addr failed for uc_overflow.\n");
3680 } else if (resp_code
== 3) {
3681 return_status
= -EIO
;
3682 dev_err(&hdev
->pdev
->dev
,
3683 "add mac addr failed for mc_overflow.\n");
3685 dev_err(&hdev
->pdev
->dev
,
3686 "add mac addr failed for undefined, code=%d.\n",
3689 } else if (op
== HCLGE_MAC_VLAN_REMOVE
) {
3692 } else if (resp_code
== 1) {
3693 return_status
= -EIO
;
3694 dev_dbg(&hdev
->pdev
->dev
,
3695 "remove mac addr failed for miss.\n");
3697 dev_err(&hdev
->pdev
->dev
,
3698 "remove mac addr failed for undefined, code=%d.\n",
3701 } else if (op
== HCLGE_MAC_VLAN_LKUP
) {
3704 } else if (resp_code
== 1) {
3705 return_status
= -EIO
;
3706 dev_dbg(&hdev
->pdev
->dev
,
3707 "lookup mac addr failed for miss.\n");
3709 dev_err(&hdev
->pdev
->dev
,
3710 "lookup mac addr failed for undefined, code=%d.\n",
3714 return_status
= -EIO
;
3715 dev_err(&hdev
->pdev
->dev
,
3716 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3720 return return_status
;
3723 static int hclge_update_desc_vfid(struct hclge_desc
*desc
, int vfid
, bool clr
)
3728 if (vfid
> 255 || vfid
< 0)
3731 if (vfid
>= 0 && vfid
<= 191) {
3732 word_num
= vfid
/ 32;
3733 bit_num
= vfid
% 32;
3735 desc
[1].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3737 desc
[1].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3739 word_num
= (vfid
- 192) / 32;
3740 bit_num
= vfid
% 32;
3742 desc
[2].data
[word_num
] &= cpu_to_le32(~(1 << bit_num
));
3744 desc
[2].data
[word_num
] |= cpu_to_le32(1 << bit_num
);
3750 static bool hclge_is_all_function_id_zero(struct hclge_desc
*desc
)
3752 #define HCLGE_DESC_NUMBER 3
3753 #define HCLGE_FUNC_NUMBER_PER_DESC 6
3756 for (i
= 0; i
< HCLGE_DESC_NUMBER
; i
++)
3757 for (j
= 0; j
< HCLGE_FUNC_NUMBER_PER_DESC
; j
++)
3758 if (desc
[i
].data
[j
])
3764 static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd
*new_req
,
3767 const unsigned char *mac_addr
= addr
;
3768 u32 high_val
= mac_addr
[2] << 16 | (mac_addr
[3] << 24) |
3769 (mac_addr
[0]) | (mac_addr
[1] << 8);
3770 u32 low_val
= mac_addr
[4] | (mac_addr
[5] << 8);
3772 new_req
->mac_addr_hi32
= cpu_to_le32(high_val
);
3773 new_req
->mac_addr_lo16
= cpu_to_le16(low_val
& 0xffff);
3776 static u16
hclge_get_mac_addr_to_mta_index(struct hclge_vport
*vport
,
3779 u16 high_val
= addr
[1] | (addr
[0] << 8);
3780 struct hclge_dev
*hdev
= vport
->back
;
3781 u32 rsh
= 4 - hdev
->mta_mac_sel_type
;
3782 u16 ret_val
= (high_val
>> rsh
) & 0xfff;
3787 static int hclge_set_mta_filter_mode(struct hclge_dev
*hdev
,
3788 enum hclge_mta_dmac_sel_type mta_mac_sel
,
3791 struct hclge_mta_filter_mode_cmd
*req
;
3792 struct hclge_desc desc
;
3795 req
= (struct hclge_mta_filter_mode_cmd
*)desc
.data
;
3796 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_MODE_CFG
, false);
3798 hnae_set_bit(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_EN_B
,
3800 hnae_set_field(req
->dmac_sel_en
, HCLGE_CFG_MTA_MAC_SEL_M
,
3801 HCLGE_CFG_MTA_MAC_SEL_S
, mta_mac_sel
);
3803 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3805 dev_err(&hdev
->pdev
->dev
,
3806 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3814 int hclge_cfg_func_mta_filter(struct hclge_dev
*hdev
,
3818 struct hclge_cfg_func_mta_filter_cmd
*req
;
3819 struct hclge_desc desc
;
3822 req
= (struct hclge_cfg_func_mta_filter_cmd
*)desc
.data
;
3823 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_MAC_FUNC_CFG
, false);
3825 hnae_set_bit(req
->accept
, HCLGE_CFG_FUNC_MTA_ACCEPT_B
,
3827 req
->function_id
= func_id
;
3829 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3831 dev_err(&hdev
->pdev
->dev
,
3832 "Config func_id enable failed for cmd_send, ret =%d.\n",
3840 static int hclge_set_mta_table_item(struct hclge_vport
*vport
,
3844 struct hclge_dev
*hdev
= vport
->back
;
3845 struct hclge_cfg_func_mta_item_cmd
*req
;
3846 struct hclge_desc desc
;
3850 req
= (struct hclge_cfg_func_mta_item_cmd
*)desc
.data
;
3851 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MTA_TBL_ITEM_CFG
, false);
3852 hnae_set_bit(req
->accept
, HCLGE_CFG_MTA_ITEM_ACCEPT_B
, enable
);
3854 hnae_set_field(item_idx
, HCLGE_CFG_MTA_ITEM_IDX_M
,
3855 HCLGE_CFG_MTA_ITEM_IDX_S
, idx
);
3856 req
->item_idx
= cpu_to_le16(item_idx
);
3858 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3860 dev_err(&hdev
->pdev
->dev
,
3861 "Config mta table item failed for cmd_send, ret =%d.\n",
3869 static int hclge_remove_mac_vlan_tbl(struct hclge_vport
*vport
,
3870 struct hclge_mac_vlan_tbl_entry_cmd
*req
)
3872 struct hclge_dev
*hdev
= vport
->back
;
3873 struct hclge_desc desc
;
3878 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_REMOVE
, false);
3880 memcpy(desc
.data
, req
, sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3882 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3884 dev_err(&hdev
->pdev
->dev
,
3885 "del mac addr failed for cmd_send, ret =%d.\n",
3889 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
3890 retval
= le16_to_cpu(desc
.retval
);
3892 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
3893 HCLGE_MAC_VLAN_REMOVE
);
3896 static int hclge_lookup_mac_vlan_tbl(struct hclge_vport
*vport
,
3897 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
3898 struct hclge_desc
*desc
,
3901 struct hclge_dev
*hdev
= vport
->back
;
3906 hclge_cmd_setup_basic_desc(&desc
[0], HCLGE_OPC_MAC_VLAN_ADD
, true);
3908 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3909 memcpy(desc
[0].data
,
3911 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3912 hclge_cmd_setup_basic_desc(&desc
[1],
3913 HCLGE_OPC_MAC_VLAN_ADD
,
3915 desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3916 hclge_cmd_setup_basic_desc(&desc
[2],
3917 HCLGE_OPC_MAC_VLAN_ADD
,
3919 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 3);
3921 memcpy(desc
[0].data
,
3923 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3924 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 1);
3927 dev_err(&hdev
->pdev
->dev
,
3928 "lookup mac addr failed for cmd_send, ret =%d.\n",
3932 resp_code
= (le32_to_cpu(desc
[0].data
[0]) >> 8) & 0xff;
3933 retval
= le16_to_cpu(desc
[0].retval
);
3935 return hclge_get_mac_vlan_cmd_status(vport
, retval
, resp_code
,
3936 HCLGE_MAC_VLAN_LKUP
);
3939 static int hclge_add_mac_vlan_tbl(struct hclge_vport
*vport
,
3940 struct hclge_mac_vlan_tbl_entry_cmd
*req
,
3941 struct hclge_desc
*mc_desc
)
3943 struct hclge_dev
*hdev
= vport
->back
;
3950 struct hclge_desc desc
;
3952 hclge_cmd_setup_basic_desc(&desc
,
3953 HCLGE_OPC_MAC_VLAN_ADD
,
3955 memcpy(desc
.data
, req
,
3956 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3957 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
3958 resp_code
= (le32_to_cpu(desc
.data
[0]) >> 8) & 0xff;
3959 retval
= le16_to_cpu(desc
.retval
);
3961 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
3963 HCLGE_MAC_VLAN_ADD
);
3965 hclge_cmd_reuse_desc(&mc_desc
[0], false);
3966 mc_desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3967 hclge_cmd_reuse_desc(&mc_desc
[1], false);
3968 mc_desc
[1].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
3969 hclge_cmd_reuse_desc(&mc_desc
[2], false);
3970 mc_desc
[2].flag
&= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT
);
3971 memcpy(mc_desc
[0].data
, req
,
3972 sizeof(struct hclge_mac_vlan_tbl_entry_cmd
));
3973 ret
= hclge_cmd_send(&hdev
->hw
, mc_desc
, 3);
3974 resp_code
= (le32_to_cpu(mc_desc
[0].data
[0]) >> 8) & 0xff;
3975 retval
= le16_to_cpu(mc_desc
[0].retval
);
3977 cfg_status
= hclge_get_mac_vlan_cmd_status(vport
, retval
,
3979 HCLGE_MAC_VLAN_ADD
);
3983 dev_err(&hdev
->pdev
->dev
,
3984 "add mac addr failed for cmd_send, ret =%d.\n",
3992 static int hclge_add_uc_addr(struct hnae3_handle
*handle
,
3993 const unsigned char *addr
)
3995 struct hclge_vport
*vport
= hclge_get_vport(handle
);
3997 return hclge_add_uc_addr_common(vport
, addr
);
4000 int hclge_add_uc_addr_common(struct hclge_vport
*vport
,
4001 const unsigned char *addr
)
4003 struct hclge_dev
*hdev
= vport
->back
;
4004 struct hclge_mac_vlan_tbl_entry_cmd req
;
4005 enum hclge_cmd_status status
;
4006 u16 egress_port
= 0;
4008 /* mac addr check */
4009 if (is_zero_ether_addr(addr
) ||
4010 is_broadcast_ether_addr(addr
) ||
4011 is_multicast_ether_addr(addr
)) {
4012 dev_err(&hdev
->pdev
->dev
,
4013 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4015 is_zero_ether_addr(addr
),
4016 is_broadcast_ether_addr(addr
),
4017 is_multicast_ether_addr(addr
));
4021 memset(&req
, 0, sizeof(req
));
4022 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4023 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4024 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 0);
4025 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4027 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_SW_EN_B
, 0);
4028 hnae_set_bit(egress_port
, HCLGE_MAC_EPORT_TYPE_B
, 0);
4029 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_VFID_M
,
4030 HCLGE_MAC_EPORT_VFID_S
, vport
->vport_id
);
4031 hnae_set_field(egress_port
, HCLGE_MAC_EPORT_PFID_M
,
4032 HCLGE_MAC_EPORT_PFID_S
, 0);
4034 req
.egress_port
= cpu_to_le16(egress_port
);
4036 hclge_prepare_mac_addr(&req
, addr
);
4038 status
= hclge_add_mac_vlan_tbl(vport
, &req
, NULL
);
4043 static int hclge_rm_uc_addr(struct hnae3_handle
*handle
,
4044 const unsigned char *addr
)
4046 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4048 return hclge_rm_uc_addr_common(vport
, addr
);
4051 int hclge_rm_uc_addr_common(struct hclge_vport
*vport
,
4052 const unsigned char *addr
)
4054 struct hclge_dev
*hdev
= vport
->back
;
4055 struct hclge_mac_vlan_tbl_entry_cmd req
;
4056 enum hclge_cmd_status status
;
4058 /* mac addr check */
4059 if (is_zero_ether_addr(addr
) ||
4060 is_broadcast_ether_addr(addr
) ||
4061 is_multicast_ether_addr(addr
)) {
4062 dev_dbg(&hdev
->pdev
->dev
,
4063 "Remove mac err! invalid mac:%pM.\n",
4068 memset(&req
, 0, sizeof(req
));
4069 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4070 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4071 hclge_prepare_mac_addr(&req
, addr
);
4072 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4077 static int hclge_add_mc_addr(struct hnae3_handle
*handle
,
4078 const unsigned char *addr
)
4080 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4082 return hclge_add_mc_addr_common(vport
, addr
);
4085 int hclge_add_mc_addr_common(struct hclge_vport
*vport
,
4086 const unsigned char *addr
)
4088 struct hclge_dev
*hdev
= vport
->back
;
4089 struct hclge_mac_vlan_tbl_entry_cmd req
;
4090 struct hclge_desc desc
[3];
4094 /* mac addr check */
4095 if (!is_multicast_ether_addr(addr
)) {
4096 dev_err(&hdev
->pdev
->dev
,
4097 "Add mc mac err! invalid mac:%pM.\n",
4101 memset(&req
, 0, sizeof(req
));
4102 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4103 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4104 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4105 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4106 hclge_prepare_mac_addr(&req
, addr
);
4107 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4109 /* This mac addr exist, update VFID for it */
4110 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4111 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4113 /* This mac addr do not exist, add new entry for it */
4114 memset(desc
[0].data
, 0, sizeof(desc
[0].data
));
4115 memset(desc
[1].data
, 0, sizeof(desc
[0].data
));
4116 memset(desc
[2].data
, 0, sizeof(desc
[0].data
));
4117 hclge_update_desc_vfid(desc
, vport
->vport_id
, false);
4118 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4121 /* Set MTA table for this MAC address */
4122 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4123 status
= hclge_set_mta_table_item(vport
, tbl_idx
, true);
4128 static int hclge_rm_mc_addr(struct hnae3_handle
*handle
,
4129 const unsigned char *addr
)
4131 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4133 return hclge_rm_mc_addr_common(vport
, addr
);
4136 int hclge_rm_mc_addr_common(struct hclge_vport
*vport
,
4137 const unsigned char *addr
)
4139 struct hclge_dev
*hdev
= vport
->back
;
4140 struct hclge_mac_vlan_tbl_entry_cmd req
;
4141 enum hclge_cmd_status status
;
4142 struct hclge_desc desc
[3];
4145 /* mac addr check */
4146 if (!is_multicast_ether_addr(addr
)) {
4147 dev_dbg(&hdev
->pdev
->dev
,
4148 "Remove mc mac err! invalid mac:%pM.\n",
4153 memset(&req
, 0, sizeof(req
));
4154 hnae_set_bit(req
.flags
, HCLGE_MAC_VLAN_BIT0_EN_B
, 1);
4155 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4156 hnae_set_bit(req
.entry_type
, HCLGE_MAC_VLAN_BIT1_EN_B
, 1);
4157 hnae_set_bit(req
.mc_mac_en
, HCLGE_MAC_VLAN_BIT0_EN_B
, 0);
4158 hclge_prepare_mac_addr(&req
, addr
);
4159 status
= hclge_lookup_mac_vlan_tbl(vport
, &req
, desc
, true);
4161 /* This mac addr exist, remove this handle's VFID for it */
4162 hclge_update_desc_vfid(desc
, vport
->vport_id
, true);
4164 if (hclge_is_all_function_id_zero(desc
))
4165 /* All the vfid is zero, so need to delete this entry */
4166 status
= hclge_remove_mac_vlan_tbl(vport
, &req
);
4168 /* Not all the vfid is zero, update the vfid */
4169 status
= hclge_add_mac_vlan_tbl(vport
, &req
, desc
);
4172 /* This mac addr do not exist, can't delete it */
4173 dev_err(&hdev
->pdev
->dev
,
4174 "Rm multicast mac addr failed, ret = %d.\n",
4179 /* Set MTB table for this MAC address */
4180 tbl_idx
= hclge_get_mac_addr_to_mta_index(vport
, addr
);
4181 status
= hclge_set_mta_table_item(vport
, tbl_idx
, false);
4186 static void hclge_get_mac_addr(struct hnae3_handle
*handle
, u8
*p
)
4188 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4189 struct hclge_dev
*hdev
= vport
->back
;
4191 ether_addr_copy(p
, hdev
->hw
.mac
.mac_addr
);
4194 static int hclge_set_mac_addr(struct hnae3_handle
*handle
, void *p
)
4196 const unsigned char *new_addr
= (const unsigned char *)p
;
4197 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4198 struct hclge_dev
*hdev
= vport
->back
;
4200 /* mac addr check */
4201 if (is_zero_ether_addr(new_addr
) ||
4202 is_broadcast_ether_addr(new_addr
) ||
4203 is_multicast_ether_addr(new_addr
)) {
4204 dev_err(&hdev
->pdev
->dev
,
4205 "Change uc mac err! invalid mac:%p.\n",
4210 hclge_rm_uc_addr(handle
, hdev
->hw
.mac
.mac_addr
);
4212 if (!hclge_add_uc_addr(handle
, new_addr
)) {
4213 ether_addr_copy(hdev
->hw
.mac
.mac_addr
, new_addr
);
4220 static int hclge_set_vlan_filter_ctrl(struct hclge_dev
*hdev
, u8 vlan_type
,
4223 struct hclge_vlan_filter_ctrl_cmd
*req
;
4224 struct hclge_desc desc
;
4227 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_CTRL
, false);
4229 req
= (struct hclge_vlan_filter_ctrl_cmd
*)desc
.data
;
4230 req
->vlan_type
= vlan_type
;
4231 req
->vlan_fe
= filter_en
;
4233 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4235 dev_err(&hdev
->pdev
->dev
, "set vlan filter fail, ret =%d.\n",
4243 #define HCLGE_FILTER_TYPE_VF 0
4244 #define HCLGE_FILTER_TYPE_PORT 1
4246 static void hclge_enable_vlan_filter(struct hnae3_handle
*handle
, bool enable
)
4248 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4249 struct hclge_dev
*hdev
= vport
->back
;
4251 hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, enable
);
4254 int hclge_set_vf_vlan_common(struct hclge_dev
*hdev
, int vfid
,
4255 bool is_kill
, u16 vlan
, u8 qos
, __be16 proto
)
4257 #define HCLGE_MAX_VF_BYTES 16
4258 struct hclge_vlan_filter_vf_cfg_cmd
*req0
;
4259 struct hclge_vlan_filter_vf_cfg_cmd
*req1
;
4260 struct hclge_desc desc
[2];
4265 hclge_cmd_setup_basic_desc(&desc
[0],
4266 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4267 hclge_cmd_setup_basic_desc(&desc
[1],
4268 HCLGE_OPC_VLAN_FILTER_VF_CFG
, false);
4270 desc
[0].flag
|= cpu_to_le16(HCLGE_CMD_FLAG_NEXT
);
4272 vf_byte_off
= vfid
/ 8;
4273 vf_byte_val
= 1 << (vfid
% 8);
4275 req0
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[0].data
;
4276 req1
= (struct hclge_vlan_filter_vf_cfg_cmd
*)desc
[1].data
;
4278 req0
->vlan_id
= cpu_to_le16(vlan
);
4279 req0
->vlan_cfg
= is_kill
;
4281 if (vf_byte_off
< HCLGE_MAX_VF_BYTES
)
4282 req0
->vf_bitmap
[vf_byte_off
] = vf_byte_val
;
4284 req1
->vf_bitmap
[vf_byte_off
- HCLGE_MAX_VF_BYTES
] = vf_byte_val
;
4286 ret
= hclge_cmd_send(&hdev
->hw
, desc
, 2);
4288 dev_err(&hdev
->pdev
->dev
,
4289 "Send vf vlan command fail, ret =%d.\n",
4295 if (!req0
->resp_code
|| req0
->resp_code
== 1)
4298 dev_err(&hdev
->pdev
->dev
,
4299 "Add vf vlan filter fail, ret =%d.\n",
4302 if (!req0
->resp_code
)
4305 dev_err(&hdev
->pdev
->dev
,
4306 "Kill vf vlan filter fail, ret =%d.\n",
4313 static int hclge_set_port_vlan_filter(struct hnae3_handle
*handle
,
4314 __be16 proto
, u16 vlan_id
,
4317 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4318 struct hclge_dev
*hdev
= vport
->back
;
4319 struct hclge_vlan_filter_pf_cfg_cmd
*req
;
4320 struct hclge_desc desc
;
4321 u8 vlan_offset_byte_val
;
4322 u8 vlan_offset_byte
;
4326 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_FILTER_PF_CFG
, false);
4328 vlan_offset_160
= vlan_id
/ 160;
4329 vlan_offset_byte
= (vlan_id
% 160) / 8;
4330 vlan_offset_byte_val
= 1 << (vlan_id
% 8);
4332 req
= (struct hclge_vlan_filter_pf_cfg_cmd
*)desc
.data
;
4333 req
->vlan_offset
= vlan_offset_160
;
4334 req
->vlan_cfg
= is_kill
;
4335 req
->vlan_offset_bitmap
[vlan_offset_byte
] = vlan_offset_byte_val
;
4337 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4339 dev_err(&hdev
->pdev
->dev
,
4340 "port vlan command, send fail, ret =%d.\n",
4345 ret
= hclge_set_vf_vlan_common(hdev
, 0, is_kill
, vlan_id
, 0, proto
);
4347 dev_err(&hdev
->pdev
->dev
,
4348 "Set pf vlan filter config fail, ret =%d.\n",
4356 static int hclge_set_vf_vlan_filter(struct hnae3_handle
*handle
, int vfid
,
4357 u16 vlan
, u8 qos
, __be16 proto
)
4359 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4360 struct hclge_dev
*hdev
= vport
->back
;
4362 if ((vfid
>= hdev
->num_alloc_vfs
) || (vlan
> 4095) || (qos
> 7))
4364 if (proto
!= htons(ETH_P_8021Q
))
4365 return -EPROTONOSUPPORT
;
4367 return hclge_set_vf_vlan_common(hdev
, vfid
, false, vlan
, qos
, proto
);
4370 static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport
*vport
)
4372 struct hclge_tx_vtag_cfg
*vcfg
= &vport
->txvlan_cfg
;
4373 struct hclge_vport_vtag_tx_cfg_cmd
*req
;
4374 struct hclge_dev
*hdev
= vport
->back
;
4375 struct hclge_desc desc
;
4378 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_TX_CFG
, false);
4380 req
= (struct hclge_vport_vtag_tx_cfg_cmd
*)desc
.data
;
4381 req
->def_vlan_tag1
= cpu_to_le16(vcfg
->default_tag1
);
4382 req
->def_vlan_tag2
= cpu_to_le16(vcfg
->default_tag2
);
4383 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_TAG_B
,
4384 vcfg
->accept_tag
? 1 : 0);
4385 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_ACCEPT_UNTAG_B
,
4386 vcfg
->accept_untag
? 1 : 0);
4387 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG1_EN_B
,
4388 vcfg
->insert_tag1_en
? 1 : 0);
4389 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_PORT_INS_TAG2_EN_B
,
4390 vcfg
->insert_tag2_en
? 1 : 0);
4391 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_CFG_NIC_ROCE_SEL_B
, 0);
4393 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4394 req
->vf_bitmap
[req
->vf_offset
] =
4395 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4397 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4399 dev_err(&hdev
->pdev
->dev
,
4400 "Send port txvlan cfg command fail, ret =%d\n",
4406 static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport
*vport
)
4408 struct hclge_rx_vtag_cfg
*vcfg
= &vport
->rxvlan_cfg
;
4409 struct hclge_vport_vtag_rx_cfg_cmd
*req
;
4410 struct hclge_dev
*hdev
= vport
->back
;
4411 struct hclge_desc desc
;
4414 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_VLAN_PORT_RX_CFG
, false);
4416 req
= (struct hclge_vport_vtag_rx_cfg_cmd
*)desc
.data
;
4417 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG1_EN_B
,
4418 vcfg
->strip_tag1_en
? 1 : 0);
4419 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_REM_TAG2_EN_B
,
4420 vcfg
->strip_tag2_en
? 1 : 0);
4421 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG1_EN_B
,
4422 vcfg
->vlan1_vlan_prionly
? 1 : 0);
4423 hnae_set_bit(req
->vport_vlan_cfg
, HCLGE_SHOW_TAG2_EN_B
,
4424 vcfg
->vlan2_vlan_prionly
? 1 : 0);
4426 req
->vf_offset
= vport
->vport_id
/ HCLGE_VF_NUM_PER_CMD
;
4427 req
->vf_bitmap
[req
->vf_offset
] =
4428 1 << (vport
->vport_id
% HCLGE_VF_NUM_PER_BYTE
);
4430 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4432 dev_err(&hdev
->pdev
->dev
,
4433 "Send port rxvlan cfg command fail, ret =%d\n",
4439 static int hclge_set_vlan_protocol_type(struct hclge_dev
*hdev
)
4441 struct hclge_rx_vlan_type_cfg_cmd
*rx_req
;
4442 struct hclge_tx_vlan_type_cfg_cmd
*tx_req
;
4443 struct hclge_desc desc
;
4446 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_TYPE_ID
, false);
4447 rx_req
= (struct hclge_rx_vlan_type_cfg_cmd
*)desc
.data
;
4448 rx_req
->ot_fst_vlan_type
=
4449 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
);
4450 rx_req
->ot_sec_vlan_type
=
4451 cpu_to_le16(hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
);
4452 rx_req
->in_fst_vlan_type
=
4453 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
);
4454 rx_req
->in_sec_vlan_type
=
4455 cpu_to_le16(hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
);
4457 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4459 dev_err(&hdev
->pdev
->dev
,
4460 "Send rxvlan protocol type command fail, ret =%d\n",
4465 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_MAC_VLAN_INSERT
, false);
4467 tx_req
= (struct hclge_tx_vlan_type_cfg_cmd
*)&desc
.data
;
4468 tx_req
->ot_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_ot_vlan_type
);
4469 tx_req
->in_vlan_type
= cpu_to_le16(hdev
->vlan_type_cfg
.tx_in_vlan_type
);
4471 status
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4473 dev_err(&hdev
->pdev
->dev
,
4474 "Send txvlan protocol type command fail, ret =%d\n",
4480 static int hclge_init_vlan_config(struct hclge_dev
*hdev
)
4482 #define HCLGE_DEF_VLAN_TYPE 0x8100
4484 struct hnae3_handle
*handle
;
4485 struct hclge_vport
*vport
;
4489 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_VF
, true);
4493 ret
= hclge_set_vlan_filter_ctrl(hdev
, HCLGE_FILTER_TYPE_PORT
, true);
4497 hdev
->vlan_type_cfg
.rx_in_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4498 hdev
->vlan_type_cfg
.rx_in_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4499 hdev
->vlan_type_cfg
.rx_ot_fst_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4500 hdev
->vlan_type_cfg
.rx_ot_sec_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4501 hdev
->vlan_type_cfg
.tx_ot_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4502 hdev
->vlan_type_cfg
.tx_in_vlan_type
= HCLGE_DEF_VLAN_TYPE
;
4504 ret
= hclge_set_vlan_protocol_type(hdev
);
4508 for (i
= 0; i
< hdev
->num_alloc_vport
; i
++) {
4509 vport
= &hdev
->vport
[i
];
4510 vport
->txvlan_cfg
.accept_tag
= true;
4511 vport
->txvlan_cfg
.accept_untag
= true;
4512 vport
->txvlan_cfg
.insert_tag1_en
= false;
4513 vport
->txvlan_cfg
.insert_tag2_en
= false;
4514 vport
->txvlan_cfg
.default_tag1
= 0;
4515 vport
->txvlan_cfg
.default_tag2
= 0;
4517 ret
= hclge_set_vlan_tx_offload_cfg(vport
);
4521 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4522 vport
->rxvlan_cfg
.strip_tag2_en
= true;
4523 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4524 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4526 ret
= hclge_set_vlan_rx_offload_cfg(vport
);
4531 handle
= &hdev
->vport
[0].nic
;
4532 return hclge_set_port_vlan_filter(handle
, htons(ETH_P_8021Q
), 0, false);
4535 static int hclge_en_hw_strip_rxvtag(struct hnae3_handle
*handle
, bool enable
)
4537 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4539 vport
->rxvlan_cfg
.strip_tag1_en
= false;
4540 vport
->rxvlan_cfg
.strip_tag2_en
= enable
;
4541 vport
->rxvlan_cfg
.vlan1_vlan_prionly
= false;
4542 vport
->rxvlan_cfg
.vlan2_vlan_prionly
= false;
4544 return hclge_set_vlan_rx_offload_cfg(vport
);
4547 static int hclge_set_mtu(struct hnae3_handle
*handle
, int new_mtu
)
4549 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4550 struct hclge_config_max_frm_size_cmd
*req
;
4551 struct hclge_dev
*hdev
= vport
->back
;
4552 struct hclge_desc desc
;
4555 if ((new_mtu
< HCLGE_MAC_MIN_MTU
) || (new_mtu
> HCLGE_MAC_MAX_MTU
))
4558 hdev
->mps
= new_mtu
;
4559 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_CONFIG_MAX_FRM_SIZE
, false);
4561 req
= (struct hclge_config_max_frm_size_cmd
*)desc
.data
;
4562 req
->max_frm_size
= cpu_to_le16(new_mtu
);
4564 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4566 dev_err(&hdev
->pdev
->dev
, "set mtu fail, ret =%d.\n", ret
);
4573 static int hclge_send_reset_tqp_cmd(struct hclge_dev
*hdev
, u16 queue_id
,
4576 struct hclge_reset_tqp_queue_cmd
*req
;
4577 struct hclge_desc desc
;
4580 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, false);
4582 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4583 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4584 hnae_set_bit(req
->reset_req
, HCLGE_TQP_RESET_B
, enable
);
4586 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4588 dev_err(&hdev
->pdev
->dev
,
4589 "Send tqp reset cmd error, status =%d\n", ret
);
4596 static int hclge_get_reset_status(struct hclge_dev
*hdev
, u16 queue_id
)
4598 struct hclge_reset_tqp_queue_cmd
*req
;
4599 struct hclge_desc desc
;
4602 hclge_cmd_setup_basic_desc(&desc
, HCLGE_OPC_RESET_TQP_QUEUE
, true);
4604 req
= (struct hclge_reset_tqp_queue_cmd
*)desc
.data
;
4605 req
->tqp_id
= cpu_to_le16(queue_id
& HCLGE_RING_ID_MASK
);
4607 ret
= hclge_cmd_send(&hdev
->hw
, &desc
, 1);
4609 dev_err(&hdev
->pdev
->dev
,
4610 "Get reset status error, status =%d\n", ret
);
4614 return hnae_get_bit(req
->ready_to_reset
, HCLGE_TQP_RESET_B
);
4617 void hclge_reset_tqp(struct hnae3_handle
*handle
, u16 queue_id
)
4619 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4620 struct hclge_dev
*hdev
= vport
->back
;
4621 int reset_try_times
= 0;
4625 ret
= hclge_tqp_enable(hdev
, queue_id
, 0, false);
4627 dev_warn(&hdev
->pdev
->dev
, "Disable tqp fail, ret = %d\n", ret
);
4631 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, true);
4633 dev_warn(&hdev
->pdev
->dev
,
4634 "Send reset tqp cmd fail, ret = %d\n", ret
);
4638 reset_try_times
= 0;
4639 while (reset_try_times
++ < HCLGE_TQP_RESET_TRY_TIMES
) {
4640 /* Wait for tqp hw reset */
4642 reset_status
= hclge_get_reset_status(hdev
, queue_id
);
4647 if (reset_try_times
>= HCLGE_TQP_RESET_TRY_TIMES
) {
4648 dev_warn(&hdev
->pdev
->dev
, "Reset TQP fail\n");
4652 ret
= hclge_send_reset_tqp_cmd(hdev
, queue_id
, false);
4654 dev_warn(&hdev
->pdev
->dev
,
4655 "Deassert the soft reset fail, ret = %d\n", ret
);
4660 static u32
hclge_get_fw_version(struct hnae3_handle
*handle
)
4662 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4663 struct hclge_dev
*hdev
= vport
->back
;
4665 return hdev
->fw_version
;
4668 static void hclge_get_flowctrl_adv(struct hnae3_handle
*handle
,
4671 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4672 struct hclge_dev
*hdev
= vport
->back
;
4673 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4678 *flowctrl_adv
|= (phydev
->advertising
& ADVERTISED_Pause
) |
4679 (phydev
->advertising
& ADVERTISED_Asym_Pause
);
4682 static void hclge_set_flowctrl_adv(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
4684 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4689 phydev
->advertising
&= ~(ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
4692 phydev
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
4695 phydev
->advertising
^= ADVERTISED_Asym_Pause
;
4698 static int hclge_cfg_pauseparam(struct hclge_dev
*hdev
, u32 rx_en
, u32 tx_en
)
4700 enum hclge_fc_mode fc_mode
;
4704 fc_mode
= HCLGE_FC_FULL
;
4705 else if (rx_en
&& !tx_en
)
4706 fc_mode
= HCLGE_FC_RX_PAUSE
;
4707 else if (!rx_en
&& tx_en
)
4708 fc_mode
= HCLGE_FC_TX_PAUSE
;
4710 fc_mode
= HCLGE_FC_NONE
;
4712 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
4713 hdev
->fc_mode_last_time
= fc_mode
;
4717 ret
= hclge_mac_pause_en_cfg(hdev
, tx_en
, rx_en
);
4719 dev_err(&hdev
->pdev
->dev
, "configure pauseparam error, ret = %d.\n",
4724 hdev
->tm_info
.fc_mode
= fc_mode
;
4729 int hclge_cfg_flowctrl(struct hclge_dev
*hdev
)
4731 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4732 u16 remote_advertising
= 0;
4733 u16 local_advertising
= 0;
4734 u32 rx_pause
, tx_pause
;
4737 if (!phydev
->link
|| !phydev
->autoneg
)
4740 if (phydev
->advertising
& ADVERTISED_Pause
)
4741 local_advertising
= ADVERTISE_PAUSE_CAP
;
4743 if (phydev
->advertising
& ADVERTISED_Asym_Pause
)
4744 local_advertising
|= ADVERTISE_PAUSE_ASYM
;
4747 remote_advertising
= LPA_PAUSE_CAP
;
4749 if (phydev
->asym_pause
)
4750 remote_advertising
|= LPA_PAUSE_ASYM
;
4752 flowctl
= mii_resolve_flowctrl_fdx(local_advertising
,
4753 remote_advertising
);
4754 tx_pause
= flowctl
& FLOW_CTRL_TX
;
4755 rx_pause
= flowctl
& FLOW_CTRL_RX
;
4757 if (phydev
->duplex
== HCLGE_MAC_HALF
) {
4762 return hclge_cfg_pauseparam(hdev
, rx_pause
, tx_pause
);
4765 static void hclge_get_pauseparam(struct hnae3_handle
*handle
, u32
*auto_neg
,
4766 u32
*rx_en
, u32
*tx_en
)
4768 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4769 struct hclge_dev
*hdev
= vport
->back
;
4771 *auto_neg
= hclge_get_autoneg(handle
);
4773 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
4779 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_RX_PAUSE
) {
4782 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_TX_PAUSE
) {
4785 } else if (hdev
->tm_info
.fc_mode
== HCLGE_FC_FULL
) {
4794 static int hclge_set_pauseparam(struct hnae3_handle
*handle
, u32 auto_neg
,
4795 u32 rx_en
, u32 tx_en
)
4797 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4798 struct hclge_dev
*hdev
= vport
->back
;
4799 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4802 /* Only support flow control negotiation for netdev with
4803 * phy attached for now.
4808 fc_autoneg
= hclge_get_autoneg(handle
);
4809 if (auto_neg
!= fc_autoneg
) {
4810 dev_info(&hdev
->pdev
->dev
,
4811 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
4815 if (hdev
->tm_info
.fc_mode
== HCLGE_FC_PFC
) {
4816 dev_info(&hdev
->pdev
->dev
,
4817 "Priority flow control enabled. Cannot set link flow control.\n");
4821 hclge_set_flowctrl_adv(hdev
, rx_en
, tx_en
);
4824 return hclge_cfg_pauseparam(hdev
, rx_en
, tx_en
);
4826 return phy_start_aneg(phydev
);
4829 static void hclge_get_ksettings_an_result(struct hnae3_handle
*handle
,
4830 u8
*auto_neg
, u32
*speed
, u8
*duplex
)
4832 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4833 struct hclge_dev
*hdev
= vport
->back
;
4836 *speed
= hdev
->hw
.mac
.speed
;
4838 *duplex
= hdev
->hw
.mac
.duplex
;
4840 *auto_neg
= hdev
->hw
.mac
.autoneg
;
4843 static void hclge_get_media_type(struct hnae3_handle
*handle
, u8
*media_type
)
4845 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4846 struct hclge_dev
*hdev
= vport
->back
;
4849 *media_type
= hdev
->hw
.mac
.media_type
;
4852 static void hclge_get_mdix_mode(struct hnae3_handle
*handle
,
4853 u8
*tp_mdix_ctrl
, u8
*tp_mdix
)
4855 struct hclge_vport
*vport
= hclge_get_vport(handle
);
4856 struct hclge_dev
*hdev
= vport
->back
;
4857 struct phy_device
*phydev
= hdev
->hw
.mac
.phydev
;
4858 int mdix_ctrl
, mdix
, retval
, is_resolved
;
4861 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
4862 *tp_mdix
= ETH_TP_MDI_INVALID
;
4866 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_MDIX
);
4868 retval
= phy_read(phydev
, HCLGE_PHY_CSC_REG
);
4869 mdix_ctrl
= hnae_get_field(retval
, HCLGE_PHY_MDIX_CTRL_M
,
4870 HCLGE_PHY_MDIX_CTRL_S
);
4872 retval
= phy_read(phydev
, HCLGE_PHY_CSS_REG
);
4873 mdix
= hnae_get_bit(retval
, HCLGE_PHY_MDIX_STATUS_B
);
4874 is_resolved
= hnae_get_bit(retval
, HCLGE_PHY_SPEED_DUP_RESOLVE_B
);
4876 phy_write(phydev
, HCLGE_PHY_PAGE_REG
, HCLGE_PHY_PAGE_COPPER
);
4878 switch (mdix_ctrl
) {
4880 *tp_mdix_ctrl
= ETH_TP_MDI
;
4883 *tp_mdix_ctrl
= ETH_TP_MDI_X
;
4886 *tp_mdix_ctrl
= ETH_TP_MDI_AUTO
;
4889 *tp_mdix_ctrl
= ETH_TP_MDI_INVALID
;
4894 *tp_mdix
= ETH_TP_MDI_INVALID
;
4896 *tp_mdix
= ETH_TP_MDI_X
;
4898 *tp_mdix
= ETH_TP_MDI
;
4901 static int hclge_init_client_instance(struct hnae3_client
*client
,
4902 struct hnae3_ae_dev
*ae_dev
)
4904 struct hclge_dev
*hdev
= ae_dev
->priv
;
4905 struct hclge_vport
*vport
;
4908 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
4909 vport
= &hdev
->vport
[i
];
4911 switch (client
->type
) {
4912 case HNAE3_CLIENT_KNIC
:
4914 hdev
->nic_client
= client
;
4915 vport
->nic
.client
= client
;
4916 ret
= client
->ops
->init_instance(&vport
->nic
);
4920 if (hdev
->roce_client
&&
4921 hnae3_dev_roce_supported(hdev
)) {
4922 struct hnae3_client
*rc
= hdev
->roce_client
;
4924 ret
= hclge_init_roce_base_info(vport
);
4928 ret
= rc
->ops
->init_instance(&vport
->roce
);
4934 case HNAE3_CLIENT_UNIC
:
4935 hdev
->nic_client
= client
;
4936 vport
->nic
.client
= client
;
4938 ret
= client
->ops
->init_instance(&vport
->nic
);
4943 case HNAE3_CLIENT_ROCE
:
4944 if (hnae3_dev_roce_supported(hdev
)) {
4945 hdev
->roce_client
= client
;
4946 vport
->roce
.client
= client
;
4949 if (hdev
->roce_client
&& hdev
->nic_client
) {
4950 ret
= hclge_init_roce_base_info(vport
);
4954 ret
= client
->ops
->init_instance(&vport
->roce
);
4966 static void hclge_uninit_client_instance(struct hnae3_client
*client
,
4967 struct hnae3_ae_dev
*ae_dev
)
4969 struct hclge_dev
*hdev
= ae_dev
->priv
;
4970 struct hclge_vport
*vport
;
4973 for (i
= 0; i
< hdev
->num_vmdq_vport
+ 1; i
++) {
4974 vport
= &hdev
->vport
[i
];
4975 if (hdev
->roce_client
) {
4976 hdev
->roce_client
->ops
->uninit_instance(&vport
->roce
,
4978 hdev
->roce_client
= NULL
;
4979 vport
->roce
.client
= NULL
;
4981 if (client
->type
== HNAE3_CLIENT_ROCE
)
4983 if (client
->ops
->uninit_instance
) {
4984 client
->ops
->uninit_instance(&vport
->nic
, 0);
4985 hdev
->nic_client
= NULL
;
4986 vport
->nic
.client
= NULL
;
4991 static int hclge_pci_init(struct hclge_dev
*hdev
)
4993 struct pci_dev
*pdev
= hdev
->pdev
;
4994 struct hclge_hw
*hw
;
4997 ret
= pci_enable_device(pdev
);
4999 dev_err(&pdev
->dev
, "failed to enable PCI device\n");
5000 goto err_no_drvdata
;
5003 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64));
5005 ret
= dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32));
5008 "can't set consistent PCI DMA");
5009 goto err_disable_device
;
5011 dev_warn(&pdev
->dev
, "set DMA mask to 32 bits\n");
5014 ret
= pci_request_regions(pdev
, HCLGE_DRIVER_NAME
);
5016 dev_err(&pdev
->dev
, "PCI request regions failed %d\n", ret
);
5017 goto err_disable_device
;
5020 pci_set_master(pdev
);
5023 hw
->io_base
= pcim_iomap(pdev
, 2, 0);
5025 dev_err(&pdev
->dev
, "Can't map configuration register space\n");
5027 goto err_clr_master
;
5030 hdev
->num_req_vfs
= pci_sriov_get_totalvfs(pdev
);
5034 pci_clear_master(pdev
);
5035 pci_release_regions(pdev
);
5037 pci_disable_device(pdev
);
5039 pci_set_drvdata(pdev
, NULL
);
5044 static void hclge_pci_uninit(struct hclge_dev
*hdev
)
5046 struct pci_dev
*pdev
= hdev
->pdev
;
5048 pci_free_irq_vectors(pdev
);
5049 pci_clear_master(pdev
);
5050 pci_release_mem_regions(pdev
);
5051 pci_disable_device(pdev
);
5054 static int hclge_init_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5056 struct pci_dev
*pdev
= ae_dev
->pdev
;
5057 struct hclge_dev
*hdev
;
5060 hdev
= devm_kzalloc(&pdev
->dev
, sizeof(*hdev
), GFP_KERNEL
);
5067 hdev
->ae_dev
= ae_dev
;
5068 hdev
->reset_type
= HNAE3_NONE_RESET
;
5069 hdev
->reset_request
= 0;
5070 hdev
->reset_pending
= 0;
5071 ae_dev
->priv
= hdev
;
5073 ret
= hclge_pci_init(hdev
);
5075 dev_err(&pdev
->dev
, "PCI init failed\n");
5079 /* Firmware command queue initialize */
5080 ret
= hclge_cmd_queue_init(hdev
);
5082 dev_err(&pdev
->dev
, "Cmd queue init failed, ret = %d.\n", ret
);
5086 /* Firmware command initialize */
5087 ret
= hclge_cmd_init(hdev
);
5091 ret
= hclge_get_cap(hdev
);
5093 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5098 ret
= hclge_configure(hdev
);
5100 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5104 ret
= hclge_init_msi(hdev
);
5106 dev_err(&pdev
->dev
, "Init MSI/MSI-X error, ret = %d.\n", ret
);
5110 ret
= hclge_misc_irq_init(hdev
);
5113 "Misc IRQ(vector0) init error, ret = %d.\n",
5118 ret
= hclge_alloc_tqps(hdev
);
5120 dev_err(&pdev
->dev
, "Allocate TQPs error, ret = %d.\n", ret
);
5124 ret
= hclge_alloc_vport(hdev
);
5126 dev_err(&pdev
->dev
, "Allocate vport error, ret = %d.\n", ret
);
5130 ret
= hclge_map_tqp(hdev
);
5132 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5136 ret
= hclge_mac_mdio_config(hdev
);
5138 dev_warn(&hdev
->pdev
->dev
,
5139 "mdio config fail ret=%d\n", ret
);
5143 ret
= hclge_mac_init(hdev
);
5145 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5148 ret
= hclge_buffer_alloc(hdev
);
5150 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
5154 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5156 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5160 ret
= hclge_init_vlan_config(hdev
);
5162 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5166 ret
= hclge_tm_schd_init(hdev
);
5168 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5172 ret
= hclge_rss_init_hw(hdev
);
5174 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5178 hclge_dcb_ops_set(hdev
);
5180 timer_setup(&hdev
->service_timer
, hclge_service_timer
, 0);
5181 INIT_WORK(&hdev
->service_task
, hclge_service_task
);
5182 INIT_WORK(&hdev
->rst_service_task
, hclge_reset_service_task
);
5183 INIT_WORK(&hdev
->mbx_service_task
, hclge_mailbox_service_task
);
5185 /* Enable MISC vector(vector0) */
5186 hclge_enable_vector(&hdev
->misc_vector
, true);
5188 set_bit(HCLGE_STATE_SERVICE_INITED
, &hdev
->state
);
5189 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5190 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED
, &hdev
->state
);
5191 clear_bit(HCLGE_STATE_RST_HANDLING
, &hdev
->state
);
5192 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED
, &hdev
->state
);
5193 clear_bit(HCLGE_STATE_MBX_HANDLING
, &hdev
->state
);
5195 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME
);
5199 pci_release_regions(pdev
);
5201 pci_set_drvdata(pdev
, NULL
);
5206 static void hclge_stats_clear(struct hclge_dev
*hdev
)
5208 memset(&hdev
->hw_stats
, 0, sizeof(hdev
->hw_stats
));
5211 static int hclge_reset_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5213 struct hclge_dev
*hdev
= ae_dev
->priv
;
5214 struct pci_dev
*pdev
= ae_dev
->pdev
;
5217 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5219 hclge_stats_clear(hdev
);
5221 ret
= hclge_cmd_init(hdev
);
5223 dev_err(&pdev
->dev
, "Cmd queue init failed\n");
5227 ret
= hclge_get_cap(hdev
);
5229 dev_err(&pdev
->dev
, "get hw capability error, ret = %d.\n",
5234 ret
= hclge_configure(hdev
);
5236 dev_err(&pdev
->dev
, "Configure dev error, ret = %d.\n", ret
);
5240 ret
= hclge_map_tqp(hdev
);
5242 dev_err(&pdev
->dev
, "Map tqp error, ret = %d.\n", ret
);
5246 ret
= hclge_mac_init(hdev
);
5248 dev_err(&pdev
->dev
, "Mac init error, ret = %d\n", ret
);
5252 ret
= hclge_buffer_alloc(hdev
);
5254 dev_err(&pdev
->dev
, "Buffer allocate fail, ret =%d\n", ret
);
5258 ret
= hclge_config_tso(hdev
, HCLGE_TSO_MSS_MIN
, HCLGE_TSO_MSS_MAX
);
5260 dev_err(&pdev
->dev
, "Enable tso fail, ret =%d\n", ret
);
5264 ret
= hclge_init_vlan_config(hdev
);
5266 dev_err(&pdev
->dev
, "VLAN init fail, ret =%d\n", ret
);
5270 ret
= hclge_tm_schd_init(hdev
);
5272 dev_err(&pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5276 ret
= hclge_rss_init_hw(hdev
);
5278 dev_err(&pdev
->dev
, "Rss init fail, ret =%d\n", ret
);
5282 /* Enable MISC vector(vector0) */
5283 hclge_enable_vector(&hdev
->misc_vector
, true);
5285 dev_info(&pdev
->dev
, "Reset done, %s driver initialization finished.\n",
5291 static void hclge_uninit_ae_dev(struct hnae3_ae_dev
*ae_dev
)
5293 struct hclge_dev
*hdev
= ae_dev
->priv
;
5294 struct hclge_mac
*mac
= &hdev
->hw
.mac
;
5296 set_bit(HCLGE_STATE_DOWN
, &hdev
->state
);
5298 if (IS_ENABLED(CONFIG_PCI_IOV
))
5299 hclge_disable_sriov(hdev
);
5301 if (hdev
->service_timer
.function
)
5302 del_timer_sync(&hdev
->service_timer
);
5303 if (hdev
->service_task
.func
)
5304 cancel_work_sync(&hdev
->service_task
);
5305 if (hdev
->rst_service_task
.func
)
5306 cancel_work_sync(&hdev
->rst_service_task
);
5307 if (hdev
->mbx_service_task
.func
)
5308 cancel_work_sync(&hdev
->mbx_service_task
);
5311 mdiobus_unregister(mac
->mdio_bus
);
5313 /* Disable MISC vector(vector0) */
5314 hclge_enable_vector(&hdev
->misc_vector
, false);
5315 hclge_destroy_cmd_queue(&hdev
->hw
);
5316 hclge_misc_irq_uninit(hdev
);
5317 hclge_pci_uninit(hdev
);
5318 ae_dev
->priv
= NULL
;
5321 static u32
hclge_get_max_channels(struct hnae3_handle
*handle
)
5323 struct hnae3_knic_private_info
*kinfo
= &handle
->kinfo
;
5324 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5325 struct hclge_dev
*hdev
= vport
->back
;
5327 return min_t(u32
, hdev
->rss_size_max
* kinfo
->num_tc
, hdev
->num_tqps
);
5330 static void hclge_get_channels(struct hnae3_handle
*handle
,
5331 struct ethtool_channels
*ch
)
5333 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5335 ch
->max_combined
= hclge_get_max_channels(handle
);
5336 ch
->other_count
= 1;
5338 ch
->combined_count
= vport
->alloc_tqps
;
5341 static void hclge_get_tqps_and_rss_info(struct hnae3_handle
*handle
,
5342 u16
*free_tqps
, u16
*max_rss_size
)
5344 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5345 struct hclge_dev
*hdev
= vport
->back
;
5349 for (i
= 0; i
< hdev
->num_tqps
; i
++) {
5350 if (!hdev
->htqp
[i
].alloced
)
5353 *free_tqps
= temp_tqps
;
5354 *max_rss_size
= hdev
->rss_size_max
;
5357 static void hclge_release_tqp(struct hclge_vport
*vport
)
5359 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5360 struct hclge_dev
*hdev
= vport
->back
;
5363 for (i
= 0; i
< kinfo
->num_tqps
; i
++) {
5364 struct hclge_tqp
*tqp
=
5365 container_of(kinfo
->tqp
[i
], struct hclge_tqp
, q
);
5367 tqp
->q
.handle
= NULL
;
5368 tqp
->q
.tqp_index
= 0;
5369 tqp
->alloced
= false;
5372 devm_kfree(&hdev
->pdev
->dev
, kinfo
->tqp
);
5376 static int hclge_set_channels(struct hnae3_handle
*handle
, u32 new_tqps_num
)
5378 struct hclge_vport
*vport
= hclge_get_vport(handle
);
5379 struct hnae3_knic_private_info
*kinfo
= &vport
->nic
.kinfo
;
5380 struct hclge_dev
*hdev
= vport
->back
;
5381 int cur_rss_size
= kinfo
->rss_size
;
5382 int cur_tqps
= kinfo
->num_tqps
;
5383 u16 tc_offset
[HCLGE_MAX_TC_NUM
];
5384 u16 tc_valid
[HCLGE_MAX_TC_NUM
];
5385 u16 tc_size
[HCLGE_MAX_TC_NUM
];
5390 hclge_release_tqp(vport
);
5392 ret
= hclge_knic_setup(vport
, new_tqps_num
);
5394 dev_err(&hdev
->pdev
->dev
, "setup nic fail, ret =%d\n", ret
);
5398 ret
= hclge_map_tqp_to_vport(hdev
, vport
);
5400 dev_err(&hdev
->pdev
->dev
, "map vport tqp fail, ret =%d\n", ret
);
5404 ret
= hclge_tm_schd_init(hdev
);
5406 dev_err(&hdev
->pdev
->dev
, "tm schd init fail, ret =%d\n", ret
);
5410 roundup_size
= roundup_pow_of_two(kinfo
->rss_size
);
5411 roundup_size
= ilog2(roundup_size
);
5412 /* Set the RSS TC mode according to the new RSS size */
5413 for (i
= 0; i
< HCLGE_MAX_TC_NUM
; i
++) {
5416 if (!(hdev
->hw_tc_map
& BIT(i
)))
5420 tc_size
[i
] = roundup_size
;
5421 tc_offset
[i
] = kinfo
->rss_size
* i
;
5423 ret
= hclge_set_rss_tc_mode(hdev
, tc_valid
, tc_size
, tc_offset
);
5427 /* Reinitializes the rss indirect table according to the new RSS size */
5428 rss_indir
= kcalloc(HCLGE_RSS_IND_TBL_SIZE
, sizeof(u32
), GFP_KERNEL
);
5432 for (i
= 0; i
< HCLGE_RSS_IND_TBL_SIZE
; i
++)
5433 rss_indir
[i
] = i
% kinfo
->rss_size
;
5435 ret
= hclge_set_rss(handle
, rss_indir
, NULL
, 0);
5437 dev_err(&hdev
->pdev
->dev
, "set rss indir table fail, ret=%d\n",
5443 dev_info(&hdev
->pdev
->dev
,
5444 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5445 cur_rss_size
, kinfo
->rss_size
,
5446 cur_tqps
, kinfo
->rss_size
* kinfo
->num_tc
);
5451 static const struct hnae3_ae_ops hclge_ops
= {
5452 .init_ae_dev
= hclge_init_ae_dev
,
5453 .uninit_ae_dev
= hclge_uninit_ae_dev
,
5454 .init_client_instance
= hclge_init_client_instance
,
5455 .uninit_client_instance
= hclge_uninit_client_instance
,
5456 .map_ring_to_vector
= hclge_map_ring_to_vector
,
5457 .unmap_ring_from_vector
= hclge_unmap_ring_frm_vector
,
5458 .get_vector
= hclge_get_vector
,
5459 .set_promisc_mode
= hclge_set_promisc_mode
,
5460 .set_loopback
= hclge_set_loopback
,
5461 .start
= hclge_ae_start
,
5462 .stop
= hclge_ae_stop
,
5463 .get_status
= hclge_get_status
,
5464 .get_ksettings_an_result
= hclge_get_ksettings_an_result
,
5465 .update_speed_duplex_h
= hclge_update_speed_duplex_h
,
5466 .cfg_mac_speed_dup_h
= hclge_cfg_mac_speed_dup_h
,
5467 .get_media_type
= hclge_get_media_type
,
5468 .get_rss_key_size
= hclge_get_rss_key_size
,
5469 .get_rss_indir_size
= hclge_get_rss_indir_size
,
5470 .get_rss
= hclge_get_rss
,
5471 .set_rss
= hclge_set_rss
,
5472 .set_rss_tuple
= hclge_set_rss_tuple
,
5473 .get_rss_tuple
= hclge_get_rss_tuple
,
5474 .get_tc_size
= hclge_get_tc_size
,
5475 .get_mac_addr
= hclge_get_mac_addr
,
5476 .set_mac_addr
= hclge_set_mac_addr
,
5477 .add_uc_addr
= hclge_add_uc_addr
,
5478 .rm_uc_addr
= hclge_rm_uc_addr
,
5479 .add_mc_addr
= hclge_add_mc_addr
,
5480 .rm_mc_addr
= hclge_rm_mc_addr
,
5481 .set_autoneg
= hclge_set_autoneg
,
5482 .get_autoneg
= hclge_get_autoneg
,
5483 .get_pauseparam
= hclge_get_pauseparam
,
5484 .set_pauseparam
= hclge_set_pauseparam
,
5485 .set_mtu
= hclge_set_mtu
,
5486 .reset_queue
= hclge_reset_tqp
,
5487 .get_stats
= hclge_get_stats
,
5488 .update_stats
= hclge_update_stats
,
5489 .get_strings
= hclge_get_strings
,
5490 .get_sset_count
= hclge_get_sset_count
,
5491 .get_fw_version
= hclge_get_fw_version
,
5492 .get_mdix_mode
= hclge_get_mdix_mode
,
5493 .enable_vlan_filter
= hclge_enable_vlan_filter
,
5494 .set_vlan_filter
= hclge_set_port_vlan_filter
,
5495 .set_vf_vlan_filter
= hclge_set_vf_vlan_filter
,
5496 .enable_hw_strip_rxvtag
= hclge_en_hw_strip_rxvtag
,
5497 .reset_event
= hclge_reset_event
,
5498 .get_tqps_and_rss_info
= hclge_get_tqps_and_rss_info
,
5499 .set_channels
= hclge_set_channels
,
5500 .get_channels
= hclge_get_channels
,
5501 .get_flowctrl_adv
= hclge_get_flowctrl_adv
,
5504 static struct hnae3_ae_algo ae_algo
= {
5507 .pdev_id_table
= ae_algo_pci_tbl
,
5510 static int hclge_init(void)
5512 pr_info("%s is initializing\n", HCLGE_NAME
);
5514 return hnae3_register_ae_algo(&ae_algo
);
5517 static void hclge_exit(void)
5519 hnae3_unregister_ae_algo(&ae_algo
);
5521 module_init(hclge_init
);
5522 module_exit(hclge_exit
);
5524 MODULE_LICENSE("GPL");
5525 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5526 MODULE_DESCRIPTION("HCLGE Driver");
5527 MODULE_VERSION(HCLGE_MOD_VERSION
);
projects / mirror_ubuntu-bionic-kernel.git / blob