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net/mlx5e: Handle RQ flush in error cases
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1 /*
2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32 #ifndef __MLX5_EN_H__
33 #define __MLX5_EN_H__
34
35 #include <linux/if_vlan.h>
36 #include <linux/etherdevice.h>
37 #include <linux/timecounter.h>
38 #include <linux/net_tstamp.h>
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/qp.h>
42 #include <linux/mlx5/cq.h>
43 #include <linux/mlx5/port.h>
44 #include <linux/mlx5/vport.h>
45 #include <linux/mlx5/transobj.h>
46 #include <linux/rhashtable.h>
47 #include "wq.h"
48 #include "mlx5_core.h"
49 #include "en_stats.h"
50
51 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
52
53 #define MLX5E_MAX_NUM_TC 8
54
55 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x6
56 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
57 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
58
59 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x1
60 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
61 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
62
63 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW 0x1
64 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW 0x4
65 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW 0x6
66
67 #define MLX5_MPWRQ_LOG_STRIDE_SIZE 6 /* >= 6, HW restriction */
68 #define MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS 8 /* >= 6, HW restriction */
69 #define MLX5_MPWRQ_LOG_WQE_SZ 17
70 #define MLX5_MPWRQ_WQE_PAGE_ORDER (MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT > 0 ? \
71 MLX5_MPWRQ_LOG_WQE_SZ - PAGE_SHIFT : 0)
72 #define MLX5_MPWRQ_PAGES_PER_WQE BIT(MLX5_MPWRQ_WQE_PAGE_ORDER)
73 #define MLX5_MPWRQ_STRIDES_PER_PAGE (MLX5_MPWRQ_NUM_STRIDES >> \
74 MLX5_MPWRQ_WQE_PAGE_ORDER)
75 #define MLX5_CHANNEL_MAX_NUM_MTTS (ALIGN(MLX5_MPWRQ_PAGES_PER_WQE, 8) * \
76 BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW))
77 #define MLX5_UMR_ALIGN (2048)
78 #define MLX5_MPWRQ_SMALL_PACKET_THRESHOLD (128)
79
80 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ (64 * 1024)
81 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
83 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
84 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
85 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
86 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW 0x2
87
88 #define MLX5E_LOG_INDIR_RQT_SIZE 0x7
89 #define MLX5E_INDIR_RQT_SIZE BIT(MLX5E_LOG_INDIR_RQT_SIZE)
90 #define MLX5E_MAX_NUM_CHANNELS (MLX5E_INDIR_RQT_SIZE >> 1)
91 #define MLX5E_TX_CQ_POLL_BUDGET 128
92 #define MLX5E_UPDATE_STATS_INTERVAL 200 /* msecs */
93 #define MLX5E_SQ_BF_BUDGET 16
94
95 #define MLX5E_NUM_MAIN_GROUPS 9
96
97 static inline u16 mlx5_min_rx_wqes(int wq_type, u32 wq_size)
98 {
99 switch (wq_type) {
100 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
101 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES_MPW,
102 wq_size / 2);
103 default:
104 return min_t(u16, MLX5E_PARAMS_DEFAULT_MIN_RX_WQES,
105 wq_size / 2);
106 }
107 }
108
109 static inline int mlx5_min_log_rq_size(int wq_type)
110 {
111 switch (wq_type) {
112 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
113 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
114 default:
115 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
116 }
117 }
118
119 static inline int mlx5_max_log_rq_size(int wq_type)
120 {
121 switch (wq_type) {
122 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
123 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW;
124 default:
125 return MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
126 }
127 }
128
129 struct mlx5e_tx_wqe {
130 struct mlx5_wqe_ctrl_seg ctrl;
131 struct mlx5_wqe_eth_seg eth;
132 };
133
134 struct mlx5e_rx_wqe {
135 struct mlx5_wqe_srq_next_seg next;
136 struct mlx5_wqe_data_seg data;
137 };
138
139 struct mlx5e_umr_wqe {
140 struct mlx5_wqe_ctrl_seg ctrl;
141 struct mlx5_wqe_umr_ctrl_seg uctrl;
142 struct mlx5_mkey_seg mkc;
143 struct mlx5_wqe_data_seg data;
144 };
145
146 #ifdef CONFIG_MLX5_CORE_EN_DCB
147 #define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */
148 #define MLX5E_MIN_BW_ALLOC 1 /* Min percentage of BW allocation */
149 #endif
150
151 struct mlx5e_params {
152 u8 log_sq_size;
153 u8 rq_wq_type;
154 u8 mpwqe_log_stride_sz;
155 u8 mpwqe_log_num_strides;
156 u8 log_rq_size;
157 u16 num_channels;
158 u8 num_tc;
159 bool rx_cqe_compress_admin;
160 bool rx_cqe_compress;
161 u16 rx_cq_moderation_usec;
162 u16 rx_cq_moderation_pkts;
163 u16 tx_cq_moderation_usec;
164 u16 tx_cq_moderation_pkts;
165 u16 min_rx_wqes;
166 bool lro_en;
167 u32 lro_wqe_sz;
168 u16 tx_max_inline;
169 u8 rss_hfunc;
170 u8 toeplitz_hash_key[40];
171 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE];
172 bool vlan_strip_disable;
173 #ifdef CONFIG_MLX5_CORE_EN_DCB
174 struct ieee_ets ets;
175 #endif
176 };
177
178 struct mlx5e_tstamp {
179 rwlock_t lock;
180 struct cyclecounter cycles;
181 struct timecounter clock;
182 struct hwtstamp_config hwtstamp_config;
183 u32 nominal_c_mult;
184 unsigned long overflow_period;
185 struct delayed_work overflow_work;
186 struct mlx5_core_dev *mdev;
187 struct ptp_clock *ptp;
188 struct ptp_clock_info ptp_info;
189 };
190
191 enum {
192 MLX5E_RQ_STATE_POST_WQES_ENABLE,
193 MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,
194 MLX5E_RQ_STATE_FLUSH_TIMEOUT,
195 };
196
197 struct mlx5e_cq {
198 /* data path - accessed per cqe */
199 struct mlx5_cqwq wq;
200
201 /* data path - accessed per napi poll */
202 struct napi_struct *napi;
203 struct mlx5_core_cq mcq;
204 struct mlx5e_channel *channel;
205 struct mlx5e_priv *priv;
206
207 /* cqe decompression */
208 struct mlx5_cqe64 title;
209 struct mlx5_mini_cqe8 mini_arr[MLX5_MINI_CQE_ARRAY_SIZE];
210 u8 mini_arr_idx;
211 u16 decmprs_left;
212 u16 decmprs_wqe_counter;
213
214 /* control */
215 struct mlx5_wq_ctrl wq_ctrl;
216 } ____cacheline_aligned_in_smp;
217
218 struct mlx5e_rq;
219 typedef void (*mlx5e_fp_handle_rx_cqe)(struct mlx5e_rq *rq,
220 struct mlx5_cqe64 *cqe);
221 typedef int (*mlx5e_fp_alloc_wqe)(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe,
222 u16 ix);
223
224 typedef void (*mlx5e_fp_dealloc_wqe)(struct mlx5e_rq *rq, u16 ix);
225
226 struct mlx5e_dma_info {
227 struct page *page;
228 dma_addr_t addr;
229 };
230
231 struct mlx5e_rq {
232 /* data path */
233 struct mlx5_wq_ll wq;
234 u32 wqe_sz;
235 struct sk_buff **skb;
236 struct mlx5e_mpw_info *wqe_info;
237 __be32 mkey_be;
238 __be32 umr_mkey_be;
239
240 struct device *pdev;
241 struct net_device *netdev;
242 struct mlx5e_tstamp *tstamp;
243 struct mlx5e_rq_stats stats;
244 struct mlx5e_cq cq;
245 mlx5e_fp_handle_rx_cqe handle_rx_cqe;
246 mlx5e_fp_alloc_wqe alloc_wqe;
247 mlx5e_fp_dealloc_wqe dealloc_wqe;
248
249 unsigned long state;
250 int ix;
251
252 /* control */
253 struct mlx5_wq_ctrl wq_ctrl;
254 u8 wq_type;
255 u32 mpwqe_stride_sz;
256 u32 mpwqe_num_strides;
257 u32 rqn;
258 struct mlx5e_channel *channel;
259 struct mlx5e_priv *priv;
260 } ____cacheline_aligned_in_smp;
261
262 struct mlx5e_umr_dma_info {
263 __be64 *mtt;
264 __be64 *mtt_no_align;
265 dma_addr_t mtt_addr;
266 struct mlx5e_dma_info *dma_info;
267 };
268
269 struct mlx5e_mpw_info {
270 union {
271 struct mlx5e_dma_info dma_info;
272 struct mlx5e_umr_dma_info umr;
273 };
274 u16 consumed_strides;
275 u16 skbs_frags[MLX5_MPWRQ_PAGES_PER_WQE];
276
277 void (*dma_pre_sync)(struct device *pdev,
278 struct mlx5e_mpw_info *wi,
279 u32 wqe_offset, u32 len);
280 void (*add_skb_frag)(struct mlx5e_rq *rq,
281 struct sk_buff *skb,
282 struct mlx5e_mpw_info *wi,
283 u32 page_idx, u32 frag_offset, u32 len);
284 void (*copy_skb_header)(struct device *pdev,
285 struct sk_buff *skb,
286 struct mlx5e_mpw_info *wi,
287 u32 page_idx, u32 offset,
288 u32 headlen);
289 void (*free_wqe)(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi);
290 };
291
292 struct mlx5e_tx_wqe_info {
293 u32 num_bytes;
294 u8 num_wqebbs;
295 u8 num_dma;
296 };
297
298 enum mlx5e_dma_map_type {
299 MLX5E_DMA_MAP_SINGLE,
300 MLX5E_DMA_MAP_PAGE
301 };
302
303 struct mlx5e_sq_dma {
304 dma_addr_t addr;
305 u32 size;
306 enum mlx5e_dma_map_type type;
307 };
308
309 enum {
310 MLX5E_SQ_STATE_WAKE_TXQ_ENABLE,
311 MLX5E_SQ_STATE_BF_ENABLE,
312 MLX5E_SQ_STATE_TX_TIMEOUT,
313 };
314
315 struct mlx5e_ico_wqe_info {
316 u8 opcode;
317 u8 num_wqebbs;
318 };
319
320 struct mlx5e_sq {
321 /* data path */
322
323 /* dirtied @completion */
324 u16 cc;
325 u32 dma_fifo_cc;
326
327 /* dirtied @xmit */
328 u16 pc ____cacheline_aligned_in_smp;
329 u32 dma_fifo_pc;
330 u16 bf_offset;
331 u16 prev_cc;
332 u8 bf_budget;
333 struct mlx5e_sq_stats stats;
334
335 struct mlx5e_cq cq;
336
337 /* pointers to per packet info: write@xmit, read@completion */
338 struct sk_buff **skb;
339 struct mlx5e_sq_dma *dma_fifo;
340 struct mlx5e_tx_wqe_info *wqe_info;
341
342 /* read only */
343 struct mlx5_wq_cyc wq;
344 u32 dma_fifo_mask;
345 void __iomem *uar_map;
346 struct netdev_queue *txq;
347 u32 sqn;
348 u16 bf_buf_size;
349 u16 max_inline;
350 u16 edge;
351 struct device *pdev;
352 struct mlx5e_tstamp *tstamp;
353 __be32 mkey_be;
354 unsigned long state;
355
356 /* control path */
357 struct mlx5_wq_ctrl wq_ctrl;
358 struct mlx5_uar uar;
359 struct mlx5e_channel *channel;
360 int tc;
361 struct mlx5e_ico_wqe_info *ico_wqe_info;
362 } ____cacheline_aligned_in_smp;
363
364 static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
365 {
366 return (((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n) ||
367 (sq->cc == sq->pc));
368 }
369
370 enum channel_flags {
371 MLX5E_CHANNEL_NAPI_SCHED = 1,
372 };
373
374 struct mlx5e_channel {
375 /* data path */
376 struct mlx5e_rq rq;
377 struct mlx5e_sq sq[MLX5E_MAX_NUM_TC];
378 struct mlx5e_sq icosq; /* internal control operations */
379 struct napi_struct napi;
380 struct device *pdev;
381 struct net_device *netdev;
382 __be32 mkey_be;
383 u8 num_tc;
384 unsigned long flags;
385
386 /* control */
387 struct mlx5e_priv *priv;
388 int ix;
389 int cpu;
390 };
391
392 enum mlx5e_traffic_types {
393 MLX5E_TT_IPV4_TCP,
394 MLX5E_TT_IPV6_TCP,
395 MLX5E_TT_IPV4_UDP,
396 MLX5E_TT_IPV6_UDP,
397 MLX5E_TT_IPV4_IPSEC_AH,
398 MLX5E_TT_IPV6_IPSEC_AH,
399 MLX5E_TT_IPV4_IPSEC_ESP,
400 MLX5E_TT_IPV6_IPSEC_ESP,
401 MLX5E_TT_IPV4,
402 MLX5E_TT_IPV6,
403 MLX5E_TT_ANY,
404 MLX5E_NUM_TT,
405 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY,
406 };
407
408 enum {
409 MLX5E_STATE_ASYNC_EVENTS_ENABLED,
410 MLX5E_STATE_OPENED,
411 MLX5E_STATE_DESTROYING,
412 };
413
414 struct mlx5e_vxlan_db {
415 spinlock_t lock; /* protect vxlan table */
416 struct radix_tree_root tree;
417 };
418
419 struct mlx5e_l2_rule {
420 u8 addr[ETH_ALEN + 2];
421 struct mlx5_flow_rule *rule;
422 };
423
424 struct mlx5e_flow_table {
425 int num_groups;
426 struct mlx5_flow_table *t;
427 struct mlx5_flow_group **g;
428 };
429
430 #define MLX5E_L2_ADDR_HASH_SIZE BIT(BITS_PER_BYTE)
431
432 struct mlx5e_tc_table {
433 struct mlx5_flow_table *t;
434
435 struct rhashtable_params ht_params;
436 struct rhashtable ht;
437 };
438
439 struct mlx5e_vlan_table {
440 struct mlx5e_flow_table ft;
441 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
442 struct mlx5_flow_rule *active_vlans_rule[VLAN_N_VID];
443 struct mlx5_flow_rule *untagged_rule;
444 struct mlx5_flow_rule *any_vlan_rule;
445 bool filter_disabled;
446 };
447
448 struct mlx5e_l2_table {
449 struct mlx5e_flow_table ft;
450 struct hlist_head netdev_uc[MLX5E_L2_ADDR_HASH_SIZE];
451 struct hlist_head netdev_mc[MLX5E_L2_ADDR_HASH_SIZE];
452 struct mlx5e_l2_rule broadcast;
453 struct mlx5e_l2_rule allmulti;
454 struct mlx5e_l2_rule promisc;
455 bool broadcast_enabled;
456 bool allmulti_enabled;
457 bool promisc_enabled;
458 };
459
460 /* L3/L4 traffic type classifier */
461 struct mlx5e_ttc_table {
462 struct mlx5e_flow_table ft;
463 struct mlx5_flow_rule *rules[MLX5E_NUM_TT];
464 };
465
466 #define ARFS_HASH_SHIFT BITS_PER_BYTE
467 #define ARFS_HASH_SIZE BIT(BITS_PER_BYTE)
468 struct arfs_table {
469 struct mlx5e_flow_table ft;
470 struct mlx5_flow_rule *default_rule;
471 struct hlist_head rules_hash[ARFS_HASH_SIZE];
472 };
473
474 enum arfs_type {
475 ARFS_IPV4_TCP,
476 ARFS_IPV6_TCP,
477 ARFS_IPV4_UDP,
478 ARFS_IPV6_UDP,
479 ARFS_NUM_TYPES,
480 };
481
482 struct mlx5e_arfs_tables {
483 struct arfs_table arfs_tables[ARFS_NUM_TYPES];
484 /* Protect aRFS rules list */
485 spinlock_t arfs_lock;
486 struct list_head rules;
487 int last_filter_id;
488 struct workqueue_struct *wq;
489 };
490
491 /* NIC prio FTS */
492 enum {
493 MLX5E_VLAN_FT_LEVEL = 0,
494 MLX5E_L2_FT_LEVEL,
495 MLX5E_TTC_FT_LEVEL,
496 MLX5E_ARFS_FT_LEVEL
497 };
498
499 struct mlx5e_flow_steering {
500 struct mlx5_flow_namespace *ns;
501 struct mlx5e_tc_table tc;
502 struct mlx5e_vlan_table vlan;
503 struct mlx5e_l2_table l2;
504 struct mlx5e_ttc_table ttc;
505 struct mlx5e_arfs_tables arfs;
506 };
507
508 struct mlx5e_direct_tir {
509 u32 tirn;
510 u32 rqtn;
511 };
512
513 enum {
514 MLX5E_TC_PRIO = 0,
515 MLX5E_NIC_PRIO
516 };
517
518 struct mlx5e_priv {
519 /* priv data path fields - start */
520 struct mlx5e_sq **txq_to_sq_map;
521 int channeltc_to_txq_map[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
522 /* priv data path fields - end */
523
524 unsigned long state;
525 struct mutex state_lock; /* Protects Interface state */
526 struct mlx5_uar cq_uar;
527 u32 pdn;
528 u32 tdn;
529 struct mlx5_core_mkey mkey;
530 struct mlx5_core_mkey umr_mkey;
531 struct mlx5e_rq drop_rq;
532
533 struct mlx5e_channel **channel;
534 u32 tisn[MLX5E_MAX_NUM_TC];
535 u32 indir_rqtn;
536 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
537 struct mlx5e_direct_tir direct_tir[MLX5E_MAX_NUM_CHANNELS];
538
539 struct mlx5e_flow_steering fs;
540 struct mlx5e_vxlan_db vxlan;
541
542 struct mlx5e_params params;
543 struct workqueue_struct *wq;
544 struct work_struct update_carrier_work;
545 struct work_struct set_rx_mode_work;
546 struct work_struct tx_timeout_work;
547 struct delayed_work update_stats_work;
548
549 struct mlx5_core_dev *mdev;
550 struct net_device *netdev;
551 struct mlx5e_stats stats;
552 struct mlx5e_tstamp tstamp;
553 u16 q_counter;
554 };
555
556 enum mlx5e_link_mode {
557 MLX5E_1000BASE_CX_SGMII = 0,
558 MLX5E_1000BASE_KX = 1,
559 MLX5E_10GBASE_CX4 = 2,
560 MLX5E_10GBASE_KX4 = 3,
561 MLX5E_10GBASE_KR = 4,
562 MLX5E_20GBASE_KR2 = 5,
563 MLX5E_40GBASE_CR4 = 6,
564 MLX5E_40GBASE_KR4 = 7,
565 MLX5E_56GBASE_R4 = 8,
566 MLX5E_10GBASE_CR = 12,
567 MLX5E_10GBASE_SR = 13,
568 MLX5E_10GBASE_ER = 14,
569 MLX5E_40GBASE_SR4 = 15,
570 MLX5E_40GBASE_LR4 = 16,
571 MLX5E_100GBASE_CR4 = 20,
572 MLX5E_100GBASE_SR4 = 21,
573 MLX5E_100GBASE_KR4 = 22,
574 MLX5E_100GBASE_LR4 = 23,
575 MLX5E_100BASE_TX = 24,
576 MLX5E_1000BASE_T = 25,
577 MLX5E_10GBASE_T = 26,
578 MLX5E_25GBASE_CR = 27,
579 MLX5E_25GBASE_KR = 28,
580 MLX5E_25GBASE_SR = 29,
581 MLX5E_50GBASE_CR2 = 30,
582 MLX5E_50GBASE_KR2 = 31,
583 MLX5E_LINK_MODES_NUMBER,
584 };
585
586 #define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
587
588 void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);
589 u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,
590 void *accel_priv, select_queue_fallback_t fallback);
591 netdev_tx_t mlx5e_xmit(struct sk_buff *skb, struct net_device *dev);
592
593 void mlx5e_completion_event(struct mlx5_core_cq *mcq);
594 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, enum mlx5_event event);
595 int mlx5e_napi_poll(struct napi_struct *napi, int budget);
596 bool mlx5e_poll_tx_cq(struct mlx5e_cq *cq, int napi_budget);
597 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget);
598 void mlx5e_free_tx_descs(struct mlx5e_sq *sq);
599 void mlx5e_free_rx_descs(struct mlx5e_rq *rq);
600
601 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
602 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe);
603 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq);
604 int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
605 int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe *wqe, u16 ix);
606 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix);
607 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
608 void mlx5e_post_rx_fragmented_mpwqe(struct mlx5e_rq *rq);
609 void mlx5e_complete_rx_linear_mpwqe(struct mlx5e_rq *rq,
610 struct mlx5_cqe64 *cqe,
611 u16 byte_cnt,
612 struct mlx5e_mpw_info *wi,
613 struct sk_buff *skb);
614 void mlx5e_complete_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
615 struct mlx5_cqe64 *cqe,
616 u16 byte_cnt,
617 struct mlx5e_mpw_info *wi,
618 struct sk_buff *skb);
619 void mlx5e_free_rx_linear_mpwqe(struct mlx5e_rq *rq,
620 struct mlx5e_mpw_info *wi);
621 void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq,
622 struct mlx5e_mpw_info *wi);
623 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
624
625 void mlx5e_update_stats(struct mlx5e_priv *priv);
626
627 int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
628 void mlx5e_destroy_flow_steering(struct mlx5e_priv *priv);
629 void mlx5e_init_l2_addr(struct mlx5e_priv *priv);
630 void mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft);
631 void mlx5e_set_rx_mode_work(struct work_struct *work);
632
633 void mlx5e_fill_hwstamp(struct mlx5e_tstamp *clock, u64 timestamp,
634 struct skb_shared_hwtstamps *hwts);
635 void mlx5e_timestamp_init(struct mlx5e_priv *priv);
636 void mlx5e_timestamp_cleanup(struct mlx5e_priv *priv);
637 int mlx5e_hwstamp_set(struct net_device *dev, struct ifreq *ifr);
638 int mlx5e_hwstamp_get(struct net_device *dev, struct ifreq *ifr);
639 void mlx5e_modify_rx_cqe_compression(struct mlx5e_priv *priv, bool val);
640
641 int mlx5e_vlan_rx_add_vid(struct net_device *dev, __always_unused __be16 proto,
642 u16 vid);
643 int mlx5e_vlan_rx_kill_vid(struct net_device *dev, __always_unused __be16 proto,
644 u16 vid);
645 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
646 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
647
648 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd);
649
650 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix);
651 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv);
652
653 int mlx5e_open_locked(struct net_device *netdev);
654 int mlx5e_close_locked(struct net_device *netdev);
655 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
656 u32 *indirection_rqt, int len,
657 int num_channels);
658 int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);
659
660 static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,
661 struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)
662 {
663 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
664
665 /* ensure wqe is visible to device before updating doorbell record */
666 dma_wmb();
667
668 *sq->wq.db = cpu_to_be32(sq->pc);
669
670 /* ensure doorbell record is visible to device before ringing the
671 * doorbell
672 */
673 wmb();
674 if (bf_sz)
675 __iowrite64_copy(sq->uar_map + ofst, ctrl, bf_sz);
676 else
677 mlx5_write64((__be32 *)ctrl, sq->uar_map + ofst, NULL);
678 /* flush the write-combining mapped buffer */
679 wmb();
680
681 sq->bf_offset ^= sq->bf_buf_size;
682 }
683
684 static inline void mlx5e_cq_arm(struct mlx5e_cq *cq)
685 {
686 struct mlx5_core_cq *mcq;
687
688 mcq = &cq->mcq;
689 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
690 }
691
692 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev *mdev)
693 {
694 return min_t(int, mdev->priv.eq_table.num_comp_vectors,
695 MLX5E_MAX_NUM_CHANNELS);
696 }
697
698 static inline int mlx5e_get_mtt_octw(int npages)
699 {
700 return ALIGN(npages, 8) / 2;
701 }
702
703 extern const struct ethtool_ops mlx5e_ethtool_ops;
704 #ifdef CONFIG_MLX5_CORE_EN_DCB
705 extern const struct dcbnl_rtnl_ops mlx5e_dcbnl_ops;
706 int mlx5e_dcbnl_ieee_setets_core(struct mlx5e_priv *priv, struct ieee_ets *ets);
707 #endif
708
709 #ifndef CONFIG_RFS_ACCEL
710 static inline int mlx5e_arfs_create_tables(struct mlx5e_priv *priv)
711 {
712 return 0;
713 }
714
715 static inline void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv) {}
716
717 static inline int mlx5e_arfs_enable(struct mlx5e_priv *priv)
718 {
719 return -ENOTSUPP;
720 }
721
722 static inline int mlx5e_arfs_disable(struct mlx5e_priv *priv)
723 {
724 return -ENOTSUPP;
725 }
726 #else
727 int mlx5e_arfs_create_tables(struct mlx5e_priv *priv);
728 void mlx5e_arfs_destroy_tables(struct mlx5e_priv *priv);
729 int mlx5e_arfs_enable(struct mlx5e_priv *priv);
730 int mlx5e_arfs_disable(struct mlx5e_priv *priv);
731 int mlx5e_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
732 u16 rxq_index, u32 flow_id);
733 #endif
734
735 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev);
736
737 #endif /* __MLX5_EN_H__ */
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