2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <net/pkt_cls.h>
35 #include <linux/mlx5/fs.h>
36 #include <net/vxlan.h>
37 #include <linux/bpf.h>
42 #include "en_accel/ipsec.h"
43 #include "en_accel/ipsec_rxtx.h"
44 #include "accel/ipsec.h"
47 struct mlx5e_rq_param
{
48 u32 rqc
[MLX5_ST_SZ_DW(rqc
)];
49 struct mlx5_wq_param wq
;
52 struct mlx5e_sq_param
{
53 u32 sqc
[MLX5_ST_SZ_DW(sqc
)];
54 struct mlx5_wq_param wq
;
57 struct mlx5e_cq_param
{
58 u32 cqc
[MLX5_ST_SZ_DW(cqc
)];
59 struct mlx5_wq_param wq
;
64 struct mlx5e_channel_param
{
65 struct mlx5e_rq_param rq
;
66 struct mlx5e_sq_param sq
;
67 struct mlx5e_sq_param xdp_sq
;
68 struct mlx5e_sq_param icosq
;
69 struct mlx5e_cq_param rx_cq
;
70 struct mlx5e_cq_param tx_cq
;
71 struct mlx5e_cq_param icosq_cq
;
74 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev
*mdev
)
76 return MLX5_CAP_GEN(mdev
, striding_rq
) &&
77 MLX5_CAP_GEN(mdev
, umr_ptr_rlky
) &&
78 MLX5_CAP_ETH(mdev
, reg_umr_sq
);
81 void mlx5e_init_rq_type_params(struct mlx5_core_dev
*mdev
,
82 struct mlx5e_params
*params
, u8 rq_type
)
84 params
->rq_wq_type
= rq_type
;
85 params
->lro_wqe_sz
= MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
;
86 switch (params
->rq_wq_type
) {
87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
88 params
->log_rq_size
= is_kdump_kernel() ?
89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW
:
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW
;
91 params
->mpwqe_log_stride_sz
= MLX5E_MPWQE_STRIDE_SZ(mdev
,
92 MLX5E_GET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
));
93 params
->mpwqe_log_num_strides
= MLX5_MPWRQ_LOG_WQE_SZ
-
94 params
->mpwqe_log_stride_sz
;
96 default: /* MLX5_WQ_TYPE_LINKED_LIST */
97 params
->log_rq_size
= is_kdump_kernel() ?
98 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE
:
99 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE
;
100 params
->rq_headroom
= params
->xdp_prog
?
101 XDP_PACKET_HEADROOM
: MLX5_RX_HEADROOM
;
102 params
->rq_headroom
+= NET_IP_ALIGN
;
104 /* Extra room needed for build_skb */
105 params
->lro_wqe_sz
-= params
->rq_headroom
+
106 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
109 mlx5_core_info(mdev
, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
110 params
->rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
,
111 BIT(params
->log_rq_size
),
112 BIT(params
->mpwqe_log_stride_sz
),
113 MLX5E_GET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
));
116 static void mlx5e_set_rq_params(struct mlx5_core_dev
*mdev
,
117 struct mlx5e_params
*params
)
119 u8 rq_type
= mlx5e_check_fragmented_striding_rq_cap(mdev
) &&
120 !params
->xdp_prog
&& !MLX5_IPSEC_DEV(mdev
) ?
121 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
122 MLX5_WQ_TYPE_LINKED_LIST
;
123 mlx5e_init_rq_type_params(mdev
, params
, rq_type
);
126 static void mlx5e_update_carrier(struct mlx5e_priv
*priv
)
128 struct mlx5_core_dev
*mdev
= priv
->mdev
;
131 port_state
= mlx5_query_vport_state(mdev
,
132 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
,
135 if (port_state
== VPORT_STATE_UP
) {
136 netdev_info(priv
->netdev
, "Link up\n");
137 netif_carrier_on(priv
->netdev
);
139 netdev_info(priv
->netdev
, "Link down\n");
140 netif_carrier_off(priv
->netdev
);
144 static void mlx5e_update_carrier_work(struct work_struct
*work
)
146 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
147 update_carrier_work
);
149 mutex_lock(&priv
->state_lock
);
150 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
151 if (priv
->profile
->update_carrier
)
152 priv
->profile
->update_carrier(priv
);
153 mutex_unlock(&priv
->state_lock
);
156 static void mlx5e_tx_timeout_work(struct work_struct
*work
)
158 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
163 mutex_lock(&priv
->state_lock
);
164 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
166 mlx5e_close_locked(priv
->netdev
);
167 err
= mlx5e_open_locked(priv
->netdev
);
169 netdev_err(priv
->netdev
, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
172 mutex_unlock(&priv
->state_lock
);
176 static void mlx5e_update_sw_counters(struct mlx5e_priv
*priv
)
178 struct mlx5e_sw_stats temp
, *s
= &temp
;
179 struct mlx5e_rq_stats
*rq_stats
;
180 struct mlx5e_sq_stats
*sq_stats
;
183 memset(s
, 0, sizeof(*s
));
184 for (i
= 0; i
< priv
->channels
.num
; i
++) {
185 struct mlx5e_channel
*c
= priv
->channels
.c
[i
];
187 rq_stats
= &c
->rq
.stats
;
189 s
->rx_packets
+= rq_stats
->packets
;
190 s
->rx_bytes
+= rq_stats
->bytes
;
191 s
->rx_lro_packets
+= rq_stats
->lro_packets
;
192 s
->rx_lro_bytes
+= rq_stats
->lro_bytes
;
193 s
->rx_removed_vlan_packets
+= rq_stats
->removed_vlan_packets
;
194 s
->rx_csum_none
+= rq_stats
->csum_none
;
195 s
->rx_csum_complete
+= rq_stats
->csum_complete
;
196 s
->rx_csum_unnecessary
+= rq_stats
->csum_unnecessary
;
197 s
->rx_csum_unnecessary_inner
+= rq_stats
->csum_unnecessary_inner
;
198 s
->rx_xdp_drop
+= rq_stats
->xdp_drop
;
199 s
->rx_xdp_tx
+= rq_stats
->xdp_tx
;
200 s
->rx_xdp_tx_full
+= rq_stats
->xdp_tx_full
;
201 s
->rx_wqe_err
+= rq_stats
->wqe_err
;
202 s
->rx_mpwqe_filler
+= rq_stats
->mpwqe_filler
;
203 s
->rx_buff_alloc_err
+= rq_stats
->buff_alloc_err
;
204 s
->rx_cqe_compress_blks
+= rq_stats
->cqe_compress_blks
;
205 s
->rx_cqe_compress_pkts
+= rq_stats
->cqe_compress_pkts
;
206 s
->rx_page_reuse
+= rq_stats
->page_reuse
;
207 s
->rx_cache_reuse
+= rq_stats
->cache_reuse
;
208 s
->rx_cache_full
+= rq_stats
->cache_full
;
209 s
->rx_cache_empty
+= rq_stats
->cache_empty
;
210 s
->rx_cache_busy
+= rq_stats
->cache_busy
;
211 s
->rx_cache_waive
+= rq_stats
->cache_waive
;
213 for (j
= 0; j
< priv
->channels
.params
.num_tc
; j
++) {
214 sq_stats
= &c
->sq
[j
].stats
;
216 s
->tx_packets
+= sq_stats
->packets
;
217 s
->tx_bytes
+= sq_stats
->bytes
;
218 s
->tx_tso_packets
+= sq_stats
->tso_packets
;
219 s
->tx_tso_bytes
+= sq_stats
->tso_bytes
;
220 s
->tx_tso_inner_packets
+= sq_stats
->tso_inner_packets
;
221 s
->tx_tso_inner_bytes
+= sq_stats
->tso_inner_bytes
;
222 s
->tx_added_vlan_packets
+= sq_stats
->added_vlan_packets
;
223 s
->tx_queue_stopped
+= sq_stats
->stopped
;
224 s
->tx_queue_wake
+= sq_stats
->wake
;
225 s
->tx_queue_dropped
+= sq_stats
->dropped
;
226 s
->tx_xmit_more
+= sq_stats
->xmit_more
;
227 s
->tx_csum_partial_inner
+= sq_stats
->csum_partial_inner
;
228 s
->tx_csum_none
+= sq_stats
->csum_none
;
229 s
->tx_csum_partial
+= sq_stats
->csum_partial
;
233 s
->link_down_events_phy
= MLX5_GET(ppcnt_reg
,
234 priv
->stats
.pport
.phy_counters
,
235 counter_set
.phys_layer_cntrs
.link_down_events
);
236 memcpy(&priv
->stats
.sw
, s
, sizeof(*s
));
239 static void mlx5e_update_vport_counters(struct mlx5e_priv
*priv
)
241 int outlen
= MLX5_ST_SZ_BYTES(query_vport_counter_out
);
242 u32
*out
= (u32
*)priv
->stats
.vport
.query_vport_out
;
243 u32 in
[MLX5_ST_SZ_DW(query_vport_counter_in
)] = {0};
244 struct mlx5_core_dev
*mdev
= priv
->mdev
;
246 MLX5_SET(query_vport_counter_in
, in
, opcode
,
247 MLX5_CMD_OP_QUERY_VPORT_COUNTER
);
248 MLX5_SET(query_vport_counter_in
, in
, op_mod
, 0);
249 MLX5_SET(query_vport_counter_in
, in
, other_vport
, 0);
251 mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, outlen
);
254 static void mlx5e_update_pport_counters(struct mlx5e_priv
*priv
, bool full
)
256 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
257 struct mlx5_core_dev
*mdev
= priv
->mdev
;
258 u32 in
[MLX5_ST_SZ_DW(ppcnt_reg
)] = {0};
259 int sz
= MLX5_ST_SZ_BYTES(ppcnt_reg
);
263 MLX5_SET(ppcnt_reg
, in
, local_port
, 1);
265 out
= pstats
->IEEE_802_3_counters
;
266 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_IEEE_802_3_COUNTERS_GROUP
);
267 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
272 out
= pstats
->RFC_2863_counters
;
273 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2863_COUNTERS_GROUP
);
274 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
276 out
= pstats
->RFC_2819_counters
;
277 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2819_COUNTERS_GROUP
);
278 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
280 out
= pstats
->phy_counters
;
281 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP
);
282 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
284 if (MLX5_CAP_PCAM_FEATURE(mdev
, ppcnt_statistical_group
)) {
285 out
= pstats
->phy_statistical_counters
;
286 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP
);
287 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
290 if (MLX5_CAP_PCAM_FEATURE(mdev
, rx_buffer_fullness_counters
)) {
291 out
= pstats
->eth_ext_counters
;
292 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP
);
293 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
296 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PER_PRIORITY_COUNTERS_GROUP
);
297 for (prio
= 0; prio
< NUM_PPORT_PRIO
; prio
++) {
298 out
= pstats
->per_prio_counters
[prio
];
299 MLX5_SET(ppcnt_reg
, in
, prio_tc
, prio
);
300 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
,
301 MLX5_REG_PPCNT
, 0, 0);
305 static void mlx5e_update_q_counter(struct mlx5e_priv
*priv
)
307 struct mlx5e_qcounter_stats
*qcnt
= &priv
->stats
.qcnt
;
308 u32 out
[MLX5_ST_SZ_DW(query_q_counter_out
)];
311 if (!priv
->q_counter
)
314 err
= mlx5_core_query_q_counter(priv
->mdev
, priv
->q_counter
, 0, out
, sizeof(out
));
318 qcnt
->rx_out_of_buffer
= MLX5_GET(query_q_counter_out
, out
, out_of_buffer
);
321 static void mlx5e_update_pcie_counters(struct mlx5e_priv
*priv
)
323 struct mlx5e_pcie_stats
*pcie_stats
= &priv
->stats
.pcie
;
324 struct mlx5_core_dev
*mdev
= priv
->mdev
;
325 u32 in
[MLX5_ST_SZ_DW(mpcnt_reg
)] = {0};
326 int sz
= MLX5_ST_SZ_BYTES(mpcnt_reg
);
329 if (!MLX5_CAP_MCAM_FEATURE(mdev
, pcie_performance_group
))
332 out
= pcie_stats
->pcie_perf_counters
;
333 MLX5_SET(mpcnt_reg
, in
, grp
, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP
);
334 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_MPCNT
, 0, 0);
337 void mlx5e_update_stats(struct mlx5e_priv
*priv
, bool full
)
340 mlx5e_update_pcie_counters(priv
);
341 mlx5e_ipsec_update_stats(priv
);
343 mlx5e_update_pport_counters(priv
, full
);
344 mlx5e_update_vport_counters(priv
);
345 mlx5e_update_q_counter(priv
);
346 mlx5e_update_sw_counters(priv
);
349 static void mlx5e_update_ndo_stats(struct mlx5e_priv
*priv
)
351 mlx5e_update_stats(priv
, false);
354 void mlx5e_update_stats_work(struct work_struct
*work
)
356 struct delayed_work
*dwork
= to_delayed_work(work
);
357 struct mlx5e_priv
*priv
= container_of(dwork
, struct mlx5e_priv
,
359 mutex_lock(&priv
->state_lock
);
360 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
361 priv
->profile
->update_stats(priv
);
362 queue_delayed_work(priv
->wq
, dwork
,
363 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL
));
365 mutex_unlock(&priv
->state_lock
);
368 static void mlx5e_async_event(struct mlx5_core_dev
*mdev
, void *vpriv
,
369 enum mlx5_dev_event event
, unsigned long param
)
371 struct mlx5e_priv
*priv
= vpriv
;
373 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
))
377 case MLX5_DEV_EVENT_PORT_UP
:
378 case MLX5_DEV_EVENT_PORT_DOWN
:
379 queue_work(priv
->wq
, &priv
->update_carrier_work
);
386 static void mlx5e_enable_async_events(struct mlx5e_priv
*priv
)
388 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
391 static void mlx5e_disable_async_events(struct mlx5e_priv
*priv
)
393 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
394 synchronize_irq(pci_irq_vector(priv
->mdev
->pdev
, MLX5_EQ_VEC_ASYNC
));
397 static inline int mlx5e_get_wqe_mtt_sz(void)
399 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
400 * To avoid copying garbage after the mtt array, we allocate
403 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE
* sizeof(__be64
),
404 MLX5_UMR_MTT_ALIGNMENT
);
407 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq
*rq
,
408 struct mlx5e_icosq
*sq
,
409 struct mlx5e_umr_wqe
*wqe
,
412 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
413 struct mlx5_wqe_umr_ctrl_seg
*ucseg
= &wqe
->uctrl
;
414 struct mlx5_wqe_data_seg
*dseg
= &wqe
->data
;
415 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
416 u8 ds_cnt
= DIV_ROUND_UP(sizeof(*wqe
), MLX5_SEND_WQE_DS
);
417 u32 umr_wqe_mtt_offset
= mlx5e_get_wqe_mtt_offset(rq
, ix
);
419 cseg
->qpn_ds
= cpu_to_be32((sq
->sqn
<< MLX5_WQE_CTRL_QPN_SHIFT
) |
421 cseg
->fm_ce_se
= MLX5_WQE_CTRL_CQ_UPDATE
;
422 cseg
->imm
= rq
->mkey_be
;
424 ucseg
->flags
= MLX5_UMR_TRANSLATION_OFFSET_EN
;
425 ucseg
->xlt_octowords
=
426 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE
));
427 ucseg
->bsf_octowords
=
428 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset
));
429 ucseg
->mkey_mask
= cpu_to_be64(MLX5_MKEY_MASK_FREE
);
431 dseg
->lkey
= sq
->mkey_be
;
432 dseg
->addr
= cpu_to_be64(wi
->umr
.mtt_addr
);
435 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq
*rq
,
436 struct mlx5e_channel
*c
)
438 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
439 int mtt_sz
= mlx5e_get_wqe_mtt_sz();
440 int mtt_alloc
= mtt_sz
+ MLX5_UMR_ALIGN
- 1;
443 rq
->mpwqe
.info
= kzalloc_node(wq_sz
* sizeof(*rq
->mpwqe
.info
),
444 GFP_KERNEL
, cpu_to_node(c
->cpu
));
448 /* We allocate more than mtt_sz as we will align the pointer */
449 rq
->mpwqe
.mtt_no_align
= kzalloc_node(mtt_alloc
* wq_sz
, GFP_KERNEL
,
450 cpu_to_node(c
->cpu
));
451 if (unlikely(!rq
->mpwqe
.mtt_no_align
))
452 goto err_free_wqe_info
;
454 for (i
= 0; i
< wq_sz
; i
++) {
455 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
457 wi
->umr
.mtt
= PTR_ALIGN(rq
->mpwqe
.mtt_no_align
+ i
* mtt_alloc
,
459 wi
->umr
.mtt_addr
= dma_map_single(c
->pdev
, wi
->umr
.mtt
, mtt_sz
,
461 if (unlikely(dma_mapping_error(c
->pdev
, wi
->umr
.mtt_addr
)))
464 mlx5e_build_umr_wqe(rq
, &c
->icosq
, &wi
->umr
.wqe
, i
);
471 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
473 dma_unmap_single(c
->pdev
, wi
->umr
.mtt_addr
, mtt_sz
,
476 kfree(rq
->mpwqe
.mtt_no_align
);
478 kfree(rq
->mpwqe
.info
);
484 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq
*rq
)
486 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
487 int mtt_sz
= mlx5e_get_wqe_mtt_sz();
490 for (i
= 0; i
< wq_sz
; i
++) {
491 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
493 dma_unmap_single(rq
->pdev
, wi
->umr
.mtt_addr
, mtt_sz
,
496 kfree(rq
->mpwqe
.mtt_no_align
);
497 kfree(rq
->mpwqe
.info
);
500 static int mlx5e_create_umr_mkey(struct mlx5_core_dev
*mdev
,
501 u64 npages
, u8 page_shift
,
502 struct mlx5_core_mkey
*umr_mkey
)
504 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
509 if (!MLX5E_VALID_NUM_MTTS(npages
))
512 in
= kvzalloc(inlen
, GFP_KERNEL
);
516 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
518 MLX5_SET(mkc
, mkc
, free
, 1);
519 MLX5_SET(mkc
, mkc
, umr_en
, 1);
520 MLX5_SET(mkc
, mkc
, lw
, 1);
521 MLX5_SET(mkc
, mkc
, lr
, 1);
522 MLX5_SET(mkc
, mkc
, access_mode
, MLX5_MKC_ACCESS_MODE_MTT
);
524 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
525 MLX5_SET(mkc
, mkc
, pd
, mdev
->mlx5e_res
.pdn
);
526 MLX5_SET64(mkc
, mkc
, len
, npages
<< page_shift
);
527 MLX5_SET(mkc
, mkc
, translations_octword_size
,
528 MLX5_MTT_OCTW(npages
));
529 MLX5_SET(mkc
, mkc
, log_page_size
, page_shift
);
531 err
= mlx5_core_create_mkey(mdev
, umr_mkey
, in
, inlen
);
537 static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev
*mdev
, struct mlx5e_rq
*rq
)
539 u64 num_mtts
= MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq
->wq
));
541 return mlx5e_create_umr_mkey(mdev
, num_mtts
, PAGE_SHIFT
, &rq
->umr_mkey
);
544 static int mlx5e_alloc_rq(struct mlx5e_channel
*c
,
545 struct mlx5e_params
*params
,
546 struct mlx5e_rq_param
*rqp
,
549 struct mlx5_core_dev
*mdev
= c
->mdev
;
550 void *rqc
= rqp
->rqc
;
551 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
558 rqp
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
560 err
= mlx5_wq_ll_create(mdev
, &rqp
->wq
, rqc_wq
, &rq
->wq
,
565 rq
->wq
.db
= &rq
->wq
.db
[MLX5_RCV_DBR
];
567 wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
569 rq
->wq_type
= params
->rq_wq_type
;
571 rq
->netdev
= c
->netdev
;
572 rq
->tstamp
= c
->tstamp
;
573 rq
->clock
= &mdev
->clock
;
578 rq
->xdp_prog
= params
->xdp_prog
? bpf_prog_inc(params
->xdp_prog
) : NULL
;
579 if (IS_ERR(rq
->xdp_prog
)) {
580 err
= PTR_ERR(rq
->xdp_prog
);
582 goto err_rq_wq_destroy
;
585 rq
->buff
.map_dir
= rq
->xdp_prog
? DMA_BIDIRECTIONAL
: DMA_FROM_DEVICE
;
586 rq
->buff
.headroom
= params
->rq_headroom
;
588 switch (rq
->wq_type
) {
589 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
591 rq
->post_wqes
= mlx5e_post_rx_mpwqes
;
592 rq
->dealloc_wqe
= mlx5e_dealloc_rx_mpwqe
;
594 rq
->handle_rx_cqe
= c
->priv
->profile
->rx_handlers
.handle_rx_cqe_mpwqe
;
595 #ifdef CONFIG_MLX5_EN_IPSEC
596 if (MLX5_IPSEC_DEV(mdev
)) {
598 netdev_err(c
->netdev
, "MPWQE RQ with IPSec offload not supported\n");
599 goto err_rq_wq_destroy
;
602 if (!rq
->handle_rx_cqe
) {
604 netdev_err(c
->netdev
, "RX handler of MPWQE RQ is not set, err %d\n", err
);
605 goto err_rq_wq_destroy
;
608 rq
->mpwqe
.log_stride_sz
= params
->mpwqe_log_stride_sz
;
609 rq
->mpwqe
.num_strides
= BIT(params
->mpwqe_log_num_strides
);
611 byte_count
= rq
->mpwqe
.num_strides
<< rq
->mpwqe
.log_stride_sz
;
613 err
= mlx5e_create_rq_umr_mkey(mdev
, rq
);
615 goto err_rq_wq_destroy
;
616 rq
->mkey_be
= cpu_to_be32(rq
->umr_mkey
.key
);
618 err
= mlx5e_rq_alloc_mpwqe_info(rq
, c
);
620 goto err_destroy_umr_mkey
;
622 default: /* MLX5_WQ_TYPE_LINKED_LIST */
624 kzalloc_node(wq_sz
* sizeof(*rq
->wqe
.frag_info
),
625 GFP_KERNEL
, cpu_to_node(c
->cpu
));
626 if (!rq
->wqe
.frag_info
) {
628 goto err_rq_wq_destroy
;
630 rq
->post_wqes
= mlx5e_post_rx_wqes
;
631 rq
->dealloc_wqe
= mlx5e_dealloc_rx_wqe
;
633 #ifdef CONFIG_MLX5_EN_IPSEC
635 rq
->handle_rx_cqe
= mlx5e_ipsec_handle_rx_cqe
;
638 rq
->handle_rx_cqe
= c
->priv
->profile
->rx_handlers
.handle_rx_cqe
;
639 if (!rq
->handle_rx_cqe
) {
640 kfree(rq
->wqe
.frag_info
);
642 netdev_err(c
->netdev
, "RX handler of RQ is not set, err %d\n", err
);
643 goto err_rq_wq_destroy
;
646 byte_count
= params
->lro_en
?
648 MLX5E_SW2HW_MTU(c
->priv
, c
->netdev
->mtu
);
649 #ifdef CONFIG_MLX5_EN_IPSEC
650 if (MLX5_IPSEC_DEV(mdev
))
651 byte_count
+= MLX5E_METADATA_ETHER_LEN
;
653 rq
->wqe
.page_reuse
= !params
->xdp_prog
&& !params
->lro_en
;
655 /* calc the required page order */
656 rq
->wqe
.frag_sz
= MLX5_SKB_FRAG_SZ(rq
->buff
.headroom
+ byte_count
);
657 npages
= DIV_ROUND_UP(rq
->wqe
.frag_sz
, PAGE_SIZE
);
658 rq
->buff
.page_order
= order_base_2(npages
);
660 byte_count
|= MLX5_HW_START_PADDING
;
661 rq
->mkey_be
= c
->mkey_be
;
664 for (i
= 0; i
< wq_sz
; i
++) {
665 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, i
);
667 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
) {
668 u64 dma_offset
= (u64
)mlx5e_get_wqe_mtt_offset(rq
, i
) << PAGE_SHIFT
;
670 wqe
->data
.addr
= cpu_to_be64(dma_offset
);
673 wqe
->data
.byte_count
= cpu_to_be32(byte_count
);
674 wqe
->data
.lkey
= rq
->mkey_be
;
677 INIT_WORK(&rq
->am
.work
, mlx5e_rx_am_work
);
678 rq
->am
.mode
= params
->rx_cq_moderation
.cq_period_mode
;
679 rq
->page_cache
.head
= 0;
680 rq
->page_cache
.tail
= 0;
684 err_destroy_umr_mkey
:
685 mlx5_core_destroy_mkey(mdev
, &rq
->umr_mkey
);
689 bpf_prog_put(rq
->xdp_prog
);
690 mlx5_wq_destroy(&rq
->wq_ctrl
);
695 static void mlx5e_free_rq(struct mlx5e_rq
*rq
)
700 bpf_prog_put(rq
->xdp_prog
);
702 switch (rq
->wq_type
) {
703 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
704 mlx5e_rq_free_mpwqe_info(rq
);
705 mlx5_core_destroy_mkey(rq
->mdev
, &rq
->umr_mkey
);
707 default: /* MLX5_WQ_TYPE_LINKED_LIST */
708 kfree(rq
->wqe
.frag_info
);
711 for (i
= rq
->page_cache
.head
; i
!= rq
->page_cache
.tail
;
712 i
= (i
+ 1) & (MLX5E_CACHE_SIZE
- 1)) {
713 struct mlx5e_dma_info
*dma_info
= &rq
->page_cache
.page_cache
[i
];
715 mlx5e_page_release(rq
, dma_info
, false);
717 mlx5_wq_destroy(&rq
->wq_ctrl
);
720 static int mlx5e_create_rq(struct mlx5e_rq
*rq
,
721 struct mlx5e_rq_param
*param
)
723 struct mlx5_core_dev
*mdev
= rq
->mdev
;
731 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) +
732 sizeof(u64
) * rq
->wq_ctrl
.buf
.npages
;
733 in
= kvzalloc(inlen
, GFP_KERNEL
);
737 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
738 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
740 memcpy(rqc
, param
->rqc
, sizeof(param
->rqc
));
742 MLX5_SET(rqc
, rqc
, cqn
, rq
->cq
.mcq
.cqn
);
743 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
744 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rq
->wq_ctrl
.buf
.page_shift
-
745 MLX5_ADAPTER_PAGE_SHIFT
);
746 MLX5_SET64(wq
, wq
, dbr_addr
, rq
->wq_ctrl
.db
.dma
);
748 mlx5_fill_page_array(&rq
->wq_ctrl
.buf
,
749 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
751 err
= mlx5_core_create_rq(mdev
, in
, inlen
, &rq
->rqn
);
758 static int mlx5e_modify_rq_state(struct mlx5e_rq
*rq
, int curr_state
,
761 struct mlx5e_channel
*c
= rq
->channel
;
762 struct mlx5_core_dev
*mdev
= c
->mdev
;
769 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
770 in
= kvzalloc(inlen
, GFP_KERNEL
);
774 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
776 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_state
);
777 MLX5_SET(rqc
, rqc
, state
, next_state
);
779 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
786 static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq
*rq
, bool enable
)
788 struct mlx5e_channel
*c
= rq
->channel
;
789 struct mlx5e_priv
*priv
= c
->priv
;
790 struct mlx5_core_dev
*mdev
= priv
->mdev
;
797 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
798 in
= kvzalloc(inlen
, GFP_KERNEL
);
802 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
804 MLX5_SET(modify_rq_in
, in
, rq_state
, MLX5_RQC_STATE_RDY
);
805 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
806 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS
);
807 MLX5_SET(rqc
, rqc
, scatter_fcs
, enable
);
808 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RDY
);
810 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
817 static int mlx5e_modify_rq_vsd(struct mlx5e_rq
*rq
, bool vsd
)
819 struct mlx5e_channel
*c
= rq
->channel
;
820 struct mlx5_core_dev
*mdev
= c
->mdev
;
826 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
827 in
= kvzalloc(inlen
, GFP_KERNEL
);
831 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
833 MLX5_SET(modify_rq_in
, in
, rq_state
, MLX5_RQC_STATE_RDY
);
834 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
835 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD
);
836 MLX5_SET(rqc
, rqc
, vsd
, vsd
);
837 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RDY
);
839 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
846 static void mlx5e_destroy_rq(struct mlx5e_rq
*rq
)
848 mlx5_core_destroy_rq(rq
->mdev
, rq
->rqn
);
851 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
)
853 unsigned long exp_time
= jiffies
+ msecs_to_jiffies(20000);
854 struct mlx5e_channel
*c
= rq
->channel
;
856 struct mlx5_wq_ll
*wq
= &rq
->wq
;
857 u16 min_wqes
= mlx5_min_rx_wqes(rq
->wq_type
, mlx5_wq_ll_get_size(wq
));
859 while (time_before(jiffies
, exp_time
)) {
860 if (wq
->cur_sz
>= min_wqes
)
866 netdev_warn(c
->netdev
, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
867 rq
->rqn
, wq
->cur_sz
, min_wqes
);
871 static void mlx5e_free_rx_descs(struct mlx5e_rq
*rq
)
873 struct mlx5_wq_ll
*wq
= &rq
->wq
;
874 struct mlx5e_rx_wqe
*wqe
;
878 /* UMR WQE (if in progress) is always at wq->head */
879 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
&&
880 rq
->mpwqe
.umr_in_progress
)
881 mlx5e_free_rx_mpwqe(rq
, &rq
->mpwqe
.info
[wq
->head
]);
883 while (!mlx5_wq_ll_is_empty(wq
)) {
884 wqe_ix_be
= *wq
->tail_next
;
885 wqe_ix
= be16_to_cpu(wqe_ix_be
);
886 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_ix
);
887 rq
->dealloc_wqe(rq
, wqe_ix
);
888 mlx5_wq_ll_pop(&rq
->wq
, wqe_ix_be
,
889 &wqe
->next
.next_wqe_index
);
892 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST
&& rq
->wqe
.page_reuse
) {
893 /* Clean outstanding pages on handled WQEs that decided to do page-reuse,
894 * but yet to be re-posted.
896 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
898 for (wqe_ix
= 0; wqe_ix
< wq_sz
; wqe_ix
++)
899 rq
->dealloc_wqe(rq
, wqe_ix
);
903 static int mlx5e_open_rq(struct mlx5e_channel
*c
,
904 struct mlx5e_params
*params
,
905 struct mlx5e_rq_param
*param
,
910 err
= mlx5e_alloc_rq(c
, params
, param
, rq
);
914 err
= mlx5e_create_rq(rq
, param
);
918 err
= mlx5e_modify_rq_state(rq
, MLX5_RQC_STATE_RST
, MLX5_RQC_STATE_RDY
);
922 if (params
->rx_am_enabled
)
923 c
->rq
.state
|= BIT(MLX5E_RQ_STATE_AM
);
928 mlx5e_destroy_rq(rq
);
935 static void mlx5e_activate_rq(struct mlx5e_rq
*rq
)
937 struct mlx5e_icosq
*sq
= &rq
->channel
->icosq
;
938 u16 pi
= sq
->pc
& sq
->wq
.sz_m1
;
939 struct mlx5e_tx_wqe
*nopwqe
;
941 set_bit(MLX5E_RQ_STATE_ENABLED
, &rq
->state
);
942 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_NOP
;
943 nopwqe
= mlx5e_post_nop(&sq
->wq
, sq
->sqn
, &sq
->pc
);
944 mlx5e_notify_hw(&sq
->wq
, sq
->pc
, sq
->uar_map
, &nopwqe
->ctrl
);
947 static void mlx5e_deactivate_rq(struct mlx5e_rq
*rq
)
949 clear_bit(MLX5E_RQ_STATE_ENABLED
, &rq
->state
);
950 napi_synchronize(&rq
->channel
->napi
); /* prevent mlx5e_post_rx_wqes */
953 static void mlx5e_close_rq(struct mlx5e_rq
*rq
)
955 cancel_work_sync(&rq
->am
.work
);
956 mlx5e_destroy_rq(rq
);
957 mlx5e_free_rx_descs(rq
);
961 static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq
*sq
)
966 static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq
*sq
, int numa
)
968 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
970 sq
->db
.di
= kzalloc_node(sizeof(*sq
->db
.di
) * wq_sz
,
973 mlx5e_free_xdpsq_db(sq
);
980 static int mlx5e_alloc_xdpsq(struct mlx5e_channel
*c
,
981 struct mlx5e_params
*params
,
982 struct mlx5e_sq_param
*param
,
983 struct mlx5e_xdpsq
*sq
)
985 void *sqc_wq
= MLX5_ADDR_OF(sqc
, param
->sqc
, wq
);
986 struct mlx5_core_dev
*mdev
= c
->mdev
;
990 sq
->mkey_be
= c
->mkey_be
;
992 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
993 sq
->min_inline_mode
= params
->tx_min_inline_mode
;
995 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
996 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
, &sq
->wq_ctrl
);
999 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1001 err
= mlx5e_alloc_xdpsq_db(sq
, cpu_to_node(c
->cpu
));
1003 goto err_sq_wq_destroy
;
1008 mlx5_wq_destroy(&sq
->wq_ctrl
);
1013 static void mlx5e_free_xdpsq(struct mlx5e_xdpsq
*sq
)
1015 mlx5e_free_xdpsq_db(sq
);
1016 mlx5_wq_destroy(&sq
->wq_ctrl
);
1019 static void mlx5e_free_icosq_db(struct mlx5e_icosq
*sq
)
1021 kfree(sq
->db
.ico_wqe
);
1024 static int mlx5e_alloc_icosq_db(struct mlx5e_icosq
*sq
, int numa
)
1026 u8 wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
1028 sq
->db
.ico_wqe
= kzalloc_node(sizeof(*sq
->db
.ico_wqe
) * wq_sz
,
1030 if (!sq
->db
.ico_wqe
)
1036 static int mlx5e_alloc_icosq(struct mlx5e_channel
*c
,
1037 struct mlx5e_sq_param
*param
,
1038 struct mlx5e_icosq
*sq
)
1040 void *sqc_wq
= MLX5_ADDR_OF(sqc
, param
->sqc
, wq
);
1041 struct mlx5_core_dev
*mdev
= c
->mdev
;
1044 sq
->mkey_be
= c
->mkey_be
;
1046 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
1048 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
1049 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
, &sq
->wq_ctrl
);
1052 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1054 err
= mlx5e_alloc_icosq_db(sq
, cpu_to_node(c
->cpu
));
1056 goto err_sq_wq_destroy
;
1058 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5E_ICOSQ_MAX_WQEBBS
;
1063 mlx5_wq_destroy(&sq
->wq_ctrl
);
1068 static void mlx5e_free_icosq(struct mlx5e_icosq
*sq
)
1070 mlx5e_free_icosq_db(sq
);
1071 mlx5_wq_destroy(&sq
->wq_ctrl
);
1074 static void mlx5e_free_txqsq_db(struct mlx5e_txqsq
*sq
)
1076 kfree(sq
->db
.wqe_info
);
1077 kfree(sq
->db
.dma_fifo
);
1080 static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq
*sq
, int numa
)
1082 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
1083 int df_sz
= wq_sz
* MLX5_SEND_WQEBB_NUM_DS
;
1085 sq
->db
.dma_fifo
= kzalloc_node(df_sz
* sizeof(*sq
->db
.dma_fifo
),
1087 sq
->db
.wqe_info
= kzalloc_node(wq_sz
* sizeof(*sq
->db
.wqe_info
),
1089 if (!sq
->db
.dma_fifo
|| !sq
->db
.wqe_info
) {
1090 mlx5e_free_txqsq_db(sq
);
1094 sq
->dma_fifo_mask
= df_sz
- 1;
1099 static int mlx5e_alloc_txqsq(struct mlx5e_channel
*c
,
1101 struct mlx5e_params
*params
,
1102 struct mlx5e_sq_param
*param
,
1103 struct mlx5e_txqsq
*sq
)
1105 void *sqc_wq
= MLX5_ADDR_OF(sqc
, param
->sqc
, wq
);
1106 struct mlx5_core_dev
*mdev
= c
->mdev
;
1110 sq
->tstamp
= c
->tstamp
;
1111 sq
->clock
= &mdev
->clock
;
1112 sq
->mkey_be
= c
->mkey_be
;
1114 sq
->txq_ix
= txq_ix
;
1115 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
1116 sq
->max_inline
= params
->tx_max_inline
;
1117 sq
->min_inline_mode
= params
->tx_min_inline_mode
;
1118 if (MLX5_IPSEC_DEV(c
->priv
->mdev
))
1119 set_bit(MLX5E_SQ_STATE_IPSEC
, &sq
->state
);
1121 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
1122 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
, &sq
->wq_ctrl
);
1125 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1127 err
= mlx5e_alloc_txqsq_db(sq
, cpu_to_node(c
->cpu
));
1129 goto err_sq_wq_destroy
;
1131 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - MLX5_SEND_WQE_MAX_WQEBBS
;
1136 mlx5_wq_destroy(&sq
->wq_ctrl
);
1141 static void mlx5e_free_txqsq(struct mlx5e_txqsq
*sq
)
1143 mlx5e_free_txqsq_db(sq
);
1144 mlx5_wq_destroy(&sq
->wq_ctrl
);
1147 struct mlx5e_create_sq_param
{
1148 struct mlx5_wq_ctrl
*wq_ctrl
;
1155 static int mlx5e_create_sq(struct mlx5_core_dev
*mdev
,
1156 struct mlx5e_sq_param
*param
,
1157 struct mlx5e_create_sq_param
*csp
,
1166 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) +
1167 sizeof(u64
) * csp
->wq_ctrl
->buf
.npages
;
1168 in
= kvzalloc(inlen
, GFP_KERNEL
);
1172 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
1173 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1175 memcpy(sqc
, param
->sqc
, sizeof(param
->sqc
));
1176 MLX5_SET(sqc
, sqc
, tis_lst_sz
, csp
->tis_lst_sz
);
1177 MLX5_SET(sqc
, sqc
, tis_num_0
, csp
->tisn
);
1178 MLX5_SET(sqc
, sqc
, cqn
, csp
->cqn
);
1180 if (MLX5_CAP_ETH(mdev
, wqe_inline_mode
) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT
)
1181 MLX5_SET(sqc
, sqc
, min_wqe_inline_mode
, csp
->min_inline_mode
);
1183 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
1185 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
1186 MLX5_SET(wq
, wq
, uar_page
, mdev
->mlx5e_res
.bfreg
.index
);
1187 MLX5_SET(wq
, wq
, log_wq_pg_sz
, csp
->wq_ctrl
->buf
.page_shift
-
1188 MLX5_ADAPTER_PAGE_SHIFT
);
1189 MLX5_SET64(wq
, wq
, dbr_addr
, csp
->wq_ctrl
->db
.dma
);
1191 mlx5_fill_page_array(&csp
->wq_ctrl
->buf
, (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
1193 err
= mlx5_core_create_sq(mdev
, in
, inlen
, sqn
);
1200 struct mlx5e_modify_sq_param
{
1207 static int mlx5e_modify_sq(struct mlx5_core_dev
*mdev
, u32 sqn
,
1208 struct mlx5e_modify_sq_param
*p
)
1215 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
1216 in
= kvzalloc(inlen
, GFP_KERNEL
);
1220 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
1222 MLX5_SET(modify_sq_in
, in
, sq_state
, p
->curr_state
);
1223 MLX5_SET(sqc
, sqc
, state
, p
->next_state
);
1224 if (p
->rl_update
&& p
->next_state
== MLX5_SQC_STATE_RDY
) {
1225 MLX5_SET64(modify_sq_in
, in
, modify_bitmask
, 1);
1226 MLX5_SET(sqc
, sqc
, packet_pacing_rate_limit_index
, p
->rl_index
);
1229 err
= mlx5_core_modify_sq(mdev
, sqn
, in
, inlen
);
1236 static void mlx5e_destroy_sq(struct mlx5_core_dev
*mdev
, u32 sqn
)
1238 mlx5_core_destroy_sq(mdev
, sqn
);
1241 static int mlx5e_create_sq_rdy(struct mlx5_core_dev
*mdev
,
1242 struct mlx5e_sq_param
*param
,
1243 struct mlx5e_create_sq_param
*csp
,
1246 struct mlx5e_modify_sq_param msp
= {0};
1249 err
= mlx5e_create_sq(mdev
, param
, csp
, sqn
);
1253 msp
.curr_state
= MLX5_SQC_STATE_RST
;
1254 msp
.next_state
= MLX5_SQC_STATE_RDY
;
1255 err
= mlx5e_modify_sq(mdev
, *sqn
, &msp
);
1257 mlx5e_destroy_sq(mdev
, *sqn
);
1262 static int mlx5e_set_sq_maxrate(struct net_device
*dev
,
1263 struct mlx5e_txqsq
*sq
, u32 rate
);
1265 static int mlx5e_open_txqsq(struct mlx5e_channel
*c
,
1268 struct mlx5e_params
*params
,
1269 struct mlx5e_sq_param
*param
,
1270 struct mlx5e_txqsq
*sq
)
1272 struct mlx5e_create_sq_param csp
= {};
1276 err
= mlx5e_alloc_txqsq(c
, txq_ix
, params
, param
, sq
);
1282 csp
.cqn
= sq
->cq
.mcq
.cqn
;
1283 csp
.wq_ctrl
= &sq
->wq_ctrl
;
1284 csp
.min_inline_mode
= sq
->min_inline_mode
;
1285 err
= mlx5e_create_sq_rdy(c
->mdev
, param
, &csp
, &sq
->sqn
);
1287 goto err_free_txqsq
;
1289 tx_rate
= c
->priv
->tx_rates
[sq
->txq_ix
];
1291 mlx5e_set_sq_maxrate(c
->netdev
, sq
, tx_rate
);
1296 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1297 mlx5e_free_txqsq(sq
);
1302 static void mlx5e_activate_txqsq(struct mlx5e_txqsq
*sq
)
1304 sq
->txq
= netdev_get_tx_queue(sq
->channel
->netdev
, sq
->txq_ix
);
1305 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1306 netdev_tx_reset_queue(sq
->txq
);
1307 netif_tx_start_queue(sq
->txq
);
1310 static inline void netif_tx_disable_queue(struct netdev_queue
*txq
)
1312 __netif_tx_lock_bh(txq
);
1313 netif_tx_stop_queue(txq
);
1314 __netif_tx_unlock_bh(txq
);
1317 static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq
*sq
)
1319 struct mlx5e_channel
*c
= sq
->channel
;
1321 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1322 /* prevent netif_tx_wake_queue */
1323 napi_synchronize(&c
->napi
);
1325 netif_tx_disable_queue(sq
->txq
);
1327 /* last doorbell out, godspeed .. */
1328 if (mlx5e_wqc_has_room_for(&sq
->wq
, sq
->cc
, sq
->pc
, 1)) {
1329 struct mlx5e_tx_wqe
*nop
;
1331 sq
->db
.wqe_info
[(sq
->pc
& sq
->wq
.sz_m1
)].skb
= NULL
;
1332 nop
= mlx5e_post_nop(&sq
->wq
, sq
->sqn
, &sq
->pc
);
1333 mlx5e_notify_hw(&sq
->wq
, sq
->pc
, sq
->uar_map
, &nop
->ctrl
);
1337 static void mlx5e_close_txqsq(struct mlx5e_txqsq
*sq
)
1339 struct mlx5e_channel
*c
= sq
->channel
;
1340 struct mlx5_core_dev
*mdev
= c
->mdev
;
1342 mlx5e_destroy_sq(mdev
, sq
->sqn
);
1344 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
1345 mlx5e_free_txqsq_descs(sq
);
1346 mlx5e_free_txqsq(sq
);
1349 static int mlx5e_open_icosq(struct mlx5e_channel
*c
,
1350 struct mlx5e_params
*params
,
1351 struct mlx5e_sq_param
*param
,
1352 struct mlx5e_icosq
*sq
)
1354 struct mlx5e_create_sq_param csp
= {};
1357 err
= mlx5e_alloc_icosq(c
, param
, sq
);
1361 csp
.cqn
= sq
->cq
.mcq
.cqn
;
1362 csp
.wq_ctrl
= &sq
->wq_ctrl
;
1363 csp
.min_inline_mode
= params
->tx_min_inline_mode
;
1364 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1365 err
= mlx5e_create_sq_rdy(c
->mdev
, param
, &csp
, &sq
->sqn
);
1367 goto err_free_icosq
;
1372 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1373 mlx5e_free_icosq(sq
);
1378 static void mlx5e_close_icosq(struct mlx5e_icosq
*sq
)
1380 struct mlx5e_channel
*c
= sq
->channel
;
1382 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1383 napi_synchronize(&c
->napi
);
1385 mlx5e_destroy_sq(c
->mdev
, sq
->sqn
);
1386 mlx5e_free_icosq(sq
);
1389 static int mlx5e_open_xdpsq(struct mlx5e_channel
*c
,
1390 struct mlx5e_params
*params
,
1391 struct mlx5e_sq_param
*param
,
1392 struct mlx5e_xdpsq
*sq
)
1394 unsigned int ds_cnt
= MLX5E_XDP_TX_DS_COUNT
;
1395 struct mlx5e_create_sq_param csp
= {};
1396 unsigned int inline_hdr_sz
= 0;
1400 err
= mlx5e_alloc_xdpsq(c
, params
, param
, sq
);
1405 csp
.tisn
= c
->priv
->tisn
[0]; /* tc = 0 */
1406 csp
.cqn
= sq
->cq
.mcq
.cqn
;
1407 csp
.wq_ctrl
= &sq
->wq_ctrl
;
1408 csp
.min_inline_mode
= sq
->min_inline_mode
;
1409 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1410 err
= mlx5e_create_sq_rdy(c
->mdev
, param
, &csp
, &sq
->sqn
);
1412 goto err_free_xdpsq
;
1414 if (sq
->min_inline_mode
!= MLX5_INLINE_MODE_NONE
) {
1415 inline_hdr_sz
= MLX5E_XDP_MIN_INLINE
;
1419 /* Pre initialize fixed WQE fields */
1420 for (i
= 0; i
< mlx5_wq_cyc_get_size(&sq
->wq
); i
++) {
1421 struct mlx5e_tx_wqe
*wqe
= mlx5_wq_cyc_get_wqe(&sq
->wq
, i
);
1422 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
1423 struct mlx5_wqe_eth_seg
*eseg
= &wqe
->eth
;
1424 struct mlx5_wqe_data_seg
*dseg
;
1426 cseg
->qpn_ds
= cpu_to_be32((sq
->sqn
<< 8) | ds_cnt
);
1427 eseg
->inline_hdr
.sz
= cpu_to_be16(inline_hdr_sz
);
1429 dseg
= (struct mlx5_wqe_data_seg
*)cseg
+ (ds_cnt
- 1);
1430 dseg
->lkey
= sq
->mkey_be
;
1436 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1437 mlx5e_free_xdpsq(sq
);
1442 static void mlx5e_close_xdpsq(struct mlx5e_xdpsq
*sq
)
1444 struct mlx5e_channel
*c
= sq
->channel
;
1446 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1447 napi_synchronize(&c
->napi
);
1449 mlx5e_destroy_sq(c
->mdev
, sq
->sqn
);
1450 mlx5e_free_xdpsq_descs(sq
);
1451 mlx5e_free_xdpsq(sq
);
1454 static int mlx5e_alloc_cq_common(struct mlx5_core_dev
*mdev
,
1455 struct mlx5e_cq_param
*param
,
1456 struct mlx5e_cq
*cq
)
1458 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1464 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
1469 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
1472 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
1473 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
1474 *mcq
->set_ci_db
= 0;
1476 mcq
->vector
= param
->eq_ix
;
1477 mcq
->comp
= mlx5e_completion_event
;
1478 mcq
->event
= mlx5e_cq_error_event
;
1481 for (i
= 0; i
< mlx5_cqwq_get_size(&cq
->wq
); i
++) {
1482 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, i
);
1492 static int mlx5e_alloc_cq(struct mlx5e_channel
*c
,
1493 struct mlx5e_cq_param
*param
,
1494 struct mlx5e_cq
*cq
)
1496 struct mlx5_core_dev
*mdev
= c
->priv
->mdev
;
1499 param
->wq
.buf_numa_node
= cpu_to_node(c
->cpu
);
1500 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
1501 param
->eq_ix
= c
->ix
;
1503 err
= mlx5e_alloc_cq_common(mdev
, param
, cq
);
1505 cq
->napi
= &c
->napi
;
1511 static void mlx5e_free_cq(struct mlx5e_cq
*cq
)
1513 mlx5_cqwq_destroy(&cq
->wq_ctrl
);
1516 static int mlx5e_create_cq(struct mlx5e_cq
*cq
, struct mlx5e_cq_param
*param
)
1518 struct mlx5_core_dev
*mdev
= cq
->mdev
;
1519 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1524 unsigned int irqn_not_used
;
1528 inlen
= MLX5_ST_SZ_BYTES(create_cq_in
) +
1529 sizeof(u64
) * cq
->wq_ctrl
.frag_buf
.npages
;
1530 in
= kvzalloc(inlen
, GFP_KERNEL
);
1534 cqc
= MLX5_ADDR_OF(create_cq_in
, in
, cq_context
);
1536 memcpy(cqc
, param
->cqc
, sizeof(param
->cqc
));
1538 mlx5_fill_page_frag_array(&cq
->wq_ctrl
.frag_buf
,
1539 (__be64
*)MLX5_ADDR_OF(create_cq_in
, in
, pas
));
1541 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn
, &irqn_not_used
);
1543 MLX5_SET(cqc
, cqc
, cq_period_mode
, param
->cq_period_mode
);
1544 MLX5_SET(cqc
, cqc
, c_eqn
, eqn
);
1545 MLX5_SET(cqc
, cqc
, uar_page
, mdev
->priv
.uar
->index
);
1546 MLX5_SET(cqc
, cqc
, log_page_size
, cq
->wq_ctrl
.frag_buf
.page_shift
-
1547 MLX5_ADAPTER_PAGE_SHIFT
);
1548 MLX5_SET64(cqc
, cqc
, dbr_addr
, cq
->wq_ctrl
.db
.dma
);
1550 err
= mlx5_core_create_cq(mdev
, mcq
, in
, inlen
);
1562 static void mlx5e_destroy_cq(struct mlx5e_cq
*cq
)
1564 mlx5_core_destroy_cq(cq
->mdev
, &cq
->mcq
);
1567 static int mlx5e_open_cq(struct mlx5e_channel
*c
,
1568 struct mlx5e_cq_moder moder
,
1569 struct mlx5e_cq_param
*param
,
1570 struct mlx5e_cq
*cq
)
1572 struct mlx5_core_dev
*mdev
= c
->mdev
;
1575 err
= mlx5e_alloc_cq(c
, param
, cq
);
1579 err
= mlx5e_create_cq(cq
, param
);
1583 if (MLX5_CAP_GEN(mdev
, cq_moderation
))
1584 mlx5_core_modify_cq_moderation(mdev
, &cq
->mcq
, moder
.usec
, moder
.pkts
);
1593 static void mlx5e_close_cq(struct mlx5e_cq
*cq
)
1595 mlx5e_destroy_cq(cq
);
1599 static int mlx5e_get_cpu(struct mlx5e_priv
*priv
, int ix
)
1601 return cpumask_first(priv
->mdev
->priv
.irq_info
[ix
].mask
);
1604 static int mlx5e_open_tx_cqs(struct mlx5e_channel
*c
,
1605 struct mlx5e_params
*params
,
1606 struct mlx5e_channel_param
*cparam
)
1611 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
1612 err
= mlx5e_open_cq(c
, params
->tx_cq_moderation
,
1613 &cparam
->tx_cq
, &c
->sq
[tc
].cq
);
1615 goto err_close_tx_cqs
;
1621 for (tc
--; tc
>= 0; tc
--)
1622 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1627 static void mlx5e_close_tx_cqs(struct mlx5e_channel
*c
)
1631 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1632 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1635 static int mlx5e_open_sqs(struct mlx5e_channel
*c
,
1636 struct mlx5e_params
*params
,
1637 struct mlx5e_channel_param
*cparam
)
1642 for (tc
= 0; tc
< params
->num_tc
; tc
++) {
1643 int txq_ix
= c
->ix
+ tc
* params
->num_channels
;
1645 err
= mlx5e_open_txqsq(c
, c
->priv
->tisn
[tc
], txq_ix
,
1646 params
, &cparam
->sq
, &c
->sq
[tc
]);
1654 for (tc
--; tc
>= 0; tc
--)
1655 mlx5e_close_txqsq(&c
->sq
[tc
]);
1660 static void mlx5e_close_sqs(struct mlx5e_channel
*c
)
1664 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1665 mlx5e_close_txqsq(&c
->sq
[tc
]);
1668 static int mlx5e_set_sq_maxrate(struct net_device
*dev
,
1669 struct mlx5e_txqsq
*sq
, u32 rate
)
1671 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1672 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1673 struct mlx5e_modify_sq_param msp
= {0};
1677 if (rate
== sq
->rate_limit
)
1682 /* remove current rl index to free space to next ones */
1683 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
1688 err
= mlx5_rl_add_rate(mdev
, rate
, &rl_index
);
1690 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1696 msp
.curr_state
= MLX5_SQC_STATE_RDY
;
1697 msp
.next_state
= MLX5_SQC_STATE_RDY
;
1698 msp
.rl_index
= rl_index
;
1699 msp
.rl_update
= true;
1700 err
= mlx5e_modify_sq(mdev
, sq
->sqn
, &msp
);
1702 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1704 /* remove the rate from the table */
1706 mlx5_rl_remove_rate(mdev
, rate
);
1710 sq
->rate_limit
= rate
;
1714 static int mlx5e_set_tx_maxrate(struct net_device
*dev
, int index
, u32 rate
)
1716 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1717 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1718 struct mlx5e_txqsq
*sq
= priv
->txq2sq
[index
];
1721 if (!mlx5_rl_is_supported(mdev
)) {
1722 netdev_err(dev
, "Rate limiting is not supported on this device\n");
1726 /* rate is given in Mb/sec, HW config is in Kb/sec */
1729 /* Check whether rate in valid range, 0 is always valid */
1730 if (rate
&& !mlx5_rl_is_in_range(mdev
, rate
)) {
1731 netdev_err(dev
, "TX rate %u, is not in range\n", rate
);
1735 mutex_lock(&priv
->state_lock
);
1736 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
1737 err
= mlx5e_set_sq_maxrate(dev
, sq
, rate
);
1739 priv
->tx_rates
[index
] = rate
;
1740 mutex_unlock(&priv
->state_lock
);
1745 static int mlx5e_open_channel(struct mlx5e_priv
*priv
, int ix
,
1746 struct mlx5e_params
*params
,
1747 struct mlx5e_channel_param
*cparam
,
1748 struct mlx5e_channel
**cp
)
1750 struct mlx5e_cq_moder icocq_moder
= {0, 0};
1751 struct net_device
*netdev
= priv
->netdev
;
1752 int cpu
= mlx5e_get_cpu(priv
, ix
);
1753 struct mlx5e_channel
*c
;
1758 c
= kzalloc_node(sizeof(*c
), GFP_KERNEL
, cpu_to_node(cpu
));
1763 c
->mdev
= priv
->mdev
;
1764 c
->tstamp
= &priv
->tstamp
;
1767 c
->pdev
= &priv
->mdev
->pdev
->dev
;
1768 c
->netdev
= priv
->netdev
;
1769 c
->mkey_be
= cpu_to_be32(priv
->mdev
->mlx5e_res
.mkey
.key
);
1770 c
->num_tc
= params
->num_tc
;
1771 c
->xdp
= !!params
->xdp_prog
;
1773 mlx5_vector2eqn(priv
->mdev
, ix
, &eqn
, &irq
);
1774 c
->irq_desc
= irq_to_desc(irq
);
1776 netif_napi_add(netdev
, &c
->napi
, mlx5e_napi_poll
, 64);
1778 err
= mlx5e_open_cq(c
, icocq_moder
, &cparam
->icosq_cq
, &c
->icosq
.cq
);
1782 err
= mlx5e_open_tx_cqs(c
, params
, cparam
);
1784 goto err_close_icosq_cq
;
1786 err
= mlx5e_open_cq(c
, params
->rx_cq_moderation
, &cparam
->rx_cq
, &c
->rq
.cq
);
1788 goto err_close_tx_cqs
;
1790 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1791 err
= c
->xdp
? mlx5e_open_cq(c
, params
->tx_cq_moderation
,
1792 &cparam
->tx_cq
, &c
->rq
.xdpsq
.cq
) : 0;
1794 goto err_close_rx_cq
;
1796 napi_enable(&c
->napi
);
1798 err
= mlx5e_open_icosq(c
, params
, &cparam
->icosq
, &c
->icosq
);
1800 goto err_disable_napi
;
1802 err
= mlx5e_open_sqs(c
, params
, cparam
);
1804 goto err_close_icosq
;
1806 err
= c
->xdp
? mlx5e_open_xdpsq(c
, params
, &cparam
->xdp_sq
, &c
->rq
.xdpsq
) : 0;
1810 err
= mlx5e_open_rq(c
, params
, &cparam
->rq
, &c
->rq
);
1812 goto err_close_xdp_sq
;
1819 mlx5e_close_xdpsq(&c
->rq
.xdpsq
);
1825 mlx5e_close_icosq(&c
->icosq
);
1828 napi_disable(&c
->napi
);
1830 mlx5e_close_cq(&c
->rq
.xdpsq
.cq
);
1833 mlx5e_close_cq(&c
->rq
.cq
);
1836 mlx5e_close_tx_cqs(c
);
1839 mlx5e_close_cq(&c
->icosq
.cq
);
1842 netif_napi_del(&c
->napi
);
1848 static void mlx5e_activate_channel(struct mlx5e_channel
*c
)
1852 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1853 mlx5e_activate_txqsq(&c
->sq
[tc
]);
1854 mlx5e_activate_rq(&c
->rq
);
1855 netif_set_xps_queue(c
->netdev
, get_cpu_mask(c
->cpu
), c
->ix
);
1858 static void mlx5e_deactivate_channel(struct mlx5e_channel
*c
)
1862 mlx5e_deactivate_rq(&c
->rq
);
1863 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1864 mlx5e_deactivate_txqsq(&c
->sq
[tc
]);
1867 static void mlx5e_close_channel(struct mlx5e_channel
*c
)
1869 mlx5e_close_rq(&c
->rq
);
1871 mlx5e_close_xdpsq(&c
->rq
.xdpsq
);
1873 mlx5e_close_icosq(&c
->icosq
);
1874 napi_disable(&c
->napi
);
1876 mlx5e_close_cq(&c
->rq
.xdpsq
.cq
);
1877 mlx5e_close_cq(&c
->rq
.cq
);
1878 mlx5e_close_tx_cqs(c
);
1879 mlx5e_close_cq(&c
->icosq
.cq
);
1880 netif_napi_del(&c
->napi
);
1885 static void mlx5e_build_rq_param(struct mlx5e_priv
*priv
,
1886 struct mlx5e_params
*params
,
1887 struct mlx5e_rq_param
*param
)
1889 void *rqc
= param
->rqc
;
1890 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1892 switch (params
->rq_wq_type
) {
1893 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1894 MLX5_SET(wq
, wq
, log_wqe_num_of_strides
, params
->mpwqe_log_num_strides
- 9);
1895 MLX5_SET(wq
, wq
, log_wqe_stride_size
, params
->mpwqe_log_stride_sz
- 6);
1896 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
1898 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1899 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1902 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
1903 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1904 MLX5_SET(wq
, wq
, log_wq_sz
, params
->log_rq_size
);
1905 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1906 MLX5_SET(rqc
, rqc
, counter_set_id
, priv
->q_counter
);
1907 MLX5_SET(rqc
, rqc
, vsd
, params
->vlan_strip_disable
);
1908 MLX5_SET(rqc
, rqc
, scatter_fcs
, params
->scatter_fcs_en
);
1910 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1911 param
->wq
.linear
= 1;
1914 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param
*param
)
1916 void *rqc
= param
->rqc
;
1917 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1919 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1920 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1923 static void mlx5e_build_sq_param_common(struct mlx5e_priv
*priv
,
1924 struct mlx5e_sq_param
*param
)
1926 void *sqc
= param
->sqc
;
1927 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1929 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1930 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1932 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1935 static void mlx5e_build_sq_param(struct mlx5e_priv
*priv
,
1936 struct mlx5e_params
*params
,
1937 struct mlx5e_sq_param
*param
)
1939 void *sqc
= param
->sqc
;
1940 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1942 mlx5e_build_sq_param_common(priv
, param
);
1943 MLX5_SET(wq
, wq
, log_wq_sz
, params
->log_sq_size
);
1944 MLX5_SET(sqc
, sqc
, allow_swp
, !!MLX5_IPSEC_DEV(priv
->mdev
));
1947 static void mlx5e_build_common_cq_param(struct mlx5e_priv
*priv
,
1948 struct mlx5e_cq_param
*param
)
1950 void *cqc
= param
->cqc
;
1952 MLX5_SET(cqc
, cqc
, uar_page
, priv
->mdev
->priv
.uar
->index
);
1955 static void mlx5e_build_rx_cq_param(struct mlx5e_priv
*priv
,
1956 struct mlx5e_params
*params
,
1957 struct mlx5e_cq_param
*param
)
1959 void *cqc
= param
->cqc
;
1962 switch (params
->rq_wq_type
) {
1963 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1964 log_cq_size
= params
->log_rq_size
+ params
->mpwqe_log_num_strides
;
1966 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1967 log_cq_size
= params
->log_rq_size
;
1970 MLX5_SET(cqc
, cqc
, log_cq_size
, log_cq_size
);
1971 if (MLX5E_GET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
)) {
1972 MLX5_SET(cqc
, cqc
, mini_cqe_res_format
, MLX5_CQE_FORMAT_CSUM
);
1973 MLX5_SET(cqc
, cqc
, cqe_comp_en
, 1);
1976 mlx5e_build_common_cq_param(priv
, param
);
1977 param
->cq_period_mode
= params
->rx_cq_moderation
.cq_period_mode
;
1980 static void mlx5e_build_tx_cq_param(struct mlx5e_priv
*priv
,
1981 struct mlx5e_params
*params
,
1982 struct mlx5e_cq_param
*param
)
1984 void *cqc
= param
->cqc
;
1986 MLX5_SET(cqc
, cqc
, log_cq_size
, params
->log_sq_size
);
1988 mlx5e_build_common_cq_param(priv
, param
);
1989 param
->cq_period_mode
= params
->tx_cq_moderation
.cq_period_mode
;
1992 static void mlx5e_build_ico_cq_param(struct mlx5e_priv
*priv
,
1994 struct mlx5e_cq_param
*param
)
1996 void *cqc
= param
->cqc
;
1998 MLX5_SET(cqc
, cqc
, log_cq_size
, log_wq_size
);
2000 mlx5e_build_common_cq_param(priv
, param
);
2002 param
->cq_period_mode
= MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
2005 static void mlx5e_build_icosq_param(struct mlx5e_priv
*priv
,
2007 struct mlx5e_sq_param
*param
)
2009 void *sqc
= param
->sqc
;
2010 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
2012 mlx5e_build_sq_param_common(priv
, param
);
2014 MLX5_SET(wq
, wq
, log_wq_sz
, log_wq_size
);
2015 MLX5_SET(sqc
, sqc
, reg_umr
, MLX5_CAP_ETH(priv
->mdev
, reg_umr_sq
));
2018 static void mlx5e_build_xdpsq_param(struct mlx5e_priv
*priv
,
2019 struct mlx5e_params
*params
,
2020 struct mlx5e_sq_param
*param
)
2022 void *sqc
= param
->sqc
;
2023 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
2025 mlx5e_build_sq_param_common(priv
, param
);
2026 MLX5_SET(wq
, wq
, log_wq_sz
, params
->log_sq_size
);
2029 static void mlx5e_build_channel_param(struct mlx5e_priv
*priv
,
2030 struct mlx5e_params
*params
,
2031 struct mlx5e_channel_param
*cparam
)
2033 u8 icosq_log_wq_sz
= MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
;
2035 mlx5e_build_rq_param(priv
, params
, &cparam
->rq
);
2036 mlx5e_build_sq_param(priv
, params
, &cparam
->sq
);
2037 mlx5e_build_xdpsq_param(priv
, params
, &cparam
->xdp_sq
);
2038 mlx5e_build_icosq_param(priv
, icosq_log_wq_sz
, &cparam
->icosq
);
2039 mlx5e_build_rx_cq_param(priv
, params
, &cparam
->rx_cq
);
2040 mlx5e_build_tx_cq_param(priv
, params
, &cparam
->tx_cq
);
2041 mlx5e_build_ico_cq_param(priv
, icosq_log_wq_sz
, &cparam
->icosq_cq
);
2044 int mlx5e_open_channels(struct mlx5e_priv
*priv
,
2045 struct mlx5e_channels
*chs
)
2047 struct mlx5e_channel_param
*cparam
;
2051 chs
->num
= chs
->params
.num_channels
;
2053 chs
->c
= kcalloc(chs
->num
, sizeof(struct mlx5e_channel
*), GFP_KERNEL
);
2054 cparam
= kzalloc(sizeof(struct mlx5e_channel_param
), GFP_KERNEL
);
2055 if (!chs
->c
|| !cparam
)
2058 mlx5e_build_channel_param(priv
, &chs
->params
, cparam
);
2059 for (i
= 0; i
< chs
->num
; i
++) {
2060 err
= mlx5e_open_channel(priv
, i
, &chs
->params
, cparam
, &chs
->c
[i
]);
2062 goto err_close_channels
;
2069 for (i
--; i
>= 0; i
--)
2070 mlx5e_close_channel(chs
->c
[i
]);
2079 static void mlx5e_activate_channels(struct mlx5e_channels
*chs
)
2083 for (i
= 0; i
< chs
->num
; i
++)
2084 mlx5e_activate_channel(chs
->c
[i
]);
2087 static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels
*chs
)
2092 for (i
= 0; i
< chs
->num
; i
++) {
2093 err
= mlx5e_wait_for_min_rx_wqes(&chs
->c
[i
]->rq
);
2101 static void mlx5e_deactivate_channels(struct mlx5e_channels
*chs
)
2105 for (i
= 0; i
< chs
->num
; i
++)
2106 mlx5e_deactivate_channel(chs
->c
[i
]);
2109 void mlx5e_close_channels(struct mlx5e_channels
*chs
)
2113 for (i
= 0; i
< chs
->num
; i
++)
2114 mlx5e_close_channel(chs
->c
[i
]);
2121 mlx5e_create_rqt(struct mlx5e_priv
*priv
, int sz
, struct mlx5e_rqt
*rqt
)
2123 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2130 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
2131 in
= kvzalloc(inlen
, GFP_KERNEL
);
2135 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
2137 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
2138 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
2140 for (i
= 0; i
< sz
; i
++)
2141 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], priv
->drop_rq
.rqn
);
2143 err
= mlx5_core_create_rqt(mdev
, in
, inlen
, &rqt
->rqtn
);
2145 rqt
->enabled
= true;
2151 void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, struct mlx5e_rqt
*rqt
)
2153 rqt
->enabled
= false;
2154 mlx5_core_destroy_rqt(priv
->mdev
, rqt
->rqtn
);
2157 int mlx5e_create_indirect_rqt(struct mlx5e_priv
*priv
)
2159 struct mlx5e_rqt
*rqt
= &priv
->indir_rqt
;
2162 err
= mlx5e_create_rqt(priv
, MLX5E_INDIR_RQT_SIZE
, rqt
);
2164 mlx5_core_warn(priv
->mdev
, "create indirect rqts failed, %d\n", err
);
2168 int mlx5e_create_direct_rqts(struct mlx5e_priv
*priv
)
2170 struct mlx5e_rqt
*rqt
;
2174 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2175 rqt
= &priv
->direct_tir
[ix
].rqt
;
2176 err
= mlx5e_create_rqt(priv
, 1 /*size */, rqt
);
2178 goto err_destroy_rqts
;
2184 mlx5_core_warn(priv
->mdev
, "create direct rqts failed, %d\n", err
);
2185 for (ix
--; ix
>= 0; ix
--)
2186 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[ix
].rqt
);
2191 void mlx5e_destroy_direct_rqts(struct mlx5e_priv
*priv
)
2195 for (i
= 0; i
< priv
->profile
->max_nch(priv
->mdev
); i
++)
2196 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[i
].rqt
);
2199 static int mlx5e_rx_hash_fn(int hfunc
)
2201 return (hfunc
== ETH_RSS_HASH_TOP
) ?
2202 MLX5_RX_HASH_FN_TOEPLITZ
:
2203 MLX5_RX_HASH_FN_INVERTED_XOR8
;
2206 static int mlx5e_bits_invert(unsigned long a
, int size
)
2211 for (i
= 0; i
< size
; i
++)
2212 inv
|= (test_bit(size
- i
- 1, &a
) ? 1 : 0) << i
;
2217 static void mlx5e_fill_rqt_rqns(struct mlx5e_priv
*priv
, int sz
,
2218 struct mlx5e_redirect_rqt_param rrp
, void *rqtc
)
2222 for (i
= 0; i
< sz
; i
++) {
2228 if (rrp
.rss
.hfunc
== ETH_RSS_HASH_XOR
)
2229 ix
= mlx5e_bits_invert(i
, ilog2(sz
));
2231 ix
= priv
->channels
.params
.indirection_rqt
[ix
];
2232 rqn
= rrp
.rss
.channels
->c
[ix
]->rq
.rqn
;
2236 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], rqn
);
2240 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
,
2241 struct mlx5e_redirect_rqt_param rrp
)
2243 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2249 inlen
= MLX5_ST_SZ_BYTES(modify_rqt_in
) + sizeof(u32
) * sz
;
2250 in
= kvzalloc(inlen
, GFP_KERNEL
);
2254 rqtc
= MLX5_ADDR_OF(modify_rqt_in
, in
, ctx
);
2256 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
2257 MLX5_SET(modify_rqt_in
, in
, bitmask
.rqn_list
, 1);
2258 mlx5e_fill_rqt_rqns(priv
, sz
, rrp
, rqtc
);
2259 err
= mlx5_core_modify_rqt(mdev
, rqtn
, in
, inlen
);
2265 static u32
mlx5e_get_direct_rqn(struct mlx5e_priv
*priv
, int ix
,
2266 struct mlx5e_redirect_rqt_param rrp
)
2271 if (ix
>= rrp
.rss
.channels
->num
)
2272 return priv
->drop_rq
.rqn
;
2274 return rrp
.rss
.channels
->c
[ix
]->rq
.rqn
;
2277 static void mlx5e_redirect_rqts(struct mlx5e_priv
*priv
,
2278 struct mlx5e_redirect_rqt_param rrp
)
2283 if (priv
->indir_rqt
.enabled
) {
2285 rqtn
= priv
->indir_rqt
.rqtn
;
2286 mlx5e_redirect_rqt(priv
, rqtn
, MLX5E_INDIR_RQT_SIZE
, rrp
);
2289 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2290 struct mlx5e_redirect_rqt_param direct_rrp
= {
2293 .rqn
= mlx5e_get_direct_rqn(priv
, ix
, rrp
)
2297 /* Direct RQ Tables */
2298 if (!priv
->direct_tir
[ix
].rqt
.enabled
)
2301 rqtn
= priv
->direct_tir
[ix
].rqt
.rqtn
;
2302 mlx5e_redirect_rqt(priv
, rqtn
, 1, direct_rrp
);
2306 static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv
*priv
,
2307 struct mlx5e_channels
*chs
)
2309 struct mlx5e_redirect_rqt_param rrp
= {
2314 .hfunc
= chs
->params
.rss_hfunc
,
2319 mlx5e_redirect_rqts(priv
, rrp
);
2322 static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv
*priv
)
2324 struct mlx5e_redirect_rqt_param drop_rrp
= {
2327 .rqn
= priv
->drop_rq
.rqn
,
2331 mlx5e_redirect_rqts(priv
, drop_rrp
);
2334 static void mlx5e_build_tir_ctx_lro(struct mlx5e_params
*params
, void *tirc
)
2336 if (!params
->lro_en
)
2339 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2341 MLX5_SET(tirc
, tirc
, lro_enable_mask
,
2342 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
|
2343 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
);
2344 MLX5_SET(tirc
, tirc
, lro_max_ip_payload_size
,
2345 (params
->lro_wqe_sz
- ROUGH_MAX_L2_L3_HDR_SZ
) >> 8);
2346 MLX5_SET(tirc
, tirc
, lro_timeout_period_usecs
, params
->lro_timeout
);
2349 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params
*params
,
2350 enum mlx5e_traffic_types tt
,
2351 void *tirc
, bool inner
)
2353 void *hfso
= inner
? MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_inner
) :
2354 MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
2356 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2357 MLX5_HASH_FIELD_SEL_DST_IP)
2359 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2360 MLX5_HASH_FIELD_SEL_DST_IP |\
2361 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2362 MLX5_HASH_FIELD_SEL_L4_DPORT)
2364 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2365 MLX5_HASH_FIELD_SEL_DST_IP |\
2366 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2368 MLX5_SET(tirc
, tirc
, rx_hash_fn
, mlx5e_rx_hash_fn(params
->rss_hfunc
));
2369 if (params
->rss_hfunc
== ETH_RSS_HASH_TOP
) {
2370 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
,
2371 rx_hash_toeplitz_key
);
2372 size_t len
= MLX5_FLD_SZ_BYTES(tirc
,
2373 rx_hash_toeplitz_key
);
2375 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
2376 memcpy(rss_key
, params
->toeplitz_hash_key
, len
);
2380 case MLX5E_TT_IPV4_TCP
:
2381 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2382 MLX5_L3_PROT_TYPE_IPV4
);
2383 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2384 MLX5_L4_PROT_TYPE_TCP
);
2385 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2386 MLX5_HASH_IP_L4PORTS
);
2389 case MLX5E_TT_IPV6_TCP
:
2390 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2391 MLX5_L3_PROT_TYPE_IPV6
);
2392 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2393 MLX5_L4_PROT_TYPE_TCP
);
2394 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2395 MLX5_HASH_IP_L4PORTS
);
2398 case MLX5E_TT_IPV4_UDP
:
2399 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2400 MLX5_L3_PROT_TYPE_IPV4
);
2401 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2402 MLX5_L4_PROT_TYPE_UDP
);
2403 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2404 MLX5_HASH_IP_L4PORTS
);
2407 case MLX5E_TT_IPV6_UDP
:
2408 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2409 MLX5_L3_PROT_TYPE_IPV6
);
2410 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2411 MLX5_L4_PROT_TYPE_UDP
);
2412 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2413 MLX5_HASH_IP_L4PORTS
);
2416 case MLX5E_TT_IPV4_IPSEC_AH
:
2417 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2418 MLX5_L3_PROT_TYPE_IPV4
);
2419 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2420 MLX5_HASH_IP_IPSEC_SPI
);
2423 case MLX5E_TT_IPV6_IPSEC_AH
:
2424 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2425 MLX5_L3_PROT_TYPE_IPV6
);
2426 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2427 MLX5_HASH_IP_IPSEC_SPI
);
2430 case MLX5E_TT_IPV4_IPSEC_ESP
:
2431 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2432 MLX5_L3_PROT_TYPE_IPV4
);
2433 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2434 MLX5_HASH_IP_IPSEC_SPI
);
2437 case MLX5E_TT_IPV6_IPSEC_ESP
:
2438 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2439 MLX5_L3_PROT_TYPE_IPV6
);
2440 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2441 MLX5_HASH_IP_IPSEC_SPI
);
2445 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2446 MLX5_L3_PROT_TYPE_IPV4
);
2447 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2452 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2453 MLX5_L3_PROT_TYPE_IPV6
);
2454 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2458 WARN_ONCE(true, "%s: bad traffic type!\n", __func__
);
2462 static int mlx5e_modify_tirs_lro(struct mlx5e_priv
*priv
)
2464 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2473 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
2474 in
= kvzalloc(inlen
, GFP_KERNEL
);
2478 MLX5_SET(modify_tir_in
, in
, bitmask
.lro
, 1);
2479 tirc
= MLX5_ADDR_OF(modify_tir_in
, in
, ctx
);
2481 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2483 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
2484 err
= mlx5_core_modify_tir(mdev
, priv
->indir_tir
[tt
].tirn
, in
,
2490 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2491 err
= mlx5_core_modify_tir(mdev
, priv
->direct_tir
[ix
].tirn
,
2503 static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv
*priv
,
2504 enum mlx5e_traffic_types tt
,
2507 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2509 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2511 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2512 MLX5_SET(tirc
, tirc
, indirect_table
, priv
->indir_rqt
.rqtn
);
2513 MLX5_SET(tirc
, tirc
, tunneled_offload_en
, 0x1);
2515 mlx5e_build_indir_tir_ctx_hash(&priv
->channels
.params
, tt
, tirc
, true);
2518 static int mlx5e_set_mtu(struct mlx5e_priv
*priv
, u16 mtu
)
2520 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2521 u16 hw_mtu
= MLX5E_SW2HW_MTU(priv
, mtu
);
2524 err
= mlx5_set_port_mtu(mdev
, hw_mtu
, 1);
2528 /* Update vport context MTU */
2529 mlx5_modify_nic_vport_mtu(mdev
, hw_mtu
);
2533 static void mlx5e_query_mtu(struct mlx5e_priv
*priv
, u16
*mtu
)
2535 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2539 err
= mlx5_query_nic_vport_mtu(mdev
, &hw_mtu
);
2540 if (err
|| !hw_mtu
) /* fallback to port oper mtu */
2541 mlx5_query_port_oper_mtu(mdev
, &hw_mtu
, 1);
2543 *mtu
= MLX5E_HW2SW_MTU(priv
, hw_mtu
);
2546 static int mlx5e_set_dev_port_mtu(struct mlx5e_priv
*priv
)
2548 struct net_device
*netdev
= priv
->netdev
;
2552 err
= mlx5e_set_mtu(priv
, netdev
->mtu
);
2556 mlx5e_query_mtu(priv
, &mtu
);
2557 if (mtu
!= netdev
->mtu
)
2558 netdev_warn(netdev
, "%s: VPort MTU %d is different than netdev mtu %d\n",
2559 __func__
, mtu
, netdev
->mtu
);
2565 static void mlx5e_netdev_set_tcs(struct net_device
*netdev
)
2567 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2568 int nch
= priv
->channels
.params
.num_channels
;
2569 int ntc
= priv
->channels
.params
.num_tc
;
2572 netdev_reset_tc(netdev
);
2577 netdev_set_num_tc(netdev
, ntc
);
2579 /* Map netdev TCs to offset 0
2580 * We have our own UP to TXQ mapping for QoS
2582 for (tc
= 0; tc
< ntc
; tc
++)
2583 netdev_set_tc_queue(netdev
, tc
, nch
, 0);
2586 static void mlx5e_build_channels_tx_maps(struct mlx5e_priv
*priv
)
2588 struct mlx5e_channel
*c
;
2589 struct mlx5e_txqsq
*sq
;
2592 for (i
= 0; i
< priv
->channels
.num
; i
++)
2593 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++)
2594 priv
->channel_tc2txq
[i
][tc
] = i
+ tc
* priv
->channels
.num
;
2596 for (i
= 0; i
< priv
->channels
.num
; i
++) {
2597 c
= priv
->channels
.c
[i
];
2598 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
2600 priv
->txq2sq
[sq
->txq_ix
] = sq
;
2605 void mlx5e_activate_priv_channels(struct mlx5e_priv
*priv
)
2607 int num_txqs
= priv
->channels
.num
* priv
->channels
.params
.num_tc
;
2608 struct net_device
*netdev
= priv
->netdev
;
2610 mlx5e_netdev_set_tcs(netdev
);
2611 netif_set_real_num_tx_queues(netdev
, num_txqs
);
2612 netif_set_real_num_rx_queues(netdev
, priv
->channels
.num
);
2614 mlx5e_build_channels_tx_maps(priv
);
2615 mlx5e_activate_channels(&priv
->channels
);
2616 netif_tx_start_all_queues(priv
->netdev
);
2618 if (MLX5_VPORT_MANAGER(priv
->mdev
))
2619 mlx5e_add_sqs_fwd_rules(priv
);
2621 mlx5e_wait_channels_min_rx_wqes(&priv
->channels
);
2622 mlx5e_redirect_rqts_to_channels(priv
, &priv
->channels
);
2625 void mlx5e_deactivate_priv_channels(struct mlx5e_priv
*priv
)
2627 mlx5e_redirect_rqts_to_drop(priv
);
2629 if (MLX5_VPORT_MANAGER(priv
->mdev
))
2630 mlx5e_remove_sqs_fwd_rules(priv
);
2632 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
2633 * polling for inactive tx queues.
2635 netif_tx_stop_all_queues(priv
->netdev
);
2636 netif_tx_disable(priv
->netdev
);
2637 mlx5e_deactivate_channels(&priv
->channels
);
2640 void mlx5e_switch_priv_channels(struct mlx5e_priv
*priv
,
2641 struct mlx5e_channels
*new_chs
,
2642 mlx5e_fp_hw_modify hw_modify
)
2644 struct net_device
*netdev
= priv
->netdev
;
2647 new_num_txqs
= new_chs
->num
* new_chs
->params
.num_tc
;
2649 carrier_ok
= netif_carrier_ok(netdev
);
2650 netif_carrier_off(netdev
);
2652 if (new_num_txqs
< netdev
->real_num_tx_queues
)
2653 netif_set_real_num_tx_queues(netdev
, new_num_txqs
);
2655 mlx5e_deactivate_priv_channels(priv
);
2656 mlx5e_close_channels(&priv
->channels
);
2658 priv
->channels
= *new_chs
;
2660 /* New channels are ready to roll, modify HW settings if needed */
2664 mlx5e_refresh_tirs(priv
, false);
2665 mlx5e_activate_priv_channels(priv
);
2667 /* return carrier back if needed */
2669 netif_carrier_on(netdev
);
2672 void mlx5e_timestamp_set(struct mlx5e_priv
*priv
)
2674 priv
->tstamp
.tx_type
= HWTSTAMP_TX_OFF
;
2675 priv
->tstamp
.rx_filter
= HWTSTAMP_FILTER_NONE
;
2678 int mlx5e_open_locked(struct net_device
*netdev
)
2680 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2683 set_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2685 err
= mlx5e_open_channels(priv
, &priv
->channels
);
2687 goto err_clear_state_opened_flag
;
2689 mlx5e_refresh_tirs(priv
, false);
2690 mlx5e_activate_priv_channels(priv
);
2691 if (priv
->profile
->update_carrier
)
2692 priv
->profile
->update_carrier(priv
);
2693 mlx5e_timestamp_set(priv
);
2695 if (priv
->profile
->update_stats
)
2696 queue_delayed_work(priv
->wq
, &priv
->update_stats_work
, 0);
2700 err_clear_state_opened_flag
:
2701 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2705 int mlx5e_open(struct net_device
*netdev
)
2707 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2710 mutex_lock(&priv
->state_lock
);
2711 err
= mlx5e_open_locked(netdev
);
2713 mlx5_set_port_admin_status(priv
->mdev
, MLX5_PORT_UP
);
2714 mutex_unlock(&priv
->state_lock
);
2719 int mlx5e_close_locked(struct net_device
*netdev
)
2721 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2723 /* May already be CLOSED in case a previous configuration operation
2724 * (e.g RX/TX queue size change) that involves close&open failed.
2726 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
2729 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2731 netif_carrier_off(priv
->netdev
);
2732 mlx5e_deactivate_priv_channels(priv
);
2733 mlx5e_close_channels(&priv
->channels
);
2738 int mlx5e_close(struct net_device
*netdev
)
2740 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2743 if (!netif_device_present(netdev
))
2746 mutex_lock(&priv
->state_lock
);
2747 mlx5_set_port_admin_status(priv
->mdev
, MLX5_PORT_DOWN
);
2748 err
= mlx5e_close_locked(netdev
);
2749 mutex_unlock(&priv
->state_lock
);
2754 static int mlx5e_alloc_drop_rq(struct mlx5_core_dev
*mdev
,
2755 struct mlx5e_rq
*rq
,
2756 struct mlx5e_rq_param
*param
)
2758 void *rqc
= param
->rqc
;
2759 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
2762 param
->wq
.db_numa_node
= param
->wq
.buf_numa_node
;
2764 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
2774 static int mlx5e_alloc_drop_cq(struct mlx5_core_dev
*mdev
,
2775 struct mlx5e_cq
*cq
,
2776 struct mlx5e_cq_param
*param
)
2778 return mlx5e_alloc_cq_common(mdev
, param
, cq
);
2781 static int mlx5e_open_drop_rq(struct mlx5_core_dev
*mdev
,
2782 struct mlx5e_rq
*drop_rq
)
2784 struct mlx5e_cq_param cq_param
= {};
2785 struct mlx5e_rq_param rq_param
= {};
2786 struct mlx5e_cq
*cq
= &drop_rq
->cq
;
2789 mlx5e_build_drop_rq_param(&rq_param
);
2791 err
= mlx5e_alloc_drop_cq(mdev
, cq
, &cq_param
);
2795 err
= mlx5e_create_cq(cq
, &cq_param
);
2799 err
= mlx5e_alloc_drop_rq(mdev
, drop_rq
, &rq_param
);
2801 goto err_destroy_cq
;
2803 err
= mlx5e_create_rq(drop_rq
, &rq_param
);
2810 mlx5e_free_rq(drop_rq
);
2813 mlx5e_destroy_cq(cq
);
2821 static void mlx5e_close_drop_rq(struct mlx5e_rq
*drop_rq
)
2823 mlx5e_destroy_rq(drop_rq
);
2824 mlx5e_free_rq(drop_rq
);
2825 mlx5e_destroy_cq(&drop_rq
->cq
);
2826 mlx5e_free_cq(&drop_rq
->cq
);
2829 int mlx5e_create_tis(struct mlx5_core_dev
*mdev
, int tc
,
2830 u32 underlay_qpn
, u32
*tisn
)
2832 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)] = {0};
2833 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
2835 MLX5_SET(tisc
, tisc
, prio
, tc
<< 1);
2836 MLX5_SET(tisc
, tisc
, underlay_qpn
, underlay_qpn
);
2837 MLX5_SET(tisc
, tisc
, transport_domain
, mdev
->mlx5e_res
.td
.tdn
);
2839 if (mlx5_lag_is_lacp_owner(mdev
))
2840 MLX5_SET(tisc
, tisc
, strict_lag_tx_port_affinity
, 1);
2842 return mlx5_core_create_tis(mdev
, in
, sizeof(in
), tisn
);
2845 void mlx5e_destroy_tis(struct mlx5_core_dev
*mdev
, u32 tisn
)
2847 mlx5_core_destroy_tis(mdev
, tisn
);
2850 int mlx5e_create_tises(struct mlx5e_priv
*priv
)
2855 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++) {
2856 err
= mlx5e_create_tis(priv
->mdev
, tc
, 0, &priv
->tisn
[tc
]);
2858 goto err_close_tises
;
2864 for (tc
--; tc
>= 0; tc
--)
2865 mlx5e_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
2870 void mlx5e_cleanup_nic_tx(struct mlx5e_priv
*priv
)
2874 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++)
2875 mlx5e_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
2878 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv
*priv
,
2879 enum mlx5e_traffic_types tt
,
2882 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2884 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2886 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2887 MLX5_SET(tirc
, tirc
, indirect_table
, priv
->indir_rqt
.rqtn
);
2888 mlx5e_build_indir_tir_ctx_hash(&priv
->channels
.params
, tt
, tirc
, false);
2891 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv
*priv
, u32 rqtn
, u32
*tirc
)
2893 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2895 mlx5e_build_tir_ctx_lro(&priv
->channels
.params
, tirc
);
2897 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2898 MLX5_SET(tirc
, tirc
, indirect_table
, rqtn
);
2899 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_INVERTED_XOR8
);
2902 int mlx5e_create_indirect_tirs(struct mlx5e_priv
*priv
)
2904 struct mlx5e_tir
*tir
;
2912 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2913 in
= kvzalloc(inlen
, GFP_KERNEL
);
2917 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
2918 memset(in
, 0, inlen
);
2919 tir
= &priv
->indir_tir
[tt
];
2920 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2921 mlx5e_build_indir_tir_ctx(priv
, tt
, tirc
);
2922 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2924 mlx5_core_warn(priv
->mdev
, "create indirect tirs failed, %d\n", err
);
2925 goto err_destroy_inner_tirs
;
2929 if (!mlx5e_tunnel_inner_ft_supported(priv
->mdev
))
2932 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++) {
2933 memset(in
, 0, inlen
);
2934 tir
= &priv
->inner_indir_tir
[i
];
2935 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2936 mlx5e_build_inner_indir_tir_ctx(priv
, i
, tirc
);
2937 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2939 mlx5_core_warn(priv
->mdev
, "create inner indirect tirs failed, %d\n", err
);
2940 goto err_destroy_inner_tirs
;
2949 err_destroy_inner_tirs
:
2950 for (i
--; i
>= 0; i
--)
2951 mlx5e_destroy_tir(priv
->mdev
, &priv
->inner_indir_tir
[i
]);
2953 for (tt
--; tt
>= 0; tt
--)
2954 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[tt
]);
2961 int mlx5e_create_direct_tirs(struct mlx5e_priv
*priv
)
2963 int nch
= priv
->profile
->max_nch(priv
->mdev
);
2964 struct mlx5e_tir
*tir
;
2971 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2972 in
= kvzalloc(inlen
, GFP_KERNEL
);
2976 for (ix
= 0; ix
< nch
; ix
++) {
2977 memset(in
, 0, inlen
);
2978 tir
= &priv
->direct_tir
[ix
];
2979 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2980 mlx5e_build_direct_tir_ctx(priv
, priv
->direct_tir
[ix
].rqt
.rqtn
, tirc
);
2981 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2983 goto err_destroy_ch_tirs
;
2990 err_destroy_ch_tirs
:
2991 mlx5_core_warn(priv
->mdev
, "create direct tirs failed, %d\n", err
);
2992 for (ix
--; ix
>= 0; ix
--)
2993 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[ix
]);
3000 void mlx5e_destroy_indirect_tirs(struct mlx5e_priv
*priv
)
3004 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++)
3005 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[i
]);
3007 if (!mlx5e_tunnel_inner_ft_supported(priv
->mdev
))
3010 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++)
3011 mlx5e_destroy_tir(priv
->mdev
, &priv
->inner_indir_tir
[i
]);
3014 void mlx5e_destroy_direct_tirs(struct mlx5e_priv
*priv
)
3016 int nch
= priv
->profile
->max_nch(priv
->mdev
);
3019 for (i
= 0; i
< nch
; i
++)
3020 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[i
]);
3023 static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels
*chs
, bool enable
)
3028 for (i
= 0; i
< chs
->num
; i
++) {
3029 err
= mlx5e_modify_rq_scatter_fcs(&chs
->c
[i
]->rq
, enable
);
3037 static int mlx5e_modify_channels_vsd(struct mlx5e_channels
*chs
, bool vsd
)
3042 for (i
= 0; i
< chs
->num
; i
++) {
3043 err
= mlx5e_modify_rq_vsd(&chs
->c
[i
]->rq
, vsd
);
3051 static int mlx5e_setup_tc_mqprio(struct net_device
*netdev
,
3052 struct tc_mqprio_qopt
*mqprio
)
3054 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3055 struct mlx5e_channels new_channels
= {};
3056 u8 tc
= mqprio
->num_tc
;
3059 mqprio
->hw
= TC_MQPRIO_HW_OFFLOAD_TCS
;
3061 if (tc
&& tc
!= MLX5E_MAX_NUM_TC
)
3064 mutex_lock(&priv
->state_lock
);
3066 new_channels
.params
= priv
->channels
.params
;
3067 new_channels
.params
.num_tc
= tc
? tc
: 1;
3069 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
3070 priv
->channels
.params
= new_channels
.params
;
3074 err
= mlx5e_open_channels(priv
, &new_channels
);
3078 mlx5e_switch_priv_channels(priv
, &new_channels
, NULL
);
3080 mutex_unlock(&priv
->state_lock
);
3084 #ifdef CONFIG_MLX5_ESWITCH
3085 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv
*priv
,
3086 struct tc_cls_flower_offload
*cls_flower
)
3088 if (cls_flower
->common
.chain_index
)
3091 switch (cls_flower
->command
) {
3092 case TC_CLSFLOWER_REPLACE
:
3093 return mlx5e_configure_flower(priv
, cls_flower
);
3094 case TC_CLSFLOWER_DESTROY
:
3095 return mlx5e_delete_flower(priv
, cls_flower
);
3096 case TC_CLSFLOWER_STATS
:
3097 return mlx5e_stats_flower(priv
, cls_flower
);
3103 int mlx5e_setup_tc_block_cb(enum tc_setup_type type
, void *type_data
,
3106 struct mlx5e_priv
*priv
= cb_priv
;
3108 if (!tc_can_offload(priv
->netdev
))
3112 case TC_SETUP_CLSFLOWER
:
3113 return mlx5e_setup_tc_cls_flower(priv
, type_data
);
3119 static int mlx5e_setup_tc_block(struct net_device
*dev
,
3120 struct tc_block_offload
*f
)
3122 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3124 if (f
->binder_type
!= TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS
)
3127 switch (f
->command
) {
3129 return tcf_block_cb_register(f
->block
, mlx5e_setup_tc_block_cb
,
3131 case TC_BLOCK_UNBIND
:
3132 tcf_block_cb_unregister(f
->block
, mlx5e_setup_tc_block_cb
,
3141 int mlx5e_setup_tc(struct net_device
*dev
, enum tc_setup_type type
,
3145 #ifdef CONFIG_MLX5_ESWITCH
3146 case TC_SETUP_BLOCK
:
3147 return mlx5e_setup_tc_block(dev
, type_data
);
3149 case TC_SETUP_QDISC_MQPRIO
:
3150 return mlx5e_setup_tc_mqprio(dev
, type_data
);
3157 mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
3159 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3160 struct mlx5e_sw_stats
*sstats
= &priv
->stats
.sw
;
3161 struct mlx5e_vport_stats
*vstats
= &priv
->stats
.vport
;
3162 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
3164 if (mlx5e_is_uplink_rep(priv
)) {
3165 stats
->rx_packets
= PPORT_802_3_GET(pstats
, a_frames_received_ok
);
3166 stats
->rx_bytes
= PPORT_802_3_GET(pstats
, a_octets_received_ok
);
3167 stats
->tx_packets
= PPORT_802_3_GET(pstats
, a_frames_transmitted_ok
);
3168 stats
->tx_bytes
= PPORT_802_3_GET(pstats
, a_octets_transmitted_ok
);
3170 stats
->rx_packets
= sstats
->rx_packets
;
3171 stats
->rx_bytes
= sstats
->rx_bytes
;
3172 stats
->tx_packets
= sstats
->tx_packets
;
3173 stats
->tx_bytes
= sstats
->tx_bytes
;
3174 stats
->tx_dropped
= sstats
->tx_queue_dropped
;
3177 stats
->rx_dropped
= priv
->stats
.qcnt
.rx_out_of_buffer
;
3179 stats
->rx_length_errors
=
3180 PPORT_802_3_GET(pstats
, a_in_range_length_errors
) +
3181 PPORT_802_3_GET(pstats
, a_out_of_range_length_field
) +
3182 PPORT_802_3_GET(pstats
, a_frame_too_long_errors
);
3183 stats
->rx_crc_errors
=
3184 PPORT_802_3_GET(pstats
, a_frame_check_sequence_errors
);
3185 stats
->rx_frame_errors
= PPORT_802_3_GET(pstats
, a_alignment_errors
);
3186 stats
->tx_aborted_errors
= PPORT_2863_GET(pstats
, if_out_discards
);
3187 stats
->rx_errors
= stats
->rx_length_errors
+ stats
->rx_crc_errors
+
3188 stats
->rx_frame_errors
;
3189 stats
->tx_errors
= stats
->tx_aborted_errors
+ stats
->tx_carrier_errors
;
3191 /* vport multicast also counts packets that are dropped due to steering
3192 * or rx out of buffer
3195 VPORT_COUNTER_GET(vstats
, received_eth_multicast
.packets
);
3198 static void mlx5e_set_rx_mode(struct net_device
*dev
)
3200 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3202 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3205 static int mlx5e_set_mac(struct net_device
*netdev
, void *addr
)
3207 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3208 struct sockaddr
*saddr
= addr
;
3210 if (!is_valid_ether_addr(saddr
->sa_data
))
3211 return -EADDRNOTAVAIL
;
3213 netif_addr_lock_bh(netdev
);
3214 ether_addr_copy(netdev
->dev_addr
, saddr
->sa_data
);
3215 netif_addr_unlock_bh(netdev
);
3217 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3222 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
3225 netdev->features |= feature; \
3227 netdev->features &= ~feature; \
3230 typedef int (*mlx5e_feature_handler
)(struct net_device
*netdev
, bool enable
);
3232 static int set_feature_lro(struct net_device
*netdev
, bool enable
)
3234 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3235 struct mlx5e_channels new_channels
= {};
3239 mutex_lock(&priv
->state_lock
);
3241 reset
= (priv
->channels
.params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST
);
3242 reset
= reset
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3244 new_channels
.params
= priv
->channels
.params
;
3245 new_channels
.params
.lro_en
= enable
;
3248 priv
->channels
.params
= new_channels
.params
;
3249 err
= mlx5e_modify_tirs_lro(priv
);
3253 err
= mlx5e_open_channels(priv
, &new_channels
);
3257 mlx5e_switch_priv_channels(priv
, &new_channels
, mlx5e_modify_tirs_lro
);
3259 mutex_unlock(&priv
->state_lock
);
3263 static int set_feature_cvlan_filter(struct net_device
*netdev
, bool enable
)
3265 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3268 mlx5e_enable_cvlan_filter(priv
);
3270 mlx5e_disable_cvlan_filter(priv
);
3275 static int set_feature_tc_num_filters(struct net_device
*netdev
, bool enable
)
3277 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3279 if (!enable
&& mlx5e_tc_num_filters(priv
)) {
3281 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3288 static int set_feature_rx_all(struct net_device
*netdev
, bool enable
)
3290 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3291 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3293 return mlx5_set_port_fcs(mdev
, !enable
);
3296 static int set_feature_rx_fcs(struct net_device
*netdev
, bool enable
)
3298 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3301 mutex_lock(&priv
->state_lock
);
3303 priv
->channels
.params
.scatter_fcs_en
= enable
;
3304 err
= mlx5e_modify_channels_scatter_fcs(&priv
->channels
, enable
);
3306 priv
->channels
.params
.scatter_fcs_en
= !enable
;
3308 mutex_unlock(&priv
->state_lock
);
3313 static int set_feature_rx_vlan(struct net_device
*netdev
, bool enable
)
3315 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3318 mutex_lock(&priv
->state_lock
);
3320 priv
->channels
.params
.vlan_strip_disable
= !enable
;
3321 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
3324 err
= mlx5e_modify_channels_vsd(&priv
->channels
, !enable
);
3326 priv
->channels
.params
.vlan_strip_disable
= enable
;
3329 mutex_unlock(&priv
->state_lock
);
3334 #ifdef CONFIG_RFS_ACCEL
3335 static int set_feature_arfs(struct net_device
*netdev
, bool enable
)
3337 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3341 err
= mlx5e_arfs_enable(priv
);
3343 err
= mlx5e_arfs_disable(priv
);
3349 static int mlx5e_handle_feature(struct net_device
*netdev
,
3350 netdev_features_t wanted_features
,
3351 netdev_features_t feature
,
3352 mlx5e_feature_handler feature_handler
)
3354 netdev_features_t changes
= wanted_features
^ netdev
->features
;
3355 bool enable
= !!(wanted_features
& feature
);
3358 if (!(changes
& feature
))
3361 err
= feature_handler(netdev
, enable
);
3363 netdev_err(netdev
, "%s feature %pNF failed, err %d\n",
3364 enable
? "Enable" : "Disable", &feature
, err
);
3368 MLX5E_SET_FEATURE(netdev
, feature
, enable
);
3372 static int mlx5e_set_features(struct net_device
*netdev
,
3373 netdev_features_t features
)
3377 err
= mlx5e_handle_feature(netdev
, features
, NETIF_F_LRO
,
3379 err
|= mlx5e_handle_feature(netdev
, features
,
3380 NETIF_F_HW_VLAN_CTAG_FILTER
,
3381 set_feature_cvlan_filter
);
3382 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_TC
,
3383 set_feature_tc_num_filters
);
3384 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_RXALL
,
3385 set_feature_rx_all
);
3386 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_RXFCS
,
3387 set_feature_rx_fcs
);
3388 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_VLAN_CTAG_RX
,
3389 set_feature_rx_vlan
);
3390 #ifdef CONFIG_RFS_ACCEL
3391 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_NTUPLE
,
3395 return err
? -EINVAL
: 0;
3398 static netdev_features_t
mlx5e_fix_features(struct net_device
*netdev
,
3399 netdev_features_t features
)
3401 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3403 mutex_lock(&priv
->state_lock
);
3404 if (!bitmap_empty(priv
->fs
.vlan
.active_svlans
, VLAN_N_VID
)) {
3405 /* HW strips the outer C-tag header, this is a problem
3406 * for S-tag traffic.
3408 features
&= ~NETIF_F_HW_VLAN_CTAG_RX
;
3409 if (!priv
->channels
.params
.vlan_strip_disable
)
3410 netdev_warn(netdev
, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3412 mutex_unlock(&priv
->state_lock
);
3417 static int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
)
3419 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3420 struct mlx5e_channels new_channels
= {};
3425 mutex_lock(&priv
->state_lock
);
3427 reset
= !priv
->channels
.params
.lro_en
&&
3428 (priv
->channels
.params
.rq_wq_type
!=
3429 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
3431 reset
= reset
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3433 curr_mtu
= netdev
->mtu
;
3434 netdev
->mtu
= new_mtu
;
3437 mlx5e_set_dev_port_mtu(priv
);
3441 new_channels
.params
= priv
->channels
.params
;
3442 err
= mlx5e_open_channels(priv
, &new_channels
);
3444 netdev
->mtu
= curr_mtu
;
3448 mlx5e_switch_priv_channels(priv
, &new_channels
, mlx5e_set_dev_port_mtu
);
3451 mutex_unlock(&priv
->state_lock
);
3455 int mlx5e_hwstamp_set(struct mlx5e_priv
*priv
, struct ifreq
*ifr
)
3457 struct hwtstamp_config config
;
3460 if (!MLX5_CAP_GEN(priv
->mdev
, device_frequency_khz
))
3463 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
3466 /* TX HW timestamp */
3467 switch (config
.tx_type
) {
3468 case HWTSTAMP_TX_OFF
:
3469 case HWTSTAMP_TX_ON
:
3475 mutex_lock(&priv
->state_lock
);
3476 /* RX HW timestamp */
3477 switch (config
.rx_filter
) {
3478 case HWTSTAMP_FILTER_NONE
:
3479 /* Reset CQE compression to Admin default */
3480 mlx5e_modify_rx_cqe_compression_locked(priv
, priv
->channels
.params
.rx_cqe_compress_def
);
3482 case HWTSTAMP_FILTER_ALL
:
3483 case HWTSTAMP_FILTER_SOME
:
3484 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
3485 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
3486 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
3487 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
3488 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
3489 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
3490 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
3491 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
3492 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
3493 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
3494 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
3495 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
3496 case HWTSTAMP_FILTER_NTP_ALL
:
3497 /* Disable CQE compression */
3498 netdev_warn(priv
->netdev
, "Disabling cqe compression");
3499 err
= mlx5e_modify_rx_cqe_compression_locked(priv
, false);
3501 netdev_err(priv
->netdev
, "Failed disabling cqe compression err=%d\n", err
);
3502 mutex_unlock(&priv
->state_lock
);
3505 config
.rx_filter
= HWTSTAMP_FILTER_ALL
;
3508 mutex_unlock(&priv
->state_lock
);
3512 memcpy(&priv
->tstamp
, &config
, sizeof(config
));
3513 mutex_unlock(&priv
->state_lock
);
3515 return copy_to_user(ifr
->ifr_data
, &config
,
3516 sizeof(config
)) ? -EFAULT
: 0;
3519 int mlx5e_hwstamp_get(struct mlx5e_priv
*priv
, struct ifreq
*ifr
)
3521 struct hwtstamp_config
*cfg
= &priv
->tstamp
;
3523 if (!MLX5_CAP_GEN(priv
->mdev
, device_frequency_khz
))
3526 return copy_to_user(ifr
->ifr_data
, cfg
, sizeof(*cfg
)) ? -EFAULT
: 0;
3529 static int mlx5e_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3531 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3535 return mlx5e_hwstamp_set(priv
, ifr
);
3537 return mlx5e_hwstamp_get(priv
, ifr
);
3543 #ifdef CONFIG_MLX5_ESWITCH
3544 static int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
)
3546 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3547 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3549 return mlx5_eswitch_set_vport_mac(mdev
->priv
.eswitch
, vf
+ 1, mac
);
3552 static int mlx5e_set_vf_vlan(struct net_device
*dev
, int vf
, u16 vlan
, u8 qos
,
3555 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3556 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3558 if (vlan_proto
!= htons(ETH_P_8021Q
))
3559 return -EPROTONOSUPPORT
;
3561 return mlx5_eswitch_set_vport_vlan(mdev
->priv
.eswitch
, vf
+ 1,
3565 static int mlx5e_set_vf_spoofchk(struct net_device
*dev
, int vf
, bool setting
)
3567 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3568 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3570 return mlx5_eswitch_set_vport_spoofchk(mdev
->priv
.eswitch
, vf
+ 1, setting
);
3573 static int mlx5e_set_vf_trust(struct net_device
*dev
, int vf
, bool setting
)
3575 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3576 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3578 return mlx5_eswitch_set_vport_trust(mdev
->priv
.eswitch
, vf
+ 1, setting
);
3581 static int mlx5e_set_vf_rate(struct net_device
*dev
, int vf
, int min_tx_rate
,
3584 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3585 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3587 return mlx5_eswitch_set_vport_rate(mdev
->priv
.eswitch
, vf
+ 1,
3588 max_tx_rate
, min_tx_rate
);
3591 static int mlx5_vport_link2ifla(u8 esw_link
)
3594 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN
:
3595 return IFLA_VF_LINK_STATE_DISABLE
;
3596 case MLX5_ESW_VPORT_ADMIN_STATE_UP
:
3597 return IFLA_VF_LINK_STATE_ENABLE
;
3599 return IFLA_VF_LINK_STATE_AUTO
;
3602 static int mlx5_ifla_link2vport(u8 ifla_link
)
3604 switch (ifla_link
) {
3605 case IFLA_VF_LINK_STATE_DISABLE
:
3606 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN
;
3607 case IFLA_VF_LINK_STATE_ENABLE
:
3608 return MLX5_ESW_VPORT_ADMIN_STATE_UP
;
3610 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO
;
3613 static int mlx5e_set_vf_link_state(struct net_device
*dev
, int vf
,
3616 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3617 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3619 return mlx5_eswitch_set_vport_state(mdev
->priv
.eswitch
, vf
+ 1,
3620 mlx5_ifla_link2vport(link_state
));
3623 static int mlx5e_get_vf_config(struct net_device
*dev
,
3624 int vf
, struct ifla_vf_info
*ivi
)
3626 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3627 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3630 err
= mlx5_eswitch_get_vport_config(mdev
->priv
.eswitch
, vf
+ 1, ivi
);
3633 ivi
->linkstate
= mlx5_vport_link2ifla(ivi
->linkstate
);
3637 static int mlx5e_get_vf_stats(struct net_device
*dev
,
3638 int vf
, struct ifla_vf_stats
*vf_stats
)
3640 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3641 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3643 return mlx5_eswitch_get_vport_stats(mdev
->priv
.eswitch
, vf
+ 1,
3648 static void mlx5e_add_vxlan_port(struct net_device
*netdev
,
3649 struct udp_tunnel_info
*ti
)
3651 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3653 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
3656 if (!mlx5e_vxlan_allowed(priv
->mdev
))
3659 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 1);
3662 static void mlx5e_del_vxlan_port(struct net_device
*netdev
,
3663 struct udp_tunnel_info
*ti
)
3665 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3667 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
3670 if (!mlx5e_vxlan_allowed(priv
->mdev
))
3673 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 0);
3676 static netdev_features_t
mlx5e_tunnel_features_check(struct mlx5e_priv
*priv
,
3677 struct sk_buff
*skb
,
3678 netdev_features_t features
)
3680 unsigned int offset
= 0;
3681 struct udphdr
*udph
;
3685 switch (vlan_get_protocol(skb
)) {
3686 case htons(ETH_P_IP
):
3687 proto
= ip_hdr(skb
)->protocol
;
3689 case htons(ETH_P_IPV6
):
3690 proto
= ipv6_find_hdr(skb
, &offset
, -1, NULL
, NULL
);
3700 udph
= udp_hdr(skb
);
3701 port
= be16_to_cpu(udph
->dest
);
3703 /* Verify if UDP port is being offloaded by HW */
3704 if (mlx5e_vxlan_lookup_port(priv
, port
))
3709 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3710 return features
& ~(NETIF_F_CSUM_MASK
| NETIF_F_GSO_MASK
);
3713 static netdev_features_t
mlx5e_features_check(struct sk_buff
*skb
,
3714 struct net_device
*netdev
,
3715 netdev_features_t features
)
3717 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3719 features
= vlan_features_check(skb
, features
);
3720 features
= vxlan_features_check(skb
, features
);
3722 #ifdef CONFIG_MLX5_EN_IPSEC
3723 if (mlx5e_ipsec_feature_check(skb
, netdev
, features
))
3727 /* Validate if the tunneled packet is being offloaded by HW */
3728 if (skb
->encapsulation
&&
3729 (features
& NETIF_F_CSUM_MASK
|| features
& NETIF_F_GSO_MASK
))
3730 return mlx5e_tunnel_features_check(priv
, skb
, features
);
3735 static void mlx5e_tx_timeout(struct net_device
*dev
)
3737 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3738 bool sched_work
= false;
3741 netdev_err(dev
, "TX timeout detected\n");
3743 for (i
= 0; i
< priv
->channels
.num
* priv
->channels
.params
.num_tc
; i
++) {
3744 struct mlx5e_txqsq
*sq
= priv
->txq2sq
[i
];
3746 if (!netif_xmit_stopped(netdev_get_tx_queue(dev
, i
)))
3749 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
3750 netdev_err(dev
, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3751 i
, sq
->sqn
, sq
->cq
.mcq
.cqn
, sq
->cc
, sq
->pc
);
3754 if (sched_work
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
3755 schedule_work(&priv
->tx_timeout_work
);
3758 static int mlx5e_xdp_set(struct net_device
*netdev
, struct bpf_prog
*prog
)
3760 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3761 struct bpf_prog
*old_prog
;
3763 bool reset
, was_opened
;
3766 mutex_lock(&priv
->state_lock
);
3768 if ((netdev
->features
& NETIF_F_LRO
) && prog
) {
3769 netdev_warn(netdev
, "can't set XDP while LRO is on, disable LRO first\n");
3774 if ((netdev
->features
& NETIF_F_HW_ESP
) && prog
) {
3775 netdev_warn(netdev
, "can't set XDP with IPSec offload\n");
3780 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3781 /* no need for full reset when exchanging programs */
3782 reset
= (!priv
->channels
.params
.xdp_prog
|| !prog
);
3784 if (was_opened
&& reset
)
3785 mlx5e_close_locked(netdev
);
3786 if (was_opened
&& !reset
) {
3787 /* num_channels is invariant here, so we can take the
3788 * batched reference right upfront.
3790 prog
= bpf_prog_add(prog
, priv
->channels
.num
);
3792 err
= PTR_ERR(prog
);
3797 /* exchange programs, extra prog reference we got from caller
3798 * as long as we don't fail from this point onwards.
3800 old_prog
= xchg(&priv
->channels
.params
.xdp_prog
, prog
);
3802 bpf_prog_put(old_prog
);
3804 if (reset
) /* change RQ type according to priv->xdp_prog */
3805 mlx5e_set_rq_params(priv
->mdev
, &priv
->channels
.params
);
3807 if (was_opened
&& reset
)
3808 mlx5e_open_locked(netdev
);
3810 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
) || reset
)
3813 /* exchanging programs w/o reset, we update ref counts on behalf
3814 * of the channels RQs here.
3816 for (i
= 0; i
< priv
->channels
.num
; i
++) {
3817 struct mlx5e_channel
*c
= priv
->channels
.c
[i
];
3819 clear_bit(MLX5E_RQ_STATE_ENABLED
, &c
->rq
.state
);
3820 napi_synchronize(&c
->napi
);
3821 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3823 old_prog
= xchg(&c
->rq
.xdp_prog
, prog
);
3825 set_bit(MLX5E_RQ_STATE_ENABLED
, &c
->rq
.state
);
3826 /* napi_schedule in case we have missed anything */
3827 napi_schedule(&c
->napi
);
3830 bpf_prog_put(old_prog
);
3834 mutex_unlock(&priv
->state_lock
);
3838 static u32
mlx5e_xdp_query(struct net_device
*dev
)
3840 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3841 const struct bpf_prog
*xdp_prog
;
3844 mutex_lock(&priv
->state_lock
);
3845 xdp_prog
= priv
->channels
.params
.xdp_prog
;
3847 prog_id
= xdp_prog
->aux
->id
;
3848 mutex_unlock(&priv
->state_lock
);
3853 static int mlx5e_xdp(struct net_device
*dev
, struct netdev_bpf
*xdp
)
3855 switch (xdp
->command
) {
3856 case XDP_SETUP_PROG
:
3857 return mlx5e_xdp_set(dev
, xdp
->prog
);
3858 case XDP_QUERY_PROG
:
3859 xdp
->prog_id
= mlx5e_xdp_query(dev
);
3860 xdp
->prog_attached
= !!xdp
->prog_id
;
3867 #ifdef CONFIG_NET_POLL_CONTROLLER
3868 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3869 * reenabling interrupts.
3871 static void mlx5e_netpoll(struct net_device
*dev
)
3873 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3874 struct mlx5e_channels
*chs
= &priv
->channels
;
3878 for (i
= 0; i
< chs
->num
; i
++)
3879 napi_schedule(&chs
->c
[i
]->napi
);
3883 static const struct net_device_ops mlx5e_netdev_ops
= {
3884 .ndo_open
= mlx5e_open
,
3885 .ndo_stop
= mlx5e_close
,
3886 .ndo_start_xmit
= mlx5e_xmit
,
3887 .ndo_setup_tc
= mlx5e_setup_tc
,
3888 .ndo_select_queue
= mlx5e_select_queue
,
3889 .ndo_get_stats64
= mlx5e_get_stats
,
3890 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
3891 .ndo_set_mac_address
= mlx5e_set_mac
,
3892 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
3893 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
3894 .ndo_set_features
= mlx5e_set_features
,
3895 .ndo_fix_features
= mlx5e_fix_features
,
3896 .ndo_change_mtu
= mlx5e_change_mtu
,
3897 .ndo_do_ioctl
= mlx5e_ioctl
,
3898 .ndo_set_tx_maxrate
= mlx5e_set_tx_maxrate
,
3899 .ndo_udp_tunnel_add
= mlx5e_add_vxlan_port
,
3900 .ndo_udp_tunnel_del
= mlx5e_del_vxlan_port
,
3901 .ndo_features_check
= mlx5e_features_check
,
3902 #ifdef CONFIG_RFS_ACCEL
3903 .ndo_rx_flow_steer
= mlx5e_rx_flow_steer
,
3905 .ndo_tx_timeout
= mlx5e_tx_timeout
,
3906 .ndo_bpf
= mlx5e_xdp
,
3907 #ifdef CONFIG_NET_POLL_CONTROLLER
3908 .ndo_poll_controller
= mlx5e_netpoll
,
3910 #ifdef CONFIG_MLX5_ESWITCH
3911 /* SRIOV E-Switch NDOs */
3912 .ndo_set_vf_mac
= mlx5e_set_vf_mac
,
3913 .ndo_set_vf_vlan
= mlx5e_set_vf_vlan
,
3914 .ndo_set_vf_spoofchk
= mlx5e_set_vf_spoofchk
,
3915 .ndo_set_vf_trust
= mlx5e_set_vf_trust
,
3916 .ndo_set_vf_rate
= mlx5e_set_vf_rate
,
3917 .ndo_get_vf_config
= mlx5e_get_vf_config
,
3918 .ndo_set_vf_link_state
= mlx5e_set_vf_link_state
,
3919 .ndo_get_vf_stats
= mlx5e_get_vf_stats
,
3920 .ndo_has_offload_stats
= mlx5e_has_offload_stats
,
3921 .ndo_get_offload_stats
= mlx5e_get_offload_stats
,
3925 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev
*mdev
)
3927 if (MLX5_CAP_GEN(mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
)
3929 if (!MLX5_CAP_GEN(mdev
, eth_net_offloads
) ||
3930 !MLX5_CAP_GEN(mdev
, nic_flow_table
) ||
3931 !MLX5_CAP_ETH(mdev
, csum_cap
) ||
3932 !MLX5_CAP_ETH(mdev
, max_lso_cap
) ||
3933 !MLX5_CAP_ETH(mdev
, vlan_cap
) ||
3934 !MLX5_CAP_ETH(mdev
, rss_ind_tbl_cap
) ||
3935 MLX5_CAP_FLOWTABLE(mdev
,
3936 flow_table_properties_nic_receive
.max_ft_level
)
3938 mlx5_core_warn(mdev
,
3939 "Not creating net device, some required device capabilities are missing\n");
3942 if (!MLX5_CAP_ETH(mdev
, self_lb_en_modifiable
))
3943 mlx5_core_warn(mdev
, "Self loop back prevention is not supported\n");
3944 if (!MLX5_CAP_GEN(mdev
, cq_moderation
))
3945 mlx5_core_warn(mdev
, "CQ moderation is not supported\n");
3950 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
)
3952 int bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
3954 return bf_buf_size
-
3955 sizeof(struct mlx5e_tx_wqe
) +
3956 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3959 void mlx5e_build_default_indir_rqt(u32
*indirection_rqt
, int len
,
3964 for (i
= 0; i
< len
; i
++)
3965 indirection_rqt
[i
] = i
% num_channels
;
3968 static int mlx5e_get_pci_bw(struct mlx5_core_dev
*mdev
, u32
*pci_bw
)
3970 enum pcie_link_width width
;
3971 enum pci_bus_speed speed
;
3974 err
= pcie_get_minimum_link(mdev
->pdev
, &speed
, &width
);
3978 if (speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
3982 case PCIE_SPEED_2_5GT
:
3983 *pci_bw
= 2500 * width
;
3985 case PCIE_SPEED_5_0GT
:
3986 *pci_bw
= 5000 * width
;
3988 case PCIE_SPEED_8_0GT
:
3989 *pci_bw
= 8000 * width
;
3998 static bool cqe_compress_heuristic(u32 link_speed
, u32 pci_bw
)
4000 return (link_speed
&& pci_bw
&&
4001 (pci_bw
< 40000) && (pci_bw
< link_speed
));
4004 static bool hw_lro_heuristic(u32 link_speed
, u32 pci_bw
)
4006 return !(link_speed
&& pci_bw
&&
4007 (pci_bw
<= 16000) && (pci_bw
< link_speed
));
4010 void mlx5e_set_tx_cq_mode_params(struct mlx5e_params
*params
, u8 cq_period_mode
)
4012 params
->tx_cq_moderation
.cq_period_mode
= cq_period_mode
;
4014 params
->tx_cq_moderation
.pkts
=
4015 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS
;
4016 params
->tx_cq_moderation
.usec
=
4017 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC
;
4019 if (cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
)
4020 params
->tx_cq_moderation
.usec
=
4021 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE
;
4023 MLX5E_SET_PFLAG(params
, MLX5E_PFLAG_TX_CQE_BASED_MODER
,
4024 params
->tx_cq_moderation
.cq_period_mode
==
4025 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
);
4028 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params
*params
, u8 cq_period_mode
)
4030 params
->rx_cq_moderation
.cq_period_mode
= cq_period_mode
;
4032 params
->rx_cq_moderation
.pkts
=
4033 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS
;
4034 params
->rx_cq_moderation
.usec
=
4035 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC
;
4037 if (cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
)
4038 params
->rx_cq_moderation
.usec
=
4039 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE
;
4041 if (params
->rx_am_enabled
)
4042 params
->rx_cq_moderation
=
4043 mlx5e_am_get_def_profile(cq_period_mode
);
4045 MLX5E_SET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_BASED_MODER
,
4046 params
->rx_cq_moderation
.cq_period_mode
==
4047 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
);
4050 u32
mlx5e_choose_lro_timeout(struct mlx5_core_dev
*mdev
, u32 wanted_timeout
)
4054 /* The supported periods are organized in ascending order */
4055 for (i
= 0; i
< MLX5E_LRO_TIMEOUT_ARR_SIZE
- 1; i
++)
4056 if (MLX5_CAP_ETH(mdev
, lro_timer_supported_periods
[i
]) >= wanted_timeout
)
4059 return MLX5_CAP_ETH(mdev
, lro_timer_supported_periods
[i
]);
4062 void mlx5e_build_nic_params(struct mlx5_core_dev
*mdev
,
4063 struct mlx5e_params
*params
,
4066 u8 cq_period_mode
= 0;
4070 params
->num_channels
= max_channels
;
4073 mlx5e_get_max_linkspeed(mdev
, &link_speed
);
4074 mlx5e_get_pci_bw(mdev
, &pci_bw
);
4075 mlx5_core_dbg(mdev
, "Max link speed = %d, PCI BW = %d\n",
4076 link_speed
, pci_bw
);
4079 params
->log_sq_size
= is_kdump_kernel() ?
4080 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
:
4081 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE
;
4083 /* set CQE compression */
4084 params
->rx_cqe_compress_def
= false;
4085 if (MLX5_CAP_GEN(mdev
, cqe_compression
) &&
4086 MLX5_CAP_GEN(mdev
, vport_group_manager
))
4087 params
->rx_cqe_compress_def
= cqe_compress_heuristic(link_speed
, pci_bw
);
4089 MLX5E_SET_PFLAG(params
, MLX5E_PFLAG_RX_CQE_COMPRESS
, params
->rx_cqe_compress_def
);
4092 mlx5e_set_rq_params(mdev
, params
);
4096 /* TODO: && MLX5_CAP_ETH(mdev, lro_cap) */
4097 if (params
->rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
)
4098 params
->lro_en
= hw_lro_heuristic(link_speed
, pci_bw
);
4099 params
->lro_timeout
= mlx5e_choose_lro_timeout(mdev
, MLX5E_DEFAULT_LRO_TIMEOUT
);
4101 /* CQ moderation params */
4102 cq_period_mode
= MLX5_CAP_GEN(mdev
, cq_period_start_from_cqe
) ?
4103 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
:
4104 MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
4105 params
->rx_am_enabled
= MLX5_CAP_GEN(mdev
, cq_moderation
);
4106 mlx5e_set_rx_cq_mode_params(params
, cq_period_mode
);
4107 mlx5e_set_tx_cq_mode_params(params
, cq_period_mode
);
4110 params
->tx_max_inline
= mlx5e_get_max_inline_cap(mdev
);
4111 params
->tx_min_inline_mode
= mlx5e_params_calculate_tx_min_inline(mdev
);
4114 params
->rss_hfunc
= ETH_RSS_HASH_XOR
;
4115 netdev_rss_key_fill(params
->toeplitz_hash_key
, sizeof(params
->toeplitz_hash_key
));
4116 mlx5e_build_default_indir_rqt(params
->indirection_rqt
,
4117 MLX5E_INDIR_RQT_SIZE
, max_channels
);
4120 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev
*mdev
,
4121 struct net_device
*netdev
,
4122 const struct mlx5e_profile
*profile
,
4125 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4128 priv
->netdev
= netdev
;
4129 priv
->profile
= profile
;
4130 priv
->ppriv
= ppriv
;
4131 priv
->msglevel
= MLX5E_MSG_LEVEL
;
4132 priv
->hard_mtu
= MLX5E_ETH_HARD_MTU
;
4134 mlx5e_build_nic_params(mdev
, &priv
->channels
.params
, profile
->max_nch(mdev
));
4136 mutex_init(&priv
->state_lock
);
4138 INIT_WORK(&priv
->update_carrier_work
, mlx5e_update_carrier_work
);
4139 INIT_WORK(&priv
->set_rx_mode_work
, mlx5e_set_rx_mode_work
);
4140 INIT_WORK(&priv
->tx_timeout_work
, mlx5e_tx_timeout_work
);
4141 INIT_DELAYED_WORK(&priv
->update_stats_work
, mlx5e_update_stats_work
);
4144 static void mlx5e_set_netdev_dev_addr(struct net_device
*netdev
)
4146 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4148 mlx5_query_nic_vport_mac_address(priv
->mdev
, 0, netdev
->dev_addr
);
4149 if (is_zero_ether_addr(netdev
->dev_addr
) &&
4150 !MLX5_CAP_GEN(priv
->mdev
, vport_group_manager
)) {
4151 eth_hw_addr_random(netdev
);
4152 mlx5_core_info(priv
->mdev
, "Assigned random MAC address %pM\n", netdev
->dev_addr
);
4156 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4157 static const struct switchdev_ops mlx5e_switchdev_ops
= {
4158 .switchdev_port_attr_get
= mlx5e_attr_get
,
4162 static void mlx5e_build_nic_netdev(struct net_device
*netdev
)
4164 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4165 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4169 SET_NETDEV_DEV(netdev
, &mdev
->pdev
->dev
);
4171 netdev
->netdev_ops
= &mlx5e_netdev_ops
;
4173 #ifdef CONFIG_MLX5_CORE_EN_DCB
4174 if (MLX5_CAP_GEN(mdev
, vport_group_manager
) && MLX5_CAP_GEN(mdev
, qos
))
4175 netdev
->dcbnl_ops
= &mlx5e_dcbnl_ops
;
4178 netdev
->watchdog_timeo
= 15 * HZ
;
4180 netdev
->ethtool_ops
= &mlx5e_ethtool_ops
;
4182 netdev
->vlan_features
|= NETIF_F_SG
;
4183 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
4184 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
4185 netdev
->vlan_features
|= NETIF_F_GRO
;
4186 netdev
->vlan_features
|= NETIF_F_TSO
;
4187 netdev
->vlan_features
|= NETIF_F_TSO6
;
4188 netdev
->vlan_features
|= NETIF_F_RXCSUM
;
4189 netdev
->vlan_features
|= NETIF_F_RXHASH
;
4191 if (!!MLX5_CAP_ETH(mdev
, lro_cap
))
4192 netdev
->vlan_features
|= NETIF_F_LRO
;
4194 netdev
->hw_features
= netdev
->vlan_features
;
4195 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
;
4196 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
;
4197 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
4198 netdev
->hw_features
|= NETIF_F_HW_VLAN_STAG_TX
;
4200 if (mlx5e_vxlan_allowed(mdev
) || MLX5_CAP_ETH(mdev
, tunnel_stateless_gre
)) {
4201 netdev
->hw_features
|= NETIF_F_GSO_PARTIAL
;
4202 netdev
->hw_enc_features
|= NETIF_F_IP_CSUM
;
4203 netdev
->hw_enc_features
|= NETIF_F_IPV6_CSUM
;
4204 netdev
->hw_enc_features
|= NETIF_F_TSO
;
4205 netdev
->hw_enc_features
|= NETIF_F_TSO6
;
4206 netdev
->hw_enc_features
|= NETIF_F_GSO_PARTIAL
;
4209 if (mlx5e_vxlan_allowed(mdev
)) {
4210 netdev
->hw_features
|= NETIF_F_GSO_UDP_TUNNEL
|
4211 NETIF_F_GSO_UDP_TUNNEL_CSUM
;
4212 netdev
->hw_enc_features
|= NETIF_F_GSO_UDP_TUNNEL
|
4213 NETIF_F_GSO_UDP_TUNNEL_CSUM
;
4214 netdev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
;
4217 if (MLX5_CAP_ETH(mdev
, tunnel_stateless_gre
)) {
4218 netdev
->hw_features
|= NETIF_F_GSO_GRE
|
4219 NETIF_F_GSO_GRE_CSUM
;
4220 netdev
->hw_enc_features
|= NETIF_F_GSO_GRE
|
4221 NETIF_F_GSO_GRE_CSUM
;
4222 netdev
->gso_partial_features
|= NETIF_F_GSO_GRE
|
4223 NETIF_F_GSO_GRE_CSUM
;
4226 mlx5_query_port_fcs(mdev
, &fcs_supported
, &fcs_enabled
);
4229 netdev
->hw_features
|= NETIF_F_RXALL
;
4231 if (MLX5_CAP_ETH(mdev
, scatter_fcs
))
4232 netdev
->hw_features
|= NETIF_F_RXFCS
;
4234 netdev
->features
= netdev
->hw_features
;
4235 if (!priv
->channels
.params
.lro_en
)
4236 netdev
->features
&= ~NETIF_F_LRO
;
4239 netdev
->features
&= ~NETIF_F_RXALL
;
4241 if (!priv
->channels
.params
.scatter_fcs_en
)
4242 netdev
->features
&= ~NETIF_F_RXFCS
;
4244 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4245 if (FT_CAP(flow_modify_en
) &&
4246 FT_CAP(modify_root
) &&
4247 FT_CAP(identified_miss_table_mode
) &&
4248 FT_CAP(flow_table_modify
)) {
4249 netdev
->hw_features
|= NETIF_F_HW_TC
;
4250 #ifdef CONFIG_RFS_ACCEL
4251 netdev
->hw_features
|= NETIF_F_NTUPLE
;
4255 netdev
->features
|= NETIF_F_HIGHDMA
;
4256 netdev
->features
|= NETIF_F_HW_VLAN_STAG_FILTER
;
4258 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
4260 mlx5e_set_netdev_dev_addr(netdev
);
4262 #if IS_ENABLED(CONFIG_NET_SWITCHDEV) && IS_ENABLED(CONFIG_MLX5_ESWITCH)
4263 if (MLX5_VPORT_MANAGER(mdev
))
4264 netdev
->switchdev_ops
= &mlx5e_switchdev_ops
;
4267 mlx5e_ipsec_build_netdev(priv
);
4270 static void mlx5e_create_q_counter(struct mlx5e_priv
*priv
)
4272 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4275 err
= mlx5_core_alloc_q_counter(mdev
, &priv
->q_counter
);
4277 mlx5_core_warn(mdev
, "alloc queue counter failed, %d\n", err
);
4278 priv
->q_counter
= 0;
4282 static void mlx5e_destroy_q_counter(struct mlx5e_priv
*priv
)
4284 if (!priv
->q_counter
)
4287 mlx5_core_dealloc_q_counter(priv
->mdev
, priv
->q_counter
);
4290 static void mlx5e_nic_init(struct mlx5_core_dev
*mdev
,
4291 struct net_device
*netdev
,
4292 const struct mlx5e_profile
*profile
,
4295 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
4298 mlx5e_build_nic_netdev_priv(mdev
, netdev
, profile
, ppriv
);
4299 err
= mlx5e_ipsec_init(priv
);
4301 mlx5_core_err(mdev
, "IPSec initialization failed, %d\n", err
);
4302 mlx5e_build_nic_netdev(netdev
);
4303 mlx5e_vxlan_init(priv
);
4306 static void mlx5e_nic_cleanup(struct mlx5e_priv
*priv
)
4308 mlx5e_ipsec_cleanup(priv
);
4309 mlx5e_vxlan_cleanup(priv
);
4311 if (priv
->channels
.params
.xdp_prog
)
4312 bpf_prog_put(priv
->channels
.params
.xdp_prog
);
4315 static int mlx5e_init_nic_rx(struct mlx5e_priv
*priv
)
4317 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4320 err
= mlx5e_create_indirect_rqt(priv
);
4324 err
= mlx5e_create_direct_rqts(priv
);
4326 goto err_destroy_indirect_rqts
;
4328 err
= mlx5e_create_indirect_tirs(priv
);
4330 goto err_destroy_direct_rqts
;
4332 err
= mlx5e_create_direct_tirs(priv
);
4334 goto err_destroy_indirect_tirs
;
4336 err
= mlx5e_create_flow_steering(priv
);
4338 mlx5_core_warn(mdev
, "create flow steering failed, %d\n", err
);
4339 goto err_destroy_direct_tirs
;
4342 err
= mlx5e_tc_init(priv
);
4344 goto err_destroy_flow_steering
;
4348 err_destroy_flow_steering
:
4349 mlx5e_destroy_flow_steering(priv
);
4350 err_destroy_direct_tirs
:
4351 mlx5e_destroy_direct_tirs(priv
);
4352 err_destroy_indirect_tirs
:
4353 mlx5e_destroy_indirect_tirs(priv
);
4354 err_destroy_direct_rqts
:
4355 mlx5e_destroy_direct_rqts(priv
);
4356 err_destroy_indirect_rqts
:
4357 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
4361 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv
*priv
)
4363 mlx5e_tc_cleanup(priv
);
4364 mlx5e_destroy_flow_steering(priv
);
4365 mlx5e_destroy_direct_tirs(priv
);
4366 mlx5e_destroy_indirect_tirs(priv
);
4367 mlx5e_destroy_direct_rqts(priv
);
4368 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
4371 static int mlx5e_init_nic_tx(struct mlx5e_priv
*priv
)
4375 err
= mlx5e_create_tises(priv
);
4377 mlx5_core_warn(priv
->mdev
, "create tises failed, %d\n", err
);
4381 #ifdef CONFIG_MLX5_CORE_EN_DCB
4382 mlx5e_dcbnl_initialize(priv
);
4387 static void mlx5e_nic_enable(struct mlx5e_priv
*priv
)
4389 struct net_device
*netdev
= priv
->netdev
;
4390 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4393 mlx5e_init_l2_addr(priv
);
4395 /* Marking the link as currently not needed by the Driver */
4396 if (!netif_running(netdev
))
4397 mlx5_set_port_admin_status(mdev
, MLX5_PORT_DOWN
);
4399 /* MTU range: 68 - hw-specific max */
4400 netdev
->min_mtu
= ETH_MIN_MTU
;
4401 mlx5_query_port_max_mtu(priv
->mdev
, &max_mtu
, 1);
4402 netdev
->max_mtu
= MLX5E_HW2SW_MTU(priv
, max_mtu
);
4403 mlx5e_set_dev_port_mtu(priv
);
4405 mlx5_lag_add(mdev
, netdev
);
4407 mlx5e_enable_async_events(priv
);
4409 if (MLX5_VPORT_MANAGER(priv
->mdev
))
4410 mlx5e_register_vport_reps(priv
);
4412 if (netdev
->reg_state
!= NETREG_REGISTERED
)
4414 #ifdef CONFIG_MLX5_CORE_EN_DCB
4415 mlx5e_dcbnl_init_app(priv
);
4417 /* Device already registered: sync netdev system state */
4418 if (mlx5e_vxlan_allowed(mdev
)) {
4420 udp_tunnel_get_rx_info(netdev
);
4424 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
4427 if (netif_running(netdev
))
4429 netif_device_attach(netdev
);
4433 static void mlx5e_nic_disable(struct mlx5e_priv
*priv
)
4435 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4437 #ifdef CONFIG_MLX5_CORE_EN_DCB
4438 if (priv
->netdev
->reg_state
== NETREG_REGISTERED
)
4439 mlx5e_dcbnl_delete_app(priv
);
4443 if (netif_running(priv
->netdev
))
4444 mlx5e_close(priv
->netdev
);
4445 netif_device_detach(priv
->netdev
);
4448 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
4450 if (MLX5_VPORT_MANAGER(priv
->mdev
))
4451 mlx5e_unregister_vport_reps(priv
);
4453 mlx5e_disable_async_events(priv
);
4454 mlx5_lag_remove(mdev
);
4457 static const struct mlx5e_profile mlx5e_nic_profile
= {
4458 .init
= mlx5e_nic_init
,
4459 .cleanup
= mlx5e_nic_cleanup
,
4460 .init_rx
= mlx5e_init_nic_rx
,
4461 .cleanup_rx
= mlx5e_cleanup_nic_rx
,
4462 .init_tx
= mlx5e_init_nic_tx
,
4463 .cleanup_tx
= mlx5e_cleanup_nic_tx
,
4464 .enable
= mlx5e_nic_enable
,
4465 .disable
= mlx5e_nic_disable
,
4466 .update_stats
= mlx5e_update_ndo_stats
,
4467 .max_nch
= mlx5e_get_max_num_channels
,
4468 .update_carrier
= mlx5e_update_carrier
,
4469 .rx_handlers
.handle_rx_cqe
= mlx5e_handle_rx_cqe
,
4470 .rx_handlers
.handle_rx_cqe_mpwqe
= mlx5e_handle_rx_cqe_mpwrq
,
4471 .max_tc
= MLX5E_MAX_NUM_TC
,
4474 /* mlx5e generic netdev management API (move to en_common.c) */
4476 struct net_device
*mlx5e_create_netdev(struct mlx5_core_dev
*mdev
,
4477 const struct mlx5e_profile
*profile
,
4480 int nch
= profile
->max_nch(mdev
);
4481 struct net_device
*netdev
;
4482 struct mlx5e_priv
*priv
;
4484 netdev
= alloc_etherdev_mqs(sizeof(struct mlx5e_priv
),
4485 nch
* profile
->max_tc
,
4488 mlx5_core_err(mdev
, "alloc_etherdev_mqs() failed\n");
4492 #ifdef CONFIG_RFS_ACCEL
4493 netdev
->rx_cpu_rmap
= mdev
->rmap
;
4496 profile
->init(mdev
, netdev
, profile
, ppriv
);
4498 netif_carrier_off(netdev
);
4500 priv
= netdev_priv(netdev
);
4502 priv
->wq
= create_singlethread_workqueue("mlx5e");
4504 goto err_cleanup_nic
;
4509 if (profile
->cleanup
)
4510 profile
->cleanup(priv
);
4511 free_netdev(netdev
);
4516 int mlx5e_attach_netdev(struct mlx5e_priv
*priv
)
4518 struct mlx5_core_dev
*mdev
= priv
->mdev
;
4519 const struct mlx5e_profile
*profile
;
4522 profile
= priv
->profile
;
4523 clear_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
4525 err
= profile
->init_tx(priv
);
4529 err
= mlx5e_open_drop_rq(mdev
, &priv
->drop_rq
);
4531 mlx5_core_err(mdev
, "open drop rq failed, %d\n", err
);
4532 goto err_cleanup_tx
;
4535 err
= profile
->init_rx(priv
);
4537 goto err_close_drop_rq
;
4539 mlx5e_create_q_counter(priv
);
4541 if (profile
->enable
)
4542 profile
->enable(priv
);
4547 mlx5e_close_drop_rq(&priv
->drop_rq
);
4550 profile
->cleanup_tx(priv
);
4556 void mlx5e_detach_netdev(struct mlx5e_priv
*priv
)
4558 const struct mlx5e_profile
*profile
= priv
->profile
;
4560 set_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
4562 if (profile
->disable
)
4563 profile
->disable(priv
);
4564 flush_workqueue(priv
->wq
);
4566 mlx5e_destroy_q_counter(priv
);
4567 profile
->cleanup_rx(priv
);
4568 mlx5e_close_drop_rq(&priv
->drop_rq
);
4569 profile
->cleanup_tx(priv
);
4570 cancel_delayed_work_sync(&priv
->update_stats_work
);
4573 void mlx5e_destroy_netdev(struct mlx5e_priv
*priv
)
4575 const struct mlx5e_profile
*profile
= priv
->profile
;
4576 struct net_device
*netdev
= priv
->netdev
;
4578 destroy_workqueue(priv
->wq
);
4579 if (profile
->cleanup
)
4580 profile
->cleanup(priv
);
4581 free_netdev(netdev
);
4584 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
4585 * hardware contexts and to connect it to the current netdev.
4587 static int mlx5e_attach(struct mlx5_core_dev
*mdev
, void *vpriv
)
4589 struct mlx5e_priv
*priv
= vpriv
;
4590 struct net_device
*netdev
= priv
->netdev
;
4593 if (netif_device_present(netdev
))
4596 err
= mlx5e_create_mdev_resources(mdev
);
4600 err
= mlx5e_attach_netdev(priv
);
4602 mlx5e_destroy_mdev_resources(mdev
);
4609 static void mlx5e_detach(struct mlx5_core_dev
*mdev
, void *vpriv
)
4611 struct mlx5e_priv
*priv
= vpriv
;
4612 struct net_device
*netdev
= priv
->netdev
;
4614 if (!netif_device_present(netdev
))
4617 mlx5e_detach_netdev(priv
);
4618 mlx5e_destroy_mdev_resources(mdev
);
4621 static void *mlx5e_add(struct mlx5_core_dev
*mdev
)
4623 struct net_device
*netdev
;
4628 err
= mlx5e_check_required_hca_cap(mdev
);
4632 #ifdef CONFIG_MLX5_ESWITCH
4633 if (MLX5_VPORT_MANAGER(mdev
)) {
4634 rpriv
= mlx5e_alloc_nic_rep_priv(mdev
);
4636 mlx5_core_warn(mdev
, "Failed to alloc NIC rep priv data\n");
4642 netdev
= mlx5e_create_netdev(mdev
, &mlx5e_nic_profile
, rpriv
);
4644 mlx5_core_err(mdev
, "mlx5e_create_netdev failed\n");
4645 goto err_free_rpriv
;
4648 priv
= netdev_priv(netdev
);
4650 err
= mlx5e_attach(mdev
, priv
);
4652 mlx5_core_err(mdev
, "mlx5e_attach failed, %d\n", err
);
4653 goto err_destroy_netdev
;
4656 err
= register_netdev(netdev
);
4658 mlx5_core_err(mdev
, "register_netdev failed, %d\n", err
);
4662 #ifdef CONFIG_MLX5_CORE_EN_DCB
4663 mlx5e_dcbnl_init_app(priv
);
4668 mlx5e_detach(mdev
, priv
);
4670 mlx5e_destroy_netdev(priv
);
4676 static void mlx5e_remove(struct mlx5_core_dev
*mdev
, void *vpriv
)
4678 struct mlx5e_priv
*priv
= vpriv
;
4679 void *ppriv
= priv
->ppriv
;
4681 #ifdef CONFIG_MLX5_CORE_EN_DCB
4682 mlx5e_dcbnl_delete_app(priv
);
4684 unregister_netdev(priv
->netdev
);
4685 mlx5e_detach(mdev
, vpriv
);
4686 mlx5e_destroy_netdev(priv
);
4690 static void *mlx5e_get_netdev(void *vpriv
)
4692 struct mlx5e_priv
*priv
= vpriv
;
4694 return priv
->netdev
;
4697 static struct mlx5_interface mlx5e_interface
= {
4699 .remove
= mlx5e_remove
,
4700 .attach
= mlx5e_attach
,
4701 .detach
= mlx5e_detach
,
4702 .event
= mlx5e_async_event
,
4703 .protocol
= MLX5_INTERFACE_PROTOCOL_ETH
,
4704 .get_dev
= mlx5e_get_netdev
,
4707 void mlx5e_init(void)
4709 mlx5e_ipsec_build_inverse_table();
4710 mlx5e_build_ptys2ethtool_map();
4711 mlx5_register_interface(&mlx5e_interface
);
4714 void mlx5e_cleanup(void)
4716 mlx5_unregister_interface(&mlx5e_interface
);