2 * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <net/tc_act/tc_gact.h>
34 #include <linux/crash_dump.h>
35 #include <net/pkt_cls.h>
36 #include <linux/mlx5/fs.h>
37 #include <net/vxlan.h>
38 #include <linux/bpf.h>
44 struct mlx5e_rq_param
{
45 u32 rqc
[MLX5_ST_SZ_DW(rqc
)];
46 struct mlx5_wq_param wq
;
50 struct mlx5e_sq_param
{
51 u32 sqc
[MLX5_ST_SZ_DW(sqc
)];
52 struct mlx5_wq_param wq
;
55 enum mlx5e_sq_type type
;
58 struct mlx5e_cq_param
{
59 u32 cqc
[MLX5_ST_SZ_DW(cqc
)];
60 struct mlx5_wq_param wq
;
65 struct mlx5e_channel_param
{
66 struct mlx5e_rq_param rq
;
67 struct mlx5e_sq_param sq
;
68 struct mlx5e_sq_param xdp_sq
;
69 struct mlx5e_sq_param icosq
;
70 struct mlx5e_cq_param rx_cq
;
71 struct mlx5e_cq_param tx_cq
;
72 struct mlx5e_cq_param icosq_cq
;
75 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev
*mdev
)
77 return MLX5_CAP_GEN(mdev
, striding_rq
) &&
78 MLX5_CAP_GEN(mdev
, umr_ptr_rlky
) &&
79 MLX5_CAP_ETH(mdev
, reg_umr_sq
);
82 void mlx5e_set_rq_type_params(struct mlx5e_priv
*priv
, u8 rq_type
)
84 priv
->params
.rq_wq_type
= rq_type
;
85 priv
->params
.lro_wqe_sz
= MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ
;
86 switch (priv
->params
.rq_wq_type
) {
87 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
88 priv
->params
.log_rq_size
= is_kdump_kernel() ?
89 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW
:
90 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW
;
91 priv
->params
.mpwqe_log_stride_sz
=
92 MLX5E_GET_PFLAG(priv
, MLX5E_PFLAG_RX_CQE_COMPRESS
) ?
93 MLX5_MPWRQ_CQE_CMPRS_LOG_STRIDE_SZ(priv
->mdev
) :
94 MLX5_MPWRQ_DEF_LOG_STRIDE_SZ(priv
->mdev
);
95 priv
->params
.mpwqe_log_num_strides
= MLX5_MPWRQ_LOG_WQE_SZ
-
96 priv
->params
.mpwqe_log_stride_sz
;
98 default: /* MLX5_WQ_TYPE_LINKED_LIST */
99 priv
->params
.log_rq_size
= is_kdump_kernel() ?
100 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE
:
101 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE
;
103 /* Extra room needed for build_skb */
104 priv
->params
.lro_wqe_sz
-= MLX5_RX_HEADROOM
+
105 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
107 priv
->params
.min_rx_wqes
= mlx5_min_rx_wqes(priv
->params
.rq_wq_type
,
108 BIT(priv
->params
.log_rq_size
));
110 mlx5_core_info(priv
->mdev
,
111 "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
112 priv
->params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
,
113 BIT(priv
->params
.log_rq_size
),
114 BIT(priv
->params
.mpwqe_log_stride_sz
),
115 MLX5E_GET_PFLAG(priv
, MLX5E_PFLAG_RX_CQE_COMPRESS
));
118 static void mlx5e_set_rq_priv_params(struct mlx5e_priv
*priv
)
120 u8 rq_type
= mlx5e_check_fragmented_striding_rq_cap(priv
->mdev
) &&
122 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
123 MLX5_WQ_TYPE_LINKED_LIST
;
124 mlx5e_set_rq_type_params(priv
, rq_type
);
127 static void mlx5e_update_carrier(struct mlx5e_priv
*priv
)
129 struct mlx5_core_dev
*mdev
= priv
->mdev
;
132 port_state
= mlx5_query_vport_state(mdev
,
133 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT
, 0);
135 if (port_state
== VPORT_STATE_UP
) {
136 netdev_info(priv
->netdev
, "Link up\n");
137 netif_carrier_on(priv
->netdev
);
139 netdev_info(priv
->netdev
, "Link down\n");
140 netif_carrier_off(priv
->netdev
);
144 static void mlx5e_update_carrier_work(struct work_struct
*work
)
146 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
147 update_carrier_work
);
149 mutex_lock(&priv
->state_lock
);
150 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
151 mlx5e_update_carrier(priv
);
152 mutex_unlock(&priv
->state_lock
);
155 static void mlx5e_tx_timeout_work(struct work_struct
*work
)
157 struct mlx5e_priv
*priv
= container_of(work
, struct mlx5e_priv
,
162 mutex_lock(&priv
->state_lock
);
163 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
165 mlx5e_close_locked(priv
->netdev
);
166 err
= mlx5e_open_locked(priv
->netdev
);
168 netdev_err(priv
->netdev
, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
171 mutex_unlock(&priv
->state_lock
);
175 static void mlx5e_update_sw_counters(struct mlx5e_priv
*priv
)
177 struct mlx5e_sw_stats
*s
= &priv
->stats
.sw
;
178 struct mlx5e_rq_stats
*rq_stats
;
179 struct mlx5e_sq_stats
*sq_stats
;
180 u64 tx_offload_none
= 0;
183 memset(s
, 0, sizeof(*s
));
184 for (i
= 0; i
< priv
->params
.num_channels
; i
++) {
185 rq_stats
= &priv
->channel
[i
]->rq
.stats
;
187 s
->rx_packets
+= rq_stats
->packets
;
188 s
->rx_bytes
+= rq_stats
->bytes
;
189 s
->rx_lro_packets
+= rq_stats
->lro_packets
;
190 s
->rx_lro_bytes
+= rq_stats
->lro_bytes
;
191 s
->rx_csum_none
+= rq_stats
->csum_none
;
192 s
->rx_csum_complete
+= rq_stats
->csum_complete
;
193 s
->rx_csum_unnecessary_inner
+= rq_stats
->csum_unnecessary_inner
;
194 s
->rx_xdp_drop
+= rq_stats
->xdp_drop
;
195 s
->rx_xdp_tx
+= rq_stats
->xdp_tx
;
196 s
->rx_xdp_tx_full
+= rq_stats
->xdp_tx_full
;
197 s
->rx_wqe_err
+= rq_stats
->wqe_err
;
198 s
->rx_mpwqe_filler
+= rq_stats
->mpwqe_filler
;
199 s
->rx_buff_alloc_err
+= rq_stats
->buff_alloc_err
;
200 s
->rx_cqe_compress_blks
+= rq_stats
->cqe_compress_blks
;
201 s
->rx_cqe_compress_pkts
+= rq_stats
->cqe_compress_pkts
;
202 s
->rx_cache_reuse
+= rq_stats
->cache_reuse
;
203 s
->rx_cache_full
+= rq_stats
->cache_full
;
204 s
->rx_cache_empty
+= rq_stats
->cache_empty
;
205 s
->rx_cache_busy
+= rq_stats
->cache_busy
;
207 for (j
= 0; j
< priv
->params
.num_tc
; j
++) {
208 sq_stats
= &priv
->channel
[i
]->sq
[j
].stats
;
210 s
->tx_packets
+= sq_stats
->packets
;
211 s
->tx_bytes
+= sq_stats
->bytes
;
212 s
->tx_tso_packets
+= sq_stats
->tso_packets
;
213 s
->tx_tso_bytes
+= sq_stats
->tso_bytes
;
214 s
->tx_tso_inner_packets
+= sq_stats
->tso_inner_packets
;
215 s
->tx_tso_inner_bytes
+= sq_stats
->tso_inner_bytes
;
216 s
->tx_queue_stopped
+= sq_stats
->stopped
;
217 s
->tx_queue_wake
+= sq_stats
->wake
;
218 s
->tx_queue_dropped
+= sq_stats
->dropped
;
219 s
->tx_xmit_more
+= sq_stats
->xmit_more
;
220 s
->tx_csum_partial_inner
+= sq_stats
->csum_partial_inner
;
221 tx_offload_none
+= sq_stats
->csum_none
;
225 /* Update calculated offload counters */
226 s
->tx_csum_partial
= s
->tx_packets
- tx_offload_none
- s
->tx_csum_partial_inner
;
227 s
->rx_csum_unnecessary
= s
->rx_packets
- s
->rx_csum_none
- s
->rx_csum_complete
;
229 s
->link_down_events_phy
= MLX5_GET(ppcnt_reg
,
230 priv
->stats
.pport
.phy_counters
,
231 counter_set
.phys_layer_cntrs
.link_down_events
);
234 static void mlx5e_update_vport_counters(struct mlx5e_priv
*priv
)
236 int outlen
= MLX5_ST_SZ_BYTES(query_vport_counter_out
);
237 u32
*out
= (u32
*)priv
->stats
.vport
.query_vport_out
;
238 u32 in
[MLX5_ST_SZ_DW(query_vport_counter_in
)] = {0};
239 struct mlx5_core_dev
*mdev
= priv
->mdev
;
241 MLX5_SET(query_vport_counter_in
, in
, opcode
,
242 MLX5_CMD_OP_QUERY_VPORT_COUNTER
);
243 MLX5_SET(query_vport_counter_in
, in
, op_mod
, 0);
244 MLX5_SET(query_vport_counter_in
, in
, other_vport
, 0);
246 memset(out
, 0, outlen
);
247 mlx5_cmd_exec(mdev
, in
, sizeof(in
), out
, outlen
);
250 static void mlx5e_update_pport_counters(struct mlx5e_priv
*priv
)
252 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
253 struct mlx5_core_dev
*mdev
= priv
->mdev
;
254 int sz
= MLX5_ST_SZ_BYTES(ppcnt_reg
);
259 in
= mlx5_vzalloc(sz
);
263 MLX5_SET(ppcnt_reg
, in
, local_port
, 1);
265 out
= pstats
->IEEE_802_3_counters
;
266 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_IEEE_802_3_COUNTERS_GROUP
);
267 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
269 out
= pstats
->RFC_2863_counters
;
270 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2863_COUNTERS_GROUP
);
271 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
273 out
= pstats
->RFC_2819_counters
;
274 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_RFC_2819_COUNTERS_GROUP
);
275 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
277 out
= pstats
->phy_counters
;
278 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP
);
279 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
281 if (MLX5_CAP_PCAM_FEATURE(mdev
, ppcnt_statistical_group
)) {
282 out
= pstats
->phy_statistical_counters
;
283 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP
);
284 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_PPCNT
, 0, 0);
287 MLX5_SET(ppcnt_reg
, in
, grp
, MLX5_PER_PRIORITY_COUNTERS_GROUP
);
288 for (prio
= 0; prio
< NUM_PPORT_PRIO
; prio
++) {
289 out
= pstats
->per_prio_counters
[prio
];
290 MLX5_SET(ppcnt_reg
, in
, prio_tc
, prio
);
291 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
,
292 MLX5_REG_PPCNT
, 0, 0);
299 static void mlx5e_update_q_counter(struct mlx5e_priv
*priv
)
301 struct mlx5e_qcounter_stats
*qcnt
= &priv
->stats
.qcnt
;
303 if (!priv
->q_counter
)
306 mlx5_core_query_out_of_buffer(priv
->mdev
, priv
->q_counter
,
307 &qcnt
->rx_out_of_buffer
);
310 static void mlx5e_update_pcie_counters(struct mlx5e_priv
*priv
)
312 struct mlx5e_pcie_stats
*pcie_stats
= &priv
->stats
.pcie
;
313 struct mlx5_core_dev
*mdev
= priv
->mdev
;
314 int sz
= MLX5_ST_SZ_BYTES(mpcnt_reg
);
318 if (!MLX5_CAP_MCAM_FEATURE(mdev
, pcie_performance_group
))
321 in
= mlx5_vzalloc(sz
);
325 out
= pcie_stats
->pcie_perf_counters
;
326 MLX5_SET(mpcnt_reg
, in
, grp
, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP
);
327 mlx5_core_access_reg(mdev
, in
, sz
, out
, sz
, MLX5_REG_MPCNT
, 0, 0);
332 void mlx5e_update_stats(struct mlx5e_priv
*priv
)
334 mlx5e_update_pcie_counters(priv
);
335 mlx5e_update_pport_counters(priv
);
336 mlx5e_update_vport_counters(priv
);
337 mlx5e_update_q_counter(priv
);
338 mlx5e_update_sw_counters(priv
);
341 void mlx5e_update_stats_work(struct work_struct
*work
)
343 struct delayed_work
*dwork
= to_delayed_work(work
);
344 struct mlx5e_priv
*priv
= container_of(dwork
, struct mlx5e_priv
,
346 mutex_lock(&priv
->state_lock
);
347 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
)) {
348 priv
->profile
->update_stats(priv
);
349 queue_delayed_work(priv
->wq
, dwork
,
350 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL
));
352 mutex_unlock(&priv
->state_lock
);
355 static void mlx5e_async_event(struct mlx5_core_dev
*mdev
, void *vpriv
,
356 enum mlx5_dev_event event
, unsigned long param
)
358 struct mlx5e_priv
*priv
= vpriv
;
359 struct ptp_clock_event ptp_event
;
360 struct mlx5_eqe
*eqe
= NULL
;
362 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
))
366 case MLX5_DEV_EVENT_PORT_UP
:
367 case MLX5_DEV_EVENT_PORT_DOWN
:
368 queue_work(priv
->wq
, &priv
->update_carrier_work
);
370 case MLX5_DEV_EVENT_PPS
:
371 eqe
= (struct mlx5_eqe
*)param
;
372 ptp_event
.type
= PTP_CLOCK_EXTTS
;
373 ptp_event
.index
= eqe
->data
.pps
.pin
;
374 ptp_event
.timestamp
=
375 timecounter_cyc2time(&priv
->tstamp
.clock
,
376 be64_to_cpu(eqe
->data
.pps
.time_stamp
));
377 mlx5e_pps_event_handler(vpriv
, &ptp_event
);
384 static void mlx5e_enable_async_events(struct mlx5e_priv
*priv
)
386 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
389 static void mlx5e_disable_async_events(struct mlx5e_priv
*priv
)
391 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED
, &priv
->state
);
392 synchronize_irq(mlx5_get_msix_vec(priv
->mdev
, MLX5_EQ_VEC_ASYNC
));
395 static inline int mlx5e_get_wqe_mtt_sz(void)
397 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
398 * To avoid copying garbage after the mtt array, we allocate
401 return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE
* sizeof(__be64
),
402 MLX5_UMR_MTT_ALIGNMENT
);
405 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq
*rq
, struct mlx5e_sq
*sq
,
406 struct mlx5e_umr_wqe
*wqe
, u16 ix
)
408 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
409 struct mlx5_wqe_umr_ctrl_seg
*ucseg
= &wqe
->uctrl
;
410 struct mlx5_wqe_data_seg
*dseg
= &wqe
->data
;
411 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
412 u8 ds_cnt
= DIV_ROUND_UP(sizeof(*wqe
), MLX5_SEND_WQE_DS
);
413 u32 umr_wqe_mtt_offset
= mlx5e_get_wqe_mtt_offset(rq
, ix
);
415 cseg
->qpn_ds
= cpu_to_be32((sq
->sqn
<< MLX5_WQE_CTRL_QPN_SHIFT
) |
417 cseg
->fm_ce_se
= MLX5_WQE_CTRL_CQ_UPDATE
;
418 cseg
->imm
= rq
->mkey_be
;
420 ucseg
->flags
= MLX5_UMR_TRANSLATION_OFFSET_EN
;
421 ucseg
->xlt_octowords
=
422 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE
));
423 ucseg
->bsf_octowords
=
424 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset
));
425 ucseg
->mkey_mask
= cpu_to_be64(MLX5_MKEY_MASK_FREE
);
427 dseg
->lkey
= sq
->mkey_be
;
428 dseg
->addr
= cpu_to_be64(wi
->umr
.mtt_addr
);
431 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq
*rq
,
432 struct mlx5e_channel
*c
)
434 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
435 int mtt_sz
= mlx5e_get_wqe_mtt_sz();
436 int mtt_alloc
= mtt_sz
+ MLX5_UMR_ALIGN
- 1;
439 rq
->mpwqe
.info
= kzalloc_node(wq_sz
* sizeof(*rq
->mpwqe
.info
),
440 GFP_KERNEL
, cpu_to_node(c
->cpu
));
444 /* We allocate more than mtt_sz as we will align the pointer */
445 rq
->mpwqe
.mtt_no_align
= kzalloc_node(mtt_alloc
* wq_sz
, GFP_KERNEL
,
446 cpu_to_node(c
->cpu
));
447 if (unlikely(!rq
->mpwqe
.mtt_no_align
))
448 goto err_free_wqe_info
;
450 for (i
= 0; i
< wq_sz
; i
++) {
451 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
453 wi
->umr
.mtt
= PTR_ALIGN(rq
->mpwqe
.mtt_no_align
+ i
* mtt_alloc
,
455 wi
->umr
.mtt_addr
= dma_map_single(c
->pdev
, wi
->umr
.mtt
, mtt_sz
,
457 if (unlikely(dma_mapping_error(c
->pdev
, wi
->umr
.mtt_addr
)))
460 mlx5e_build_umr_wqe(rq
, &c
->icosq
, &wi
->umr
.wqe
, i
);
467 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
469 dma_unmap_single(c
->pdev
, wi
->umr
.mtt_addr
, mtt_sz
,
472 kfree(rq
->mpwqe
.mtt_no_align
);
474 kfree(rq
->mpwqe
.info
);
480 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq
*rq
)
482 int wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
483 int mtt_sz
= mlx5e_get_wqe_mtt_sz();
486 for (i
= 0; i
< wq_sz
; i
++) {
487 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[i
];
489 dma_unmap_single(rq
->pdev
, wi
->umr
.mtt_addr
, mtt_sz
,
492 kfree(rq
->mpwqe
.mtt_no_align
);
493 kfree(rq
->mpwqe
.info
);
496 static int mlx5e_create_umr_mkey(struct mlx5e_priv
*priv
,
497 u64 npages
, u8 page_shift
,
498 struct mlx5_core_mkey
*umr_mkey
)
500 struct mlx5_core_dev
*mdev
= priv
->mdev
;
501 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
506 if (!MLX5E_VALID_NUM_MTTS(npages
))
509 in
= mlx5_vzalloc(inlen
);
513 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
515 MLX5_SET(mkc
, mkc
, free
, 1);
516 MLX5_SET(mkc
, mkc
, umr_en
, 1);
517 MLX5_SET(mkc
, mkc
, lw
, 1);
518 MLX5_SET(mkc
, mkc
, lr
, 1);
519 MLX5_SET(mkc
, mkc
, access_mode
, MLX5_MKC_ACCESS_MODE_MTT
);
521 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
522 MLX5_SET(mkc
, mkc
, pd
, mdev
->mlx5e_res
.pdn
);
523 MLX5_SET64(mkc
, mkc
, len
, npages
<< page_shift
);
524 MLX5_SET(mkc
, mkc
, translations_octword_size
,
525 MLX5_MTT_OCTW(npages
));
526 MLX5_SET(mkc
, mkc
, log_page_size
, page_shift
);
528 err
= mlx5_core_create_mkey(mdev
, umr_mkey
, in
, inlen
);
534 static int mlx5e_create_rq_umr_mkey(struct mlx5e_rq
*rq
)
536 struct mlx5e_priv
*priv
= rq
->priv
;
537 u64 num_mtts
= MLX5E_REQUIRED_MTTS(BIT(priv
->params
.log_rq_size
));
539 return mlx5e_create_umr_mkey(priv
, num_mtts
, PAGE_SHIFT
, &rq
->umr_mkey
);
542 static int mlx5e_create_rq(struct mlx5e_channel
*c
,
543 struct mlx5e_rq_param
*param
,
546 struct mlx5e_priv
*priv
= c
->priv
;
547 struct mlx5_core_dev
*mdev
= priv
->mdev
;
548 void *rqc
= param
->rqc
;
549 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
557 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
559 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
564 rq
->wq
.db
= &rq
->wq
.db
[MLX5_RCV_DBR
];
566 wq_sz
= mlx5_wq_ll_get_size(&rq
->wq
);
568 rq
->wq_type
= priv
->params
.rq_wq_type
;
570 rq
->netdev
= c
->netdev
;
571 rq
->tstamp
= &priv
->tstamp
;
576 rq
->xdp_prog
= priv
->xdp_prog
? bpf_prog_inc(priv
->xdp_prog
) : NULL
;
577 if (IS_ERR(rq
->xdp_prog
)) {
578 err
= PTR_ERR(rq
->xdp_prog
);
580 goto err_rq_wq_destroy
;
584 rq
->buff
.map_dir
= DMA_BIDIRECTIONAL
;
585 rq
->rx_headroom
= XDP_PACKET_HEADROOM
;
587 rq
->buff
.map_dir
= DMA_FROM_DEVICE
;
588 rq
->rx_headroom
= MLX5_RX_HEADROOM
;
591 switch (priv
->params
.rq_wq_type
) {
592 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
593 if (mlx5e_is_vf_vport_rep(priv
)) {
595 goto err_rq_wq_destroy
;
598 rq
->handle_rx_cqe
= mlx5e_handle_rx_cqe_mpwrq
;
599 rq
->alloc_wqe
= mlx5e_alloc_rx_mpwqe
;
600 rq
->dealloc_wqe
= mlx5e_dealloc_rx_mpwqe
;
602 rq
->mpwqe_stride_sz
= BIT(priv
->params
.mpwqe_log_stride_sz
);
603 rq
->mpwqe_num_strides
= BIT(priv
->params
.mpwqe_log_num_strides
);
605 rq
->buff
.wqe_sz
= rq
->mpwqe_stride_sz
* rq
->mpwqe_num_strides
;
606 byte_count
= rq
->buff
.wqe_sz
;
608 err
= mlx5e_create_rq_umr_mkey(rq
);
610 goto err_rq_wq_destroy
;
611 rq
->mkey_be
= cpu_to_be32(rq
->umr_mkey
.key
);
613 err
= mlx5e_rq_alloc_mpwqe_info(rq
, c
);
615 goto err_destroy_umr_mkey
;
617 default: /* MLX5_WQ_TYPE_LINKED_LIST */
618 rq
->dma_info
= kzalloc_node(wq_sz
* sizeof(*rq
->dma_info
),
619 GFP_KERNEL
, cpu_to_node(c
->cpu
));
622 goto err_rq_wq_destroy
;
625 if (mlx5e_is_vf_vport_rep(priv
))
626 rq
->handle_rx_cqe
= mlx5e_handle_rx_cqe_rep
;
628 rq
->handle_rx_cqe
= mlx5e_handle_rx_cqe
;
630 rq
->alloc_wqe
= mlx5e_alloc_rx_wqe
;
631 rq
->dealloc_wqe
= mlx5e_dealloc_rx_wqe
;
633 rq
->buff
.wqe_sz
= (priv
->params
.lro_en
) ?
634 priv
->params
.lro_wqe_sz
:
635 MLX5E_SW2HW_MTU(priv
->netdev
->mtu
);
636 byte_count
= rq
->buff
.wqe_sz
;
638 /* calc the required page order */
639 frag_sz
= rq
->rx_headroom
+
640 byte_count
/* packet data */ +
641 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
642 frag_sz
= SKB_DATA_ALIGN(frag_sz
);
644 npages
= DIV_ROUND_UP(frag_sz
, PAGE_SIZE
);
645 rq
->buff
.page_order
= order_base_2(npages
);
647 byte_count
|= MLX5_HW_START_PADDING
;
648 rq
->mkey_be
= c
->mkey_be
;
651 for (i
= 0; i
< wq_sz
; i
++) {
652 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, i
);
654 wqe
->data
.byte_count
= cpu_to_be32(byte_count
);
655 wqe
->data
.lkey
= rq
->mkey_be
;
658 INIT_WORK(&rq
->am
.work
, mlx5e_rx_am_work
);
659 rq
->am
.mode
= priv
->params
.rx_cq_period_mode
;
661 rq
->page_cache
.head
= 0;
662 rq
->page_cache
.tail
= 0;
666 err_destroy_umr_mkey
:
667 mlx5_core_destroy_mkey(mdev
, &rq
->umr_mkey
);
671 bpf_prog_put(rq
->xdp_prog
);
672 mlx5_wq_destroy(&rq
->wq_ctrl
);
677 static void mlx5e_destroy_rq(struct mlx5e_rq
*rq
)
682 bpf_prog_put(rq
->xdp_prog
);
684 switch (rq
->wq_type
) {
685 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
686 mlx5e_rq_free_mpwqe_info(rq
);
687 mlx5_core_destroy_mkey(rq
->priv
->mdev
, &rq
->umr_mkey
);
689 default: /* MLX5_WQ_TYPE_LINKED_LIST */
693 for (i
= rq
->page_cache
.head
; i
!= rq
->page_cache
.tail
;
694 i
= (i
+ 1) & (MLX5E_CACHE_SIZE
- 1)) {
695 struct mlx5e_dma_info
*dma_info
= &rq
->page_cache
.page_cache
[i
];
697 mlx5e_page_release(rq
, dma_info
, false);
699 mlx5_wq_destroy(&rq
->wq_ctrl
);
702 static int mlx5e_enable_rq(struct mlx5e_rq
*rq
, struct mlx5e_rq_param
*param
)
704 struct mlx5e_priv
*priv
= rq
->priv
;
705 struct mlx5_core_dev
*mdev
= priv
->mdev
;
713 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) +
714 sizeof(u64
) * rq
->wq_ctrl
.buf
.npages
;
715 in
= mlx5_vzalloc(inlen
);
719 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
720 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
722 memcpy(rqc
, param
->rqc
, sizeof(param
->rqc
));
724 MLX5_SET(rqc
, rqc
, cqn
, rq
->cq
.mcq
.cqn
);
725 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
726 MLX5_SET(rqc
, rqc
, vsd
, priv
->params
.vlan_strip_disable
);
727 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rq
->wq_ctrl
.buf
.page_shift
-
728 MLX5_ADAPTER_PAGE_SHIFT
);
729 MLX5_SET64(wq
, wq
, dbr_addr
, rq
->wq_ctrl
.db
.dma
);
731 mlx5_fill_page_array(&rq
->wq_ctrl
.buf
,
732 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
734 err
= mlx5_core_create_rq(mdev
, in
, inlen
, &rq
->rqn
);
741 static int mlx5e_modify_rq_state(struct mlx5e_rq
*rq
, int curr_state
,
744 struct mlx5e_channel
*c
= rq
->channel
;
745 struct mlx5e_priv
*priv
= c
->priv
;
746 struct mlx5_core_dev
*mdev
= priv
->mdev
;
753 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
754 in
= mlx5_vzalloc(inlen
);
758 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
760 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_state
);
761 MLX5_SET(rqc
, rqc
, state
, next_state
);
763 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
770 static int mlx5e_modify_rq_vsd(struct mlx5e_rq
*rq
, bool vsd
)
772 struct mlx5e_channel
*c
= rq
->channel
;
773 struct mlx5e_priv
*priv
= c
->priv
;
774 struct mlx5_core_dev
*mdev
= priv
->mdev
;
781 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
782 in
= mlx5_vzalloc(inlen
);
786 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
788 MLX5_SET(modify_rq_in
, in
, rq_state
, MLX5_RQC_STATE_RDY
);
789 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
790 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD
);
791 MLX5_SET(rqc
, rqc
, vsd
, vsd
);
792 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RDY
);
794 err
= mlx5_core_modify_rq(mdev
, rq
->rqn
, in
, inlen
);
801 static void mlx5e_disable_rq(struct mlx5e_rq
*rq
)
803 mlx5_core_destroy_rq(rq
->priv
->mdev
, rq
->rqn
);
806 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq
*rq
)
808 unsigned long exp_time
= jiffies
+ msecs_to_jiffies(20000);
809 struct mlx5e_channel
*c
= rq
->channel
;
810 struct mlx5e_priv
*priv
= c
->priv
;
811 struct mlx5_wq_ll
*wq
= &rq
->wq
;
813 while (time_before(jiffies
, exp_time
)) {
814 if (wq
->cur_sz
>= priv
->params
.min_rx_wqes
)
823 static void mlx5e_free_rx_descs(struct mlx5e_rq
*rq
)
825 struct mlx5_wq_ll
*wq
= &rq
->wq
;
826 struct mlx5e_rx_wqe
*wqe
;
830 /* UMR WQE (if in progress) is always at wq->head */
831 if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS
, &rq
->state
))
832 mlx5e_free_rx_mpwqe(rq
, &rq
->mpwqe
.info
[wq
->head
]);
834 while (!mlx5_wq_ll_is_empty(wq
)) {
835 wqe_ix_be
= *wq
->tail_next
;
836 wqe_ix
= be16_to_cpu(wqe_ix_be
);
837 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_ix
);
838 rq
->dealloc_wqe(rq
, wqe_ix
);
839 mlx5_wq_ll_pop(&rq
->wq
, wqe_ix_be
,
840 &wqe
->next
.next_wqe_index
);
844 static int mlx5e_open_rq(struct mlx5e_channel
*c
,
845 struct mlx5e_rq_param
*param
,
848 struct mlx5e_sq
*sq
= &c
->icosq
;
849 u16 pi
= sq
->pc
& sq
->wq
.sz_m1
;
852 err
= mlx5e_create_rq(c
, param
, rq
);
856 err
= mlx5e_enable_rq(rq
, param
);
860 set_bit(MLX5E_RQ_STATE_ENABLED
, &rq
->state
);
861 err
= mlx5e_modify_rq_state(rq
, MLX5_RQC_STATE_RST
, MLX5_RQC_STATE_RDY
);
865 if (param
->am_enabled
)
866 set_bit(MLX5E_RQ_STATE_AM
, &c
->rq
.state
);
868 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_NOP
;
869 sq
->db
.ico_wqe
[pi
].num_wqebbs
= 1;
870 mlx5e_send_nop(sq
, true); /* trigger mlx5e_post_rx_wqes() */
875 clear_bit(MLX5E_RQ_STATE_ENABLED
, &rq
->state
);
876 mlx5e_disable_rq(rq
);
878 mlx5e_destroy_rq(rq
);
883 static void mlx5e_close_rq(struct mlx5e_rq
*rq
)
885 clear_bit(MLX5E_RQ_STATE_ENABLED
, &rq
->state
);
886 napi_synchronize(&rq
->channel
->napi
); /* prevent mlx5e_post_rx_wqes */
887 cancel_work_sync(&rq
->am
.work
);
889 mlx5e_disable_rq(rq
);
890 mlx5e_free_rx_descs(rq
);
891 mlx5e_destroy_rq(rq
);
894 static void mlx5e_free_sq_xdp_db(struct mlx5e_sq
*sq
)
896 kfree(sq
->db
.xdp
.di
);
897 kfree(sq
->db
.xdp
.wqe_info
);
900 static int mlx5e_alloc_sq_xdp_db(struct mlx5e_sq
*sq
, int numa
)
902 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
904 sq
->db
.xdp
.di
= kzalloc_node(sizeof(*sq
->db
.xdp
.di
) * wq_sz
,
906 sq
->db
.xdp
.wqe_info
= kzalloc_node(sizeof(*sq
->db
.xdp
.wqe_info
) * wq_sz
,
908 if (!sq
->db
.xdp
.di
|| !sq
->db
.xdp
.wqe_info
) {
909 mlx5e_free_sq_xdp_db(sq
);
916 static void mlx5e_free_sq_ico_db(struct mlx5e_sq
*sq
)
918 kfree(sq
->db
.ico_wqe
);
921 static int mlx5e_alloc_sq_ico_db(struct mlx5e_sq
*sq
, int numa
)
923 u8 wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
925 sq
->db
.ico_wqe
= kzalloc_node(sizeof(*sq
->db
.ico_wqe
) * wq_sz
,
933 static void mlx5e_free_sq_txq_db(struct mlx5e_sq
*sq
)
935 kfree(sq
->db
.txq
.wqe_info
);
936 kfree(sq
->db
.txq
.dma_fifo
);
937 kfree(sq
->db
.txq
.skb
);
940 static int mlx5e_alloc_sq_txq_db(struct mlx5e_sq
*sq
, int numa
)
942 int wq_sz
= mlx5_wq_cyc_get_size(&sq
->wq
);
943 int df_sz
= wq_sz
* MLX5_SEND_WQEBB_NUM_DS
;
945 sq
->db
.txq
.skb
= kzalloc_node(wq_sz
* sizeof(*sq
->db
.txq
.skb
),
947 sq
->db
.txq
.dma_fifo
= kzalloc_node(df_sz
* sizeof(*sq
->db
.txq
.dma_fifo
),
949 sq
->db
.txq
.wqe_info
= kzalloc_node(wq_sz
* sizeof(*sq
->db
.txq
.wqe_info
),
951 if (!sq
->db
.txq
.skb
|| !sq
->db
.txq
.dma_fifo
|| !sq
->db
.txq
.wqe_info
) {
952 mlx5e_free_sq_txq_db(sq
);
956 sq
->dma_fifo_mask
= df_sz
- 1;
961 static void mlx5e_free_sq_db(struct mlx5e_sq
*sq
)
965 mlx5e_free_sq_txq_db(sq
);
968 mlx5e_free_sq_ico_db(sq
);
971 mlx5e_free_sq_xdp_db(sq
);
976 static int mlx5e_alloc_sq_db(struct mlx5e_sq
*sq
, int numa
)
980 return mlx5e_alloc_sq_txq_db(sq
, numa
);
982 return mlx5e_alloc_sq_ico_db(sq
, numa
);
984 return mlx5e_alloc_sq_xdp_db(sq
, numa
);
990 static int mlx5e_sq_get_max_wqebbs(u8 sq_type
)
994 return MLX5E_ICOSQ_MAX_WQEBBS
;
996 return MLX5E_XDP_TX_WQEBBS
;
998 return MLX5_SEND_WQE_MAX_WQEBBS
;
1001 static int mlx5e_create_sq(struct mlx5e_channel
*c
,
1003 struct mlx5e_sq_param
*param
,
1004 struct mlx5e_sq
*sq
)
1006 struct mlx5e_priv
*priv
= c
->priv
;
1007 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1009 void *sqc
= param
->sqc
;
1010 void *sqc_wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1013 sq
->type
= param
->type
;
1015 sq
->tstamp
= &priv
->tstamp
;
1016 sq
->mkey_be
= c
->mkey_be
;
1019 sq
->uar_map
= mdev
->mlx5e_res
.bfreg
.map
;
1021 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
1023 err
= mlx5_wq_cyc_create(mdev
, ¶m
->wq
, sqc_wq
, &sq
->wq
,
1028 sq
->wq
.db
= &sq
->wq
.db
[MLX5_SND_DBR
];
1030 sq
->max_inline
= param
->max_inline
;
1031 sq
->min_inline_mode
= param
->min_inline_mode
;
1033 err
= mlx5e_alloc_sq_db(sq
, cpu_to_node(c
->cpu
));
1035 goto err_sq_wq_destroy
;
1037 if (sq
->type
== MLX5E_SQ_TXQ
) {
1040 txq_ix
= c
->ix
+ tc
* priv
->params
.num_channels
;
1041 sq
->txq
= netdev_get_tx_queue(priv
->netdev
, txq_ix
);
1042 priv
->txq_to_sq_map
[txq_ix
] = sq
;
1045 sq
->edge
= (sq
->wq
.sz_m1
+ 1) - mlx5e_sq_get_max_wqebbs(sq
->type
);
1050 mlx5_wq_destroy(&sq
->wq_ctrl
);
1055 static void mlx5e_destroy_sq(struct mlx5e_sq
*sq
)
1057 mlx5e_free_sq_db(sq
);
1058 mlx5_wq_destroy(&sq
->wq_ctrl
);
1061 static int mlx5e_enable_sq(struct mlx5e_sq
*sq
, struct mlx5e_sq_param
*param
)
1063 struct mlx5e_channel
*c
= sq
->channel
;
1064 struct mlx5e_priv
*priv
= c
->priv
;
1065 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1073 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) +
1074 sizeof(u64
) * sq
->wq_ctrl
.buf
.npages
;
1075 in
= mlx5_vzalloc(inlen
);
1079 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
1080 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1082 memcpy(sqc
, param
->sqc
, sizeof(param
->sqc
));
1084 MLX5_SET(sqc
, sqc
, tis_num_0
, param
->type
== MLX5E_SQ_ICO
?
1085 0 : priv
->tisn
[sq
->tc
]);
1086 MLX5_SET(sqc
, sqc
, cqn
, sq
->cq
.mcq
.cqn
);
1088 if (MLX5_CAP_ETH(mdev
, wqe_inline_mode
) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT
)
1089 MLX5_SET(sqc
, sqc
, min_wqe_inline_mode
, sq
->min_inline_mode
);
1091 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
1092 MLX5_SET(sqc
, sqc
, tis_lst_sz
, param
->type
== MLX5E_SQ_ICO
? 0 : 1);
1094 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
1095 MLX5_SET(wq
, wq
, uar_page
, mdev
->mlx5e_res
.bfreg
.index
);
1096 MLX5_SET(wq
, wq
, log_wq_pg_sz
, sq
->wq_ctrl
.buf
.page_shift
-
1097 MLX5_ADAPTER_PAGE_SHIFT
);
1098 MLX5_SET64(wq
, wq
, dbr_addr
, sq
->wq_ctrl
.db
.dma
);
1100 mlx5_fill_page_array(&sq
->wq_ctrl
.buf
,
1101 (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
));
1103 err
= mlx5_core_create_sq(mdev
, in
, inlen
, &sq
->sqn
);
1110 static int mlx5e_modify_sq(struct mlx5e_sq
*sq
, int curr_state
,
1111 int next_state
, bool update_rl
, int rl_index
)
1113 struct mlx5e_channel
*c
= sq
->channel
;
1114 struct mlx5e_priv
*priv
= c
->priv
;
1115 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1122 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
1123 in
= mlx5_vzalloc(inlen
);
1127 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
1129 MLX5_SET(modify_sq_in
, in
, sq_state
, curr_state
);
1130 MLX5_SET(sqc
, sqc
, state
, next_state
);
1131 if (update_rl
&& next_state
== MLX5_SQC_STATE_RDY
) {
1132 MLX5_SET64(modify_sq_in
, in
, modify_bitmask
, 1);
1133 MLX5_SET(sqc
, sqc
, packet_pacing_rate_limit_index
, rl_index
);
1136 err
= mlx5_core_modify_sq(mdev
, sq
->sqn
, in
, inlen
);
1143 static void mlx5e_disable_sq(struct mlx5e_sq
*sq
)
1145 struct mlx5e_channel
*c
= sq
->channel
;
1146 struct mlx5e_priv
*priv
= c
->priv
;
1147 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1149 mlx5_core_destroy_sq(mdev
, sq
->sqn
);
1151 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
1154 static int mlx5e_open_sq(struct mlx5e_channel
*c
,
1156 struct mlx5e_sq_param
*param
,
1157 struct mlx5e_sq
*sq
)
1161 err
= mlx5e_create_sq(c
, tc
, param
, sq
);
1165 err
= mlx5e_enable_sq(sq
, param
);
1167 goto err_destroy_sq
;
1169 set_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1170 err
= mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RST
, MLX5_SQC_STATE_RDY
,
1173 goto err_disable_sq
;
1176 netdev_tx_reset_queue(sq
->txq
);
1177 netif_tx_start_queue(sq
->txq
);
1183 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1184 mlx5e_disable_sq(sq
);
1186 mlx5e_destroy_sq(sq
);
1191 static inline void netif_tx_disable_queue(struct netdev_queue
*txq
)
1193 __netif_tx_lock_bh(txq
);
1194 netif_tx_stop_queue(txq
);
1195 __netif_tx_unlock_bh(txq
);
1198 static void mlx5e_close_sq(struct mlx5e_sq
*sq
)
1200 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
1201 /* prevent netif_tx_wake_queue */
1202 napi_synchronize(&sq
->channel
->napi
);
1205 netif_tx_disable_queue(sq
->txq
);
1207 /* last doorbell out, godspeed .. */
1208 if (mlx5e_sq_has_room_for(sq
, 1)) {
1209 sq
->db
.txq
.skb
[(sq
->pc
& sq
->wq
.sz_m1
)] = NULL
;
1210 mlx5e_send_nop(sq
, true);
1214 mlx5e_disable_sq(sq
);
1215 mlx5e_free_sq_descs(sq
);
1216 mlx5e_destroy_sq(sq
);
1219 static int mlx5e_create_cq(struct mlx5e_channel
*c
,
1220 struct mlx5e_cq_param
*param
,
1221 struct mlx5e_cq
*cq
)
1223 struct mlx5e_priv
*priv
= c
->priv
;
1224 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1225 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1231 param
->wq
.buf_numa_node
= cpu_to_node(c
->cpu
);
1232 param
->wq
.db_numa_node
= cpu_to_node(c
->cpu
);
1233 param
->eq_ix
= c
->ix
;
1235 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
1240 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
1242 cq
->napi
= &c
->napi
;
1245 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
1246 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
1247 *mcq
->set_ci_db
= 0;
1249 mcq
->vector
= param
->eq_ix
;
1250 mcq
->comp
= mlx5e_completion_event
;
1251 mcq
->event
= mlx5e_cq_error_event
;
1254 for (i
= 0; i
< mlx5_cqwq_get_size(&cq
->wq
); i
++) {
1255 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, i
);
1266 static void mlx5e_destroy_cq(struct mlx5e_cq
*cq
)
1268 mlx5_cqwq_destroy(&cq
->wq_ctrl
);
1271 static int mlx5e_enable_cq(struct mlx5e_cq
*cq
, struct mlx5e_cq_param
*param
)
1273 struct mlx5e_priv
*priv
= cq
->priv
;
1274 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1275 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
1280 unsigned int irqn_not_used
;
1284 inlen
= MLX5_ST_SZ_BYTES(create_cq_in
) +
1285 sizeof(u64
) * cq
->wq_ctrl
.frag_buf
.npages
;
1286 in
= mlx5_vzalloc(inlen
);
1290 cqc
= MLX5_ADDR_OF(create_cq_in
, in
, cq_context
);
1292 memcpy(cqc
, param
->cqc
, sizeof(param
->cqc
));
1294 mlx5_fill_page_frag_array(&cq
->wq_ctrl
.frag_buf
,
1295 (__be64
*)MLX5_ADDR_OF(create_cq_in
, in
, pas
));
1297 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn
, &irqn_not_used
);
1299 MLX5_SET(cqc
, cqc
, cq_period_mode
, param
->cq_period_mode
);
1300 MLX5_SET(cqc
, cqc
, c_eqn
, eqn
);
1301 MLX5_SET(cqc
, cqc
, uar_page
, mdev
->priv
.uar
->index
);
1302 MLX5_SET(cqc
, cqc
, log_page_size
, cq
->wq_ctrl
.frag_buf
.page_shift
-
1303 MLX5_ADAPTER_PAGE_SHIFT
);
1304 MLX5_SET64(cqc
, cqc
, dbr_addr
, cq
->wq_ctrl
.db
.dma
);
1306 err
= mlx5_core_create_cq(mdev
, mcq
, in
, inlen
);
1318 static void mlx5e_disable_cq(struct mlx5e_cq
*cq
)
1320 struct mlx5e_priv
*priv
= cq
->priv
;
1321 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1323 mlx5_core_destroy_cq(mdev
, &cq
->mcq
);
1326 static int mlx5e_open_cq(struct mlx5e_channel
*c
,
1327 struct mlx5e_cq_param
*param
,
1328 struct mlx5e_cq
*cq
,
1329 struct mlx5e_cq_moder moderation
)
1332 struct mlx5e_priv
*priv
= c
->priv
;
1333 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1335 err
= mlx5e_create_cq(c
, param
, cq
);
1339 err
= mlx5e_enable_cq(cq
, param
);
1341 goto err_destroy_cq
;
1343 if (MLX5_CAP_GEN(mdev
, cq_moderation
))
1344 mlx5_core_modify_cq_moderation(mdev
, &cq
->mcq
,
1350 mlx5e_destroy_cq(cq
);
1355 static void mlx5e_close_cq(struct mlx5e_cq
*cq
)
1357 mlx5e_disable_cq(cq
);
1358 mlx5e_destroy_cq(cq
);
1361 static int mlx5e_get_cpu(struct mlx5e_priv
*priv
, int ix
)
1363 return cpumask_first(priv
->mdev
->priv
.irq_info
[ix
].mask
);
1366 static int mlx5e_open_tx_cqs(struct mlx5e_channel
*c
,
1367 struct mlx5e_channel_param
*cparam
)
1369 struct mlx5e_priv
*priv
= c
->priv
;
1373 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
1374 err
= mlx5e_open_cq(c
, &cparam
->tx_cq
, &c
->sq
[tc
].cq
,
1375 priv
->params
.tx_cq_moderation
);
1377 goto err_close_tx_cqs
;
1383 for (tc
--; tc
>= 0; tc
--)
1384 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1389 static void mlx5e_close_tx_cqs(struct mlx5e_channel
*c
)
1393 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1394 mlx5e_close_cq(&c
->sq
[tc
].cq
);
1397 static int mlx5e_open_sqs(struct mlx5e_channel
*c
,
1398 struct mlx5e_channel_param
*cparam
)
1403 for (tc
= 0; tc
< c
->num_tc
; tc
++) {
1404 err
= mlx5e_open_sq(c
, tc
, &cparam
->sq
, &c
->sq
[tc
]);
1412 for (tc
--; tc
>= 0; tc
--)
1413 mlx5e_close_sq(&c
->sq
[tc
]);
1418 static void mlx5e_close_sqs(struct mlx5e_channel
*c
)
1422 for (tc
= 0; tc
< c
->num_tc
; tc
++)
1423 mlx5e_close_sq(&c
->sq
[tc
]);
1426 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv
*priv
, int ix
)
1430 for (i
= 0; i
< priv
->profile
->max_tc
; i
++)
1431 priv
->channeltc_to_txq_map
[ix
][i
] =
1432 ix
+ i
* priv
->params
.num_channels
;
1435 static int mlx5e_set_sq_maxrate(struct net_device
*dev
,
1436 struct mlx5e_sq
*sq
, u32 rate
)
1438 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1439 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1443 if (rate
== sq
->rate_limit
)
1448 /* remove current rl index to free space to next ones */
1449 mlx5_rl_remove_rate(mdev
, sq
->rate_limit
);
1454 err
= mlx5_rl_add_rate(mdev
, rate
, &rl_index
);
1456 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1462 err
= mlx5e_modify_sq(sq
, MLX5_SQC_STATE_RDY
,
1463 MLX5_SQC_STATE_RDY
, true, rl_index
);
1465 netdev_err(dev
, "Failed configuring rate %u: %d\n",
1467 /* remove the rate from the table */
1469 mlx5_rl_remove_rate(mdev
, rate
);
1473 sq
->rate_limit
= rate
;
1477 static int mlx5e_set_tx_maxrate(struct net_device
*dev
, int index
, u32 rate
)
1479 struct mlx5e_priv
*priv
= netdev_priv(dev
);
1480 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1481 struct mlx5e_sq
*sq
= priv
->txq_to_sq_map
[index
];
1484 if (!mlx5_rl_is_supported(mdev
)) {
1485 netdev_err(dev
, "Rate limiting is not supported on this device\n");
1489 /* rate is given in Mb/sec, HW config is in Kb/sec */
1492 /* Check whether rate in valid range, 0 is always valid */
1493 if (rate
&& !mlx5_rl_is_in_range(mdev
, rate
)) {
1494 netdev_err(dev
, "TX rate %u, is not in range\n", rate
);
1498 mutex_lock(&priv
->state_lock
);
1499 if (test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
1500 err
= mlx5e_set_sq_maxrate(dev
, sq
, rate
);
1502 priv
->tx_rates
[index
] = rate
;
1503 mutex_unlock(&priv
->state_lock
);
1508 static inline int mlx5e_get_max_num_channels(struct mlx5_core_dev
*mdev
)
1510 return is_kdump_kernel() ?
1511 MLX5E_MIN_NUM_CHANNELS
:
1512 min_t(int, mdev
->priv
.eq_table
.num_comp_vectors
,
1513 MLX5E_MAX_NUM_CHANNELS
);
1516 static int mlx5e_open_channel(struct mlx5e_priv
*priv
, int ix
,
1517 struct mlx5e_channel_param
*cparam
,
1518 struct mlx5e_channel
**cp
)
1520 struct mlx5e_cq_moder icosq_cq_moder
= {0, 0};
1521 struct net_device
*netdev
= priv
->netdev
;
1522 struct mlx5e_cq_moder rx_cq_profile
;
1523 int cpu
= mlx5e_get_cpu(priv
, ix
);
1524 struct mlx5e_channel
*c
;
1525 struct mlx5e_sq
*sq
;
1529 c
= kzalloc_node(sizeof(*c
), GFP_KERNEL
, cpu_to_node(cpu
));
1536 c
->pdev
= &priv
->mdev
->pdev
->dev
;
1537 c
->netdev
= priv
->netdev
;
1538 c
->mkey_be
= cpu_to_be32(priv
->mdev
->mlx5e_res
.mkey
.key
);
1539 c
->num_tc
= priv
->params
.num_tc
;
1540 c
->xdp
= !!priv
->xdp_prog
;
1542 if (priv
->params
.rx_am_enabled
)
1543 rx_cq_profile
= mlx5e_am_get_def_profile(priv
->params
.rx_cq_period_mode
);
1545 rx_cq_profile
= priv
->params
.rx_cq_moderation
;
1547 mlx5e_build_channeltc_to_txq_map(priv
, ix
);
1549 netif_napi_add(netdev
, &c
->napi
, mlx5e_napi_poll
, 64);
1551 err
= mlx5e_open_cq(c
, &cparam
->icosq_cq
, &c
->icosq
.cq
, icosq_cq_moder
);
1555 err
= mlx5e_open_tx_cqs(c
, cparam
);
1557 goto err_close_icosq_cq
;
1559 err
= mlx5e_open_cq(c
, &cparam
->rx_cq
, &c
->rq
.cq
,
1562 goto err_close_tx_cqs
;
1564 /* XDP SQ CQ params are same as normal TXQ sq CQ params */
1565 err
= c
->xdp
? mlx5e_open_cq(c
, &cparam
->tx_cq
, &c
->xdp_sq
.cq
,
1566 priv
->params
.tx_cq_moderation
) : 0;
1568 goto err_close_rx_cq
;
1570 napi_enable(&c
->napi
);
1572 err
= mlx5e_open_sq(c
, 0, &cparam
->icosq
, &c
->icosq
);
1574 goto err_disable_napi
;
1576 err
= mlx5e_open_sqs(c
, cparam
);
1578 goto err_close_icosq
;
1580 for (i
= 0; i
< priv
->params
.num_tc
; i
++) {
1581 u32 txq_ix
= priv
->channeltc_to_txq_map
[ix
][i
];
1583 if (priv
->tx_rates
[txq_ix
]) {
1584 sq
= priv
->txq_to_sq_map
[txq_ix
];
1585 mlx5e_set_sq_maxrate(priv
->netdev
, sq
,
1586 priv
->tx_rates
[txq_ix
]);
1590 err
= c
->xdp
? mlx5e_open_sq(c
, 0, &cparam
->xdp_sq
, &c
->xdp_sq
) : 0;
1594 err
= mlx5e_open_rq(c
, &cparam
->rq
, &c
->rq
);
1596 goto err_close_xdp_sq
;
1598 netif_set_xps_queue(netdev
, get_cpu_mask(c
->cpu
), ix
);
1604 mlx5e_close_sq(&c
->xdp_sq
);
1610 mlx5e_close_sq(&c
->icosq
);
1613 napi_disable(&c
->napi
);
1615 mlx5e_close_cq(&c
->xdp_sq
.cq
);
1618 mlx5e_close_cq(&c
->rq
.cq
);
1621 mlx5e_close_tx_cqs(c
);
1624 mlx5e_close_cq(&c
->icosq
.cq
);
1627 netif_napi_del(&c
->napi
);
1633 static void mlx5e_close_channel(struct mlx5e_channel
*c
)
1635 mlx5e_close_rq(&c
->rq
);
1637 mlx5e_close_sq(&c
->xdp_sq
);
1639 mlx5e_close_sq(&c
->icosq
);
1640 napi_disable(&c
->napi
);
1642 mlx5e_close_cq(&c
->xdp_sq
.cq
);
1643 mlx5e_close_cq(&c
->rq
.cq
);
1644 mlx5e_close_tx_cqs(c
);
1645 mlx5e_close_cq(&c
->icosq
.cq
);
1646 netif_napi_del(&c
->napi
);
1651 static void mlx5e_build_rq_param(struct mlx5e_priv
*priv
,
1652 struct mlx5e_rq_param
*param
)
1654 void *rqc
= param
->rqc
;
1655 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1657 switch (priv
->params
.rq_wq_type
) {
1658 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1659 MLX5_SET(wq
, wq
, log_wqe_num_of_strides
,
1660 priv
->params
.mpwqe_log_num_strides
- 9);
1661 MLX5_SET(wq
, wq
, log_wqe_stride_size
,
1662 priv
->params
.mpwqe_log_stride_sz
- 6);
1663 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
1665 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1666 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1669 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
1670 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1671 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_rq_size
);
1672 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1673 MLX5_SET(rqc
, rqc
, counter_set_id
, priv
->q_counter
);
1675 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1676 param
->wq
.linear
= 1;
1678 param
->am_enabled
= priv
->params
.rx_am_enabled
;
1681 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param
*param
)
1683 void *rqc
= param
->rqc
;
1684 void *wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1686 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_LINKED_LIST
);
1687 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(sizeof(struct mlx5e_rx_wqe
)));
1690 static void mlx5e_build_sq_param_common(struct mlx5e_priv
*priv
,
1691 struct mlx5e_sq_param
*param
)
1693 void *sqc
= param
->sqc
;
1694 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1696 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1697 MLX5_SET(wq
, wq
, pd
, priv
->mdev
->mlx5e_res
.pdn
);
1699 param
->wq
.buf_numa_node
= dev_to_node(&priv
->mdev
->pdev
->dev
);
1702 static void mlx5e_build_sq_param(struct mlx5e_priv
*priv
,
1703 struct mlx5e_sq_param
*param
)
1705 void *sqc
= param
->sqc
;
1706 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1708 mlx5e_build_sq_param_common(priv
, param
);
1709 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_sq_size
);
1711 param
->max_inline
= priv
->params
.tx_max_inline
;
1712 param
->min_inline_mode
= priv
->params
.tx_min_inline_mode
;
1713 param
->type
= MLX5E_SQ_TXQ
;
1716 static void mlx5e_build_common_cq_param(struct mlx5e_priv
*priv
,
1717 struct mlx5e_cq_param
*param
)
1719 void *cqc
= param
->cqc
;
1721 MLX5_SET(cqc
, cqc
, uar_page
, priv
->mdev
->priv
.uar
->index
);
1724 static void mlx5e_build_rx_cq_param(struct mlx5e_priv
*priv
,
1725 struct mlx5e_cq_param
*param
)
1727 void *cqc
= param
->cqc
;
1730 switch (priv
->params
.rq_wq_type
) {
1731 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
:
1732 log_cq_size
= priv
->params
.log_rq_size
+
1733 priv
->params
.mpwqe_log_num_strides
;
1735 default: /* MLX5_WQ_TYPE_LINKED_LIST */
1736 log_cq_size
= priv
->params
.log_rq_size
;
1739 MLX5_SET(cqc
, cqc
, log_cq_size
, log_cq_size
);
1740 if (MLX5E_GET_PFLAG(priv
, MLX5E_PFLAG_RX_CQE_COMPRESS
)) {
1741 MLX5_SET(cqc
, cqc
, mini_cqe_res_format
, MLX5_CQE_FORMAT_CSUM
);
1742 MLX5_SET(cqc
, cqc
, cqe_comp_en
, 1);
1745 mlx5e_build_common_cq_param(priv
, param
);
1747 param
->cq_period_mode
= priv
->params
.rx_cq_period_mode
;
1750 static void mlx5e_build_tx_cq_param(struct mlx5e_priv
*priv
,
1751 struct mlx5e_cq_param
*param
)
1753 void *cqc
= param
->cqc
;
1755 MLX5_SET(cqc
, cqc
, log_cq_size
, priv
->params
.log_sq_size
);
1757 mlx5e_build_common_cq_param(priv
, param
);
1759 param
->cq_period_mode
= MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
1762 static void mlx5e_build_ico_cq_param(struct mlx5e_priv
*priv
,
1763 struct mlx5e_cq_param
*param
,
1766 void *cqc
= param
->cqc
;
1768 MLX5_SET(cqc
, cqc
, log_cq_size
, log_wq_size
);
1770 mlx5e_build_common_cq_param(priv
, param
);
1772 param
->cq_period_mode
= MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
1775 static void mlx5e_build_icosq_param(struct mlx5e_priv
*priv
,
1776 struct mlx5e_sq_param
*param
,
1779 void *sqc
= param
->sqc
;
1780 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1782 mlx5e_build_sq_param_common(priv
, param
);
1784 MLX5_SET(wq
, wq
, log_wq_sz
, log_wq_size
);
1785 MLX5_SET(sqc
, sqc
, reg_umr
, MLX5_CAP_ETH(priv
->mdev
, reg_umr_sq
));
1787 param
->type
= MLX5E_SQ_ICO
;
1790 static void mlx5e_build_xdpsq_param(struct mlx5e_priv
*priv
,
1791 struct mlx5e_sq_param
*param
)
1793 void *sqc
= param
->sqc
;
1794 void *wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1796 mlx5e_build_sq_param_common(priv
, param
);
1797 MLX5_SET(wq
, wq
, log_wq_sz
, priv
->params
.log_sq_size
);
1799 param
->max_inline
= priv
->params
.tx_max_inline
;
1800 param
->min_inline_mode
= priv
->params
.tx_min_inline_mode
;
1801 param
->type
= MLX5E_SQ_XDP
;
1804 static void mlx5e_build_channel_param(struct mlx5e_priv
*priv
, struct mlx5e_channel_param
*cparam
)
1806 u8 icosq_log_wq_sz
= MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
;
1808 mlx5e_build_rq_param(priv
, &cparam
->rq
);
1809 mlx5e_build_sq_param(priv
, &cparam
->sq
);
1810 mlx5e_build_xdpsq_param(priv
, &cparam
->xdp_sq
);
1811 mlx5e_build_icosq_param(priv
, &cparam
->icosq
, icosq_log_wq_sz
);
1812 mlx5e_build_rx_cq_param(priv
, &cparam
->rx_cq
);
1813 mlx5e_build_tx_cq_param(priv
, &cparam
->tx_cq
);
1814 mlx5e_build_ico_cq_param(priv
, &cparam
->icosq_cq
, icosq_log_wq_sz
);
1817 static int mlx5e_open_channels(struct mlx5e_priv
*priv
)
1819 struct mlx5e_channel_param
*cparam
;
1820 int nch
= priv
->params
.num_channels
;
1825 priv
->channel
= kcalloc(nch
, sizeof(struct mlx5e_channel
*),
1828 priv
->txq_to_sq_map
= kcalloc(nch
* priv
->params
.num_tc
,
1829 sizeof(struct mlx5e_sq
*), GFP_KERNEL
);
1831 cparam
= kzalloc(sizeof(struct mlx5e_channel_param
), GFP_KERNEL
);
1833 if (!priv
->channel
|| !priv
->txq_to_sq_map
|| !cparam
)
1834 goto err_free_txq_to_sq_map
;
1836 mlx5e_build_channel_param(priv
, cparam
);
1838 for (i
= 0; i
< nch
; i
++) {
1839 err
= mlx5e_open_channel(priv
, i
, cparam
, &priv
->channel
[i
]);
1841 goto err_close_channels
;
1844 for (j
= 0; j
< nch
; j
++) {
1845 err
= mlx5e_wait_for_min_rx_wqes(&priv
->channel
[j
]->rq
);
1847 goto err_close_channels
;
1850 /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1851 * polling for inactive tx queues.
1853 netif_tx_start_all_queues(priv
->netdev
);
1859 for (i
--; i
>= 0; i
--)
1860 mlx5e_close_channel(priv
->channel
[i
]);
1862 err_free_txq_to_sq_map
:
1863 kfree(priv
->txq_to_sq_map
);
1864 kfree(priv
->channel
);
1870 static void mlx5e_close_channels(struct mlx5e_priv
*priv
)
1874 /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1875 * polling for inactive tx queues.
1877 netif_tx_stop_all_queues(priv
->netdev
);
1878 netif_tx_disable(priv
->netdev
);
1880 for (i
= 0; i
< priv
->params
.num_channels
; i
++)
1881 mlx5e_close_channel(priv
->channel
[i
]);
1883 kfree(priv
->txq_to_sq_map
);
1884 kfree(priv
->channel
);
1887 static int mlx5e_rx_hash_fn(int hfunc
)
1889 return (hfunc
== ETH_RSS_HASH_TOP
) ?
1890 MLX5_RX_HASH_FN_TOEPLITZ
:
1891 MLX5_RX_HASH_FN_INVERTED_XOR8
;
1894 static int mlx5e_bits_invert(unsigned long a
, int size
)
1899 for (i
= 0; i
< size
; i
++)
1900 inv
|= (test_bit(size
- i
- 1, &a
) ? 1 : 0) << i
;
1905 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv
*priv
, void *rqtc
)
1909 for (i
= 0; i
< MLX5E_INDIR_RQT_SIZE
; i
++) {
1913 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_XOR
)
1914 ix
= mlx5e_bits_invert(i
, MLX5E_LOG_INDIR_RQT_SIZE
);
1916 ix
= priv
->params
.indirection_rqt
[ix
];
1917 rqn
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1918 priv
->channel
[ix
]->rq
.rqn
:
1920 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], rqn
);
1924 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv
*priv
, void *rqtc
,
1927 u32 rqn
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
) ?
1928 priv
->channel
[ix
]->rq
.rqn
:
1931 MLX5_SET(rqtc
, rqtc
, rq_num
[0], rqn
);
1934 static int mlx5e_create_rqt(struct mlx5e_priv
*priv
, int sz
,
1935 int ix
, struct mlx5e_rqt
*rqt
)
1937 struct mlx5_core_dev
*mdev
= priv
->mdev
;
1943 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
1944 in
= mlx5_vzalloc(inlen
);
1948 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
1950 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
1951 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
1953 if (sz
> 1) /* RSS */
1954 mlx5e_fill_indir_rqt_rqns(priv
, rqtc
);
1956 mlx5e_fill_direct_rqt_rqn(priv
, rqtc
, ix
);
1958 err
= mlx5_core_create_rqt(mdev
, in
, inlen
, &rqt
->rqtn
);
1960 rqt
->enabled
= true;
1966 void mlx5e_destroy_rqt(struct mlx5e_priv
*priv
, struct mlx5e_rqt
*rqt
)
1968 rqt
->enabled
= false;
1969 mlx5_core_destroy_rqt(priv
->mdev
, rqt
->rqtn
);
1972 static int mlx5e_create_indirect_rqts(struct mlx5e_priv
*priv
)
1974 struct mlx5e_rqt
*rqt
= &priv
->indir_rqt
;
1976 return mlx5e_create_rqt(priv
, MLX5E_INDIR_RQT_SIZE
, 0, rqt
);
1979 int mlx5e_create_direct_rqts(struct mlx5e_priv
*priv
)
1981 struct mlx5e_rqt
*rqt
;
1985 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
1986 rqt
= &priv
->direct_tir
[ix
].rqt
;
1987 err
= mlx5e_create_rqt(priv
, 1 /*size */, ix
, rqt
);
1989 goto err_destroy_rqts
;
1995 for (ix
--; ix
>= 0; ix
--)
1996 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[ix
].rqt
);
2001 int mlx5e_redirect_rqt(struct mlx5e_priv
*priv
, u32 rqtn
, int sz
, int ix
)
2003 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2009 inlen
= MLX5_ST_SZ_BYTES(modify_rqt_in
) + sizeof(u32
) * sz
;
2010 in
= mlx5_vzalloc(inlen
);
2014 rqtc
= MLX5_ADDR_OF(modify_rqt_in
, in
, ctx
);
2016 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
2017 if (sz
> 1) /* RSS */
2018 mlx5e_fill_indir_rqt_rqns(priv
, rqtc
);
2020 mlx5e_fill_direct_rqt_rqn(priv
, rqtc
, ix
);
2022 MLX5_SET(modify_rqt_in
, in
, bitmask
.rqn_list
, 1);
2024 err
= mlx5_core_modify_rqt(mdev
, rqtn
, in
, inlen
);
2031 static void mlx5e_redirect_rqts(struct mlx5e_priv
*priv
)
2036 if (priv
->indir_rqt
.enabled
) {
2037 rqtn
= priv
->indir_rqt
.rqtn
;
2038 mlx5e_redirect_rqt(priv
, rqtn
, MLX5E_INDIR_RQT_SIZE
, 0);
2041 for (ix
= 0; ix
< priv
->params
.num_channels
; ix
++) {
2042 if (!priv
->direct_tir
[ix
].rqt
.enabled
)
2044 rqtn
= priv
->direct_tir
[ix
].rqt
.rqtn
;
2045 mlx5e_redirect_rqt(priv
, rqtn
, 1, ix
);
2049 static void mlx5e_build_tir_ctx_lro(void *tirc
, struct mlx5e_priv
*priv
)
2051 if (!priv
->params
.lro_en
)
2054 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2056 MLX5_SET(tirc
, tirc
, lro_enable_mask
,
2057 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO
|
2058 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO
);
2059 MLX5_SET(tirc
, tirc
, lro_max_ip_payload_size
,
2060 (priv
->params
.lro_wqe_sz
-
2061 ROUGH_MAX_L2_L3_HDR_SZ
) >> 8);
2062 MLX5_SET(tirc
, tirc
, lro_timeout_period_usecs
, priv
->params
.lro_timeout
);
2065 void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_priv
*priv
, void *tirc
,
2066 enum mlx5e_traffic_types tt
)
2068 void *hfso
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
2070 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2071 MLX5_HASH_FIELD_SEL_DST_IP)
2073 #define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2074 MLX5_HASH_FIELD_SEL_DST_IP |\
2075 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2076 MLX5_HASH_FIELD_SEL_L4_DPORT)
2078 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2079 MLX5_HASH_FIELD_SEL_DST_IP |\
2080 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2082 MLX5_SET(tirc
, tirc
, rx_hash_fn
,
2083 mlx5e_rx_hash_fn(priv
->params
.rss_hfunc
));
2084 if (priv
->params
.rss_hfunc
== ETH_RSS_HASH_TOP
) {
2085 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
,
2086 rx_hash_toeplitz_key
);
2087 size_t len
= MLX5_FLD_SZ_BYTES(tirc
,
2088 rx_hash_toeplitz_key
);
2090 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
2091 memcpy(rss_key
, priv
->params
.toeplitz_hash_key
, len
);
2095 case MLX5E_TT_IPV4_TCP
:
2096 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2097 MLX5_L3_PROT_TYPE_IPV4
);
2098 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2099 MLX5_L4_PROT_TYPE_TCP
);
2100 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2101 MLX5_HASH_IP_L4PORTS
);
2104 case MLX5E_TT_IPV6_TCP
:
2105 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2106 MLX5_L3_PROT_TYPE_IPV6
);
2107 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2108 MLX5_L4_PROT_TYPE_TCP
);
2109 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2110 MLX5_HASH_IP_L4PORTS
);
2113 case MLX5E_TT_IPV4_UDP
:
2114 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2115 MLX5_L3_PROT_TYPE_IPV4
);
2116 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2117 MLX5_L4_PROT_TYPE_UDP
);
2118 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2119 MLX5_HASH_IP_L4PORTS
);
2122 case MLX5E_TT_IPV6_UDP
:
2123 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2124 MLX5_L3_PROT_TYPE_IPV6
);
2125 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
2126 MLX5_L4_PROT_TYPE_UDP
);
2127 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2128 MLX5_HASH_IP_L4PORTS
);
2131 case MLX5E_TT_IPV4_IPSEC_AH
:
2132 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2133 MLX5_L3_PROT_TYPE_IPV4
);
2134 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2135 MLX5_HASH_IP_IPSEC_SPI
);
2138 case MLX5E_TT_IPV6_IPSEC_AH
:
2139 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2140 MLX5_L3_PROT_TYPE_IPV6
);
2141 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2142 MLX5_HASH_IP_IPSEC_SPI
);
2145 case MLX5E_TT_IPV4_IPSEC_ESP
:
2146 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2147 MLX5_L3_PROT_TYPE_IPV4
);
2148 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2149 MLX5_HASH_IP_IPSEC_SPI
);
2152 case MLX5E_TT_IPV6_IPSEC_ESP
:
2153 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2154 MLX5_L3_PROT_TYPE_IPV6
);
2155 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2156 MLX5_HASH_IP_IPSEC_SPI
);
2160 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2161 MLX5_L3_PROT_TYPE_IPV4
);
2162 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2167 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
2168 MLX5_L3_PROT_TYPE_IPV6
);
2169 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
,
2173 WARN_ONCE(true, "%s: bad traffic type!\n", __func__
);
2177 static int mlx5e_modify_tirs_lro(struct mlx5e_priv
*priv
)
2179 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2188 inlen
= MLX5_ST_SZ_BYTES(modify_tir_in
);
2189 in
= mlx5_vzalloc(inlen
);
2193 MLX5_SET(modify_tir_in
, in
, bitmask
.lro
, 1);
2194 tirc
= MLX5_ADDR_OF(modify_tir_in
, in
, ctx
);
2196 mlx5e_build_tir_ctx_lro(tirc
, priv
);
2198 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
2199 err
= mlx5_core_modify_tir(mdev
, priv
->indir_tir
[tt
].tirn
, in
,
2205 for (ix
= 0; ix
< priv
->profile
->max_nch(priv
->mdev
); ix
++) {
2206 err
= mlx5_core_modify_tir(mdev
, priv
->direct_tir
[ix
].tirn
,
2218 static int mlx5e_set_mtu(struct mlx5e_priv
*priv
, u16 mtu
)
2220 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2221 u16 hw_mtu
= MLX5E_SW2HW_MTU(mtu
);
2224 err
= mlx5_set_port_mtu(mdev
, hw_mtu
, 1);
2228 /* Update vport context MTU */
2229 mlx5_modify_nic_vport_mtu(mdev
, hw_mtu
);
2233 static void mlx5e_query_mtu(struct mlx5e_priv
*priv
, u16
*mtu
)
2235 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2239 err
= mlx5_query_nic_vport_mtu(mdev
, &hw_mtu
);
2240 if (err
|| !hw_mtu
) /* fallback to port oper mtu */
2241 mlx5_query_port_oper_mtu(mdev
, &hw_mtu
, 1);
2243 *mtu
= MLX5E_HW2SW_MTU(hw_mtu
);
2246 static int mlx5e_set_dev_port_mtu(struct net_device
*netdev
)
2248 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2252 err
= mlx5e_set_mtu(priv
, netdev
->mtu
);
2256 mlx5e_query_mtu(priv
, &mtu
);
2257 if (mtu
!= netdev
->mtu
)
2258 netdev_warn(netdev
, "%s: VPort MTU %d is different than netdev mtu %d\n",
2259 __func__
, mtu
, netdev
->mtu
);
2265 static void mlx5e_netdev_set_tcs(struct net_device
*netdev
)
2267 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2268 int nch
= priv
->params
.num_channels
;
2269 int ntc
= priv
->params
.num_tc
;
2272 netdev_reset_tc(netdev
);
2277 netdev_set_num_tc(netdev
, ntc
);
2279 /* Map netdev TCs to offset 0
2280 * We have our own UP to TXQ mapping for QoS
2282 for (tc
= 0; tc
< ntc
; tc
++)
2283 netdev_set_tc_queue(netdev
, tc
, nch
, 0);
2286 int mlx5e_open_locked(struct net_device
*netdev
)
2288 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2289 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2293 set_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2295 mlx5e_netdev_set_tcs(netdev
);
2297 num_txqs
= priv
->params
.num_channels
* priv
->params
.num_tc
;
2298 netif_set_real_num_tx_queues(netdev
, num_txqs
);
2299 netif_set_real_num_rx_queues(netdev
, priv
->params
.num_channels
);
2301 err
= mlx5e_open_channels(priv
);
2303 netdev_err(netdev
, "%s: mlx5e_open_channels failed, %d\n",
2305 goto err_clear_state_opened_flag
;
2308 err
= mlx5e_refresh_tirs_self_loopback(priv
->mdev
, false);
2310 netdev_err(netdev
, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
2312 goto err_close_channels
;
2315 mlx5e_redirect_rqts(priv
);
2316 mlx5e_update_carrier(priv
);
2317 mlx5e_timestamp_init(priv
);
2318 #ifdef CONFIG_RFS_ACCEL
2319 priv
->netdev
->rx_cpu_rmap
= priv
->mdev
->rmap
;
2321 if (priv
->profile
->update_stats
)
2322 queue_delayed_work(priv
->wq
, &priv
->update_stats_work
, 0);
2324 if (MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
2325 err
= mlx5e_add_sqs_fwd_rules(priv
);
2327 goto err_close_channels
;
2332 mlx5e_close_channels(priv
);
2333 err_clear_state_opened_flag
:
2334 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2338 int mlx5e_open(struct net_device
*netdev
)
2340 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2343 mutex_lock(&priv
->state_lock
);
2344 err
= mlx5e_open_locked(netdev
);
2345 mutex_unlock(&priv
->state_lock
);
2350 int mlx5e_close_locked(struct net_device
*netdev
)
2352 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2353 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2355 /* May already be CLOSED in case a previous configuration operation
2356 * (e.g RX/TX queue size change) that involves close&open failed.
2358 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
2361 clear_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2363 if (MLX5_CAP_GEN(mdev
, vport_group_manager
))
2364 mlx5e_remove_sqs_fwd_rules(priv
);
2366 mlx5e_timestamp_cleanup(priv
);
2367 netif_carrier_off(priv
->netdev
);
2368 mlx5e_redirect_rqts(priv
);
2369 mlx5e_close_channels(priv
);
2374 int mlx5e_close(struct net_device
*netdev
)
2376 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2379 if (!netif_device_present(netdev
))
2382 mutex_lock(&priv
->state_lock
);
2383 err
= mlx5e_close_locked(netdev
);
2384 mutex_unlock(&priv
->state_lock
);
2389 static int mlx5e_create_drop_rq(struct mlx5e_priv
*priv
,
2390 struct mlx5e_rq
*rq
,
2391 struct mlx5e_rq_param
*param
)
2393 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2394 void *rqc
= param
->rqc
;
2395 void *rqc_wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
2398 param
->wq
.db_numa_node
= param
->wq
.buf_numa_node
;
2400 err
= mlx5_wq_ll_create(mdev
, ¶m
->wq
, rqc_wq
, &rq
->wq
,
2410 static int mlx5e_create_drop_cq(struct mlx5e_priv
*priv
,
2411 struct mlx5e_cq
*cq
,
2412 struct mlx5e_cq_param
*param
)
2414 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2415 struct mlx5_core_cq
*mcq
= &cq
->mcq
;
2420 err
= mlx5_cqwq_create(mdev
, ¶m
->wq
, param
->cqc
, &cq
->wq
,
2425 mlx5_vector2eqn(mdev
, param
->eq_ix
, &eqn_not_used
, &irqn
);
2428 mcq
->set_ci_db
= cq
->wq_ctrl
.db
.db
;
2429 mcq
->arm_db
= cq
->wq_ctrl
.db
.db
+ 1;
2430 *mcq
->set_ci_db
= 0;
2432 mcq
->vector
= param
->eq_ix
;
2433 mcq
->comp
= mlx5e_completion_event
;
2434 mcq
->event
= mlx5e_cq_error_event
;
2442 static int mlx5e_open_drop_rq(struct mlx5e_priv
*priv
)
2444 struct mlx5e_cq_param cq_param
;
2445 struct mlx5e_rq_param rq_param
;
2446 struct mlx5e_rq
*rq
= &priv
->drop_rq
;
2447 struct mlx5e_cq
*cq
= &priv
->drop_rq
.cq
;
2450 memset(&cq_param
, 0, sizeof(cq_param
));
2451 memset(&rq_param
, 0, sizeof(rq_param
));
2452 mlx5e_build_drop_rq_param(&rq_param
);
2454 err
= mlx5e_create_drop_cq(priv
, cq
, &cq_param
);
2458 err
= mlx5e_enable_cq(cq
, &cq_param
);
2460 goto err_destroy_cq
;
2462 err
= mlx5e_create_drop_rq(priv
, rq
, &rq_param
);
2464 goto err_disable_cq
;
2466 err
= mlx5e_enable_rq(rq
, &rq_param
);
2468 goto err_destroy_rq
;
2473 mlx5e_destroy_rq(&priv
->drop_rq
);
2476 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
2479 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
2484 static void mlx5e_close_drop_rq(struct mlx5e_priv
*priv
)
2486 mlx5e_disable_rq(&priv
->drop_rq
);
2487 mlx5e_destroy_rq(&priv
->drop_rq
);
2488 mlx5e_disable_cq(&priv
->drop_rq
.cq
);
2489 mlx5e_destroy_cq(&priv
->drop_rq
.cq
);
2492 static int mlx5e_create_tis(struct mlx5e_priv
*priv
, int tc
)
2494 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2495 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)] = {0};
2496 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
2498 MLX5_SET(tisc
, tisc
, prio
, tc
<< 1);
2499 MLX5_SET(tisc
, tisc
, transport_domain
, mdev
->mlx5e_res
.td
.tdn
);
2501 if (mlx5_lag_is_lacp_owner(mdev
))
2502 MLX5_SET(tisc
, tisc
, strict_lag_tx_port_affinity
, 1);
2504 return mlx5_core_create_tis(mdev
, in
, sizeof(in
), &priv
->tisn
[tc
]);
2507 static void mlx5e_destroy_tis(struct mlx5e_priv
*priv
, int tc
)
2509 mlx5_core_destroy_tis(priv
->mdev
, priv
->tisn
[tc
]);
2512 int mlx5e_create_tises(struct mlx5e_priv
*priv
)
2517 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++) {
2518 err
= mlx5e_create_tis(priv
, tc
);
2520 goto err_close_tises
;
2526 for (tc
--; tc
>= 0; tc
--)
2527 mlx5e_destroy_tis(priv
, tc
);
2532 void mlx5e_cleanup_nic_tx(struct mlx5e_priv
*priv
)
2536 for (tc
= 0; tc
< priv
->profile
->max_tc
; tc
++)
2537 mlx5e_destroy_tis(priv
, tc
);
2540 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv
*priv
, u32
*tirc
,
2541 enum mlx5e_traffic_types tt
)
2543 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2545 mlx5e_build_tir_ctx_lro(tirc
, priv
);
2547 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2548 MLX5_SET(tirc
, tirc
, indirect_table
, priv
->indir_rqt
.rqtn
);
2549 mlx5e_build_indir_tir_ctx_hash(priv
, tirc
, tt
);
2552 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv
*priv
, u32
*tirc
,
2555 MLX5_SET(tirc
, tirc
, transport_domain
, priv
->mdev
->mlx5e_res
.td
.tdn
);
2557 mlx5e_build_tir_ctx_lro(tirc
, priv
);
2559 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_INDIRECT
);
2560 MLX5_SET(tirc
, tirc
, indirect_table
, rqtn
);
2561 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_INVERTED_XOR8
);
2564 static int mlx5e_create_indirect_tirs(struct mlx5e_priv
*priv
)
2566 struct mlx5e_tir
*tir
;
2573 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2574 in
= mlx5_vzalloc(inlen
);
2578 for (tt
= 0; tt
< MLX5E_NUM_INDIR_TIRS
; tt
++) {
2579 memset(in
, 0, inlen
);
2580 tir
= &priv
->indir_tir
[tt
];
2581 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2582 mlx5e_build_indir_tir_ctx(priv
, tirc
, tt
);
2583 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2585 goto err_destroy_tirs
;
2593 for (tt
--; tt
>= 0; tt
--)
2594 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[tt
]);
2601 int mlx5e_create_direct_tirs(struct mlx5e_priv
*priv
)
2603 int nch
= priv
->profile
->max_nch(priv
->mdev
);
2604 struct mlx5e_tir
*tir
;
2611 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
2612 in
= mlx5_vzalloc(inlen
);
2616 for (ix
= 0; ix
< nch
; ix
++) {
2617 memset(in
, 0, inlen
);
2618 tir
= &priv
->direct_tir
[ix
];
2619 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
2620 mlx5e_build_direct_tir_ctx(priv
, tirc
,
2621 priv
->direct_tir
[ix
].rqt
.rqtn
);
2622 err
= mlx5e_create_tir(priv
->mdev
, tir
, in
, inlen
);
2624 goto err_destroy_ch_tirs
;
2631 err_destroy_ch_tirs
:
2632 for (ix
--; ix
>= 0; ix
--)
2633 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[ix
]);
2640 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv
*priv
)
2644 for (i
= 0; i
< MLX5E_NUM_INDIR_TIRS
; i
++)
2645 mlx5e_destroy_tir(priv
->mdev
, &priv
->indir_tir
[i
]);
2648 void mlx5e_destroy_direct_tirs(struct mlx5e_priv
*priv
)
2650 int nch
= priv
->profile
->max_nch(priv
->mdev
);
2653 for (i
= 0; i
< nch
; i
++)
2654 mlx5e_destroy_tir(priv
->mdev
, &priv
->direct_tir
[i
]);
2657 int mlx5e_modify_rqs_vsd(struct mlx5e_priv
*priv
, bool vsd
)
2662 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
2665 for (i
= 0; i
< priv
->params
.num_channels
; i
++) {
2666 err
= mlx5e_modify_rq_vsd(&priv
->channel
[i
]->rq
, vsd
);
2674 static int mlx5e_setup_tc(struct net_device
*netdev
, u8 tc
)
2676 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2680 if (tc
&& tc
!= MLX5E_MAX_NUM_TC
)
2683 mutex_lock(&priv
->state_lock
);
2685 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2687 mlx5e_close_locked(priv
->netdev
);
2689 priv
->params
.num_tc
= tc
? tc
: 1;
2692 err
= mlx5e_open_locked(priv
->netdev
);
2694 mutex_unlock(&priv
->state_lock
);
2699 static int mlx5e_ndo_setup_tc(struct net_device
*dev
, u32 handle
,
2700 __be16 proto
, struct tc_to_netdev
*tc
)
2702 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2704 if (TC_H_MAJ(handle
) != TC_H_MAJ(TC_H_INGRESS
))
2708 case TC_SETUP_CLSFLOWER
:
2709 switch (tc
->cls_flower
->command
) {
2710 case TC_CLSFLOWER_REPLACE
:
2711 return mlx5e_configure_flower(priv
, proto
, tc
->cls_flower
);
2712 case TC_CLSFLOWER_DESTROY
:
2713 return mlx5e_delete_flower(priv
, tc
->cls_flower
);
2714 case TC_CLSFLOWER_STATS
:
2715 return mlx5e_stats_flower(priv
, tc
->cls_flower
);
2722 if (tc
->type
!= TC_SETUP_MQPRIO
)
2725 tc
->mqprio
->hw
= TC_MQPRIO_HW_OFFLOAD_TCS
;
2727 return mlx5e_setup_tc(dev
, tc
->mqprio
->num_tc
);
2731 mlx5e_get_stats(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
2733 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2734 struct mlx5e_sw_stats
*sstats
= &priv
->stats
.sw
;
2735 struct mlx5e_vport_stats
*vstats
= &priv
->stats
.vport
;
2736 struct mlx5e_pport_stats
*pstats
= &priv
->stats
.pport
;
2738 if (mlx5e_is_uplink_rep(priv
)) {
2739 stats
->rx_packets
= PPORT_802_3_GET(pstats
, a_frames_received_ok
);
2740 stats
->rx_bytes
= PPORT_802_3_GET(pstats
, a_octets_received_ok
);
2741 stats
->tx_packets
= PPORT_802_3_GET(pstats
, a_frames_transmitted_ok
);
2742 stats
->tx_bytes
= PPORT_802_3_GET(pstats
, a_octets_transmitted_ok
);
2744 stats
->rx_packets
= sstats
->rx_packets
;
2745 stats
->rx_bytes
= sstats
->rx_bytes
;
2746 stats
->tx_packets
= sstats
->tx_packets
;
2747 stats
->tx_bytes
= sstats
->tx_bytes
;
2748 stats
->tx_dropped
= sstats
->tx_queue_dropped
;
2751 stats
->rx_dropped
= priv
->stats
.qcnt
.rx_out_of_buffer
;
2753 stats
->rx_length_errors
=
2754 PPORT_802_3_GET(pstats
, a_in_range_length_errors
) +
2755 PPORT_802_3_GET(pstats
, a_out_of_range_length_field
) +
2756 PPORT_802_3_GET(pstats
, a_frame_too_long_errors
);
2757 stats
->rx_crc_errors
=
2758 PPORT_802_3_GET(pstats
, a_frame_check_sequence_errors
);
2759 stats
->rx_frame_errors
= PPORT_802_3_GET(pstats
, a_alignment_errors
);
2760 stats
->tx_aborted_errors
= PPORT_2863_GET(pstats
, if_out_discards
);
2761 stats
->tx_carrier_errors
=
2762 PPORT_802_3_GET(pstats
, a_symbol_error_during_carrier
);
2763 stats
->rx_errors
= stats
->rx_length_errors
+ stats
->rx_crc_errors
+
2764 stats
->rx_frame_errors
;
2765 stats
->tx_errors
= stats
->tx_aborted_errors
+ stats
->tx_carrier_errors
;
2767 /* vport multicast also counts packets that are dropped due to steering
2768 * or rx out of buffer
2771 VPORT_COUNTER_GET(vstats
, received_eth_multicast
.packets
);
2775 static void mlx5e_set_rx_mode(struct net_device
*dev
)
2777 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2779 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
2782 static int mlx5e_set_mac(struct net_device
*netdev
, void *addr
)
2784 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2785 struct sockaddr
*saddr
= addr
;
2787 if (!is_valid_ether_addr(saddr
->sa_data
))
2788 return -EADDRNOTAVAIL
;
2790 netif_addr_lock_bh(netdev
);
2791 ether_addr_copy(netdev
->dev_addr
, saddr
->sa_data
);
2792 netif_addr_unlock_bh(netdev
);
2794 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
2799 #define MLX5E_SET_FEATURE(netdev, feature, enable) \
2802 netdev->features |= feature; \
2804 netdev->features &= ~feature; \
2807 typedef int (*mlx5e_feature_handler
)(struct net_device
*netdev
, bool enable
);
2809 static int set_feature_lro(struct net_device
*netdev
, bool enable
)
2811 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2812 bool was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2815 mutex_lock(&priv
->state_lock
);
2817 if (was_opened
&& (priv
->params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST
))
2818 mlx5e_close_locked(priv
->netdev
);
2820 priv
->params
.lro_en
= enable
;
2821 err
= mlx5e_modify_tirs_lro(priv
);
2823 netdev_err(netdev
, "lro modify failed, %d\n", err
);
2824 priv
->params
.lro_en
= !enable
;
2827 if (was_opened
&& (priv
->params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST
))
2828 mlx5e_open_locked(priv
->netdev
);
2830 mutex_unlock(&priv
->state_lock
);
2835 static int set_feature_vlan_filter(struct net_device
*netdev
, bool enable
)
2837 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2840 mlx5e_enable_vlan_filter(priv
);
2842 mlx5e_disable_vlan_filter(priv
);
2847 static int set_feature_tc_num_filters(struct net_device
*netdev
, bool enable
)
2849 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2851 if (!enable
&& mlx5e_tc_num_filters(priv
)) {
2853 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2860 static int set_feature_rx_all(struct net_device
*netdev
, bool enable
)
2862 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2863 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2865 return mlx5_set_port_fcs(mdev
, !enable
);
2868 static int set_feature_rx_vlan(struct net_device
*netdev
, bool enable
)
2870 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2873 mutex_lock(&priv
->state_lock
);
2875 priv
->params
.vlan_strip_disable
= !enable
;
2876 err
= mlx5e_modify_rqs_vsd(priv
, !enable
);
2878 priv
->params
.vlan_strip_disable
= enable
;
2880 mutex_unlock(&priv
->state_lock
);
2885 #ifdef CONFIG_RFS_ACCEL
2886 static int set_feature_arfs(struct net_device
*netdev
, bool enable
)
2888 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2892 err
= mlx5e_arfs_enable(priv
);
2894 err
= mlx5e_arfs_disable(priv
);
2900 static int mlx5e_handle_feature(struct net_device
*netdev
,
2901 netdev_features_t wanted_features
,
2902 netdev_features_t feature
,
2903 mlx5e_feature_handler feature_handler
)
2905 netdev_features_t changes
= wanted_features
^ netdev
->features
;
2906 bool enable
= !!(wanted_features
& feature
);
2909 if (!(changes
& feature
))
2912 err
= feature_handler(netdev
, enable
);
2914 netdev_err(netdev
, "%s feature 0x%llx failed err %d\n",
2915 enable
? "Enable" : "Disable", feature
, err
);
2919 MLX5E_SET_FEATURE(netdev
, feature
, enable
);
2923 static int mlx5e_set_features(struct net_device
*netdev
,
2924 netdev_features_t features
)
2928 err
= mlx5e_handle_feature(netdev
, features
, NETIF_F_LRO
,
2930 err
|= mlx5e_handle_feature(netdev
, features
,
2931 NETIF_F_HW_VLAN_CTAG_FILTER
,
2932 set_feature_vlan_filter
);
2933 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_TC
,
2934 set_feature_tc_num_filters
);
2935 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_RXALL
,
2936 set_feature_rx_all
);
2937 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_HW_VLAN_CTAG_RX
,
2938 set_feature_rx_vlan
);
2939 #ifdef CONFIG_RFS_ACCEL
2940 err
|= mlx5e_handle_feature(netdev
, features
, NETIF_F_NTUPLE
,
2944 return err
? -EINVAL
: 0;
2947 static int mlx5e_change_mtu(struct net_device
*netdev
, int new_mtu
)
2949 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
2954 mutex_lock(&priv
->state_lock
);
2956 reset
= !priv
->params
.lro_en
&&
2957 (priv
->params
.rq_wq_type
!=
2958 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
);
2960 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
2961 if (was_opened
&& reset
)
2962 mlx5e_close_locked(netdev
);
2964 netdev
->mtu
= new_mtu
;
2965 mlx5e_set_dev_port_mtu(netdev
);
2967 if (was_opened
&& reset
)
2968 err
= mlx5e_open_locked(netdev
);
2970 mutex_unlock(&priv
->state_lock
);
2975 static int mlx5e_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2979 return mlx5e_hwstamp_set(dev
, ifr
);
2981 return mlx5e_hwstamp_get(dev
, ifr
);
2987 static int mlx5e_set_vf_mac(struct net_device
*dev
, int vf
, u8
*mac
)
2989 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2990 struct mlx5_core_dev
*mdev
= priv
->mdev
;
2992 return mlx5_eswitch_set_vport_mac(mdev
->priv
.eswitch
, vf
+ 1, mac
);
2995 static int mlx5e_set_vf_vlan(struct net_device
*dev
, int vf
, u16 vlan
, u8 qos
,
2998 struct mlx5e_priv
*priv
= netdev_priv(dev
);
2999 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3001 if (vlan_proto
!= htons(ETH_P_8021Q
))
3002 return -EPROTONOSUPPORT
;
3004 return mlx5_eswitch_set_vport_vlan(mdev
->priv
.eswitch
, vf
+ 1,
3008 static int mlx5e_set_vf_spoofchk(struct net_device
*dev
, int vf
, bool setting
)
3010 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3011 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3013 return mlx5_eswitch_set_vport_spoofchk(mdev
->priv
.eswitch
, vf
+ 1, setting
);
3016 static int mlx5e_set_vf_trust(struct net_device
*dev
, int vf
, bool setting
)
3018 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3019 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3021 return mlx5_eswitch_set_vport_trust(mdev
->priv
.eswitch
, vf
+ 1, setting
);
3024 static int mlx5e_set_vf_rate(struct net_device
*dev
, int vf
, int min_tx_rate
,
3027 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3028 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3030 return mlx5_eswitch_set_vport_rate(mdev
->priv
.eswitch
, vf
+ 1,
3031 max_tx_rate
, min_tx_rate
);
3034 static int mlx5_vport_link2ifla(u8 esw_link
)
3037 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN
:
3038 return IFLA_VF_LINK_STATE_DISABLE
;
3039 case MLX5_ESW_VPORT_ADMIN_STATE_UP
:
3040 return IFLA_VF_LINK_STATE_ENABLE
;
3042 return IFLA_VF_LINK_STATE_AUTO
;
3045 static int mlx5_ifla_link2vport(u8 ifla_link
)
3047 switch (ifla_link
) {
3048 case IFLA_VF_LINK_STATE_DISABLE
:
3049 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN
;
3050 case IFLA_VF_LINK_STATE_ENABLE
:
3051 return MLX5_ESW_VPORT_ADMIN_STATE_UP
;
3053 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO
;
3056 static int mlx5e_set_vf_link_state(struct net_device
*dev
, int vf
,
3059 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3060 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3062 return mlx5_eswitch_set_vport_state(mdev
->priv
.eswitch
, vf
+ 1,
3063 mlx5_ifla_link2vport(link_state
));
3066 static int mlx5e_get_vf_config(struct net_device
*dev
,
3067 int vf
, struct ifla_vf_info
*ivi
)
3069 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3070 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3073 err
= mlx5_eswitch_get_vport_config(mdev
->priv
.eswitch
, vf
+ 1, ivi
);
3076 ivi
->linkstate
= mlx5_vport_link2ifla(ivi
->linkstate
);
3080 static int mlx5e_get_vf_stats(struct net_device
*dev
,
3081 int vf
, struct ifla_vf_stats
*vf_stats
)
3083 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3084 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3086 return mlx5_eswitch_get_vport_stats(mdev
->priv
.eswitch
, vf
+ 1,
3090 static void mlx5e_add_vxlan_port(struct net_device
*netdev
,
3091 struct udp_tunnel_info
*ti
)
3093 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3095 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
3098 if (!mlx5e_vxlan_allowed(priv
->mdev
))
3101 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 1);
3104 static void mlx5e_del_vxlan_port(struct net_device
*netdev
,
3105 struct udp_tunnel_info
*ti
)
3107 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3109 if (ti
->type
!= UDP_TUNNEL_TYPE_VXLAN
)
3112 if (!mlx5e_vxlan_allowed(priv
->mdev
))
3115 mlx5e_vxlan_queue_work(priv
, ti
->sa_family
, be16_to_cpu(ti
->port
), 0);
3118 static netdev_features_t
mlx5e_vxlan_features_check(struct mlx5e_priv
*priv
,
3119 struct sk_buff
*skb
,
3120 netdev_features_t features
)
3122 struct udphdr
*udph
;
3126 switch (vlan_get_protocol(skb
)) {
3127 case htons(ETH_P_IP
):
3128 proto
= ip_hdr(skb
)->protocol
;
3130 case htons(ETH_P_IPV6
):
3131 proto
= ipv6_hdr(skb
)->nexthdr
;
3137 if (proto
== IPPROTO_UDP
) {
3138 udph
= udp_hdr(skb
);
3139 port
= be16_to_cpu(udph
->dest
);
3142 /* Verify if UDP port is being offloaded by HW */
3143 if (port
&& mlx5e_vxlan_lookup_port(priv
, port
))
3147 /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
3148 return features
& ~(NETIF_F_CSUM_MASK
| NETIF_F_GSO_MASK
);
3151 static netdev_features_t
mlx5e_features_check(struct sk_buff
*skb
,
3152 struct net_device
*netdev
,
3153 netdev_features_t features
)
3155 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3157 features
= vlan_features_check(skb
, features
);
3158 features
= vxlan_features_check(skb
, features
);
3160 /* Validate if the tunneled packet is being offloaded by HW */
3161 if (skb
->encapsulation
&&
3162 (features
& NETIF_F_CSUM_MASK
|| features
& NETIF_F_GSO_MASK
))
3163 return mlx5e_vxlan_features_check(priv
, skb
, features
);
3168 static void mlx5e_tx_timeout(struct net_device
*dev
)
3170 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3171 bool sched_work
= false;
3174 netdev_err(dev
, "TX timeout detected\n");
3176 for (i
= 0; i
< priv
->params
.num_channels
* priv
->params
.num_tc
; i
++) {
3177 struct mlx5e_sq
*sq
= priv
->txq_to_sq_map
[i
];
3179 if (!netif_xmit_stopped(netdev_get_tx_queue(dev
, i
)))
3182 clear_bit(MLX5E_SQ_STATE_ENABLED
, &sq
->state
);
3183 netdev_err(dev
, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
3184 i
, sq
->sqn
, sq
->cq
.mcq
.cqn
, sq
->cc
, sq
->pc
);
3187 if (sched_work
&& test_bit(MLX5E_STATE_OPENED
, &priv
->state
))
3188 schedule_work(&priv
->tx_timeout_work
);
3191 static int mlx5e_xdp_set(struct net_device
*netdev
, struct bpf_prog
*prog
)
3193 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3194 struct bpf_prog
*old_prog
;
3196 bool reset
, was_opened
;
3199 mutex_lock(&priv
->state_lock
);
3201 if ((netdev
->features
& NETIF_F_LRO
) && prog
) {
3202 netdev_warn(netdev
, "can't set XDP while LRO is on, disable LRO first\n");
3207 was_opened
= test_bit(MLX5E_STATE_OPENED
, &priv
->state
);
3208 /* no need for full reset when exchanging programs */
3209 reset
= (!priv
->xdp_prog
|| !prog
);
3211 if (was_opened
&& reset
)
3212 mlx5e_close_locked(netdev
);
3213 if (was_opened
&& !reset
) {
3214 /* num_channels is invariant here, so we can take the
3215 * batched reference right upfront.
3217 prog
= bpf_prog_add(prog
, priv
->params
.num_channels
);
3219 err
= PTR_ERR(prog
);
3224 /* exchange programs, extra prog reference we got from caller
3225 * as long as we don't fail from this point onwards.
3227 old_prog
= xchg(&priv
->xdp_prog
, prog
);
3229 bpf_prog_put(old_prog
);
3231 if (reset
) /* change RQ type according to priv->xdp_prog */
3232 mlx5e_set_rq_priv_params(priv
);
3234 if (was_opened
&& reset
)
3235 mlx5e_open_locked(netdev
);
3237 if (!test_bit(MLX5E_STATE_OPENED
, &priv
->state
) || reset
)
3240 /* exchanging programs w/o reset, we update ref counts on behalf
3241 * of the channels RQs here.
3243 for (i
= 0; i
< priv
->params
.num_channels
; i
++) {
3244 struct mlx5e_channel
*c
= priv
->channel
[i
];
3246 clear_bit(MLX5E_RQ_STATE_ENABLED
, &c
->rq
.state
);
3247 napi_synchronize(&c
->napi
);
3248 /* prevent mlx5e_poll_rx_cq from accessing rq->xdp_prog */
3250 old_prog
= xchg(&c
->rq
.xdp_prog
, prog
);
3252 set_bit(MLX5E_RQ_STATE_ENABLED
, &c
->rq
.state
);
3253 /* napi_schedule in case we have missed anything */
3254 set_bit(MLX5E_CHANNEL_NAPI_SCHED
, &c
->flags
);
3255 napi_schedule(&c
->napi
);
3258 bpf_prog_put(old_prog
);
3262 mutex_unlock(&priv
->state_lock
);
3266 static bool mlx5e_xdp_attached(struct net_device
*dev
)
3268 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3270 return !!priv
->xdp_prog
;
3273 static int mlx5e_xdp(struct net_device
*dev
, struct netdev_xdp
*xdp
)
3275 switch (xdp
->command
) {
3276 case XDP_SETUP_PROG
:
3277 return mlx5e_xdp_set(dev
, xdp
->prog
);
3278 case XDP_QUERY_PROG
:
3279 xdp
->prog_attached
= mlx5e_xdp_attached(dev
);
3286 #ifdef CONFIG_NET_POLL_CONTROLLER
3287 /* Fake "interrupt" called by netpoll (eg netconsole) to send skbs without
3288 * reenabling interrupts.
3290 static void mlx5e_netpoll(struct net_device
*dev
)
3292 struct mlx5e_priv
*priv
= netdev_priv(dev
);
3295 for (i
= 0; i
< priv
->params
.num_channels
; i
++)
3296 napi_schedule(&priv
->channel
[i
]->napi
);
3300 static const struct net_device_ops mlx5e_netdev_ops_basic
= {
3301 .ndo_open
= mlx5e_open
,
3302 .ndo_stop
= mlx5e_close
,
3303 .ndo_start_xmit
= mlx5e_xmit
,
3304 .ndo_setup_tc
= mlx5e_ndo_setup_tc
,
3305 .ndo_select_queue
= mlx5e_select_queue
,
3306 .ndo_get_stats64
= mlx5e_get_stats
,
3307 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
3308 .ndo_set_mac_address
= mlx5e_set_mac
,
3309 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
3310 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
3311 .ndo_set_features
= mlx5e_set_features
,
3312 .ndo_change_mtu
= mlx5e_change_mtu
,
3313 .ndo_do_ioctl
= mlx5e_ioctl
,
3314 .ndo_set_tx_maxrate
= mlx5e_set_tx_maxrate
,
3315 #ifdef CONFIG_RFS_ACCEL
3316 .ndo_rx_flow_steer
= mlx5e_rx_flow_steer
,
3318 .ndo_tx_timeout
= mlx5e_tx_timeout
,
3319 .ndo_xdp
= mlx5e_xdp
,
3320 #ifdef CONFIG_NET_POLL_CONTROLLER
3321 .ndo_poll_controller
= mlx5e_netpoll
,
3325 static const struct net_device_ops mlx5e_netdev_ops_sriov
= {
3326 .ndo_open
= mlx5e_open
,
3327 .ndo_stop
= mlx5e_close
,
3328 .ndo_start_xmit
= mlx5e_xmit
,
3329 .ndo_setup_tc
= mlx5e_ndo_setup_tc
,
3330 .ndo_select_queue
= mlx5e_select_queue
,
3331 .ndo_get_stats64
= mlx5e_get_stats
,
3332 .ndo_set_rx_mode
= mlx5e_set_rx_mode
,
3333 .ndo_set_mac_address
= mlx5e_set_mac
,
3334 .ndo_vlan_rx_add_vid
= mlx5e_vlan_rx_add_vid
,
3335 .ndo_vlan_rx_kill_vid
= mlx5e_vlan_rx_kill_vid
,
3336 .ndo_set_features
= mlx5e_set_features
,
3337 .ndo_change_mtu
= mlx5e_change_mtu
,
3338 .ndo_do_ioctl
= mlx5e_ioctl
,
3339 .ndo_udp_tunnel_add
= mlx5e_add_vxlan_port
,
3340 .ndo_udp_tunnel_del
= mlx5e_del_vxlan_port
,
3341 .ndo_set_tx_maxrate
= mlx5e_set_tx_maxrate
,
3342 .ndo_features_check
= mlx5e_features_check
,
3343 #ifdef CONFIG_RFS_ACCEL
3344 .ndo_rx_flow_steer
= mlx5e_rx_flow_steer
,
3346 .ndo_set_vf_mac
= mlx5e_set_vf_mac
,
3347 .ndo_set_vf_vlan
= mlx5e_set_vf_vlan
,
3348 .ndo_set_vf_spoofchk
= mlx5e_set_vf_spoofchk
,
3349 .ndo_set_vf_trust
= mlx5e_set_vf_trust
,
3350 .ndo_set_vf_rate
= mlx5e_set_vf_rate
,
3351 .ndo_get_vf_config
= mlx5e_get_vf_config
,
3352 .ndo_set_vf_link_state
= mlx5e_set_vf_link_state
,
3353 .ndo_get_vf_stats
= mlx5e_get_vf_stats
,
3354 .ndo_tx_timeout
= mlx5e_tx_timeout
,
3355 .ndo_xdp
= mlx5e_xdp
,
3356 #ifdef CONFIG_NET_POLL_CONTROLLER
3357 .ndo_poll_controller
= mlx5e_netpoll
,
3359 .ndo_has_offload_stats
= mlx5e_has_offload_stats
,
3360 .ndo_get_offload_stats
= mlx5e_get_offload_stats
,
3363 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev
*mdev
)
3365 if (MLX5_CAP_GEN(mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
)
3367 if (!MLX5_CAP_GEN(mdev
, eth_net_offloads
) ||
3368 !MLX5_CAP_GEN(mdev
, nic_flow_table
) ||
3369 !MLX5_CAP_ETH(mdev
, csum_cap
) ||
3370 !MLX5_CAP_ETH(mdev
, max_lso_cap
) ||
3371 !MLX5_CAP_ETH(mdev
, vlan_cap
) ||
3372 !MLX5_CAP_ETH(mdev
, rss_ind_tbl_cap
) ||
3373 MLX5_CAP_FLOWTABLE(mdev
,
3374 flow_table_properties_nic_receive
.max_ft_level
)
3376 mlx5_core_warn(mdev
,
3377 "Not creating net device, some required device capabilities are missing\n");
3380 if (!MLX5_CAP_ETH(mdev
, self_lb_en_modifiable
))
3381 mlx5_core_warn(mdev
, "Self loop back prevention is not supported\n");
3382 if (!MLX5_CAP_GEN(mdev
, cq_moderation
))
3383 mlx5_core_warn(mdev
, "CQ modiration is not supported\n");
3388 u16
mlx5e_get_max_inline_cap(struct mlx5_core_dev
*mdev
)
3390 int bf_buf_size
= (1 << MLX5_CAP_GEN(mdev
, log_bf_reg_size
)) / 2;
3392 return bf_buf_size
-
3393 sizeof(struct mlx5e_tx_wqe
) +
3394 2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3397 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev
*mdev
,
3398 u32
*indirection_rqt
, int len
,
3401 int node
= mdev
->priv
.numa_node
;
3402 int node_num_of_cores
;
3406 node
= first_online_node
;
3408 node_num_of_cores
= cpumask_weight(cpumask_of_node(node
));
3410 if (node_num_of_cores
)
3411 num_channels
= min_t(int, num_channels
, node_num_of_cores
);
3413 for (i
= 0; i
< len
; i
++)
3414 indirection_rqt
[i
] = i
% num_channels
;
3417 static int mlx5e_get_pci_bw(struct mlx5_core_dev
*mdev
, u32
*pci_bw
)
3419 enum pcie_link_width width
;
3420 enum pci_bus_speed speed
;
3423 err
= pcie_get_minimum_link(mdev
->pdev
, &speed
, &width
);
3427 if (speed
== PCI_SPEED_UNKNOWN
|| width
== PCIE_LNK_WIDTH_UNKNOWN
)
3431 case PCIE_SPEED_2_5GT
:
3432 *pci_bw
= 2500 * width
;
3434 case PCIE_SPEED_5_0GT
:
3435 *pci_bw
= 5000 * width
;
3437 case PCIE_SPEED_8_0GT
:
3438 *pci_bw
= 8000 * width
;
3447 static bool cqe_compress_heuristic(u32 link_speed
, u32 pci_bw
)
3449 return (link_speed
&& pci_bw
&&
3450 (pci_bw
< 40000) && (pci_bw
< link_speed
));
3453 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params
*params
, u8 cq_period_mode
)
3455 params
->rx_cq_period_mode
= cq_period_mode
;
3457 params
->rx_cq_moderation
.pkts
=
3458 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS
;
3459 params
->rx_cq_moderation
.usec
=
3460 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC
;
3462 if (cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
)
3463 params
->rx_cq_moderation
.usec
=
3464 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE
;
3467 u32
mlx5e_choose_lro_timeout(struct mlx5_core_dev
*mdev
, u32 wanted_timeout
)
3471 /* The supported periods are organized in ascending order */
3472 for (i
= 0; i
< MLX5E_LRO_TIMEOUT_ARR_SIZE
- 1; i
++)
3473 if (MLX5_CAP_ETH(mdev
, lro_timer_supported_periods
[i
]) >= wanted_timeout
)
3476 return MLX5_CAP_ETH(mdev
, lro_timer_supported_periods
[i
]);
3479 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev
*mdev
,
3480 struct net_device
*netdev
,
3481 const struct mlx5e_profile
*profile
,
3484 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3487 u8 cq_period_mode
= MLX5_CAP_GEN(mdev
, cq_period_start_from_cqe
) ?
3488 MLX5_CQ_PERIOD_MODE_START_FROM_CQE
:
3489 MLX5_CQ_PERIOD_MODE_START_FROM_EQE
;
3492 priv
->netdev
= netdev
;
3493 priv
->params
.num_channels
= profile
->max_nch(mdev
);
3494 priv
->profile
= profile
;
3495 priv
->ppriv
= ppriv
;
3497 priv
->params
.lro_timeout
=
3498 mlx5e_choose_lro_timeout(mdev
, MLX5E_DEFAULT_LRO_TIMEOUT
);
3500 priv
->params
.log_sq_size
= is_kdump_kernel() ?
3501 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE
:
3502 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE
;
3504 /* set CQE compression */
3505 priv
->params
.rx_cqe_compress_def
= false;
3506 if (MLX5_CAP_GEN(mdev
, cqe_compression
) &&
3507 MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
3508 mlx5e_get_max_linkspeed(mdev
, &link_speed
);
3509 mlx5e_get_pci_bw(mdev
, &pci_bw
);
3510 mlx5_core_dbg(mdev
, "Max link speed = %d, PCI BW = %d\n",
3511 link_speed
, pci_bw
);
3512 priv
->params
.rx_cqe_compress_def
=
3513 cqe_compress_heuristic(link_speed
, pci_bw
);
3516 MLX5E_SET_PFLAG(priv
, MLX5E_PFLAG_RX_CQE_COMPRESS
,
3517 priv
->params
.rx_cqe_compress_def
);
3519 mlx5e_set_rq_priv_params(priv
);
3520 if (priv
->params
.rq_wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
)
3521 priv
->params
.lro_en
= true;
3523 priv
->params
.rx_am_enabled
= MLX5_CAP_GEN(mdev
, cq_moderation
);
3524 mlx5e_set_rx_cq_mode_params(&priv
->params
, cq_period_mode
);
3526 priv
->params
.tx_cq_moderation
.usec
=
3527 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC
;
3528 priv
->params
.tx_cq_moderation
.pkts
=
3529 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS
;
3530 priv
->params
.tx_max_inline
= mlx5e_get_max_inline_cap(mdev
);
3531 mlx5_query_min_inline(mdev
, &priv
->params
.tx_min_inline_mode
);
3532 if (priv
->params
.tx_min_inline_mode
== MLX5_INLINE_MODE_NONE
&&
3533 !MLX5_CAP_ETH(mdev
, wqe_vlan_insert
))
3534 priv
->params
.tx_min_inline_mode
= MLX5_INLINE_MODE_L2
;
3536 priv
->params
.num_tc
= 1;
3537 priv
->params
.rss_hfunc
= ETH_RSS_HASH_XOR
;
3539 netdev_rss_key_fill(priv
->params
.toeplitz_hash_key
,
3540 sizeof(priv
->params
.toeplitz_hash_key
));
3542 mlx5e_build_default_indir_rqt(mdev
, priv
->params
.indirection_rqt
,
3543 MLX5E_INDIR_RQT_SIZE
, profile
->max_nch(mdev
));
3545 /* Initialize pflags */
3546 MLX5E_SET_PFLAG(priv
, MLX5E_PFLAG_RX_CQE_BASED_MODER
,
3547 priv
->params
.rx_cq_period_mode
== MLX5_CQ_PERIOD_MODE_START_FROM_CQE
);
3549 mutex_init(&priv
->state_lock
);
3551 INIT_WORK(&priv
->update_carrier_work
, mlx5e_update_carrier_work
);
3552 INIT_WORK(&priv
->set_rx_mode_work
, mlx5e_set_rx_mode_work
);
3553 INIT_WORK(&priv
->tx_timeout_work
, mlx5e_tx_timeout_work
);
3554 INIT_DELAYED_WORK(&priv
->update_stats_work
, mlx5e_update_stats_work
);
3557 static void mlx5e_set_netdev_dev_addr(struct net_device
*netdev
)
3559 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3561 mlx5_query_nic_vport_mac_address(priv
->mdev
, 0, netdev
->dev_addr
);
3562 if (is_zero_ether_addr(netdev
->dev_addr
) &&
3563 !MLX5_CAP_GEN(priv
->mdev
, vport_group_manager
)) {
3564 eth_hw_addr_random(netdev
);
3565 mlx5_core_info(priv
->mdev
, "Assigned random MAC address %pM\n", netdev
->dev_addr
);
3569 static const struct switchdev_ops mlx5e_switchdev_ops
= {
3570 .switchdev_port_attr_get
= mlx5e_attr_get
,
3573 static void mlx5e_build_nic_netdev(struct net_device
*netdev
)
3575 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3576 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3580 SET_NETDEV_DEV(netdev
, &mdev
->pdev
->dev
);
3582 if (MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
3583 netdev
->netdev_ops
= &mlx5e_netdev_ops_sriov
;
3584 #ifdef CONFIG_MLX5_CORE_EN_DCB
3585 if (MLX5_CAP_GEN(mdev
, qos
))
3586 netdev
->dcbnl_ops
= &mlx5e_dcbnl_ops
;
3589 netdev
->netdev_ops
= &mlx5e_netdev_ops_basic
;
3592 netdev
->watchdog_timeo
= 15 * HZ
;
3594 netdev
->ethtool_ops
= &mlx5e_ethtool_ops
;
3596 netdev
->vlan_features
|= NETIF_F_SG
;
3597 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
3598 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
3599 netdev
->vlan_features
|= NETIF_F_GRO
;
3600 netdev
->vlan_features
|= NETIF_F_TSO
;
3601 netdev
->vlan_features
|= NETIF_F_TSO6
;
3602 netdev
->vlan_features
|= NETIF_F_RXCSUM
;
3603 netdev
->vlan_features
|= NETIF_F_RXHASH
;
3605 if (!!MLX5_CAP_ETH(mdev
, lro_cap
))
3606 netdev
->vlan_features
|= NETIF_F_LRO
;
3608 netdev
->hw_features
= netdev
->vlan_features
;
3609 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_TX
;
3610 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
;
3611 netdev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
3613 if (mlx5e_vxlan_allowed(mdev
)) {
3614 netdev
->hw_features
|= NETIF_F_GSO_UDP_TUNNEL
|
3615 NETIF_F_GSO_UDP_TUNNEL_CSUM
|
3616 NETIF_F_GSO_PARTIAL
;
3617 netdev
->hw_enc_features
|= NETIF_F_IP_CSUM
;
3618 netdev
->hw_enc_features
|= NETIF_F_IPV6_CSUM
;
3619 netdev
->hw_enc_features
|= NETIF_F_TSO
;
3620 netdev
->hw_enc_features
|= NETIF_F_TSO6
;
3621 netdev
->hw_enc_features
|= NETIF_F_GSO_UDP_TUNNEL
;
3622 netdev
->hw_enc_features
|= NETIF_F_GSO_UDP_TUNNEL_CSUM
|
3623 NETIF_F_GSO_PARTIAL
;
3624 netdev
->gso_partial_features
= NETIF_F_GSO_UDP_TUNNEL_CSUM
;
3627 mlx5_query_port_fcs(mdev
, &fcs_supported
, &fcs_enabled
);
3630 netdev
->hw_features
|= NETIF_F_RXALL
;
3632 netdev
->features
= netdev
->hw_features
;
3633 if (!priv
->params
.lro_en
)
3634 netdev
->features
&= ~NETIF_F_LRO
;
3637 netdev
->features
&= ~NETIF_F_RXALL
;
3639 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3640 if (FT_CAP(flow_modify_en
) &&
3641 FT_CAP(modify_root
) &&
3642 FT_CAP(identified_miss_table_mode
) &&
3643 FT_CAP(flow_table_modify
)) {
3644 netdev
->hw_features
|= NETIF_F_HW_TC
;
3645 #ifdef CONFIG_RFS_ACCEL
3646 netdev
->hw_features
|= NETIF_F_NTUPLE
;
3650 netdev
->features
|= NETIF_F_HIGHDMA
;
3652 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
3654 mlx5e_set_netdev_dev_addr(netdev
);
3656 #ifdef CONFIG_NET_SWITCHDEV
3657 if (MLX5_CAP_GEN(mdev
, vport_group_manager
))
3658 netdev
->switchdev_ops
= &mlx5e_switchdev_ops
;
3662 static void mlx5e_create_q_counter(struct mlx5e_priv
*priv
)
3664 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3667 err
= mlx5_core_alloc_q_counter(mdev
, &priv
->q_counter
);
3669 mlx5_core_warn(mdev
, "alloc queue counter failed, %d\n", err
);
3670 priv
->q_counter
= 0;
3674 static void mlx5e_destroy_q_counter(struct mlx5e_priv
*priv
)
3676 if (!priv
->q_counter
)
3679 mlx5_core_dealloc_q_counter(priv
->mdev
, priv
->q_counter
);
3682 static void mlx5e_nic_init(struct mlx5_core_dev
*mdev
,
3683 struct net_device
*netdev
,
3684 const struct mlx5e_profile
*profile
,
3687 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3689 mlx5e_build_nic_netdev_priv(mdev
, netdev
, profile
, ppriv
);
3690 mlx5e_build_nic_netdev(netdev
);
3691 mlx5e_vxlan_init(priv
);
3694 static void mlx5e_nic_cleanup(struct mlx5e_priv
*priv
)
3696 mlx5e_vxlan_cleanup(priv
);
3699 bpf_prog_put(priv
->xdp_prog
);
3702 static int mlx5e_init_nic_rx(struct mlx5e_priv
*priv
)
3704 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3708 err
= mlx5e_create_indirect_rqts(priv
);
3710 mlx5_core_warn(mdev
, "create indirect rqts failed, %d\n", err
);
3714 err
= mlx5e_create_direct_rqts(priv
);
3716 mlx5_core_warn(mdev
, "create direct rqts failed, %d\n", err
);
3717 goto err_destroy_indirect_rqts
;
3720 err
= mlx5e_create_indirect_tirs(priv
);
3722 mlx5_core_warn(mdev
, "create indirect tirs failed, %d\n", err
);
3723 goto err_destroy_direct_rqts
;
3726 err
= mlx5e_create_direct_tirs(priv
);
3728 mlx5_core_warn(mdev
, "create direct tirs failed, %d\n", err
);
3729 goto err_destroy_indirect_tirs
;
3732 err
= mlx5e_create_flow_steering(priv
);
3734 mlx5_core_warn(mdev
, "create flow steering failed, %d\n", err
);
3735 goto err_destroy_direct_tirs
;
3738 err
= mlx5e_tc_init(priv
);
3740 goto err_destroy_flow_steering
;
3744 err_destroy_flow_steering
:
3745 mlx5e_destroy_flow_steering(priv
);
3746 err_destroy_direct_tirs
:
3747 mlx5e_destroy_direct_tirs(priv
);
3748 err_destroy_indirect_tirs
:
3749 mlx5e_destroy_indirect_tirs(priv
);
3750 err_destroy_direct_rqts
:
3751 for (i
= 0; i
< priv
->profile
->max_nch(mdev
); i
++)
3752 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[i
].rqt
);
3753 err_destroy_indirect_rqts
:
3754 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
3758 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv
*priv
)
3762 mlx5e_tc_cleanup(priv
);
3763 mlx5e_destroy_flow_steering(priv
);
3764 mlx5e_destroy_direct_tirs(priv
);
3765 mlx5e_destroy_indirect_tirs(priv
);
3766 for (i
= 0; i
< priv
->profile
->max_nch(priv
->mdev
); i
++)
3767 mlx5e_destroy_rqt(priv
, &priv
->direct_tir
[i
].rqt
);
3768 mlx5e_destroy_rqt(priv
, &priv
->indir_rqt
);
3771 static int mlx5e_init_nic_tx(struct mlx5e_priv
*priv
)
3775 err
= mlx5e_create_tises(priv
);
3777 mlx5_core_warn(priv
->mdev
, "create tises failed, %d\n", err
);
3781 #ifdef CONFIG_MLX5_CORE_EN_DCB
3782 mlx5e_dcbnl_initialize(priv
);
3787 static void mlx5e_nic_enable(struct mlx5e_priv
*priv
)
3789 struct net_device
*netdev
= priv
->netdev
;
3790 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3791 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
3792 struct mlx5_eswitch_rep rep
;
3794 mlx5_lag_add(mdev
, netdev
);
3796 mlx5e_enable_async_events(priv
);
3798 if (MLX5_CAP_GEN(mdev
, vport_group_manager
)) {
3799 mlx5_query_nic_vport_mac_address(mdev
, 0, rep
.hw_id
);
3800 rep
.load
= mlx5e_nic_rep_load
;
3801 rep
.unload
= mlx5e_nic_rep_unload
;
3802 rep
.vport
= FDB_UPLINK_VPORT
;
3803 rep
.netdev
= netdev
;
3804 mlx5_eswitch_register_vport_rep(esw
, 0, &rep
);
3807 if (netdev
->reg_state
!= NETREG_REGISTERED
)
3810 /* Device already registered: sync netdev system state */
3811 if (mlx5e_vxlan_allowed(mdev
)) {
3813 udp_tunnel_get_rx_info(netdev
);
3817 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3820 static void mlx5e_nic_disable(struct mlx5e_priv
*priv
)
3822 struct mlx5_core_dev
*mdev
= priv
->mdev
;
3823 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
3825 queue_work(priv
->wq
, &priv
->set_rx_mode_work
);
3826 if (MLX5_CAP_GEN(mdev
, vport_group_manager
))
3827 mlx5_eswitch_unregister_vport_rep(esw
, 0);
3828 mlx5e_disable_async_events(priv
);
3829 mlx5_lag_remove(mdev
);
3832 static const struct mlx5e_profile mlx5e_nic_profile
= {
3833 .init
= mlx5e_nic_init
,
3834 .cleanup
= mlx5e_nic_cleanup
,
3835 .init_rx
= mlx5e_init_nic_rx
,
3836 .cleanup_rx
= mlx5e_cleanup_nic_rx
,
3837 .init_tx
= mlx5e_init_nic_tx
,
3838 .cleanup_tx
= mlx5e_cleanup_nic_tx
,
3839 .enable
= mlx5e_nic_enable
,
3840 .disable
= mlx5e_nic_disable
,
3841 .update_stats
= mlx5e_update_stats
,
3842 .max_nch
= mlx5e_get_max_num_channels
,
3843 .max_tc
= MLX5E_MAX_NUM_TC
,
3846 struct net_device
*mlx5e_create_netdev(struct mlx5_core_dev
*mdev
,
3847 const struct mlx5e_profile
*profile
,
3850 int nch
= profile
->max_nch(mdev
);
3851 struct net_device
*netdev
;
3852 struct mlx5e_priv
*priv
;
3854 netdev
= alloc_etherdev_mqs(sizeof(struct mlx5e_priv
),
3855 nch
* profile
->max_tc
,
3858 mlx5_core_err(mdev
, "alloc_etherdev_mqs() failed\n");
3862 profile
->init(mdev
, netdev
, profile
, ppriv
);
3864 netif_carrier_off(netdev
);
3866 priv
= netdev_priv(netdev
);
3868 priv
->wq
= create_singlethread_workqueue("mlx5e");
3870 goto err_cleanup_nic
;
3875 profile
->cleanup(priv
);
3876 free_netdev(netdev
);
3881 int mlx5e_attach_netdev(struct mlx5_core_dev
*mdev
, struct net_device
*netdev
)
3883 const struct mlx5e_profile
*profile
;
3884 struct mlx5e_priv
*priv
;
3888 priv
= netdev_priv(netdev
);
3889 profile
= priv
->profile
;
3890 clear_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
3892 err
= profile
->init_tx(priv
);
3896 err
= mlx5e_open_drop_rq(priv
);
3898 mlx5_core_err(mdev
, "open drop rq failed, %d\n", err
);
3899 goto err_cleanup_tx
;
3902 err
= profile
->init_rx(priv
);
3904 goto err_close_drop_rq
;
3906 mlx5e_create_q_counter(priv
);
3908 mlx5e_init_l2_addr(priv
);
3910 /* MTU range: 68 - hw-specific max */
3911 netdev
->min_mtu
= ETH_MIN_MTU
;
3912 mlx5_query_port_max_mtu(priv
->mdev
, &max_mtu
, 1);
3913 netdev
->max_mtu
= MLX5E_HW2SW_MTU(max_mtu
);
3915 mlx5e_set_dev_port_mtu(netdev
);
3917 if (profile
->enable
)
3918 profile
->enable(priv
);
3921 if (netif_running(netdev
))
3923 netif_device_attach(netdev
);
3929 mlx5e_close_drop_rq(priv
);
3932 profile
->cleanup_tx(priv
);
3938 static void mlx5e_register_vport_rep(struct mlx5_core_dev
*mdev
)
3940 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
3941 int total_vfs
= MLX5_TOTAL_VPORTS(mdev
);
3945 if (!MLX5_CAP_GEN(mdev
, vport_group_manager
))
3948 mlx5_query_nic_vport_mac_address(mdev
, 0, mac
);
3950 for (vport
= 1; vport
< total_vfs
; vport
++) {
3951 struct mlx5_eswitch_rep rep
;
3953 rep
.load
= mlx5e_vport_rep_load
;
3954 rep
.unload
= mlx5e_vport_rep_unload
;
3956 ether_addr_copy(rep
.hw_id
, mac
);
3957 mlx5_eswitch_register_vport_rep(esw
, vport
, &rep
);
3961 static void mlx5e_unregister_vport_rep(struct mlx5_core_dev
*mdev
)
3963 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
3964 int total_vfs
= MLX5_TOTAL_VPORTS(mdev
);
3967 if (!MLX5_CAP_GEN(mdev
, vport_group_manager
))
3970 for (vport
= 1; vport
< total_vfs
; vport
++)
3971 mlx5_eswitch_unregister_vport_rep(esw
, vport
);
3974 void mlx5e_detach_netdev(struct mlx5_core_dev
*mdev
, struct net_device
*netdev
)
3976 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
3977 const struct mlx5e_profile
*profile
= priv
->profile
;
3979 set_bit(MLX5E_STATE_DESTROYING
, &priv
->state
);
3982 if (netif_running(netdev
))
3983 mlx5e_close(netdev
);
3984 netif_device_detach(netdev
);
3987 if (profile
->disable
)
3988 profile
->disable(priv
);
3989 flush_workqueue(priv
->wq
);
3991 mlx5e_destroy_q_counter(priv
);
3992 profile
->cleanup_rx(priv
);
3993 mlx5e_close_drop_rq(priv
);
3994 profile
->cleanup_tx(priv
);
3995 cancel_delayed_work_sync(&priv
->update_stats_work
);
3998 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3999 * hardware contexts and to connect it to the current netdev.
4001 static int mlx5e_attach(struct mlx5_core_dev
*mdev
, void *vpriv
)
4003 struct mlx5e_priv
*priv
= vpriv
;
4004 struct net_device
*netdev
= priv
->netdev
;
4007 if (netif_device_present(netdev
))
4010 err
= mlx5e_create_mdev_resources(mdev
);
4014 err
= mlx5e_attach_netdev(mdev
, netdev
);
4016 mlx5e_destroy_mdev_resources(mdev
);
4020 mlx5e_register_vport_rep(mdev
);
4024 static void mlx5e_detach(struct mlx5_core_dev
*mdev
, void *vpriv
)
4026 struct mlx5e_priv
*priv
= vpriv
;
4027 struct net_device
*netdev
= priv
->netdev
;
4029 if (!netif_device_present(netdev
))
4032 mlx5e_unregister_vport_rep(mdev
);
4033 mlx5e_detach_netdev(mdev
, netdev
);
4034 mlx5e_destroy_mdev_resources(mdev
);
4037 static void *mlx5e_add(struct mlx5_core_dev
*mdev
)
4039 struct mlx5_eswitch
*esw
= mdev
->priv
.eswitch
;
4040 int total_vfs
= MLX5_TOTAL_VPORTS(mdev
);
4045 struct net_device
*netdev
;
4047 err
= mlx5e_check_required_hca_cap(mdev
);
4051 if (MLX5_CAP_GEN(mdev
, vport_group_manager
))
4052 ppriv
= &esw
->offloads
.vport_reps
[0];
4054 netdev
= mlx5e_create_netdev(mdev
, &mlx5e_nic_profile
, ppriv
);
4056 mlx5_core_err(mdev
, "mlx5e_create_netdev failed\n");
4057 goto err_unregister_reps
;
4060 priv
= netdev_priv(netdev
);
4062 err
= mlx5e_attach(mdev
, priv
);
4064 mlx5_core_err(mdev
, "mlx5e_attach failed, %d\n", err
);
4065 goto err_destroy_netdev
;
4068 err
= register_netdev(netdev
);
4070 mlx5_core_err(mdev
, "register_netdev failed, %d\n", err
);
4077 mlx5e_detach(mdev
, priv
);
4080 mlx5e_destroy_netdev(mdev
, priv
);
4082 err_unregister_reps
:
4083 for (vport
= 1; vport
< total_vfs
; vport
++)
4084 mlx5_eswitch_unregister_vport_rep(esw
, vport
);
4089 void mlx5e_destroy_netdev(struct mlx5_core_dev
*mdev
, struct mlx5e_priv
*priv
)
4091 const struct mlx5e_profile
*profile
= priv
->profile
;
4092 struct net_device
*netdev
= priv
->netdev
;
4094 destroy_workqueue(priv
->wq
);
4095 if (profile
->cleanup
)
4096 profile
->cleanup(priv
);
4097 free_netdev(netdev
);
4100 static void mlx5e_remove(struct mlx5_core_dev
*mdev
, void *vpriv
)
4102 struct mlx5e_priv
*priv
= vpriv
;
4104 unregister_netdev(priv
->netdev
);
4105 mlx5e_detach(mdev
, vpriv
);
4106 mlx5e_destroy_netdev(mdev
, priv
);
4109 static void *mlx5e_get_netdev(void *vpriv
)
4111 struct mlx5e_priv
*priv
= vpriv
;
4113 return priv
->netdev
;
4116 static struct mlx5_interface mlx5e_interface
= {
4118 .remove
= mlx5e_remove
,
4119 .attach
= mlx5e_attach
,
4120 .detach
= mlx5e_detach
,
4121 .event
= mlx5e_async_event
,
4122 .protocol
= MLX5_INTERFACE_PROTOCOL_ETH
,
4123 .get_dev
= mlx5e_get_netdev
,
4126 void mlx5e_init(void)
4128 mlx5e_build_ptys2ethtool_map();
4129 mlx5_register_interface(&mlx5e_interface
);
4132 void mlx5e_cleanup(void)
4134 mlx5_unregister_interface(&mlx5e_interface
);