2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
43 #include "ipoib/ipoib.h"
44 #include "en_accel/ipsec_rxtx.h"
45 #include "lib/clock.h"
47 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config
*config
)
49 return config
->rx_filter
== HWTSTAMP_FILTER_ALL
;
52 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq
*cq
, u32 cqcc
,
55 u32 ci
= cqcc
& cq
->wq
.sz_m1
;
57 memcpy(data
, mlx5_cqwq_get_wqe(&cq
->wq
, ci
), sizeof(struct mlx5_cqe64
));
60 static inline void mlx5e_read_title_slot(struct mlx5e_rq
*rq
,
61 struct mlx5e_cq
*cq
, u32 cqcc
)
63 mlx5e_read_cqe_slot(cq
, cqcc
, &cq
->title
);
64 cq
->decmprs_left
= be32_to_cpu(cq
->title
.byte_cnt
);
65 cq
->decmprs_wqe_counter
= be16_to_cpu(cq
->title
.wqe_counter
);
66 rq
->stats
.cqe_compress_blks
++;
69 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq
*cq
, u32 cqcc
)
71 mlx5e_read_cqe_slot(cq
, cqcc
, cq
->mini_arr
);
75 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq
*cq
, u32 cqcc
, int n
)
77 u8 op_own
= (cqcc
>> cq
->wq
.log_sz
) & 1;
78 u32 wq_sz
= 1 << cq
->wq
.log_sz
;
79 u32 ci
= cqcc
& cq
->wq
.sz_m1
;
80 u32 ci_top
= min_t(u32
, wq_sz
, ci
+ n
);
82 for (; ci
< ci_top
; ci
++, n
--) {
83 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, ci
);
88 if (unlikely(ci
== wq_sz
)) {
90 for (ci
= 0; ci
< n
; ci
++) {
91 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, ci
);
98 static inline void mlx5e_decompress_cqe(struct mlx5e_rq
*rq
,
99 struct mlx5e_cq
*cq
, u32 cqcc
)
101 cq
->title
.byte_cnt
= cq
->mini_arr
[cq
->mini_arr_idx
].byte_cnt
;
102 cq
->title
.check_sum
= cq
->mini_arr
[cq
->mini_arr_idx
].checksum
;
103 cq
->title
.op_own
&= 0xf0;
104 cq
->title
.op_own
|= 0x01 & (cqcc
>> cq
->wq
.log_sz
);
105 cq
->title
.wqe_counter
= cpu_to_be16(cq
->decmprs_wqe_counter
);
107 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
)
108 cq
->decmprs_wqe_counter
+=
109 mpwrq_get_cqe_consumed_strides(&cq
->title
);
111 cq
->decmprs_wqe_counter
=
112 (cq
->decmprs_wqe_counter
+ 1) & rq
->wq
.sz_m1
;
115 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq
*rq
,
116 struct mlx5e_cq
*cq
, u32 cqcc
)
118 mlx5e_decompress_cqe(rq
, cq
, cqcc
);
119 cq
->title
.rss_hash_type
= 0;
120 cq
->title
.rss_hash_result
= 0;
123 static inline u32
mlx5e_decompress_cqes_cont(struct mlx5e_rq
*rq
,
125 int update_owner_only
,
128 u32 cqcc
= cq
->wq
.cc
+ update_owner_only
;
132 cqe_count
= min_t(u32
, cq
->decmprs_left
, budget_rem
);
134 for (i
= update_owner_only
; i
< cqe_count
;
135 i
++, cq
->mini_arr_idx
++, cqcc
++) {
136 if (cq
->mini_arr_idx
== MLX5_MINI_CQE_ARRAY_SIZE
)
137 mlx5e_read_mini_arr_slot(cq
, cqcc
);
139 mlx5e_decompress_cqe_no_hash(rq
, cq
, cqcc
);
140 rq
->handle_rx_cqe(rq
, &cq
->title
);
142 mlx5e_cqes_update_owner(cq
, cq
->wq
.cc
, cqcc
- cq
->wq
.cc
);
144 cq
->decmprs_left
-= cqe_count
;
145 rq
->stats
.cqe_compress_pkts
+= cqe_count
;
150 static inline u32
mlx5e_decompress_cqes_start(struct mlx5e_rq
*rq
,
154 mlx5e_read_title_slot(rq
, cq
, cq
->wq
.cc
);
155 mlx5e_read_mini_arr_slot(cq
, cq
->wq
.cc
+ 1);
156 mlx5e_decompress_cqe(rq
, cq
, cq
->wq
.cc
);
157 rq
->handle_rx_cqe(rq
, &cq
->title
);
160 return mlx5e_decompress_cqes_cont(rq
, cq
, 1, budget_rem
) - 1;
163 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
165 static inline bool mlx5e_page_is_reserved(struct page
*page
)
167 return page_is_pfmemalloc(page
) || page_to_nid(page
) != numa_mem_id();
170 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq
*rq
,
171 struct mlx5e_dma_info
*dma_info
)
173 struct mlx5e_page_cache
*cache
= &rq
->page_cache
;
174 u32 tail_next
= (cache
->tail
+ 1) & (MLX5E_CACHE_SIZE
- 1);
176 if (tail_next
== cache
->head
) {
177 rq
->stats
.cache_full
++;
181 if (unlikely(mlx5e_page_is_reserved(dma_info
->page
))) {
182 rq
->stats
.cache_waive
++;
186 cache
->page_cache
[cache
->tail
] = *dma_info
;
187 cache
->tail
= tail_next
;
191 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq
*rq
,
192 struct mlx5e_dma_info
*dma_info
)
194 struct mlx5e_page_cache
*cache
= &rq
->page_cache
;
196 if (unlikely(cache
->head
== cache
->tail
)) {
197 rq
->stats
.cache_empty
++;
201 if (page_ref_count(cache
->page_cache
[cache
->head
].page
) != 1) {
202 rq
->stats
.cache_busy
++;
206 *dma_info
= cache
->page_cache
[cache
->head
];
207 cache
->head
= (cache
->head
+ 1) & (MLX5E_CACHE_SIZE
- 1);
208 rq
->stats
.cache_reuse
++;
210 dma_sync_single_for_device(rq
->pdev
, dma_info
->addr
,
216 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq
*rq
,
217 struct mlx5e_dma_info
*dma_info
)
219 if (mlx5e_rx_cache_get(rq
, dma_info
))
222 dma_info
->page
= dev_alloc_pages(rq
->buff
.page_order
);
223 if (unlikely(!dma_info
->page
))
226 dma_info
->addr
= dma_map_page(rq
->pdev
, dma_info
->page
, 0,
227 RQ_PAGE_SIZE(rq
), rq
->buff
.map_dir
);
228 if (unlikely(dma_mapping_error(rq
->pdev
, dma_info
->addr
))) {
229 put_page(dma_info
->page
);
230 dma_info
->page
= NULL
;
237 void mlx5e_page_release(struct mlx5e_rq
*rq
, struct mlx5e_dma_info
*dma_info
,
240 if (likely(recycle
) && mlx5e_rx_cache_put(rq
, dma_info
))
243 dma_unmap_page(rq
->pdev
, dma_info
->addr
, RQ_PAGE_SIZE(rq
),
245 put_page(dma_info
->page
);
248 static inline bool mlx5e_page_reuse(struct mlx5e_rq
*rq
,
249 struct mlx5e_wqe_frag_info
*wi
)
251 return rq
->wqe
.page_reuse
&& wi
->di
.page
&&
252 (wi
->offset
+ rq
->wqe
.frag_sz
<= RQ_PAGE_SIZE(rq
)) &&
253 !mlx5e_page_is_reserved(wi
->di
.page
);
256 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq
*rq
, struct mlx5e_rx_wqe
*wqe
, u16 ix
)
258 struct mlx5e_wqe_frag_info
*wi
= &rq
->wqe
.frag_info
[ix
];
260 /* check if page exists, hence can be reused */
262 if (unlikely(mlx5e_page_alloc_mapped(rq
, &wi
->di
)))
267 wqe
->data
.addr
= cpu_to_be64(wi
->di
.addr
+ wi
->offset
+ rq
->buff
.headroom
);
271 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq
*rq
,
272 struct mlx5e_wqe_frag_info
*wi
)
274 mlx5e_page_release(rq
, &wi
->di
, true);
278 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq
*rq
,
279 struct mlx5e_wqe_frag_info
*wi
)
281 if (mlx5e_page_reuse(rq
, wi
)) {
282 rq
->stats
.page_reuse
++;
286 mlx5e_free_rx_wqe(rq
, wi
);
289 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq
*rq
, u16 ix
)
291 struct mlx5e_wqe_frag_info
*wi
= &rq
->wqe
.frag_info
[ix
];
294 mlx5e_free_rx_wqe(rq
, wi
);
297 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq
*rq
)
299 return rq
->mpwqe
.num_strides
>> MLX5_MPWRQ_WQE_PAGE_ORDER
;
302 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq
*rq
,
304 struct mlx5e_mpw_info
*wi
,
305 u32 page_idx
, u32 frag_offset
,
308 unsigned int truesize
= ALIGN(len
, BIT(rq
->mpwqe
.log_stride_sz
));
310 dma_sync_single_for_cpu(rq
->pdev
,
311 wi
->umr
.dma_info
[page_idx
].addr
+ frag_offset
,
312 len
, DMA_FROM_DEVICE
);
313 wi
->skbs_frags
[page_idx
]++;
314 skb_add_rx_frag(skb
, skb_shinfo(skb
)->nr_frags
,
315 wi
->umr
.dma_info
[page_idx
].page
, frag_offset
,
320 mlx5e_copy_skb_header_mpwqe(struct device
*pdev
,
322 struct mlx5e_mpw_info
*wi
,
323 u32 page_idx
, u32 offset
,
326 u16 headlen_pg
= min_t(u32
, headlen
, PAGE_SIZE
- offset
);
327 struct mlx5e_dma_info
*dma_info
= &wi
->umr
.dma_info
[page_idx
];
330 /* Aligning len to sizeof(long) optimizes memcpy performance */
331 len
= ALIGN(headlen_pg
, sizeof(long));
332 dma_sync_single_for_cpu(pdev
, dma_info
->addr
+ offset
, len
,
334 skb_copy_to_linear_data_offset(skb
, 0,
335 page_address(dma_info
->page
) + offset
,
337 if (unlikely(offset
+ headlen
> PAGE_SIZE
)) {
340 len
= ALIGN(headlen
- headlen_pg
, sizeof(long));
341 dma_sync_single_for_cpu(pdev
, dma_info
->addr
, len
,
343 skb_copy_to_linear_data_offset(skb
, headlen_pg
,
344 page_address(dma_info
->page
),
349 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq
*rq
, u16 ix
)
351 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
352 struct mlx5e_icosq
*sq
= &rq
->channel
->icosq
;
353 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
354 struct mlx5e_umr_wqe
*wqe
;
355 u8 num_wqebbs
= DIV_ROUND_UP(sizeof(*wqe
), MLX5_SEND_WQE_BB
);
358 /* fill sq edge with nops to avoid wqe wrap around */
359 while ((pi
= (sq
->pc
& wq
->sz_m1
)) > sq
->edge
) {
360 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_NOP
;
361 mlx5e_post_nop(wq
, sq
->sqn
, &sq
->pc
);
364 wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
365 memcpy(wqe
, &wi
->umr
.wqe
, sizeof(*wqe
));
366 wqe
->ctrl
.opmod_idx_opcode
=
367 cpu_to_be32((sq
->pc
<< MLX5_WQE_CTRL_WQE_INDEX_SHIFT
) |
370 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_UMR
;
371 sq
->pc
+= num_wqebbs
;
372 mlx5e_notify_hw(&sq
->wq
, sq
->pc
, sq
->uar_map
, &wqe
->ctrl
);
375 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq
*rq
,
378 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
379 int pg_strides
= mlx5e_mpwqe_strides_per_page(rq
);
380 struct mlx5e_dma_info
*dma_info
= &wi
->umr
.dma_info
[0];
384 for (i
= 0; i
< MLX5_MPWRQ_PAGES_PER_WQE
; i
++, dma_info
++) {
385 err
= mlx5e_page_alloc_mapped(rq
, dma_info
);
388 wi
->umr
.mtt
[i
] = cpu_to_be64(dma_info
->addr
| MLX5_EN_WR
);
389 page_ref_add(dma_info
->page
, pg_strides
);
392 memset(wi
->skbs_frags
, 0, sizeof(*wi
->skbs_frags
) * MLX5_MPWRQ_PAGES_PER_WQE
);
393 wi
->consumed_strides
= 0;
400 page_ref_sub(dma_info
->page
, pg_strides
);
401 mlx5e_page_release(rq
, dma_info
, true);
407 void mlx5e_free_rx_mpwqe(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
)
409 int pg_strides
= mlx5e_mpwqe_strides_per_page(rq
);
410 struct mlx5e_dma_info
*dma_info
= &wi
->umr
.dma_info
[0];
413 for (i
= 0; i
< MLX5_MPWRQ_PAGES_PER_WQE
; i
++, dma_info
++) {
414 page_ref_sub(dma_info
->page
, pg_strides
- wi
->skbs_frags
[i
]);
415 mlx5e_page_release(rq
, dma_info
, true);
419 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq
*rq
)
421 struct mlx5_wq_ll
*wq
= &rq
->wq
;
422 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(wq
, wq
->head
);
424 rq
->mpwqe
.umr_in_progress
= false;
426 mlx5_wq_ll_push(wq
, be16_to_cpu(wqe
->next
.next_wqe_index
));
428 /* ensure wqes are visible to device before updating doorbell record */
431 mlx5_wq_ll_update_db_record(wq
);
434 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
)
438 err
= mlx5e_alloc_rx_umr_mpwqe(rq
, ix
);
440 rq
->stats
.buff_alloc_err
++;
443 rq
->mpwqe
.umr_in_progress
= true;
444 mlx5e_post_umr_wqe(rq
, ix
);
448 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
)
450 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
452 mlx5e_free_rx_mpwqe(rq
, wi
);
455 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
)
457 struct mlx5_wq_ll
*wq
= &rq
->wq
;
460 if (unlikely(!MLX5E_TEST_BIT(rq
->state
, MLX5E_RQ_STATE_ENABLED
)))
463 if (mlx5_wq_ll_is_full(wq
))
467 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(wq
, wq
->head
);
469 err
= mlx5e_alloc_rx_wqe(rq
, wqe
, wq
->head
);
471 rq
->stats
.buff_alloc_err
++;
475 mlx5_wq_ll_push(wq
, be16_to_cpu(wqe
->next
.next_wqe_index
));
476 } while (!mlx5_wq_ll_is_full(wq
));
478 /* ensure wqes are visible to device before updating doorbell record */
481 mlx5_wq_ll_update_db_record(wq
);
486 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq
*cq
,
487 struct mlx5e_icosq
*sq
,
489 struct mlx5_cqe64
*cqe
)
491 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
492 u16 ci
= be16_to_cpu(cqe
->wqe_counter
) & wq
->sz_m1
;
493 struct mlx5e_sq_wqe_info
*icowi
= &sq
->db
.ico_wqe
[ci
];
495 mlx5_cqwq_pop(&cq
->wq
);
497 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_REQ
)) {
498 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
503 if (likely(icowi
->opcode
== MLX5_OPCODE_UMR
)) {
504 mlx5e_post_rx_mpwqe(rq
);
508 if (unlikely(icowi
->opcode
!= MLX5_OPCODE_NOP
))
510 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
514 static void mlx5e_poll_ico_cq(struct mlx5e_cq
*cq
, struct mlx5e_rq
*rq
)
516 struct mlx5e_icosq
*sq
= container_of(cq
, struct mlx5e_icosq
, cq
);
517 struct mlx5_cqe64
*cqe
;
519 if (unlikely(!MLX5E_TEST_BIT(sq
->state
, MLX5E_SQ_STATE_ENABLED
)))
522 cqe
= mlx5_cqwq_get_cqe(&cq
->wq
);
526 /* by design, there's only a single cqe */
527 mlx5e_poll_ico_single_cqe(cq
, sq
, rq
, cqe
);
529 mlx5_cqwq_update_db_record(&cq
->wq
);
532 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq
*rq
)
534 struct mlx5_wq_ll
*wq
= &rq
->wq
;
536 if (unlikely(!MLX5E_TEST_BIT(rq
->state
, MLX5E_RQ_STATE_ENABLED
)))
539 mlx5e_poll_ico_cq(&rq
->channel
->icosq
.cq
, rq
);
541 if (mlx5_wq_ll_is_full(wq
))
544 if (!rq
->mpwqe
.umr_in_progress
)
545 mlx5e_alloc_rx_mpwqe(rq
, wq
->head
);
550 static void mlx5e_lro_update_hdr(struct sk_buff
*skb
, struct mlx5_cqe64
*cqe
,
553 struct ethhdr
*eth
= (struct ethhdr
*)(skb
->data
);
555 int network_depth
= 0;
560 u8 l4_hdr_type
= get_cqe_l4_hdr_type(cqe
);
561 u8 tcp_ack
= (l4_hdr_type
== CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA
) ||
562 (l4_hdr_type
== CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA
);
564 proto
= __vlan_get_protocol(skb
, eth
->h_proto
, &network_depth
);
566 tot_len
= cqe_bcnt
- network_depth
;
567 ip_p
= skb
->data
+ network_depth
;
569 if (proto
== htons(ETH_P_IP
)) {
570 struct iphdr
*ipv4
= ip_p
;
572 tcp
= ip_p
+ sizeof(struct iphdr
);
573 skb_shinfo(skb
)->gso_type
= SKB_GSO_TCPV4
;
575 ipv4
->ttl
= cqe
->lro_min_ttl
;
576 ipv4
->tot_len
= cpu_to_be16(tot_len
);
578 ipv4
->check
= ip_fast_csum((unsigned char *)ipv4
,
581 struct ipv6hdr
*ipv6
= ip_p
;
583 tcp
= ip_p
+ sizeof(struct ipv6hdr
);
584 skb_shinfo(skb
)->gso_type
= SKB_GSO_TCPV6
;
586 ipv6
->hop_limit
= cqe
->lro_min_ttl
;
587 ipv6
->payload_len
= cpu_to_be16(tot_len
-
588 sizeof(struct ipv6hdr
));
591 tcp
->psh
= get_cqe_lro_tcppsh(cqe
);
595 tcp
->ack_seq
= cqe
->lro_ack_seq_num
;
596 tcp
->window
= cqe
->lro_tcp_win
;
600 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64
*cqe
,
603 u8 cht
= cqe
->rss_hash_type
;
604 int ht
= (cht
& CQE_RSS_HTYPE_L4
) ? PKT_HASH_TYPE_L4
:
605 (cht
& CQE_RSS_HTYPE_IP
) ? PKT_HASH_TYPE_L3
:
607 skb_set_hash(skb
, be32_to_cpu(cqe
->rss_hash_result
), ht
);
610 static inline bool is_last_ethertype_ip(struct sk_buff
*skb
, int *network_depth
)
612 __be16 ethertype
= ((struct ethhdr
*)skb
->data
)->h_proto
;
614 ethertype
= __vlan_get_protocol(skb
, ethertype
, network_depth
);
615 return (ethertype
== htons(ETH_P_IP
) || ethertype
== htons(ETH_P_IPV6
));
618 static inline void mlx5e_handle_csum(struct net_device
*netdev
,
619 struct mlx5_cqe64
*cqe
,
624 int network_depth
= 0;
626 if (unlikely(!(netdev
->features
& NETIF_F_RXCSUM
)))
630 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
631 rq
->stats
.csum_unnecessary
++;
635 if (is_last_ethertype_ip(skb
, &network_depth
)) {
636 skb
->ip_summed
= CHECKSUM_COMPLETE
;
637 skb
->csum
= csum_unfold((__force __sum16
)cqe
->check_sum
);
638 if (network_depth
> ETH_HLEN
)
639 /* CQE csum is calculated from the IP header and does
640 * not cover VLAN headers (if present). This will add
641 * the checksum manually.
643 skb
->csum
= csum_partial(skb
->data
+ ETH_HLEN
,
644 network_depth
- ETH_HLEN
,
646 rq
->stats
.csum_complete
++;
650 if (likely((cqe
->hds_ip_ext
& CQE_L3_OK
) &&
651 (cqe
->hds_ip_ext
& CQE_L4_OK
))) {
652 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
653 if (cqe_is_tunneled(cqe
)) {
655 skb
->encapsulation
= 1;
656 rq
->stats
.csum_unnecessary_inner
++;
659 rq
->stats
.csum_unnecessary
++;
663 skb
->ip_summed
= CHECKSUM_NONE
;
664 rq
->stats
.csum_none
++;
667 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64
*cqe
,
672 struct net_device
*netdev
= rq
->netdev
;
675 skb
->mac_len
= ETH_HLEN
;
676 lro_num_seg
= be32_to_cpu(cqe
->srqn
) >> 24;
677 if (lro_num_seg
> 1) {
678 mlx5e_lro_update_hdr(skb
, cqe
, cqe_bcnt
);
679 skb_shinfo(skb
)->gso_size
= DIV_ROUND_UP(cqe_bcnt
, lro_num_seg
);
680 /* Subtract one since we already counted this as one
681 * "regular" packet in mlx5e_complete_rx_cqe()
683 rq
->stats
.packets
+= lro_num_seg
- 1;
684 rq
->stats
.lro_packets
++;
685 rq
->stats
.lro_bytes
+= cqe_bcnt
;
688 if (unlikely(mlx5e_rx_hw_stamp(rq
->tstamp
)))
689 skb_hwtstamps(skb
)->hwtstamp
=
690 mlx5_timecounter_cyc2time(rq
->clock
, get_cqe_ts(cqe
));
692 skb_record_rx_queue(skb
, rq
->ix
);
694 if (likely(netdev
->features
& NETIF_F_RXHASH
))
695 mlx5e_skb_set_hash(cqe
, skb
);
697 if (cqe_has_vlan(cqe
)) {
698 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
699 be16_to_cpu(cqe
->vlan_info
));
700 rq
->stats
.removed_vlan_packets
++;
703 skb
->mark
= be32_to_cpu(cqe
->sop_drop_qpn
) & MLX5E_TC_FLOW_ID_MASK
;
705 mlx5e_handle_csum(netdev
, cqe
, rq
, skb
, !!lro_num_seg
);
706 skb
->protocol
= eth_type_trans(skb
, netdev
);
709 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq
*rq
,
710 struct mlx5_cqe64
*cqe
,
715 rq
->stats
.bytes
+= cqe_bcnt
;
716 mlx5e_build_rx_skb(cqe
, cqe_bcnt
, rq
, skb
);
719 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq
*sq
)
721 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
722 struct mlx5e_tx_wqe
*wqe
;
723 u16 pi
= (sq
->pc
- 1) & wq
->sz_m1
; /* last pi */
725 wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
727 mlx5e_notify_hw(wq
, sq
->pc
, sq
->uar_map
, &wqe
->ctrl
);
730 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq
*rq
,
731 struct mlx5e_dma_info
*di
,
732 const struct xdp_buff
*xdp
)
734 struct mlx5e_xdpsq
*sq
= &rq
->xdpsq
;
735 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
736 u16 pi
= sq
->pc
& wq
->sz_m1
;
737 struct mlx5e_tx_wqe
*wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
739 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
740 struct mlx5_wqe_eth_seg
*eseg
= &wqe
->eth
;
741 struct mlx5_wqe_data_seg
*dseg
;
743 ptrdiff_t data_offset
= xdp
->data
- xdp
->data_hard_start
;
744 dma_addr_t dma_addr
= di
->addr
+ data_offset
;
745 unsigned int dma_len
= xdp
->data_end
- xdp
->data
;
749 if (unlikely(dma_len
< MLX5E_XDP_MIN_INLINE
||
750 MLX5E_SW2HW_MTU(rq
->channel
->priv
, rq
->netdev
->mtu
) < dma_len
)) {
751 rq
->stats
.xdp_drop
++;
755 if (unlikely(!mlx5e_wqc_has_room_for(wq
, sq
->cc
, sq
->pc
, 1))) {
756 if (sq
->db
.doorbell
) {
757 /* SQ is full, ring doorbell */
758 mlx5e_xmit_xdp_doorbell(sq
);
759 sq
->db
.doorbell
= false;
761 rq
->stats
.xdp_tx_full
++;
765 dma_sync_single_for_device(sq
->pdev
, dma_addr
, dma_len
, PCI_DMA_TODEVICE
);
769 dseg
= (struct mlx5_wqe_data_seg
*)eseg
+ 1;
771 /* copy the inline part if required */
772 if (sq
->min_inline_mode
!= MLX5_INLINE_MODE_NONE
) {
773 memcpy(eseg
->inline_hdr
.start
, xdp
->data
, MLX5E_XDP_MIN_INLINE
);
774 eseg
->inline_hdr
.sz
= cpu_to_be16(MLX5E_XDP_MIN_INLINE
);
775 dma_len
-= MLX5E_XDP_MIN_INLINE
;
776 dma_addr
+= MLX5E_XDP_MIN_INLINE
;
780 /* write the dma part */
781 dseg
->addr
= cpu_to_be64(dma_addr
);
782 dseg
->byte_count
= cpu_to_be32(dma_len
);
784 cseg
->opmod_idx_opcode
= cpu_to_be32((sq
->pc
<< 8) | MLX5_OPCODE_SEND
);
786 /* move page to reference to sq responsibility,
787 * and mark so it's not put back in page-cache.
789 rq
->wqe
.xdp_xmit
= true;
793 sq
->db
.doorbell
= true;
799 /* returns true if packet was consumed by xdp */
800 static inline int mlx5e_xdp_handle(struct mlx5e_rq
*rq
,
801 struct mlx5e_dma_info
*di
,
802 void *va
, u16
*rx_headroom
, u32
*len
)
804 const struct bpf_prog
*prog
= READ_ONCE(rq
->xdp_prog
);
811 xdp
.data
= va
+ *rx_headroom
;
812 xdp_set_data_meta_invalid(&xdp
);
813 xdp
.data_end
= xdp
.data
+ *len
;
814 xdp
.data_hard_start
= va
;
816 act
= bpf_prog_run_xdp(prog
, &xdp
);
819 *rx_headroom
= xdp
.data
- xdp
.data_hard_start
;
820 *len
= xdp
.data_end
- xdp
.data
;
823 if (unlikely(!mlx5e_xmit_xdp_frame(rq
, di
, &xdp
)))
824 trace_xdp_exception(rq
->netdev
, prog
, act
);
827 bpf_warn_invalid_xdp_action(act
);
829 trace_xdp_exception(rq
->netdev
, prog
, act
);
831 rq
->stats
.xdp_drop
++;
837 struct sk_buff
*skb_from_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
,
838 struct mlx5e_wqe_frag_info
*wi
, u32 cqe_bcnt
)
840 struct mlx5e_dma_info
*di
= &wi
->di
;
841 u16 rx_headroom
= rq
->buff
.headroom
;
847 va
= page_address(di
->page
) + wi
->offset
;
848 data
= va
+ rx_headroom
;
849 frag_size
= MLX5_SKB_FRAG_SZ(rx_headroom
+ cqe_bcnt
);
851 dma_sync_single_range_for_cpu(rq
->pdev
,
852 di
->addr
+ wi
->offset
,
856 wi
->offset
+= frag_size
;
858 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_RESP_SEND
)) {
864 consumed
= mlx5e_xdp_handle(rq
, di
, va
, &rx_headroom
, &cqe_bcnt
);
867 return NULL
; /* page/packet was consumed by XDP */
869 skb
= build_skb(va
, frag_size
);
870 if (unlikely(!skb
)) {
871 rq
->stats
.buff_alloc_err
++;
875 /* queue up for recycling/reuse */
876 page_ref_inc(di
->page
);
878 skb_reserve(skb
, rx_headroom
);
879 skb_put(skb
, cqe_bcnt
);
884 void mlx5e_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
886 struct mlx5e_wqe_frag_info
*wi
;
887 struct mlx5e_rx_wqe
*wqe
;
888 __be16 wqe_counter_be
;
893 wqe_counter_be
= cqe
->wqe_counter
;
894 wqe_counter
= be16_to_cpu(wqe_counter_be
);
895 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
896 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
897 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
899 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
901 /* probably for XDP */
902 if (rq
->wqe
.xdp_xmit
) {
904 rq
->wqe
.xdp_xmit
= false;
905 /* do not return page to cache, it will be returned on XDP_TX completion */
908 /* probably an XDP_DROP, save the page-reuse checks */
909 mlx5e_free_rx_wqe(rq
, wi
);
913 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
914 napi_gro_receive(rq
->cq
.napi
, skb
);
916 mlx5e_free_rx_wqe_reuse(rq
, wi
);
918 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
919 &wqe
->next
.next_wqe_index
);
922 #ifdef CONFIG_MLX5_ESWITCH
923 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
925 struct net_device
*netdev
= rq
->netdev
;
926 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
927 struct mlx5e_rep_priv
*rpriv
= priv
->ppriv
;
928 struct mlx5_eswitch_rep
*rep
= rpriv
->rep
;
929 struct mlx5e_wqe_frag_info
*wi
;
930 struct mlx5e_rx_wqe
*wqe
;
932 __be16 wqe_counter_be
;
936 wqe_counter_be
= cqe
->wqe_counter
;
937 wqe_counter
= be16_to_cpu(wqe_counter_be
);
938 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
939 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
940 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
942 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
944 if (rq
->wqe
.xdp_xmit
) {
946 rq
->wqe
.xdp_xmit
= false;
947 /* do not return page to cache, it will be returned on XDP_TX completion */
950 /* probably an XDP_DROP, save the page-reuse checks */
951 mlx5e_free_rx_wqe(rq
, wi
);
955 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
957 if (rep
->vlan
&& skb_vlan_tag_present(skb
))
960 napi_gro_receive(rq
->cq
.napi
, skb
);
962 mlx5e_free_rx_wqe_reuse(rq
, wi
);
964 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
965 &wqe
->next
.next_wqe_index
);
969 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq
*rq
,
970 struct mlx5_cqe64
*cqe
,
971 struct mlx5e_mpw_info
*wi
,
975 u16 stride_ix
= mpwrq_get_cqe_stride_index(cqe
);
976 u32 wqe_offset
= stride_ix
<< rq
->mpwqe
.log_stride_sz
;
977 u32 head_offset
= wqe_offset
& (PAGE_SIZE
- 1);
978 u32 page_idx
= wqe_offset
>> PAGE_SHIFT
;
979 u32 head_page_idx
= page_idx
;
980 u16 headlen
= min_t(u16
, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD
, cqe_bcnt
);
981 u32 frag_offset
= head_offset
+ headlen
;
982 u16 byte_cnt
= cqe_bcnt
- headlen
;
984 if (unlikely(frag_offset
>= PAGE_SIZE
)) {
986 frag_offset
-= PAGE_SIZE
;
990 u32 pg_consumed_bytes
=
991 min_t(u32
, PAGE_SIZE
- frag_offset
, byte_cnt
);
993 mlx5e_add_skb_frag_mpwqe(rq
, skb
, wi
, page_idx
, frag_offset
,
995 byte_cnt
-= pg_consumed_bytes
;
1000 mlx5e_copy_skb_header_mpwqe(rq
->pdev
, skb
, wi
, head_page_idx
,
1001 head_offset
, headlen
);
1002 /* skb linear part was allocated with headlen and aligned to long */
1003 skb
->tail
+= headlen
;
1004 skb
->len
+= headlen
;
1007 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1009 u16 cstrides
= mpwrq_get_cqe_consumed_strides(cqe
);
1010 u16 wqe_id
= be16_to_cpu(cqe
->wqe_id
);
1011 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[wqe_id
];
1012 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_id
);
1013 struct sk_buff
*skb
;
1016 wi
->consumed_strides
+= cstrides
;
1018 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_RESP_SEND
)) {
1019 rq
->stats
.wqe_err
++;
1023 if (unlikely(mpwrq_is_filler_cqe(cqe
))) {
1024 rq
->stats
.mpwqe_filler
++;
1028 skb
= napi_alloc_skb(rq
->cq
.napi
,
1029 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD
,
1031 if (unlikely(!skb
)) {
1032 rq
->stats
.buff_alloc_err
++;
1036 prefetchw(skb
->data
);
1037 cqe_bcnt
= mpwrq_get_cqe_byte_cnt(cqe
);
1039 mlx5e_mpwqe_fill_rx_skb(rq
, cqe
, wi
, cqe_bcnt
, skb
);
1040 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1041 napi_gro_receive(rq
->cq
.napi
, skb
);
1044 if (likely(wi
->consumed_strides
< rq
->mpwqe
.num_strides
))
1047 mlx5e_free_rx_mpwqe(rq
, wi
);
1048 mlx5_wq_ll_pop(&rq
->wq
, cqe
->wqe_id
, &wqe
->next
.next_wqe_index
);
1051 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
)
1053 struct mlx5e_rq
*rq
= container_of(cq
, struct mlx5e_rq
, cq
);
1054 struct mlx5e_xdpsq
*xdpsq
;
1055 struct mlx5_cqe64
*cqe
;
1058 if (unlikely(!MLX5E_TEST_BIT(rq
->state
, MLX5E_RQ_STATE_ENABLED
)))
1061 if (cq
->decmprs_left
)
1062 work_done
+= mlx5e_decompress_cqes_cont(rq
, cq
, 0, budget
);
1064 cqe
= mlx5_cqwq_get_cqe(&cq
->wq
);
1071 if (mlx5_get_cqe_format(cqe
) == MLX5_COMPRESSED
) {
1073 mlx5e_decompress_cqes_start(rq
, cq
,
1074 budget
- work_done
);
1078 mlx5_cqwq_pop(&cq
->wq
);
1080 rq
->handle_rx_cqe(rq
, cqe
);
1081 } while ((++work_done
< budget
) && (cqe
= mlx5_cqwq_get_cqe(&cq
->wq
)));
1083 if (xdpsq
->db
.doorbell
) {
1084 mlx5e_xmit_xdp_doorbell(xdpsq
);
1085 xdpsq
->db
.doorbell
= false;
1088 mlx5_cqwq_update_db_record(&cq
->wq
);
1090 /* ensure cq space is freed before enabling more cqes */
1096 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq
*cq
)
1098 struct mlx5e_xdpsq
*sq
;
1099 struct mlx5_cqe64
*cqe
;
1100 struct mlx5e_rq
*rq
;
1104 sq
= container_of(cq
, struct mlx5e_xdpsq
, cq
);
1106 if (unlikely(!MLX5E_TEST_BIT(sq
->state
, MLX5E_SQ_STATE_ENABLED
)))
1109 cqe
= mlx5_cqwq_get_cqe(&cq
->wq
);
1113 rq
= container_of(sq
, struct mlx5e_rq
, xdpsq
);
1115 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1116 * otherwise a cq overrun may occur
1125 mlx5_cqwq_pop(&cq
->wq
);
1127 wqe_counter
= be16_to_cpu(cqe
->wqe_counter
);
1130 struct mlx5e_dma_info
*di
;
1133 last_wqe
= (sqcc
== wqe_counter
);
1135 ci
= sqcc
& sq
->wq
.sz_m1
;
1136 di
= &sq
->db
.di
[ci
];
1139 /* Recycle RX page */
1140 mlx5e_page_release(rq
, di
, true);
1141 } while (!last_wqe
);
1142 } while ((++i
< MLX5E_TX_CQ_POLL_BUDGET
) && (cqe
= mlx5_cqwq_get_cqe(&cq
->wq
)));
1144 mlx5_cqwq_update_db_record(&cq
->wq
);
1146 /* ensure cq space is freed before enabling more cqes */
1150 return (i
== MLX5E_TX_CQ_POLL_BUDGET
);
1153 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq
*sq
)
1155 struct mlx5e_rq
*rq
= container_of(sq
, struct mlx5e_rq
, xdpsq
);
1156 struct mlx5e_dma_info
*di
;
1159 while (sq
->cc
!= sq
->pc
) {
1160 ci
= sq
->cc
& sq
->wq
.sz_m1
;
1161 di
= &sq
->db
.di
[ci
];
1164 mlx5e_page_release(rq
, di
, false);
1168 #ifdef CONFIG_MLX5_CORE_IPOIB
1170 #define MLX5_IB_GRH_DGID_OFFSET 24
1171 #define MLX5_GID_SIZE 16
1173 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq
*rq
,
1174 struct mlx5_cqe64
*cqe
,
1176 struct sk_buff
*skb
)
1178 struct net_device
*netdev
;
1179 char *pseudo_header
;
1184 qpn
= be32_to_cpu(cqe
->sop_drop_qpn
) & 0xffffff;
1185 netdev
= mlx5i_pkey_get_netdev(rq
->netdev
, qpn
);
1187 /* No mapping present, cannot process SKB. This might happen if a child
1188 * interface is going down while having unprocessed CQEs on parent RQ
1190 if (unlikely(!netdev
)) {
1191 /* TODO: add drop counters support */
1193 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn
);
1197 g
= (be32_to_cpu(cqe
->flags_rqpn
) >> 28) & 3;
1198 dgid
= skb
->data
+ MLX5_IB_GRH_DGID_OFFSET
;
1199 if ((!g
) || dgid
[0] != 0xff)
1200 skb
->pkt_type
= PACKET_HOST
;
1201 else if (memcmp(dgid
, netdev
->broadcast
+ 4, MLX5_GID_SIZE
) == 0)
1202 skb
->pkt_type
= PACKET_BROADCAST
;
1204 skb
->pkt_type
= PACKET_MULTICAST
;
1206 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1207 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1210 skb_pull(skb
, MLX5_IB_GRH_BYTES
);
1212 skb
->protocol
= *((__be16
*)(skb
->data
));
1214 skb
->ip_summed
= CHECKSUM_COMPLETE
;
1215 skb
->csum
= csum_unfold((__force __sum16
)cqe
->check_sum
);
1217 if (unlikely(mlx5e_rx_hw_stamp(rq
->tstamp
)))
1218 skb_hwtstamps(skb
)->hwtstamp
=
1219 mlx5_timecounter_cyc2time(rq
->clock
, get_cqe_ts(cqe
));
1221 skb_record_rx_queue(skb
, rq
->ix
);
1223 if (likely(netdev
->features
& NETIF_F_RXHASH
))
1224 mlx5e_skb_set_hash(cqe
, skb
);
1226 /* 20 bytes of ipoib header and 4 for encap existing */
1227 pseudo_header
= skb_push(skb
, MLX5_IPOIB_PSEUDO_LEN
);
1228 memset(pseudo_header
, 0, MLX5_IPOIB_PSEUDO_LEN
);
1229 skb_reset_mac_header(skb
);
1230 skb_pull(skb
, MLX5_IPOIB_HARD_LEN
);
1234 rq
->stats
.csum_complete
++;
1235 rq
->stats
.packets
++;
1236 rq
->stats
.bytes
+= cqe_bcnt
;
1239 void mlx5i_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1241 struct mlx5e_wqe_frag_info
*wi
;
1242 struct mlx5e_rx_wqe
*wqe
;
1243 __be16 wqe_counter_be
;
1244 struct sk_buff
*skb
;
1248 wqe_counter_be
= cqe
->wqe_counter
;
1249 wqe_counter
= be16_to_cpu(wqe_counter_be
);
1250 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
1251 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
1252 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
1254 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
1258 mlx5i_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1259 if (unlikely(!skb
->dev
)) {
1260 dev_kfree_skb_any(skb
);
1263 napi_gro_receive(rq
->cq
.napi
, skb
);
1266 mlx5e_free_rx_wqe_reuse(rq
, wi
);
1267 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
1268 &wqe
->next
.next_wqe_index
);
1271 #endif /* CONFIG_MLX5_CORE_IPOIB */
1273 #ifdef CONFIG_MLX5_EN_IPSEC
1275 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1277 struct mlx5e_wqe_frag_info
*wi
;
1278 struct mlx5e_rx_wqe
*wqe
;
1279 __be16 wqe_counter_be
;
1280 struct sk_buff
*skb
;
1284 wqe_counter_be
= cqe
->wqe_counter
;
1285 wqe_counter
= be16_to_cpu(wqe_counter_be
);
1286 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
1287 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
1288 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
1290 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
1291 if (unlikely(!skb
)) {
1292 /* a DROP, save the page-reuse checks */
1293 mlx5e_free_rx_wqe(rq
, wi
);
1296 skb
= mlx5e_ipsec_handle_rx_skb(rq
->netdev
, skb
);
1297 if (unlikely(!skb
)) {
1298 mlx5e_free_rx_wqe(rq
, wi
);
1302 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1303 napi_gro_receive(rq
->cq
.napi
, skb
);
1305 mlx5e_free_rx_wqe_reuse(rq
, wi
);
1307 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
1308 &wqe
->next
.next_wqe_index
);
1311 #endif /* CONFIG_MLX5_EN_IPSEC */