2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
39 #include <net/ip6_checksum.h>
44 #include "ipoib/ipoib.h"
45 #include "en_accel/ipsec_rxtx.h"
46 #include "lib/clock.h"
48 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config
*config
)
50 return config
->rx_filter
== HWTSTAMP_FILTER_ALL
;
53 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq
*cq
, u32 cqcc
,
56 u32 ci
= cqcc
& cq
->wq
.sz_m1
;
58 memcpy(data
, mlx5_cqwq_get_wqe(&cq
->wq
, ci
), sizeof(struct mlx5_cqe64
));
61 static inline void mlx5e_read_title_slot(struct mlx5e_rq
*rq
,
62 struct mlx5e_cq
*cq
, u32 cqcc
)
64 mlx5e_read_cqe_slot(cq
, cqcc
, &cq
->title
);
65 cq
->decmprs_left
= be32_to_cpu(cq
->title
.byte_cnt
);
66 cq
->decmprs_wqe_counter
= be16_to_cpu(cq
->title
.wqe_counter
);
67 rq
->stats
.cqe_compress_blks
++;
70 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq
*cq
, u32 cqcc
)
72 mlx5e_read_cqe_slot(cq
, cqcc
, cq
->mini_arr
);
76 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq
*cq
, u32 cqcc
, int n
)
78 u8 op_own
= (cqcc
>> cq
->wq
.log_sz
) & 1;
79 u32 wq_sz
= 1 << cq
->wq
.log_sz
;
80 u32 ci
= cqcc
& cq
->wq
.sz_m1
;
81 u32 ci_top
= min_t(u32
, wq_sz
, ci
+ n
);
83 for (; ci
< ci_top
; ci
++, n
--) {
84 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, ci
);
89 if (unlikely(ci
== wq_sz
)) {
91 for (ci
= 0; ci
< n
; ci
++) {
92 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, ci
);
99 static inline void mlx5e_decompress_cqe(struct mlx5e_rq
*rq
,
100 struct mlx5e_cq
*cq
, u32 cqcc
)
102 cq
->title
.byte_cnt
= cq
->mini_arr
[cq
->mini_arr_idx
].byte_cnt
;
103 cq
->title
.check_sum
= cq
->mini_arr
[cq
->mini_arr_idx
].checksum
;
104 cq
->title
.op_own
&= 0xf0;
105 cq
->title
.op_own
|= 0x01 & (cqcc
>> cq
->wq
.log_sz
);
106 cq
->title
.wqe_counter
= cpu_to_be16(cq
->decmprs_wqe_counter
);
108 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
)
109 cq
->decmprs_wqe_counter
+=
110 mpwrq_get_cqe_consumed_strides(&cq
->title
);
112 cq
->decmprs_wqe_counter
=
113 (cq
->decmprs_wqe_counter
+ 1) & rq
->wq
.sz_m1
;
116 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq
*rq
,
117 struct mlx5e_cq
*cq
, u32 cqcc
)
119 mlx5e_decompress_cqe(rq
, cq
, cqcc
);
120 cq
->title
.rss_hash_type
= 0;
121 cq
->title
.rss_hash_result
= 0;
124 static inline u32
mlx5e_decompress_cqes_cont(struct mlx5e_rq
*rq
,
126 int update_owner_only
,
129 u32 cqcc
= cq
->wq
.cc
+ update_owner_only
;
133 cqe_count
= min_t(u32
, cq
->decmprs_left
, budget_rem
);
135 for (i
= update_owner_only
; i
< cqe_count
;
136 i
++, cq
->mini_arr_idx
++, cqcc
++) {
137 if (cq
->mini_arr_idx
== MLX5_MINI_CQE_ARRAY_SIZE
)
138 mlx5e_read_mini_arr_slot(cq
, cqcc
);
140 mlx5e_decompress_cqe_no_hash(rq
, cq
, cqcc
);
141 rq
->handle_rx_cqe(rq
, &cq
->title
);
143 mlx5e_cqes_update_owner(cq
, cq
->wq
.cc
, cqcc
- cq
->wq
.cc
);
145 cq
->decmprs_left
-= cqe_count
;
146 rq
->stats
.cqe_compress_pkts
+= cqe_count
;
151 static inline u32
mlx5e_decompress_cqes_start(struct mlx5e_rq
*rq
,
155 mlx5e_read_title_slot(rq
, cq
, cq
->wq
.cc
);
156 mlx5e_read_mini_arr_slot(cq
, cq
->wq
.cc
+ 1);
157 mlx5e_decompress_cqe(rq
, cq
, cq
->wq
.cc
);
158 rq
->handle_rx_cqe(rq
, &cq
->title
);
161 return mlx5e_decompress_cqes_cont(rq
, cq
, 1, budget_rem
) - 1;
164 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
166 static inline bool mlx5e_page_is_reserved(struct page
*page
)
168 return page_is_pfmemalloc(page
) || page_to_nid(page
) != numa_mem_id();
171 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq
*rq
,
172 struct mlx5e_dma_info
*dma_info
)
174 struct mlx5e_page_cache
*cache
= &rq
->page_cache
;
175 u32 tail_next
= (cache
->tail
+ 1) & (MLX5E_CACHE_SIZE
- 1);
177 if (tail_next
== cache
->head
) {
178 rq
->stats
.cache_full
++;
182 if (unlikely(mlx5e_page_is_reserved(dma_info
->page
))) {
183 rq
->stats
.cache_waive
++;
187 cache
->page_cache
[cache
->tail
] = *dma_info
;
188 cache
->tail
= tail_next
;
192 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq
*rq
,
193 struct mlx5e_dma_info
*dma_info
)
195 struct mlx5e_page_cache
*cache
= &rq
->page_cache
;
197 if (unlikely(cache
->head
== cache
->tail
)) {
198 rq
->stats
.cache_empty
++;
202 if (page_ref_count(cache
->page_cache
[cache
->head
].page
) != 1) {
203 rq
->stats
.cache_busy
++;
207 *dma_info
= cache
->page_cache
[cache
->head
];
208 cache
->head
= (cache
->head
+ 1) & (MLX5E_CACHE_SIZE
- 1);
209 rq
->stats
.cache_reuse
++;
211 dma_sync_single_for_device(rq
->pdev
, dma_info
->addr
,
217 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq
*rq
,
218 struct mlx5e_dma_info
*dma_info
)
220 if (mlx5e_rx_cache_get(rq
, dma_info
))
223 dma_info
->page
= dev_alloc_pages(rq
->buff
.page_order
);
224 if (unlikely(!dma_info
->page
))
227 dma_info
->addr
= dma_map_page(rq
->pdev
, dma_info
->page
, 0,
228 RQ_PAGE_SIZE(rq
), rq
->buff
.map_dir
);
229 if (unlikely(dma_mapping_error(rq
->pdev
, dma_info
->addr
))) {
230 put_page(dma_info
->page
);
231 dma_info
->page
= NULL
;
238 void mlx5e_page_release(struct mlx5e_rq
*rq
, struct mlx5e_dma_info
*dma_info
,
241 if (likely(recycle
) && mlx5e_rx_cache_put(rq
, dma_info
))
244 dma_unmap_page(rq
->pdev
, dma_info
->addr
, RQ_PAGE_SIZE(rq
),
246 put_page(dma_info
->page
);
249 static inline bool mlx5e_page_reuse(struct mlx5e_rq
*rq
,
250 struct mlx5e_wqe_frag_info
*wi
)
252 return rq
->wqe
.page_reuse
&& wi
->di
.page
&&
253 (wi
->offset
+ rq
->wqe
.frag_sz
<= RQ_PAGE_SIZE(rq
)) &&
254 !mlx5e_page_is_reserved(wi
->di
.page
);
257 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq
*rq
, struct mlx5e_rx_wqe
*wqe
, u16 ix
)
259 struct mlx5e_wqe_frag_info
*wi
= &rq
->wqe
.frag_info
[ix
];
261 /* check if page exists, hence can be reused */
263 if (unlikely(mlx5e_page_alloc_mapped(rq
, &wi
->di
)))
268 wqe
->data
.addr
= cpu_to_be64(wi
->di
.addr
+ wi
->offset
+ rq
->buff
.headroom
);
272 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq
*rq
,
273 struct mlx5e_wqe_frag_info
*wi
)
275 mlx5e_page_release(rq
, &wi
->di
, true);
279 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq
*rq
,
280 struct mlx5e_wqe_frag_info
*wi
)
282 if (mlx5e_page_reuse(rq
, wi
)) {
283 rq
->stats
.page_reuse
++;
287 mlx5e_free_rx_wqe(rq
, wi
);
290 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq
*rq
, u16 ix
)
292 struct mlx5e_wqe_frag_info
*wi
= &rq
->wqe
.frag_info
[ix
];
295 mlx5e_free_rx_wqe(rq
, wi
);
298 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq
*rq
)
300 return rq
->mpwqe
.num_strides
>> MLX5_MPWRQ_WQE_PAGE_ORDER
;
303 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq
*rq
,
305 struct mlx5e_mpw_info
*wi
,
306 u32 page_idx
, u32 frag_offset
,
309 unsigned int truesize
= ALIGN(len
, BIT(rq
->mpwqe
.log_stride_sz
));
311 dma_sync_single_for_cpu(rq
->pdev
,
312 wi
->umr
.dma_info
[page_idx
].addr
+ frag_offset
,
313 len
, DMA_FROM_DEVICE
);
314 wi
->skbs_frags
[page_idx
]++;
315 skb_add_rx_frag(skb
, skb_shinfo(skb
)->nr_frags
,
316 wi
->umr
.dma_info
[page_idx
].page
, frag_offset
,
321 mlx5e_copy_skb_header_mpwqe(struct device
*pdev
,
323 struct mlx5e_mpw_info
*wi
,
324 u32 page_idx
, u32 offset
,
327 u16 headlen_pg
= min_t(u32
, headlen
, PAGE_SIZE
- offset
);
328 struct mlx5e_dma_info
*dma_info
= &wi
->umr
.dma_info
[page_idx
];
331 /* Aligning len to sizeof(long) optimizes memcpy performance */
332 len
= ALIGN(headlen_pg
, sizeof(long));
333 dma_sync_single_for_cpu(pdev
, dma_info
->addr
+ offset
, len
,
335 skb_copy_to_linear_data_offset(skb
, 0,
336 page_address(dma_info
->page
) + offset
,
338 if (unlikely(offset
+ headlen
> PAGE_SIZE
)) {
341 len
= ALIGN(headlen
- headlen_pg
, sizeof(long));
342 dma_sync_single_for_cpu(pdev
, dma_info
->addr
, len
,
344 skb_copy_to_linear_data_offset(skb
, headlen_pg
,
345 page_address(dma_info
->page
),
350 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq
*rq
, u16 ix
)
352 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
353 struct mlx5e_icosq
*sq
= &rq
->channel
->icosq
;
354 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
355 struct mlx5e_umr_wqe
*wqe
;
356 u8 num_wqebbs
= DIV_ROUND_UP(sizeof(*wqe
), MLX5_SEND_WQE_BB
);
359 /* fill sq edge with nops to avoid wqe wrap around */
360 while ((pi
= (sq
->pc
& wq
->sz_m1
)) > sq
->edge
) {
361 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_NOP
;
362 mlx5e_post_nop(wq
, sq
->sqn
, &sq
->pc
);
365 wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
366 memcpy(wqe
, &wi
->umr
.wqe
, sizeof(*wqe
));
367 wqe
->ctrl
.opmod_idx_opcode
=
368 cpu_to_be32((sq
->pc
<< MLX5_WQE_CTRL_WQE_INDEX_SHIFT
) |
371 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_UMR
;
372 sq
->pc
+= num_wqebbs
;
373 mlx5e_notify_hw(&sq
->wq
, sq
->pc
, sq
->uar_map
, &wqe
->ctrl
);
376 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq
*rq
,
379 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
380 int pg_strides
= mlx5e_mpwqe_strides_per_page(rq
);
381 struct mlx5e_dma_info
*dma_info
= &wi
->umr
.dma_info
[0];
385 for (i
= 0; i
< MLX5_MPWRQ_PAGES_PER_WQE
; i
++, dma_info
++) {
386 err
= mlx5e_page_alloc_mapped(rq
, dma_info
);
389 wi
->umr
.mtt
[i
] = cpu_to_be64(dma_info
->addr
| MLX5_EN_WR
);
390 page_ref_add(dma_info
->page
, pg_strides
);
393 memset(wi
->skbs_frags
, 0, sizeof(*wi
->skbs_frags
) * MLX5_MPWRQ_PAGES_PER_WQE
);
394 wi
->consumed_strides
= 0;
401 page_ref_sub(dma_info
->page
, pg_strides
);
402 mlx5e_page_release(rq
, dma_info
, true);
408 void mlx5e_free_rx_mpwqe(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
)
410 int pg_strides
= mlx5e_mpwqe_strides_per_page(rq
);
411 struct mlx5e_dma_info
*dma_info
= &wi
->umr
.dma_info
[0];
414 for (i
= 0; i
< MLX5_MPWRQ_PAGES_PER_WQE
; i
++, dma_info
++) {
415 page_ref_sub(dma_info
->page
, pg_strides
- wi
->skbs_frags
[i
]);
416 mlx5e_page_release(rq
, dma_info
, true);
420 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq
*rq
)
422 struct mlx5_wq_ll
*wq
= &rq
->wq
;
423 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(wq
, wq
->head
);
425 rq
->mpwqe
.umr_in_progress
= false;
427 mlx5_wq_ll_push(wq
, be16_to_cpu(wqe
->next
.next_wqe_index
));
429 /* ensure wqes are visible to device before updating doorbell record */
432 mlx5_wq_ll_update_db_record(wq
);
435 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
)
439 err
= mlx5e_alloc_rx_umr_mpwqe(rq
, ix
);
441 rq
->stats
.buff_alloc_err
++;
444 rq
->mpwqe
.umr_in_progress
= true;
445 mlx5e_post_umr_wqe(rq
, ix
);
449 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
)
451 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
453 mlx5e_free_rx_mpwqe(rq
, wi
);
456 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
)
458 struct mlx5_wq_ll
*wq
= &rq
->wq
;
461 if (unlikely(!MLX5E_TEST_BIT(rq
->state
, MLX5E_RQ_STATE_ENABLED
)))
464 if (mlx5_wq_ll_is_full(wq
))
468 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(wq
, wq
->head
);
470 err
= mlx5e_alloc_rx_wqe(rq
, wqe
, wq
->head
);
472 rq
->stats
.buff_alloc_err
++;
476 mlx5_wq_ll_push(wq
, be16_to_cpu(wqe
->next
.next_wqe_index
));
477 } while (!mlx5_wq_ll_is_full(wq
));
479 /* ensure wqes are visible to device before updating doorbell record */
482 mlx5_wq_ll_update_db_record(wq
);
487 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq
*cq
,
488 struct mlx5e_icosq
*sq
,
490 struct mlx5_cqe64
*cqe
)
492 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
493 u16 ci
= be16_to_cpu(cqe
->wqe_counter
) & wq
->sz_m1
;
494 struct mlx5e_sq_wqe_info
*icowi
= &sq
->db
.ico_wqe
[ci
];
496 mlx5_cqwq_pop(&cq
->wq
);
498 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_REQ
)) {
499 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
504 if (likely(icowi
->opcode
== MLX5_OPCODE_UMR
)) {
505 mlx5e_post_rx_mpwqe(rq
);
509 if (unlikely(icowi
->opcode
!= MLX5_OPCODE_NOP
))
511 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
515 static void mlx5e_poll_ico_cq(struct mlx5e_cq
*cq
, struct mlx5e_rq
*rq
)
517 struct mlx5e_icosq
*sq
= container_of(cq
, struct mlx5e_icosq
, cq
);
518 struct mlx5_cqe64
*cqe
;
520 if (unlikely(!MLX5E_TEST_BIT(sq
->state
, MLX5E_SQ_STATE_ENABLED
)))
523 cqe
= mlx5_cqwq_get_cqe(&cq
->wq
);
527 /* by design, there's only a single cqe */
528 mlx5e_poll_ico_single_cqe(cq
, sq
, rq
, cqe
);
530 mlx5_cqwq_update_db_record(&cq
->wq
);
533 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq
*rq
)
535 struct mlx5_wq_ll
*wq
= &rq
->wq
;
537 if (unlikely(!MLX5E_TEST_BIT(rq
->state
, MLX5E_RQ_STATE_ENABLED
)))
540 mlx5e_poll_ico_cq(&rq
->channel
->icosq
.cq
, rq
);
542 if (mlx5_wq_ll_is_full(wq
))
545 if (!rq
->mpwqe
.umr_in_progress
)
546 mlx5e_alloc_rx_mpwqe(rq
, wq
->head
);
551 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64
*cqe
, struct tcphdr
*tcp
)
553 u8 l4_hdr_type
= get_cqe_l4_hdr_type(cqe
);
554 u8 tcp_ack
= (l4_hdr_type
== CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA
) ||
555 (l4_hdr_type
== CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA
);
558 tcp
->psh
= get_cqe_lro_tcppsh(cqe
);
562 tcp
->ack_seq
= cqe
->lro_ack_seq_num
;
563 tcp
->window
= cqe
->lro_tcp_win
;
567 static void mlx5e_lro_update_hdr(struct sk_buff
*skb
, struct mlx5_cqe64
*cqe
,
570 struct ethhdr
*eth
= (struct ethhdr
*)(skb
->data
);
572 int network_depth
= 0;
578 proto
= __vlan_get_protocol(skb
, eth
->h_proto
, &network_depth
);
580 tot_len
= cqe_bcnt
- network_depth
;
581 ip_p
= skb
->data
+ network_depth
;
583 if (proto
== htons(ETH_P_IP
)) {
584 struct iphdr
*ipv4
= ip_p
;
586 tcp
= ip_p
+ sizeof(struct iphdr
);
587 skb_shinfo(skb
)->gso_type
= SKB_GSO_TCPV4
;
589 ipv4
->ttl
= cqe
->lro_min_ttl
;
590 ipv4
->tot_len
= cpu_to_be16(tot_len
);
592 ipv4
->check
= ip_fast_csum((unsigned char *)ipv4
,
595 mlx5e_lro_update_tcp_hdr(cqe
, tcp
);
596 check
= csum_partial(tcp
, tcp
->doff
* 4,
597 csum_unfold((__force __sum16
)cqe
->check_sum
));
598 /* Almost done, don't forget the pseudo header */
599 tcp
->check
= csum_tcpudp_magic(ipv4
->saddr
, ipv4
->daddr
,
600 tot_len
- sizeof(struct iphdr
),
603 u16 payload_len
= tot_len
- sizeof(struct ipv6hdr
);
604 struct ipv6hdr
*ipv6
= ip_p
;
606 tcp
= ip_p
+ sizeof(struct ipv6hdr
);
607 skb_shinfo(skb
)->gso_type
= SKB_GSO_TCPV6
;
609 ipv6
->hop_limit
= cqe
->lro_min_ttl
;
610 ipv6
->payload_len
= cpu_to_be16(payload_len
);
612 mlx5e_lro_update_tcp_hdr(cqe
, tcp
);
613 check
= csum_partial(tcp
, tcp
->doff
* 4,
614 csum_unfold((__force __sum16
)cqe
->check_sum
));
615 /* Almost done, don't forget the pseudo header */
616 tcp
->check
= csum_ipv6_magic(&ipv6
->saddr
, &ipv6
->daddr
, payload_len
,
621 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64
*cqe
,
624 u8 cht
= cqe
->rss_hash_type
;
625 int ht
= (cht
& CQE_RSS_HTYPE_L4
) ? PKT_HASH_TYPE_L4
:
626 (cht
& CQE_RSS_HTYPE_IP
) ? PKT_HASH_TYPE_L3
:
628 skb_set_hash(skb
, be32_to_cpu(cqe
->rss_hash_result
), ht
);
631 static inline bool is_last_ethertype_ip(struct sk_buff
*skb
, int *network_depth
)
633 __be16 ethertype
= ((struct ethhdr
*)skb
->data
)->h_proto
;
635 ethertype
= __vlan_get_protocol(skb
, ethertype
, network_depth
);
636 return (ethertype
== htons(ETH_P_IP
) || ethertype
== htons(ETH_P_IPV6
));
639 static inline void mlx5e_handle_csum(struct net_device
*netdev
,
640 struct mlx5_cqe64
*cqe
,
645 int network_depth
= 0;
647 if (unlikely(!(netdev
->features
& NETIF_F_RXCSUM
)))
651 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
652 rq
->stats
.csum_unnecessary
++;
656 if (is_last_ethertype_ip(skb
, &network_depth
)) {
657 skb
->ip_summed
= CHECKSUM_COMPLETE
;
658 skb
->csum
= csum_unfold((__force __sum16
)cqe
->check_sum
);
659 if (network_depth
> ETH_HLEN
)
660 /* CQE csum is calculated from the IP header and does
661 * not cover VLAN headers (if present). This will add
662 * the checksum manually.
664 skb
->csum
= csum_partial(skb
->data
+ ETH_HLEN
,
665 network_depth
- ETH_HLEN
,
667 rq
->stats
.csum_complete
++;
671 if (likely((cqe
->hds_ip_ext
& CQE_L3_OK
) &&
672 (cqe
->hds_ip_ext
& CQE_L4_OK
))) {
673 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
674 if (cqe_is_tunneled(cqe
)) {
676 skb
->encapsulation
= 1;
677 rq
->stats
.csum_unnecessary_inner
++;
680 rq
->stats
.csum_unnecessary
++;
684 skb
->ip_summed
= CHECKSUM_NONE
;
685 rq
->stats
.csum_none
++;
688 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64
*cqe
,
693 struct net_device
*netdev
= rq
->netdev
;
696 skb
->mac_len
= ETH_HLEN
;
697 lro_num_seg
= be32_to_cpu(cqe
->srqn
) >> 24;
698 if (lro_num_seg
> 1) {
699 mlx5e_lro_update_hdr(skb
, cqe
, cqe_bcnt
);
700 skb_shinfo(skb
)->gso_size
= DIV_ROUND_UP(cqe_bcnt
, lro_num_seg
);
701 /* Subtract one since we already counted this as one
702 * "regular" packet in mlx5e_complete_rx_cqe()
704 rq
->stats
.packets
+= lro_num_seg
- 1;
705 rq
->stats
.lro_packets
++;
706 rq
->stats
.lro_bytes
+= cqe_bcnt
;
709 if (unlikely(mlx5e_rx_hw_stamp(rq
->tstamp
)))
710 skb_hwtstamps(skb
)->hwtstamp
=
711 mlx5_timecounter_cyc2time(rq
->clock
, get_cqe_ts(cqe
));
713 skb_record_rx_queue(skb
, rq
->ix
);
715 if (likely(netdev
->features
& NETIF_F_RXHASH
))
716 mlx5e_skb_set_hash(cqe
, skb
);
718 if (cqe_has_vlan(cqe
)) {
719 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
720 be16_to_cpu(cqe
->vlan_info
));
721 rq
->stats
.removed_vlan_packets
++;
724 skb
->mark
= be32_to_cpu(cqe
->sop_drop_qpn
) & MLX5E_TC_FLOW_ID_MASK
;
726 mlx5e_handle_csum(netdev
, cqe
, rq
, skb
, !!lro_num_seg
);
727 skb
->protocol
= eth_type_trans(skb
, netdev
);
730 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq
*rq
,
731 struct mlx5_cqe64
*cqe
,
736 rq
->stats
.bytes
+= cqe_bcnt
;
737 mlx5e_build_rx_skb(cqe
, cqe_bcnt
, rq
, skb
);
740 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq
*sq
)
742 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
743 struct mlx5e_tx_wqe
*wqe
;
744 u16 pi
= (sq
->pc
- 1) & wq
->sz_m1
; /* last pi */
746 wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
748 mlx5e_notify_hw(wq
, sq
->pc
, sq
->uar_map
, &wqe
->ctrl
);
751 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq
*rq
,
752 struct mlx5e_dma_info
*di
,
753 const struct xdp_buff
*xdp
)
755 struct mlx5e_xdpsq
*sq
= &rq
->xdpsq
;
756 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
757 u16 pi
= sq
->pc
& wq
->sz_m1
;
758 struct mlx5e_tx_wqe
*wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
760 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
761 struct mlx5_wqe_eth_seg
*eseg
= &wqe
->eth
;
762 struct mlx5_wqe_data_seg
*dseg
;
764 ptrdiff_t data_offset
= xdp
->data
- xdp
->data_hard_start
;
765 dma_addr_t dma_addr
= di
->addr
+ data_offset
;
766 unsigned int dma_len
= xdp
->data_end
- xdp
->data
;
770 if (unlikely(dma_len
< MLX5E_XDP_MIN_INLINE
||
771 MLX5E_SW2HW_MTU(rq
->channel
->priv
, rq
->netdev
->mtu
) < dma_len
)) {
772 rq
->stats
.xdp_drop
++;
776 if (unlikely(!mlx5e_wqc_has_room_for(wq
, sq
->cc
, sq
->pc
, 1))) {
777 if (sq
->db
.doorbell
) {
778 /* SQ is full, ring doorbell */
779 mlx5e_xmit_xdp_doorbell(sq
);
780 sq
->db
.doorbell
= false;
782 rq
->stats
.xdp_tx_full
++;
786 dma_sync_single_for_device(sq
->pdev
, dma_addr
, dma_len
, PCI_DMA_TODEVICE
);
790 dseg
= (struct mlx5_wqe_data_seg
*)eseg
+ 1;
792 /* copy the inline part if required */
793 if (sq
->min_inline_mode
!= MLX5_INLINE_MODE_NONE
) {
794 memcpy(eseg
->inline_hdr
.start
, xdp
->data
, MLX5E_XDP_MIN_INLINE
);
795 eseg
->inline_hdr
.sz
= cpu_to_be16(MLX5E_XDP_MIN_INLINE
);
796 dma_len
-= MLX5E_XDP_MIN_INLINE
;
797 dma_addr
+= MLX5E_XDP_MIN_INLINE
;
801 /* write the dma part */
802 dseg
->addr
= cpu_to_be64(dma_addr
);
803 dseg
->byte_count
= cpu_to_be32(dma_len
);
805 cseg
->opmod_idx_opcode
= cpu_to_be32((sq
->pc
<< 8) | MLX5_OPCODE_SEND
);
807 /* move page to reference to sq responsibility,
808 * and mark so it's not put back in page-cache.
810 rq
->wqe
.xdp_xmit
= true;
814 sq
->db
.doorbell
= true;
820 /* returns true if packet was consumed by xdp */
821 static inline int mlx5e_xdp_handle(struct mlx5e_rq
*rq
,
822 struct mlx5e_dma_info
*di
,
823 void *va
, u16
*rx_headroom
, u32
*len
)
825 const struct bpf_prog
*prog
= READ_ONCE(rq
->xdp_prog
);
832 xdp
.data
= va
+ *rx_headroom
;
833 xdp_set_data_meta_invalid(&xdp
);
834 xdp
.data_end
= xdp
.data
+ *len
;
835 xdp
.data_hard_start
= va
;
837 act
= bpf_prog_run_xdp(prog
, &xdp
);
840 *rx_headroom
= xdp
.data
- xdp
.data_hard_start
;
841 *len
= xdp
.data_end
- xdp
.data
;
844 if (unlikely(!mlx5e_xmit_xdp_frame(rq
, di
, &xdp
)))
845 trace_xdp_exception(rq
->netdev
, prog
, act
);
848 bpf_warn_invalid_xdp_action(act
);
850 trace_xdp_exception(rq
->netdev
, prog
, act
);
852 rq
->stats
.xdp_drop
++;
858 struct sk_buff
*skb_from_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
,
859 struct mlx5e_wqe_frag_info
*wi
, u32 cqe_bcnt
)
861 struct mlx5e_dma_info
*di
= &wi
->di
;
862 u16 rx_headroom
= rq
->buff
.headroom
;
868 va
= page_address(di
->page
) + wi
->offset
;
869 data
= va
+ rx_headroom
;
870 frag_size
= MLX5_SKB_FRAG_SZ(rx_headroom
+ cqe_bcnt
);
872 dma_sync_single_range_for_cpu(rq
->pdev
,
873 di
->addr
+ wi
->offset
,
877 wi
->offset
+= frag_size
;
879 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_RESP_SEND
)) {
885 consumed
= mlx5e_xdp_handle(rq
, di
, va
, &rx_headroom
, &cqe_bcnt
);
888 return NULL
; /* page/packet was consumed by XDP */
890 skb
= build_skb(va
, frag_size
);
891 if (unlikely(!skb
)) {
892 rq
->stats
.buff_alloc_err
++;
896 /* queue up for recycling/reuse */
897 page_ref_inc(di
->page
);
899 skb_reserve(skb
, rx_headroom
);
900 skb_put(skb
, cqe_bcnt
);
905 void mlx5e_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
907 struct mlx5e_wqe_frag_info
*wi
;
908 struct mlx5e_rx_wqe
*wqe
;
909 __be16 wqe_counter_be
;
914 wqe_counter_be
= cqe
->wqe_counter
;
915 wqe_counter
= be16_to_cpu(wqe_counter_be
);
916 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
917 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
918 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
920 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
922 /* probably for XDP */
923 if (rq
->wqe
.xdp_xmit
) {
925 rq
->wqe
.xdp_xmit
= false;
926 /* do not return page to cache, it will be returned on XDP_TX completion */
929 /* probably an XDP_DROP, save the page-reuse checks */
930 mlx5e_free_rx_wqe(rq
, wi
);
934 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
935 napi_gro_receive(rq
->cq
.napi
, skb
);
937 mlx5e_free_rx_wqe_reuse(rq
, wi
);
939 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
940 &wqe
->next
.next_wqe_index
);
943 #ifdef CONFIG_MLX5_ESWITCH
944 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
946 struct net_device
*netdev
= rq
->netdev
;
947 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
948 struct mlx5e_rep_priv
*rpriv
= priv
->ppriv
;
949 struct mlx5_eswitch_rep
*rep
= rpriv
->rep
;
950 struct mlx5e_wqe_frag_info
*wi
;
951 struct mlx5e_rx_wqe
*wqe
;
953 __be16 wqe_counter_be
;
957 wqe_counter_be
= cqe
->wqe_counter
;
958 wqe_counter
= be16_to_cpu(wqe_counter_be
);
959 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
960 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
961 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
963 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
965 if (rq
->wqe
.xdp_xmit
) {
967 rq
->wqe
.xdp_xmit
= false;
968 /* do not return page to cache, it will be returned on XDP_TX completion */
971 /* probably an XDP_DROP, save the page-reuse checks */
972 mlx5e_free_rx_wqe(rq
, wi
);
976 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
978 if (rep
->vlan
&& skb_vlan_tag_present(skb
))
981 napi_gro_receive(rq
->cq
.napi
, skb
);
983 mlx5e_free_rx_wqe_reuse(rq
, wi
);
985 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
986 &wqe
->next
.next_wqe_index
);
990 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq
*rq
,
991 struct mlx5_cqe64
*cqe
,
992 struct mlx5e_mpw_info
*wi
,
996 u16 stride_ix
= mpwrq_get_cqe_stride_index(cqe
);
997 u32 wqe_offset
= stride_ix
<< rq
->mpwqe
.log_stride_sz
;
998 u32 head_offset
= wqe_offset
& (PAGE_SIZE
- 1);
999 u32 page_idx
= wqe_offset
>> PAGE_SHIFT
;
1000 u32 head_page_idx
= page_idx
;
1001 u16 headlen
= min_t(u16
, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD
, cqe_bcnt
);
1002 u32 frag_offset
= head_offset
+ headlen
;
1003 u16 byte_cnt
= cqe_bcnt
- headlen
;
1005 if (unlikely(frag_offset
>= PAGE_SIZE
)) {
1007 frag_offset
-= PAGE_SIZE
;
1011 u32 pg_consumed_bytes
=
1012 min_t(u32
, PAGE_SIZE
- frag_offset
, byte_cnt
);
1014 mlx5e_add_skb_frag_mpwqe(rq
, skb
, wi
, page_idx
, frag_offset
,
1016 byte_cnt
-= pg_consumed_bytes
;
1021 mlx5e_copy_skb_header_mpwqe(rq
->pdev
, skb
, wi
, head_page_idx
,
1022 head_offset
, headlen
);
1023 /* skb linear part was allocated with headlen and aligned to long */
1024 skb
->tail
+= headlen
;
1025 skb
->len
+= headlen
;
1028 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1030 u16 cstrides
= mpwrq_get_cqe_consumed_strides(cqe
);
1031 u16 wqe_id
= be16_to_cpu(cqe
->wqe_id
);
1032 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[wqe_id
];
1033 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_id
);
1034 struct sk_buff
*skb
;
1037 wi
->consumed_strides
+= cstrides
;
1039 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_RESP_SEND
)) {
1040 rq
->stats
.wqe_err
++;
1044 if (unlikely(mpwrq_is_filler_cqe(cqe
))) {
1045 rq
->stats
.mpwqe_filler
++;
1049 skb
= napi_alloc_skb(rq
->cq
.napi
,
1050 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD
,
1052 if (unlikely(!skb
)) {
1053 rq
->stats
.buff_alloc_err
++;
1057 prefetchw(skb
->data
);
1058 cqe_bcnt
= mpwrq_get_cqe_byte_cnt(cqe
);
1060 mlx5e_mpwqe_fill_rx_skb(rq
, cqe
, wi
, cqe_bcnt
, skb
);
1061 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1062 napi_gro_receive(rq
->cq
.napi
, skb
);
1065 if (likely(wi
->consumed_strides
< rq
->mpwqe
.num_strides
))
1068 mlx5e_free_rx_mpwqe(rq
, wi
);
1069 mlx5_wq_ll_pop(&rq
->wq
, cqe
->wqe_id
, &wqe
->next
.next_wqe_index
);
1072 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
)
1074 struct mlx5e_rq
*rq
= container_of(cq
, struct mlx5e_rq
, cq
);
1075 struct mlx5e_xdpsq
*xdpsq
;
1076 struct mlx5_cqe64
*cqe
;
1079 if (unlikely(!MLX5E_TEST_BIT(rq
->state
, MLX5E_RQ_STATE_ENABLED
)))
1082 if (cq
->decmprs_left
)
1083 work_done
+= mlx5e_decompress_cqes_cont(rq
, cq
, 0, budget
);
1085 cqe
= mlx5_cqwq_get_cqe(&cq
->wq
);
1092 if (mlx5_get_cqe_format(cqe
) == MLX5_COMPRESSED
) {
1094 mlx5e_decompress_cqes_start(rq
, cq
,
1095 budget
- work_done
);
1099 mlx5_cqwq_pop(&cq
->wq
);
1101 rq
->handle_rx_cqe(rq
, cqe
);
1102 } while ((++work_done
< budget
) && (cqe
= mlx5_cqwq_get_cqe(&cq
->wq
)));
1104 if (xdpsq
->db
.doorbell
) {
1105 mlx5e_xmit_xdp_doorbell(xdpsq
);
1106 xdpsq
->db
.doorbell
= false;
1109 mlx5_cqwq_update_db_record(&cq
->wq
);
1111 /* ensure cq space is freed before enabling more cqes */
1117 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq
*cq
)
1119 struct mlx5e_xdpsq
*sq
;
1120 struct mlx5_cqe64
*cqe
;
1121 struct mlx5e_rq
*rq
;
1125 sq
= container_of(cq
, struct mlx5e_xdpsq
, cq
);
1127 if (unlikely(!MLX5E_TEST_BIT(sq
->state
, MLX5E_SQ_STATE_ENABLED
)))
1130 cqe
= mlx5_cqwq_get_cqe(&cq
->wq
);
1134 rq
= container_of(sq
, struct mlx5e_rq
, xdpsq
);
1136 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1137 * otherwise a cq overrun may occur
1146 mlx5_cqwq_pop(&cq
->wq
);
1148 wqe_counter
= be16_to_cpu(cqe
->wqe_counter
);
1151 struct mlx5e_dma_info
*di
;
1154 last_wqe
= (sqcc
== wqe_counter
);
1156 ci
= sqcc
& sq
->wq
.sz_m1
;
1157 di
= &sq
->db
.di
[ci
];
1160 /* Recycle RX page */
1161 mlx5e_page_release(rq
, di
, true);
1162 } while (!last_wqe
);
1163 } while ((++i
< MLX5E_TX_CQ_POLL_BUDGET
) && (cqe
= mlx5_cqwq_get_cqe(&cq
->wq
)));
1165 mlx5_cqwq_update_db_record(&cq
->wq
);
1167 /* ensure cq space is freed before enabling more cqes */
1171 return (i
== MLX5E_TX_CQ_POLL_BUDGET
);
1174 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq
*sq
)
1176 struct mlx5e_rq
*rq
= container_of(sq
, struct mlx5e_rq
, xdpsq
);
1177 struct mlx5e_dma_info
*di
;
1180 while (sq
->cc
!= sq
->pc
) {
1181 ci
= sq
->cc
& sq
->wq
.sz_m1
;
1182 di
= &sq
->db
.di
[ci
];
1185 mlx5e_page_release(rq
, di
, false);
1189 #ifdef CONFIG_MLX5_CORE_IPOIB
1191 #define MLX5_IB_GRH_DGID_OFFSET 24
1192 #define MLX5_GID_SIZE 16
1194 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq
*rq
,
1195 struct mlx5_cqe64
*cqe
,
1197 struct sk_buff
*skb
)
1199 struct net_device
*netdev
;
1200 char *pseudo_header
;
1205 qpn
= be32_to_cpu(cqe
->sop_drop_qpn
) & 0xffffff;
1206 netdev
= mlx5i_pkey_get_netdev(rq
->netdev
, qpn
);
1208 /* No mapping present, cannot process SKB. This might happen if a child
1209 * interface is going down while having unprocessed CQEs on parent RQ
1211 if (unlikely(!netdev
)) {
1212 /* TODO: add drop counters support */
1214 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn
);
1218 g
= (be32_to_cpu(cqe
->flags_rqpn
) >> 28) & 3;
1219 dgid
= skb
->data
+ MLX5_IB_GRH_DGID_OFFSET
;
1220 if ((!g
) || dgid
[0] != 0xff)
1221 skb
->pkt_type
= PACKET_HOST
;
1222 else if (memcmp(dgid
, netdev
->broadcast
+ 4, MLX5_GID_SIZE
) == 0)
1223 skb
->pkt_type
= PACKET_BROADCAST
;
1225 skb
->pkt_type
= PACKET_MULTICAST
;
1227 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1228 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1231 skb_pull(skb
, MLX5_IB_GRH_BYTES
);
1233 skb
->protocol
= *((__be16
*)(skb
->data
));
1235 skb
->ip_summed
= CHECKSUM_COMPLETE
;
1236 skb
->csum
= csum_unfold((__force __sum16
)cqe
->check_sum
);
1238 if (unlikely(mlx5e_rx_hw_stamp(rq
->tstamp
)))
1239 skb_hwtstamps(skb
)->hwtstamp
=
1240 mlx5_timecounter_cyc2time(rq
->clock
, get_cqe_ts(cqe
));
1242 skb_record_rx_queue(skb
, rq
->ix
);
1244 if (likely(netdev
->features
& NETIF_F_RXHASH
))
1245 mlx5e_skb_set_hash(cqe
, skb
);
1247 /* 20 bytes of ipoib header and 4 for encap existing */
1248 pseudo_header
= skb_push(skb
, MLX5_IPOIB_PSEUDO_LEN
);
1249 memset(pseudo_header
, 0, MLX5_IPOIB_PSEUDO_LEN
);
1250 skb_reset_mac_header(skb
);
1251 skb_pull(skb
, MLX5_IPOIB_HARD_LEN
);
1255 rq
->stats
.csum_complete
++;
1256 rq
->stats
.packets
++;
1257 rq
->stats
.bytes
+= cqe_bcnt
;
1260 void mlx5i_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1262 struct mlx5e_wqe_frag_info
*wi
;
1263 struct mlx5e_rx_wqe
*wqe
;
1264 __be16 wqe_counter_be
;
1265 struct sk_buff
*skb
;
1269 wqe_counter_be
= cqe
->wqe_counter
;
1270 wqe_counter
= be16_to_cpu(wqe_counter_be
);
1271 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
1272 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
1273 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
1275 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
1279 mlx5i_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1280 if (unlikely(!skb
->dev
)) {
1281 dev_kfree_skb_any(skb
);
1284 napi_gro_receive(rq
->cq
.napi
, skb
);
1287 mlx5e_free_rx_wqe_reuse(rq
, wi
);
1288 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
1289 &wqe
->next
.next_wqe_index
);
1292 #endif /* CONFIG_MLX5_CORE_IPOIB */
1294 #ifdef CONFIG_MLX5_EN_IPSEC
1296 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1298 struct mlx5e_wqe_frag_info
*wi
;
1299 struct mlx5e_rx_wqe
*wqe
;
1300 __be16 wqe_counter_be
;
1301 struct sk_buff
*skb
;
1305 wqe_counter_be
= cqe
->wqe_counter
;
1306 wqe_counter
= be16_to_cpu(wqe_counter_be
);
1307 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
1308 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
1309 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
1311 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
1312 if (unlikely(!skb
)) {
1313 /* a DROP, save the page-reuse checks */
1314 mlx5e_free_rx_wqe(rq
, wi
);
1317 skb
= mlx5e_ipsec_handle_rx_skb(rq
->netdev
, skb
);
1318 if (unlikely(!skb
)) {
1319 mlx5e_free_rx_wqe(rq
, wi
);
1323 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1324 napi_gro_receive(rq
->cq
.napi
, skb
);
1326 mlx5e_free_rx_wqe_reuse(rq
, wi
);
1328 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
1329 &wqe
->next
.next_wqe_index
);
1332 #endif /* CONFIG_MLX5_EN_IPSEC */