2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/bpf_trace.h>
38 #include <net/busy_poll.h>
39 #include <net/ip6_checksum.h>
40 #include <net/inet_ecn.h>
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "lib/clock.h"
49 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config
*config
)
51 return config
->rx_filter
== HWTSTAMP_FILTER_ALL
;
54 static inline void mlx5e_read_cqe_slot(struct mlx5e_cq
*cq
, u32 cqcc
,
57 u32 ci
= cqcc
& cq
->wq
.sz_m1
;
59 memcpy(data
, mlx5_cqwq_get_wqe(&cq
->wq
, ci
), sizeof(struct mlx5_cqe64
));
62 static inline void mlx5e_read_title_slot(struct mlx5e_rq
*rq
,
63 struct mlx5e_cq
*cq
, u32 cqcc
)
65 mlx5e_read_cqe_slot(cq
, cqcc
, &cq
->title
);
66 cq
->decmprs_left
= be32_to_cpu(cq
->title
.byte_cnt
);
67 cq
->decmprs_wqe_counter
= be16_to_cpu(cq
->title
.wqe_counter
);
68 rq
->stats
.cqe_compress_blks
++;
71 static inline void mlx5e_read_mini_arr_slot(struct mlx5e_cq
*cq
, u32 cqcc
)
73 mlx5e_read_cqe_slot(cq
, cqcc
, cq
->mini_arr
);
77 static inline void mlx5e_cqes_update_owner(struct mlx5e_cq
*cq
, u32 cqcc
, int n
)
79 u8 op_own
= (cqcc
>> cq
->wq
.log_sz
) & 1;
80 u32 wq_sz
= 1 << cq
->wq
.log_sz
;
81 u32 ci
= cqcc
& cq
->wq
.sz_m1
;
82 u32 ci_top
= min_t(u32
, wq_sz
, ci
+ n
);
84 for (; ci
< ci_top
; ci
++, n
--) {
85 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, ci
);
90 if (unlikely(ci
== wq_sz
)) {
92 for (ci
= 0; ci
< n
; ci
++) {
93 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(&cq
->wq
, ci
);
100 static inline void mlx5e_decompress_cqe(struct mlx5e_rq
*rq
,
101 struct mlx5e_cq
*cq
, u32 cqcc
)
103 cq
->title
.byte_cnt
= cq
->mini_arr
[cq
->mini_arr_idx
].byte_cnt
;
104 cq
->title
.check_sum
= cq
->mini_arr
[cq
->mini_arr_idx
].checksum
;
105 cq
->title
.op_own
&= 0xf0;
106 cq
->title
.op_own
|= 0x01 & (cqcc
>> cq
->wq
.log_sz
);
107 cq
->title
.wqe_counter
= cpu_to_be16(cq
->decmprs_wqe_counter
);
109 if (rq
->wq_type
== MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ
)
110 cq
->decmprs_wqe_counter
+=
111 mpwrq_get_cqe_consumed_strides(&cq
->title
);
113 cq
->decmprs_wqe_counter
=
114 (cq
->decmprs_wqe_counter
+ 1) & rq
->wq
.sz_m1
;
117 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq
*rq
,
118 struct mlx5e_cq
*cq
, u32 cqcc
)
120 mlx5e_decompress_cqe(rq
, cq
, cqcc
);
121 cq
->title
.rss_hash_type
= 0;
122 cq
->title
.rss_hash_result
= 0;
125 static inline u32
mlx5e_decompress_cqes_cont(struct mlx5e_rq
*rq
,
127 int update_owner_only
,
130 u32 cqcc
= cq
->wq
.cc
+ update_owner_only
;
134 cqe_count
= min_t(u32
, cq
->decmprs_left
, budget_rem
);
136 for (i
= update_owner_only
; i
< cqe_count
;
137 i
++, cq
->mini_arr_idx
++, cqcc
++) {
138 if (cq
->mini_arr_idx
== MLX5_MINI_CQE_ARRAY_SIZE
)
139 mlx5e_read_mini_arr_slot(cq
, cqcc
);
141 mlx5e_decompress_cqe_no_hash(rq
, cq
, cqcc
);
142 rq
->handle_rx_cqe(rq
, &cq
->title
);
144 mlx5e_cqes_update_owner(cq
, cq
->wq
.cc
, cqcc
- cq
->wq
.cc
);
146 cq
->decmprs_left
-= cqe_count
;
147 rq
->stats
.cqe_compress_pkts
+= cqe_count
;
152 static inline u32
mlx5e_decompress_cqes_start(struct mlx5e_rq
*rq
,
156 mlx5e_read_title_slot(rq
, cq
, cq
->wq
.cc
);
157 mlx5e_read_mini_arr_slot(cq
, cq
->wq
.cc
+ 1);
158 mlx5e_decompress_cqe(rq
, cq
, cq
->wq
.cc
);
159 rq
->handle_rx_cqe(rq
, &cq
->title
);
162 return mlx5e_decompress_cqes_cont(rq
, cq
, 1, budget_rem
) - 1;
165 #define RQ_PAGE_SIZE(rq) ((1 << rq->buff.page_order) << PAGE_SHIFT)
167 static inline bool mlx5e_page_is_reserved(struct page
*page
)
169 return page_is_pfmemalloc(page
) || page_to_nid(page
) != numa_mem_id();
172 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq
*rq
,
173 struct mlx5e_dma_info
*dma_info
)
175 struct mlx5e_page_cache
*cache
= &rq
->page_cache
;
176 u32 tail_next
= (cache
->tail
+ 1) & (MLX5E_CACHE_SIZE
- 1);
178 if (tail_next
== cache
->head
) {
179 rq
->stats
.cache_full
++;
183 if (unlikely(mlx5e_page_is_reserved(dma_info
->page
))) {
184 rq
->stats
.cache_waive
++;
188 cache
->page_cache
[cache
->tail
] = *dma_info
;
189 cache
->tail
= tail_next
;
193 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq
*rq
,
194 struct mlx5e_dma_info
*dma_info
)
196 struct mlx5e_page_cache
*cache
= &rq
->page_cache
;
198 if (unlikely(cache
->head
== cache
->tail
)) {
199 rq
->stats
.cache_empty
++;
203 if (page_ref_count(cache
->page_cache
[cache
->head
].page
) != 1) {
204 rq
->stats
.cache_busy
++;
208 *dma_info
= cache
->page_cache
[cache
->head
];
209 cache
->head
= (cache
->head
+ 1) & (MLX5E_CACHE_SIZE
- 1);
210 rq
->stats
.cache_reuse
++;
212 dma_sync_single_for_device(rq
->pdev
, dma_info
->addr
,
218 static inline int mlx5e_page_alloc_mapped(struct mlx5e_rq
*rq
,
219 struct mlx5e_dma_info
*dma_info
)
221 if (mlx5e_rx_cache_get(rq
, dma_info
))
224 dma_info
->page
= dev_alloc_pages(rq
->buff
.page_order
);
225 if (unlikely(!dma_info
->page
))
228 dma_info
->addr
= dma_map_page(rq
->pdev
, dma_info
->page
, 0,
229 RQ_PAGE_SIZE(rq
), rq
->buff
.map_dir
);
230 if (unlikely(dma_mapping_error(rq
->pdev
, dma_info
->addr
))) {
231 put_page(dma_info
->page
);
232 dma_info
->page
= NULL
;
239 void mlx5e_page_release(struct mlx5e_rq
*rq
, struct mlx5e_dma_info
*dma_info
,
242 if (likely(recycle
) && mlx5e_rx_cache_put(rq
, dma_info
))
245 dma_unmap_page(rq
->pdev
, dma_info
->addr
, RQ_PAGE_SIZE(rq
),
247 put_page(dma_info
->page
);
250 static inline bool mlx5e_page_reuse(struct mlx5e_rq
*rq
,
251 struct mlx5e_wqe_frag_info
*wi
)
253 return rq
->wqe
.page_reuse
&& wi
->di
.page
&&
254 (wi
->offset
+ rq
->wqe
.frag_sz
<= RQ_PAGE_SIZE(rq
)) &&
255 !mlx5e_page_is_reserved(wi
->di
.page
);
258 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq
*rq
, struct mlx5e_rx_wqe
*wqe
, u16 ix
)
260 struct mlx5e_wqe_frag_info
*wi
= &rq
->wqe
.frag_info
[ix
];
262 /* check if page exists, hence can be reused */
264 if (unlikely(mlx5e_page_alloc_mapped(rq
, &wi
->di
)))
269 wqe
->data
.addr
= cpu_to_be64(wi
->di
.addr
+ wi
->offset
+ rq
->buff
.headroom
);
273 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq
*rq
,
274 struct mlx5e_wqe_frag_info
*wi
)
276 mlx5e_page_release(rq
, &wi
->di
, true);
280 static inline void mlx5e_free_rx_wqe_reuse(struct mlx5e_rq
*rq
,
281 struct mlx5e_wqe_frag_info
*wi
)
283 if (mlx5e_page_reuse(rq
, wi
)) {
284 rq
->stats
.page_reuse
++;
288 mlx5e_free_rx_wqe(rq
, wi
);
291 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq
*rq
, u16 ix
)
293 struct mlx5e_wqe_frag_info
*wi
= &rq
->wqe
.frag_info
[ix
];
296 mlx5e_free_rx_wqe(rq
, wi
);
299 static inline int mlx5e_mpwqe_strides_per_page(struct mlx5e_rq
*rq
)
301 return rq
->mpwqe
.num_strides
>> MLX5_MPWRQ_WQE_PAGE_ORDER
;
304 static inline void mlx5e_add_skb_frag_mpwqe(struct mlx5e_rq
*rq
,
306 struct mlx5e_mpw_info
*wi
,
307 u32 page_idx
, u32 frag_offset
,
310 unsigned int truesize
= ALIGN(len
, BIT(rq
->mpwqe
.log_stride_sz
));
312 dma_sync_single_for_cpu(rq
->pdev
,
313 wi
->umr
.dma_info
[page_idx
].addr
+ frag_offset
,
314 len
, DMA_FROM_DEVICE
);
315 wi
->skbs_frags
[page_idx
]++;
316 skb_add_rx_frag(skb
, skb_shinfo(skb
)->nr_frags
,
317 wi
->umr
.dma_info
[page_idx
].page
, frag_offset
,
322 mlx5e_copy_skb_header_mpwqe(struct device
*pdev
,
324 struct mlx5e_mpw_info
*wi
,
325 u32 page_idx
, u32 offset
,
328 u16 headlen_pg
= min_t(u32
, headlen
, PAGE_SIZE
- offset
);
329 struct mlx5e_dma_info
*dma_info
= &wi
->umr
.dma_info
[page_idx
];
332 /* Aligning len to sizeof(long) optimizes memcpy performance */
333 len
= ALIGN(headlen_pg
, sizeof(long));
334 dma_sync_single_for_cpu(pdev
, dma_info
->addr
+ offset
, len
,
336 skb_copy_to_linear_data_offset(skb
, 0,
337 page_address(dma_info
->page
) + offset
,
339 if (unlikely(offset
+ headlen
> PAGE_SIZE
)) {
342 len
= ALIGN(headlen
- headlen_pg
, sizeof(long));
343 dma_sync_single_for_cpu(pdev
, dma_info
->addr
, len
,
345 skb_copy_to_linear_data_offset(skb
, headlen_pg
,
346 page_address(dma_info
->page
),
351 static inline void mlx5e_post_umr_wqe(struct mlx5e_rq
*rq
, u16 ix
)
353 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
354 struct mlx5e_icosq
*sq
= &rq
->channel
->icosq
;
355 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
356 struct mlx5e_umr_wqe
*wqe
;
357 u8 num_wqebbs
= DIV_ROUND_UP(sizeof(*wqe
), MLX5_SEND_WQE_BB
);
360 /* fill sq edge with nops to avoid wqe wrap around */
361 while ((pi
= (sq
->pc
& wq
->sz_m1
)) > sq
->edge
) {
362 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_NOP
;
363 mlx5e_post_nop(wq
, sq
->sqn
, &sq
->pc
);
366 wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
367 memcpy(wqe
, &wi
->umr
.wqe
, sizeof(*wqe
));
368 wqe
->ctrl
.opmod_idx_opcode
=
369 cpu_to_be32((sq
->pc
<< MLX5_WQE_CTRL_WQE_INDEX_SHIFT
) |
372 sq
->db
.ico_wqe
[pi
].opcode
= MLX5_OPCODE_UMR
;
373 sq
->pc
+= num_wqebbs
;
374 mlx5e_notify_hw(&sq
->wq
, sq
->pc
, sq
->uar_map
, &wqe
->ctrl
);
377 static int mlx5e_alloc_rx_umr_mpwqe(struct mlx5e_rq
*rq
,
380 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
381 int pg_strides
= mlx5e_mpwqe_strides_per_page(rq
);
382 struct mlx5e_dma_info
*dma_info
= &wi
->umr
.dma_info
[0];
386 for (i
= 0; i
< MLX5_MPWRQ_PAGES_PER_WQE
; i
++, dma_info
++) {
387 err
= mlx5e_page_alloc_mapped(rq
, dma_info
);
390 wi
->umr
.mtt
[i
] = cpu_to_be64(dma_info
->addr
| MLX5_EN_WR
);
391 page_ref_add(dma_info
->page
, pg_strides
);
394 memset(wi
->skbs_frags
, 0, sizeof(*wi
->skbs_frags
) * MLX5_MPWRQ_PAGES_PER_WQE
);
395 wi
->consumed_strides
= 0;
402 page_ref_sub(dma_info
->page
, pg_strides
);
403 mlx5e_page_release(rq
, dma_info
, true);
409 void mlx5e_free_rx_mpwqe(struct mlx5e_rq
*rq
, struct mlx5e_mpw_info
*wi
)
411 int pg_strides
= mlx5e_mpwqe_strides_per_page(rq
);
412 struct mlx5e_dma_info
*dma_info
= &wi
->umr
.dma_info
[0];
415 for (i
= 0; i
< MLX5_MPWRQ_PAGES_PER_WQE
; i
++, dma_info
++) {
416 page_ref_sub(dma_info
->page
, pg_strides
- wi
->skbs_frags
[i
]);
417 mlx5e_page_release(rq
, dma_info
, true);
421 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq
*rq
)
423 struct mlx5_wq_ll
*wq
= &rq
->wq
;
424 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(wq
, wq
->head
);
426 rq
->mpwqe
.umr_in_progress
= false;
428 mlx5_wq_ll_push(wq
, be16_to_cpu(wqe
->next
.next_wqe_index
));
430 /* ensure wqes are visible to device before updating doorbell record */
433 mlx5_wq_ll_update_db_record(wq
);
436 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
)
440 err
= mlx5e_alloc_rx_umr_mpwqe(rq
, ix
);
442 rq
->stats
.buff_alloc_err
++;
445 rq
->mpwqe
.umr_in_progress
= true;
446 mlx5e_post_umr_wqe(rq
, ix
);
450 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq
*rq
, u16 ix
)
452 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[ix
];
454 mlx5e_free_rx_mpwqe(rq
, wi
);
457 bool mlx5e_post_rx_wqes(struct mlx5e_rq
*rq
)
459 struct mlx5_wq_ll
*wq
= &rq
->wq
;
462 if (unlikely(!MLX5E_TEST_BIT(rq
->state
, MLX5E_RQ_STATE_ENABLED
)))
465 if (mlx5_wq_ll_is_full(wq
))
469 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(wq
, wq
->head
);
471 err
= mlx5e_alloc_rx_wqe(rq
, wqe
, wq
->head
);
473 rq
->stats
.buff_alloc_err
++;
477 mlx5_wq_ll_push(wq
, be16_to_cpu(wqe
->next
.next_wqe_index
));
478 } while (!mlx5_wq_ll_is_full(wq
));
480 /* ensure wqes are visible to device before updating doorbell record */
483 mlx5_wq_ll_update_db_record(wq
);
488 static inline void mlx5e_poll_ico_single_cqe(struct mlx5e_cq
*cq
,
489 struct mlx5e_icosq
*sq
,
491 struct mlx5_cqe64
*cqe
)
493 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
494 u16 ci
= be16_to_cpu(cqe
->wqe_counter
) & wq
->sz_m1
;
495 struct mlx5e_sq_wqe_info
*icowi
= &sq
->db
.ico_wqe
[ci
];
497 mlx5_cqwq_pop(&cq
->wq
);
499 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_REQ
)) {
500 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
505 if (likely(icowi
->opcode
== MLX5_OPCODE_UMR
)) {
506 mlx5e_post_rx_mpwqe(rq
);
510 if (unlikely(icowi
->opcode
!= MLX5_OPCODE_NOP
))
512 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
516 static void mlx5e_poll_ico_cq(struct mlx5e_cq
*cq
, struct mlx5e_rq
*rq
)
518 struct mlx5e_icosq
*sq
= container_of(cq
, struct mlx5e_icosq
, cq
);
519 struct mlx5_cqe64
*cqe
;
521 if (unlikely(!MLX5E_TEST_BIT(sq
->state
, MLX5E_SQ_STATE_ENABLED
)))
524 cqe
= mlx5_cqwq_get_cqe(&cq
->wq
);
528 /* by design, there's only a single cqe */
529 mlx5e_poll_ico_single_cqe(cq
, sq
, rq
, cqe
);
531 mlx5_cqwq_update_db_record(&cq
->wq
);
534 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq
*rq
)
536 struct mlx5_wq_ll
*wq
= &rq
->wq
;
538 if (unlikely(!MLX5E_TEST_BIT(rq
->state
, MLX5E_RQ_STATE_ENABLED
)))
541 mlx5e_poll_ico_cq(&rq
->channel
->icosq
.cq
, rq
);
543 if (mlx5_wq_ll_is_full(wq
))
546 if (!rq
->mpwqe
.umr_in_progress
)
547 mlx5e_alloc_rx_mpwqe(rq
, wq
->head
);
552 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64
*cqe
, struct tcphdr
*tcp
)
554 u8 l4_hdr_type
= get_cqe_l4_hdr_type(cqe
);
555 u8 tcp_ack
= (l4_hdr_type
== CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA
) ||
556 (l4_hdr_type
== CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA
);
559 tcp
->psh
= get_cqe_lro_tcppsh(cqe
);
563 tcp
->ack_seq
= cqe
->lro_ack_seq_num
;
564 tcp
->window
= cqe
->lro_tcp_win
;
568 static void mlx5e_lro_update_hdr(struct sk_buff
*skb
, struct mlx5_cqe64
*cqe
,
571 struct ethhdr
*eth
= (struct ethhdr
*)(skb
->data
);
573 int network_depth
= 0;
579 proto
= __vlan_get_protocol(skb
, eth
->h_proto
, &network_depth
);
581 tot_len
= cqe_bcnt
- network_depth
;
582 ip_p
= skb
->data
+ network_depth
;
584 if (proto
== htons(ETH_P_IP
)) {
585 struct iphdr
*ipv4
= ip_p
;
587 tcp
= ip_p
+ sizeof(struct iphdr
);
588 skb_shinfo(skb
)->gso_type
= SKB_GSO_TCPV4
;
590 ipv4
->ttl
= cqe
->lro_min_ttl
;
591 ipv4
->tot_len
= cpu_to_be16(tot_len
);
593 ipv4
->check
= ip_fast_csum((unsigned char *)ipv4
,
596 mlx5e_lro_update_tcp_hdr(cqe
, tcp
);
597 check
= csum_partial(tcp
, tcp
->doff
* 4,
598 csum_unfold((__force __sum16
)cqe
->check_sum
));
599 /* Almost done, don't forget the pseudo header */
600 tcp
->check
= csum_tcpudp_magic(ipv4
->saddr
, ipv4
->daddr
,
601 tot_len
- sizeof(struct iphdr
),
604 u16 payload_len
= tot_len
- sizeof(struct ipv6hdr
);
605 struct ipv6hdr
*ipv6
= ip_p
;
607 tcp
= ip_p
+ sizeof(struct ipv6hdr
);
608 skb_shinfo(skb
)->gso_type
= SKB_GSO_TCPV6
;
610 ipv6
->hop_limit
= cqe
->lro_min_ttl
;
611 ipv6
->payload_len
= cpu_to_be16(payload_len
);
613 mlx5e_lro_update_tcp_hdr(cqe
, tcp
);
614 check
= csum_partial(tcp
, tcp
->doff
* 4,
615 csum_unfold((__force __sum16
)cqe
->check_sum
));
616 /* Almost done, don't forget the pseudo header */
617 tcp
->check
= csum_ipv6_magic(&ipv6
->saddr
, &ipv6
->daddr
, payload_len
,
622 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64
*cqe
,
625 u8 cht
= cqe
->rss_hash_type
;
626 int ht
= (cht
& CQE_RSS_HTYPE_L4
) ? PKT_HASH_TYPE_L4
:
627 (cht
& CQE_RSS_HTYPE_IP
) ? PKT_HASH_TYPE_L3
:
629 skb_set_hash(skb
, be32_to_cpu(cqe
->rss_hash_result
), ht
);
632 static inline bool is_last_ethertype_ip(struct sk_buff
*skb
, int *network_depth
,
635 *proto
= ((struct ethhdr
*)skb
->data
)->h_proto
;
636 *proto
= __vlan_get_protocol(skb
, *proto
, network_depth
);
637 return (*proto
== htons(ETH_P_IP
) || *proto
== htons(ETH_P_IPV6
));
640 static inline void mlx5e_enable_ecn(struct mlx5e_rq
*rq
, struct sk_buff
*skb
)
642 int network_depth
= 0;
647 if (unlikely(!is_last_ethertype_ip(skb
, &network_depth
, &proto
)))
650 ip
= skb
->data
+ network_depth
;
651 rc
= ((proto
== htons(ETH_P_IP
)) ? IP_ECN_set_ce((struct iphdr
*)ip
) :
652 IP6_ECN_set_ce(skb
, (struct ipv6hdr
*)ip
));
654 rq
->stats
.ecn_mark
+= !!rc
;
657 static u32
mlx5e_get_fcs(const struct sk_buff
*skb
)
659 const void *fcs_bytes
;
662 fcs_bytes
= skb_header_pointer(skb
, skb
->len
- ETH_FCS_LEN
,
663 ETH_FCS_LEN
, &_fcs_bytes
);
665 return __get_unaligned_cpu32(fcs_bytes
);
668 static u8
get_ip_proto(struct sk_buff
*skb
, int network_depth
, __be16 proto
)
670 void *ip_p
= skb
->data
+ network_depth
;
672 return (proto
== htons(ETH_P_IP
)) ? ((struct iphdr
*)ip_p
)->protocol
:
673 ((struct ipv6hdr
*)ip_p
)->nexthdr
;
676 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
678 static inline void mlx5e_handle_csum(struct net_device
*netdev
,
679 struct mlx5_cqe64
*cqe
,
684 int network_depth
= 0;
687 if (unlikely(!(netdev
->features
& NETIF_F_RXCSUM
)))
691 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
692 rq
->stats
.csum_unnecessary
++;
696 if (unlikely(test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE
, &rq
->state
)))
697 goto csum_unnecessary
;
699 /* CQE csum doesn't cover padding octets in short ethernet
700 * frames. And the pad field is appended prior to calculating
701 * and appending the FCS field.
703 * Detecting these padded frames requires to verify and parse
704 * IP headers, so we simply force all those small frames to be
705 * CHECKSUM_UNNECESSARY even if they are not padded.
707 if (short_frame(skb
->len
))
708 goto csum_unnecessary
;
710 if (likely(is_last_ethertype_ip(skb
, &network_depth
, &proto
))) {
711 if (unlikely(get_ip_proto(skb
, network_depth
, proto
) == IPPROTO_SCTP
))
712 goto csum_unnecessary
;
714 skb
->ip_summed
= CHECKSUM_COMPLETE
;
715 skb
->csum
= csum_unfold((__force __sum16
)cqe
->check_sum
);
716 if (network_depth
> ETH_HLEN
)
717 /* CQE csum is calculated from the IP header and does
718 * not cover VLAN headers (if present). This will add
719 * the checksum manually.
721 skb
->csum
= csum_partial(skb
->data
+ ETH_HLEN
,
722 network_depth
- ETH_HLEN
,
724 if (unlikely(netdev
->features
& NETIF_F_RXFCS
))
725 skb
->csum
= csum_block_add(skb
->csum
,
726 (__force __wsum
)mlx5e_get_fcs(skb
),
727 skb
->len
- ETH_FCS_LEN
);
728 rq
->stats
.csum_complete
++;
733 if (likely((cqe
->hds_ip_ext
& CQE_L3_OK
) &&
734 (cqe
->hds_ip_ext
& CQE_L4_OK
))) {
735 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
736 if (cqe_is_tunneled(cqe
)) {
738 skb
->encapsulation
= 1;
739 rq
->stats
.csum_unnecessary_inner
++;
742 rq
->stats
.csum_unnecessary
++;
746 skb
->ip_summed
= CHECKSUM_NONE
;
747 rq
->stats
.csum_none
++;
750 #define MLX5E_CE_BIT_MASK 0x80
752 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64
*cqe
,
757 struct net_device
*netdev
= rq
->netdev
;
760 skb
->mac_len
= ETH_HLEN
;
761 lro_num_seg
= be32_to_cpu(cqe
->srqn
) >> 24;
762 if (lro_num_seg
> 1) {
763 mlx5e_lro_update_hdr(skb
, cqe
, cqe_bcnt
);
764 skb_shinfo(skb
)->gso_size
= DIV_ROUND_UP(cqe_bcnt
, lro_num_seg
);
765 /* Subtract one since we already counted this as one
766 * "regular" packet in mlx5e_complete_rx_cqe()
768 rq
->stats
.packets
+= lro_num_seg
- 1;
769 rq
->stats
.lro_packets
++;
770 rq
->stats
.lro_bytes
+= cqe_bcnt
;
773 if (unlikely(mlx5e_rx_hw_stamp(rq
->tstamp
)))
774 skb_hwtstamps(skb
)->hwtstamp
=
775 mlx5_timecounter_cyc2time(rq
->clock
, get_cqe_ts(cqe
));
777 skb_record_rx_queue(skb
, rq
->ix
);
779 if (likely(netdev
->features
& NETIF_F_RXHASH
))
780 mlx5e_skb_set_hash(cqe
, skb
);
782 if (cqe_has_vlan(cqe
)) {
783 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
784 be16_to_cpu(cqe
->vlan_info
));
785 rq
->stats
.removed_vlan_packets
++;
788 skb
->mark
= be32_to_cpu(cqe
->sop_drop_qpn
) & MLX5E_TC_FLOW_ID_MASK
;
790 mlx5e_handle_csum(netdev
, cqe
, rq
, skb
, !!lro_num_seg
);
791 /* checking CE bit in cqe - MSB in ml_path field */
792 if (unlikely(cqe
->ml_path
& MLX5E_CE_BIT_MASK
))
793 mlx5e_enable_ecn(rq
, skb
);
795 skb
->protocol
= eth_type_trans(skb
, netdev
);
798 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq
*rq
,
799 struct mlx5_cqe64
*cqe
,
804 rq
->stats
.bytes
+= cqe_bcnt
;
805 mlx5e_build_rx_skb(cqe
, cqe_bcnt
, rq
, skb
);
808 static inline void mlx5e_xmit_xdp_doorbell(struct mlx5e_xdpsq
*sq
)
810 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
811 struct mlx5e_tx_wqe
*wqe
;
812 u16 pi
= (sq
->pc
- 1) & wq
->sz_m1
; /* last pi */
814 wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
816 mlx5e_notify_hw(wq
, sq
->pc
, sq
->uar_map
, &wqe
->ctrl
);
819 static inline bool mlx5e_xmit_xdp_frame(struct mlx5e_rq
*rq
,
820 struct mlx5e_dma_info
*di
,
821 const struct xdp_buff
*xdp
)
823 struct mlx5e_xdpsq
*sq
= &rq
->xdpsq
;
824 struct mlx5_wq_cyc
*wq
= &sq
->wq
;
825 u16 pi
= sq
->pc
& wq
->sz_m1
;
826 struct mlx5e_tx_wqe
*wqe
= mlx5_wq_cyc_get_wqe(wq
, pi
);
828 struct mlx5_wqe_ctrl_seg
*cseg
= &wqe
->ctrl
;
829 struct mlx5_wqe_eth_seg
*eseg
= &wqe
->eth
;
830 struct mlx5_wqe_data_seg
*dseg
;
832 ptrdiff_t data_offset
= xdp
->data
- xdp
->data_hard_start
;
833 dma_addr_t dma_addr
= di
->addr
+ data_offset
;
834 unsigned int dma_len
= xdp
->data_end
- xdp
->data
;
838 if (unlikely(dma_len
< MLX5E_XDP_MIN_INLINE
||
839 MLX5E_SW2HW_MTU(rq
->channel
->priv
, rq
->netdev
->mtu
) < dma_len
)) {
840 rq
->stats
.xdp_drop
++;
844 if (unlikely(!mlx5e_wqc_has_room_for(wq
, sq
->cc
, sq
->pc
, 1))) {
845 if (sq
->db
.doorbell
) {
846 /* SQ is full, ring doorbell */
847 mlx5e_xmit_xdp_doorbell(sq
);
848 sq
->db
.doorbell
= false;
850 rq
->stats
.xdp_tx_full
++;
854 dma_sync_single_for_device(sq
->pdev
, dma_addr
, dma_len
, PCI_DMA_TODEVICE
);
858 dseg
= (struct mlx5_wqe_data_seg
*)eseg
+ 1;
860 /* copy the inline part if required */
861 if (sq
->min_inline_mode
!= MLX5_INLINE_MODE_NONE
) {
862 memcpy(eseg
->inline_hdr
.start
, xdp
->data
, MLX5E_XDP_MIN_INLINE
);
863 eseg
->inline_hdr
.sz
= cpu_to_be16(MLX5E_XDP_MIN_INLINE
);
864 dma_len
-= MLX5E_XDP_MIN_INLINE
;
865 dma_addr
+= MLX5E_XDP_MIN_INLINE
;
869 /* write the dma part */
870 dseg
->addr
= cpu_to_be64(dma_addr
);
871 dseg
->byte_count
= cpu_to_be32(dma_len
);
873 cseg
->opmod_idx_opcode
= cpu_to_be32((sq
->pc
<< 8) | MLX5_OPCODE_SEND
);
875 /* move page to reference to sq responsibility,
876 * and mark so it's not put back in page-cache.
878 rq
->wqe
.xdp_xmit
= true;
882 sq
->db
.doorbell
= true;
888 /* returns true if packet was consumed by xdp */
889 static inline int mlx5e_xdp_handle(struct mlx5e_rq
*rq
,
890 struct mlx5e_dma_info
*di
,
891 void *va
, u16
*rx_headroom
, u32
*len
)
893 const struct bpf_prog
*prog
= READ_ONCE(rq
->xdp_prog
);
900 xdp
.data
= va
+ *rx_headroom
;
901 xdp_set_data_meta_invalid(&xdp
);
902 xdp
.data_end
= xdp
.data
+ *len
;
903 xdp
.data_hard_start
= va
;
905 act
= bpf_prog_run_xdp(prog
, &xdp
);
908 *rx_headroom
= xdp
.data
- xdp
.data_hard_start
;
909 *len
= xdp
.data_end
- xdp
.data
;
912 if (unlikely(!mlx5e_xmit_xdp_frame(rq
, di
, &xdp
)))
913 trace_xdp_exception(rq
->netdev
, prog
, act
);
916 bpf_warn_invalid_xdp_action(act
);
918 trace_xdp_exception(rq
->netdev
, prog
, act
);
920 rq
->stats
.xdp_drop
++;
926 struct sk_buff
*skb_from_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
,
927 struct mlx5e_wqe_frag_info
*wi
, u32 cqe_bcnt
)
929 struct mlx5e_dma_info
*di
= &wi
->di
;
930 u16 rx_headroom
= rq
->buff
.headroom
;
936 va
= page_address(di
->page
) + wi
->offset
;
937 data
= va
+ rx_headroom
;
938 frag_size
= MLX5_SKB_FRAG_SZ(rx_headroom
+ cqe_bcnt
);
940 dma_sync_single_range_for_cpu(rq
->pdev
,
941 di
->addr
+ wi
->offset
,
945 wi
->offset
+= frag_size
;
947 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_RESP_SEND
)) {
953 consumed
= mlx5e_xdp_handle(rq
, di
, va
, &rx_headroom
, &cqe_bcnt
);
956 return NULL
; /* page/packet was consumed by XDP */
958 skb
= build_skb(va
, frag_size
);
959 if (unlikely(!skb
)) {
960 rq
->stats
.buff_alloc_err
++;
964 /* queue up for recycling/reuse */
965 page_ref_inc(di
->page
);
967 skb_reserve(skb
, rx_headroom
);
968 skb_put(skb
, cqe_bcnt
);
973 void mlx5e_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
975 struct mlx5e_wqe_frag_info
*wi
;
976 struct mlx5e_rx_wqe
*wqe
;
977 __be16 wqe_counter_be
;
982 wqe_counter_be
= cqe
->wqe_counter
;
983 wqe_counter
= be16_to_cpu(wqe_counter_be
);
984 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
985 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
986 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
988 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
990 /* probably for XDP */
991 if (rq
->wqe
.xdp_xmit
) {
993 rq
->wqe
.xdp_xmit
= false;
994 /* do not return page to cache, it will be returned on XDP_TX completion */
997 /* probably an XDP_DROP, save the page-reuse checks */
998 mlx5e_free_rx_wqe(rq
, wi
);
1002 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1003 napi_gro_receive(rq
->cq
.napi
, skb
);
1005 mlx5e_free_rx_wqe_reuse(rq
, wi
);
1007 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
1008 &wqe
->next
.next_wqe_index
);
1011 #ifdef CONFIG_MLX5_ESWITCH
1012 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1014 struct net_device
*netdev
= rq
->netdev
;
1015 struct mlx5e_priv
*priv
= netdev_priv(netdev
);
1016 struct mlx5e_rep_priv
*rpriv
= priv
->ppriv
;
1017 struct mlx5_eswitch_rep
*rep
= rpriv
->rep
;
1018 struct mlx5e_wqe_frag_info
*wi
;
1019 struct mlx5e_rx_wqe
*wqe
;
1020 struct sk_buff
*skb
;
1021 __be16 wqe_counter_be
;
1025 wqe_counter_be
= cqe
->wqe_counter
;
1026 wqe_counter
= be16_to_cpu(wqe_counter_be
);
1027 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
1028 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
1029 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
1031 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
1033 if (rq
->wqe
.xdp_xmit
) {
1035 rq
->wqe
.xdp_xmit
= false;
1036 /* do not return page to cache, it will be returned on XDP_TX completion */
1039 /* probably an XDP_DROP, save the page-reuse checks */
1040 mlx5e_free_rx_wqe(rq
, wi
);
1044 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1046 if (rep
->vlan
&& skb_vlan_tag_present(skb
))
1049 napi_gro_receive(rq
->cq
.napi
, skb
);
1051 mlx5e_free_rx_wqe_reuse(rq
, wi
);
1053 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
1054 &wqe
->next
.next_wqe_index
);
1058 static inline void mlx5e_mpwqe_fill_rx_skb(struct mlx5e_rq
*rq
,
1059 struct mlx5_cqe64
*cqe
,
1060 struct mlx5e_mpw_info
*wi
,
1062 struct sk_buff
*skb
)
1064 u16 stride_ix
= mpwrq_get_cqe_stride_index(cqe
);
1065 u32 wqe_offset
= stride_ix
<< rq
->mpwqe
.log_stride_sz
;
1066 u32 head_offset
= wqe_offset
& (PAGE_SIZE
- 1);
1067 u32 page_idx
= wqe_offset
>> PAGE_SHIFT
;
1068 u32 head_page_idx
= page_idx
;
1069 u16 headlen
= min_t(u16
, MLX5_MPWRQ_SMALL_PACKET_THRESHOLD
, cqe_bcnt
);
1070 u32 frag_offset
= head_offset
+ headlen
;
1071 u16 byte_cnt
= cqe_bcnt
- headlen
;
1073 if (unlikely(frag_offset
>= PAGE_SIZE
)) {
1075 frag_offset
-= PAGE_SIZE
;
1079 u32 pg_consumed_bytes
=
1080 min_t(u32
, PAGE_SIZE
- frag_offset
, byte_cnt
);
1082 mlx5e_add_skb_frag_mpwqe(rq
, skb
, wi
, page_idx
, frag_offset
,
1084 byte_cnt
-= pg_consumed_bytes
;
1089 mlx5e_copy_skb_header_mpwqe(rq
->pdev
, skb
, wi
, head_page_idx
,
1090 head_offset
, headlen
);
1091 /* skb linear part was allocated with headlen and aligned to long */
1092 skb
->tail
+= headlen
;
1093 skb
->len
+= headlen
;
1096 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1098 u16 cstrides
= mpwrq_get_cqe_consumed_strides(cqe
);
1099 u16 wqe_id
= be16_to_cpu(cqe
->wqe_id
);
1100 struct mlx5e_mpw_info
*wi
= &rq
->mpwqe
.info
[wqe_id
];
1101 struct mlx5e_rx_wqe
*wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_id
);
1102 struct sk_buff
*skb
;
1105 wi
->consumed_strides
+= cstrides
;
1107 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_RESP_SEND
)) {
1108 rq
->stats
.wqe_err
++;
1112 if (unlikely(mpwrq_is_filler_cqe(cqe
))) {
1113 rq
->stats
.mpwqe_filler
++;
1117 skb
= napi_alloc_skb(rq
->cq
.napi
,
1118 ALIGN(MLX5_MPWRQ_SMALL_PACKET_THRESHOLD
,
1120 if (unlikely(!skb
)) {
1121 rq
->stats
.buff_alloc_err
++;
1125 prefetchw(skb
->data
);
1126 cqe_bcnt
= mpwrq_get_cqe_byte_cnt(cqe
);
1128 mlx5e_mpwqe_fill_rx_skb(rq
, cqe
, wi
, cqe_bcnt
, skb
);
1129 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1130 napi_gro_receive(rq
->cq
.napi
, skb
);
1133 if (likely(wi
->consumed_strides
< rq
->mpwqe
.num_strides
))
1136 mlx5e_free_rx_mpwqe(rq
, wi
);
1137 mlx5_wq_ll_pop(&rq
->wq
, cqe
->wqe_id
, &wqe
->next
.next_wqe_index
);
1140 int mlx5e_poll_rx_cq(struct mlx5e_cq
*cq
, int budget
)
1142 struct mlx5e_rq
*rq
= container_of(cq
, struct mlx5e_rq
, cq
);
1143 struct mlx5e_xdpsq
*xdpsq
= &rq
->xdpsq
;
1144 struct mlx5_cqe64
*cqe
;
1147 if (unlikely(!MLX5E_TEST_BIT(rq
->state
, MLX5E_RQ_STATE_ENABLED
)))
1150 if (cq
->decmprs_left
)
1151 work_done
+= mlx5e_decompress_cqes_cont(rq
, cq
, 0, budget
);
1153 cqe
= mlx5_cqwq_get_cqe(&cq
->wq
);
1155 if (unlikely(work_done
))
1161 if (mlx5_get_cqe_format(cqe
) == MLX5_COMPRESSED
) {
1163 mlx5e_decompress_cqes_start(rq
, cq
,
1164 budget
- work_done
);
1168 mlx5_cqwq_pop(&cq
->wq
);
1170 rq
->handle_rx_cqe(rq
, cqe
);
1171 } while ((++work_done
< budget
) && (cqe
= mlx5_cqwq_get_cqe(&cq
->wq
)));
1174 if (xdpsq
->db
.doorbell
) {
1175 mlx5e_xmit_xdp_doorbell(xdpsq
);
1176 xdpsq
->db
.doorbell
= false;
1179 mlx5_cqwq_update_db_record(&cq
->wq
);
1181 /* ensure cq space is freed before enabling more cqes */
1187 bool mlx5e_poll_xdpsq_cq(struct mlx5e_cq
*cq
)
1189 struct mlx5e_xdpsq
*sq
;
1190 struct mlx5_cqe64
*cqe
;
1191 struct mlx5e_rq
*rq
;
1195 sq
= container_of(cq
, struct mlx5e_xdpsq
, cq
);
1197 if (unlikely(!MLX5E_TEST_BIT(sq
->state
, MLX5E_SQ_STATE_ENABLED
)))
1200 cqe
= mlx5_cqwq_get_cqe(&cq
->wq
);
1204 rq
= container_of(sq
, struct mlx5e_rq
, xdpsq
);
1206 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
1207 * otherwise a cq overrun may occur
1216 mlx5_cqwq_pop(&cq
->wq
);
1218 wqe_counter
= be16_to_cpu(cqe
->wqe_counter
);
1221 struct mlx5e_dma_info
*di
;
1224 last_wqe
= (sqcc
== wqe_counter
);
1226 ci
= sqcc
& sq
->wq
.sz_m1
;
1227 di
= &sq
->db
.di
[ci
];
1230 /* Recycle RX page */
1231 mlx5e_page_release(rq
, di
, true);
1232 } while (!last_wqe
);
1233 } while ((++i
< MLX5E_TX_CQ_POLL_BUDGET
) && (cqe
= mlx5_cqwq_get_cqe(&cq
->wq
)));
1235 mlx5_cqwq_update_db_record(&cq
->wq
);
1237 /* ensure cq space is freed before enabling more cqes */
1241 return (i
== MLX5E_TX_CQ_POLL_BUDGET
);
1244 void mlx5e_free_xdpsq_descs(struct mlx5e_xdpsq
*sq
)
1246 struct mlx5e_rq
*rq
= container_of(sq
, struct mlx5e_rq
, xdpsq
);
1247 struct mlx5e_dma_info
*di
;
1250 while (sq
->cc
!= sq
->pc
) {
1251 ci
= sq
->cc
& sq
->wq
.sz_m1
;
1252 di
= &sq
->db
.di
[ci
];
1255 mlx5e_page_release(rq
, di
, false);
1259 #ifdef CONFIG_MLX5_CORE_IPOIB
1261 #define MLX5_IB_GRH_DGID_OFFSET 24
1262 #define MLX5_GID_SIZE 16
1264 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq
*rq
,
1265 struct mlx5_cqe64
*cqe
,
1267 struct sk_buff
*skb
)
1269 struct hwtstamp_config
*tstamp
;
1270 struct net_device
*netdev
;
1271 struct mlx5e_priv
*priv
;
1272 char *pseudo_header
;
1277 qpn
= be32_to_cpu(cqe
->sop_drop_qpn
) & 0xffffff;
1278 netdev
= mlx5i_pkey_get_netdev(rq
->netdev
, qpn
);
1280 /* No mapping present, cannot process SKB. This might happen if a child
1281 * interface is going down while having unprocessed CQEs on parent RQ
1283 if (unlikely(!netdev
)) {
1284 /* TODO: add drop counters support */
1286 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn
);
1290 priv
= mlx5i_epriv(netdev
);
1291 tstamp
= &priv
->tstamp
;
1293 g
= (be32_to_cpu(cqe
->flags_rqpn
) >> 28) & 3;
1294 dgid
= skb
->data
+ MLX5_IB_GRH_DGID_OFFSET
;
1295 if ((!g
) || dgid
[0] != 0xff)
1296 skb
->pkt_type
= PACKET_HOST
;
1297 else if (memcmp(dgid
, netdev
->broadcast
+ 4, MLX5_GID_SIZE
) == 0)
1298 skb
->pkt_type
= PACKET_BROADCAST
;
1300 skb
->pkt_type
= PACKET_MULTICAST
;
1302 /* TODO: IB/ipoib: Allow mcast packets from other VFs
1303 * 68996a6e760e5c74654723eeb57bf65628ae87f4
1306 skb_pull(skb
, MLX5_IB_GRH_BYTES
);
1308 skb
->protocol
= *((__be16
*)(skb
->data
));
1310 skb
->ip_summed
= CHECKSUM_COMPLETE
;
1311 skb
->csum
= csum_unfold((__force __sum16
)cqe
->check_sum
);
1313 if (unlikely(mlx5e_rx_hw_stamp(tstamp
)))
1314 skb_hwtstamps(skb
)->hwtstamp
=
1315 mlx5_timecounter_cyc2time(rq
->clock
, get_cqe_ts(cqe
));
1317 skb_record_rx_queue(skb
, rq
->ix
);
1319 if (likely(netdev
->features
& NETIF_F_RXHASH
))
1320 mlx5e_skb_set_hash(cqe
, skb
);
1322 /* 20 bytes of ipoib header and 4 for encap existing */
1323 pseudo_header
= skb_push(skb
, MLX5_IPOIB_PSEUDO_LEN
);
1324 memset(pseudo_header
, 0, MLX5_IPOIB_PSEUDO_LEN
);
1325 skb_reset_mac_header(skb
);
1326 skb_pull(skb
, MLX5_IPOIB_HARD_LEN
);
1330 rq
->stats
.csum_complete
++;
1331 rq
->stats
.packets
++;
1332 rq
->stats
.bytes
+= cqe_bcnt
;
1335 void mlx5i_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1337 struct mlx5e_wqe_frag_info
*wi
;
1338 struct mlx5e_rx_wqe
*wqe
;
1339 __be16 wqe_counter_be
;
1340 struct sk_buff
*skb
;
1344 wqe_counter_be
= cqe
->wqe_counter
;
1345 wqe_counter
= be16_to_cpu(wqe_counter_be
);
1346 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
1347 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
1348 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
1350 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
1354 mlx5i_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1355 if (unlikely(!skb
->dev
)) {
1356 dev_kfree_skb_any(skb
);
1359 napi_gro_receive(rq
->cq
.napi
, skb
);
1362 mlx5e_free_rx_wqe_reuse(rq
, wi
);
1363 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
1364 &wqe
->next
.next_wqe_index
);
1367 #endif /* CONFIG_MLX5_CORE_IPOIB */
1369 #ifdef CONFIG_MLX5_EN_IPSEC
1371 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq
*rq
, struct mlx5_cqe64
*cqe
)
1373 struct mlx5e_wqe_frag_info
*wi
;
1374 struct mlx5e_rx_wqe
*wqe
;
1375 __be16 wqe_counter_be
;
1376 struct sk_buff
*skb
;
1380 wqe_counter_be
= cqe
->wqe_counter
;
1381 wqe_counter
= be16_to_cpu(wqe_counter_be
);
1382 wqe
= mlx5_wq_ll_get_wqe(&rq
->wq
, wqe_counter
);
1383 wi
= &rq
->wqe
.frag_info
[wqe_counter
];
1384 cqe_bcnt
= be32_to_cpu(cqe
->byte_cnt
);
1386 skb
= skb_from_cqe(rq
, cqe
, wi
, cqe_bcnt
);
1387 if (unlikely(!skb
)) {
1388 /* a DROP, save the page-reuse checks */
1389 mlx5e_free_rx_wqe(rq
, wi
);
1392 skb
= mlx5e_ipsec_handle_rx_skb(rq
->netdev
, skb
);
1393 if (unlikely(!skb
)) {
1394 mlx5e_free_rx_wqe(rq
, wi
);
1398 mlx5e_complete_rx_cqe(rq
, cqe
, cqe_bcnt
, skb
);
1399 napi_gro_receive(rq
->cq
.napi
, skb
);
1401 mlx5e_free_rx_wqe_reuse(rq
, wi
);
1403 mlx5_wq_ll_pop(&rq
->wq
, wqe_counter_be
,
1404 &wqe
->next
.next_wqe_index
);
1407 #endif /* CONFIG_MLX5_EN_IPSEC */