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2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 struct mlx5_cqe64
*mlx5e_get_cqe(struct mlx5e_cq
*cq
)
37 struct mlx5_cqwq
*wq
= &cq
->wq
;
38 u32 ci
= mlx5_cqwq_get_ci(wq
);
39 struct mlx5_cqe64
*cqe
= mlx5_cqwq_get_wqe(wq
, ci
);
40 int cqe_ownership_bit
= cqe
->op_own
& MLX5_CQE_OWNER_MASK
;
41 int sw_ownership_val
= mlx5_cqwq_get_wrap_cnt(wq
) & 1;
43 if (cqe_ownership_bit
!= sw_ownership_val
)
46 /* ensure cqe content is read after cqe ownership bit */
52 static void mlx5e_poll_ico_cq(struct mlx5e_cq
*cq
)
54 struct mlx5_wq_cyc
*wq
;
55 struct mlx5_cqe64
*cqe
;
59 cqe
= mlx5e_get_cqe(cq
);
63 sq
= container_of(cq
, struct mlx5e_sq
, cq
);
66 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
67 * otherwise a cq overrun may occur
72 u16 ci
= be16_to_cpu(cqe
->wqe_counter
) & wq
->sz_m1
;
73 struct mlx5e_ico_wqe_info
*icowi
= &sq
->ico_wqe_info
[ci
];
75 mlx5_cqwq_pop(&cq
->wq
);
76 sqcc
+= icowi
->num_wqebbs
;
78 if (unlikely((cqe
->op_own
>> 4) != MLX5_CQE_REQ
)) {
79 WARN_ONCE(true, "mlx5e: Bad OP in ICOSQ CQE: 0x%x\n",
84 switch (icowi
->opcode
) {
88 mlx5e_post_rx_fragmented_mpwqe(&sq
->channel
->rq
);
92 "mlx5e: Bad OPCODE in ICOSQ WQE info: 0x%x\n",
96 } while ((cqe
= mlx5e_get_cqe(cq
)));
98 mlx5_cqwq_update_db_record(&cq
->wq
);
100 /* ensure cq space is freed before enabling more cqes */
106 int mlx5e_napi_poll(struct napi_struct
*napi
, int budget
)
108 struct mlx5e_channel
*c
= container_of(napi
, struct mlx5e_channel
,
114 clear_bit(MLX5E_CHANNEL_NAPI_SCHED
, &c
->flags
);
116 for (i
= 0; i
< c
->num_tc
; i
++)
117 busy
|= mlx5e_poll_tx_cq(&c
->sq
[i
].cq
, budget
);
119 work_done
= mlx5e_poll_rx_cq(&c
->rq
.cq
, budget
);
120 busy
|= work_done
== budget
;
122 mlx5e_poll_ico_cq(&c
->icosq
.cq
);
124 busy
|= mlx5e_post_rx_wqes(&c
->rq
);
129 napi_complete_done(napi
, work_done
);
131 /* avoid losing completion event during/after polling cqs */
132 if (test_bit(MLX5E_CHANNEL_NAPI_SCHED
, &c
->flags
)) {
137 for (i
= 0; i
< c
->num_tc
; i
++)
138 mlx5e_cq_arm(&c
->sq
[i
].cq
);
140 if (test_bit(MLX5E_RQ_STATE_AM
, &c
->rq
.state
))
143 mlx5e_cq_arm(&c
->rq
.cq
);
144 mlx5e_cq_arm(&c
->icosq
.cq
);
149 void mlx5e_completion_event(struct mlx5_core_cq
*mcq
)
151 struct mlx5e_cq
*cq
= container_of(mcq
, struct mlx5e_cq
, mcq
);
154 set_bit(MLX5E_CHANNEL_NAPI_SCHED
, &cq
->channel
->flags
);
155 napi_schedule(cq
->napi
);
158 void mlx5e_cq_error_event(struct mlx5_core_cq
*mcq
, enum mlx5_event event
)
160 struct mlx5e_cq
*cq
= container_of(mcq
, struct mlx5e_cq
, mcq
);
161 struct mlx5e_channel
*c
= cq
->channel
;
162 struct mlx5e_priv
*priv
= c
->priv
;
163 struct net_device
*netdev
= priv
->netdev
;
165 netdev_err(netdev
, "%s: cqn=0x%.6x event=0x%.2x\n",
166 __func__
, mcq
->cqn
, event
);