drivers/net/ethernet/mellanox/mlx5/core/eswitch.h

   1 /*
   2  * Copyright (c) 2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #ifndef __MLX5_ESWITCH_H__
  34 #define __MLX5_ESWITCH_H__
  35
  36 #include <linux/if_ether.h>
  37 #include <linux/if_link.h>
  38 #include <net/devlink.h>
  39 #include <linux/mlx5/device.h>
  40 #include <linux/mlx5/eswitch.h>
  41 #include "lib/mpfs.h"
  42
  43 #ifdef CONFIG_MLX5_ESWITCH
  44
  45 #define MLX5_MAX_UC_PER_VPORT(dev) \
  46         (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
  47
  48 #define MLX5_MAX_MC_PER_VPORT(dev) \
  49         (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
  50
  51 #define FDB_UPLINK_VPORT 0xffff
  52
  53 #define MLX5_MIN_BW_SHARE 1
  54
  55 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
  56         min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
  57
  58 #define mlx5_esw_has_fwd_fdb(dev) \
  59         MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
  60
  61 struct vport_ingress {
  62         struct mlx5_flow_table *acl;
  63         struct mlx5_flow_group *allow_untagged_spoofchk_grp;
  64         struct mlx5_flow_group *allow_spoofchk_only_grp;
  65         struct mlx5_flow_group *allow_untagged_only_grp;
  66         struct mlx5_flow_group *drop_grp;
  67         struct mlx5_flow_handle  *allow_rule;
  68         struct mlx5_flow_handle  *drop_rule;
  69         struct mlx5_fc           *drop_counter;
  70 };
  71
  72 struct vport_egress {
  73         struct mlx5_flow_table *acl;
  74         struct mlx5_flow_group *allowed_vlans_grp;
  75         struct mlx5_flow_group *drop_grp;
  76         struct mlx5_flow_handle  *allowed_vlan;
  77         struct mlx5_flow_handle  *drop_rule;
  78         struct mlx5_fc           *drop_counter;
  79 };
  80
  81 struct mlx5_vport_drop_stats {
  82         u64 rx_dropped;
  83         u64 tx_dropped;
  84 };
  85
  86 struct mlx5_vport_info {
  87         u8                      mac[ETH_ALEN];
  88         u16                     vlan;
  89         u8                      qos;
  90         u64                     node_guid;
  91         int                     link_state;
  92         u32                     min_rate;
  93         u32                     max_rate;
  94         bool                    spoofchk;
  95         bool                    trusted;
  96 };
  97
  98 struct mlx5_vport {
  99         struct mlx5_core_dev    *dev;
 100         int                     vport;
 101         struct hlist_head       uc_list[MLX5_L2_ADDR_HASH_SIZE];
 102         struct hlist_head       mc_list[MLX5_L2_ADDR_HASH_SIZE];
 103         struct mlx5_flow_handle *promisc_rule;
 104         struct mlx5_flow_handle *allmulti_rule;
 105         struct work_struct      vport_change_handler;
 106
 107         struct vport_ingress    ingress;
 108         struct vport_egress     egress;
 109
 110         struct mlx5_vport_info  info;
 111
 112         struct {
 113                 bool            enabled;
 114                 u32             esw_tsar_ix;
 115                 u32             bw_share;
 116         } qos;
 117
 118         bool                    enabled;
 119         u16                     enabled_events;
 120 };
 121
 122 struct mlx5_eswitch_fdb {
 123         union {
 124                 struct legacy_fdb {
 125                         struct mlx5_flow_table *fdb;
 126                         struct mlx5_flow_group *addr_grp;
 127                         struct mlx5_flow_group *allmulti_grp;
 128                         struct mlx5_flow_group *promisc_grp;
 129                 } legacy;
 130
 131                 struct offloads_fdb {
 132                         struct mlx5_flow_table *fast_fdb;
 133                         struct mlx5_flow_table *fwd_fdb;
 134                         struct mlx5_flow_table *slow_fdb;
 135                         struct mlx5_flow_group *send_to_vport_grp;
 136                         struct mlx5_flow_group *miss_grp;
 137                         struct mlx5_flow_handle *miss_rule_uni;
 138                         struct mlx5_flow_handle *miss_rule_multi;
 139                         int vlan_push_pop_refcount;
 140                 } offloads;
 141         };
 142 };
 143
 144 struct mlx5_esw_offload {
 145         struct mlx5_flow_table *ft_offloads;
 146         struct mlx5_flow_group *vport_rx_group;
 147         struct mlx5_eswitch_rep *vport_reps;
 148         DECLARE_HASHTABLE(encap_tbl, 8);
 149         DECLARE_HASHTABLE(mod_hdr_tbl, 8);
 150         u8 inline_mode;
 151         u64 num_flows;
 152         u8 encap;
 153 };
 154
 155 /* E-Switch MC FDB table hash node */
 156 struct esw_mc_addr { /* SRIOV only */
 157         struct l2addr_node     node;
 158         struct mlx5_flow_handle *uplink_rule; /* Forward to uplink rule */
 159         u32                    refcnt;
 160 };
 161
 162 struct mlx5_eswitch {
 163         struct mlx5_core_dev    *dev;
 164         struct mlx5_eswitch_fdb fdb_table;
 165         struct hlist_head       mc_table[MLX5_L2_ADDR_HASH_SIZE];
 166         struct workqueue_struct *work_queue;
 167         struct mlx5_vport       *vports;
 168         int                     total_vports;
 169         int                     enabled_vports;
 170         /* Synchronize between vport change events
 171          * and async SRIOV admin state changes
 172          */
 173         struct mutex            state_lock;
 174         struct esw_mc_addr      mc_promisc;
 175
 176         struct {
 177                 bool            enabled;
 178                 u32             root_tsar_id;
 179         } qos;
 180
 181         struct mlx5_esw_offload offloads;
 182         int                     mode;
 183 };
 184
 185 void esw_offloads_cleanup(struct mlx5_eswitch *esw, int nvports);
 186 int esw_offloads_init(struct mlx5_eswitch *esw, int nvports);
 187 void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
 188 int esw_offloads_init_reps(struct mlx5_eswitch *esw);
 189
 190 /* E-Switch API */
 191 int mlx5_eswitch_init(struct mlx5_core_dev *dev);
 192 void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
 193 void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe);
 194 int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
 195 void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
 196 int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
 197                                int vport, u8 mac[ETH_ALEN]);
 198 int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
 199                                  int vport, int link_state);
 200 int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
 201                                 int vport, u16 vlan, u8 qos);
 202 int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
 203                                     int vport, bool spoofchk);
 204 int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
 205                                  int vport_num, bool setting);
 206 int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, int vport,
 207                                 u32 max_rate, u32 min_rate);
 208 int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
 209                                   int vport, struct ifla_vf_info *ivi);
 210 int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
 211                                  int vport,
 212                                  struct ifla_vf_stats *vf_stats);
 213 void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
 214
 215 struct mlx5_flow_spec;
 216 struct mlx5_esw_flow_attr;
 217
 218 struct mlx5_flow_handle *
 219 mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
 220                                 struct mlx5_flow_spec *spec,
 221                                 struct mlx5_esw_flow_attr *attr);
 222 void
 223 mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
 224                                 struct mlx5_flow_handle *rule,
 225                                 struct mlx5_esw_flow_attr *attr);
 226
 227 struct mlx5_flow_handle *
 228 mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, int vport, u32 tirn);
 229
 230 enum {
 231         SET_VLAN_STRIP  = BIT(0),
 232         SET_VLAN_INSERT = BIT(1)
 233 };
 234
 235 enum mlx5_flow_match_level {
 236         MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
 237         MLX5_MATCH_L2   = MLX5_INLINE_MODE_L2,
 238         MLX5_MATCH_L3   = MLX5_INLINE_MODE_IP,
 239         MLX5_MATCH_L4   = MLX5_INLINE_MODE_TCP_UDP,
 240 };
 241
 242 /* current maximum for flow based vport multicasting */
 243 #define MLX5_MAX_FLOW_FWD_VPORTS 2
 244
 245 struct mlx5_esw_flow_attr {
 246         struct mlx5_eswitch_rep *in_rep;
 247         struct mlx5_eswitch_rep *out_rep[MLX5_MAX_FLOW_FWD_VPORTS];
 248         struct mlx5_core_dev    *out_mdev[MLX5_MAX_FLOW_FWD_VPORTS];
 249         struct mlx5_core_dev    *in_mdev;
 250
 251         int mirror_count;
 252         int out_count;
 253
 254         int     action;
 255         __be16  vlan_proto;
 256         u16     vlan_vid;
 257         u8      vlan_prio;
 258         bool    vlan_handled;
 259         u32     encap_id;
 260         u32     mod_hdr_id;
 261         u8      match_level;
 262         struct mlx5e_tc_flow_parse_attr *parse_attr;
 263 };
 264
 265 int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode);
 266 int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
 267 int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode);
 268 int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
 269 int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode);
 270 int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap);
 271 int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap);
 272 void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
 273
 274 int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
 275                                  struct mlx5_esw_flow_attr *attr);
 276 int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
 277                                  struct mlx5_esw_flow_attr *attr);
 278 int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
 279                                   int vport, u16 vlan, u8 qos, u8 set_flags);
 280
 281 static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev)
 282 {
 283         return MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
 284                MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
 285 }
 286
 287 #define MLX5_DEBUG_ESWITCH_MASK BIT(3)
 288
 289 #define esw_info(dev, format, ...)                              \
 290         pr_info("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
 291
 292 #define esw_warn(dev, format, ...)                              \
 293         pr_warn("(%s): E-Switch: " format, (dev)->priv.name, ##__VA_ARGS__)
 294
 295 #define esw_debug(dev, format, ...)                             \
 296         mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
 297 #else  /* CONFIG_MLX5_ESWITCH */
 298 /* eswitch API stubs */
 299 static inline int  mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
 300 static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
 301 static inline void mlx5_eswitch_vport_event(struct mlx5_eswitch *esw, struct mlx5_eqe *eqe) {}
 302 static inline int  mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
 303 static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
 304 #endif /* CONFIG_MLX5_ESWITCH */
 305
 306 #endif /* __MLX5_ESWITCH_H__ */