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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma
[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / mscc / ocelot.c
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Microsemi Ocelot Switch driver
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7 #include <linux/dsa/ocelot.h>
8 #include <linux/if_bridge.h>
9 #include <linux/ptp_classify.h>
10 #include <soc/mscc/ocelot_vcap.h>
11 #include "ocelot.h"
12 #include "ocelot_vcap.h"
13
14 #define TABLE_UPDATE_SLEEP_US 10
15 #define TABLE_UPDATE_TIMEOUT_US 100000
16
17 struct ocelot_mact_entry {
18 u8 mac[ETH_ALEN];
19 u16 vid;
20 enum macaccess_entry_type type;
21 };
22
23 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot)
24 {
25 return ocelot_read(ocelot, ANA_TABLES_MACACCESS);
26 }
27
28 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot)
29 {
30 u32 val;
31
32 return readx_poll_timeout(ocelot_mact_read_macaccess,
33 ocelot, val,
34 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) ==
35 MACACCESS_CMD_IDLE,
36 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
37 }
38
39 static void ocelot_mact_select(struct ocelot *ocelot,
40 const unsigned char mac[ETH_ALEN],
41 unsigned int vid)
42 {
43 u32 macl = 0, mach = 0;
44
45 /* Set the MAC address to handle and the vlan associated in a format
46 * understood by the hardware.
47 */
48 mach |= vid << 16;
49 mach |= mac[0] << 8;
50 mach |= mac[1] << 0;
51 macl |= mac[2] << 24;
52 macl |= mac[3] << 16;
53 macl |= mac[4] << 8;
54 macl |= mac[5] << 0;
55
56 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA);
57 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA);
58
59 }
60
61 int ocelot_mact_learn(struct ocelot *ocelot, int port,
62 const unsigned char mac[ETH_ALEN],
63 unsigned int vid, enum macaccess_entry_type type)
64 {
65 u32 cmd = ANA_TABLES_MACACCESS_VALID |
66 ANA_TABLES_MACACCESS_DEST_IDX(port) |
67 ANA_TABLES_MACACCESS_ENTRYTYPE(type) |
68 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN);
69 unsigned int mc_ports;
70
71 /* Set MAC_CPU_COPY if the CPU port is used by a multicast entry */
72 if (type == ENTRYTYPE_MACv4)
73 mc_ports = (mac[1] << 8) | mac[2];
74 else if (type == ENTRYTYPE_MACv6)
75 mc_ports = (mac[0] << 8) | mac[1];
76 else
77 mc_ports = 0;
78
79 if (mc_ports & BIT(ocelot->num_phys_ports))
80 cmd |= ANA_TABLES_MACACCESS_MAC_CPU_COPY;
81
82 ocelot_mact_select(ocelot, mac, vid);
83
84 /* Issue a write command */
85 ocelot_write(ocelot, cmd, ANA_TABLES_MACACCESS);
86
87 return ocelot_mact_wait_for_completion(ocelot);
88 }
89 EXPORT_SYMBOL(ocelot_mact_learn);
90
91 int ocelot_mact_forget(struct ocelot *ocelot,
92 const unsigned char mac[ETH_ALEN], unsigned int vid)
93 {
94 ocelot_mact_select(ocelot, mac, vid);
95
96 /* Issue a forget command */
97 ocelot_write(ocelot,
98 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET),
99 ANA_TABLES_MACACCESS);
100
101 return ocelot_mact_wait_for_completion(ocelot);
102 }
103 EXPORT_SYMBOL(ocelot_mact_forget);
104
105 static void ocelot_mact_init(struct ocelot *ocelot)
106 {
107 /* Configure the learning mode entries attributes:
108 * - Do not copy the frame to the CPU extraction queues.
109 * - Use the vlan and mac_cpoy for dmac lookup.
110 */
111 ocelot_rmw(ocelot, 0,
112 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS
113 | ANA_AGENCTRL_LEARN_FWD_KILL
114 | ANA_AGENCTRL_LEARN_IGNORE_VLAN,
115 ANA_AGENCTRL);
116
117 /* Clear the MAC table */
118 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
119 }
120
121 static void ocelot_vcap_enable(struct ocelot *ocelot, int port)
122 {
123 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
124 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
125 ANA_PORT_VCAP_S2_CFG, port);
126
127 ocelot_write_gix(ocelot, ANA_PORT_VCAP_CFG_S1_ENA,
128 ANA_PORT_VCAP_CFG, port);
129
130 ocelot_rmw_gix(ocelot, REW_PORT_CFG_ES0_EN,
131 REW_PORT_CFG_ES0_EN,
132 REW_PORT_CFG, port);
133 }
134
135 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
136 {
137 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
138 }
139
140 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot)
141 {
142 u32 val;
143
144 return readx_poll_timeout(ocelot_vlant_read_vlanaccess,
145 ocelot,
146 val,
147 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) ==
148 ANA_TABLES_VLANACCESS_CMD_IDLE,
149 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US);
150 }
151
152 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask)
153 {
154 /* Select the VID to configure */
155 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid),
156 ANA_TABLES_VLANTIDX);
157 /* Set the vlan port members mask and issue a write command */
158 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) |
159 ANA_TABLES_VLANACCESS_CMD_WRITE,
160 ANA_TABLES_VLANACCESS);
161
162 return ocelot_vlant_wait_for_completion(ocelot);
163 }
164
165 static void ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
166 struct ocelot_vlan native_vlan)
167 {
168 struct ocelot_port *ocelot_port = ocelot->ports[port];
169 u32 val = 0;
170
171 ocelot_port->native_vlan = native_vlan;
172
173 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(native_vlan.vid),
174 REW_PORT_VLAN_CFG_PORT_VID_M,
175 REW_PORT_VLAN_CFG, port);
176
177 if (ocelot_port->vlan_aware) {
178 if (native_vlan.valid)
179 /* Tag all frames except when VID == DEFAULT_VLAN */
180 val = REW_TAG_CFG_TAG_CFG(1);
181 else
182 /* Tag all frames */
183 val = REW_TAG_CFG_TAG_CFG(3);
184 } else {
185 /* Port tagging disabled. */
186 val = REW_TAG_CFG_TAG_CFG(0);
187 }
188 ocelot_rmw_gix(ocelot, val,
189 REW_TAG_CFG_TAG_CFG_M,
190 REW_TAG_CFG, port);
191 }
192
193 /* Default vlan to clasify for untagged frames (may be zero) */
194 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port,
195 struct ocelot_vlan pvid_vlan)
196 {
197 struct ocelot_port *ocelot_port = ocelot->ports[port];
198 u32 val = 0;
199
200 ocelot_port->pvid_vlan = pvid_vlan;
201
202 if (!ocelot_port->vlan_aware)
203 pvid_vlan.vid = 0;
204
205 ocelot_rmw_gix(ocelot,
206 ANA_PORT_VLAN_CFG_VLAN_VID(pvid_vlan.vid),
207 ANA_PORT_VLAN_CFG_VLAN_VID_M,
208 ANA_PORT_VLAN_CFG, port);
209
210 /* If there's no pvid, we should drop not only untagged traffic (which
211 * happens automatically), but also 802.1p traffic which gets
212 * classified to VLAN 0, but that is always in our RX filter, so it
213 * would get accepted were it not for this setting.
214 */
215 if (!pvid_vlan.valid && ocelot_port->vlan_aware)
216 val = ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
217 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA;
218
219 ocelot_rmw_gix(ocelot, val,
220 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA |
221 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA,
222 ANA_PORT_DROP_CFG, port);
223 }
224
225 static int ocelot_vlan_member_set(struct ocelot *ocelot, u32 vlan_mask, u16 vid)
226 {
227 int err;
228
229 err = ocelot_vlant_set_mask(ocelot, vid, vlan_mask);
230 if (err)
231 return err;
232
233 ocelot->vlan_mask[vid] = vlan_mask;
234
235 return 0;
236 }
237
238 static int ocelot_vlan_member_add(struct ocelot *ocelot, int port, u16 vid)
239 {
240 return ocelot_vlan_member_set(ocelot,
241 ocelot->vlan_mask[vid] | BIT(port),
242 vid);
243 }
244
245 static int ocelot_vlan_member_del(struct ocelot *ocelot, int port, u16 vid)
246 {
247 return ocelot_vlan_member_set(ocelot,
248 ocelot->vlan_mask[vid] & ~BIT(port),
249 vid);
250 }
251
252 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
253 bool vlan_aware, struct netlink_ext_ack *extack)
254 {
255 struct ocelot_vcap_block *block = &ocelot->block[VCAP_IS1];
256 struct ocelot_port *ocelot_port = ocelot->ports[port];
257 struct ocelot_vcap_filter *filter;
258 u32 val;
259
260 list_for_each_entry(filter, &block->rules, list) {
261 if (filter->ingress_port_mask & BIT(port) &&
262 filter->action.vid_replace_ena) {
263 NL_SET_ERR_MSG_MOD(extack,
264 "Cannot change VLAN state with vlan modify rules active");
265 return -EBUSY;
266 }
267 }
268
269 ocelot_port->vlan_aware = vlan_aware;
270
271 if (vlan_aware)
272 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
273 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1);
274 else
275 val = 0;
276 ocelot_rmw_gix(ocelot, val,
277 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
278 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M,
279 ANA_PORT_VLAN_CFG, port);
280
281 ocelot_port_set_pvid(ocelot, port, ocelot_port->pvid_vlan);
282 ocelot_port_set_native_vlan(ocelot, port, ocelot_port->native_vlan);
283
284 return 0;
285 }
286 EXPORT_SYMBOL(ocelot_port_vlan_filtering);
287
288 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
289 bool untagged, struct netlink_ext_ack *extack)
290 {
291 struct ocelot_port *ocelot_port = ocelot->ports[port];
292
293 /* Deny changing the native VLAN, but always permit deleting it */
294 if (untagged && ocelot_port->native_vlan.vid != vid &&
295 ocelot_port->native_vlan.valid) {
296 NL_SET_ERR_MSG_MOD(extack,
297 "Port already has a native VLAN");
298 return -EBUSY;
299 }
300
301 return 0;
302 }
303 EXPORT_SYMBOL(ocelot_vlan_prepare);
304
305 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
306 bool untagged)
307 {
308 int err;
309
310 err = ocelot_vlan_member_add(ocelot, port, vid);
311 if (err)
312 return err;
313
314 /* Default ingress vlan classification */
315 if (pvid) {
316 struct ocelot_vlan pvid_vlan;
317
318 pvid_vlan.vid = vid;
319 pvid_vlan.valid = true;
320 ocelot_port_set_pvid(ocelot, port, pvid_vlan);
321 }
322
323 /* Untagged egress vlan clasification */
324 if (untagged) {
325 struct ocelot_vlan native_vlan;
326
327 native_vlan.vid = vid;
328 native_vlan.valid = true;
329 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
330 }
331
332 return 0;
333 }
334 EXPORT_SYMBOL(ocelot_vlan_add);
335
336 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
337 {
338 struct ocelot_port *ocelot_port = ocelot->ports[port];
339 int err;
340
341 err = ocelot_vlan_member_del(ocelot, port, vid);
342 if (err)
343 return err;
344
345 /* Ingress */
346 if (ocelot_port->pvid_vlan.vid == vid) {
347 struct ocelot_vlan pvid_vlan = {0};
348
349 ocelot_port_set_pvid(ocelot, port, pvid_vlan);
350 }
351
352 /* Egress */
353 if (ocelot_port->native_vlan.vid == vid) {
354 struct ocelot_vlan native_vlan = {0};
355
356 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
357 }
358
359 return 0;
360 }
361 EXPORT_SYMBOL(ocelot_vlan_del);
362
363 static void ocelot_vlan_init(struct ocelot *ocelot)
364 {
365 unsigned long all_ports = GENMASK(ocelot->num_phys_ports - 1, 0);
366 u16 port, vid;
367
368 /* Clear VLAN table, by default all ports are members of all VLANs */
369 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT,
370 ANA_TABLES_VLANACCESS);
371 ocelot_vlant_wait_for_completion(ocelot);
372
373 /* Configure the port VLAN memberships */
374 for (vid = 1; vid < VLAN_N_VID; vid++)
375 ocelot_vlan_member_set(ocelot, 0, vid);
376
377 /* Because VLAN filtering is enabled, we need VID 0 to get untagged
378 * traffic. It is added automatically if 8021q module is loaded, but
379 * we can't rely on it since module may be not loaded.
380 */
381 ocelot_vlan_member_set(ocelot, all_ports, 0);
382
383 /* Set vlan ingress filter mask to all ports but the CPU port by
384 * default.
385 */
386 ocelot_write(ocelot, all_ports, ANA_VLANMASK);
387
388 for (port = 0; port < ocelot->num_phys_ports; port++) {
389 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port);
390 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port);
391 }
392 }
393
394 static u32 ocelot_read_eq_avail(struct ocelot *ocelot, int port)
395 {
396 return ocelot_read_rix(ocelot, QSYS_SW_STATUS, port);
397 }
398
399 static int ocelot_port_flush(struct ocelot *ocelot, int port)
400 {
401 unsigned int pause_ena;
402 int err, val;
403
404 /* Disable dequeuing from the egress queues */
405 ocelot_rmw_rix(ocelot, QSYS_PORT_MODE_DEQUEUE_DIS,
406 QSYS_PORT_MODE_DEQUEUE_DIS,
407 QSYS_PORT_MODE, port);
408
409 /* Disable flow control */
410 ocelot_fields_read(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, &pause_ena);
411 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
412
413 /* Disable priority flow control */
414 ocelot_fields_write(ocelot, port,
415 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA, 0);
416
417 /* Wait at least the time it takes to receive a frame of maximum length
418 * at the port.
419 * Worst-case delays for 10 kilobyte jumbo frames are:
420 * 8 ms on a 10M port
421 * 800 μs on a 100M port
422 * 80 μs on a 1G port
423 * 32 μs on a 2.5G port
424 */
425 usleep_range(8000, 10000);
426
427 /* Disable half duplex backpressure. */
428 ocelot_rmw_rix(ocelot, 0, SYS_FRONT_PORT_MODE_HDX_MODE,
429 SYS_FRONT_PORT_MODE, port);
430
431 /* Flush the queues associated with the port. */
432 ocelot_rmw_gix(ocelot, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG_FLUSH_ENA,
433 REW_PORT_CFG, port);
434
435 /* Enable dequeuing from the egress queues. */
436 ocelot_rmw_rix(ocelot, 0, QSYS_PORT_MODE_DEQUEUE_DIS, QSYS_PORT_MODE,
437 port);
438
439 /* Wait until flushing is complete. */
440 err = read_poll_timeout(ocelot_read_eq_avail, val, !val,
441 100, 2000000, false, ocelot, port);
442
443 /* Clear flushing again. */
444 ocelot_rmw_gix(ocelot, 0, REW_PORT_CFG_FLUSH_ENA, REW_PORT_CFG, port);
445
446 /* Re-enable flow control */
447 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, pause_ena);
448
449 return err;
450 }
451
452 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
453 unsigned int link_an_mode,
454 phy_interface_t interface,
455 unsigned long quirks)
456 {
457 struct ocelot_port *ocelot_port = ocelot->ports[port];
458 int err;
459
460 ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
461 DEV_MAC_ENA_CFG);
462
463 ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
464
465 err = ocelot_port_flush(ocelot, port);
466 if (err)
467 dev_err(ocelot->dev, "failed to flush port %d: %d\n",
468 port, err);
469
470 /* Put the port in reset. */
471 if (interface != PHY_INTERFACE_MODE_QSGMII ||
472 !(quirks & OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP))
473 ocelot_port_rmwl(ocelot_port,
474 DEV_CLOCK_CFG_MAC_TX_RST |
475 DEV_CLOCK_CFG_MAC_TX_RST,
476 DEV_CLOCK_CFG_MAC_TX_RST |
477 DEV_CLOCK_CFG_MAC_TX_RST,
478 DEV_CLOCK_CFG);
479 }
480 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_down);
481
482 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
483 struct phy_device *phydev,
484 unsigned int link_an_mode,
485 phy_interface_t interface,
486 int speed, int duplex,
487 bool tx_pause, bool rx_pause,
488 unsigned long quirks)
489 {
490 struct ocelot_port *ocelot_port = ocelot->ports[port];
491 int mac_speed, mode = 0;
492 u32 mac_fc_cfg;
493
494 /* The MAC might be integrated in systems where the MAC speed is fixed
495 * and it's the PCS who is performing the rate adaptation, so we have
496 * to write "1000Mbps" into the LINK_SPEED field of DEV_CLOCK_CFG
497 * (which is also its default value).
498 */
499 if ((quirks & OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION) ||
500 speed == SPEED_1000) {
501 mac_speed = OCELOT_SPEED_1000;
502 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
503 } else if (speed == SPEED_2500) {
504 mac_speed = OCELOT_SPEED_2500;
505 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
506 } else if (speed == SPEED_100) {
507 mac_speed = OCELOT_SPEED_100;
508 } else {
509 mac_speed = OCELOT_SPEED_10;
510 }
511
512 if (duplex == DUPLEX_FULL)
513 mode |= DEV_MAC_MODE_CFG_FDX_ENA;
514
515 ocelot_port_writel(ocelot_port, mode, DEV_MAC_MODE_CFG);
516
517 /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
518 * PORT_RST bits in DEV_CLOCK_CFG.
519 */
520 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
521 DEV_CLOCK_CFG);
522
523 switch (speed) {
524 case SPEED_10:
525 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_10);
526 break;
527 case SPEED_100:
528 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_100);
529 break;
530 case SPEED_1000:
531 case SPEED_2500:
532 mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(OCELOT_SPEED_1000);
533 break;
534 default:
535 dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
536 port, speed);
537 return;
538 }
539
540 /* Handle RX pause in all cases, with 2500base-X this is used for rate
541 * adaptation.
542 */
543 mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
544
545 if (tx_pause)
546 mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
547 SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
548 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
549 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
550
551 /* Flow control. Link speed is only used here to evaluate the time
552 * specification in incoming pause frames.
553 */
554 ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
555
556 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
557
558 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, tx_pause);
559
560 /* Undo the effects of ocelot_phylink_mac_link_down:
561 * enable MAC module
562 */
563 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
564 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
565
566 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
567 * reset
568 */
569 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
570 DEV_CLOCK_CFG);
571
572 /* No PFC */
573 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
574 ANA_PFC_PFC_CFG, port);
575
576 /* Core: Enable port for frame transfer */
577 ocelot_fields_write(ocelot, port,
578 QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
579 }
580 EXPORT_SYMBOL_GPL(ocelot_phylink_mac_link_up);
581
582 static void ocelot_port_add_txtstamp_skb(struct ocelot *ocelot, int port,
583 struct sk_buff *clone)
584 {
585 struct ocelot_port *ocelot_port = ocelot->ports[port];
586
587 spin_lock(&ocelot_port->ts_id_lock);
588
589 skb_shinfo(clone)->tx_flags |= SKBTX_IN_PROGRESS;
590 /* Store timestamp ID in OCELOT_SKB_CB(clone)->ts_id */
591 OCELOT_SKB_CB(clone)->ts_id = ocelot_port->ts_id;
592 ocelot_port->ts_id = (ocelot_port->ts_id + 1) % 4;
593 skb_queue_tail(&ocelot_port->tx_skbs, clone);
594
595 spin_unlock(&ocelot_port->ts_id_lock);
596 }
597
598 u32 ocelot_ptp_rew_op(struct sk_buff *skb)
599 {
600 struct sk_buff *clone = OCELOT_SKB_CB(skb)->clone;
601 u8 ptp_cmd = OCELOT_SKB_CB(skb)->ptp_cmd;
602 u32 rew_op = 0;
603
604 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP && clone) {
605 rew_op = ptp_cmd;
606 rew_op |= OCELOT_SKB_CB(clone)->ts_id << 3;
607 } else if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) {
608 rew_op = ptp_cmd;
609 }
610
611 return rew_op;
612 }
613 EXPORT_SYMBOL(ocelot_ptp_rew_op);
614
615 static bool ocelot_ptp_is_onestep_sync(struct sk_buff *skb)
616 {
617 struct ptp_header *hdr;
618 unsigned int ptp_class;
619 u8 msgtype, twostep;
620
621 ptp_class = ptp_classify_raw(skb);
622 if (ptp_class == PTP_CLASS_NONE)
623 return false;
624
625 hdr = ptp_parse_header(skb, ptp_class);
626 if (!hdr)
627 return false;
628
629 msgtype = ptp_get_msgtype(hdr, ptp_class);
630 twostep = hdr->flag_field[0] & 0x2;
631
632 if (msgtype == PTP_MSGTYPE_SYNC && twostep == 0)
633 return true;
634
635 return false;
636 }
637
638 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
639 struct sk_buff *skb,
640 struct sk_buff **clone)
641 {
642 struct ocelot_port *ocelot_port = ocelot->ports[port];
643 u8 ptp_cmd = ocelot_port->ptp_cmd;
644
645 /* Store ptp_cmd in OCELOT_SKB_CB(skb)->ptp_cmd */
646 if (ptp_cmd == IFH_REW_OP_ORIGIN_PTP) {
647 if (ocelot_ptp_is_onestep_sync(skb)) {
648 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
649 return 0;
650 }
651
652 /* Fall back to two-step timestamping */
653 ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
654 }
655
656 if (ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
657 *clone = skb_clone_sk(skb);
658 if (!(*clone))
659 return -ENOMEM;
660
661 ocelot_port_add_txtstamp_skb(ocelot, port, *clone);
662 OCELOT_SKB_CB(skb)->ptp_cmd = ptp_cmd;
663 }
664
665 return 0;
666 }
667 EXPORT_SYMBOL(ocelot_port_txtstamp_request);
668
669 static void ocelot_get_hwtimestamp(struct ocelot *ocelot,
670 struct timespec64 *ts)
671 {
672 unsigned long flags;
673 u32 val;
674
675 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags);
676
677 /* Read current PTP time to get seconds */
678 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN);
679
680 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM);
681 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE);
682 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN);
683 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN);
684
685 /* Read packet HW timestamp from FIFO */
686 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP);
687 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val);
688
689 /* Sec has incremented since the ts was registered */
690 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC))
691 ts->tv_sec--;
692
693 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags);
694 }
695
696 void ocelot_get_txtstamp(struct ocelot *ocelot)
697 {
698 int budget = OCELOT_PTP_QUEUE_SZ;
699
700 while (budget--) {
701 struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
702 struct skb_shared_hwtstamps shhwtstamps;
703 struct ocelot_port *port;
704 struct timespec64 ts;
705 unsigned long flags;
706 u32 val, id, txport;
707
708 val = ocelot_read(ocelot, SYS_PTP_STATUS);
709
710 /* Check if a timestamp can be retrieved */
711 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD))
712 break;
713
714 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL);
715
716 /* Retrieve the ts ID and Tx port */
717 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val);
718 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val);
719
720 /* Retrieve its associated skb */
721 port = ocelot->ports[txport];
722
723 spin_lock_irqsave(&port->tx_skbs.lock, flags);
724
725 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
726 if (OCELOT_SKB_CB(skb)->ts_id != id)
727 continue;
728 __skb_unlink(skb, &port->tx_skbs);
729 skb_match = skb;
730 break;
731 }
732
733 spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
734
735 /* Get the h/w timestamp */
736 ocelot_get_hwtimestamp(ocelot, &ts);
737
738 if (unlikely(!skb_match))
739 continue;
740
741 /* Set the timestamp into the skb */
742 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
743 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
744 skb_complete_tx_timestamp(skb_match, &shhwtstamps);
745
746 /* Next ts */
747 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT);
748 }
749 }
750 EXPORT_SYMBOL(ocelot_get_txtstamp);
751
752 static int ocelot_rx_frame_word(struct ocelot *ocelot, u8 grp, bool ifh,
753 u32 *rval)
754 {
755 u32 bytes_valid, val;
756
757 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
758 if (val == XTR_NOT_READY) {
759 if (ifh)
760 return -EIO;
761
762 do {
763 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
764 } while (val == XTR_NOT_READY);
765 }
766
767 switch (val) {
768 case XTR_ABORT:
769 return -EIO;
770 case XTR_EOF_0:
771 case XTR_EOF_1:
772 case XTR_EOF_2:
773 case XTR_EOF_3:
774 case XTR_PRUNED:
775 bytes_valid = XTR_VALID_BYTES(val);
776 val = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
777 if (val == XTR_ESCAPE)
778 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
779 else
780 *rval = val;
781
782 return bytes_valid;
783 case XTR_ESCAPE:
784 *rval = ocelot_read_rix(ocelot, QS_XTR_RD, grp);
785
786 return 4;
787 default:
788 *rval = val;
789
790 return 4;
791 }
792 }
793
794 static int ocelot_xtr_poll_xfh(struct ocelot *ocelot, int grp, u32 *xfh)
795 {
796 int i, err = 0;
797
798 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) {
799 err = ocelot_rx_frame_word(ocelot, grp, true, &xfh[i]);
800 if (err != 4)
801 return (err < 0) ? err : -EIO;
802 }
803
804 return 0;
805 }
806
807 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **nskb)
808 {
809 struct skb_shared_hwtstamps *shhwtstamps;
810 u64 tod_in_ns, full_ts_in_ns;
811 u64 timestamp, src_port, len;
812 u32 xfh[OCELOT_TAG_LEN / 4];
813 struct net_device *dev;
814 struct timespec64 ts;
815 struct sk_buff *skb;
816 int sz, buf_len;
817 u32 val, *buf;
818 int err;
819
820 err = ocelot_xtr_poll_xfh(ocelot, grp, xfh);
821 if (err)
822 return err;
823
824 ocelot_xfh_get_src_port(xfh, &src_port);
825 ocelot_xfh_get_len(xfh, &len);
826 ocelot_xfh_get_rew_val(xfh, &timestamp);
827
828 if (WARN_ON(src_port >= ocelot->num_phys_ports))
829 return -EINVAL;
830
831 dev = ocelot->ops->port_to_netdev(ocelot, src_port);
832 if (!dev)
833 return -EINVAL;
834
835 skb = netdev_alloc_skb(dev, len);
836 if (unlikely(!skb)) {
837 netdev_err(dev, "Unable to allocate sk_buff\n");
838 return -ENOMEM;
839 }
840
841 buf_len = len - ETH_FCS_LEN;
842 buf = (u32 *)skb_put(skb, buf_len);
843
844 len = 0;
845 do {
846 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
847 if (sz < 0) {
848 err = sz;
849 goto out_free_skb;
850 }
851 *buf++ = val;
852 len += sz;
853 } while (len < buf_len);
854
855 /* Read the FCS */
856 sz = ocelot_rx_frame_word(ocelot, grp, false, &val);
857 if (sz < 0) {
858 err = sz;
859 goto out_free_skb;
860 }
861
862 /* Update the statistics if part of the FCS was read before */
863 len -= ETH_FCS_LEN - sz;
864
865 if (unlikely(dev->features & NETIF_F_RXFCS)) {
866 buf = (u32 *)skb_put(skb, ETH_FCS_LEN);
867 *buf = val;
868 }
869
870 if (ocelot->ptp) {
871 ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
872
873 tod_in_ns = ktime_set(ts.tv_sec, ts.tv_nsec);
874 if ((tod_in_ns & 0xffffffff) < timestamp)
875 full_ts_in_ns = (((tod_in_ns >> 32) - 1) << 32) |
876 timestamp;
877 else
878 full_ts_in_ns = (tod_in_ns & GENMASK_ULL(63, 32)) |
879 timestamp;
880
881 shhwtstamps = skb_hwtstamps(skb);
882 memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
883 shhwtstamps->hwtstamp = full_ts_in_ns;
884 }
885
886 /* Everything we see on an interface that is in the HW bridge
887 * has already been forwarded.
888 */
889 if (ocelot->ports[src_port]->bridge)
890 skb->offload_fwd_mark = 1;
891
892 skb->protocol = eth_type_trans(skb, dev);
893
894 *nskb = skb;
895
896 return 0;
897
898 out_free_skb:
899 kfree_skb(skb);
900 return err;
901 }
902 EXPORT_SYMBOL(ocelot_xtr_poll_frame);
903
904 bool ocelot_can_inject(struct ocelot *ocelot, int grp)
905 {
906 u32 val = ocelot_read(ocelot, QS_INJ_STATUS);
907
908 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))))
909 return false;
910 if (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))
911 return false;
912
913 return true;
914 }
915 EXPORT_SYMBOL(ocelot_can_inject);
916
917 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
918 u32 rew_op, struct sk_buff *skb)
919 {
920 u32 ifh[OCELOT_TAG_LEN / 4] = {0};
921 unsigned int i, count, last;
922
923 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
924 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp);
925
926 ocelot_ifh_set_bypass(ifh, 1);
927 ocelot_ifh_set_dest(ifh, BIT_ULL(port));
928 ocelot_ifh_set_tag_type(ifh, IFH_TAG_TYPE_C);
929 ocelot_ifh_set_vid(ifh, skb_vlan_tag_get(skb));
930 ocelot_ifh_set_rew_op(ifh, rew_op);
931
932 for (i = 0; i < OCELOT_TAG_LEN / 4; i++)
933 ocelot_write_rix(ocelot, ifh[i], QS_INJ_WR, grp);
934
935 count = DIV_ROUND_UP(skb->len, 4);
936 last = skb->len % 4;
937 for (i = 0; i < count; i++)
938 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp);
939
940 /* Add padding */
941 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) {
942 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
943 i++;
944 }
945
946 /* Indicate EOF and valid bytes in last word */
947 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) |
948 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) |
949 QS_INJ_CTRL_EOF,
950 QS_INJ_CTRL, grp);
951
952 /* Add dummy CRC */
953 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp);
954 skb_tx_timestamp(skb);
955
956 skb->dev->stats.tx_packets++;
957 skb->dev->stats.tx_bytes += skb->len;
958 }
959 EXPORT_SYMBOL(ocelot_port_inject_frame);
960
961 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp)
962 {
963 while (ocelot_read(ocelot, QS_XTR_DATA_PRESENT) & BIT(grp))
964 ocelot_read_rix(ocelot, QS_XTR_RD, grp);
965 }
966 EXPORT_SYMBOL(ocelot_drain_cpu_queue);
967
968 int ocelot_fdb_add(struct ocelot *ocelot, int port,
969 const unsigned char *addr, u16 vid)
970 {
971 int pgid = port;
972
973 if (port == ocelot->npi)
974 pgid = PGID_CPU;
975
976 return ocelot_mact_learn(ocelot, pgid, addr, vid, ENTRYTYPE_LOCKED);
977 }
978 EXPORT_SYMBOL(ocelot_fdb_add);
979
980 int ocelot_fdb_del(struct ocelot *ocelot, int port,
981 const unsigned char *addr, u16 vid)
982 {
983 return ocelot_mact_forget(ocelot, addr, vid);
984 }
985 EXPORT_SYMBOL(ocelot_fdb_del);
986
987 int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid,
988 bool is_static, void *data)
989 {
990 struct ocelot_dump_ctx *dump = data;
991 u32 portid = NETLINK_CB(dump->cb->skb).portid;
992 u32 seq = dump->cb->nlh->nlmsg_seq;
993 struct nlmsghdr *nlh;
994 struct ndmsg *ndm;
995
996 if (dump->idx < dump->cb->args[2])
997 goto skip;
998
999 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH,
1000 sizeof(*ndm), NLM_F_MULTI);
1001 if (!nlh)
1002 return -EMSGSIZE;
1003
1004 ndm = nlmsg_data(nlh);
1005 ndm->ndm_family = AF_BRIDGE;
1006 ndm->ndm_pad1 = 0;
1007 ndm->ndm_pad2 = 0;
1008 ndm->ndm_flags = NTF_SELF;
1009 ndm->ndm_type = 0;
1010 ndm->ndm_ifindex = dump->dev->ifindex;
1011 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
1012
1013 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr))
1014 goto nla_put_failure;
1015
1016 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid))
1017 goto nla_put_failure;
1018
1019 nlmsg_end(dump->skb, nlh);
1020
1021 skip:
1022 dump->idx++;
1023 return 0;
1024
1025 nla_put_failure:
1026 nlmsg_cancel(dump->skb, nlh);
1027 return -EMSGSIZE;
1028 }
1029 EXPORT_SYMBOL(ocelot_port_fdb_do_dump);
1030
1031 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col,
1032 struct ocelot_mact_entry *entry)
1033 {
1034 u32 val, dst, macl, mach;
1035 char mac[ETH_ALEN];
1036
1037 /* Set row and column to read from */
1038 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row);
1039 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col);
1040
1041 /* Issue a read command */
1042 ocelot_write(ocelot,
1043 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ),
1044 ANA_TABLES_MACACCESS);
1045
1046 if (ocelot_mact_wait_for_completion(ocelot))
1047 return -ETIMEDOUT;
1048
1049 /* Read the entry flags */
1050 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS);
1051 if (!(val & ANA_TABLES_MACACCESS_VALID))
1052 return -EINVAL;
1053
1054 /* If the entry read has another port configured as its destination,
1055 * do not report it.
1056 */
1057 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3;
1058 if (dst != port)
1059 return -EINVAL;
1060
1061 /* Get the entry's MAC address and VLAN id */
1062 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA);
1063 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA);
1064
1065 mac[0] = (mach >> 8) & 0xff;
1066 mac[1] = (mach >> 0) & 0xff;
1067 mac[2] = (macl >> 24) & 0xff;
1068 mac[3] = (macl >> 16) & 0xff;
1069 mac[4] = (macl >> 8) & 0xff;
1070 mac[5] = (macl >> 0) & 0xff;
1071
1072 entry->vid = (mach >> 16) & 0xfff;
1073 ether_addr_copy(entry->mac, mac);
1074
1075 return 0;
1076 }
1077
1078 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1079 dsa_fdb_dump_cb_t *cb, void *data)
1080 {
1081 int i, j;
1082
1083 /* Loop through all the mac tables entries. */
1084 for (i = 0; i < ocelot->num_mact_rows; i++) {
1085 for (j = 0; j < 4; j++) {
1086 struct ocelot_mact_entry entry;
1087 bool is_static;
1088 int ret;
1089
1090 ret = ocelot_mact_read(ocelot, port, i, j, &entry);
1091 /* If the entry is invalid (wrong port, invalid...),
1092 * skip it.
1093 */
1094 if (ret == -EINVAL)
1095 continue;
1096 else if (ret)
1097 return ret;
1098
1099 is_static = (entry.type == ENTRYTYPE_LOCKED);
1100
1101 ret = cb(entry.mac, entry.vid, is_static, data);
1102 if (ret)
1103 return ret;
1104 }
1105 }
1106
1107 return 0;
1108 }
1109 EXPORT_SYMBOL(ocelot_fdb_dump);
1110
1111 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr)
1112 {
1113 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config,
1114 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0;
1115 }
1116 EXPORT_SYMBOL(ocelot_hwstamp_get);
1117
1118 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr)
1119 {
1120 struct ocelot_port *ocelot_port = ocelot->ports[port];
1121 struct hwtstamp_config cfg;
1122
1123 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1124 return -EFAULT;
1125
1126 /* reserved for future extensions */
1127 if (cfg.flags)
1128 return -EINVAL;
1129
1130 /* Tx type sanity check */
1131 switch (cfg.tx_type) {
1132 case HWTSTAMP_TX_ON:
1133 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP;
1134 break;
1135 case HWTSTAMP_TX_ONESTEP_SYNC:
1136 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we
1137 * need to update the origin time.
1138 */
1139 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP;
1140 break;
1141 case HWTSTAMP_TX_OFF:
1142 ocelot_port->ptp_cmd = 0;
1143 break;
1144 default:
1145 return -ERANGE;
1146 }
1147
1148 mutex_lock(&ocelot->ptp_lock);
1149
1150 switch (cfg.rx_filter) {
1151 case HWTSTAMP_FILTER_NONE:
1152 break;
1153 case HWTSTAMP_FILTER_ALL:
1154 case HWTSTAMP_FILTER_SOME:
1155 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1156 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1157 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1158 case HWTSTAMP_FILTER_NTP_ALL:
1159 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1160 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1161 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1162 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1163 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1164 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1165 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1166 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1167 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1168 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1169 break;
1170 default:
1171 mutex_unlock(&ocelot->ptp_lock);
1172 return -ERANGE;
1173 }
1174
1175 /* Commit back the result & save it */
1176 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg));
1177 mutex_unlock(&ocelot->ptp_lock);
1178
1179 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1180 }
1181 EXPORT_SYMBOL(ocelot_hwstamp_set);
1182
1183 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
1184 {
1185 int i;
1186
1187 if (sset != ETH_SS_STATS)
1188 return;
1189
1190 for (i = 0; i < ocelot->num_stats; i++)
1191 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
1192 ETH_GSTRING_LEN);
1193 }
1194 EXPORT_SYMBOL(ocelot_get_strings);
1195
1196 static void ocelot_update_stats(struct ocelot *ocelot)
1197 {
1198 int i, j;
1199
1200 mutex_lock(&ocelot->stats_lock);
1201
1202 for (i = 0; i < ocelot->num_phys_ports; i++) {
1203 /* Configure the port to read the stats from */
1204 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG);
1205
1206 for (j = 0; j < ocelot->num_stats; j++) {
1207 u32 val;
1208 unsigned int idx = i * ocelot->num_stats + j;
1209
1210 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS,
1211 ocelot->stats_layout[j].offset);
1212
1213 if (val < (ocelot->stats[idx] & U32_MAX))
1214 ocelot->stats[idx] += (u64)1 << 32;
1215
1216 ocelot->stats[idx] = (ocelot->stats[idx] &
1217 ~(u64)U32_MAX) + val;
1218 }
1219 }
1220
1221 mutex_unlock(&ocelot->stats_lock);
1222 }
1223
1224 static void ocelot_check_stats_work(struct work_struct *work)
1225 {
1226 struct delayed_work *del_work = to_delayed_work(work);
1227 struct ocelot *ocelot = container_of(del_work, struct ocelot,
1228 stats_work);
1229
1230 ocelot_update_stats(ocelot);
1231
1232 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
1233 OCELOT_STATS_CHECK_DELAY);
1234 }
1235
1236 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
1237 {
1238 int i;
1239
1240 /* check and update now */
1241 ocelot_update_stats(ocelot);
1242
1243 /* Copy all counters */
1244 for (i = 0; i < ocelot->num_stats; i++)
1245 *data++ = ocelot->stats[port * ocelot->num_stats + i];
1246 }
1247 EXPORT_SYMBOL(ocelot_get_ethtool_stats);
1248
1249 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
1250 {
1251 if (sset != ETH_SS_STATS)
1252 return -EOPNOTSUPP;
1253
1254 return ocelot->num_stats;
1255 }
1256 EXPORT_SYMBOL(ocelot_get_sset_count);
1257
1258 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1259 struct ethtool_ts_info *info)
1260 {
1261 info->phc_index = ocelot->ptp_clock ?
1262 ptp_clock_index(ocelot->ptp_clock) : -1;
1263 if (info->phc_index == -1) {
1264 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1265 SOF_TIMESTAMPING_RX_SOFTWARE |
1266 SOF_TIMESTAMPING_SOFTWARE;
1267 return 0;
1268 }
1269 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE |
1270 SOF_TIMESTAMPING_RX_SOFTWARE |
1271 SOF_TIMESTAMPING_SOFTWARE |
1272 SOF_TIMESTAMPING_TX_HARDWARE |
1273 SOF_TIMESTAMPING_RX_HARDWARE |
1274 SOF_TIMESTAMPING_RAW_HARDWARE;
1275 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) |
1276 BIT(HWTSTAMP_TX_ONESTEP_SYNC);
1277 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL);
1278
1279 return 0;
1280 }
1281 EXPORT_SYMBOL(ocelot_get_ts_info);
1282
1283 static u32 ocelot_get_bond_mask(struct ocelot *ocelot, struct net_device *bond,
1284 bool only_active_ports)
1285 {
1286 u32 mask = 0;
1287 int port;
1288
1289 for (port = 0; port < ocelot->num_phys_ports; port++) {
1290 struct ocelot_port *ocelot_port = ocelot->ports[port];
1291
1292 if (!ocelot_port)
1293 continue;
1294
1295 if (ocelot_port->bond == bond) {
1296 if (only_active_ports && !ocelot_port->lag_tx_active)
1297 continue;
1298
1299 mask |= BIT(port);
1300 }
1301 }
1302
1303 return mask;
1304 }
1305
1306 static u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot,
1307 struct net_device *bridge)
1308 {
1309 u32 mask = 0;
1310 int port;
1311
1312 for (port = 0; port < ocelot->num_phys_ports; port++) {
1313 struct ocelot_port *ocelot_port = ocelot->ports[port];
1314
1315 if (!ocelot_port)
1316 continue;
1317
1318 if (ocelot_port->stp_state == BR_STATE_FORWARDING &&
1319 ocelot_port->bridge == bridge)
1320 mask |= BIT(port);
1321 }
1322
1323 return mask;
1324 }
1325
1326 static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot)
1327 {
1328 u32 mask = 0;
1329 int port;
1330
1331 for (port = 0; port < ocelot->num_phys_ports; port++) {
1332 struct ocelot_port *ocelot_port = ocelot->ports[port];
1333
1334 if (!ocelot_port)
1335 continue;
1336
1337 if (ocelot_port->is_dsa_8021q_cpu)
1338 mask |= BIT(port);
1339 }
1340
1341 return mask;
1342 }
1343
1344 void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot)
1345 {
1346 unsigned long cpu_fwd_mask;
1347 int port;
1348
1349 /* If a DSA tag_8021q CPU exists, it needs to be included in the
1350 * regular forwarding path of the front ports regardless of whether
1351 * those are bridged or standalone.
1352 * If DSA tag_8021q is not used, this returns 0, which is fine because
1353 * the hardware-based CPU port module can be a destination for packets
1354 * even if it isn't part of PGID_SRC.
1355 */
1356 cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot);
1357
1358 /* Apply FWD mask. The loop is needed to add/remove the current port as
1359 * a source for the other ports.
1360 */
1361 for (port = 0; port < ocelot->num_phys_ports; port++) {
1362 struct ocelot_port *ocelot_port = ocelot->ports[port];
1363 unsigned long mask;
1364
1365 if (!ocelot_port) {
1366 /* Unused ports can't send anywhere */
1367 mask = 0;
1368 } else if (ocelot_port->is_dsa_8021q_cpu) {
1369 /* The DSA tag_8021q CPU ports need to be able to
1370 * forward packets to all other ports except for
1371 * themselves
1372 */
1373 mask = GENMASK(ocelot->num_phys_ports - 1, 0);
1374 mask &= ~cpu_fwd_mask;
1375 } else if (ocelot_port->bridge) {
1376 struct net_device *bridge = ocelot_port->bridge;
1377 struct net_device *bond = ocelot_port->bond;
1378
1379 mask = ocelot_get_bridge_fwd_mask(ocelot, bridge);
1380 mask |= cpu_fwd_mask;
1381 mask &= ~BIT(port);
1382 if (bond) {
1383 mask &= ~ocelot_get_bond_mask(ocelot, bond,
1384 false);
1385 }
1386 } else {
1387 /* Standalone ports forward only to DSA tag_8021q CPU
1388 * ports (if those exist), or to the hardware CPU port
1389 * module otherwise.
1390 */
1391 mask = cpu_fwd_mask;
1392 }
1393
1394 ocelot_write_rix(ocelot, mask, ANA_PGID_PGID, PGID_SRC + port);
1395 }
1396 }
1397 EXPORT_SYMBOL(ocelot_apply_bridge_fwd_mask);
1398
1399 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
1400 {
1401 struct ocelot_port *ocelot_port = ocelot->ports[port];
1402 u32 learn_ena = 0;
1403
1404 ocelot_port->stp_state = state;
1405
1406 if ((state == BR_STATE_LEARNING || state == BR_STATE_FORWARDING) &&
1407 ocelot_port->learn_ena)
1408 learn_ena = ANA_PORT_PORT_CFG_LEARN_ENA;
1409
1410 ocelot_rmw_gix(ocelot, learn_ena, ANA_PORT_PORT_CFG_LEARN_ENA,
1411 ANA_PORT_PORT_CFG, port);
1412
1413 ocelot_apply_bridge_fwd_mask(ocelot);
1414 }
1415 EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
1416
1417 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
1418 {
1419 unsigned int age_period = ANA_AUTOAGE_AGE_PERIOD(msecs / 2000);
1420
1421 /* Setting AGE_PERIOD to zero effectively disables automatic aging,
1422 * which is clearly not what our intention is. So avoid that.
1423 */
1424 if (!age_period)
1425 age_period = 1;
1426
1427 ocelot_rmw(ocelot, age_period, ANA_AUTOAGE_AGE_PERIOD_M, ANA_AUTOAGE);
1428 }
1429 EXPORT_SYMBOL(ocelot_set_ageing_time);
1430
1431 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot,
1432 const unsigned char *addr,
1433 u16 vid)
1434 {
1435 struct ocelot_multicast *mc;
1436
1437 list_for_each_entry(mc, &ocelot->multicast, list) {
1438 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid)
1439 return mc;
1440 }
1441
1442 return NULL;
1443 }
1444
1445 static enum macaccess_entry_type ocelot_classify_mdb(const unsigned char *addr)
1446 {
1447 if (addr[0] == 0x01 && addr[1] == 0x00 && addr[2] == 0x5e)
1448 return ENTRYTYPE_MACv4;
1449 if (addr[0] == 0x33 && addr[1] == 0x33)
1450 return ENTRYTYPE_MACv6;
1451 return ENTRYTYPE_LOCKED;
1452 }
1453
1454 static struct ocelot_pgid *ocelot_pgid_alloc(struct ocelot *ocelot, int index,
1455 unsigned long ports)
1456 {
1457 struct ocelot_pgid *pgid;
1458
1459 pgid = kzalloc(sizeof(*pgid), GFP_KERNEL);
1460 if (!pgid)
1461 return ERR_PTR(-ENOMEM);
1462
1463 pgid->ports = ports;
1464 pgid->index = index;
1465 refcount_set(&pgid->refcount, 1);
1466 list_add_tail(&pgid->list, &ocelot->pgids);
1467
1468 return pgid;
1469 }
1470
1471 static void ocelot_pgid_free(struct ocelot *ocelot, struct ocelot_pgid *pgid)
1472 {
1473 if (!refcount_dec_and_test(&pgid->refcount))
1474 return;
1475
1476 list_del(&pgid->list);
1477 kfree(pgid);
1478 }
1479
1480 static struct ocelot_pgid *ocelot_mdb_get_pgid(struct ocelot *ocelot,
1481 const struct ocelot_multicast *mc)
1482 {
1483 struct ocelot_pgid *pgid;
1484 int index;
1485
1486 /* According to VSC7514 datasheet 3.9.1.5 IPv4 Multicast Entries and
1487 * 3.9.1.6 IPv6 Multicast Entries, "Instead of a lookup in the
1488 * destination mask table (PGID), the destination set is programmed as
1489 * part of the entry MAC address.", and the DEST_IDX is set to 0.
1490 */
1491 if (mc->entry_type == ENTRYTYPE_MACv4 ||
1492 mc->entry_type == ENTRYTYPE_MACv6)
1493 return ocelot_pgid_alloc(ocelot, 0, mc->ports);
1494
1495 list_for_each_entry(pgid, &ocelot->pgids, list) {
1496 /* When searching for a nonreserved multicast PGID, ignore the
1497 * dummy PGID of zero that we have for MACv4/MACv6 entries
1498 */
1499 if (pgid->index && pgid->ports == mc->ports) {
1500 refcount_inc(&pgid->refcount);
1501 return pgid;
1502 }
1503 }
1504
1505 /* Search for a free index in the nonreserved multicast PGID area */
1506 for_each_nonreserved_multicast_dest_pgid(ocelot, index) {
1507 bool used = false;
1508
1509 list_for_each_entry(pgid, &ocelot->pgids, list) {
1510 if (pgid->index == index) {
1511 used = true;
1512 break;
1513 }
1514 }
1515
1516 if (!used)
1517 return ocelot_pgid_alloc(ocelot, index, mc->ports);
1518 }
1519
1520 return ERR_PTR(-ENOSPC);
1521 }
1522
1523 static void ocelot_encode_ports_to_mdb(unsigned char *addr,
1524 struct ocelot_multicast *mc)
1525 {
1526 ether_addr_copy(addr, mc->addr);
1527
1528 if (mc->entry_type == ENTRYTYPE_MACv4) {
1529 addr[0] = 0;
1530 addr[1] = mc->ports >> 8;
1531 addr[2] = mc->ports & 0xff;
1532 } else if (mc->entry_type == ENTRYTYPE_MACv6) {
1533 addr[0] = mc->ports >> 8;
1534 addr[1] = mc->ports & 0xff;
1535 }
1536 }
1537
1538 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1539 const struct switchdev_obj_port_mdb *mdb)
1540 {
1541 unsigned char addr[ETH_ALEN];
1542 struct ocelot_multicast *mc;
1543 struct ocelot_pgid *pgid;
1544 u16 vid = mdb->vid;
1545
1546 if (port == ocelot->npi)
1547 port = ocelot->num_phys_ports;
1548
1549 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1550 if (!mc) {
1551 /* New entry */
1552 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL);
1553 if (!mc)
1554 return -ENOMEM;
1555
1556 mc->entry_type = ocelot_classify_mdb(mdb->addr);
1557 ether_addr_copy(mc->addr, mdb->addr);
1558 mc->vid = vid;
1559
1560 list_add_tail(&mc->list, &ocelot->multicast);
1561 } else {
1562 /* Existing entry. Clean up the current port mask from
1563 * hardware now, because we'll be modifying it.
1564 */
1565 ocelot_pgid_free(ocelot, mc->pgid);
1566 ocelot_encode_ports_to_mdb(addr, mc);
1567 ocelot_mact_forget(ocelot, addr, vid);
1568 }
1569
1570 mc->ports |= BIT(port);
1571
1572 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1573 if (IS_ERR(pgid)) {
1574 dev_err(ocelot->dev,
1575 "Cannot allocate PGID for mdb %pM vid %d\n",
1576 mc->addr, mc->vid);
1577 devm_kfree(ocelot->dev, mc);
1578 return PTR_ERR(pgid);
1579 }
1580 mc->pgid = pgid;
1581
1582 ocelot_encode_ports_to_mdb(addr, mc);
1583
1584 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1585 mc->entry_type != ENTRYTYPE_MACv6)
1586 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1587 pgid->index);
1588
1589 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1590 mc->entry_type);
1591 }
1592 EXPORT_SYMBOL(ocelot_port_mdb_add);
1593
1594 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1595 const struct switchdev_obj_port_mdb *mdb)
1596 {
1597 unsigned char addr[ETH_ALEN];
1598 struct ocelot_multicast *mc;
1599 struct ocelot_pgid *pgid;
1600 u16 vid = mdb->vid;
1601
1602 if (port == ocelot->npi)
1603 port = ocelot->num_phys_ports;
1604
1605 mc = ocelot_multicast_get(ocelot, mdb->addr, vid);
1606 if (!mc)
1607 return -ENOENT;
1608
1609 ocelot_encode_ports_to_mdb(addr, mc);
1610 ocelot_mact_forget(ocelot, addr, vid);
1611
1612 ocelot_pgid_free(ocelot, mc->pgid);
1613 mc->ports &= ~BIT(port);
1614 if (!mc->ports) {
1615 list_del(&mc->list);
1616 devm_kfree(ocelot->dev, mc);
1617 return 0;
1618 }
1619
1620 /* We have a PGID with fewer ports now */
1621 pgid = ocelot_mdb_get_pgid(ocelot, mc);
1622 if (IS_ERR(pgid))
1623 return PTR_ERR(pgid);
1624 mc->pgid = pgid;
1625
1626 ocelot_encode_ports_to_mdb(addr, mc);
1627
1628 if (mc->entry_type != ENTRYTYPE_MACv4 &&
1629 mc->entry_type != ENTRYTYPE_MACv6)
1630 ocelot_write_rix(ocelot, pgid->ports, ANA_PGID_PGID,
1631 pgid->index);
1632
1633 return ocelot_mact_learn(ocelot, pgid->index, addr, vid,
1634 mc->entry_type);
1635 }
1636 EXPORT_SYMBOL(ocelot_port_mdb_del);
1637
1638 void ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1639 struct net_device *bridge)
1640 {
1641 struct ocelot_port *ocelot_port = ocelot->ports[port];
1642
1643 ocelot_port->bridge = bridge;
1644
1645 ocelot_apply_bridge_fwd_mask(ocelot);
1646 }
1647 EXPORT_SYMBOL(ocelot_port_bridge_join);
1648
1649 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1650 struct net_device *bridge)
1651 {
1652 struct ocelot_port *ocelot_port = ocelot->ports[port];
1653 struct ocelot_vlan pvid = {0}, native_vlan = {0};
1654
1655 ocelot_port->bridge = NULL;
1656
1657 ocelot_port_set_pvid(ocelot, port, pvid);
1658 ocelot_port_set_native_vlan(ocelot, port, native_vlan);
1659 ocelot_apply_bridge_fwd_mask(ocelot);
1660 }
1661 EXPORT_SYMBOL(ocelot_port_bridge_leave);
1662
1663 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
1664 {
1665 unsigned long visited = GENMASK(ocelot->num_phys_ports - 1, 0);
1666 int i, port, lag;
1667
1668 /* Reset destination and aggregation PGIDS */
1669 for_each_unicast_dest_pgid(ocelot, port)
1670 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
1671
1672 for_each_aggr_pgid(ocelot, i)
1673 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0),
1674 ANA_PGID_PGID, i);
1675
1676 /* The visited ports bitmask holds the list of ports offloading any
1677 * bonding interface. Initially we mark all these ports as unvisited,
1678 * then every time we visit a port in this bitmask, we know that it is
1679 * the lowest numbered port, i.e. the one whose logical ID == physical
1680 * port ID == LAG ID. So we mark as visited all further ports in the
1681 * bitmask that are offloading the same bonding interface. This way,
1682 * we set up the aggregation PGIDs only once per bonding interface.
1683 */
1684 for (port = 0; port < ocelot->num_phys_ports; port++) {
1685 struct ocelot_port *ocelot_port = ocelot->ports[port];
1686
1687 if (!ocelot_port || !ocelot_port->bond)
1688 continue;
1689
1690 visited &= ~BIT(port);
1691 }
1692
1693 /* Now, set PGIDs for each active LAG */
1694 for (lag = 0; lag < ocelot->num_phys_ports; lag++) {
1695 struct net_device *bond = ocelot->ports[lag]->bond;
1696 int num_active_ports = 0;
1697 unsigned long bond_mask;
1698 u8 aggr_idx[16];
1699
1700 if (!bond || (visited & BIT(lag)))
1701 continue;
1702
1703 bond_mask = ocelot_get_bond_mask(ocelot, bond, true);
1704
1705 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) {
1706 // Destination mask
1707 ocelot_write_rix(ocelot, bond_mask,
1708 ANA_PGID_PGID, port);
1709 aggr_idx[num_active_ports++] = port;
1710 }
1711
1712 for_each_aggr_pgid(ocelot, i) {
1713 u32 ac;
1714
1715 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i);
1716 ac &= ~bond_mask;
1717 /* Don't do division by zero if there was no active
1718 * port. Just make all aggregation codes zero.
1719 */
1720 if (num_active_ports)
1721 ac |= BIT(aggr_idx[i % num_active_ports]);
1722 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i);
1723 }
1724
1725 /* Mark all ports in the same LAG as visited to avoid applying
1726 * the same config again.
1727 */
1728 for (port = lag; port < ocelot->num_phys_ports; port++) {
1729 struct ocelot_port *ocelot_port = ocelot->ports[port];
1730
1731 if (!ocelot_port)
1732 continue;
1733
1734 if (ocelot_port->bond == bond)
1735 visited |= BIT(port);
1736 }
1737 }
1738 }
1739
1740 /* When offloading a bonding interface, the switch ports configured under the
1741 * same bond must have the same logical port ID, equal to the physical port ID
1742 * of the lowest numbered physical port in that bond. Otherwise, in standalone/
1743 * bridged mode, each port has a logical port ID equal to its physical port ID.
1744 */
1745 static void ocelot_setup_logical_port_ids(struct ocelot *ocelot)
1746 {
1747 int port;
1748
1749 for (port = 0; port < ocelot->num_phys_ports; port++) {
1750 struct ocelot_port *ocelot_port = ocelot->ports[port];
1751 struct net_device *bond;
1752
1753 if (!ocelot_port)
1754 continue;
1755
1756 bond = ocelot_port->bond;
1757 if (bond) {
1758 int lag = __ffs(ocelot_get_bond_mask(ocelot, bond,
1759 false));
1760
1761 ocelot_rmw_gix(ocelot,
1762 ANA_PORT_PORT_CFG_PORTID_VAL(lag),
1763 ANA_PORT_PORT_CFG_PORTID_VAL_M,
1764 ANA_PORT_PORT_CFG, port);
1765 } else {
1766 ocelot_rmw_gix(ocelot,
1767 ANA_PORT_PORT_CFG_PORTID_VAL(port),
1768 ANA_PORT_PORT_CFG_PORTID_VAL_M,
1769 ANA_PORT_PORT_CFG, port);
1770 }
1771 }
1772 }
1773
1774 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1775 struct net_device *bond,
1776 struct netdev_lag_upper_info *info)
1777 {
1778 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
1779 return -EOPNOTSUPP;
1780
1781 ocelot->ports[port]->bond = bond;
1782
1783 ocelot_setup_logical_port_ids(ocelot);
1784 ocelot_apply_bridge_fwd_mask(ocelot);
1785 ocelot_set_aggr_pgids(ocelot);
1786
1787 return 0;
1788 }
1789 EXPORT_SYMBOL(ocelot_port_lag_join);
1790
1791 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1792 struct net_device *bond)
1793 {
1794 ocelot->ports[port]->bond = NULL;
1795
1796 ocelot_setup_logical_port_ids(ocelot);
1797 ocelot_apply_bridge_fwd_mask(ocelot);
1798 ocelot_set_aggr_pgids(ocelot);
1799 }
1800 EXPORT_SYMBOL(ocelot_port_lag_leave);
1801
1802 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active)
1803 {
1804 struct ocelot_port *ocelot_port = ocelot->ports[port];
1805
1806 ocelot_port->lag_tx_active = lag_tx_active;
1807
1808 /* Rebalance the LAGs */
1809 ocelot_set_aggr_pgids(ocelot);
1810 }
1811 EXPORT_SYMBOL(ocelot_port_lag_change);
1812
1813 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu.
1814 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG.
1815 * In the special case that it's the NPI port that we're configuring, the
1816 * length of the tag and optional prefix needs to be accounted for privately,
1817 * in order to be able to sustain communication at the requested @sdu.
1818 */
1819 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu)
1820 {
1821 struct ocelot_port *ocelot_port = ocelot->ports[port];
1822 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN;
1823 int pause_start, pause_stop;
1824 int atop, atop_tot;
1825
1826 if (port == ocelot->npi) {
1827 maxlen += OCELOT_TAG_LEN;
1828
1829 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1830 maxlen += OCELOT_SHORT_PREFIX_LEN;
1831 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1832 maxlen += OCELOT_LONG_PREFIX_LEN;
1833 }
1834
1835 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG);
1836
1837 /* Set Pause watermark hysteresis */
1838 pause_start = 6 * maxlen / OCELOT_BUFFER_CELL_SZ;
1839 pause_stop = 4 * maxlen / OCELOT_BUFFER_CELL_SZ;
1840 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_START,
1841 pause_start);
1842 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_STOP,
1843 pause_stop);
1844
1845 /* Tail dropping watermarks */
1846 atop_tot = (ocelot->packet_buffer_size - 9 * maxlen) /
1847 OCELOT_BUFFER_CELL_SZ;
1848 atop = (9 * maxlen) / OCELOT_BUFFER_CELL_SZ;
1849 ocelot_write_rix(ocelot, ocelot->ops->wm_enc(atop), SYS_ATOP, port);
1850 ocelot_write(ocelot, ocelot->ops->wm_enc(atop_tot), SYS_ATOP_TOT_CFG);
1851 }
1852 EXPORT_SYMBOL(ocelot_port_set_maxlen);
1853
1854 int ocelot_get_max_mtu(struct ocelot *ocelot, int port)
1855 {
1856 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN;
1857
1858 if (port == ocelot->npi) {
1859 max_mtu -= OCELOT_TAG_LEN;
1860
1861 if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_SHORT)
1862 max_mtu -= OCELOT_SHORT_PREFIX_LEN;
1863 else if (ocelot->npi_inj_prefix == OCELOT_TAG_PREFIX_LONG)
1864 max_mtu -= OCELOT_LONG_PREFIX_LEN;
1865 }
1866
1867 return max_mtu;
1868 }
1869 EXPORT_SYMBOL(ocelot_get_max_mtu);
1870
1871 static void ocelot_port_set_learning(struct ocelot *ocelot, int port,
1872 bool enabled)
1873 {
1874 struct ocelot_port *ocelot_port = ocelot->ports[port];
1875 u32 val = 0;
1876
1877 if (enabled)
1878 val = ANA_PORT_PORT_CFG_LEARN_ENA;
1879
1880 ocelot_rmw_gix(ocelot, val, ANA_PORT_PORT_CFG_LEARN_ENA,
1881 ANA_PORT_PORT_CFG, port);
1882
1883 ocelot_port->learn_ena = enabled;
1884 }
1885
1886 static void ocelot_port_set_ucast_flood(struct ocelot *ocelot, int port,
1887 bool enabled)
1888 {
1889 u32 val = 0;
1890
1891 if (enabled)
1892 val = BIT(port);
1893
1894 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_UC);
1895 }
1896
1897 static void ocelot_port_set_mcast_flood(struct ocelot *ocelot, int port,
1898 bool enabled)
1899 {
1900 u32 val = 0;
1901
1902 if (enabled)
1903 val = BIT(port);
1904
1905 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_MC);
1906 }
1907
1908 static void ocelot_port_set_bcast_flood(struct ocelot *ocelot, int port,
1909 bool enabled)
1910 {
1911 u32 val = 0;
1912
1913 if (enabled)
1914 val = BIT(port);
1915
1916 ocelot_rmw_rix(ocelot, val, BIT(port), ANA_PGID_PGID, PGID_BC);
1917 }
1918
1919 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
1920 struct switchdev_brport_flags flags)
1921 {
1922 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
1923 BR_BCAST_FLOOD))
1924 return -EINVAL;
1925
1926 return 0;
1927 }
1928 EXPORT_SYMBOL(ocelot_port_pre_bridge_flags);
1929
1930 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
1931 struct switchdev_brport_flags flags)
1932 {
1933 if (flags.mask & BR_LEARNING)
1934 ocelot_port_set_learning(ocelot, port,
1935 !!(flags.val & BR_LEARNING));
1936
1937 if (flags.mask & BR_FLOOD)
1938 ocelot_port_set_ucast_flood(ocelot, port,
1939 !!(flags.val & BR_FLOOD));
1940
1941 if (flags.mask & BR_MCAST_FLOOD)
1942 ocelot_port_set_mcast_flood(ocelot, port,
1943 !!(flags.val & BR_MCAST_FLOOD));
1944
1945 if (flags.mask & BR_BCAST_FLOOD)
1946 ocelot_port_set_bcast_flood(ocelot, port,
1947 !!(flags.val & BR_BCAST_FLOOD));
1948 }
1949 EXPORT_SYMBOL(ocelot_port_bridge_flags);
1950
1951 void ocelot_init_port(struct ocelot *ocelot, int port)
1952 {
1953 struct ocelot_port *ocelot_port = ocelot->ports[port];
1954
1955 skb_queue_head_init(&ocelot_port->tx_skbs);
1956 spin_lock_init(&ocelot_port->ts_id_lock);
1957
1958 /* Basic L2 initialization */
1959
1960 /* Set MAC IFG Gaps
1961 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0
1962 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5
1963 */
1964 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5),
1965 DEV_MAC_IFG_CFG);
1966
1967 /* Load seed (0) and set MAC HDX late collision */
1968 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) |
1969 DEV_MAC_HDX_CFG_SEED_LOAD,
1970 DEV_MAC_HDX_CFG);
1971 mdelay(1);
1972 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
1973 DEV_MAC_HDX_CFG);
1974
1975 /* Set Max Length and maximum tags allowed */
1976 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN);
1977 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) |
1978 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA |
1979 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA |
1980 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA,
1981 DEV_MAC_TAGS_CFG);
1982
1983 /* Set SMAC of Pause frame (00:00:00:00:00:00) */
1984 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG);
1985 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG);
1986
1987 /* Enable transmission of pause frames */
1988 ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 1);
1989
1990 /* Drop frames with multicast source address */
1991 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1992 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA,
1993 ANA_PORT_DROP_CFG, port);
1994
1995 /* Set default VLAN and tag type to 8021Q. */
1996 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q),
1997 REW_PORT_VLAN_CFG_PORT_TPID_M,
1998 REW_PORT_VLAN_CFG, port);
1999
2000 /* Disable source address learning for standalone mode */
2001 ocelot_port_set_learning(ocelot, port, false);
2002
2003 /* Set the port's initial logical port ID value, enable receiving
2004 * frames on it, and configure the MAC address learning type to
2005 * automatic.
2006 */
2007 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
2008 ANA_PORT_PORT_CFG_RECV_ENA |
2009 ANA_PORT_PORT_CFG_PORTID_VAL(port),
2010 ANA_PORT_PORT_CFG, port);
2011
2012 /* Enable vcap lookups */
2013 ocelot_vcap_enable(ocelot, port);
2014 }
2015 EXPORT_SYMBOL(ocelot_init_port);
2016
2017 /* Configure and enable the CPU port module, which is a set of queues
2018 * accessible through register MMIO, frame DMA or Ethernet (in case
2019 * NPI mode is used).
2020 */
2021 static void ocelot_cpu_port_init(struct ocelot *ocelot)
2022 {
2023 int cpu = ocelot->num_phys_ports;
2024
2025 /* The unicast destination PGID for the CPU port module is unused */
2026 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu);
2027 /* Instead set up a multicast destination PGID for traffic copied to
2028 * the CPU. Whitelisted MAC addresses like the port netdevice MAC
2029 * addresses will be copied to the CPU via this PGID.
2030 */
2031 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU);
2032 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA |
2033 ANA_PORT_PORT_CFG_PORTID_VAL(cpu),
2034 ANA_PORT_PORT_CFG, cpu);
2035
2036 /* Enable CPU port module */
2037 ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
2038 /* CPU port Injection/Extraction configuration */
2039 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,
2040 OCELOT_TAG_PREFIX_NONE);
2041 ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,
2042 OCELOT_TAG_PREFIX_NONE);
2043
2044 /* Configure the CPU port to be VLAN aware */
2045 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |
2046 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA |
2047 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1),
2048 ANA_PORT_VLAN_CFG, cpu);
2049 }
2050
2051 static void ocelot_detect_features(struct ocelot *ocelot)
2052 {
2053 int mmgt, eq_ctrl;
2054
2055 /* For Ocelot, Felix, Seville, Serval etc, SYS:MMGT:MMGT:FREECNT holds
2056 * the number of 240-byte free memory words (aka 4-cell chunks) and not
2057 * 192 bytes as the documentation incorrectly says.
2058 */
2059 mmgt = ocelot_read(ocelot, SYS_MMGT);
2060 ocelot->packet_buffer_size = 240 * SYS_MMGT_FREECNT(mmgt);
2061
2062 eq_ctrl = ocelot_read(ocelot, QSYS_EQ_CTRL);
2063 ocelot->num_frame_refs = QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(eq_ctrl);
2064 }
2065
2066 int ocelot_init(struct ocelot *ocelot)
2067 {
2068 char queue_name[32];
2069 int i, ret;
2070 u32 port;
2071
2072 if (ocelot->ops->reset) {
2073 ret = ocelot->ops->reset(ocelot);
2074 if (ret) {
2075 dev_err(ocelot->dev, "Switch reset failed\n");
2076 return ret;
2077 }
2078 }
2079
2080 ocelot->stats = devm_kcalloc(ocelot->dev,
2081 ocelot->num_phys_ports * ocelot->num_stats,
2082 sizeof(u64), GFP_KERNEL);
2083 if (!ocelot->stats)
2084 return -ENOMEM;
2085
2086 mutex_init(&ocelot->stats_lock);
2087 mutex_init(&ocelot->ptp_lock);
2088 spin_lock_init(&ocelot->ptp_clock_lock);
2089 snprintf(queue_name, sizeof(queue_name), "%s-stats",
2090 dev_name(ocelot->dev));
2091 ocelot->stats_queue = create_singlethread_workqueue(queue_name);
2092 if (!ocelot->stats_queue)
2093 return -ENOMEM;
2094
2095 ocelot->owq = alloc_ordered_workqueue("ocelot-owq", 0);
2096 if (!ocelot->owq) {
2097 destroy_workqueue(ocelot->stats_queue);
2098 return -ENOMEM;
2099 }
2100
2101 INIT_LIST_HEAD(&ocelot->multicast);
2102 INIT_LIST_HEAD(&ocelot->pgids);
2103 ocelot_detect_features(ocelot);
2104 ocelot_mact_init(ocelot);
2105 ocelot_vlan_init(ocelot);
2106 ocelot_vcap_init(ocelot);
2107 ocelot_cpu_port_init(ocelot);
2108
2109 for (port = 0; port < ocelot->num_phys_ports; port++) {
2110 /* Clear all counters (5 groups) */
2111 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) |
2112 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f),
2113 SYS_STAT_CFG);
2114 }
2115
2116 /* Only use S-Tag */
2117 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG);
2118
2119 /* Aggregation mode */
2120 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA |
2121 ANA_AGGR_CFG_AC_DMAC_ENA |
2122 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA |
2123 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA |
2124 ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA |
2125 ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA,
2126 ANA_AGGR_CFG);
2127
2128 /* Set MAC age time to default value. The entry is aged after
2129 * 2*AGE_PERIOD
2130 */
2131 ocelot_write(ocelot,
2132 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ),
2133 ANA_AUTOAGE);
2134
2135 /* Disable learning for frames discarded by VLAN ingress filtering */
2136 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1);
2137
2138 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */
2139 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA |
2140 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING);
2141
2142 /* Setup flooding PGIDs */
2143 for (i = 0; i < ocelot->num_flooding_pgids; i++)
2144 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) |
2145 ANA_FLOODING_FLD_BROADCAST(PGID_BC) |
2146 ANA_FLOODING_FLD_UNICAST(PGID_UC),
2147 ANA_FLOODING, i);
2148 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) |
2149 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) |
2150 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) |
2151 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC),
2152 ANA_FLOODING_IPMC);
2153
2154 for (port = 0; port < ocelot->num_phys_ports; port++) {
2155 /* Transmit the frame to the local port. */
2156 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port);
2157 /* Do not forward BPDU frames to the front ports. */
2158 ocelot_write_gix(ocelot,
2159 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff),
2160 ANA_PORT_CPU_FWD_BPDU_CFG,
2161 port);
2162 /* Ensure bridging is disabled */
2163 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port);
2164 }
2165
2166 for_each_nonreserved_multicast_dest_pgid(ocelot, i) {
2167 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0));
2168
2169 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i);
2170 }
2171
2172 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_BLACKHOLE);
2173
2174 /* Allow broadcast and unknown L2 multicast to the CPU. */
2175 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2176 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2177 ANA_PGID_PGID, PGID_MC);
2178 ocelot_rmw_rix(ocelot, ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2179 ANA_PGID_PGID_PGID(BIT(ocelot->num_phys_ports)),
2180 ANA_PGID_PGID, PGID_BC);
2181 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4);
2182 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6);
2183
2184 /* Allow manual injection via DEVCPU_QS registers, and byte swap these
2185 * registers endianness.
2186 */
2187 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP |
2188 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0);
2189 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP |
2190 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0);
2191 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) |
2192 ANA_CPUQ_CFG_CPUQ_LRN(2) |
2193 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) |
2194 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) |
2195 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) |
2196 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) |
2197 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) |
2198 ANA_CPUQ_CFG_CPUQ_IGMP(6) |
2199 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG);
2200 for (i = 0; i < 16; i++)
2201 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) |
2202 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6),
2203 ANA_CPUQ_8021_CFG, i);
2204
2205 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work);
2206 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work,
2207 OCELOT_STATS_CHECK_DELAY);
2208
2209 return 0;
2210 }
2211 EXPORT_SYMBOL(ocelot_init);
2212
2213 void ocelot_deinit(struct ocelot *ocelot)
2214 {
2215 cancel_delayed_work(&ocelot->stats_work);
2216 destroy_workqueue(ocelot->stats_queue);
2217 destroy_workqueue(ocelot->owq);
2218 mutex_destroy(&ocelot->stats_lock);
2219 }
2220 EXPORT_SYMBOL(ocelot_deinit);
2221
2222 void ocelot_deinit_port(struct ocelot *ocelot, int port)
2223 {
2224 struct ocelot_port *ocelot_port = ocelot->ports[port];
2225
2226 skb_queue_purge(&ocelot_port->tx_skbs);
2227 }
2228 EXPORT_SYMBOL(ocelot_deinit_port);
2229
2230 MODULE_LICENSE("Dual MIT/GPL");
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