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Merge tag 'pm-4.10-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / renesas / sh_eth.c
1 /* SuperH Ethernet device driver
2 *
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
32 #include <linux/of.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
38 #include <linux/io.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
46
47 #include "sh_eth.h"
48
49 #define SH_ETH_DEF_MSG_ENABLE \
50 (NETIF_MSG_LINK | \
51 NETIF_MSG_TIMER | \
52 NETIF_MSG_RX_ERR| \
53 NETIF_MSG_TX_ERR)
54
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
56
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
59
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
62
63 [EDSR] = 0x0000,
64 [EDMR] = 0x0400,
65 [EDTRR] = 0x0408,
66 [EDRRR] = 0x0410,
67 [EESR] = 0x0428,
68 [EESIPR] = 0x0430,
69 [TDLAR] = 0x0010,
70 [TDFAR] = 0x0014,
71 [TDFXR] = 0x0018,
72 [TDFFR] = 0x001c,
73 [RDLAR] = 0x0030,
74 [RDFAR] = 0x0034,
75 [RDFXR] = 0x0038,
76 [RDFFR] = 0x003c,
77 [TRSCER] = 0x0438,
78 [RMFCR] = 0x0440,
79 [TFTR] = 0x0448,
80 [FDR] = 0x0450,
81 [RMCR] = 0x0458,
82 [RPADIR] = 0x0460,
83 [FCFTR] = 0x0468,
84 [CSMR] = 0x04E4,
85
86 [ECMR] = 0x0500,
87 [ECSR] = 0x0510,
88 [ECSIPR] = 0x0518,
89 [PIR] = 0x0520,
90 [PSR] = 0x0528,
91 [PIPR] = 0x052c,
92 [RFLR] = 0x0508,
93 [APR] = 0x0554,
94 [MPR] = 0x0558,
95 [PFTCR] = 0x055c,
96 [PFRCR] = 0x0560,
97 [TPAUSER] = 0x0564,
98 [GECMR] = 0x05b0,
99 [BCULR] = 0x05b4,
100 [MAHR] = 0x05c0,
101 [MALR] = 0x05c8,
102 [TROCR] = 0x0700,
103 [CDCR] = 0x0708,
104 [LCCR] = 0x0710,
105 [CEFCR] = 0x0740,
106 [FRECR] = 0x0748,
107 [TSFRCR] = 0x0750,
108 [TLFRCR] = 0x0758,
109 [RFCR] = 0x0760,
110 [CERCR] = 0x0768,
111 [CEECR] = 0x0770,
112 [MAFCR] = 0x0778,
113 [RMII_MII] = 0x0790,
114
115 [ARSTR] = 0x0000,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
119 [TSU_FCM] = 0x0018,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
129 [TSU_FWSR] = 0x0050,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
136 [TSU_TEN] = 0x0064,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
142
143 [TXNLCR0] = 0x0080,
144 [TXALCR0] = 0x0084,
145 [RXNLCR0] = 0x0088,
146 [RXALCR0] = 0x008c,
147 [FWNLCR0] = 0x0090,
148 [FWALCR0] = 0x0094,
149 [TXNLCR1] = 0x00a0,
150 [TXALCR1] = 0x00a0,
151 [RXNLCR1] = 0x00a8,
152 [RXALCR1] = 0x00ac,
153 [FWNLCR1] = 0x00b0,
154 [FWALCR1] = 0x00b4,
155 };
156
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
159
160 [EDSR] = 0x0000,
161 [EDMR] = 0x0400,
162 [EDTRR] = 0x0408,
163 [EDRRR] = 0x0410,
164 [EESR] = 0x0428,
165 [EESIPR] = 0x0430,
166 [TDLAR] = 0x0010,
167 [TDFAR] = 0x0014,
168 [TDFXR] = 0x0018,
169 [TDFFR] = 0x001c,
170 [RDLAR] = 0x0030,
171 [RDFAR] = 0x0034,
172 [RDFXR] = 0x0038,
173 [RDFFR] = 0x003c,
174 [TRSCER] = 0x0438,
175 [RMFCR] = 0x0440,
176 [TFTR] = 0x0448,
177 [FDR] = 0x0450,
178 [RMCR] = 0x0458,
179 [RPADIR] = 0x0460,
180 [FCFTR] = 0x0468,
181 [CSMR] = 0x04E4,
182
183 [ECMR] = 0x0500,
184 [RFLR] = 0x0508,
185 [ECSR] = 0x0510,
186 [ECSIPR] = 0x0518,
187 [PIR] = 0x0520,
188 [APR] = 0x0554,
189 [MPR] = 0x0558,
190 [PFTCR] = 0x055c,
191 [PFRCR] = 0x0560,
192 [TPAUSER] = 0x0564,
193 [MAHR] = 0x05c0,
194 [MALR] = 0x05c8,
195 [CEFCR] = 0x0740,
196 [FRECR] = 0x0748,
197 [TSFRCR] = 0x0750,
198 [TLFRCR] = 0x0758,
199 [RFCR] = 0x0760,
200 [MAFCR] = 0x0778,
201
202 [ARSTR] = 0x0000,
203 [TSU_CTRST] = 0x0004,
204 [TSU_FWSLC] = 0x0038,
205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
207 [TSU_TEN] = 0x0064,
208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
212 [TSU_ADRH0] = 0x0100,
213
214 [TXNLCR0] = 0x0080,
215 [TXALCR0] = 0x0084,
216 [RXNLCR0] = 0x0088,
217 [RXALCR0] = 0x008C,
218 };
219
220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
221 SH_ETH_OFFSET_DEFAULTS,
222
223 [ECMR] = 0x0300,
224 [RFLR] = 0x0308,
225 [ECSR] = 0x0310,
226 [ECSIPR] = 0x0318,
227 [PIR] = 0x0320,
228 [PSR] = 0x0328,
229 [RDMLR] = 0x0340,
230 [IPGR] = 0x0350,
231 [APR] = 0x0354,
232 [MPR] = 0x0358,
233 [RFCF] = 0x0360,
234 [TPAUSER] = 0x0364,
235 [TPAUSECR] = 0x0368,
236 [MAHR] = 0x03c0,
237 [MALR] = 0x03c8,
238 [TROCR] = 0x03d0,
239 [CDCR] = 0x03d4,
240 [LCCR] = 0x03d8,
241 [CNDCR] = 0x03dc,
242 [CEFCR] = 0x03e4,
243 [FRECR] = 0x03e8,
244 [TSFRCR] = 0x03ec,
245 [TLFRCR] = 0x03f0,
246 [RFCR] = 0x03f4,
247 [MAFCR] = 0x03f8,
248
249 [EDMR] = 0x0200,
250 [EDTRR] = 0x0208,
251 [EDRRR] = 0x0210,
252 [TDLAR] = 0x0218,
253 [RDLAR] = 0x0220,
254 [EESR] = 0x0228,
255 [EESIPR] = 0x0230,
256 [TRSCER] = 0x0238,
257 [RMFCR] = 0x0240,
258 [TFTR] = 0x0248,
259 [FDR] = 0x0250,
260 [RMCR] = 0x0258,
261 [TFUCR] = 0x0264,
262 [RFOCR] = 0x0268,
263 [RMIIMODE] = 0x026c,
264 [FCFTR] = 0x0270,
265 [TRIMD] = 0x027c,
266 };
267
268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
269 SH_ETH_OFFSET_DEFAULTS,
270
271 [ECMR] = 0x0100,
272 [RFLR] = 0x0108,
273 [ECSR] = 0x0110,
274 [ECSIPR] = 0x0118,
275 [PIR] = 0x0120,
276 [PSR] = 0x0128,
277 [RDMLR] = 0x0140,
278 [IPGR] = 0x0150,
279 [APR] = 0x0154,
280 [MPR] = 0x0158,
281 [TPAUSER] = 0x0164,
282 [RFCF] = 0x0160,
283 [TPAUSECR] = 0x0168,
284 [BCFRR] = 0x016c,
285 [MAHR] = 0x01c0,
286 [MALR] = 0x01c8,
287 [TROCR] = 0x01d0,
288 [CDCR] = 0x01d4,
289 [LCCR] = 0x01d8,
290 [CNDCR] = 0x01dc,
291 [CEFCR] = 0x01e4,
292 [FRECR] = 0x01e8,
293 [TSFRCR] = 0x01ec,
294 [TLFRCR] = 0x01f0,
295 [RFCR] = 0x01f4,
296 [MAFCR] = 0x01f8,
297 [RTRATE] = 0x01fc,
298
299 [EDMR] = 0x0000,
300 [EDTRR] = 0x0008,
301 [EDRRR] = 0x0010,
302 [TDLAR] = 0x0018,
303 [RDLAR] = 0x0020,
304 [EESR] = 0x0028,
305 [EESIPR] = 0x0030,
306 [TRSCER] = 0x0038,
307 [RMFCR] = 0x0040,
308 [TFTR] = 0x0048,
309 [FDR] = 0x0050,
310 [RMCR] = 0x0058,
311 [TFUCR] = 0x0064,
312 [RFOCR] = 0x0068,
313 [FCFTR] = 0x0070,
314 [RPADIR] = 0x0078,
315 [TRIMD] = 0x007c,
316 [RBWAR] = 0x00c8,
317 [RDFAR] = 0x00cc,
318 [TBRAR] = 0x00d4,
319 [TDFAR] = 0x00d8,
320 };
321
322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
323 SH_ETH_OFFSET_DEFAULTS,
324
325 [EDMR] = 0x0000,
326 [EDTRR] = 0x0004,
327 [EDRRR] = 0x0008,
328 [TDLAR] = 0x000c,
329 [RDLAR] = 0x0010,
330 [EESR] = 0x0014,
331 [EESIPR] = 0x0018,
332 [TRSCER] = 0x001c,
333 [RMFCR] = 0x0020,
334 [TFTR] = 0x0024,
335 [FDR] = 0x0028,
336 [RMCR] = 0x002c,
337 [EDOCR] = 0x0030,
338 [FCFTR] = 0x0034,
339 [RPADIR] = 0x0038,
340 [TRIMD] = 0x003c,
341 [RBWAR] = 0x0040,
342 [RDFAR] = 0x0044,
343 [TBRAR] = 0x004c,
344 [TDFAR] = 0x0050,
345
346 [ECMR] = 0x0160,
347 [ECSR] = 0x0164,
348 [ECSIPR] = 0x0168,
349 [PIR] = 0x016c,
350 [MAHR] = 0x0170,
351 [MALR] = 0x0174,
352 [RFLR] = 0x0178,
353 [PSR] = 0x017c,
354 [TROCR] = 0x0180,
355 [CDCR] = 0x0184,
356 [LCCR] = 0x0188,
357 [CNDCR] = 0x018c,
358 [CEFCR] = 0x0194,
359 [FRECR] = 0x0198,
360 [TSFRCR] = 0x019c,
361 [TLFRCR] = 0x01a0,
362 [RFCR] = 0x01a4,
363 [MAFCR] = 0x01a8,
364 [IPGR] = 0x01b4,
365 [APR] = 0x01b8,
366 [MPR] = 0x01bc,
367 [TPAUSER] = 0x01c4,
368 [BCFR] = 0x01cc,
369
370 [ARSTR] = 0x0000,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
374 [TSU_FCM] = 0x0018,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
386 [TSU_FWSR] = 0x0050,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
389 [TSU_TEN] = 0x0064,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
394
395 [TXNLCR0] = 0x0080,
396 [TXALCR0] = 0x0084,
397 [RXNLCR0] = 0x0088,
398 [RXALCR0] = 0x008c,
399 [FWNLCR0] = 0x0090,
400 [FWALCR0] = 0x0094,
401 [TXNLCR1] = 0x00a0,
402 [TXALCR1] = 0x00a0,
403 [RXNLCR1] = 0x00a8,
404 [RXALCR1] = 0x00ac,
405 [FWNLCR1] = 0x00b0,
406 [FWALCR1] = 0x00b4,
407
408 [TSU_ADRH0] = 0x0100,
409 };
410
411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
413
414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
415 {
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
418
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
420 return;
421
422 iowrite32(data, mdp->addr + offset);
423 }
424
425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
426 {
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
429
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
431 return ~0U;
432
433 return ioread32(mdp->addr + offset);
434 }
435
436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
437 u32 set)
438 {
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
440 enum_index);
441 }
442
443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
444 {
445 return mdp->reg_offset == sh_eth_offset_gigabit;
446 }
447
448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
449 {
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
451 }
452
453 static void sh_eth_select_mii(struct net_device *ndev)
454 {
455 struct sh_eth_private *mdp = netdev_priv(ndev);
456 u32 value;
457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476 }
477
478 static void sh_eth_set_duplex(struct net_device *ndev)
479 {
480 struct sh_eth_private *mdp = netdev_priv(ndev);
481
482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
483 }
484
485 static void sh_eth_chip_reset(struct net_device *ndev)
486 {
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
491 mdelay(1);
492 }
493
494 static void sh_eth_set_rate_gether(struct net_device *ndev)
495 {
496 struct sh_eth_private *mdp = netdev_priv(ndev);
497
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
501 break;
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
504 break;
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
507 break;
508 }
509 }
510
511 #ifdef CONFIG_OF
512 /* R7S72100 */
513 static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
516
517 .register_type = SH_ETH_REG_FAST_RZ,
518
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
521 .eesipr_value = 0xe77f009f,
522
523 .tx_check = EESR_TC1 | EESR_FTC,
524 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
525 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
526 EESR_TDE | EESR_ECI,
527 .fdr_value = 0x0000070f,
528
529 .no_psr = 1,
530 .apr = 1,
531 .mpr = 1,
532 .tpauser = 1,
533 .hw_swap = 1,
534 .rpadir = 1,
535 .rpadir_value = 2 << 16,
536 .no_trimd = 1,
537 .no_ade = 1,
538 .hw_crc = 1,
539 .tsu = 1,
540 .shift_rd0 = 1,
541 };
542
543 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
544 {
545 sh_eth_chip_reset(ndev);
546
547 sh_eth_select_mii(ndev);
548 }
549
550 /* R8A7740 */
551 static struct sh_eth_cpu_data r8a7740_data = {
552 .chip_reset = sh_eth_chip_reset_r8a7740,
553 .set_duplex = sh_eth_set_duplex,
554 .set_rate = sh_eth_set_rate_gether,
555
556 .register_type = SH_ETH_REG_GIGABIT,
557
558 .ecsr_value = ECSR_ICD | ECSR_MPD,
559 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
560 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
561
562 .tx_check = EESR_TC1 | EESR_FTC,
563 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
564 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
565 EESR_TDE | EESR_ECI,
566 .fdr_value = 0x0000070f,
567
568 .apr = 1,
569 .mpr = 1,
570 .tpauser = 1,
571 .bculr = 1,
572 .hw_swap = 1,
573 .rpadir = 1,
574 .rpadir_value = 2 << 16,
575 .no_trimd = 1,
576 .no_ade = 1,
577 .tsu = 1,
578 .select_mii = 1,
579 .shift_rd0 = 1,
580 };
581
582 /* There is CPU dependent code */
583 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
584 {
585 struct sh_eth_private *mdp = netdev_priv(ndev);
586
587 switch (mdp->speed) {
588 case 10: /* 10BASE */
589 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
590 break;
591 case 100:/* 100BASE */
592 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
593 break;
594 }
595 }
596
597 /* R8A7778/9 */
598 static struct sh_eth_cpu_data r8a777x_data = {
599 .set_duplex = sh_eth_set_duplex,
600 .set_rate = sh_eth_set_rate_r8a777x,
601
602 .register_type = SH_ETH_REG_FAST_RCAR,
603
604 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
605 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
606 .eesipr_value = 0x01ff009f,
607
608 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
609 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
610 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
611 EESR_ECI,
612 .fdr_value = 0x00000f0f,
613
614 .apr = 1,
615 .mpr = 1,
616 .tpauser = 1,
617 .hw_swap = 1,
618 };
619
620 /* R8A7790/1 */
621 static struct sh_eth_cpu_data r8a779x_data = {
622 .set_duplex = sh_eth_set_duplex,
623 .set_rate = sh_eth_set_rate_r8a777x,
624
625 .register_type = SH_ETH_REG_FAST_RCAR,
626
627 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
628 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
629 .eesipr_value = 0x01ff009f,
630
631 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
632 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
633 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
634 EESR_ECI,
635 .fdr_value = 0x00000f0f,
636
637 .trscer_err_mask = DESC_I_RINT8,
638
639 .apr = 1,
640 .mpr = 1,
641 .tpauser = 1,
642 .hw_swap = 1,
643 .rmiimode = 1,
644 };
645 #endif /* CONFIG_OF */
646
647 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
648 {
649 struct sh_eth_private *mdp = netdev_priv(ndev);
650
651 switch (mdp->speed) {
652 case 10: /* 10BASE */
653 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
654 break;
655 case 100:/* 100BASE */
656 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
657 break;
658 }
659 }
660
661 /* SH7724 */
662 static struct sh_eth_cpu_data sh7724_data = {
663 .set_duplex = sh_eth_set_duplex,
664 .set_rate = sh_eth_set_rate_sh7724,
665
666 .register_type = SH_ETH_REG_FAST_SH4,
667
668 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
669 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
670 .eesipr_value = 0x01ff009f,
671
672 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
673 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
674 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
675 EESR_ECI,
676
677 .apr = 1,
678 .mpr = 1,
679 .tpauser = 1,
680 .hw_swap = 1,
681 .rpadir = 1,
682 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
683 };
684
685 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
686 {
687 struct sh_eth_private *mdp = netdev_priv(ndev);
688
689 switch (mdp->speed) {
690 case 10: /* 10BASE */
691 sh_eth_write(ndev, 0, RTRATE);
692 break;
693 case 100:/* 100BASE */
694 sh_eth_write(ndev, 1, RTRATE);
695 break;
696 }
697 }
698
699 /* SH7757 */
700 static struct sh_eth_cpu_data sh7757_data = {
701 .set_duplex = sh_eth_set_duplex,
702 .set_rate = sh_eth_set_rate_sh7757,
703
704 .register_type = SH_ETH_REG_FAST_SH4,
705
706 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
707
708 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
709 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
710 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
711 EESR_ECI,
712
713 .irq_flags = IRQF_SHARED,
714 .apr = 1,
715 .mpr = 1,
716 .tpauser = 1,
717 .hw_swap = 1,
718 .no_ade = 1,
719 .rpadir = 1,
720 .rpadir_value = 2 << 16,
721 .rtrate = 1,
722 };
723
724 #define SH_GIGA_ETH_BASE 0xfee00000UL
725 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
726 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
727 static void sh_eth_chip_reset_giga(struct net_device *ndev)
728 {
729 u32 mahr[2], malr[2];
730 int i;
731
732 /* save MAHR and MALR */
733 for (i = 0; i < 2; i++) {
734 malr[i] = ioread32((void *)GIGA_MALR(i));
735 mahr[i] = ioread32((void *)GIGA_MAHR(i));
736 }
737
738 sh_eth_chip_reset(ndev);
739
740 /* restore MAHR and MALR */
741 for (i = 0; i < 2; i++) {
742 iowrite32(malr[i], (void *)GIGA_MALR(i));
743 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
744 }
745 }
746
747 static void sh_eth_set_rate_giga(struct net_device *ndev)
748 {
749 struct sh_eth_private *mdp = netdev_priv(ndev);
750
751 switch (mdp->speed) {
752 case 10: /* 10BASE */
753 sh_eth_write(ndev, 0x00000000, GECMR);
754 break;
755 case 100:/* 100BASE */
756 sh_eth_write(ndev, 0x00000010, GECMR);
757 break;
758 case 1000: /* 1000BASE */
759 sh_eth_write(ndev, 0x00000020, GECMR);
760 break;
761 }
762 }
763
764 /* SH7757(GETHERC) */
765 static struct sh_eth_cpu_data sh7757_data_giga = {
766 .chip_reset = sh_eth_chip_reset_giga,
767 .set_duplex = sh_eth_set_duplex,
768 .set_rate = sh_eth_set_rate_giga,
769
770 .register_type = SH_ETH_REG_GIGABIT,
771
772 .ecsr_value = ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
774 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
775
776 .tx_check = EESR_TC1 | EESR_FTC,
777 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
778 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
779 EESR_TDE | EESR_ECI,
780 .fdr_value = 0x0000072f,
781
782 .irq_flags = IRQF_SHARED,
783 .apr = 1,
784 .mpr = 1,
785 .tpauser = 1,
786 .bculr = 1,
787 .hw_swap = 1,
788 .rpadir = 1,
789 .rpadir_value = 2 << 16,
790 .no_trimd = 1,
791 .no_ade = 1,
792 .tsu = 1,
793 };
794
795 /* SH7734 */
796 static struct sh_eth_cpu_data sh7734_data = {
797 .chip_reset = sh_eth_chip_reset,
798 .set_duplex = sh_eth_set_duplex,
799 .set_rate = sh_eth_set_rate_gether,
800
801 .register_type = SH_ETH_REG_GIGABIT,
802
803 .ecsr_value = ECSR_ICD | ECSR_MPD,
804 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
805 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
806
807 .tx_check = EESR_TC1 | EESR_FTC,
808 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
809 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
810 EESR_TDE | EESR_ECI,
811
812 .apr = 1,
813 .mpr = 1,
814 .tpauser = 1,
815 .bculr = 1,
816 .hw_swap = 1,
817 .no_trimd = 1,
818 .no_ade = 1,
819 .tsu = 1,
820 .hw_crc = 1,
821 .select_mii = 1,
822 .shift_rd0 = 1,
823 };
824
825 /* SH7763 */
826 static struct sh_eth_cpu_data sh7763_data = {
827 .chip_reset = sh_eth_chip_reset,
828 .set_duplex = sh_eth_set_duplex,
829 .set_rate = sh_eth_set_rate_gether,
830
831 .register_type = SH_ETH_REG_GIGABIT,
832
833 .ecsr_value = ECSR_ICD | ECSR_MPD,
834 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
835 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
836
837 .tx_check = EESR_TC1 | EESR_FTC,
838 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
839 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
840 EESR_ECI,
841
842 .apr = 1,
843 .mpr = 1,
844 .tpauser = 1,
845 .bculr = 1,
846 .hw_swap = 1,
847 .no_trimd = 1,
848 .no_ade = 1,
849 .tsu = 1,
850 .irq_flags = IRQF_SHARED,
851 };
852
853 static struct sh_eth_cpu_data sh7619_data = {
854 .register_type = SH_ETH_REG_FAST_SH3_SH2,
855
856 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
857
858 .apr = 1,
859 .mpr = 1,
860 .tpauser = 1,
861 .hw_swap = 1,
862 };
863
864 static struct sh_eth_cpu_data sh771x_data = {
865 .register_type = SH_ETH_REG_FAST_SH3_SH2,
866
867 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
868 .tsu = 1,
869 };
870
871 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
872 {
873 if (!cd->ecsr_value)
874 cd->ecsr_value = DEFAULT_ECSR_INIT;
875
876 if (!cd->ecsipr_value)
877 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
878
879 if (!cd->fcftr_value)
880 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
881 DEFAULT_FIFO_F_D_RFD;
882
883 if (!cd->fdr_value)
884 cd->fdr_value = DEFAULT_FDR_INIT;
885
886 if (!cd->tx_check)
887 cd->tx_check = DEFAULT_TX_CHECK;
888
889 if (!cd->eesr_err_check)
890 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
891
892 if (!cd->trscer_err_mask)
893 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
894 }
895
896 static int sh_eth_check_reset(struct net_device *ndev)
897 {
898 int ret = 0;
899 int cnt = 100;
900
901 while (cnt > 0) {
902 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
903 break;
904 mdelay(1);
905 cnt--;
906 }
907 if (cnt <= 0) {
908 netdev_err(ndev, "Device reset failed\n");
909 ret = -ETIMEDOUT;
910 }
911 return ret;
912 }
913
914 static int sh_eth_reset(struct net_device *ndev)
915 {
916 struct sh_eth_private *mdp = netdev_priv(ndev);
917 int ret = 0;
918
919 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
920 sh_eth_write(ndev, EDSR_ENALL, EDSR);
921 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
922
923 ret = sh_eth_check_reset(ndev);
924 if (ret)
925 return ret;
926
927 /* Table Init */
928 sh_eth_write(ndev, 0x0, TDLAR);
929 sh_eth_write(ndev, 0x0, TDFAR);
930 sh_eth_write(ndev, 0x0, TDFXR);
931 sh_eth_write(ndev, 0x0, TDFFR);
932 sh_eth_write(ndev, 0x0, RDLAR);
933 sh_eth_write(ndev, 0x0, RDFAR);
934 sh_eth_write(ndev, 0x0, RDFXR);
935 sh_eth_write(ndev, 0x0, RDFFR);
936
937 /* Reset HW CRC register */
938 if (mdp->cd->hw_crc)
939 sh_eth_write(ndev, 0x0, CSMR);
940
941 /* Select MII mode */
942 if (mdp->cd->select_mii)
943 sh_eth_select_mii(ndev);
944 } else {
945 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
946 mdelay(3);
947 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
948 }
949
950 return ret;
951 }
952
953 static void sh_eth_set_receive_align(struct sk_buff *skb)
954 {
955 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
956
957 if (reserve)
958 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
959 }
960
961 /* Program the hardware MAC address from dev->dev_addr. */
962 static void update_mac_address(struct net_device *ndev)
963 {
964 sh_eth_write(ndev,
965 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
966 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
967 sh_eth_write(ndev,
968 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
969 }
970
971 /* Get MAC address from SuperH MAC address register
972 *
973 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
974 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
975 * When you want use this device, you must set MAC address in bootloader.
976 *
977 */
978 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
979 {
980 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
981 memcpy(ndev->dev_addr, mac, ETH_ALEN);
982 } else {
983 u32 mahr = sh_eth_read(ndev, MAHR);
984 u32 malr = sh_eth_read(ndev, MALR);
985
986 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
987 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
988 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
989 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
990 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
991 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
992 }
993 }
994
995 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
996 {
997 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
998 return EDTRR_TRNS_GETHER;
999 else
1000 return EDTRR_TRNS_ETHER;
1001 }
1002
1003 struct bb_info {
1004 void (*set_gate)(void *addr);
1005 struct mdiobb_ctrl ctrl;
1006 void *addr;
1007 };
1008
1009 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1010 {
1011 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1012 u32 pir;
1013
1014 if (bitbang->set_gate)
1015 bitbang->set_gate(bitbang->addr);
1016
1017 pir = ioread32(bitbang->addr);
1018 if (set)
1019 pir |= mask;
1020 else
1021 pir &= ~mask;
1022 iowrite32(pir, bitbang->addr);
1023 }
1024
1025 /* Data I/O pin control */
1026 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1027 {
1028 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1029 }
1030
1031 /* Set bit data*/
1032 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1033 {
1034 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1035 }
1036
1037 /* Get bit data*/
1038 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1039 {
1040 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1041
1042 if (bitbang->set_gate)
1043 bitbang->set_gate(bitbang->addr);
1044
1045 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1046 }
1047
1048 /* MDC pin control */
1049 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1050 {
1051 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1052 }
1053
1054 /* mdio bus control struct */
1055 static struct mdiobb_ops bb_ops = {
1056 .owner = THIS_MODULE,
1057 .set_mdc = sh_mdc_ctrl,
1058 .set_mdio_dir = sh_mmd_ctrl,
1059 .set_mdio_data = sh_set_mdio,
1060 .get_mdio_data = sh_get_mdio,
1061 };
1062
1063 /* free skb and descriptor buffer */
1064 static void sh_eth_ring_free(struct net_device *ndev)
1065 {
1066 struct sh_eth_private *mdp = netdev_priv(ndev);
1067 int ringsize, i;
1068
1069 /* Free Rx skb ringbuffer */
1070 if (mdp->rx_skbuff) {
1071 for (i = 0; i < mdp->num_rx_ring; i++)
1072 dev_kfree_skb(mdp->rx_skbuff[i]);
1073 }
1074 kfree(mdp->rx_skbuff);
1075 mdp->rx_skbuff = NULL;
1076
1077 /* Free Tx skb ringbuffer */
1078 if (mdp->tx_skbuff) {
1079 for (i = 0; i < mdp->num_tx_ring; i++)
1080 dev_kfree_skb(mdp->tx_skbuff[i]);
1081 }
1082 kfree(mdp->tx_skbuff);
1083 mdp->tx_skbuff = NULL;
1084
1085 if (mdp->rx_ring) {
1086 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1087 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1088 mdp->rx_desc_dma);
1089 mdp->rx_ring = NULL;
1090 }
1091
1092 if (mdp->tx_ring) {
1093 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1094 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1095 mdp->tx_desc_dma);
1096 mdp->tx_ring = NULL;
1097 }
1098 }
1099
1100 /* format skb and descriptor buffer */
1101 static void sh_eth_ring_format(struct net_device *ndev)
1102 {
1103 struct sh_eth_private *mdp = netdev_priv(ndev);
1104 int i;
1105 struct sk_buff *skb;
1106 struct sh_eth_rxdesc *rxdesc = NULL;
1107 struct sh_eth_txdesc *txdesc = NULL;
1108 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1109 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1110 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1111 dma_addr_t dma_addr;
1112 u32 buf_len;
1113
1114 mdp->cur_rx = 0;
1115 mdp->cur_tx = 0;
1116 mdp->dirty_rx = 0;
1117 mdp->dirty_tx = 0;
1118
1119 memset(mdp->rx_ring, 0, rx_ringsize);
1120
1121 /* build Rx ring buffer */
1122 for (i = 0; i < mdp->num_rx_ring; i++) {
1123 /* skb */
1124 mdp->rx_skbuff[i] = NULL;
1125 skb = netdev_alloc_skb(ndev, skbuff_size);
1126 if (skb == NULL)
1127 break;
1128 sh_eth_set_receive_align(skb);
1129
1130 /* The size of the buffer is a multiple of 32 bytes. */
1131 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1132 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1133 DMA_FROM_DEVICE);
1134 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1135 kfree_skb(skb);
1136 break;
1137 }
1138 mdp->rx_skbuff[i] = skb;
1139
1140 /* RX descriptor */
1141 rxdesc = &mdp->rx_ring[i];
1142 rxdesc->len = cpu_to_le32(buf_len << 16);
1143 rxdesc->addr = cpu_to_le32(dma_addr);
1144 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1145
1146 /* Rx descriptor address set */
1147 if (i == 0) {
1148 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1149 if (sh_eth_is_gether(mdp) ||
1150 sh_eth_is_rz_fast_ether(mdp))
1151 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1152 }
1153 }
1154
1155 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1156
1157 /* Mark the last entry as wrapping the ring. */
1158 if (rxdesc)
1159 rxdesc->status |= cpu_to_le32(RD_RDLE);
1160
1161 memset(mdp->tx_ring, 0, tx_ringsize);
1162
1163 /* build Tx ring buffer */
1164 for (i = 0; i < mdp->num_tx_ring; i++) {
1165 mdp->tx_skbuff[i] = NULL;
1166 txdesc = &mdp->tx_ring[i];
1167 txdesc->status = cpu_to_le32(TD_TFP);
1168 txdesc->len = cpu_to_le32(0);
1169 if (i == 0) {
1170 /* Tx descriptor address set */
1171 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1172 if (sh_eth_is_gether(mdp) ||
1173 sh_eth_is_rz_fast_ether(mdp))
1174 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1175 }
1176 }
1177
1178 txdesc->status |= cpu_to_le32(TD_TDLE);
1179 }
1180
1181 /* Get skb and descriptor buffer */
1182 static int sh_eth_ring_init(struct net_device *ndev)
1183 {
1184 struct sh_eth_private *mdp = netdev_priv(ndev);
1185 int rx_ringsize, tx_ringsize;
1186
1187 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1188 * card needs room to do 8 byte alignment, +2 so we can reserve
1189 * the first 2 bytes, and +16 gets room for the status word from the
1190 * card.
1191 */
1192 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1193 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1194 if (mdp->cd->rpadir)
1195 mdp->rx_buf_sz += NET_IP_ALIGN;
1196
1197 /* Allocate RX and TX skb rings */
1198 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1199 GFP_KERNEL);
1200 if (!mdp->rx_skbuff)
1201 return -ENOMEM;
1202
1203 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1204 GFP_KERNEL);
1205 if (!mdp->tx_skbuff)
1206 goto ring_free;
1207
1208 /* Allocate all Rx descriptors. */
1209 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1210 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1211 GFP_KERNEL);
1212 if (!mdp->rx_ring)
1213 goto ring_free;
1214
1215 mdp->dirty_rx = 0;
1216
1217 /* Allocate all Tx descriptors. */
1218 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1219 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1220 GFP_KERNEL);
1221 if (!mdp->tx_ring)
1222 goto ring_free;
1223 return 0;
1224
1225 ring_free:
1226 /* Free Rx and Tx skb ring buffer and DMA buffer */
1227 sh_eth_ring_free(ndev);
1228
1229 return -ENOMEM;
1230 }
1231
1232 static int sh_eth_dev_init(struct net_device *ndev)
1233 {
1234 struct sh_eth_private *mdp = netdev_priv(ndev);
1235 int ret;
1236
1237 /* Soft Reset */
1238 ret = sh_eth_reset(ndev);
1239 if (ret)
1240 return ret;
1241
1242 if (mdp->cd->rmiimode)
1243 sh_eth_write(ndev, 0x1, RMIIMODE);
1244
1245 /* Descriptor format */
1246 sh_eth_ring_format(ndev);
1247 if (mdp->cd->rpadir)
1248 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1249
1250 /* all sh_eth int mask */
1251 sh_eth_write(ndev, 0, EESIPR);
1252
1253 #if defined(__LITTLE_ENDIAN)
1254 if (mdp->cd->hw_swap)
1255 sh_eth_write(ndev, EDMR_EL, EDMR);
1256 else
1257 #endif
1258 sh_eth_write(ndev, 0, EDMR);
1259
1260 /* FIFO size set */
1261 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1262 sh_eth_write(ndev, 0, TFTR);
1263
1264 /* Frame recv control (enable multiple-packets per rx irq) */
1265 sh_eth_write(ndev, RMCR_RNC, RMCR);
1266
1267 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1268
1269 if (mdp->cd->bculr)
1270 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1271
1272 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1273
1274 if (!mdp->cd->no_trimd)
1275 sh_eth_write(ndev, 0, TRIMD);
1276
1277 /* Recv frame limit set register */
1278 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1279 RFLR);
1280
1281 sh_eth_modify(ndev, EESR, 0, 0);
1282 mdp->irq_enabled = true;
1283 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1284
1285 /* PAUSE Prohibition */
1286 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1287 ECMR_TE | ECMR_RE, ECMR);
1288
1289 if (mdp->cd->set_rate)
1290 mdp->cd->set_rate(ndev);
1291
1292 /* E-MAC Status Register clear */
1293 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1294
1295 /* E-MAC Interrupt Enable register */
1296 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1297
1298 /* Set MAC address */
1299 update_mac_address(ndev);
1300
1301 /* mask reset */
1302 if (mdp->cd->apr)
1303 sh_eth_write(ndev, APR_AP, APR);
1304 if (mdp->cd->mpr)
1305 sh_eth_write(ndev, MPR_MP, MPR);
1306 if (mdp->cd->tpauser)
1307 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1308
1309 /* Setting the Rx mode will start the Rx process. */
1310 sh_eth_write(ndev, EDRRR_R, EDRRR);
1311
1312 return ret;
1313 }
1314
1315 static void sh_eth_dev_exit(struct net_device *ndev)
1316 {
1317 struct sh_eth_private *mdp = netdev_priv(ndev);
1318 int i;
1319
1320 /* Deactivate all TX descriptors, so DMA should stop at next
1321 * packet boundary if it's currently running
1322 */
1323 for (i = 0; i < mdp->num_tx_ring; i++)
1324 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1325
1326 /* Disable TX FIFO egress to MAC */
1327 sh_eth_rcv_snd_disable(ndev);
1328
1329 /* Stop RX DMA at next packet boundary */
1330 sh_eth_write(ndev, 0, EDRRR);
1331
1332 /* Aside from TX DMA, we can't tell when the hardware is
1333 * really stopped, so we need to reset to make sure.
1334 * Before doing that, wait for long enough to *probably*
1335 * finish transmitting the last packet and poll stats.
1336 */
1337 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1338 sh_eth_get_stats(ndev);
1339 sh_eth_reset(ndev);
1340
1341 /* Set MAC address again */
1342 update_mac_address(ndev);
1343 }
1344
1345 /* free Tx skb function */
1346 static int sh_eth_txfree(struct net_device *ndev)
1347 {
1348 struct sh_eth_private *mdp = netdev_priv(ndev);
1349 struct sh_eth_txdesc *txdesc;
1350 int free_num = 0;
1351 int entry;
1352
1353 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1354 entry = mdp->dirty_tx % mdp->num_tx_ring;
1355 txdesc = &mdp->tx_ring[entry];
1356 if (txdesc->status & cpu_to_le32(TD_TACT))
1357 break;
1358 /* TACT bit must be checked before all the following reads */
1359 dma_rmb();
1360 netif_info(mdp, tx_done, ndev,
1361 "tx entry %d status 0x%08x\n",
1362 entry, le32_to_cpu(txdesc->status));
1363 /* Free the original skb. */
1364 if (mdp->tx_skbuff[entry]) {
1365 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1366 le32_to_cpu(txdesc->len) >> 16,
1367 DMA_TO_DEVICE);
1368 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1369 mdp->tx_skbuff[entry] = NULL;
1370 free_num++;
1371 }
1372 txdesc->status = cpu_to_le32(TD_TFP);
1373 if (entry >= mdp->num_tx_ring - 1)
1374 txdesc->status |= cpu_to_le32(TD_TDLE);
1375
1376 ndev->stats.tx_packets++;
1377 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1378 }
1379 return free_num;
1380 }
1381
1382 /* Packet receive function */
1383 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1384 {
1385 struct sh_eth_private *mdp = netdev_priv(ndev);
1386 struct sh_eth_rxdesc *rxdesc;
1387
1388 int entry = mdp->cur_rx % mdp->num_rx_ring;
1389 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1390 int limit;
1391 struct sk_buff *skb;
1392 u32 desc_status;
1393 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1394 dma_addr_t dma_addr;
1395 u16 pkt_len;
1396 u32 buf_len;
1397
1398 boguscnt = min(boguscnt, *quota);
1399 limit = boguscnt;
1400 rxdesc = &mdp->rx_ring[entry];
1401 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1402 /* RACT bit must be checked before all the following reads */
1403 dma_rmb();
1404 desc_status = le32_to_cpu(rxdesc->status);
1405 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1406
1407 if (--boguscnt < 0)
1408 break;
1409
1410 netif_info(mdp, rx_status, ndev,
1411 "rx entry %d status 0x%08x len %d\n",
1412 entry, desc_status, pkt_len);
1413
1414 if (!(desc_status & RDFEND))
1415 ndev->stats.rx_length_errors++;
1416
1417 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1418 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1419 * bit 0. However, in case of the R8A7740 and R7S72100
1420 * the RFS bits are from bit 25 to bit 16. So, the
1421 * driver needs right shifting by 16.
1422 */
1423 if (mdp->cd->shift_rd0)
1424 desc_status >>= 16;
1425
1426 skb = mdp->rx_skbuff[entry];
1427 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1428 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1429 ndev->stats.rx_errors++;
1430 if (desc_status & RD_RFS1)
1431 ndev->stats.rx_crc_errors++;
1432 if (desc_status & RD_RFS2)
1433 ndev->stats.rx_frame_errors++;
1434 if (desc_status & RD_RFS3)
1435 ndev->stats.rx_length_errors++;
1436 if (desc_status & RD_RFS4)
1437 ndev->stats.rx_length_errors++;
1438 if (desc_status & RD_RFS6)
1439 ndev->stats.rx_missed_errors++;
1440 if (desc_status & RD_RFS10)
1441 ndev->stats.rx_over_errors++;
1442 } else if (skb) {
1443 dma_addr = le32_to_cpu(rxdesc->addr);
1444 if (!mdp->cd->hw_swap)
1445 sh_eth_soft_swap(
1446 phys_to_virt(ALIGN(dma_addr, 4)),
1447 pkt_len + 2);
1448 mdp->rx_skbuff[entry] = NULL;
1449 if (mdp->cd->rpadir)
1450 skb_reserve(skb, NET_IP_ALIGN);
1451 dma_unmap_single(&ndev->dev, dma_addr,
1452 ALIGN(mdp->rx_buf_sz, 32),
1453 DMA_FROM_DEVICE);
1454 skb_put(skb, pkt_len);
1455 skb->protocol = eth_type_trans(skb, ndev);
1456 netif_receive_skb(skb);
1457 ndev->stats.rx_packets++;
1458 ndev->stats.rx_bytes += pkt_len;
1459 if (desc_status & RD_RFS8)
1460 ndev->stats.multicast++;
1461 }
1462 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1463 rxdesc = &mdp->rx_ring[entry];
1464 }
1465
1466 /* Refill the Rx ring buffers. */
1467 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1468 entry = mdp->dirty_rx % mdp->num_rx_ring;
1469 rxdesc = &mdp->rx_ring[entry];
1470 /* The size of the buffer is 32 byte boundary. */
1471 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1472 rxdesc->len = cpu_to_le32(buf_len << 16);
1473
1474 if (mdp->rx_skbuff[entry] == NULL) {
1475 skb = netdev_alloc_skb(ndev, skbuff_size);
1476 if (skb == NULL)
1477 break; /* Better luck next round. */
1478 sh_eth_set_receive_align(skb);
1479 dma_addr = dma_map_single(&ndev->dev, skb->data,
1480 buf_len, DMA_FROM_DEVICE);
1481 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1482 kfree_skb(skb);
1483 break;
1484 }
1485 mdp->rx_skbuff[entry] = skb;
1486
1487 skb_checksum_none_assert(skb);
1488 rxdesc->addr = cpu_to_le32(dma_addr);
1489 }
1490 dma_wmb(); /* RACT bit must be set after all the above writes */
1491 if (entry >= mdp->num_rx_ring - 1)
1492 rxdesc->status |=
1493 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1494 else
1495 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1496 }
1497
1498 /* Restart Rx engine if stopped. */
1499 /* If we don't need to check status, don't. -KDU */
1500 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1501 /* fix the values for the next receiving if RDE is set */
1502 if (intr_status & EESR_RDE &&
1503 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1504 u32 count = (sh_eth_read(ndev, RDFAR) -
1505 sh_eth_read(ndev, RDLAR)) >> 4;
1506
1507 mdp->cur_rx = count;
1508 mdp->dirty_rx = count;
1509 }
1510 sh_eth_write(ndev, EDRRR_R, EDRRR);
1511 }
1512
1513 *quota -= limit - boguscnt - 1;
1514
1515 return *quota <= 0;
1516 }
1517
1518 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1519 {
1520 /* disable tx and rx */
1521 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1522 }
1523
1524 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1525 {
1526 /* enable tx and rx */
1527 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1528 }
1529
1530 /* error control function */
1531 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1532 {
1533 struct sh_eth_private *mdp = netdev_priv(ndev);
1534 u32 felic_stat;
1535 u32 link_stat;
1536 u32 mask;
1537
1538 if (intr_status & EESR_ECI) {
1539 felic_stat = sh_eth_read(ndev, ECSR);
1540 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1541 if (felic_stat & ECSR_ICD)
1542 ndev->stats.tx_carrier_errors++;
1543 if (felic_stat & ECSR_LCHNG) {
1544 /* Link Changed */
1545 if (mdp->cd->no_psr || mdp->no_ether_link) {
1546 goto ignore_link;
1547 } else {
1548 link_stat = (sh_eth_read(ndev, PSR));
1549 if (mdp->ether_link_active_low)
1550 link_stat = ~link_stat;
1551 }
1552 if (!(link_stat & PHY_ST_LINK)) {
1553 sh_eth_rcv_snd_disable(ndev);
1554 } else {
1555 /* Link Up */
1556 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1557 /* clear int */
1558 sh_eth_modify(ndev, ECSR, 0, 0);
1559 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1560 DMAC_M_ECI);
1561 /* enable tx and rx */
1562 sh_eth_rcv_snd_enable(ndev);
1563 }
1564 }
1565 }
1566
1567 ignore_link:
1568 if (intr_status & EESR_TWB) {
1569 /* Unused write back interrupt */
1570 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1571 ndev->stats.tx_aborted_errors++;
1572 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1573 }
1574 }
1575
1576 if (intr_status & EESR_RABT) {
1577 /* Receive Abort int */
1578 if (intr_status & EESR_RFRMER) {
1579 /* Receive Frame Overflow int */
1580 ndev->stats.rx_frame_errors++;
1581 }
1582 }
1583
1584 if (intr_status & EESR_TDE) {
1585 /* Transmit Descriptor Empty int */
1586 ndev->stats.tx_fifo_errors++;
1587 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1588 }
1589
1590 if (intr_status & EESR_TFE) {
1591 /* FIFO under flow */
1592 ndev->stats.tx_fifo_errors++;
1593 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1594 }
1595
1596 if (intr_status & EESR_RDE) {
1597 /* Receive Descriptor Empty int */
1598 ndev->stats.rx_over_errors++;
1599 }
1600
1601 if (intr_status & EESR_RFE) {
1602 /* Receive FIFO Overflow int */
1603 ndev->stats.rx_fifo_errors++;
1604 }
1605
1606 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1607 /* Address Error */
1608 ndev->stats.tx_fifo_errors++;
1609 netif_err(mdp, tx_err, ndev, "Address Error\n");
1610 }
1611
1612 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1613 if (mdp->cd->no_ade)
1614 mask &= ~EESR_ADE;
1615 if (intr_status & mask) {
1616 /* Tx error */
1617 u32 edtrr = sh_eth_read(ndev, EDTRR);
1618
1619 /* dmesg */
1620 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1621 intr_status, mdp->cur_tx, mdp->dirty_tx,
1622 (u32)ndev->state, edtrr);
1623 /* dirty buffer free */
1624 sh_eth_txfree(ndev);
1625
1626 /* SH7712 BUG */
1627 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1628 /* tx dma start */
1629 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1630 }
1631 /* wakeup */
1632 netif_wake_queue(ndev);
1633 }
1634 }
1635
1636 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1637 {
1638 struct net_device *ndev = netdev;
1639 struct sh_eth_private *mdp = netdev_priv(ndev);
1640 struct sh_eth_cpu_data *cd = mdp->cd;
1641 irqreturn_t ret = IRQ_NONE;
1642 u32 intr_status, intr_enable;
1643
1644 spin_lock(&mdp->lock);
1645
1646 /* Get interrupt status */
1647 intr_status = sh_eth_read(ndev, EESR);
1648 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1649 * enabled since it's the one that comes thru regardless of the mask,
1650 * and we need to fully handle it in sh_eth_error() in order to quench
1651 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1652 */
1653 intr_enable = sh_eth_read(ndev, EESIPR);
1654 intr_status &= intr_enable | DMAC_M_ECI;
1655 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1656 ret = IRQ_HANDLED;
1657 else
1658 goto out;
1659
1660 if (unlikely(!mdp->irq_enabled)) {
1661 sh_eth_write(ndev, 0, EESIPR);
1662 goto out;
1663 }
1664
1665 if (intr_status & EESR_RX_CHECK) {
1666 if (napi_schedule_prep(&mdp->napi)) {
1667 /* Mask Rx interrupts */
1668 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1669 EESIPR);
1670 __napi_schedule(&mdp->napi);
1671 } else {
1672 netdev_warn(ndev,
1673 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1674 intr_status, intr_enable);
1675 }
1676 }
1677
1678 /* Tx Check */
1679 if (intr_status & cd->tx_check) {
1680 /* Clear Tx interrupts */
1681 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1682
1683 sh_eth_txfree(ndev);
1684 netif_wake_queue(ndev);
1685 }
1686
1687 if (intr_status & cd->eesr_err_check) {
1688 /* Clear error interrupts */
1689 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1690
1691 sh_eth_error(ndev, intr_status);
1692 }
1693
1694 out:
1695 spin_unlock(&mdp->lock);
1696
1697 return ret;
1698 }
1699
1700 static int sh_eth_poll(struct napi_struct *napi, int budget)
1701 {
1702 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1703 napi);
1704 struct net_device *ndev = napi->dev;
1705 int quota = budget;
1706 u32 intr_status;
1707
1708 for (;;) {
1709 intr_status = sh_eth_read(ndev, EESR);
1710 if (!(intr_status & EESR_RX_CHECK))
1711 break;
1712 /* Clear Rx interrupts */
1713 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1714
1715 if (sh_eth_rx(ndev, intr_status, &quota))
1716 goto out;
1717 }
1718
1719 napi_complete(napi);
1720
1721 /* Reenable Rx interrupts */
1722 if (mdp->irq_enabled)
1723 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1724 out:
1725 return budget - quota;
1726 }
1727
1728 /* PHY state control function */
1729 static void sh_eth_adjust_link(struct net_device *ndev)
1730 {
1731 struct sh_eth_private *mdp = netdev_priv(ndev);
1732 struct phy_device *phydev = ndev->phydev;
1733 int new_state = 0;
1734
1735 if (phydev->link) {
1736 if (phydev->duplex != mdp->duplex) {
1737 new_state = 1;
1738 mdp->duplex = phydev->duplex;
1739 if (mdp->cd->set_duplex)
1740 mdp->cd->set_duplex(ndev);
1741 }
1742
1743 if (phydev->speed != mdp->speed) {
1744 new_state = 1;
1745 mdp->speed = phydev->speed;
1746 if (mdp->cd->set_rate)
1747 mdp->cd->set_rate(ndev);
1748 }
1749 if (!mdp->link) {
1750 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1751 new_state = 1;
1752 mdp->link = phydev->link;
1753 if (mdp->cd->no_psr || mdp->no_ether_link)
1754 sh_eth_rcv_snd_enable(ndev);
1755 }
1756 } else if (mdp->link) {
1757 new_state = 1;
1758 mdp->link = 0;
1759 mdp->speed = 0;
1760 mdp->duplex = -1;
1761 if (mdp->cd->no_psr || mdp->no_ether_link)
1762 sh_eth_rcv_snd_disable(ndev);
1763 }
1764
1765 if (new_state && netif_msg_link(mdp))
1766 phy_print_status(phydev);
1767 }
1768
1769 /* PHY init function */
1770 static int sh_eth_phy_init(struct net_device *ndev)
1771 {
1772 struct device_node *np = ndev->dev.parent->of_node;
1773 struct sh_eth_private *mdp = netdev_priv(ndev);
1774 struct phy_device *phydev;
1775
1776 mdp->link = 0;
1777 mdp->speed = 0;
1778 mdp->duplex = -1;
1779
1780 /* Try connect to PHY */
1781 if (np) {
1782 struct device_node *pn;
1783
1784 pn = of_parse_phandle(np, "phy-handle", 0);
1785 phydev = of_phy_connect(ndev, pn,
1786 sh_eth_adjust_link, 0,
1787 mdp->phy_interface);
1788
1789 of_node_put(pn);
1790 if (!phydev)
1791 phydev = ERR_PTR(-ENOENT);
1792 } else {
1793 char phy_id[MII_BUS_ID_SIZE + 3];
1794
1795 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1796 mdp->mii_bus->id, mdp->phy_id);
1797
1798 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1799 mdp->phy_interface);
1800 }
1801
1802 if (IS_ERR(phydev)) {
1803 netdev_err(ndev, "failed to connect PHY\n");
1804 return PTR_ERR(phydev);
1805 }
1806
1807 phy_attached_info(phydev);
1808
1809 return 0;
1810 }
1811
1812 /* PHY control start function */
1813 static int sh_eth_phy_start(struct net_device *ndev)
1814 {
1815 int ret;
1816
1817 ret = sh_eth_phy_init(ndev);
1818 if (ret)
1819 return ret;
1820
1821 phy_start(ndev->phydev);
1822
1823 return 0;
1824 }
1825
1826 static int sh_eth_get_link_ksettings(struct net_device *ndev,
1827 struct ethtool_link_ksettings *cmd)
1828 {
1829 struct sh_eth_private *mdp = netdev_priv(ndev);
1830 unsigned long flags;
1831 int ret;
1832
1833 if (!ndev->phydev)
1834 return -ENODEV;
1835
1836 spin_lock_irqsave(&mdp->lock, flags);
1837 ret = phy_ethtool_ksettings_get(ndev->phydev, cmd);
1838 spin_unlock_irqrestore(&mdp->lock, flags);
1839
1840 return ret;
1841 }
1842
1843 static int sh_eth_set_link_ksettings(struct net_device *ndev,
1844 const struct ethtool_link_ksettings *cmd)
1845 {
1846 struct sh_eth_private *mdp = netdev_priv(ndev);
1847 unsigned long flags;
1848 int ret;
1849
1850 if (!ndev->phydev)
1851 return -ENODEV;
1852
1853 spin_lock_irqsave(&mdp->lock, flags);
1854
1855 /* disable tx and rx */
1856 sh_eth_rcv_snd_disable(ndev);
1857
1858 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1859 if (ret)
1860 goto error_exit;
1861
1862 if (cmd->base.duplex == DUPLEX_FULL)
1863 mdp->duplex = 1;
1864 else
1865 mdp->duplex = 0;
1866
1867 if (mdp->cd->set_duplex)
1868 mdp->cd->set_duplex(ndev);
1869
1870 error_exit:
1871 mdelay(1);
1872
1873 /* enable tx and rx */
1874 sh_eth_rcv_snd_enable(ndev);
1875
1876 spin_unlock_irqrestore(&mdp->lock, flags);
1877
1878 return ret;
1879 }
1880
1881 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1882 * version must be bumped as well. Just adding registers up to that
1883 * limit is fine, as long as the existing register indices don't
1884 * change.
1885 */
1886 #define SH_ETH_REG_DUMP_VERSION 1
1887 #define SH_ETH_REG_DUMP_MAX_REGS 256
1888
1889 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1890 {
1891 struct sh_eth_private *mdp = netdev_priv(ndev);
1892 struct sh_eth_cpu_data *cd = mdp->cd;
1893 u32 *valid_map;
1894 size_t len;
1895
1896 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1897
1898 /* Dump starts with a bitmap that tells ethtool which
1899 * registers are defined for this chip.
1900 */
1901 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1902 if (buf) {
1903 valid_map = buf;
1904 buf += len;
1905 } else {
1906 valid_map = NULL;
1907 }
1908
1909 /* Add a register to the dump, if it has a defined offset.
1910 * This automatically skips most undefined registers, but for
1911 * some it is also necessary to check a capability flag in
1912 * struct sh_eth_cpu_data.
1913 */
1914 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1915 #define add_reg_from(reg, read_expr) do { \
1916 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1917 if (buf) { \
1918 mark_reg_valid(reg); \
1919 *buf++ = read_expr; \
1920 } \
1921 ++len; \
1922 } \
1923 } while (0)
1924 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1925 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1926
1927 add_reg(EDSR);
1928 add_reg(EDMR);
1929 add_reg(EDTRR);
1930 add_reg(EDRRR);
1931 add_reg(EESR);
1932 add_reg(EESIPR);
1933 add_reg(TDLAR);
1934 add_reg(TDFAR);
1935 add_reg(TDFXR);
1936 add_reg(TDFFR);
1937 add_reg(RDLAR);
1938 add_reg(RDFAR);
1939 add_reg(RDFXR);
1940 add_reg(RDFFR);
1941 add_reg(TRSCER);
1942 add_reg(RMFCR);
1943 add_reg(TFTR);
1944 add_reg(FDR);
1945 add_reg(RMCR);
1946 add_reg(TFUCR);
1947 add_reg(RFOCR);
1948 if (cd->rmiimode)
1949 add_reg(RMIIMODE);
1950 add_reg(FCFTR);
1951 if (cd->rpadir)
1952 add_reg(RPADIR);
1953 if (!cd->no_trimd)
1954 add_reg(TRIMD);
1955 add_reg(ECMR);
1956 add_reg(ECSR);
1957 add_reg(ECSIPR);
1958 add_reg(PIR);
1959 if (!cd->no_psr)
1960 add_reg(PSR);
1961 add_reg(RDMLR);
1962 add_reg(RFLR);
1963 add_reg(IPGR);
1964 if (cd->apr)
1965 add_reg(APR);
1966 if (cd->mpr)
1967 add_reg(MPR);
1968 add_reg(RFCR);
1969 add_reg(RFCF);
1970 if (cd->tpauser)
1971 add_reg(TPAUSER);
1972 add_reg(TPAUSECR);
1973 add_reg(GECMR);
1974 if (cd->bculr)
1975 add_reg(BCULR);
1976 add_reg(MAHR);
1977 add_reg(MALR);
1978 add_reg(TROCR);
1979 add_reg(CDCR);
1980 add_reg(LCCR);
1981 add_reg(CNDCR);
1982 add_reg(CEFCR);
1983 add_reg(FRECR);
1984 add_reg(TSFRCR);
1985 add_reg(TLFRCR);
1986 add_reg(CERCR);
1987 add_reg(CEECR);
1988 add_reg(MAFCR);
1989 if (cd->rtrate)
1990 add_reg(RTRATE);
1991 if (cd->hw_crc)
1992 add_reg(CSMR);
1993 if (cd->select_mii)
1994 add_reg(RMII_MII);
1995 add_reg(ARSTR);
1996 if (cd->tsu) {
1997 add_tsu_reg(TSU_CTRST);
1998 add_tsu_reg(TSU_FWEN0);
1999 add_tsu_reg(TSU_FWEN1);
2000 add_tsu_reg(TSU_FCM);
2001 add_tsu_reg(TSU_BSYSL0);
2002 add_tsu_reg(TSU_BSYSL1);
2003 add_tsu_reg(TSU_PRISL0);
2004 add_tsu_reg(TSU_PRISL1);
2005 add_tsu_reg(TSU_FWSL0);
2006 add_tsu_reg(TSU_FWSL1);
2007 add_tsu_reg(TSU_FWSLC);
2008 add_tsu_reg(TSU_QTAG0);
2009 add_tsu_reg(TSU_QTAG1);
2010 add_tsu_reg(TSU_QTAGM0);
2011 add_tsu_reg(TSU_QTAGM1);
2012 add_tsu_reg(TSU_FWSR);
2013 add_tsu_reg(TSU_FWINMK);
2014 add_tsu_reg(TSU_ADQT0);
2015 add_tsu_reg(TSU_ADQT1);
2016 add_tsu_reg(TSU_VTAG0);
2017 add_tsu_reg(TSU_VTAG1);
2018 add_tsu_reg(TSU_ADSBSY);
2019 add_tsu_reg(TSU_TEN);
2020 add_tsu_reg(TSU_POST1);
2021 add_tsu_reg(TSU_POST2);
2022 add_tsu_reg(TSU_POST3);
2023 add_tsu_reg(TSU_POST4);
2024 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2025 /* This is the start of a table, not just a single
2026 * register.
2027 */
2028 if (buf) {
2029 unsigned int i;
2030
2031 mark_reg_valid(TSU_ADRH0);
2032 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2033 *buf++ = ioread32(
2034 mdp->tsu_addr +
2035 mdp->reg_offset[TSU_ADRH0] +
2036 i * 4);
2037 }
2038 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2039 }
2040 }
2041
2042 #undef mark_reg_valid
2043 #undef add_reg_from
2044 #undef add_reg
2045 #undef add_tsu_reg
2046
2047 return len * 4;
2048 }
2049
2050 static int sh_eth_get_regs_len(struct net_device *ndev)
2051 {
2052 return __sh_eth_get_regs(ndev, NULL);
2053 }
2054
2055 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2056 void *buf)
2057 {
2058 struct sh_eth_private *mdp = netdev_priv(ndev);
2059
2060 regs->version = SH_ETH_REG_DUMP_VERSION;
2061
2062 pm_runtime_get_sync(&mdp->pdev->dev);
2063 __sh_eth_get_regs(ndev, buf);
2064 pm_runtime_put_sync(&mdp->pdev->dev);
2065 }
2066
2067 static int sh_eth_nway_reset(struct net_device *ndev)
2068 {
2069 struct sh_eth_private *mdp = netdev_priv(ndev);
2070 unsigned long flags;
2071 int ret;
2072
2073 if (!ndev->phydev)
2074 return -ENODEV;
2075
2076 spin_lock_irqsave(&mdp->lock, flags);
2077 ret = phy_start_aneg(ndev->phydev);
2078 spin_unlock_irqrestore(&mdp->lock, flags);
2079
2080 return ret;
2081 }
2082
2083 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2084 {
2085 struct sh_eth_private *mdp = netdev_priv(ndev);
2086 return mdp->msg_enable;
2087 }
2088
2089 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2090 {
2091 struct sh_eth_private *mdp = netdev_priv(ndev);
2092 mdp->msg_enable = value;
2093 }
2094
2095 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2096 "rx_current", "tx_current",
2097 "rx_dirty", "tx_dirty",
2098 };
2099 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2100
2101 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2102 {
2103 switch (sset) {
2104 case ETH_SS_STATS:
2105 return SH_ETH_STATS_LEN;
2106 default:
2107 return -EOPNOTSUPP;
2108 }
2109 }
2110
2111 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2112 struct ethtool_stats *stats, u64 *data)
2113 {
2114 struct sh_eth_private *mdp = netdev_priv(ndev);
2115 int i = 0;
2116
2117 /* device-specific stats */
2118 data[i++] = mdp->cur_rx;
2119 data[i++] = mdp->cur_tx;
2120 data[i++] = mdp->dirty_rx;
2121 data[i++] = mdp->dirty_tx;
2122 }
2123
2124 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2125 {
2126 switch (stringset) {
2127 case ETH_SS_STATS:
2128 memcpy(data, *sh_eth_gstrings_stats,
2129 sizeof(sh_eth_gstrings_stats));
2130 break;
2131 }
2132 }
2133
2134 static void sh_eth_get_ringparam(struct net_device *ndev,
2135 struct ethtool_ringparam *ring)
2136 {
2137 struct sh_eth_private *mdp = netdev_priv(ndev);
2138
2139 ring->rx_max_pending = RX_RING_MAX;
2140 ring->tx_max_pending = TX_RING_MAX;
2141 ring->rx_pending = mdp->num_rx_ring;
2142 ring->tx_pending = mdp->num_tx_ring;
2143 }
2144
2145 static int sh_eth_set_ringparam(struct net_device *ndev,
2146 struct ethtool_ringparam *ring)
2147 {
2148 struct sh_eth_private *mdp = netdev_priv(ndev);
2149 int ret;
2150
2151 if (ring->tx_pending > TX_RING_MAX ||
2152 ring->rx_pending > RX_RING_MAX ||
2153 ring->tx_pending < TX_RING_MIN ||
2154 ring->rx_pending < RX_RING_MIN)
2155 return -EINVAL;
2156 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2157 return -EINVAL;
2158
2159 if (netif_running(ndev)) {
2160 netif_device_detach(ndev);
2161 netif_tx_disable(ndev);
2162
2163 /* Serialise with the interrupt handler and NAPI, then
2164 * disable interrupts. We have to clear the
2165 * irq_enabled flag first to ensure that interrupts
2166 * won't be re-enabled.
2167 */
2168 mdp->irq_enabled = false;
2169 synchronize_irq(ndev->irq);
2170 napi_synchronize(&mdp->napi);
2171 sh_eth_write(ndev, 0x0000, EESIPR);
2172
2173 sh_eth_dev_exit(ndev);
2174
2175 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2176 sh_eth_ring_free(ndev);
2177 }
2178
2179 /* Set new parameters */
2180 mdp->num_rx_ring = ring->rx_pending;
2181 mdp->num_tx_ring = ring->tx_pending;
2182
2183 if (netif_running(ndev)) {
2184 ret = sh_eth_ring_init(ndev);
2185 if (ret < 0) {
2186 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2187 __func__);
2188 return ret;
2189 }
2190 ret = sh_eth_dev_init(ndev);
2191 if (ret < 0) {
2192 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2193 __func__);
2194 return ret;
2195 }
2196
2197 netif_device_attach(ndev);
2198 }
2199
2200 return 0;
2201 }
2202
2203 static const struct ethtool_ops sh_eth_ethtool_ops = {
2204 .get_regs_len = sh_eth_get_regs_len,
2205 .get_regs = sh_eth_get_regs,
2206 .nway_reset = sh_eth_nway_reset,
2207 .get_msglevel = sh_eth_get_msglevel,
2208 .set_msglevel = sh_eth_set_msglevel,
2209 .get_link = ethtool_op_get_link,
2210 .get_strings = sh_eth_get_strings,
2211 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2212 .get_sset_count = sh_eth_get_sset_count,
2213 .get_ringparam = sh_eth_get_ringparam,
2214 .set_ringparam = sh_eth_set_ringparam,
2215 .get_link_ksettings = sh_eth_get_link_ksettings,
2216 .set_link_ksettings = sh_eth_set_link_ksettings,
2217 };
2218
2219 /* network device open function */
2220 static int sh_eth_open(struct net_device *ndev)
2221 {
2222 struct sh_eth_private *mdp = netdev_priv(ndev);
2223 int ret;
2224
2225 pm_runtime_get_sync(&mdp->pdev->dev);
2226
2227 napi_enable(&mdp->napi);
2228
2229 ret = request_irq(ndev->irq, sh_eth_interrupt,
2230 mdp->cd->irq_flags, ndev->name, ndev);
2231 if (ret) {
2232 netdev_err(ndev, "Can not assign IRQ number\n");
2233 goto out_napi_off;
2234 }
2235
2236 /* Descriptor set */
2237 ret = sh_eth_ring_init(ndev);
2238 if (ret)
2239 goto out_free_irq;
2240
2241 /* device init */
2242 ret = sh_eth_dev_init(ndev);
2243 if (ret)
2244 goto out_free_irq;
2245
2246 /* PHY control start*/
2247 ret = sh_eth_phy_start(ndev);
2248 if (ret)
2249 goto out_free_irq;
2250
2251 netif_start_queue(ndev);
2252
2253 mdp->is_opened = 1;
2254
2255 return ret;
2256
2257 out_free_irq:
2258 free_irq(ndev->irq, ndev);
2259 out_napi_off:
2260 napi_disable(&mdp->napi);
2261 pm_runtime_put_sync(&mdp->pdev->dev);
2262 return ret;
2263 }
2264
2265 /* Timeout function */
2266 static void sh_eth_tx_timeout(struct net_device *ndev)
2267 {
2268 struct sh_eth_private *mdp = netdev_priv(ndev);
2269 struct sh_eth_rxdesc *rxdesc;
2270 int i;
2271
2272 netif_stop_queue(ndev);
2273
2274 netif_err(mdp, timer, ndev,
2275 "transmit timed out, status %8.8x, resetting...\n",
2276 sh_eth_read(ndev, EESR));
2277
2278 /* tx_errors count up */
2279 ndev->stats.tx_errors++;
2280
2281 /* Free all the skbuffs in the Rx queue. */
2282 for (i = 0; i < mdp->num_rx_ring; i++) {
2283 rxdesc = &mdp->rx_ring[i];
2284 rxdesc->status = cpu_to_le32(0);
2285 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2286 dev_kfree_skb(mdp->rx_skbuff[i]);
2287 mdp->rx_skbuff[i] = NULL;
2288 }
2289 for (i = 0; i < mdp->num_tx_ring; i++) {
2290 dev_kfree_skb(mdp->tx_skbuff[i]);
2291 mdp->tx_skbuff[i] = NULL;
2292 }
2293
2294 /* device init */
2295 sh_eth_dev_init(ndev);
2296
2297 netif_start_queue(ndev);
2298 }
2299
2300 /* Packet transmit function */
2301 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2302 {
2303 struct sh_eth_private *mdp = netdev_priv(ndev);
2304 struct sh_eth_txdesc *txdesc;
2305 dma_addr_t dma_addr;
2306 u32 entry;
2307 unsigned long flags;
2308
2309 spin_lock_irqsave(&mdp->lock, flags);
2310 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2311 if (!sh_eth_txfree(ndev)) {
2312 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2313 netif_stop_queue(ndev);
2314 spin_unlock_irqrestore(&mdp->lock, flags);
2315 return NETDEV_TX_BUSY;
2316 }
2317 }
2318 spin_unlock_irqrestore(&mdp->lock, flags);
2319
2320 if (skb_put_padto(skb, ETH_ZLEN))
2321 return NETDEV_TX_OK;
2322
2323 entry = mdp->cur_tx % mdp->num_tx_ring;
2324 mdp->tx_skbuff[entry] = skb;
2325 txdesc = &mdp->tx_ring[entry];
2326 /* soft swap. */
2327 if (!mdp->cd->hw_swap)
2328 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2329 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2330 DMA_TO_DEVICE);
2331 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2332 kfree_skb(skb);
2333 return NETDEV_TX_OK;
2334 }
2335 txdesc->addr = cpu_to_le32(dma_addr);
2336 txdesc->len = cpu_to_le32(skb->len << 16);
2337
2338 dma_wmb(); /* TACT bit must be set after all the above writes */
2339 if (entry >= mdp->num_tx_ring - 1)
2340 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2341 else
2342 txdesc->status |= cpu_to_le32(TD_TACT);
2343
2344 mdp->cur_tx++;
2345
2346 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2347 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2348
2349 return NETDEV_TX_OK;
2350 }
2351
2352 /* The statistics registers have write-clear behaviour, which means we
2353 * will lose any increment between the read and write. We mitigate
2354 * this by only clearing when we read a non-zero value, so we will
2355 * never falsely report a total of zero.
2356 */
2357 static void
2358 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2359 {
2360 u32 delta = sh_eth_read(ndev, reg);
2361
2362 if (delta) {
2363 *stat += delta;
2364 sh_eth_write(ndev, 0, reg);
2365 }
2366 }
2367
2368 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2369 {
2370 struct sh_eth_private *mdp = netdev_priv(ndev);
2371
2372 if (sh_eth_is_rz_fast_ether(mdp))
2373 return &ndev->stats;
2374
2375 if (!mdp->is_opened)
2376 return &ndev->stats;
2377
2378 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2379 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2380 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2381
2382 if (sh_eth_is_gether(mdp)) {
2383 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2384 CERCR);
2385 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2386 CEECR);
2387 } else {
2388 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2389 CNDCR);
2390 }
2391
2392 return &ndev->stats;
2393 }
2394
2395 /* device close function */
2396 static int sh_eth_close(struct net_device *ndev)
2397 {
2398 struct sh_eth_private *mdp = netdev_priv(ndev);
2399
2400 netif_stop_queue(ndev);
2401
2402 /* Serialise with the interrupt handler and NAPI, then disable
2403 * interrupts. We have to clear the irq_enabled flag first to
2404 * ensure that interrupts won't be re-enabled.
2405 */
2406 mdp->irq_enabled = false;
2407 synchronize_irq(ndev->irq);
2408 napi_disable(&mdp->napi);
2409 sh_eth_write(ndev, 0x0000, EESIPR);
2410
2411 sh_eth_dev_exit(ndev);
2412
2413 /* PHY Disconnect */
2414 if (ndev->phydev) {
2415 phy_stop(ndev->phydev);
2416 phy_disconnect(ndev->phydev);
2417 }
2418
2419 free_irq(ndev->irq, ndev);
2420
2421 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2422 sh_eth_ring_free(ndev);
2423
2424 pm_runtime_put_sync(&mdp->pdev->dev);
2425
2426 mdp->is_opened = 0;
2427
2428 return 0;
2429 }
2430
2431 /* ioctl to device function */
2432 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2433 {
2434 struct phy_device *phydev = ndev->phydev;
2435
2436 if (!netif_running(ndev))
2437 return -EINVAL;
2438
2439 if (!phydev)
2440 return -ENODEV;
2441
2442 return phy_mii_ioctl(phydev, rq, cmd);
2443 }
2444
2445 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2446 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2447 int entry)
2448 {
2449 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2450 }
2451
2452 static u32 sh_eth_tsu_get_post_mask(int entry)
2453 {
2454 return 0x0f << (28 - ((entry % 8) * 4));
2455 }
2456
2457 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2458 {
2459 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2460 }
2461
2462 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2463 int entry)
2464 {
2465 struct sh_eth_private *mdp = netdev_priv(ndev);
2466 u32 tmp;
2467 void *reg_offset;
2468
2469 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2470 tmp = ioread32(reg_offset);
2471 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2472 }
2473
2474 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2475 int entry)
2476 {
2477 struct sh_eth_private *mdp = netdev_priv(ndev);
2478 u32 post_mask, ref_mask, tmp;
2479 void *reg_offset;
2480
2481 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2482 post_mask = sh_eth_tsu_get_post_mask(entry);
2483 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2484
2485 tmp = ioread32(reg_offset);
2486 iowrite32(tmp & ~post_mask, reg_offset);
2487
2488 /* If other port enables, the function returns "true" */
2489 return tmp & ref_mask;
2490 }
2491
2492 static int sh_eth_tsu_busy(struct net_device *ndev)
2493 {
2494 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2495 struct sh_eth_private *mdp = netdev_priv(ndev);
2496
2497 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2498 udelay(10);
2499 timeout--;
2500 if (timeout <= 0) {
2501 netdev_err(ndev, "%s: timeout\n", __func__);
2502 return -ETIMEDOUT;
2503 }
2504 }
2505
2506 return 0;
2507 }
2508
2509 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2510 const u8 *addr)
2511 {
2512 u32 val;
2513
2514 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2515 iowrite32(val, reg);
2516 if (sh_eth_tsu_busy(ndev) < 0)
2517 return -EBUSY;
2518
2519 val = addr[4] << 8 | addr[5];
2520 iowrite32(val, reg + 4);
2521 if (sh_eth_tsu_busy(ndev) < 0)
2522 return -EBUSY;
2523
2524 return 0;
2525 }
2526
2527 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2528 {
2529 u32 val;
2530
2531 val = ioread32(reg);
2532 addr[0] = (val >> 24) & 0xff;
2533 addr[1] = (val >> 16) & 0xff;
2534 addr[2] = (val >> 8) & 0xff;
2535 addr[3] = val & 0xff;
2536 val = ioread32(reg + 4);
2537 addr[4] = (val >> 8) & 0xff;
2538 addr[5] = val & 0xff;
2539 }
2540
2541
2542 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2543 {
2544 struct sh_eth_private *mdp = netdev_priv(ndev);
2545 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2546 int i;
2547 u8 c_addr[ETH_ALEN];
2548
2549 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2550 sh_eth_tsu_read_entry(reg_offset, c_addr);
2551 if (ether_addr_equal(addr, c_addr))
2552 return i;
2553 }
2554
2555 return -ENOENT;
2556 }
2557
2558 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2559 {
2560 u8 blank[ETH_ALEN];
2561 int entry;
2562
2563 memset(blank, 0, sizeof(blank));
2564 entry = sh_eth_tsu_find_entry(ndev, blank);
2565 return (entry < 0) ? -ENOMEM : entry;
2566 }
2567
2568 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2569 int entry)
2570 {
2571 struct sh_eth_private *mdp = netdev_priv(ndev);
2572 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2573 int ret;
2574 u8 blank[ETH_ALEN];
2575
2576 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2577 ~(1 << (31 - entry)), TSU_TEN);
2578
2579 memset(blank, 0, sizeof(blank));
2580 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2581 if (ret < 0)
2582 return ret;
2583 return 0;
2584 }
2585
2586 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2587 {
2588 struct sh_eth_private *mdp = netdev_priv(ndev);
2589 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2590 int i, ret;
2591
2592 if (!mdp->cd->tsu)
2593 return 0;
2594
2595 i = sh_eth_tsu_find_entry(ndev, addr);
2596 if (i < 0) {
2597 /* No entry found, create one */
2598 i = sh_eth_tsu_find_empty(ndev);
2599 if (i < 0)
2600 return -ENOMEM;
2601 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2602 if (ret < 0)
2603 return ret;
2604
2605 /* Enable the entry */
2606 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2607 (1 << (31 - i)), TSU_TEN);
2608 }
2609
2610 /* Entry found or created, enable POST */
2611 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2612
2613 return 0;
2614 }
2615
2616 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2617 {
2618 struct sh_eth_private *mdp = netdev_priv(ndev);
2619 int i, ret;
2620
2621 if (!mdp->cd->tsu)
2622 return 0;
2623
2624 i = sh_eth_tsu_find_entry(ndev, addr);
2625 if (i) {
2626 /* Entry found */
2627 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2628 goto done;
2629
2630 /* Disable the entry if both ports was disabled */
2631 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2632 if (ret < 0)
2633 return ret;
2634 }
2635 done:
2636 return 0;
2637 }
2638
2639 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2640 {
2641 struct sh_eth_private *mdp = netdev_priv(ndev);
2642 int i, ret;
2643
2644 if (!mdp->cd->tsu)
2645 return 0;
2646
2647 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2648 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2649 continue;
2650
2651 /* Disable the entry if both ports was disabled */
2652 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2653 if (ret < 0)
2654 return ret;
2655 }
2656
2657 return 0;
2658 }
2659
2660 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2661 {
2662 struct sh_eth_private *mdp = netdev_priv(ndev);
2663 u8 addr[ETH_ALEN];
2664 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2665 int i;
2666
2667 if (!mdp->cd->tsu)
2668 return;
2669
2670 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2671 sh_eth_tsu_read_entry(reg_offset, addr);
2672 if (is_multicast_ether_addr(addr))
2673 sh_eth_tsu_del_entry(ndev, addr);
2674 }
2675 }
2676
2677 /* Update promiscuous flag and multicast filter */
2678 static void sh_eth_set_rx_mode(struct net_device *ndev)
2679 {
2680 struct sh_eth_private *mdp = netdev_priv(ndev);
2681 u32 ecmr_bits;
2682 int mcast_all = 0;
2683 unsigned long flags;
2684
2685 spin_lock_irqsave(&mdp->lock, flags);
2686 /* Initial condition is MCT = 1, PRM = 0.
2687 * Depending on ndev->flags, set PRM or clear MCT
2688 */
2689 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2690 if (mdp->cd->tsu)
2691 ecmr_bits |= ECMR_MCT;
2692
2693 if (!(ndev->flags & IFF_MULTICAST)) {
2694 sh_eth_tsu_purge_mcast(ndev);
2695 mcast_all = 1;
2696 }
2697 if (ndev->flags & IFF_ALLMULTI) {
2698 sh_eth_tsu_purge_mcast(ndev);
2699 ecmr_bits &= ~ECMR_MCT;
2700 mcast_all = 1;
2701 }
2702
2703 if (ndev->flags & IFF_PROMISC) {
2704 sh_eth_tsu_purge_all(ndev);
2705 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2706 } else if (mdp->cd->tsu) {
2707 struct netdev_hw_addr *ha;
2708 netdev_for_each_mc_addr(ha, ndev) {
2709 if (mcast_all && is_multicast_ether_addr(ha->addr))
2710 continue;
2711
2712 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2713 if (!mcast_all) {
2714 sh_eth_tsu_purge_mcast(ndev);
2715 ecmr_bits &= ~ECMR_MCT;
2716 mcast_all = 1;
2717 }
2718 }
2719 }
2720 }
2721
2722 /* update the ethernet mode */
2723 sh_eth_write(ndev, ecmr_bits, ECMR);
2724
2725 spin_unlock_irqrestore(&mdp->lock, flags);
2726 }
2727
2728 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2729 {
2730 if (!mdp->port)
2731 return TSU_VTAG0;
2732 else
2733 return TSU_VTAG1;
2734 }
2735
2736 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2737 __be16 proto, u16 vid)
2738 {
2739 struct sh_eth_private *mdp = netdev_priv(ndev);
2740 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2741
2742 if (unlikely(!mdp->cd->tsu))
2743 return -EPERM;
2744
2745 /* No filtering if vid = 0 */
2746 if (!vid)
2747 return 0;
2748
2749 mdp->vlan_num_ids++;
2750
2751 /* The controller has one VLAN tag HW filter. So, if the filter is
2752 * already enabled, the driver disables it and the filte
2753 */
2754 if (mdp->vlan_num_ids > 1) {
2755 /* disable VLAN filter */
2756 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2757 return 0;
2758 }
2759
2760 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2761 vtag_reg_index);
2762
2763 return 0;
2764 }
2765
2766 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2767 __be16 proto, u16 vid)
2768 {
2769 struct sh_eth_private *mdp = netdev_priv(ndev);
2770 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2771
2772 if (unlikely(!mdp->cd->tsu))
2773 return -EPERM;
2774
2775 /* No filtering if vid = 0 */
2776 if (!vid)
2777 return 0;
2778
2779 mdp->vlan_num_ids--;
2780 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2781
2782 return 0;
2783 }
2784
2785 /* SuperH's TSU register init function */
2786 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2787 {
2788 if (sh_eth_is_rz_fast_ether(mdp)) {
2789 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2790 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2791 TSU_FWSLC); /* Enable POST registers */
2792 return;
2793 }
2794
2795 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2796 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2797 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2798 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2799 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2800 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2801 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2802 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2803 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2804 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2805 if (sh_eth_is_gether(mdp)) {
2806 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2807 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2808 } else {
2809 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2810 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2811 }
2812 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2813 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2814 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2815 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2816 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2817 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2818 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2819 }
2820
2821 /* MDIO bus release function */
2822 static int sh_mdio_release(struct sh_eth_private *mdp)
2823 {
2824 /* unregister mdio bus */
2825 mdiobus_unregister(mdp->mii_bus);
2826
2827 /* free bitbang info */
2828 free_mdio_bitbang(mdp->mii_bus);
2829
2830 return 0;
2831 }
2832
2833 /* MDIO bus init function */
2834 static int sh_mdio_init(struct sh_eth_private *mdp,
2835 struct sh_eth_plat_data *pd)
2836 {
2837 int ret;
2838 struct bb_info *bitbang;
2839 struct platform_device *pdev = mdp->pdev;
2840 struct device *dev = &mdp->pdev->dev;
2841
2842 /* create bit control struct for PHY */
2843 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2844 if (!bitbang)
2845 return -ENOMEM;
2846
2847 /* bitbang init */
2848 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2849 bitbang->set_gate = pd->set_mdio_gate;
2850 bitbang->ctrl.ops = &bb_ops;
2851
2852 /* MII controller setting */
2853 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2854 if (!mdp->mii_bus)
2855 return -ENOMEM;
2856
2857 /* Hook up MII support for ethtool */
2858 mdp->mii_bus->name = "sh_mii";
2859 mdp->mii_bus->parent = dev;
2860 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2861 pdev->name, pdev->id);
2862
2863 /* register MDIO bus */
2864 if (dev->of_node) {
2865 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2866 } else {
2867 if (pd->phy_irq > 0)
2868 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2869
2870 ret = mdiobus_register(mdp->mii_bus);
2871 }
2872
2873 if (ret)
2874 goto out_free_bus;
2875
2876 return 0;
2877
2878 out_free_bus:
2879 free_mdio_bitbang(mdp->mii_bus);
2880 return ret;
2881 }
2882
2883 static const u16 *sh_eth_get_register_offset(int register_type)
2884 {
2885 const u16 *reg_offset = NULL;
2886
2887 switch (register_type) {
2888 case SH_ETH_REG_GIGABIT:
2889 reg_offset = sh_eth_offset_gigabit;
2890 break;
2891 case SH_ETH_REG_FAST_RZ:
2892 reg_offset = sh_eth_offset_fast_rz;
2893 break;
2894 case SH_ETH_REG_FAST_RCAR:
2895 reg_offset = sh_eth_offset_fast_rcar;
2896 break;
2897 case SH_ETH_REG_FAST_SH4:
2898 reg_offset = sh_eth_offset_fast_sh4;
2899 break;
2900 case SH_ETH_REG_FAST_SH3_SH2:
2901 reg_offset = sh_eth_offset_fast_sh3_sh2;
2902 break;
2903 }
2904
2905 return reg_offset;
2906 }
2907
2908 static const struct net_device_ops sh_eth_netdev_ops = {
2909 .ndo_open = sh_eth_open,
2910 .ndo_stop = sh_eth_close,
2911 .ndo_start_xmit = sh_eth_start_xmit,
2912 .ndo_get_stats = sh_eth_get_stats,
2913 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2914 .ndo_tx_timeout = sh_eth_tx_timeout,
2915 .ndo_do_ioctl = sh_eth_do_ioctl,
2916 .ndo_validate_addr = eth_validate_addr,
2917 .ndo_set_mac_address = eth_mac_addr,
2918 };
2919
2920 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2921 .ndo_open = sh_eth_open,
2922 .ndo_stop = sh_eth_close,
2923 .ndo_start_xmit = sh_eth_start_xmit,
2924 .ndo_get_stats = sh_eth_get_stats,
2925 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2926 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2927 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2928 .ndo_tx_timeout = sh_eth_tx_timeout,
2929 .ndo_do_ioctl = sh_eth_do_ioctl,
2930 .ndo_validate_addr = eth_validate_addr,
2931 .ndo_set_mac_address = eth_mac_addr,
2932 };
2933
2934 #ifdef CONFIG_OF
2935 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2936 {
2937 struct device_node *np = dev->of_node;
2938 struct sh_eth_plat_data *pdata;
2939 const char *mac_addr;
2940
2941 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2942 if (!pdata)
2943 return NULL;
2944
2945 pdata->phy_interface = of_get_phy_mode(np);
2946
2947 mac_addr = of_get_mac_address(np);
2948 if (mac_addr)
2949 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2950
2951 pdata->no_ether_link =
2952 of_property_read_bool(np, "renesas,no-ether-link");
2953 pdata->ether_link_active_low =
2954 of_property_read_bool(np, "renesas,ether-link-active-low");
2955
2956 return pdata;
2957 }
2958
2959 static const struct of_device_id sh_eth_match_table[] = {
2960 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2961 { .compatible = "renesas,ether-r8a7743", .data = &r8a779x_data },
2962 { .compatible = "renesas,ether-r8a7745", .data = &r8a779x_data },
2963 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2964 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2965 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2966 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2967 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2968 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2969 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2970 { }
2971 };
2972 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2973 #else
2974 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2975 {
2976 return NULL;
2977 }
2978 #endif
2979
2980 static int sh_eth_drv_probe(struct platform_device *pdev)
2981 {
2982 struct resource *res;
2983 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2984 const struct platform_device_id *id = platform_get_device_id(pdev);
2985 struct sh_eth_private *mdp;
2986 struct net_device *ndev;
2987 int ret, devno;
2988
2989 /* get base addr */
2990 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2991
2992 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2993 if (!ndev)
2994 return -ENOMEM;
2995
2996 pm_runtime_enable(&pdev->dev);
2997 pm_runtime_get_sync(&pdev->dev);
2998
2999 devno = pdev->id;
3000 if (devno < 0)
3001 devno = 0;
3002
3003 ret = platform_get_irq(pdev, 0);
3004 if (ret < 0)
3005 goto out_release;
3006 ndev->irq = ret;
3007
3008 SET_NETDEV_DEV(ndev, &pdev->dev);
3009
3010 mdp = netdev_priv(ndev);
3011 mdp->num_tx_ring = TX_RING_SIZE;
3012 mdp->num_rx_ring = RX_RING_SIZE;
3013 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3014 if (IS_ERR(mdp->addr)) {
3015 ret = PTR_ERR(mdp->addr);
3016 goto out_release;
3017 }
3018
3019 ndev->base_addr = res->start;
3020
3021 spin_lock_init(&mdp->lock);
3022 mdp->pdev = pdev;
3023
3024 if (pdev->dev.of_node)
3025 pd = sh_eth_parse_dt(&pdev->dev);
3026 if (!pd) {
3027 dev_err(&pdev->dev, "no platform data\n");
3028 ret = -EINVAL;
3029 goto out_release;
3030 }
3031
3032 /* get PHY ID */
3033 mdp->phy_id = pd->phy;
3034 mdp->phy_interface = pd->phy_interface;
3035 mdp->no_ether_link = pd->no_ether_link;
3036 mdp->ether_link_active_low = pd->ether_link_active_low;
3037
3038 /* set cpu data */
3039 if (id)
3040 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3041 else
3042 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3043
3044 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3045 if (!mdp->reg_offset) {
3046 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3047 mdp->cd->register_type);
3048 ret = -EINVAL;
3049 goto out_release;
3050 }
3051 sh_eth_set_default_cpu_data(mdp->cd);
3052
3053 /* set function */
3054 if (mdp->cd->tsu)
3055 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3056 else
3057 ndev->netdev_ops = &sh_eth_netdev_ops;
3058 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3059 ndev->watchdog_timeo = TX_TIMEOUT;
3060
3061 /* debug message level */
3062 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3063
3064 /* read and set MAC address */
3065 read_mac_address(ndev, pd->mac_addr);
3066 if (!is_valid_ether_addr(ndev->dev_addr)) {
3067 dev_warn(&pdev->dev,
3068 "no valid MAC address supplied, using a random one.\n");
3069 eth_hw_addr_random(ndev);
3070 }
3071
3072 /* ioremap the TSU registers */
3073 if (mdp->cd->tsu) {
3074 struct resource *rtsu;
3075 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3076 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3077 if (IS_ERR(mdp->tsu_addr)) {
3078 ret = PTR_ERR(mdp->tsu_addr);
3079 goto out_release;
3080 }
3081 mdp->port = devno % 2;
3082 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3083 }
3084
3085 /* initialize first or needed device */
3086 if (!devno || pd->needs_init) {
3087 if (mdp->cd->chip_reset)
3088 mdp->cd->chip_reset(ndev);
3089
3090 if (mdp->cd->tsu) {
3091 /* TSU init (Init only)*/
3092 sh_eth_tsu_init(mdp);
3093 }
3094 }
3095
3096 if (mdp->cd->rmiimode)
3097 sh_eth_write(ndev, 0x1, RMIIMODE);
3098
3099 /* MDIO bus init */
3100 ret = sh_mdio_init(mdp, pd);
3101 if (ret) {
3102 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3103 goto out_release;
3104 }
3105
3106 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3107
3108 /* network device register */
3109 ret = register_netdev(ndev);
3110 if (ret)
3111 goto out_napi_del;
3112
3113 /* print device information */
3114 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3115 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3116
3117 pm_runtime_put(&pdev->dev);
3118 platform_set_drvdata(pdev, ndev);
3119
3120 return ret;
3121
3122 out_napi_del:
3123 netif_napi_del(&mdp->napi);
3124 sh_mdio_release(mdp);
3125
3126 out_release:
3127 /* net_dev free */
3128 if (ndev)
3129 free_netdev(ndev);
3130
3131 pm_runtime_put(&pdev->dev);
3132 pm_runtime_disable(&pdev->dev);
3133 return ret;
3134 }
3135
3136 static int sh_eth_drv_remove(struct platform_device *pdev)
3137 {
3138 struct net_device *ndev = platform_get_drvdata(pdev);
3139 struct sh_eth_private *mdp = netdev_priv(ndev);
3140
3141 unregister_netdev(ndev);
3142 netif_napi_del(&mdp->napi);
3143 sh_mdio_release(mdp);
3144 pm_runtime_disable(&pdev->dev);
3145 free_netdev(ndev);
3146
3147 return 0;
3148 }
3149
3150 #ifdef CONFIG_PM
3151 #ifdef CONFIG_PM_SLEEP
3152 static int sh_eth_suspend(struct device *dev)
3153 {
3154 struct net_device *ndev = dev_get_drvdata(dev);
3155 int ret = 0;
3156
3157 if (netif_running(ndev)) {
3158 netif_device_detach(ndev);
3159 ret = sh_eth_close(ndev);
3160 }
3161
3162 return ret;
3163 }
3164
3165 static int sh_eth_resume(struct device *dev)
3166 {
3167 struct net_device *ndev = dev_get_drvdata(dev);
3168 int ret = 0;
3169
3170 if (netif_running(ndev)) {
3171 ret = sh_eth_open(ndev);
3172 if (ret < 0)
3173 return ret;
3174 netif_device_attach(ndev);
3175 }
3176
3177 return ret;
3178 }
3179 #endif
3180
3181 static int sh_eth_runtime_nop(struct device *dev)
3182 {
3183 /* Runtime PM callback shared between ->runtime_suspend()
3184 * and ->runtime_resume(). Simply returns success.
3185 *
3186 * This driver re-initializes all registers after
3187 * pm_runtime_get_sync() anyway so there is no need
3188 * to save and restore registers here.
3189 */
3190 return 0;
3191 }
3192
3193 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3194 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3195 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3196 };
3197 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3198 #else
3199 #define SH_ETH_PM_OPS NULL
3200 #endif
3201
3202 static struct platform_device_id sh_eth_id_table[] = {
3203 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3204 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3205 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3206 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3207 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3208 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3209 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3210 { }
3211 };
3212 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3213
3214 static struct platform_driver sh_eth_driver = {
3215 .probe = sh_eth_drv_probe,
3216 .remove = sh_eth_drv_remove,
3217 .id_table = sh_eth_id_table,
3218 .driver = {
3219 .name = CARDNAME,
3220 .pm = SH_ETH_PM_OPS,
3221 .of_match_table = of_match_ptr(sh_eth_match_table),
3222 },
3223 };
3224
3225 module_platform_driver(sh_eth_driver);
3226
3227 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3228 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3229 MODULE_LICENSE("GPL v2");
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