2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2012 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
26 #define CARDNAME "sh-eth"
27 #define TX_TIMEOUT (5*HZ)
28 #define TX_RING_SIZE 64 /* Tx ring size */
29 #define RX_RING_SIZE 64 /* Rx ring size */
30 #define TX_RING_MIN 64
31 #define RX_RING_MIN 64
32 #define TX_RING_MAX 1024
33 #define RX_RING_MAX 1024
35 #define PKT_BUF_SZ 1538
36 #define SH_ETH_TSU_TIMEOUT_MS 500
37 #define SH_ETH_TSU_CAM_ENTRIES 32
40 /* E-DMAC registers */
108 /* TSU Absolute address */
155 /* This value must be written at last. */
156 SH_ETH_MAX_REGISTER_OFFSET
,
159 /* Driver's parameters */
160 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
161 #define SH4_SKB_RX_ALIGN 32
163 #define SH2_SH3_SKB_RX_ALIGN 2
169 #if defined(CONFIG_CPU_SUBTYPE_SH7734) || defined(CONFIG_CPU_SUBTYPE_SH7763) ||\
170 defined(CONFIG_ARCH_R8A7740)
173 EDSR_ENT
= 0x01, EDSR_ENR
= 0x02,
175 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
179 GECMR_10
= 0x0, GECMR_100
= 0x04, GECMR_1000
= 0x01,
185 EDMR_EL
= 0x40, /* Litte endian */
186 EDMR_DL1
= 0x20, EDMR_DL0
= 0x10,
187 EDMR_SRST_GETHER
= 0x03,
188 EDMR_SRST_ETHER
= 0x01,
193 EDTRR_TRNS_GETHER
= 0x03,
194 EDTRR_TRNS_ETHER
= 0x01,
204 TPAUSER_TPAUSE
= 0x0000ffff,
205 TPAUSER_UNLIMITED
= 0,
210 BCFR_RPAUSE
= 0x0000ffff,
216 PIR_MDI
= 0x08, PIR_MDO
= 0x04, PIR_MMD
= 0x02, PIR_MDC
= 0x01,
220 enum PHY_STATUS_BIT
{ PHY_ST_LINK
= 0x01, };
224 EESR_TWB1
= 0x80000000,
225 EESR_TWB
= 0x40000000, /* same as TWB0 */
226 EESR_TC1
= 0x20000000,
227 EESR_TUC
= 0x10000000,
228 EESR_ROC
= 0x08000000,
229 EESR_TABT
= 0x04000000,
230 EESR_RABT
= 0x02000000,
231 EESR_RFRMER
= 0x01000000, /* same as RFCOF */
232 EESR_ADE
= 0x00800000,
233 EESR_ECI
= 0x00400000,
234 EESR_FTC
= 0x00200000, /* same as TC or TC0 */
235 EESR_TDE
= 0x00100000,
236 EESR_TFE
= 0x00080000, /* same as TFUF */
237 EESR_FRC
= 0x00040000, /* same as FR */
238 EESR_RDE
= 0x00020000,
239 EESR_RFE
= 0x00010000,
240 EESR_CND
= 0x00000800,
241 EESR_DLC
= 0x00000400,
242 EESR_CD
= 0x00000200,
243 EESR_RTO
= 0x00000100,
244 EESR_RMAF
= 0x00000080,
245 EESR_CEEF
= 0x00000040,
246 EESR_CELF
= 0x00000020,
247 EESR_RRF
= 0x00000010,
248 EESR_RTLF
= 0x00000008,
249 EESR_RTSF
= 0x00000004,
250 EESR_PRE
= 0x00000002,
251 EESR_CERF
= 0x00000001,
254 #define DEFAULT_TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
256 #define DEFAULT_EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
257 EESR_RDE | EESR_RFRMER | EESR_ADE | \
258 EESR_TFE | EESR_TDE | EESR_ECI)
259 #define DEFAULT_TX_ERROR_CHECK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
264 DMAC_M_TWB
= 0x40000000, DMAC_M_TABT
= 0x04000000,
265 DMAC_M_RABT
= 0x02000000,
266 DMAC_M_RFRMER
= 0x01000000, DMAC_M_ADF
= 0x00800000,
267 DMAC_M_ECI
= 0x00400000, DMAC_M_FTC
= 0x00200000,
268 DMAC_M_TDE
= 0x00100000, DMAC_M_TFE
= 0x00080000,
269 DMAC_M_FRC
= 0x00040000, DMAC_M_RDE
= 0x00020000,
270 DMAC_M_RFE
= 0x00010000, DMAC_M_TINT4
= 0x00000800,
271 DMAC_M_TINT3
= 0x00000400, DMAC_M_TINT2
= 0x00000200,
272 DMAC_M_TINT1
= 0x00000100, DMAC_M_RINT8
= 0x00000080,
273 DMAC_M_RINT5
= 0x00000010, DMAC_M_RINT4
= 0x00000008,
274 DMAC_M_RINT3
= 0x00000004, DMAC_M_RINT2
= 0x00000002,
275 DMAC_M_RINT1
= 0x00000001,
278 /* Receive descriptor bit */
280 RD_RACT
= 0x80000000, RD_RDEL
= 0x40000000,
281 RD_RFP1
= 0x20000000, RD_RFP0
= 0x10000000,
282 RD_RFE
= 0x08000000, RD_RFS10
= 0x00000200,
283 RD_RFS9
= 0x00000100, RD_RFS8
= 0x00000080,
284 RD_RFS7
= 0x00000040, RD_RFS6
= 0x00000020,
285 RD_RFS5
= 0x00000010, RD_RFS4
= 0x00000008,
286 RD_RFS3
= 0x00000004, RD_RFS2
= 0x00000002,
287 RD_RFS1
= 0x00000001,
289 #define RDF1ST RD_RFP1
290 #define RDFEND RD_RFP0
291 #define RD_RFP (RD_RFP1|RD_RFP0)
295 FCFTR_RFF2
= 0x00040000, FCFTR_RFF1
= 0x00020000,
296 FCFTR_RFF0
= 0x00010000, FCFTR_RFD2
= 0x00000004,
297 FCFTR_RFD1
= 0x00000002, FCFTR_RFD0
= 0x00000001,
299 #define DEFAULT_FIFO_F_D_RFF (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
300 #define DEFAULT_FIFO_F_D_RFD (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
302 /* Transfer descriptor bit */
304 TD_TACT
= 0x80000000,
305 TD_TDLE
= 0x40000000, TD_TFP1
= 0x20000000,
306 TD_TFP0
= 0x10000000,
308 #define TDF1ST TD_TFP1
309 #define TDFEND TD_TFP0
310 #define TD_TFP (TD_TFP1|TD_TFP0)
313 #define DEFAULT_RMCR_VALUE 0x00000000
316 enum FELIC_MODE_BIT
{
317 ECMR_TRCCM
= 0x04000000, ECMR_RCSC
= 0x00800000,
318 ECMR_DPAD
= 0x00200000, ECMR_RZPF
= 0x00100000,
319 ECMR_ZPF
= 0x00080000, ECMR_PFR
= 0x00040000, ECMR_RXF
= 0x00020000,
320 ECMR_TXF
= 0x00010000, ECMR_MCT
= 0x00002000, ECMR_PRCEF
= 0x00001000,
321 ECMR_PMDE
= 0x00000200, ECMR_RE
= 0x00000040, ECMR_TE
= 0x00000020,
322 ECMR_RTM
= 0x00000010, ECMR_ILB
= 0x00000008, ECMR_ELB
= 0x00000004,
323 ECMR_DM
= 0x00000002, ECMR_PRM
= 0x00000001,
327 enum ECSR_STATUS_BIT
{
328 ECSR_BRCRX
= 0x20, ECSR_PSRTO
= 0x10,
330 ECSR_MPD
= 0x02, ECSR_ICD
= 0x01,
333 #define DEFAULT_ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
334 ECSR_ICD | ECSIPR_MPDIP)
337 enum ECSIPR_STATUS_MASK_BIT
{
338 ECSIPR_BRCRXIP
= 0x20, ECSIPR_PSRTOIP
= 0x10,
339 ECSIPR_LCHNGIP
= 0x04,
340 ECSIPR_MPDIP
= 0x02, ECSIPR_ICDIP
= 0x01,
343 #define DEFAULT_ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
344 ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
358 DESC_I_TINT4
= 0x0800, DESC_I_TINT3
= 0x0400, DESC_I_TINT2
= 0x0200,
359 DESC_I_TINT1
= 0x0100, DESC_I_RINT8
= 0x0080, DESC_I_RINT5
= 0x0010,
360 DESC_I_RINT4
= 0x0008, DESC_I_RINT3
= 0x0004, DESC_I_RINT2
= 0x0002,
361 DESC_I_RINT1
= 0x0001,
366 RPADIR_PADS1
= 0x20000, RPADIR_PADS0
= 0x10000,
367 RPADIR_PADR
= 0x0003f,
371 #define DEFAULT_FDR_INIT 0x00000707
374 enum ARSTR_BIT
{ ARSTR_ARSTR
= 0x00000001, };
378 TSU_FWEN0_0
= 0x00000001,
382 enum TSU_ADSBSY_BIT
{
383 TSU_ADSBSY_0
= 0x00000001,
388 TSU_TEN_0
= 0x80000000,
393 TSU_FWSL0_FW50
= 0x1000, TSU_FWSL0_FW40
= 0x0800,
394 TSU_FWSL0_FW30
= 0x0400, TSU_FWSL0_FW20
= 0x0200,
395 TSU_FWSL0_FW10
= 0x0100, TSU_FWSL0_RMSA0
= 0x0010,
400 TSU_FWSLC_POSTENU
= 0x2000, TSU_FWSLC_POSTENL
= 0x1000,
401 TSU_FWSLC_CAMSEL03
= 0x0080, TSU_FWSLC_CAMSEL02
= 0x0040,
402 TSU_FWSLC_CAMSEL01
= 0x0020, TSU_FWSLC_CAMSEL00
= 0x0010,
403 TSU_FWSLC_CAMSEL13
= 0x0008, TSU_FWSLC_CAMSEL12
= 0x0004,
404 TSU_FWSLC_CAMSEL11
= 0x0002, TSU_FWSLC_CAMSEL10
= 0x0001,
408 #define TSU_VTAG_ENABLE 0x80000000
409 #define TSU_VTAG_VID_MASK 0x00000fff
412 * The sh ether Tx buffer descriptors.
413 * This structure should be 20 bytes.
415 struct sh_eth_txdesc
{
416 u32 status
; /* TD0 */
417 #if defined(__LITTLE_ENDIAN)
419 u16 buffer_length
; /* TD1 */
421 u16 buffer_length
; /* TD1 */
425 u32 pad1
; /* padding data */
426 } __attribute__((aligned(2), packed
));
429 * The sh ether Rx buffer descriptors.
430 * This structure should be 20 bytes.
432 struct sh_eth_rxdesc
{
433 u32 status
; /* RD0 */
434 #if defined(__LITTLE_ENDIAN)
435 u16 frame_length
; /* RD1 */
436 u16 buffer_length
; /* RD1 */
438 u16 buffer_length
; /* RD1 */
439 u16 frame_length
; /* RD1 */
442 u32 pad0
; /* padding data */
443 } __attribute__((aligned(2), packed
));
445 /* This structure is used by each CPU dependency handling. */
446 struct sh_eth_cpu_data
{
447 /* optional functions */
448 void (*chip_reset
)(struct net_device
*ndev
);
449 void (*set_duplex
)(struct net_device
*ndev
);
450 void (*set_rate
)(struct net_device
*ndev
);
452 /* mandatory initialize value */
453 unsigned long eesipr_value
;
455 /* optional initialize value */
456 unsigned long ecsr_value
;
457 unsigned long ecsipr_value
;
458 unsigned long fdr_value
;
459 unsigned long fcftr_value
;
460 unsigned long rpadir_value
;
461 unsigned long rmcr_value
;
463 /* interrupt checking mask */
464 unsigned long tx_check
;
465 unsigned long eesr_err_check
;
466 unsigned long tx_error_check
;
468 /* hardware features */
469 unsigned no_psr
:1; /* EtherC DO NOT have PSR */
470 unsigned apr
:1; /* EtherC have APR */
471 unsigned mpr
:1; /* EtherC have MPR */
472 unsigned tpauser
:1; /* EtherC have TPAUSER */
473 unsigned bculr
:1; /* EtherC have BCULR */
474 unsigned tsu
:1; /* EtherC have TSU */
475 unsigned hw_swap
:1; /* E-DMAC have DE bit in EDMR */
476 unsigned rpadir
:1; /* E-DMAC have RPADIR */
477 unsigned no_trimd
:1; /* E-DMAC DO NOT have TRIMD */
478 unsigned no_ade
:1; /* E-DMAC DO NOT have ADE bit in EESR */
479 unsigned hw_crc
:1; /* E-DMAC have CSMR */
480 unsigned select_mii
:1; /* EtherC have RMII_MII (MII select register) */
483 struct sh_eth_private
{
484 struct platform_device
*pdev
;
485 struct sh_eth_cpu_data
*cd
;
486 const u16
*reg_offset
;
488 void __iomem
*tsu_addr
;
491 dma_addr_t rx_desc_dma
;
492 dma_addr_t tx_desc_dma
;
493 struct sh_eth_rxdesc
*rx_ring
;
494 struct sh_eth_txdesc
*tx_ring
;
495 struct sk_buff
**rx_skbuff
;
496 struct sk_buff
**tx_skbuff
;
498 u32 cur_rx
, dirty_rx
; /* Producer/consumer ring indices */
499 u32 cur_tx
, dirty_tx
;
500 u32 rx_buf_sz
; /* Based on MTU+slack. */
502 /* MII transceiver section. */
503 u32 phy_id
; /* PHY ID */
504 struct mii_bus
*mii_bus
; /* MDIO bus control */
505 struct phy_device
*phydev
; /* PHY device control */
507 phy_interface_t phy_interface
;
511 int port
; /* for TSU */
512 int vlan_num_ids
; /* for VLAN tag filter */
514 unsigned no_ether_link
:1;
515 unsigned ether_link_active_low
:1;
518 static inline void sh_eth_soft_swap(char *src
, int len
)
520 #ifdef __LITTLE_ENDIAN__
523 maxp
= p
+ ((len
+ sizeof(u32
) - 1) / sizeof(u32
));
525 for (; p
< maxp
; p
++)
530 static inline void sh_eth_write(struct net_device
*ndev
, unsigned long data
,
533 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
535 iowrite32(data
, mdp
->addr
+ mdp
->reg_offset
[enum_index
]);
538 static inline unsigned long sh_eth_read(struct net_device
*ndev
,
541 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
543 return ioread32(mdp
->addr
+ mdp
->reg_offset
[enum_index
]);
546 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private
*mdp
,
549 return mdp
->tsu_addr
+ mdp
->reg_offset
[enum_index
];
552 static inline void sh_eth_tsu_write(struct sh_eth_private
*mdp
,
553 unsigned long data
, int enum_index
)
555 iowrite32(data
, mdp
->tsu_addr
+ mdp
->reg_offset
[enum_index
]);
558 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private
*mdp
,
561 return ioread32(mdp
->tsu_addr
+ mdp
->reg_offset
[enum_index
]);
564 #endif /* #ifndef __SH_ETH_H__ */