1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_vlan.h>
20 #include <linux/timer.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/mutex.h>
28 #include <linux/rwsem.h>
29 #include <linux/vmalloc.h>
30 #include <linux/i2c.h>
31 #include <linux/mtd/mtd.h>
32 #include <net/busy_poll.h>
38 /**************************************************************************
42 **************************************************************************/
44 #define EFX_DRIVER_VERSION "4.1"
47 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
50 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
51 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
54 /**************************************************************************
58 **************************************************************************/
60 #define EFX_MAX_CHANNELS 32U
61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
62 #define EFX_EXTRA_CHANNEL_IOV 0
63 #define EFX_EXTRA_CHANNEL_PTP 1
64 #define EFX_MAX_EXTRA_CHANNELS 2U
66 /* Checksum generation is a per-queue option in hardware, so each
67 * queue visible to the networking core is backed by two hardware TX
69 #define EFX_MAX_TX_TC 2
70 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
71 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
72 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
73 #define EFX_TXQ_TYPES 4
74 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
76 /* Maximum possible MTU the driver supports */
77 #define EFX_MAX_MTU (9 * 1024)
79 /* Minimum MTU, from RFC791 (IP) */
80 #define EFX_MIN_MTU 68
82 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
83 * and should be a multiple of the cache line size.
85 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
87 /* If possible, we should ensure cache line alignment at start and end
88 * of every buffer. Otherwise, we just need to ensure 4-byte
89 * alignment of the network header.
92 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
94 #define EFX_RX_BUF_ALIGNMENT 4
97 /* Forward declare Precision Time Protocol (PTP) support structure. */
99 struct hwtstamp_config
;
101 struct efx_self_tests
;
104 * struct efx_buffer - A general-purpose DMA buffer
105 * @addr: host base address of the buffer
106 * @dma_addr: DMA base address of the buffer
107 * @len: Buffer length, in bytes
109 * The NIC uses these buffers for its interrupt status registers and
119 * struct efx_special_buffer - DMA buffer entered into buffer table
120 * @buf: Standard &struct efx_buffer
121 * @index: Buffer index within controller;s buffer table
122 * @entries: Number of buffer table entries
124 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
125 * Event and descriptor rings are addressed via one or more buffer
126 * table entries (and so can be physically non-contiguous, although we
127 * currently do not take advantage of that). On Falcon and Siena we
128 * have to take care of allocating and initialising the entries
129 * ourselves. On later hardware this is managed by the firmware and
130 * @index and @entries are left as 0.
132 struct efx_special_buffer
{
133 struct efx_buffer buf
;
135 unsigned int entries
;
139 * struct efx_tx_buffer - buffer state for a TX descriptor
140 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
141 * freed when descriptor completes
142 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
143 * @dma_addr: DMA address of the fragment.
144 * @flags: Flags for allocation and DMA mapping type
145 * @len: Length of this fragment.
146 * This field is zero when the queue slot is empty.
147 * @unmap_len: Length of this fragment to unmap
148 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
149 * Only valid if @unmap_len != 0.
151 struct efx_tx_buffer
{
152 const struct sk_buff
*skb
;
157 unsigned short flags
;
159 unsigned short unmap_len
;
160 unsigned short dma_offset
;
162 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
163 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
164 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
165 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
168 * struct efx_tx_queue - An Efx TX queue
170 * This is a ring buffer of TX fragments.
171 * Since the TX completion path always executes on the same
172 * CPU and the xmit path can operate on different CPUs,
173 * performance is increased by ensuring that the completion
174 * path and the xmit path operate on different cache lines.
175 * This is particularly important if the xmit path is always
176 * executing on one CPU which is different from the completion
177 * path. There is also a cache line for members which are
178 * read but not written on the fast path.
180 * @efx: The associated Efx NIC
181 * @queue: DMA queue number
182 * @tso_version: Version of TSO in use for this queue.
183 * @channel: The associated channel
184 * @core_txq: The networking core TX queue structure
185 * @buffer: The software buffer ring
186 * @cb_page: Array of pages of copy buffers. Carved up according to
187 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
188 * @txd: The hardware descriptor ring
189 * @ptr_mask: The size of the ring minus 1.
190 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
191 * Size of the region is efx_piobuf_size.
192 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
193 * @initialised: Has hardware queue been initialised?
194 * @handle_tso: TSO xmit preparation handler. Sets up the TSO metadata and
195 * may also map tx data, depending on the nature of the TSO implementation.
196 * @read_count: Current read pointer.
197 * This is the number of buffers that have been removed from both rings.
198 * @old_write_count: The value of @write_count when last checked.
199 * This is here for performance reasons. The xmit path will
200 * only get the up-to-date value of @write_count if this
201 * variable indicates that the queue is empty. This is to
202 * avoid cache-line ping-pong between the xmit path and the
204 * @merge_events: Number of TX merged completion events
205 * @insert_count: Current insert pointer
206 * This is the number of buffers that have been added to the
208 * @write_count: Current write pointer
209 * This is the number of buffers that have been added to the
211 * @old_read_count: The value of read_count when last checked.
212 * This is here for performance reasons. The xmit path will
213 * only get the up-to-date value of read_count if this
214 * variable indicates that the queue is full. This is to
215 * avoid cache-line ping-pong between the xmit path and the
217 * @tso_bursts: Number of times TSO xmit invoked by kernel
218 * @tso_long_headers: Number of packets with headers too long for standard
220 * @tso_packets: Number of packets via the TSO xmit path
221 * @tso_fallbacks: Number of times TSO fallback used
222 * @pushes: Number of times the TX push feature has been used
223 * @pio_packets: Number of times the TX PIO feature has been used
224 * @xmit_more_available: Are any packets waiting to be pushed to the NIC
225 * @cb_packets: Number of times the TX copybreak feature has been used
226 * @empty_read_count: If the completion path has seen the queue as empty
227 * and the transmission path has not yet checked this, the value of
228 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
230 struct efx_tx_queue
{
231 /* Members which don't change on the fast path */
232 struct efx_nic
*efx ____cacheline_aligned_in_smp
;
234 unsigned int tso_version
;
235 struct efx_channel
*channel
;
236 struct netdev_queue
*core_txq
;
237 struct efx_tx_buffer
*buffer
;
238 struct efx_buffer
*cb_page
;
239 struct efx_special_buffer txd
;
240 unsigned int ptr_mask
;
241 void __iomem
*piobuf
;
242 unsigned int piobuf_offset
;
245 /* Function pointers used in the fast path. */
246 int (*handle_tso
)(struct efx_tx_queue
*, struct sk_buff
*, bool *);
248 /* Members used mainly on the completion path */
249 unsigned int read_count ____cacheline_aligned_in_smp
;
250 unsigned int old_write_count
;
251 unsigned int merge_events
;
252 unsigned int bytes_compl
;
253 unsigned int pkts_compl
;
255 /* Members used only on the xmit path */
256 unsigned int insert_count ____cacheline_aligned_in_smp
;
257 unsigned int write_count
;
258 unsigned int old_read_count
;
259 unsigned int tso_bursts
;
260 unsigned int tso_long_headers
;
261 unsigned int tso_packets
;
262 unsigned int tso_fallbacks
;
264 unsigned int pio_packets
;
265 bool xmit_more_available
;
266 unsigned int cb_packets
;
267 /* Statistics to supplement MAC stats */
268 unsigned long tx_packets
;
270 /* Members shared between paths and sometimes updated */
271 unsigned int empty_read_count ____cacheline_aligned_in_smp
;
272 #define EFX_EMPTY_COUNT_VALID 0x80000000
273 atomic_t flush_outstanding
;
276 #define EFX_TX_CB_ORDER 7
277 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
280 * struct efx_rx_buffer - An Efx RX data buffer
281 * @dma_addr: DMA base address of the buffer
282 * @page: The associated page buffer.
283 * Will be %NULL if the buffer slot is currently free.
284 * @page_offset: If pending: offset in @page of DMA base address.
285 * If completed: offset in @page of Ethernet header.
286 * @len: If pending: length for DMA descriptor.
287 * If completed: received length, excluding hash prefix.
288 * @flags: Flags for buffer and packet state. These are only set on the
289 * first buffer of a scattered packet.
291 struct efx_rx_buffer
{
298 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
299 #define EFX_RX_PKT_CSUMMED 0x0002
300 #define EFX_RX_PKT_DISCARD 0x0004
301 #define EFX_RX_PKT_TCP 0x0040
302 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
305 * struct efx_rx_page_state - Page-based rx buffer state
307 * Inserted at the start of every page allocated for receive buffers.
308 * Used to facilitate sharing dma mappings between recycled rx buffers
309 * and those passed up to the kernel.
311 * @dma_addr: The dma address of this page.
313 struct efx_rx_page_state
{
316 unsigned int __pad
[0] ____cacheline_aligned
;
320 * struct efx_rx_queue - An Efx RX queue
321 * @efx: The associated Efx NIC
322 * @core_index: Index of network core RX queue. Will be >= 0 iff this
323 * is associated with a real RX queue.
324 * @buffer: The software buffer ring
325 * @rxd: The hardware descriptor ring
326 * @ptr_mask: The size of the ring minus 1.
327 * @refill_enabled: Enable refill whenever fill level is low
328 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
329 * @rxq_flush_pending.
330 * @added_count: Number of buffers added to the receive queue.
331 * @notified_count: Number of buffers given to NIC (<= @added_count).
332 * @removed_count: Number of buffers removed from the receive queue.
333 * @scatter_n: Used by NIC specific receive code.
334 * @scatter_len: Used by NIC specific receive code.
335 * @page_ring: The ring to store DMA mapped pages for reuse.
336 * @page_add: Counter to calculate the write pointer for the recycle ring.
337 * @page_remove: Counter to calculate the read pointer for the recycle ring.
338 * @page_recycle_count: The number of pages that have been recycled.
339 * @page_recycle_failed: The number of pages that couldn't be recycled because
340 * the kernel still held a reference to them.
341 * @page_recycle_full: The number of pages that were released because the
342 * recycle ring was full.
343 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
344 * @max_fill: RX descriptor maximum fill level (<= ring size)
345 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
347 * @min_fill: RX descriptor minimum non-zero fill level.
348 * This records the minimum fill level observed when a ring
349 * refill was triggered.
350 * @recycle_count: RX buffer recycle counter.
351 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
353 struct efx_rx_queue
{
356 struct efx_rx_buffer
*buffer
;
357 struct efx_special_buffer rxd
;
358 unsigned int ptr_mask
;
362 unsigned int added_count
;
363 unsigned int notified_count
;
364 unsigned int removed_count
;
365 unsigned int scatter_n
;
366 unsigned int scatter_len
;
367 struct page
**page_ring
;
368 unsigned int page_add
;
369 unsigned int page_remove
;
370 unsigned int page_recycle_count
;
371 unsigned int page_recycle_failed
;
372 unsigned int page_recycle_full
;
373 unsigned int page_ptr_mask
;
374 unsigned int max_fill
;
375 unsigned int fast_fill_trigger
;
376 unsigned int min_fill
;
377 unsigned int min_overfill
;
378 unsigned int recycle_count
;
379 struct timer_list slow_fill
;
380 unsigned int slow_fill_count
;
381 /* Statistics to supplement MAC stats */
382 unsigned long rx_packets
;
385 enum efx_sync_events_state
{
386 SYNC_EVENTS_DISABLED
= 0,
387 SYNC_EVENTS_QUIESCENT
,
388 SYNC_EVENTS_REQUESTED
,
393 * struct efx_channel - An Efx channel
395 * A channel comprises an event queue, at least one TX queue, at least
396 * one RX queue, and an associated tasklet for processing the event
399 * @efx: Associated Efx NIC
400 * @channel: Channel instance number
401 * @type: Channel type definition
402 * @eventq_init: Event queue initialised flag
403 * @enabled: Channel enabled indicator
404 * @irq: IRQ number (MSI and MSI-X only)
405 * @irq_moderation_us: IRQ moderation value (in microseconds)
406 * @napi_dev: Net device used with NAPI
407 * @napi_str: NAPI control structure
408 * @state: state for NAPI vs busy polling
409 * @state_lock: lock protecting @state
410 * @eventq: Event queue buffer
411 * @eventq_mask: Event queue pointer mask
412 * @eventq_read_ptr: Event queue read pointer
413 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
414 * @irq_count: Number of IRQs since last adaptive moderation decision
415 * @irq_mod_score: IRQ moderation score
416 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
417 * indexed by filter ID
418 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
419 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
420 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
421 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
422 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
423 * @n_rx_overlength: Count of RX_OVERLENGTH errors
424 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
425 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
426 * lack of descriptors
427 * @n_rx_merge_events: Number of RX merged completion events
428 * @n_rx_merge_packets: Number of RX packets completed by merged events
429 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
430 * __efx_rx_packet(), or zero if there is none
431 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
432 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
433 * @rx_queue: RX queue for this channel
434 * @tx_queue: TX queues for this channel
435 * @sync_events_state: Current state of sync events on this channel
436 * @sync_timestamp_major: Major part of the last ptp sync event
437 * @sync_timestamp_minor: Minor part of the last ptp sync event
442 const struct efx_channel_type
*type
;
446 unsigned int irq_moderation_us
;
447 struct net_device
*napi_dev
;
448 struct napi_struct napi_str
;
449 #ifdef CONFIG_NET_RX_BUSY_POLL
450 unsigned long busy_poll_state
;
452 struct efx_special_buffer eventq
;
453 unsigned int eventq_mask
;
454 unsigned int eventq_read_ptr
;
457 unsigned int irq_count
;
458 unsigned int irq_mod_score
;
459 #ifdef CONFIG_RFS_ACCEL
460 unsigned int rfs_filters_added
;
461 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF
465 unsigned n_rx_tobe_disc
;
466 unsigned n_rx_ip_hdr_chksum_err
;
467 unsigned n_rx_tcp_udp_chksum_err
;
468 unsigned n_rx_mcast_mismatch
;
469 unsigned n_rx_frm_trunc
;
470 unsigned n_rx_overlength
;
471 unsigned n_skbuff_leaks
;
472 unsigned int n_rx_nodesc_trunc
;
473 unsigned int n_rx_merge_events
;
474 unsigned int n_rx_merge_packets
;
476 unsigned int rx_pkt_n_frags
;
477 unsigned int rx_pkt_index
;
479 struct efx_rx_queue rx_queue
;
480 struct efx_tx_queue tx_queue
[EFX_TXQ_TYPES
];
482 enum efx_sync_events_state sync_events_state
;
483 u32 sync_timestamp_major
;
484 u32 sync_timestamp_minor
;
487 #ifdef CONFIG_NET_RX_BUSY_POLL
488 enum efx_channel_busy_poll_state
{
489 EFX_CHANNEL_STATE_IDLE
= 0,
490 EFX_CHANNEL_STATE_NAPI
= BIT(0),
491 EFX_CHANNEL_STATE_NAPI_REQ_BIT
= 1,
492 EFX_CHANNEL_STATE_NAPI_REQ
= BIT(1),
493 EFX_CHANNEL_STATE_POLL_BIT
= 2,
494 EFX_CHANNEL_STATE_POLL
= BIT(2),
495 EFX_CHANNEL_STATE_DISABLE_BIT
= 3,
498 static inline void efx_channel_busy_poll_init(struct efx_channel
*channel
)
500 WRITE_ONCE(channel
->busy_poll_state
, EFX_CHANNEL_STATE_IDLE
);
503 /* Called from the device poll routine to get ownership of a channel. */
504 static inline bool efx_channel_lock_napi(struct efx_channel
*channel
)
506 unsigned long prev
, old
= READ_ONCE(channel
->busy_poll_state
);
510 case EFX_CHANNEL_STATE_POLL
:
511 /* Ensure efx_channel_try_lock_poll() wont starve us */
512 set_bit(EFX_CHANNEL_STATE_NAPI_REQ_BIT
,
513 &channel
->busy_poll_state
);
515 case EFX_CHANNEL_STATE_POLL
| EFX_CHANNEL_STATE_NAPI_REQ
:
520 prev
= cmpxchg(&channel
->busy_poll_state
, old
,
521 EFX_CHANNEL_STATE_NAPI
);
522 if (unlikely(prev
!= old
)) {
523 /* This is likely to mean we've just entered polling
524 * state. Go back round to set the REQ bit.
533 static inline void efx_channel_unlock_napi(struct efx_channel
*channel
)
535 /* Make sure write has completed from efx_channel_lock_napi() */
537 WRITE_ONCE(channel
->busy_poll_state
, EFX_CHANNEL_STATE_IDLE
);
540 /* Called from efx_busy_poll(). */
541 static inline bool efx_channel_try_lock_poll(struct efx_channel
*channel
)
543 return cmpxchg(&channel
->busy_poll_state
, EFX_CHANNEL_STATE_IDLE
,
544 EFX_CHANNEL_STATE_POLL
) == EFX_CHANNEL_STATE_IDLE
;
547 static inline void efx_channel_unlock_poll(struct efx_channel
*channel
)
549 clear_bit_unlock(EFX_CHANNEL_STATE_POLL_BIT
, &channel
->busy_poll_state
);
552 static inline bool efx_channel_busy_polling(struct efx_channel
*channel
)
554 return test_bit(EFX_CHANNEL_STATE_POLL_BIT
, &channel
->busy_poll_state
);
557 static inline void efx_channel_enable(struct efx_channel
*channel
)
559 clear_bit_unlock(EFX_CHANNEL_STATE_DISABLE_BIT
,
560 &channel
->busy_poll_state
);
563 /* Stop further polling or napi access.
564 * Returns false if the channel is currently busy polling.
566 static inline bool efx_channel_disable(struct efx_channel
*channel
)
568 set_bit(EFX_CHANNEL_STATE_DISABLE_BIT
, &channel
->busy_poll_state
);
569 /* Implicit barrier in efx_channel_busy_polling() */
570 return !efx_channel_busy_polling(channel
);
573 #else /* CONFIG_NET_RX_BUSY_POLL */
575 static inline void efx_channel_busy_poll_init(struct efx_channel
*channel
)
579 static inline bool efx_channel_lock_napi(struct efx_channel
*channel
)
584 static inline void efx_channel_unlock_napi(struct efx_channel
*channel
)
588 static inline bool efx_channel_try_lock_poll(struct efx_channel
*channel
)
593 static inline void efx_channel_unlock_poll(struct efx_channel
*channel
)
597 static inline bool efx_channel_busy_polling(struct efx_channel
*channel
)
602 static inline void efx_channel_enable(struct efx_channel
*channel
)
606 static inline bool efx_channel_disable(struct efx_channel
*channel
)
610 #endif /* CONFIG_NET_RX_BUSY_POLL */
613 * struct efx_msi_context - Context for each MSI
614 * @efx: The associated NIC
615 * @index: Index of the channel/IRQ
616 * @name: Name of the channel/IRQ
618 * Unlike &struct efx_channel, this is never reallocated and is always
619 * safe for the IRQ handler to access.
621 struct efx_msi_context
{
624 char name
[IFNAMSIZ
+ 6];
628 * struct efx_channel_type - distinguishes traffic and extra channels
629 * @handle_no_channel: Handle failure to allocate an extra channel
630 * @pre_probe: Set up extra state prior to initialisation
631 * @post_remove: Tear down extra state after finalisation, if allocated.
632 * May be called on channels that have not been probed.
633 * @get_name: Generate the channel's name (used for its IRQ handler)
634 * @copy: Copy the channel state prior to reallocation. May be %NULL if
635 * reallocation is not supported.
636 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
637 * @keep_eventq: Flag for whether event queue should be kept initialised
638 * while the device is stopped
640 struct efx_channel_type
{
641 void (*handle_no_channel
)(struct efx_nic
*);
642 int (*pre_probe
)(struct efx_channel
*);
643 void (*post_remove
)(struct efx_channel
*);
644 void (*get_name
)(struct efx_channel
*, char *buf
, size_t len
);
645 struct efx_channel
*(*copy
)(const struct efx_channel
*);
646 bool (*receive_skb
)(struct efx_channel
*, struct sk_buff
*);
656 #define STRING_TABLE_LOOKUP(val, member) \
657 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
659 extern const char *const efx_loopback_mode_names
[];
660 extern const unsigned int efx_loopback_mode_max
;
661 #define LOOPBACK_MODE(efx) \
662 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
664 extern const char *const efx_reset_type_names
[];
665 extern const unsigned int efx_reset_type_max
;
666 #define RESET_TYPE(type) \
667 STRING_TABLE_LOOKUP(type, efx_reset_type)
670 /* Be careful if altering to correct macro below */
671 EFX_INT_MODE_MSIX
= 0,
672 EFX_INT_MODE_MSI
= 1,
673 EFX_INT_MODE_LEGACY
= 2,
674 EFX_INT_MODE_MAX
/* Insert any new items before this */
676 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
679 STATE_UNINIT
= 0, /* device being probed/removed or is frozen */
680 STATE_READY
= 1, /* hardware ready and netdev registered */
681 STATE_DISABLED
= 2, /* device disabled due to hardware errors */
682 STATE_RECOVERY
= 3, /* device recovering from PCI error */
685 /* Forward declaration */
688 /* Pseudo bit-mask flow control field */
689 #define EFX_FC_RX FLOW_CTRL_RX
690 #define EFX_FC_TX FLOW_CTRL_TX
691 #define EFX_FC_AUTO 4
694 * struct efx_link_state - Current state of the link
696 * @fd: Link is full-duplex
697 * @fc: Actual flow control flags
698 * @speed: Link speed (Mbps)
700 struct efx_link_state
{
707 static inline bool efx_link_state_equal(const struct efx_link_state
*left
,
708 const struct efx_link_state
*right
)
710 return left
->up
== right
->up
&& left
->fd
== right
->fd
&&
711 left
->fc
== right
->fc
&& left
->speed
== right
->speed
;
715 * struct efx_phy_operations - Efx PHY operations table
716 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
717 * efx->loopback_modes.
718 * @init: Initialise PHY
719 * @fini: Shut down PHY
720 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
721 * @poll: Update @link_state and report whether it changed.
722 * Serialised by the mac_lock.
723 * @get_link_ksettings: Get ethtool settings. Serialised by the mac_lock.
724 * @set_link_ksettings: Set ethtool settings. Serialised by the mac_lock.
725 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
726 * (only needed where AN bit is set in mmds)
727 * @test_alive: Test that PHY is 'alive' (online)
728 * @test_name: Get the name of a PHY-specific test/result
729 * @run_tests: Run tests and record results as appropriate (offline).
730 * Flags are the ethtool tests flags.
732 struct efx_phy_operations
{
733 int (*probe
) (struct efx_nic
*efx
);
734 int (*init
) (struct efx_nic
*efx
);
735 void (*fini
) (struct efx_nic
*efx
);
736 void (*remove
) (struct efx_nic
*efx
);
737 int (*reconfigure
) (struct efx_nic
*efx
);
738 bool (*poll
) (struct efx_nic
*efx
);
739 void (*get_link_ksettings
)(struct efx_nic
*efx
,
740 struct ethtool_link_ksettings
*cmd
);
741 int (*set_link_ksettings
)(struct efx_nic
*efx
,
742 const struct ethtool_link_ksettings
*cmd
);
743 void (*set_npage_adv
) (struct efx_nic
*efx
, u32
);
744 int (*test_alive
) (struct efx_nic
*efx
);
745 const char *(*test_name
) (struct efx_nic
*efx
, unsigned int index
);
746 int (*run_tests
) (struct efx_nic
*efx
, int *results
, unsigned flags
);
747 int (*get_module_eeprom
) (struct efx_nic
*efx
,
748 struct ethtool_eeprom
*ee
,
750 int (*get_module_info
) (struct efx_nic
*efx
,
751 struct ethtool_modinfo
*modinfo
);
755 * enum efx_phy_mode - PHY operating mode flags
756 * @PHY_MODE_NORMAL: on and should pass traffic
757 * @PHY_MODE_TX_DISABLED: on with TX disabled
758 * @PHY_MODE_LOW_POWER: set to low power through MDIO
759 * @PHY_MODE_OFF: switched off through external control
760 * @PHY_MODE_SPECIAL: on but will not pass traffic
764 PHY_MODE_TX_DISABLED
= 1,
765 PHY_MODE_LOW_POWER
= 2,
767 PHY_MODE_SPECIAL
= 8,
770 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode
)
772 return !!(mode
& ~PHY_MODE_TX_DISABLED
);
776 * struct efx_hw_stat_desc - Description of a hardware statistic
777 * @name: Name of the statistic as visible through ethtool, or %NULL if
778 * it should not be exposed
779 * @dma_width: Width in bits (0 for non-DMA statistics)
780 * @offset: Offset within stats (ignored for non-DMA statistics)
782 struct efx_hw_stat_desc
{
788 /* Number of bits used in a multicast filter hash address */
789 #define EFX_MCAST_HASH_BITS 8
791 /* Number of (single-bit) entries in a multicast filter hash */
792 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
794 /* An Efx multicast filter hash */
795 union efx_multicast_hash
{
796 u8 byte
[EFX_MCAST_HASH_ENTRIES
/ 8];
797 efx_oword_t oword
[EFX_MCAST_HASH_ENTRIES
/ sizeof(efx_oword_t
) / 8];
803 * struct efx_nic - an Efx NIC
804 * @name: Device name (net device name or bus id before net device registered)
805 * @pci_dev: The PCI device
806 * @node: List node for maintaning primary/secondary function lists
807 * @primary: &struct efx_nic instance for the primary function of this
808 * controller. May be the same structure, and may be %NULL if no
809 * primary function is bound. Serialised by rtnl_lock.
810 * @secondary_list: List of &struct efx_nic instances for the secondary PCI
811 * functions of the controller, if this is for the primary function.
812 * Serialised by rtnl_lock.
813 * @type: Controller type attributes
814 * @legacy_irq: IRQ number
815 * @workqueue: Workqueue for port reconfigures and the HW monitor.
816 * Work items do not hold and must not acquire RTNL.
817 * @workqueue_name: Name of workqueue
818 * @reset_work: Scheduled reset workitem
819 * @membase_phys: Memory BAR value as physical address
820 * @membase: Memory BAR value
821 * @interrupt_mode: Interrupt mode
822 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
823 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds
824 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
825 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
826 * @irq_rx_moderation_us: IRQ moderation time for RX event queues
827 * @msg_enable: Log message enable flags
828 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
829 * @reset_pending: Bitmask for pending resets
830 * @tx_queue: TX DMA queues
831 * @rx_queue: RX DMA queues
833 * @msi_context: Context for each MSI
834 * @extra_channel_types: Types of extra (non-traffic) channels that
835 * should be allocated for this NIC
836 * @rxq_entries: Size of receive queues requested by user.
837 * @txq_entries: Size of transmit queues requested by user.
838 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
839 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
840 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
841 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
842 * @sram_lim_qw: Qword address limit of SRAM
843 * @next_buffer_table: First available buffer table id
844 * @n_channels: Number of channels in use
845 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
846 * @n_tx_channels: Number of channels used for TX
847 * @rx_ip_align: RX DMA address offset to have IP header aligned in
848 * in accordance with NET_IP_ALIGN
849 * @rx_dma_len: Current maximum RX DMA length
850 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
851 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
852 * for use in sk_buff::truesize
853 * @rx_prefix_size: Size of RX prefix before packet data
854 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
855 * (valid only if @rx_prefix_size != 0; always negative)
856 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
857 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
858 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
859 * (valid only if channel->sync_timestamps_enabled; always negative)
860 * @rx_hash_key: Toeplitz hash key for RSS
861 * @rx_indir_table: Indirection table for RSS
862 * @rx_scatter: Scatter mode enabled for receives
863 * @rss_active: RSS enabled on hardware
864 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
865 * @int_error_count: Number of internal errors seen recently
866 * @int_error_expire: Time at which error count will be expired
867 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
868 * acknowledge but do nothing else.
869 * @irq_status: Interrupt status buffer
870 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
871 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
872 * @selftest_work: Work item for asynchronous self-test
873 * @mtd_list: List of MTDs attached to the NIC
874 * @nic_data: Hardware dependent state
875 * @mcdi: Management-Controller-to-Driver Interface state
876 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
877 * efx_monitor() and efx_reconfigure_port()
878 * @port_enabled: Port enabled indicator.
879 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
880 * efx_mac_work() with kernel interfaces. Safe to read under any
881 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
882 * be held to modify it.
883 * @port_initialized: Port initialized?
884 * @net_dev: Operating system network device. Consider holding the rtnl lock
885 * @fixed_features: Features which cannot be turned off
886 * @stats_buffer: DMA buffer for statistics
887 * @phy_type: PHY type
888 * @phy_op: PHY interface
889 * @phy_data: PHY private data (including PHY-specific stats)
890 * @mdio: PHY MDIO interface
891 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
892 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
893 * @link_advertising: Autonegotiation advertising flags
894 * @link_state: Current state of the link
895 * @n_link_state_changes: Number of times the link has changed state
896 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
897 * Protected by @mac_lock.
898 * @multicast_hash: Multicast hash table for Falcon-arch.
899 * Protected by @mac_lock.
900 * @wanted_fc: Wanted flow control flags
901 * @fc_disable: When non-zero flow control is disabled. Typically used to
902 * ensure that network back pressure doesn't delay dma queue flushes.
903 * Serialised by the rtnl lock.
904 * @mac_work: Work item for changing MAC promiscuity and multicast hash
905 * @loopback_mode: Loopback status
906 * @loopback_modes: Supported loopback mode bitmask
907 * @loopback_selftest: Offline self-test private state
908 * @filter_sem: Filter table rw_semaphore, for freeing the table
909 * @filter_lock: Filter table lock, for mere content changes
910 * @filter_state: Architecture-dependent filter table state
911 * @rps_expire_channel: Next channel to check for expiry
912 * @rps_expire_index: Next index to check for expiry in
913 * @rps_expire_channel's @rps_flow_id
914 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
915 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
916 * Decremented when the efx_flush_rx_queue() is called.
917 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
918 * completed (either success or failure). Not used when MCDI is used to
919 * flush receive queues.
920 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
921 * @vf_count: Number of VFs intended to be enabled.
922 * @vf_init_count: Number of VFs that have been fully initialised.
923 * @vi_scale: log2 number of vnics per VF.
924 * @ptp_data: PTP state data
925 * @vpd_sn: Serial number read from VPD
926 * @monitor_work: Hardware monitor workitem
927 * @biu_lock: BIU (bus interface unit) lock
928 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
929 * field is used by efx_test_interrupts() to verify that an
930 * interrupt has occurred.
931 * @stats_lock: Statistics update lock. Must be held when calling
932 * efx_nic_type::{update,start,stop}_stats.
933 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
935 * This is stored in the private area of the &struct net_device.
938 /* The following fields should be written very rarely */
941 struct list_head node
;
942 struct efx_nic
*primary
;
943 struct list_head secondary_list
;
944 struct pci_dev
*pci_dev
;
945 unsigned int port_num
;
946 const struct efx_nic_type
*type
;
948 bool eeh_disabled_legacy_irq
;
949 struct workqueue_struct
*workqueue
;
950 char workqueue_name
[16];
951 struct work_struct reset_work
;
952 resource_size_t membase_phys
;
953 void __iomem
*membase
;
955 enum efx_int_mode interrupt_mode
;
956 unsigned int timer_quantum_ns
;
957 unsigned int timer_max_ns
;
958 bool irq_rx_adaptive
;
959 unsigned int irq_mod_step_us
;
960 unsigned int irq_rx_moderation_us
;
963 enum nic_state state
;
964 unsigned long reset_pending
;
966 struct efx_channel
*channel
[EFX_MAX_CHANNELS
];
967 struct efx_msi_context msi_context
[EFX_MAX_CHANNELS
];
968 const struct efx_channel_type
*
969 extra_channel_type
[EFX_MAX_EXTRA_CHANNELS
];
971 unsigned rxq_entries
;
972 unsigned txq_entries
;
973 unsigned int txq_stop_thresh
;
974 unsigned int txq_wake_thresh
;
978 unsigned sram_lim_qw
;
979 unsigned next_buffer_table
;
981 unsigned int max_channels
;
982 unsigned int max_tx_channels
;
984 unsigned n_rx_channels
;
986 unsigned tx_channel_offset
;
987 unsigned n_tx_channels
;
988 unsigned int rx_ip_align
;
989 unsigned int rx_dma_len
;
990 unsigned int rx_buffer_order
;
991 unsigned int rx_buffer_truesize
;
992 unsigned int rx_page_buf_step
;
993 unsigned int rx_bufs_per_page
;
994 unsigned int rx_pages_per_batch
;
995 unsigned int rx_prefix_size
;
996 int rx_packet_hash_offset
;
997 int rx_packet_len_offset
;
998 int rx_packet_ts_offset
;
1000 u32 rx_indir_table
[128];
1003 bool rx_hash_udp_4tuple
;
1005 unsigned int_error_count
;
1006 unsigned long int_error_expire
;
1008 bool irq_soft_enabled
;
1009 struct efx_buffer irq_status
;
1010 unsigned irq_zero_count
;
1012 struct delayed_work selftest_work
;
1014 #ifdef CONFIG_SFC_MTD
1015 struct list_head mtd_list
;
1019 struct efx_mcdi_data
*mcdi
;
1021 struct mutex mac_lock
;
1022 struct work_struct mac_work
;
1025 bool mc_bist_for_other_fn
;
1026 bool port_initialized
;
1027 struct net_device
*net_dev
;
1029 netdev_features_t fixed_features
;
1031 struct efx_buffer stats_buffer
;
1032 u64 rx_nodesc_drops_total
;
1033 u64 rx_nodesc_drops_while_down
;
1034 bool rx_nodesc_drops_prev_state
;
1036 unsigned int phy_type
;
1037 const struct efx_phy_operations
*phy_op
;
1039 struct mdio_if_info mdio
;
1040 unsigned int mdio_bus
;
1041 enum efx_phy_mode phy_mode
;
1043 u32 link_advertising
;
1044 struct efx_link_state link_state
;
1045 unsigned int n_link_state_changes
;
1047 bool unicast_filter
;
1048 union efx_multicast_hash multicast_hash
;
1050 unsigned fc_disable
;
1053 enum efx_loopback_mode loopback_mode
;
1056 void *loopback_selftest
;
1058 struct rw_semaphore filter_sem
;
1059 spinlock_t filter_lock
;
1061 #ifdef CONFIG_RFS_ACCEL
1062 unsigned int rps_expire_channel
;
1063 unsigned int rps_expire_index
;
1066 atomic_t active_queues
;
1067 atomic_t rxq_flush_pending
;
1068 atomic_t rxq_flush_outstanding
;
1069 wait_queue_head_t flush_wq
;
1071 #ifdef CONFIG_SFC_SRIOV
1073 unsigned vf_init_count
;
1077 struct efx_ptp_data
*ptp_data
;
1081 /* The following fields may be written more often */
1083 struct delayed_work monitor_work ____cacheline_aligned_in_smp
;
1084 spinlock_t biu_lock
;
1086 spinlock_t stats_lock
;
1087 atomic_t n_rx_noskb_drops
;
1090 static inline int efx_dev_registered(struct efx_nic
*efx
)
1092 return efx
->net_dev
->reg_state
== NETREG_REGISTERED
;
1095 static inline unsigned int efx_port_num(struct efx_nic
*efx
)
1097 return efx
->port_num
;
1100 struct efx_mtd_partition
{
1101 struct list_head node
;
1102 struct mtd_info mtd
;
1103 const char *dev_type_name
;
1104 const char *type_name
;
1105 char name
[IFNAMSIZ
+ 20];
1109 * struct efx_nic_type - Efx device type definition
1110 * @mem_bar: Get the memory BAR
1111 * @mem_map_size: Get memory BAR mapped size
1112 * @probe: Probe the controller
1113 * @remove: Free resources allocated by probe()
1114 * @init: Initialise the controller
1115 * @dimension_resources: Dimension controller resources (buffer table,
1116 * and VIs once the available interrupt resources are clear)
1117 * @fini: Shut down the controller
1118 * @monitor: Periodic function for polling link state and hardware monitor
1119 * @map_reset_reason: Map ethtool reset reason to a reset method
1120 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1121 * @reset: Reset the controller hardware and possibly the PHY. This will
1122 * be called while the controller is uninitialised.
1123 * @probe_port: Probe the MAC and PHY
1124 * @remove_port: Free resources allocated by probe_port()
1125 * @handle_global_event: Handle a "global" event (may be %NULL)
1126 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1127 * @prepare_flush: Prepare the hardware for flushing the DMA queues
1128 * (for Falcon architecture)
1129 * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1131 * @prepare_flr: Prepare for an FLR
1132 * @finish_flr: Clean up after an FLR
1133 * @describe_stats: Describe statistics for ethtool
1134 * @update_stats: Update statistics not provided by event handling.
1135 * Either argument may be %NULL.
1136 * @start_stats: Start the regular fetching of statistics
1137 * @pull_stats: Pull stats from the NIC and wait until they arrive.
1138 * @stop_stats: Stop the regular fetching of statistics
1139 * @set_id_led: Set state of identifying LED or revert to automatic function
1140 * @push_irq_moderation: Apply interrupt moderation value
1141 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1142 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1143 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1144 * to the hardware. Serialised by the mac_lock.
1145 * @check_mac_fault: Check MAC fault state. True if fault present.
1146 * @get_wol: Get WoL configuration from driver state
1147 * @set_wol: Push WoL configuration to the NIC
1148 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1149 * @test_chip: Test registers. May use efx_farch_test_registers(), and is
1150 * expected to reset the NIC.
1151 * @test_nvram: Test validity of NVRAM contents
1152 * @mcdi_request: Send an MCDI request with the given header and SDU.
1153 * The SDU length may be any value from 0 up to the protocol-
1154 * defined maximum, but its buffer will be padded to a multiple
1156 * @mcdi_poll_response: Test whether an MCDI response is available.
1157 * @mcdi_read_response: Read the MCDI response PDU. The offset will
1158 * be a multiple of 4. The length may not be, but the buffer
1159 * will be padded so it is safe to round up.
1160 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
1161 * return an appropriate error code for aborting any current
1162 * request; otherwise return 0.
1163 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1164 * be separately enabled after this.
1165 * @irq_test_generate: Generate a test IRQ
1166 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1167 * queue must be separately disabled before this.
1168 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1169 * a pointer to the &struct efx_msi_context for the channel.
1170 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1171 * is a pointer to the &struct efx_nic.
1172 * @tx_probe: Allocate resources for TX queue
1173 * @tx_init: Initialise TX queue on the NIC
1174 * @tx_remove: Free resources for TX queue
1175 * @tx_write: Write TX descriptors and doorbell
1176 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1177 * @rx_probe: Allocate resources for RX queue
1178 * @rx_init: Initialise RX queue on the NIC
1179 * @rx_remove: Free resources for RX queue
1180 * @rx_write: Write RX descriptors and doorbell
1181 * @rx_defer_refill: Generate a refill reminder event
1182 * @ev_probe: Allocate resources for event queue
1183 * @ev_init: Initialise event queue on the NIC
1184 * @ev_fini: Deinitialise event queue on the NIC
1185 * @ev_remove: Free resources for event queue
1186 * @ev_process: Process events for a queue, up to the given NAPI quota
1187 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1188 * @ev_test_generate: Generate a test event
1189 * @filter_table_probe: Probe filter capabilities and set up filter software state
1190 * @filter_table_restore: Restore filters removed from hardware
1191 * @filter_table_remove: Remove filters from hardware and tear down software state
1192 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1193 * @filter_insert: add or replace a filter
1194 * @filter_remove_safe: remove a filter by ID, carefully
1195 * @filter_get_safe: retrieve a filter by ID, carefully
1196 * @filter_clear_rx: Remove all RX filters whose priority is less than or
1197 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1198 * @filter_count_rx_used: Get the number of filters in use at a given priority
1199 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1200 * @filter_get_rx_ids: Get list of RX filters at a given priority
1201 * @filter_rfs_insert: Add or replace a filter for RFS. This must be
1202 * atomic. The hardware change may be asynchronous but should
1203 * not be delayed for long. It may fail if this can't be done
1205 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1206 * This must check whether the specified table entry is used by RFS
1207 * and that rps_may_expire_flow() returns true for it.
1208 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1209 * using efx_mtd_add()
1210 * @mtd_rename: Set an MTD partition name using the net device name
1211 * @mtd_read: Read from an MTD partition
1212 * @mtd_erase: Erase part of an MTD partition
1213 * @mtd_write: Write to an MTD partition
1214 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1215 * also notifies the driver that a writer has finished using this
1217 * @ptp_write_host_time: Send host time to MC as part of sync protocol
1218 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1219 * timestamping, possibly only temporarily for the purposes of a reset.
1220 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1221 * and tx_type will already have been validated but this operation
1222 * must validate and update rx_filter.
1223 * @set_mac_address: Set the MAC address of the device
1224 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1225 * If %NULL, then device does not support any TSO version.
1226 * @revision: Hardware architecture revision
1227 * @txd_ptr_tbl_base: TX descriptor ring base address
1228 * @rxd_ptr_tbl_base: RX descriptor ring base address
1229 * @buf_tbl_base: Buffer table base address
1230 * @evq_ptr_tbl_base: Event queue pointer table base address
1231 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1232 * @max_dma_mask: Maximum possible DMA mask
1233 * @rx_prefix_size: Size of RX prefix before packet data
1234 * @rx_hash_offset: Offset of RX flow hash within prefix
1235 * @rx_ts_offset: Offset of timestamp within prefix
1236 * @rx_buffer_padding: Size of padding at end of RX packet
1237 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1238 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1239 * @max_interrupt_mode: Highest capability interrupt mode supported
1240 * from &enum efx_init_mode.
1241 * @timer_period_max: Maximum period of interrupt timer (in ticks)
1242 * @offload_features: net_device feature flags for protocol offload
1243 * features implemented in hardware
1244 * @mcdi_max_ver: Maximum MCDI version supported
1245 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1247 struct efx_nic_type
{
1249 unsigned int mem_bar
;
1250 unsigned int (*mem_map_size
)(struct efx_nic
*efx
);
1251 int (*probe
)(struct efx_nic
*efx
);
1252 void (*remove
)(struct efx_nic
*efx
);
1253 int (*init
)(struct efx_nic
*efx
);
1254 int (*dimension_resources
)(struct efx_nic
*efx
);
1255 void (*fini
)(struct efx_nic
*efx
);
1256 void (*monitor
)(struct efx_nic
*efx
);
1257 enum reset_type (*map_reset_reason
)(enum reset_type reason
);
1258 int (*map_reset_flags
)(u32
*flags
);
1259 int (*reset
)(struct efx_nic
*efx
, enum reset_type method
);
1260 int (*probe_port
)(struct efx_nic
*efx
);
1261 void (*remove_port
)(struct efx_nic
*efx
);
1262 bool (*handle_global_event
)(struct efx_channel
*channel
, efx_qword_t
*);
1263 int (*fini_dmaq
)(struct efx_nic
*efx
);
1264 void (*prepare_flush
)(struct efx_nic
*efx
);
1265 void (*finish_flush
)(struct efx_nic
*efx
);
1266 void (*prepare_flr
)(struct efx_nic
*efx
);
1267 void (*finish_flr
)(struct efx_nic
*efx
);
1268 size_t (*describe_stats
)(struct efx_nic
*efx
, u8
*names
);
1269 size_t (*update_stats
)(struct efx_nic
*efx
, u64
*full_stats
,
1270 struct rtnl_link_stats64
*core_stats
);
1271 void (*start_stats
)(struct efx_nic
*efx
);
1272 void (*pull_stats
)(struct efx_nic
*efx
);
1273 void (*stop_stats
)(struct efx_nic
*efx
);
1274 void (*set_id_led
)(struct efx_nic
*efx
, enum efx_led_mode mode
);
1275 void (*push_irq_moderation
)(struct efx_channel
*channel
);
1276 int (*reconfigure_port
)(struct efx_nic
*efx
);
1277 void (*prepare_enable_fc_tx
)(struct efx_nic
*efx
);
1278 int (*reconfigure_mac
)(struct efx_nic
*efx
);
1279 bool (*check_mac_fault
)(struct efx_nic
*efx
);
1280 void (*get_wol
)(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
);
1281 int (*set_wol
)(struct efx_nic
*efx
, u32 type
);
1282 void (*resume_wol
)(struct efx_nic
*efx
);
1283 int (*test_chip
)(struct efx_nic
*efx
, struct efx_self_tests
*tests
);
1284 int (*test_nvram
)(struct efx_nic
*efx
);
1285 void (*mcdi_request
)(struct efx_nic
*efx
,
1286 const efx_dword_t
*hdr
, size_t hdr_len
,
1287 const efx_dword_t
*sdu
, size_t sdu_len
);
1288 bool (*mcdi_poll_response
)(struct efx_nic
*efx
);
1289 void (*mcdi_read_response
)(struct efx_nic
*efx
, efx_dword_t
*pdu
,
1290 size_t pdu_offset
, size_t pdu_len
);
1291 int (*mcdi_poll_reboot
)(struct efx_nic
*efx
);
1292 void (*mcdi_reboot_detected
)(struct efx_nic
*efx
);
1293 void (*irq_enable_master
)(struct efx_nic
*efx
);
1294 int (*irq_test_generate
)(struct efx_nic
*efx
);
1295 void (*irq_disable_non_ev
)(struct efx_nic
*efx
);
1296 irqreturn_t (*irq_handle_msi
)(int irq
, void *dev_id
);
1297 irqreturn_t (*irq_handle_legacy
)(int irq
, void *dev_id
);
1298 int (*tx_probe
)(struct efx_tx_queue
*tx_queue
);
1299 void (*tx_init
)(struct efx_tx_queue
*tx_queue
);
1300 void (*tx_remove
)(struct efx_tx_queue
*tx_queue
);
1301 void (*tx_write
)(struct efx_tx_queue
*tx_queue
);
1302 unsigned int (*tx_limit_len
)(struct efx_tx_queue
*tx_queue
,
1303 dma_addr_t dma_addr
, unsigned int len
);
1304 int (*rx_push_rss_config
)(struct efx_nic
*efx
, bool user
,
1305 const u32
*rx_indir_table
);
1306 int (*rx_probe
)(struct efx_rx_queue
*rx_queue
);
1307 void (*rx_init
)(struct efx_rx_queue
*rx_queue
);
1308 void (*rx_remove
)(struct efx_rx_queue
*rx_queue
);
1309 void (*rx_write
)(struct efx_rx_queue
*rx_queue
);
1310 void (*rx_defer_refill
)(struct efx_rx_queue
*rx_queue
);
1311 int (*ev_probe
)(struct efx_channel
*channel
);
1312 int (*ev_init
)(struct efx_channel
*channel
);
1313 void (*ev_fini
)(struct efx_channel
*channel
);
1314 void (*ev_remove
)(struct efx_channel
*channel
);
1315 int (*ev_process
)(struct efx_channel
*channel
, int quota
);
1316 void (*ev_read_ack
)(struct efx_channel
*channel
);
1317 void (*ev_test_generate
)(struct efx_channel
*channel
);
1318 int (*filter_table_probe
)(struct efx_nic
*efx
);
1319 void (*filter_table_restore
)(struct efx_nic
*efx
);
1320 void (*filter_table_remove
)(struct efx_nic
*efx
);
1321 void (*filter_update_rx_scatter
)(struct efx_nic
*efx
);
1322 s32 (*filter_insert
)(struct efx_nic
*efx
,
1323 struct efx_filter_spec
*spec
, bool replace
);
1324 int (*filter_remove_safe
)(struct efx_nic
*efx
,
1325 enum efx_filter_priority priority
,
1327 int (*filter_get_safe
)(struct efx_nic
*efx
,
1328 enum efx_filter_priority priority
,
1329 u32 filter_id
, struct efx_filter_spec
*);
1330 int (*filter_clear_rx
)(struct efx_nic
*efx
,
1331 enum efx_filter_priority priority
);
1332 u32 (*filter_count_rx_used
)(struct efx_nic
*efx
,
1333 enum efx_filter_priority priority
);
1334 u32 (*filter_get_rx_id_limit
)(struct efx_nic
*efx
);
1335 s32 (*filter_get_rx_ids
)(struct efx_nic
*efx
,
1336 enum efx_filter_priority priority
,
1337 u32
*buf
, u32 size
);
1338 #ifdef CONFIG_RFS_ACCEL
1339 s32 (*filter_rfs_insert
)(struct efx_nic
*efx
,
1340 struct efx_filter_spec
*spec
);
1341 bool (*filter_rfs_expire_one
)(struct efx_nic
*efx
, u32 flow_id
,
1342 unsigned int index
);
1344 #ifdef CONFIG_SFC_MTD
1345 int (*mtd_probe
)(struct efx_nic
*efx
);
1346 void (*mtd_rename
)(struct efx_mtd_partition
*part
);
1347 int (*mtd_read
)(struct mtd_info
*mtd
, loff_t start
, size_t len
,
1348 size_t *retlen
, u8
*buffer
);
1349 int (*mtd_erase
)(struct mtd_info
*mtd
, loff_t start
, size_t len
);
1350 int (*mtd_write
)(struct mtd_info
*mtd
, loff_t start
, size_t len
,
1351 size_t *retlen
, const u8
*buffer
);
1352 int (*mtd_sync
)(struct mtd_info
*mtd
);
1354 void (*ptp_write_host_time
)(struct efx_nic
*efx
, u32 host_time
);
1355 int (*ptp_set_ts_sync_events
)(struct efx_nic
*efx
, bool en
, bool temp
);
1356 int (*ptp_set_ts_config
)(struct efx_nic
*efx
,
1357 struct hwtstamp_config
*init
);
1358 int (*sriov_configure
)(struct efx_nic
*efx
, int num_vfs
);
1359 int (*vlan_rx_add_vid
)(struct efx_nic
*efx
, __be16 proto
, u16 vid
);
1360 int (*vlan_rx_kill_vid
)(struct efx_nic
*efx
, __be16 proto
, u16 vid
);
1361 int (*sriov_init
)(struct efx_nic
*efx
);
1362 void (*sriov_fini
)(struct efx_nic
*efx
);
1363 bool (*sriov_wanted
)(struct efx_nic
*efx
);
1364 void (*sriov_reset
)(struct efx_nic
*efx
);
1365 void (*sriov_flr
)(struct efx_nic
*efx
, unsigned vf_i
);
1366 int (*sriov_set_vf_mac
)(struct efx_nic
*efx
, int vf_i
, u8
*mac
);
1367 int (*sriov_set_vf_vlan
)(struct efx_nic
*efx
, int vf_i
, u16 vlan
,
1369 int (*sriov_set_vf_spoofchk
)(struct efx_nic
*efx
, int vf_i
,
1371 int (*sriov_get_vf_config
)(struct efx_nic
*efx
, int vf_i
,
1372 struct ifla_vf_info
*ivi
);
1373 int (*sriov_set_vf_link_state
)(struct efx_nic
*efx
, int vf_i
,
1375 int (*sriov_get_phys_port_id
)(struct efx_nic
*efx
,
1376 struct netdev_phys_item_id
*ppid
);
1377 int (*vswitching_probe
)(struct efx_nic
*efx
);
1378 int (*vswitching_restore
)(struct efx_nic
*efx
);
1379 void (*vswitching_remove
)(struct efx_nic
*efx
);
1380 int (*get_mac_address
)(struct efx_nic
*efx
, unsigned char *perm_addr
);
1381 int (*set_mac_address
)(struct efx_nic
*efx
);
1382 u32 (*tso_versions
)(struct efx_nic
*efx
);
1385 unsigned int txd_ptr_tbl_base
;
1386 unsigned int rxd_ptr_tbl_base
;
1387 unsigned int buf_tbl_base
;
1388 unsigned int evq_ptr_tbl_base
;
1389 unsigned int evq_rptr_tbl_base
;
1391 unsigned int rx_prefix_size
;
1392 unsigned int rx_hash_offset
;
1393 unsigned int rx_ts_offset
;
1394 unsigned int rx_buffer_padding
;
1395 bool can_rx_scatter
;
1396 bool always_rx_scatter
;
1397 unsigned int max_interrupt_mode
;
1398 unsigned int timer_period_max
;
1399 netdev_features_t offload_features
;
1401 unsigned int max_rx_ip_filters
;
1402 u32 hwtstamp_filters
;
1405 /**************************************************************************
1407 * Prototypes and inline functions
1409 *************************************************************************/
1411 static inline struct efx_channel
*
1412 efx_get_channel(struct efx_nic
*efx
, unsigned index
)
1414 EFX_WARN_ON_ONCE_PARANOID(index
>= efx
->n_channels
);
1415 return efx
->channel
[index
];
1418 /* Iterate over all used channels */
1419 #define efx_for_each_channel(_channel, _efx) \
1420 for (_channel = (_efx)->channel[0]; \
1422 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1423 (_efx)->channel[_channel->channel + 1] : NULL)
1425 /* Iterate over all used channels in reverse */
1426 #define efx_for_each_channel_rev(_channel, _efx) \
1427 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1429 _channel = _channel->channel ? \
1430 (_efx)->channel[_channel->channel - 1] : NULL)
1432 static inline struct efx_tx_queue
*
1433 efx_get_tx_queue(struct efx_nic
*efx
, unsigned index
, unsigned type
)
1435 EFX_WARN_ON_ONCE_PARANOID(index
>= efx
->n_tx_channels
||
1436 type
>= EFX_TXQ_TYPES
);
1437 return &efx
->channel
[efx
->tx_channel_offset
+ index
]->tx_queue
[type
];
1440 static inline bool efx_channel_has_tx_queues(struct efx_channel
*channel
)
1442 return channel
->channel
- channel
->efx
->tx_channel_offset
<
1443 channel
->efx
->n_tx_channels
;
1446 static inline struct efx_tx_queue
*
1447 efx_channel_get_tx_queue(struct efx_channel
*channel
, unsigned type
)
1449 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_tx_queues(channel
) ||
1450 type
>= EFX_TXQ_TYPES
);
1451 return &channel
->tx_queue
[type
];
1454 static inline bool efx_tx_queue_used(struct efx_tx_queue
*tx_queue
)
1456 return !(tx_queue
->efx
->net_dev
->num_tc
< 2 &&
1457 tx_queue
->queue
& EFX_TXQ_TYPE_HIGHPRI
);
1460 /* Iterate over all TX queues belonging to a channel */
1461 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1462 if (!efx_channel_has_tx_queues(_channel)) \
1465 for (_tx_queue = (_channel)->tx_queue; \
1466 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1467 efx_tx_queue_used(_tx_queue); \
1470 /* Iterate over all possible TX queues belonging to a channel */
1471 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
1472 if (!efx_channel_has_tx_queues(_channel)) \
1475 for (_tx_queue = (_channel)->tx_queue; \
1476 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
1479 static inline bool efx_channel_has_rx_queue(struct efx_channel
*channel
)
1481 return channel
->rx_queue
.core_index
>= 0;
1484 static inline struct efx_rx_queue
*
1485 efx_channel_get_rx_queue(struct efx_channel
*channel
)
1487 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel
));
1488 return &channel
->rx_queue
;
1491 /* Iterate over all RX queues belonging to a channel */
1492 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1493 if (!efx_channel_has_rx_queue(_channel)) \
1496 for (_rx_queue = &(_channel)->rx_queue; \
1500 static inline struct efx_channel
*
1501 efx_rx_queue_channel(struct efx_rx_queue
*rx_queue
)
1503 return container_of(rx_queue
, struct efx_channel
, rx_queue
);
1506 static inline int efx_rx_queue_index(struct efx_rx_queue
*rx_queue
)
1508 return efx_rx_queue_channel(rx_queue
)->channel
;
1511 /* Returns a pointer to the specified receive buffer in the RX
1514 static inline struct efx_rx_buffer
*efx_rx_buffer(struct efx_rx_queue
*rx_queue
,
1517 return &rx_queue
->buffer
[index
];
1521 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1523 * This calculates the maximum frame length that will be used for a
1524 * given MTU. The frame length will be equal to the MTU plus a
1525 * constant amount of header space and padding. This is the quantity
1526 * that the net driver will program into the MAC as the maximum frame
1529 * The 10G MAC requires 8-byte alignment on the frame
1530 * length, so we round up to the nearest 8.
1532 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1533 * XGMII cycle). If the frame length reaches the maximum value in the
1534 * same cycle, the XMAC can miss the IPG altogether. We work around
1535 * this by adding a further 16 bytes.
1537 #define EFX_FRAME_PAD 16
1538 #define EFX_MAX_FRAME_LEN(mtu) \
1539 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1541 static inline bool efx_xmit_with_hwtstamp(struct sk_buff
*skb
)
1543 return skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
;
1545 static inline void efx_xmit_hwtstamp_pending(struct sk_buff
*skb
)
1547 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
1550 /* Get all supported features.
1551 * If a feature is not fixed, it is present in hw_features.
1552 * If a feature is fixed, it does not present in hw_features, but
1553 * always in features.
1555 static inline netdev_features_t
efx_supported_features(const struct efx_nic
*efx
)
1557 const struct net_device
*net_dev
= efx
->net_dev
;
1559 return net_dev
->features
| net_dev
->hw_features
;
1562 /* Get the current TX queue insert index. */
1563 static inline unsigned int
1564 efx_tx_queue_get_insert_index(const struct efx_tx_queue
*tx_queue
)
1566 return tx_queue
->insert_count
& tx_queue
->ptr_mask
;
1569 /* Get a TX buffer. */
1570 static inline struct efx_tx_buffer
*
1571 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue
*tx_queue
)
1573 return &tx_queue
->buffer
[efx_tx_queue_get_insert_index(tx_queue
)];
1576 /* Get a TX buffer, checking it's not currently in use. */
1577 static inline struct efx_tx_buffer
*
1578 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue
*tx_queue
)
1580 struct efx_tx_buffer
*buffer
=
1581 __efx_tx_queue_get_insert_buffer(tx_queue
);
1583 EFX_WARN_ON_ONCE_PARANOID(buffer
->len
);
1584 EFX_WARN_ON_ONCE_PARANOID(buffer
->flags
);
1585 EFX_WARN_ON_ONCE_PARANOID(buffer
->unmap_len
);
1590 #endif /* EFX_NET_DRIVER_H */