drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This only implements the mac core functions for this chip.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  23 *******************************************************************************/
  24
  25 #include <linux/crc32.h>
  26 #include <linux/slab.h>
  27 #include <linux/ethtool.h>
  28 #include <asm/io.h>
  29 #include "stmmac_pcs.h"
  30 #include "dwmac1000.h"
  31
  32 static void dwmac1000_core_init(struct mac_device_info *hw, int mtu)
  33 {
  34         void __iomem *ioaddr = hw->pcsr;
  35         u32 value = readl(ioaddr + GMAC_CONTROL);
  36
  37         /* Configure GMAC core */
  38         value |= GMAC_CORE_INIT;
  39
  40         if (mtu > 1500)
  41                 value |= GMAC_CONTROL_2K;
  42         if (mtu > 2000)
  43                 value |= GMAC_CONTROL_JE;
  44
  45         if (hw->ps) {
  46                 value |= GMAC_CONTROL_TE;
  47
  48                 if (hw->ps == SPEED_1000) {
  49                         value &= ~GMAC_CONTROL_PS;
  50                 } else {
  51                         value |= GMAC_CONTROL_PS;
  52
  53                         if (hw->ps == SPEED_10)
  54                                 value &= ~GMAC_CONTROL_FES;
  55                         else
  56                                 value |= GMAC_CONTROL_FES;
  57                 }
  58         }
  59
  60         writel(value, ioaddr + GMAC_CONTROL);
  61
  62         /* Mask GMAC interrupts */
  63         value = GMAC_INT_DEFAULT_MASK;
  64
  65         if (hw->pmt)
  66                 value &= ~GMAC_INT_DISABLE_PMT;
  67         if (hw->pcs)
  68                 value &= ~GMAC_INT_DISABLE_PCS;
  69
  70         writel(value, ioaddr + GMAC_INT_MASK);
  71
  72 #ifdef STMMAC_VLAN_TAG_USED
  73         /* Tag detection without filtering */
  74         writel(0x0, ioaddr + GMAC_VLAN_TAG);
  75 #endif
  76 }
  77
  78 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
  79 {
  80         void __iomem *ioaddr = hw->pcsr;
  81         u32 value = readl(ioaddr + GMAC_CONTROL);
  82
  83         if (hw->rx_csum)
  84                 value |= GMAC_CONTROL_IPC;
  85         else
  86                 value &= ~GMAC_CONTROL_IPC;
  87
  88         writel(value, ioaddr + GMAC_CONTROL);
  89
  90         value = readl(ioaddr + GMAC_CONTROL);
  91
  92         return !!(value & GMAC_CONTROL_IPC);
  93 }
  94
  95 static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
  96 {
  97         void __iomem *ioaddr = hw->pcsr;
  98         int i;
  99
 100         for (i = 0; i < 55; i++)
 101                 reg_space[i] = readl(ioaddr + i * 4);
 102 }
 103
 104 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
 105                                     unsigned char *addr,
 106                                     unsigned int reg_n)
 107 {
 108         void __iomem *ioaddr = hw->pcsr;
 109         stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 110                             GMAC_ADDR_LOW(reg_n));
 111 }
 112
 113 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
 114                                     unsigned char *addr,
 115                                     unsigned int reg_n)
 116 {
 117         void __iomem *ioaddr = hw->pcsr;
 118         stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 119                             GMAC_ADDR_LOW(reg_n));
 120 }
 121
 122 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
 123                                  int mcbitslog2)
 124 {
 125         int numhashregs, regs;
 126
 127         switch (mcbitslog2) {
 128         case 6:
 129                 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
 130                 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
 131                 return;
 132                 break;
 133         case 7:
 134                 numhashregs = 4;
 135                 break;
 136         case 8:
 137                 numhashregs = 8;
 138                 break;
 139         default:
 140                 pr_debug("STMMAC: err in setting multicast filter\n");
 141                 return;
 142                 break;
 143         }
 144         for (regs = 0; regs < numhashregs; regs++)
 145                 writel(mcfilterbits[regs],
 146                        ioaddr + GMAC_EXTHASH_BASE + regs * 4);
 147 }
 148
 149 static void dwmac1000_set_filter(struct mac_device_info *hw,
 150                                  struct net_device *dev)
 151 {
 152         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 153         unsigned int value = 0;
 154         unsigned int perfect_addr_number = hw->unicast_filter_entries;
 155         u32 mc_filter[8];
 156         int mcbitslog2 = hw->mcast_bits_log2;
 157
 158         pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
 159                  netdev_mc_count(dev), netdev_uc_count(dev));
 160
 161         memset(mc_filter, 0, sizeof(mc_filter));
 162
 163         if (dev->flags & IFF_PROMISC) {
 164                 value = GMAC_FRAME_FILTER_PR;
 165         } else if (dev->flags & IFF_ALLMULTI) {
 166                 value = GMAC_FRAME_FILTER_PM;   /* pass all multi */
 167         } else if (!netdev_mc_empty(dev)) {
 168                 struct netdev_hw_addr *ha;
 169
 170                 /* Hash filter for multicast */
 171                 value = GMAC_FRAME_FILTER_HMC;
 172
 173                 netdev_for_each_mc_addr(ha, dev) {
 174                         /* The upper n bits of the calculated CRC are used to
 175                          * index the contents of the hash table. The number of
 176                          * bits used depends on the hardware configuration
 177                          * selected at core configuration time.
 178                          */
 179                         int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 180                                               ETH_ALEN)) >>
 181                                               (32 - mcbitslog2);
 182                         /* The most significant bit determines the register to
 183                          * use (H/L) while the other 5 bits determine the bit
 184                          * within the register.
 185                          */
 186                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
 187                 }
 188         }
 189
 190         dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
 191
 192         /* Handle multiple unicast addresses (perfect filtering) */
 193         if (netdev_uc_count(dev) > perfect_addr_number)
 194                 /* Switch to promiscuous mode if more than unicast
 195                  * addresses are requested than supported by hardware.
 196                  */
 197                 value |= GMAC_FRAME_FILTER_PR;
 198         else {
 199                 int reg = 1;
 200                 struct netdev_hw_addr *ha;
 201
 202                 netdev_for_each_uc_addr(ha, dev) {
 203                         stmmac_set_mac_addr(ioaddr, ha->addr,
 204                                             GMAC_ADDR_HIGH(reg),
 205                                             GMAC_ADDR_LOW(reg));
 206                         reg++;
 207                 }
 208         }
 209
 210 #ifdef FRAME_FILTER_DEBUG
 211         /* Enable Receive all mode (to debug filtering_fail errors) */
 212         value |= GMAC_FRAME_FILTER_RA;
 213 #endif
 214         writel(value, ioaddr + GMAC_FRAME_FILTER);
 215 }
 216
 217
 218 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 219                                 unsigned int fc, unsigned int pause_time,
 220                                 u32 tx_cnt)
 221 {
 222         void __iomem *ioaddr = hw->pcsr;
 223         /* Set flow such that DZPQ in Mac Register 6 is 0,
 224          * and unicast pause detect is enabled.
 225          */
 226         unsigned int flow = GMAC_FLOW_CTRL_UP;
 227
 228         pr_debug("GMAC Flow-Control:\n");
 229         if (fc & FLOW_RX) {
 230                 pr_debug("\tReceive Flow-Control ON\n");
 231                 flow |= GMAC_FLOW_CTRL_RFE;
 232         }
 233         if (fc & FLOW_TX) {
 234                 pr_debug("\tTransmit Flow-Control ON\n");
 235                 flow |= GMAC_FLOW_CTRL_TFE;
 236         }
 237
 238         if (duplex) {
 239                 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 240                 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
 241         }
 242
 243         writel(flow, ioaddr + GMAC_FLOW_CTRL);
 244 }
 245
 246 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
 247 {
 248         void __iomem *ioaddr = hw->pcsr;
 249         unsigned int pmt = 0;
 250
 251         if (mode & WAKE_MAGIC) {
 252                 pr_debug("GMAC: WOL Magic frame\n");
 253                 pmt |= power_down | magic_pkt_en;
 254         }
 255         if (mode & WAKE_UCAST) {
 256                 pr_debug("GMAC: WOL on global unicast\n");
 257                 pmt |= power_down | global_unicast | wake_up_frame_en;
 258         }
 259
 260         writel(pmt, ioaddr + GMAC_PMT);
 261 }
 262
 263 /* RGMII or SMII interface */
 264 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 265 {
 266         u32 status;
 267
 268         status = readl(ioaddr + GMAC_RGSMIIIS);
 269         x->irq_rgmii_n++;
 270
 271         /* Check the link status */
 272         if (status & GMAC_RGSMIIIS_LNKSTS) {
 273                 int speed_value;
 274
 275                 x->pcs_link = 1;
 276
 277                 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
 278                                GMAC_RGSMIIIS_SPEED_SHIFT);
 279                 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
 280                         x->pcs_speed = SPEED_1000;
 281                 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
 282                         x->pcs_speed = SPEED_100;
 283                 else
 284                         x->pcs_speed = SPEED_10;
 285
 286                 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
 287
 288                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 289                         x->pcs_duplex ? "Full" : "Half");
 290         } else {
 291                 x->pcs_link = 0;
 292                 pr_info("Link is Down\n");
 293         }
 294 }
 295
 296 static int dwmac1000_irq_status(struct mac_device_info *hw,
 297                                 struct stmmac_extra_stats *x)
 298 {
 299         void __iomem *ioaddr = hw->pcsr;
 300         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 301         u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
 302         int ret = 0;
 303
 304         /* Discard masked bits */
 305         intr_status &= ~intr_mask;
 306
 307         /* Not used events (e.g. MMC interrupts) are not handled. */
 308         if ((intr_status & GMAC_INT_STATUS_MMCTIS))
 309                 x->mmc_tx_irq_n++;
 310         if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
 311                 x->mmc_rx_irq_n++;
 312         if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
 313                 x->mmc_rx_csum_offload_irq_n++;
 314         if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
 315                 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
 316                 readl(ioaddr + GMAC_PMT);
 317                 x->irq_receive_pmt_irq_n++;
 318         }
 319
 320         /* MAC tx/rx EEE LPI entry/exit interrupts */
 321         if (intr_status & GMAC_INT_STATUS_LPIIS) {
 322                 /* Clean LPI interrupt by reading the Reg 12 */
 323                 ret = readl(ioaddr + LPI_CTRL_STATUS);
 324
 325                 if (ret & LPI_CTRL_STATUS_TLPIEN)
 326                         x->irq_tx_path_in_lpi_mode_n++;
 327                 if (ret & LPI_CTRL_STATUS_TLPIEX)
 328                         x->irq_tx_path_exit_lpi_mode_n++;
 329                 if (ret & LPI_CTRL_STATUS_RLPIEN)
 330                         x->irq_rx_path_in_lpi_mode_n++;
 331                 if (ret & LPI_CTRL_STATUS_RLPIEX)
 332                         x->irq_rx_path_exit_lpi_mode_n++;
 333         }
 334
 335         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 336
 337         if (intr_status & PCS_RGSMIIIS_IRQ)
 338                 dwmac1000_rgsmii(ioaddr, x);
 339
 340         return ret;
 341 }
 342
 343 static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
 344                                    bool en_tx_lpi_clockgating)
 345 {
 346         void __iomem *ioaddr = hw->pcsr;
 347         u32 value;
 348
 349         /*TODO - en_tx_lpi_clockgating treatment */
 350
 351         /* Enable the link status receive on RGMII, SGMII ore SMII
 352          * receive path and instruct the transmit to enter in LPI
 353          * state.
 354          */
 355         value = readl(ioaddr + LPI_CTRL_STATUS);
 356         value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
 357         writel(value, ioaddr + LPI_CTRL_STATUS);
 358 }
 359
 360 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
 361 {
 362         void __iomem *ioaddr = hw->pcsr;
 363         u32 value;
 364
 365         value = readl(ioaddr + LPI_CTRL_STATUS);
 366         value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
 367         writel(value, ioaddr + LPI_CTRL_STATUS);
 368 }
 369
 370 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
 371 {
 372         void __iomem *ioaddr = hw->pcsr;
 373         u32 value;
 374
 375         value = readl(ioaddr + LPI_CTRL_STATUS);
 376
 377         if (link)
 378                 value |= LPI_CTRL_STATUS_PLS;
 379         else
 380                 value &= ~LPI_CTRL_STATUS_PLS;
 381
 382         writel(value, ioaddr + LPI_CTRL_STATUS);
 383 }
 384
 385 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 386 {
 387         void __iomem *ioaddr = hw->pcsr;
 388         int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
 389
 390         /* Program the timers in the LPI timer control register:
 391          * LS: minimum time (ms) for which the link
 392          *  status from PHY should be ok before transmitting
 393          *  the LPI pattern.
 394          * TW: minimum time (us) for which the core waits
 395          *  after it has stopped transmitting the LPI pattern.
 396          */
 397         writel(value, ioaddr + LPI_TIMER_CTRL);
 398 }
 399
 400 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 401                                bool loopback)
 402 {
 403         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 404 }
 405
 406 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
 407 {
 408         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 409 }
 410
 411 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 412 {
 413         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 414 }
 415
 416 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 417                             u32 rx_queues, u32 tx_queues)
 418 {
 419         u32 value = readl(ioaddr + GMAC_DEBUG);
 420
 421         if (value & GMAC_DEBUG_TXSTSFSTS)
 422                 x->mtl_tx_status_fifo_full++;
 423         if (value & GMAC_DEBUG_TXFSTS)
 424                 x->mtl_tx_fifo_not_empty++;
 425         if (value & GMAC_DEBUG_TWCSTS)
 426                 x->mmtl_fifo_ctrl++;
 427         if (value & GMAC_DEBUG_TRCSTS_MASK) {
 428                 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
 429                              >> GMAC_DEBUG_TRCSTS_SHIFT;
 430                 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
 431                         x->mtl_tx_fifo_read_ctrl_write++;
 432                 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
 433                         x->mtl_tx_fifo_read_ctrl_wait++;
 434                 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
 435                         x->mtl_tx_fifo_read_ctrl_read++;
 436                 else
 437                         x->mtl_tx_fifo_read_ctrl_idle++;
 438         }
 439         if (value & GMAC_DEBUG_TXPAUSED)
 440                 x->mac_tx_in_pause++;
 441         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 442                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 443                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 444
 445                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 446                         x->mac_tx_frame_ctrl_xfer++;
 447                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 448                         x->mac_tx_frame_ctrl_pause++;
 449                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 450                         x->mac_tx_frame_ctrl_wait++;
 451                 else
 452                         x->mac_tx_frame_ctrl_idle++;
 453         }
 454         if (value & GMAC_DEBUG_TPESTS)
 455                 x->mac_gmii_tx_proto_engine++;
 456         if (value & GMAC_DEBUG_RXFSTS_MASK) {
 457                 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
 458                              >> GMAC_DEBUG_RRCSTS_SHIFT;
 459
 460                 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
 461                         x->mtl_rx_fifo_fill_level_full++;
 462                 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
 463                         x->mtl_rx_fifo_fill_above_thresh++;
 464                 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
 465                         x->mtl_rx_fifo_fill_below_thresh++;
 466                 else
 467                         x->mtl_rx_fifo_fill_level_empty++;
 468         }
 469         if (value & GMAC_DEBUG_RRCSTS_MASK) {
 470                 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
 471                              GMAC_DEBUG_RRCSTS_SHIFT;
 472
 473                 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
 474                         x->mtl_rx_fifo_read_ctrl_flush++;
 475                 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
 476                         x->mtl_rx_fifo_read_ctrl_read_data++;
 477                 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
 478                         x->mtl_rx_fifo_read_ctrl_status++;
 479                 else
 480                         x->mtl_rx_fifo_read_ctrl_idle++;
 481         }
 482         if (value & GMAC_DEBUG_RWCSTS)
 483                 x->mtl_rx_fifo_ctrl_active++;
 484         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 485                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 486                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 487         if (value & GMAC_DEBUG_RPESTS)
 488                 x->mac_gmii_rx_proto_engine++;
 489 }
 490
 491 static const struct stmmac_ops dwmac1000_ops = {
 492         .core_init = dwmac1000_core_init,
 493         .rx_ipc = dwmac1000_rx_ipc_enable,
 494         .dump_regs = dwmac1000_dump_regs,
 495         .host_irq_status = dwmac1000_irq_status,
 496         .set_filter = dwmac1000_set_filter,
 497         .flow_ctrl = dwmac1000_flow_ctrl,
 498         .pmt = dwmac1000_pmt,
 499         .set_umac_addr = dwmac1000_set_umac_addr,
 500         .get_umac_addr = dwmac1000_get_umac_addr,
 501         .set_eee_mode = dwmac1000_set_eee_mode,
 502         .reset_eee_mode = dwmac1000_reset_eee_mode,
 503         .set_eee_timer = dwmac1000_set_eee_timer,
 504         .set_eee_pls = dwmac1000_set_eee_pls,
 505         .debug = dwmac1000_debug,
 506         .pcs_ctrl_ane = dwmac1000_ctrl_ane,
 507         .pcs_rane = dwmac1000_rane,
 508         .pcs_get_adv_lp = dwmac1000_get_adv_lp,
 509 };
 510
 511 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
 512                                         int perfect_uc_entries,
 513                                         int *synopsys_id)
 514 {
 515         struct mac_device_info *mac;
 516         u32 hwid = readl(ioaddr + GMAC_VERSION);
 517
 518         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 519         if (!mac)
 520                 return NULL;
 521
 522         mac->pcsr = ioaddr;
 523         mac->multicast_filter_bins = mcbins;
 524         mac->unicast_filter_entries = perfect_uc_entries;
 525         mac->mcast_bits_log2 = 0;
 526
 527         if (mac->multicast_filter_bins)
 528                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 529
 530         mac->mac = &dwmac1000_ops;
 531         mac->dma = &dwmac1000_dma_ops;
 532
 533         mac->link.port = GMAC_CONTROL_PS;
 534         mac->link.duplex = GMAC_CONTROL_DM;
 535         mac->link.speed = GMAC_CONTROL_FES;
 536         mac->mii.addr = GMAC_MII_ADDR;
 537         mac->mii.data = GMAC_MII_DATA;
 538         mac->mii.addr_shift = 11;
 539         mac->mii.addr_mask = 0x0000F800;
 540         mac->mii.reg_shift = 6;
 541         mac->mii.reg_mask = 0x000007C0;
 542         mac->mii.clk_csr_shift = 2;
 543         mac->mii.clk_csr_mask = GENMASK(5, 2);
 544
 545         /* Get and dump the chip ID */
 546         *synopsys_id = stmmac_get_synopsys_id(hwid);
 547
 548         return mac;
 549 }